leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update SVR numbers to expand support

Browse Source 
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming
2008-02-06 01:19:40 -06:00
committed by Andrew Fleming-AFLEMING
parent b83eef440c
commit 1ced121600
3 changed files with 81 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
cpu/mpc85xx/cpu.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright 2004,2007 Freescale Semiconductor, Inc.
* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -30,6 +30,39 @@
#include <command.h>
#include <asm/cache.h>
struct cpu_type {
char name[15];
u32 soc_ver;
};
#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533),
CPU_TYPE_ENTRY(8533_E),
CPU_TYPE_ENTRY(8540),
CPU_TYPE_ENTRY(8541),
CPU_TYPE_ENTRY(8541_E),
CPU_TYPE_ENTRY(8543),
CPU_TYPE_ENTRY(8543_E),
CPU_TYPE_ENTRY(8544),
CPU_TYPE_ENTRY(8544_E),
CPU_TYPE_ENTRY(8545),
CPU_TYPE_ENTRY(8545_E),
CPU_TYPE_ENTRY(8547_E),
CPU_TYPE_ENTRY(8548),
CPU_TYPE_ENTRY(8548_E),
CPU_TYPE_ENTRY(8555),
CPU_TYPE_ENTRY(8555_E),
CPU_TYPE_ENTRY(8560),
CPU_TYPE_ENTRY(8567),
CPU_TYPE_ENTRY(8567_E),
CPU_TYPE_ENTRY(8568),
CPU_TYPE_ENTRY(8568_E),
CPU_TYPE_ENTRY(8572),
CPU_TYPE_ENTRY(8572_E),
};
int checkcpu (void)
{
sys_info_t sysinfo;
@@ -39,47 +72,26 @@ int checkcpu (void)
uint fam;
uint ver;
uint major, minor;
int i;
u32 ddr_ratio;
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
svr = get_svr();
ver = SVR_VER(svr);
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
puts("CPU: ");
switch (ver) {
case SVR_8540:
puts("8540");
break;
case SVR_8541:
puts("8541");
break;
case SVR_8555:
puts("8555");
break;
case SVR_8560:
puts("8560");
break;
case SVR_8548:
puts("8548");
break;
case SVR_8548_E:
puts("8548_E");
break;
case SVR_8544:
puts("8544");
break;
case SVR_8544_E:
puts("8544_E");
break;
case SVR_8568_E:
puts("8568_E");
break;
default:
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if (cpu_type_list[i].soc_ver == ver) {
puts(cpu_type_list[i].name);
break;
}
if (i == ARRAY_SIZE(cpu_type_list))
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
pvr = get_pvr();
@@ -142,10 +154,9 @@ int checkcpu (void)
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
if (ver == SVR_8560) {
printf("CPM: %lu Mhz\n",
sysinfo.freqSystemBus / 1000000);
}
#ifdef CONFIG_CPM2
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");

2
cpu/mpc86xx/cpu.c
View File

@@ -69,7 +69,7 @@ checkcpu(void)
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
svr = get_svr();
ver = SVR_VER(svr);
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);