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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

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This commit is contained in:
Tom Rini
2019-04-26 13:49:58 -04:00
parent 7d99406742 bf068c7643
commit 1c64692df2
36 changed files with 104 additions and 288 deletions
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6
include/configs/socfpga_arria10_socdk.h
View File

@@ -19,12 +19,6 @@
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000
/* Ethernet on SoC (EMAC) */
/*
* U-Boot environment configurations
*/
/*
* Serial / UART configurations
*/

2
include/configs/socfpga_arria5_socdk.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

116
include/configs/socfpga_common.h
View File

@@ -10,8 +10,6 @@
*/
#define CONFIG_CLOCKS
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
@@ -26,7 +24,13 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
#endif
#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
@@ -38,12 +42,23 @@
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_SPL_STACK \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
* in U-Boot pre-reloc is higher than in SPL.
*/
#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
@@ -55,29 +70,12 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
#endif
/*
* Cache
*/
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* EPCS/EPCQx1 Serial Flash Controller
*/
#ifdef CONFIG_ALTERA_SPI
/*
* The base address is configurable in QSys, each board must specify the
* base address based on it's particular FPGA configuration. Please note
* that the address here is incremented by 0x400 from the Base address
* selected in QSys, since the SPI registers are at offset +0x400.
* #define CONFIG_SYS_SPI_BASE 0xff240400
*/
#endif
/*
* Ethernet on SoC (EMAC)
*/
@@ -132,32 +130,6 @@
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*
* I2C support
*/
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SPEED1 100000
#define CONFIG_SYS_I2C_SPEED2 100000
#define CONFIG_SYS_I2C_SPEED3 100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_SYS_I2C_SLAVE1 0x02
#define CONFIG_SYS_I2C_SLAVE2 0x02
#define CONFIG_SYS_I2C_SLAVE3 0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
#endif
#endif /* CONFIG_DM_I2C */
/*
* QSPI support
*/
@@ -171,15 +143,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
#endif
/*
* Designware SPI support
*/
/*
* Serial Driver
*/
#define CONFIG_SYS_NS16550_SERIAL
/*
* USB
*/
@@ -215,20 +178,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#endif
/*
* mtd partitioning for serial NOR flash
*
* device nor0 <ff705000.spi.0>, # parts = 6
* #: name size offset mask_flags
* 0: u-boot 0x00100000 0x00000000 0
* 1: env1 0x00040000 0x00100000 0
* 2: env2 0x00040000 0x00140000 0
* 3: UBI 0x03e80000 0x00180000 0
* 4: boot 0x00e80000 0x00180000 0
* 5: rootfs 0x01000000 0x01000000 0
*
*/
/*
* SPL
*
@@ -236,9 +185,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*
* 0xFFFF_0000 ...... Start of SRAM
* 0xFFFF_xxxx ...... Top of stack (grows down)
* 0xFFFF_yyyy ...... Malloc area
* 0xFFFF_zzzz ...... Global Data
* 0xFFFF_FF00 ...... End of SRAM
* 0xFFFF_yyyy ...... Global Data
* 0xFFFF_zzzz ...... Malloc area
* 0xFFFF_FFFF ...... End of SRAM
*
* SRAM Memory layout for Arria 10:
* 0xFFE0_0000 ...... Start of SRAM (bottom)
@@ -252,16 +201,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#endif
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_START
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE + \
CONFIG_SYS_INIT_RAM_ADDR)
#endif
#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
@@ -292,15 +231,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#endif
/*
* Stack setup
*/
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
#endif
/* Extra Environment */
#ifndef CONFIG_SPL_BUILD

2
include/configs/socfpga_cyclone5_socdk.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

2
include/configs/socfpga_de0_nano_soc.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

2
include/configs/socfpga_de10_nano.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

2
include/configs/socfpga_de1_soc.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

2
include/configs/socfpga_is1.h
View File

@@ -19,8 +19,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_ARP_TIMEOUT 500UL
/* PHY */
#endif
/* The rest of the configuration is shared */

2
include/configs/socfpga_sockit.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

2
include/configs/socfpga_socrates.h
View File

@@ -14,8 +14,6 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

11
include/configs/socfpga_sr1500.h
View File

@@ -19,8 +19,6 @@
/* The PHY is autodetected, so no MII PHY address is needed here */
#define PHY_ANEG_TIMEOUT 8000
/* Environment */
/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET
@@ -36,15 +34,6 @@
#define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
/*
* The QSPI NOR flash layout on SR1500:
*
* 0000.0000 - 0003.ffff: SPL (4 times)
* 0004.0000 - 000d.ffff: U-Boot
* 000e.0000 - 000e.ffff: env1
* 000f.0000 - 000f.ffff: env2
*/
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

18
include/configs/socfpga_vining_fpga.h
View File

@@ -16,27 +16,9 @@
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* I2C EEPROM */
#ifdef CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
#endif
/*
* Status LEDs:
* 0 ... Top Green
* 1 ... Top Red
* 2 ... Bottom Green
* 3 ... Bottom Red
*/
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_BOOTP_SEND_HOSTNAME
/* PHY */
#endif
/* Extra Environment */