diff --git a/.travis.yml b/.travis.yml index 6ce2ef7fba..321fd793a7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -42,12 +42,12 @@ install: - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` # prepare buildman environment - echo -e "[toolchain]\nroot = /usr" > ~/.buildman - - echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman + - echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman - echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman - cat ~/.buildman - virtualenv /tmp/venv - . /tmp/venv/bin/activate - - pip install pytest + - pip install pytest==2.8.7 - pip install python-subunit - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd @@ -75,8 +75,8 @@ before_script: echo -e "\n[toolchain-alias]\nx86 = i386" >> ~/.buildman; fi - if [[ "${TOOLCHAIN}" == arc ]]; then - wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz && - tar -C /tmp -xf arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz; + wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz && + tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz; fi - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz && @@ -332,6 +332,14 @@ matrix: - name: "sloccount" script: - sloccount . + # ensure all configs have MAINTAINERS entries + - name: "Check for configs without MAINTAINERS entry" + script: + - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi + # Ensure host tools build + - name: "Build tools-only" + script: + - make tools-only_config tools-only -j$(nproc) # test/py - name: "test/py sandbox" diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt new file mode 100644 index 0000000000..acd466fdc6 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CON devices + +The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocon_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocon_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt new file mode 100644 index 0000000000..819db22bf7 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt @@ -0,0 +1,19 @@ +gdsys IHS FPGA for CPU devices + +The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides +support for enabling and starting the FPGA, as well as verifying working bus +communication. + +Required properties: +- compatible: must be "gdsys,iocpu_fpga" +- reset-gpios: List of GPIOs controlling the FPGA's reset +- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is + done + +Example: + +FPGA0 { + compatible = "gdsys,iocpu_fpga"; + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/Documentation/devicetree/bindings/misc/gdsys,soc.txt new file mode 100644 index 0000000000..278e935b16 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/gdsys,soc.txt @@ -0,0 +1,16 @@ +gdsys soc bus driver + +This driver provides a simple interface for the busses associated with gdsys +IHS FPGAs. The bus itself contains devices whose register maps are contained +within the FPGA's register space. + +Required properties: +- fpga: A phandle to the controlling IHS FPGA + +Example: + +FPGA0BUS: fpga0bus { + compatible = "gdsys,soc"; + ranges = <0x0 0xe0600000 0x00004000>; + fpga = <&FPGA0>; +}; diff --git a/Kconfig b/Kconfig index dca9bb4e43..aff7b2e00a 100644 --- a/Kconfig +++ b/Kconfig @@ -86,6 +86,7 @@ config DISTRO_DEFAULTS select SUPPORT_RAW_INITRD select SYS_LONGHELP imply CMD_MII if NET + imply USB_STORAGE imply USE_BOOTCOMMAND help Select this to enable various options and commands which are suitable @@ -125,6 +126,7 @@ config SYS_BOOT_GET_KBD config SYS_MALLOC_F bool "Enable malloc() pool before relocation" default y if DM + help Before relocation, memory is very limited on many platforms. Still, we can provide a small malloc() pool if needed. Driver model in @@ -135,6 +137,7 @@ config SYS_MALLOC_F_LEN hex "Size of malloc() pool before relocation" depends on SYS_MALLOC_F default 0x1000 if AM33XX + default 0x2800 if SANDBOX default 0x400 help Before relocation, memory is very limited on many platforms. Still, @@ -248,6 +251,16 @@ config FIT if FIT +config FIT_EXTERNAL_OFFSET + hex "Text Base" + default 0x0 + help + This specifies a data offset in fit image. + The offset is from data payload offset to the beginning of + fit image header. When specifies a offset, specific data + could be put in the hole between data payload and fit image + header, such as CSF data on i.MX platform. + config FIT_ENABLE_SHA256_SUPPORT bool "Support SHA256 checksum of FIT image contents" default y @@ -290,6 +303,14 @@ config FIT_SIGNATURE_MAX_SIZE device memory. Assure this size does not extend past expected storage space. +config FIT_ENABLE_RSASSA_PSS_SUPPORT + bool "Support rsassa-pss signature scheme of FIT image contents" + depends on FIT_SIGNATURE + default n + help + Enable this to support the pss padding algorithm as described + in the rfc8017 (https://tools.ietf.org/html/rfc8017). + config FIT_VERBOSE bool "Show verbose messages when FIT images fail" help diff --git a/MAINTAINERS b/MAINTAINERS index abdb6dcdb5..ae825014bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2,6 +2,8 @@ Descriptions of section entries: P: Person (obsolete) M: Mail patches to: FullName + R: Designated reviewer: FullName + These reviewers should be CCed on patches. L: Mailing list that is relevant to this area W: Web-page with status/info Q: Patchwork web based patch tracking system site @@ -158,6 +160,26 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM MEDIATEK +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: arch/arm/mach-mediatek/ +F: arch/arm/include/asm/arch-mediatek/ +F: board/mediatek/ +F: doc/README.mediatek +F: drivers/clk/mediatek/ +F: drivers/mmc/mtk-sd.c +F: drivers/pinctrl/mediatek/ +F: drivers/power/domain/mtk-power-domain.c +F: drivers/ram/mediatek/ +F: drivers/spi/mtk_qspi.c +F: drivers/timer/mtk_timer.c +F: drivers/watchdog/mtk_wdt.c +F: tools/mtk_image.c +F: tools/mtk_image.h +N: mediatek + ARM OWL M: Manivannan Sadhasivam S: Maintained @@ -358,6 +380,11 @@ S: Maintained T: git git://git.denx.de/u-boot-microblaze.git F: arch/arm/mach-zynqmp-r5/ +BINMAN +M: Simon Glass +S: Maintained +F: tools/binman/ + BUILDMAN M: Simon Glass S: Maintained @@ -394,6 +421,7 @@ F: test/dm/ EFI PAYLOAD M: Alexander Graf +R: Heinrich Schuchardt S: Maintained T: git git://github.com/agraf/u-boot.git F: doc/README.uefi @@ -484,6 +512,24 @@ S: Maintained T: git git://git.denx.de/u-boot-mips.git F: arch/mips/ +MIPS MSCC +M: Gregory CLEMENT +M: Lars Povlsen +M: Horatiu Vultur +S: Maintained +F: arch/mips/mach-mscc/ +F: arch/mips/dts/luton* +F: arch/mips/dts/mscc* +F: arch/mips/dts/ocelot* +F: board/mscc/ +F: configs/mscc* +F: include/configs/vcoreiii.h + +MIPS JZ4780 +M: Ezequiel Garcia +S: Maintained +F: arch/mips/mach-jz47xx/ + MMC M: Jaehoon Chung S: Maintained @@ -691,5 +737,6 @@ L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained T: git git://git.denx.de/u-boot.git +F: configs/tools-only_defconfig F: * F: */ diff --git a/Makefile b/Makefile index 552687db53..eeb299fc38 100755 --- a/Makefile +++ b/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -VERSION = 2018 -PATCHLEVEL = 11 +VERSION = 2019 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -443,7 +443,7 @@ defaultenv_h := include/generated/defaultenv_autogenerated.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ - ubootversion backup tests + ubootversion backup tests check qcheck config-targets := 0 mixed-targets := 0 @@ -695,7 +695,6 @@ libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/ libs-y += drivers/mtd/spi/ libs-y += drivers/net/ libs-y += drivers/net/phy/ -libs-y += drivers/pci/ libs-y += drivers/power/ \ drivers/power/domain/ \ drivers/power/fuel_gauge/ \ @@ -725,8 +724,7 @@ libs-y += common/ libs-y += env/ libs-$(CONFIG_API) += api/ libs-$(CONFIG_HAS_POST) += post/ -libs-y += test/ -libs-y += test/dm/ +libs-$(CONFIG_UNIT_TEST) += test/ test/dm/ libs-$(CONFIG_UT_ENV) += test/env/ libs-$(CONFIG_UT_OVERLAY) += test/overlay/ @@ -852,6 +850,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin endif +ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin + # Add optional build target if defined in board/cpu/soc headers ifneq ($(CONFIG_BUILD_TARGET),) ALL-y += $(CONFIG_BUILD_TARGET:"%"=%) @@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_mkfitimage = MKIMAGE $@ -cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ +cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_cat = CAT $@ @@ -912,11 +912,68 @@ cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \ all: $(ALL-y) cfg ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y) - @echo "===================== WARNING ======================" - @echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove" - @echo "(possibly in a subsequent patch in your series)" - @echo "before sending patches to the mailing list." - @echo "====================================================" + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove" + @echo >&2 "(possibly in a subsequent patch in your series)" + @echo >&2 "before sending patches to the mailing list." + @echo >&2 "====================================================" +endif +ifeq ($(CONFIG_MMC),y) +ifneq ($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board does not use CONFIG_DM_MMC. Please update" + @echo >&2 "the board to use CONFIG_DM_MMC before the v2019.04 release." + @echo >&2 "Failure to update by the deadline may result in board removal." + @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." + @echo >&2 "====================================================" +endif +endif +ifeq ($(CONFIG_USB),y) +ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board does not use CONFIG_DM_USB. Please update" + @echo >&2 "the board to use CONFIG_DM_USB before the v2019.07 release." + @echo >&2 "Failure to update by the deadline may result in board removal." + @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." + @echo >&2 "====================================================" +endif +endif +ifeq ($(CONFIG_LIBATA)$(CONFIG_DM_SCSI)$(CONFIG_MVSATA_IDE),y) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board does not use CONFIG_DM_SCSI. Please update" + @echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release." + @echo >&2 "Failure to update by the deadline may result in board removal." + @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." + @echo >&2 "====================================================" +endif +ifeq ($(CONFIG_OF_EMBED),y) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "CONFIG_OF_EMBED is enabled. This option should only" + @echo >&2 "be used for debugging purposes. Please use" + @echo >&2 "CONFIG_OF_SEPARATE for boards in mainline." + @echo >&2 "See doc/README.fdt-control for more info." + @echo >&2 "====================================================" +endif +ifeq ($(CONFIG_SPI),y) +ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board does not use CONFIG_DM_SPI. Please update" + @echo >&2 "the board before v2019.04 for no dm conversion" + @echo >&2 "and v2019.07 for partially dm converted drivers." + @echo >&2 "Failure to update can lead to driver/board removal" + @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." + @echo >&2 "====================================================" +endif +endif +ifeq ($(CONFIG_SPI_FLASH),y) +ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy) + @echo >&2 "===================== WARNING ======================" + @echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update" + @echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release." + @echo >&2 "Failure to update by the deadline may result in board removal." + @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." + @echo >&2 "====================================================" +endif endif @# Check that this build does not use CONFIG options that we do not @# know about unless they are in Kconfig. All the existing CONFIG @@ -1048,9 +1105,11 @@ u-boot.ldr: u-boot # binman # --------------------------------------------------------------------------- +# Use 'make BINMAN_DEBUG=1' to enable debugging quiet_cmd_binman = BINMAN $@ -cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \ - -I . -I $(srctree)/board/$(BOARDDIR) $< +cmd_binman = $(srctree)/tools/binman/binman -u -d u-boot.dtb -O . -m \ + -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ + $(if $(BINMAN_DEBUG),-D) $(BINMAN_$(@F)) $< OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex @@ -1169,6 +1228,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +ifeq ($(CONFIG_ARCH_IMX8M), y) +flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +endif + u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ @@ -1359,6 +1423,26 @@ u-boot.elf: u-boot.bin $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o $(call if_changed,u-boot-elf) +# MediaTek's ARM-based u-boot needs a header to contains its load address +# which is parsed by the BootROM. +# If the SPL build is enabled, the header will be added to the spl binary, +# and the spl binary and the u-boot.img will be combined into one file. +# Otherwise the header will be added to the u-boot.bin directly. + +ifeq ($(CONFIG_SPL),y) +spl/u-boot-spl-mtk.bin: spl/u-boot-spl + +u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE + $(call if_changed,binman) +else +MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \ + -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))" + +u-boot-mtk.bin: u-boot.bin FORCE + $(call if_changed,mkimage) +endif + ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink) # Rule to link u-boot @@ -1703,6 +1787,7 @@ help: @echo 'Test targets:' @echo '' @echo ' check - Run all automated tests that use sandbox' + @echo ' qcheck - Run quick automated tests that use sandbox' @echo '' @echo 'Other generic targets:' @echo ' all - Build all necessary images depending on configuration' @@ -1745,6 +1830,9 @@ help: tests check: $(srctree)/test/run +qcheck: + $(srctree)/test/run quick + # Documentation targets # --------------------------------------------------------------------------- DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \ diff --git a/README b/README index a46c7c63a4..17d56b8034 100644 --- a/README +++ b/README @@ -1932,14 +1932,6 @@ The following options need to be configured: SPI configuration items (port pins to use, etc). For an example, see include/configs/sacsng.h. - CONFIG_HARD_SPI - - Enables a hardware SPI driver for general-purpose reads - and writes. As with CONFIG_SOFT_SPI, the board configuration - must define a list of chip-select function pointers. - Currently supported on some MPC8xxx processors. For an - example, see include/configs/mpc8349emds.h. - CONFIG_SYS_SPI_MXC_WAIT Timeout for waiting until spi transfer completed. default: (CONFIG_SYS_HZ/100) /* 10 ms */ diff --git a/api/api_storage.c b/api/api_storage.c index 8aeeda2715..2b90c18aae 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -99,6 +99,7 @@ static int dev_stor_get(int type, int *more, struct device_info *di) { struct blk_desc *dd; int found = 0; + int found_last = 0; int i = 0; /* Wasn't configured for this type, return 0 directly */ @@ -111,9 +112,13 @@ static int dev_stor_get(int type, int *more, struct device_info *di) if (di->cookie == (void *)blk_get_dev(specs[type].name, i)) { i += 1; + found_last = 1; break; } } + + if (!found_last) + i = 0; } for (; i < specs[type].max_dev; i++) { diff --git a/arch/Kconfig b/arch/Kconfig index 1f2f407d64..35e2712fce 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -91,6 +91,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL imply BITREVERSE + select BLOBLIST imply CMD_DM imply CMD_GETTIME imply CMD_HASH @@ -110,6 +111,12 @@ config SANDBOX imply LIBAVB imply CMD_AVB imply UDP_FUNCTION_FASTBOOT + imply VIRTIO_MMIO + imply VIRTIO_PCI + imply VIRTIO_SANDBOX + imply VIRTIO_BLK + imply VIRTIO_NET + imply DM_SOUND config SH bool "SuperH architecture" @@ -120,6 +127,7 @@ config X86 select CREATE_ARCH_SYMLINK select DM select DM_PCI + select HAVE_ARCH_IOMAP select HAVE_PRIVATE_LIBGCC select OF_CONTROL select PCI diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 9920d2e719..fff6591c68 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -16,6 +16,20 @@ * access: "lr"/"sr". */ +/* + * Typically 8 least significant bits of Build Configuration Register (BCR) + * describe version of the HW block in question. Moreover if decoded version + * is 0 this means given HW block is absent - this is especially useful because + * we may safely read BRC regardless HW block existence while an attempt to + * access any other AUX regs associated with this HW block lead to imediate + * "instruction error" exception. + * + * I.e. before using any cofigurable HW block it's required to make sure it + * exists at all, and for that we introduce a special macro below. + */ +#define ARC_BCR_VERSION_MASK GENMASK(7, 0) +#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) + #define ARC_AUX_IDENTITY 0x04 #define ARC_AUX_STATUS32 0x0a @@ -73,7 +87,7 @@ #define ARC_BCR_CLUSTER 0xcf /* MMU Management regs */ -#define ARC_AUX_MMU_BCR 0x06f +#define ARC_AUX_MMU_BCR 0x6f /* IO coherency related auxiliary registers */ #define ARC_AUX_IO_COH_ENABLE 0x500 @@ -81,6 +95,15 @@ #define ARC_AUX_IO_COH_AP0_BASE 0x508 #define ARC_AUX_IO_COH_AP0_SIZE 0x509 +/* XY-memory related */ +#define ARC_AUX_XY_BUILD 0x79 + +/* DSP-extensions related auxiliary registers */ +#define ARC_AUX_DSP_BUILD 0x7A + +/* ARC Subsystems related auxiliary registers */ +#define ARC_AUX_SUBSYS_BUILD 0xF0 + #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ #define read_aux_reg(reg) __builtin_arc_lr(reg) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index a969a16722..07daaa8d15 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -35,34 +36,193 @@ int dram_init(void) } #ifdef CONFIG_DISPLAY_CPUINFO -const char *decode_identity(void) +const char *arc_700_version(int arcver, char *name, int name_len) { - int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; + const char *arc_ver; switch (arcver) { - /* ARCompact cores */ - case 0x32: return "ARC 700 v4.4-4.5"; - case 0x33: return "ARC 700 v4.6-v4.9"; - case 0x34: return "ARC 700 v4.10"; - case 0x35: return "ARC 700 v4.11"; - - /* ARCv2 cores */ - case 0x41: return "ARC EM v1.1a"; - case 0x42: return "ARC EM v3.0"; - case 0x43: return "ARC EM v4.0"; - case 0x50: return "ARC HS v1.0"; - case 0x51: return "ARC EM v2.0"; - case 0x52: return "ARC EM v2.1"; - case 0x53: return "ARC HS v3.0"; - case 0x54: return "ARC HS v4.0"; - - default: return "Unknown ARC core"; + case 0x32: + arc_ver = "v4.4-4.5"; + break; + case 0x33: + arc_ver = "v4.6-v4.9"; + break; + case 0x34: + arc_ver = "v4.10"; + break; + case 0x35: + arc_ver = "v4.11"; + break; + default: + arc_ver = "unknown version"; } + + snprintf(name, name_len, "ARC 700 %s", arc_ver); + + return name; +} + +struct em_template_t { + const bool cache; + const bool dsp; + const bool xymem; + const char name[8]; +}; + +static const struct em_template_t em_versions[] = { + {false, false, false, "EM4"}, + {true, false, false, "EM6"}, + {false, true, false, "EM5D"}, + {true, true, false, "EM7D"}, + {false, true, true, "EM9D"}, + {true, true, true, "EM11D"}, +}; + +const char *arc_em_version(int arcver, char *name, int name_len) +{ + const char *arc_name = "EM"; + const char *arc_ver; + bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); + bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD); + bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD); + int i; + + for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) { + if (em_versions[i].cache == cache && + em_versions[i].dsp == dsp && + em_versions[i].xymem == xymem) { + arc_name = em_versions[i].name; + break; + } + } + + switch (arcver) { + case 0x41: + arc_ver = "v1.1a"; + break; + case 0x42: + arc_ver = "v3.0"; + break; + case 0x43: + arc_ver = "v4.0"; + break; + case 0x44: + arc_ver = "v5.0"; + break; + default: + arc_ver = "unknown version"; + } + + snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver); + + return name; +} + +struct hs_template_t { + const bool cache; + const bool mmu; + const bool dual_issue; + const bool dsp; + const char name[8]; +}; + +static const struct hs_template_t hs_versions[] = { + {false, false, false, false, "HS34"}, + {true, false, false, false, "HS36"}, + {true, true, false, false, "HS38"}, + {false, false, true, false, "HS44"}, + {true, false, true, false, "HS46"}, + {true, true, true, false, "HS48"}, + {false, false, true, true, "HS45D"}, + {true, false, true, true, "HS47D"}, +}; + +const char *arc_hs_version(int arcver, char *name, int name_len) +{ + const char *arc_name = "HS"; + const char *arc_ver; + bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); + bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD); + bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR); + bool dual_issue = arcver == 0x54 ? true : false; + int i; + + for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) { + if (hs_versions[i].cache == cache && + hs_versions[i].mmu == mmu && + hs_versions[i].dual_issue == dual_issue && + hs_versions[i].dsp == dsp) { + arc_name = hs_versions[i].name; + break; + } + } + + switch (arcver) { + case 0x50: + arc_ver = "v1.0"; + break; + case 0x51: + arc_ver = "v2.0"; + break; + case 0x52: + arc_ver = "v2.1c"; + break; + case 0x53: + arc_ver = "v3.0"; + break; + case 0x54: + arc_ver = "v4.0"; + break; + default: + arc_ver = "unknown version"; + } + + snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver); + + return name; +} + +const char *decode_identity(void) +{ +#define MAX_CPU_NAME_LEN 64 + + int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; + char *name = malloc(MAX_CPU_NAME_LEN); + + if (arcver >= 0x50) + return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN); + else if (arcver >= 0x40) + return arc_em_version(arcver, name, MAX_CPU_NAME_LEN); + else if (arcver >= 0x30) + return arc_700_version(arcver, name, MAX_CPU_NAME_LEN); + else + return "Unknown ARC core"; +} + +const char *decode_subsystem(void) +{ + int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0); + + switch (subsys_type) { + case 0: return NULL; + case 2: return "ARC Sensor & Control IP Subsystem"; + case 3: return "ARC Data Fusion IP Subsystem"; + case 4: return "ARC Secure Subsystem"; + default: return "Unknown subsystem"; + }; } __weak int print_cpuinfo(void) { - printf("CPU: %s\n", decode_identity()); + const char *subsys_name = decode_subsystem(); + char mhz[8]; + + printf("CPU: %s at %s MHz\n", decode_identity(), + strmhz(mhz, gd->cpu_clk)); + + if (subsys_name) + printf("Subsys:%s\n", subsys_name); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ee3af615f9..520ea8bed9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,6 +528,12 @@ config ARCH_BCM283X imply CMD_DM imply FAT_WRITE +config ARCH_BCM6858 + bool "Broadcom BCM6858 family" + select DM + select OF_CONTROL + imply CMD_DM + config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" select CPU_V7A @@ -601,6 +607,7 @@ config ARCH_EXYNOS select DM_SPI select DM_SPI_FLASH select SPI + imply SYS_THUMB_BUILD imply CMD_DM imply FAT_WRITE @@ -658,6 +665,20 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select BINMAN + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family developed by MediaTek Inc. + Please refer to doc/README.mediatek for more information. + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -674,7 +695,7 @@ config ARCH_IMX8 select DM select OF_CONTROL -config ARCH_MX8M +config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select DM @@ -764,6 +785,7 @@ config ARCH_RMOBILE imply CMD_DM imply FAT_WRITE imply SYS_THUMB_BUILD + imply ARCH_MISC_INIT if DISPLAY_CPUINFO config TARGET_S32V234EVB bool "Support s32v234evb" @@ -796,15 +818,11 @@ config ARCH_SOCFPGA select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT - select SPL_LIBDISK_SUPPORT select SPL_LIBGENERIC_SUPPORT - select SPL_MMC_SUPPORT if DM_MMC select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT - select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT - select SPL_SPI_SUPPORT if DM_SPI select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL select SYS_NS16550 @@ -815,8 +833,12 @@ config ARCH_SOCFPGA imply DM_SPI imply DM_SPI_FLASH imply FAT_WRITE + imply SPL_LIBDISK_SUPPORT + imply SPL_MMC_SUPPORT imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + imply SPL_SPI_FLASH_SUPPORT + imply SPL_SPI_SUPPORT config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" @@ -848,6 +870,7 @@ config ARCH_SUNXI imply CMD_UBI if NAND imply DISTRO_DEFAULTS imply FAT_WRITE + imply FIT imply OF_LIBFDT_OVERLAY imply PRE_CONSOLE_BUFFER imply SPL_GPIO_SUPPORT @@ -910,6 +933,7 @@ config ARCH_ZYNQMP_R5 select DM_SERIAL select OF_CONTROL imply CMD_DM + imply DM_USB_GADGET config ARCH_ZYNQMP bool "Xilinx ZynqMP based platform" @@ -927,6 +951,7 @@ config ARCH_ZYNQMP imply CMD_DM imply FAT_WRITE imply MP + imply DM_USB_GADGET config TEGRA bool "NVIDIA Tegra" @@ -1427,7 +1452,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig" source "arch/arm/mach-imx/imx8/Kconfig" -source "arch/arm/mach-imx/mx8m/Kconfig" +source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" @@ -1443,6 +1468,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" @@ -1490,12 +1517,14 @@ source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" +source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/broadcom/bcmns2/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/eets/pdu001/Kconfig" +source "board/emulation/qemu-arm/Kconfig" source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1935..87d9d4b9f7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA @@ -102,11 +103,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S index 0d8b59eb6b..eae69e36c3 100644 --- a/arch/arm/cpu/armv7/smccc-call.S +++ b/arch/arm/cpu/armv7/smccc-call.S @@ -7,6 +7,8 @@ #include #include + .section .text.efi_runtime + #define UNWIND(x...) /* * Wrap c macros in asm macros to delay expansion until after the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 81edec01bf..0cb6dd39cc 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,6 +205,15 @@ ENTRY(cpu_init_cp15) mov r2, r3, lsl #4 @ shift variant field for combined value orr r2, r4, r2 @ r2 has combined CPU variant + revision +/* Early stack for ERRATA that needs into call C code */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) +#else + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) +#endif + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 + #ifdef CONFIG_ARM_ERRATA_798870 cmp r2, #0x30 @ Applies to lower than R3p0 bge skip_errata_798870 @ skip if not affected rev diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index c8bebabdf6..1c12bbde75 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -96,6 +96,7 @@ endmenu config PSCI_RESET bool "Use PSCI for reset and shutdown" default y + select ARM_SMCCC if OF_CONTROL depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ @@ -144,6 +145,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + default n + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. + if SYS_HAS_ARMV8_SECURE_BASE config ARMV8_SECURE_BASE diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fadc0..2b086da79b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,7 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -22,22 +22,22 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN - select ARM_ERRATA_855873 + select ARM_ERRATA_855873 if !TFABOOT select FSL_LSCH2 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 - select SYS_FSL_ERRATUM_A009660 - select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009660 if !TFABOOT + select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009929 - select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR3 @@ -62,17 +62,17 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 - select SYS_FSL_ERRATUM_A008336 - select SYS_FSL_ERRATUM_A008511 - select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A008336 if !TFABOOT + select SYS_FSL_ERRATUM_A008511 if !TFABOOT + select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 - select SYS_FSL_ERRATUM_A009803 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009803 if !TFABOOT + select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A010165 if !TFABOOT select SYS_FSL_ERRATUM_A010539 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -180,9 +216,12 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -199,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -297,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -339,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -348,6 +392,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_NXP_SRDS_3 + bool + config SYS_HAS_SERDES bool @@ -398,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -458,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -500,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. @@ -514,3 +564,10 @@ config HAS_FSL_XHCI_USB help For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. + +config TFABOOT + bool "Support for booting from TFA" + default n + help + Enabling this will make a U-Boot binary that is capable of being + booted via TFA. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 91fdbad8be..e9bc987a9c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be00bd55ab..1fc025b581 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -31,8 +31,331 @@ #include #include +#ifdef CONFIG_TFABOOT +#include +#ifdef CONFIG_CHAIN_OF_TRUST +#include +#endif +#endif + DECLARE_GLOBAL_DATA_PTR; +static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), + CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), + CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), + CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), + CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), + CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), + CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), + CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), + CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), +}; + +#define EARLY_PGTABLE_SIZE 0x5000 +static struct mm_region early_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_FSL_IFC + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | +#endif + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif + {}, /* list terminator */ +}; + +static struct mm_region final_map[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + SYS_FSL_OCRAM_SPACE_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#ifdef CONFIG_FSL_IFC + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, +#endif + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + {}, /* space holder for secure mem */ +#endif + {}, +}; + struct mm_region *mem_map = early_map; void cpu_name(char *name) @@ -46,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -74,7 +401,10 @@ static inline void early_mmu_setup(void) unsigned int el = current_el(); /* global data is already setup, no allocation yet */ - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + if (el == 3) + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + else + gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; @@ -279,7 +609,221 @@ void enable_caches(void) icache_enable(); dcache_enable(); } +#endif /* CONFIG_SYS_DCACHE_OFF */ + +#ifdef CONFIG_TFABOOT +enum boot_src __get_boot_src(u32 porsr1) +{ + enum boot_src src = BOOT_SOURCE_RESERVED; + u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; +#if !defined(CONFIG_NXP_LSCH3_2) + u32 val; #endif + debug("%s: rcw_src 0x%x\n", __func__, rcw_src); + +#if defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_NXP_LSCH3_2) + switch (rcw_src) { + case RCW_SRC_SDHC1_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_SDHC2_VAL: + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + case RCW_SRC_FLEXSPI_NAND2K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_FLEXSPI_NAND4K_VAL: + src = BOOT_SOURCE_XSPI_NAND; + break; + case RCW_SRC_RESERVED_1_VAL: + src = BOOT_SOURCE_RESERVED; + break; + case RCW_SRC_FLEXSPI_NOR_24B: + src = BOOT_SOURCE_XSPI_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } +#else + val = rcw_src & RCW_SRC_TYPE_MASK; + if (val == RCW_SRC_NOR_VAL) { + val = rcw_src & NOR_TYPE_MASK; + + switch (val) { + case NOR_16B_VAL: + case NOR_32B_VAL: + src = BOOT_SOURCE_IFC_NOR; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } else { + /* RCW SRC Serial Flash */ + val = rcw_src & RCW_SRC_SERIAL_MASK; + switch (val) { + case RCW_SRC_QSPI_VAL: + /* RCW SRC Serial NOR (QSPI) */ + src = BOOT_SOURCE_QSPI_NOR; + break; + case RCW_SRC_SD_CARD_VAL: + /* RCW SRC SD Card */ + src = BOOT_SOURCE_SD_MMC; + break; + case RCW_SRC_EMMC_VAL: + /* RCW SRC EMMC */ + src = BOOT_SOURCE_SD_MMC2; + break; + case RCW_SRC_I2C1_VAL: + /* RCW SRC I2C1 Extended */ + src = BOOT_SOURCE_I2C1_EXTENDED; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } +#endif +#elif defined(CONFIG_FSL_LSCH2) + /* RCW SRC NAND */ + val = rcw_src & RCW_SRC_NAND_MASK; + if (val == RCW_SRC_NAND_VAL) { + val = rcw_src & NAND_RESERVED_MASK; + if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2) + src = BOOT_SOURCE_IFC_NAND; + + } else { + /* RCW SRC NOR */ + val = rcw_src & RCW_SRC_NOR_MASK; + if (val == NOR_8B_VAL || val == NOR_16B_VAL) { + src = BOOT_SOURCE_IFC_NOR; + } else { + switch (rcw_src) { + case QSPI_VAL1: + case QSPI_VAL2: + src = BOOT_SOURCE_QSPI_NOR; + break; + case SD_VAL: + src = BOOT_SOURCE_SD_MMC; + break; + default: + src = BOOT_SOURCE_RESERVED; + } + } + } +#endif + + if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) + src = BOOT_SOURCE_QSPI_NOR; + + debug("%s: src 0x%x\n", __func__, src); + return src; +} + +enum boot_src get_boot_src(void) +{ + struct pt_regs regs; + u32 porsr1 = 0; + +#if defined(CONFIG_FSL_LSCH3) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#endif + + if (current_el() == 2) { + regs.regs[0] = SIP_SVC_RCW; + + smc_call(®s); + if (!regs.regs[0]) + porsr1 = regs.regs[1]; + } + + if (current_el() == 3 || !porsr1) { +#ifdef CONFIG_FSL_LSCH3 + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + porsr1 = in_be32(&gur->porsr1); +#endif + } + + debug("%s: porsr1 0x%x\n", __func__, porsr1); + + return __get_boot_src(porsr1); +} + +#ifdef CONFIG_ENV_IS_IN_MMC +int mmc_get_env_dev(void) +{ + enum boot_src src = get_boot_src(); + int dev = CONFIG_SYS_MMC_ENV_DEV; + + switch (src) { + case BOOT_SOURCE_SD_MMC: + dev = 0; + break; + case BOOT_SOURCE_SD_MMC2: + dev = 1; + break; + default: + break; + } + + return dev; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_src src = get_boot_src(); + enum env_location env_loc = ENVL_NOWHERE; + + if (prio) + return ENVL_UNKNOWN; + +#ifdef CONFIG_CHAIN_OF_TRUST + /* Check Boot Mode + * If Boot Mode is Secure, return ENVL_NOWHERE + */ + if (fsl_check_boot_mode_secure() == 1) + goto done; +#endif + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + env_loc = ENVL_FLASH; + break; + case BOOT_SOURCE_QSPI_NOR: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NOR: + env_loc = ENVL_SPI_FLASH; + break; + case BOOT_SOURCE_IFC_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_QSPI_NAND: + /* FALLTHROUGH */ + case BOOT_SOURCE_XSPI_NAND: + env_loc = ENVL_NAND; + break; + case BOOT_SOURCE_SD_MMC: + /* FALLTHROUGH */ + case BOOT_SOURCE_SD_MMC2: + env_loc = ENVL_MMC; + break; + case BOOT_SOURCE_I2C1_EXTENDED: + /* FALLTHROUGH */ + default: + break; + } + +#ifdef CONFIG_CHAIN_OF_TRUST +done: +#endif + return env_loc; +} +#endif /* CONFIG_TFABOOT */ u32 initiator_type(u32 cluster, int init_id) { @@ -627,10 +1171,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER @@ -724,12 +1274,96 @@ phys_size_t get_effective_memsize(void) return ea_size; } +#ifdef CONFIG_TFABOOT +phys_size_t tfa_get_dram_size(void) +{ + struct pt_regs regs; + phys_size_t dram_size = 0; + + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = -1; + + smc_call(®s); + if (regs.regs[0]) + return 0; + + dram_size = regs.regs[1]; + return dram_size; +} + +static int tfa_dram_init_banksize(void) +{ + int i = 0, ret = 0; + struct pt_regs regs; + phys_size_t dram_size = tfa_get_dram_size(); + + debug("dram_size %llx\n", dram_size); + + if (!dram_size) + return -EINVAL; + + do { + regs.regs[0] = SMC_DRAM_BANK_INFO; + regs.regs[1] = i; + + smc_call(®s); + if (regs.regs[0]) { + ret = -EINVAL; + break; + } + + debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], + regs.regs[2]); + gd->bd->bi_dram[i].start = regs.regs[1]; + gd->bd->bi_dram[i].size = regs.regs[2]; + + dram_size -= gd->bd->bi_dram[i].size; + + i++; + } while (dram_size); + + if (i > 0) + ret = 0; + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + + return ret; +} +#endif + int dram_init_banksize(void) { #ifdef CONFIG_SYS_DP_DDR_BASE_PHY phys_size_t dp_ddr_size; #endif +#ifdef CONFIG_TFABOOT + if (!tfa_dram_init_banksize()) + return 0; +#endif /* * gd->ram_size has the total size of DDR memory, less reserved secure * memory. The DDR extends from low region to high region(s) presuming @@ -936,7 +1570,8 @@ void update_early_mmu_table(void) __weak int dram_init(void) { fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index a6ef830069..9583bf743e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 @@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, for example LS1043A. + +Watchdog support Overview +------------------- +Support watchdog driver for LSCH2. The driver is disabled in default. +You can enable it by setting CONFIG_IMX_WATCHDOG. +Use following config to set watchdog timeout, if this config is not defined, +the default timeout value is 128s which is the maximum. Set 10 seconds for +example: + #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000 +Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the +watchdog will not be fed in u-boot. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000000..6d4bd0b80a --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab9052d..a0e262169e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2bef841194..ab1be3fa54 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2016-2018 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -16,11 +17,23 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -57,6 +70,12 @@ int is_serdes_configured(enum srds_prtcl device) ret |= serdes2_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + + ret |= serdes3_prtcl_map[device]; +#endif return !!ret; } @@ -81,6 +100,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + case NXP_SRDS_3: + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT; + break; #endif default: printf("invalid SerDes%d\n", sd); @@ -129,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -149,6 +201,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, (int)lane_prtcl); break; } +#endif #endif } } @@ -200,6 +253,12 @@ struct serdes_prctl_info srds_prctl_info[] = { .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK, .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT }, +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + {.id = 3, + .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT + }, #endif {} /* NULL ENTRY */ }; @@ -340,6 +399,11 @@ int setup_serdes_volt(u32 svdd) struct ccsr_serdes __iomem *serdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); +#endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + struct ccsr_serdes __iomem *serdes3_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); #endif u32 cfg_tmp; int svdd_cur, svdd_tar; @@ -370,6 +434,9 @@ int setup_serdes_volt(u32 svdd) #ifdef CONFIG_SYS_FSL_SRDS_2 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false); +#endif /* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -383,6 +450,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset(cfg_tmp, serdes3_base); +#endif + /* Put the Rx/Tx calibration into reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_rx_tx_cal_reset(serdes1_base); @@ -392,6 +465,10 @@ int setup_serdes_volt(u32 svdd) do_rx_tx_cal_reset(serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_rx_tx_cal_reset(serdes3_base); +#endif + ret = set_serdes_volt(svdd); if (ret < 0) { printf("could not change SVDD\n"); @@ -408,6 +485,11 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_serdes_enable(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_serdes_enable(cfg_tmp, serdes3_base); +#endif /* Wait for at at least 625us, ensure the PLLs being reset are locked */ udelay(800); @@ -422,6 +504,13 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_pll_lock(cfg_tmp, serdes2_base); #endif + +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_lock(cfg_tmp, serdes3_base); +#endif + /* Take the all enabled lanes out of reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); @@ -430,6 +519,10 @@ int setup_serdes_volt(u32 svdd) do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true); +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; @@ -441,6 +534,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset_done(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset_done(cfg_tmp, serdes3_base); +#endif + return ret; } @@ -472,4 +571,12 @@ void fsl_serdes_init(void) FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + serdes_init(NXP_SRDS_3, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, + FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index ef3987ea84..6721a579ea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: @@ -295,7 +304,8 @@ ENTRY(lowlevel_init) 100: #endif -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_TFABOOT) && \ + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) bl fsl_ocram_init #endif @@ -344,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000000..a04a370268 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 54fb0745f9..0092a22394 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -24,6 +24,10 @@ #include #endif #include +#ifdef CONFIG_TFABOOT +#include +DECLARE_GLOBAL_DATA_PTR; +#endif bool soc_has_dp_ddr(void) { @@ -679,12 +683,136 @@ int qspi_ahb_init(void) } #endif +#ifdef CONFIG_TFABOOT +#define MAX_BOOTCMD_SIZE 256 + +int fsl_setenv_bootcmd(void) +{ + int ret; + enum boot_src src = get_boot_src(); + char bootcmd_str[MAX_BOOTCMD_SIZE]; + + switch (src) { +#ifdef IFC_NOR_BOOTCOMMAND + case BOOT_SOURCE_IFC_NOR: + sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NOR: + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NOR: + sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef IFC_NAND_BOOTCOMMAND + case BOOT_SOURCE_IFC_NAND: + sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NAND: + sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NAND: + sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef SD_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC: + sprintf(bootcmd_str, SD_BOOTCOMMAND); + break; +#endif +#ifdef SD2_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC2: + sprintf(bootcmd_str, SD2_BOOTCOMMAND); + break; +#endif + default: +#ifdef QSPI_NOR_BOOTCOMMAND + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); +#endif + break; + } + + ret = env_set("bootcmd", bootcmd_str); + if (ret) { + printf("Failed to set bootcmd: ret = %d\n", ret); + return ret; + } + return 0; +} + +int fsl_setenv_mcinitcmd(void) +{ + int ret = 0; + enum boot_src src = get_boot_src(); + + switch (src) { +#ifdef IFC_MC_INIT_CMD + case BOOT_SOURCE_IFC_NAND: + case BOOT_SOURCE_IFC_NOR: + ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); + break; +#endif +#ifdef QSPI_MC_INIT_CMD + case BOOT_SOURCE_QSPI_NAND: + case BOOT_SOURCE_QSPI_NOR: + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); + break; +#endif +#ifdef XSPI_MC_INIT_CMD + case BOOT_SOURCE_XSPI_NAND: + case BOOT_SOURCE_XSPI_NOR: + ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); + break; +#endif +#ifdef SD_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC: + ret = env_set("mcinitcmd", SD_MC_INIT_CMD); + break; +#endif +#ifdef SD2_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC2: + ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); + break; +#endif + default: +#ifdef QSPI_MC_INIT_CMD + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); +#endif + break; + } + + if (ret) { + printf("Failed to set mcinitcmd: ret = %d\n", ret); + return ret; + } + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_TFABOOT + /* + * check if gd->env_addr is default_environment; then setenv bootcmd + * and mcinitcmd. + */ + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { + fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); + } +#endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); #endif diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 0ba3dad8cc..9957c2974b 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -19,7 +18,7 @@ * x0~x7: input arguments * x0~x3: output arguments */ -static void __efi_runtime hvc_call(struct pt_regs *args) +static void hvc_call(struct pt_regs *args) { asm volatile( "ldr x0, %0\n" @@ -53,7 +52,7 @@ static void __efi_runtime hvc_call(struct pt_regs *args) * x0~x3: output arguments */ -void __efi_runtime smc_call(struct pt_regs *args) +void smc_call(struct pt_regs *args) { asm volatile( "ldr x0, %0\n" @@ -83,9 +82,9 @@ void __efi_runtime smc_call(struct pt_regs *args) * use PSCI on U-Boot running below a hypervisor, please detect * this and set the flag accordingly. */ -static const __efi_runtime_data bool use_smc_for_psci = true; +static const bool use_smc_for_psci = true; -void __noreturn __efi_runtime psci_system_reset(void) +void __noreturn psci_system_reset(void) { struct pt_regs regs; @@ -100,7 +99,7 @@ void __noreturn __efi_runtime psci_system_reset(void) ; } -void __noreturn __efi_runtime psci_system_off(void) +void __noreturn psci_system_off(void) { struct pt_regs regs; @@ -114,44 +113,3 @@ void __noreturn __efi_runtime psci_system_off(void) while (1) ; } - -#ifdef CONFIG_CMD_POWEROFF -int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - puts("poweroff ...\n"); - - udelay(50000); /* wait 50 ms */ - - disable_interrupts(); - - psci_system_off(); - - /*NOTREACHED*/ - return 0; -} -#endif - -#ifdef CONFIG_PSCI_RESET -void reset_misc(void) -{ - psci_system_reset(); -} - -#ifdef CONFIG_EFI_LOADER -void __efi_runtime EFIAPI efi_reset_system( - enum efi_reset_type reset_type, - efi_status_t reset_status, - unsigned long data_size, void *reset_data) -{ - if (reset_type == EFI_RESET_COLD || - reset_type == EFI_RESET_WARM || - reset_type == EFI_RESET_PLATFORM_SPECIFIC) { - psci_system_reset(); - } else if (reset_type == EFI_RESET_SHUTDOWN) { - psci_system_off(); - } - - while (1) { } -} -#endif /* CONFIG_EFI_LOADER */ -#endif /* CONFIG_PSCI_RESET */ diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 097f91bace..358df8fee9 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -236,6 +236,28 @@ handle_sync: b unhandled_exception +#ifdef CONFIG_ARMV8_EA_EL3_FIRST +/* + * Override this function if custom error handling is + * needed for asynchronous aborts + */ +ENTRY(plat_error_handler) + ret +ENDPROC(plat_error_handler) +.weak plat_error_handler + +handle_error: + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov x9, #1 + msr spsel, x9 + mov sp, x0 + + bl plat_error_handler /* Platform specific error handling */ +deadloop: + b deadloop /* Never return */ +#endif + .align 11 .globl el3_exception_vectors el3_exception_vectors: @@ -261,7 +283,11 @@ el3_exception_vectors: .align 7 b unhandled_exception /* FIQ, Lower EL using AArch64 */ .align 7 +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + b handle_error /* SError, Lower EL using AArch64 */ +#else b unhandled_exception /* SError, Lower EL using AArch64 */ +#endif .align 7 b unhandled_exception /* Sync, Lower EL using AArch32 */ .align 7 diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index a13c92e246..8dc0ac9266 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void) */ bool sec_firmware_support_hwrng(void) { +#ifdef CONFIG_TFABOOT + /* return true as TFA has one job ring reserved */ + return true; +#endif if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { return true; } diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 1c0f963e18..af1b2da072 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32) mov x3, x2 mov x2, x1 mov x1, x4 - ldr x0, =0xc000ff04 + ldr x0, =0xc200ff17 smc #0 ret ENDPROC(armv8_el2_to_aarch32) diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S index 16c9e298b4..86de4b4089 100644 --- a/arch/arm/cpu/armv8/smccc-call.S +++ b/arch/arm/cpu/armv8/smccc-call.S @@ -6,6 +6,8 @@ #include #include + .section .text.efi_runtime + .macro SMCCC instr .cfi_startproc \instr #0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5236fda736..d3330d9ea5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-minnie.dtb \ rk3288-vyasa.dtb \ rk3328-evb.dtb \ + rk3399-ficus.dtb \ rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ @@ -51,6 +52,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-rock960.dtb \ + rv1108-elgin-r1.dtb \ rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ @@ -59,7 +62,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-p212.dtb \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ - meson-gxm-khadas-vim2.dtb + meson-gxm-khadas-vim2.dtb \ + meson-axg-s400.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -100,6 +104,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-7040-db-nand.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ + armada-8040-clearfog-gt-8k.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ @@ -199,7 +204,8 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ am335x-icev2.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ - am335x-pdu001.dtb + am335x-pdu001.dtb \ + am335x-chiliboard.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ @@ -378,6 +384,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dts dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ @@ -408,6 +415,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtb dtb-$(CONFIG_MACH_SUN50I) += \ @@ -418,6 +426,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-orangepi-win.dtb \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ @@ -469,6 +478,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb-u-boot.dtb \ r8a7795-salvator-x-u-boot.dtb \ @@ -569,7 +580,11 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb -dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb +dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb + +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts new file mode 100644 index 0000000000..f939cf6406 --- /dev/null +++ b/arch/arm/dts/am335x-baltos.dts @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include + +/ { + model = "OnRISC Baltos"; + compatible = "vscom,onrisc", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + >; + }; + + tps65910_pins: pinmux_tps65910_pins { + pinctrl-single,pins = < + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + + }; + tca6416_pins: pinmux_tca6416_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + boot@0 { + label = "SPL"; + reg = <0x0 0x20000>; + }; + boot@20000{ + label = "SPL.backup1"; + reg = <0x20000 0x20000>; + }; + boot@40000 { + label = "SPL.backup2"; + reg = <0x40000 0x20000>; + }; + boot@60000 { + label = "SPL.backup3"; + reg = <0x60000 0x20000>; + }; + boot@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + boot@260000 { + label = "UBI"; + reg = <0x260000 0xfda0000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <1000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi new file mode 100644 index 0000000000..4f9d308039 --- /dev/null +++ b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2018 Grinn Sp. z o.o. -- http://www.grinn-global.com/ + * Author: Marcin Niestroj + */ + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts new file mode 100644 index 0000000000..59431b2359 --- /dev/null +++ b/arch/arm/dts/am335x-chiliboard.dts @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "am335x-chilisom.dtsi" + +/ { + model = "AM335x Chiliboard"; + compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom", + "ti,am33xx"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_gpio_pins>; + + led0 { + label = "led0"; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led1"; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&am33xx_pinmux { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + /* mdio_clk.mdio_clk */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb1_drvvbus: usb1_drvvbus { + pinctrl-single,pins = < + AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ + >; + }; + + sd_pins: pinmux_sd_card { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + led_gpio_pins: led_gpio_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */ + AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&ldo4_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* Ethernet */ +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +/* USB */ +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_drvvbus>; + + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/* microSD */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins>; + vmmc-supply = <&ldo4_reg>; + bus-width = <0x4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&tps { + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + charger { + status = "okay"; + }; + + pwrbutton { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi new file mode 100644 index 0000000000..1b43ebd08b --- /dev/null +++ b/arch/arm/dts/am335x-chilisom.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Author: Rostislav Lisovy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am33xx.dtsi" +#include + +/ { + model = "Grinn AM335x ChiliSOM"; + compatible = "grinn,am335x-chilisom", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nandflash_pins: nandflash_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3d"; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&rtc { + system-power-controller; + + pinctrl-0 = <&ext_wakeup>; + pinctrl-names = "default"; + + ext_wakeup: ext-wakeup { + pins = "ext_wakeup0"; + input-enable; + }; +}; + +/* NAND Flash */ +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + }; +}; diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index a6f20af648..fe27207588 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -80,8 +80,6 @@ gpio_keys: volume_keys@0 { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; switch@9 { @@ -723,8 +721,8 @@ &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 12 - &edma 13>; + dmas = <&edma 12 0 + &edma 13 0>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts index b3e9b61bae..0767578aee 100644 --- a/arch/arm/dts/am335x-evmsk.dts +++ b/arch/arm/dts/am335x-evmsk.dts @@ -109,8 +109,6 @@ gpio_buttons: gpio_buttons@0 { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; switch@1 { label = "button0"; diff --git a/arch/arm/dts/am335x-pdu001-u-boot.dtsi b/arch/arm/dts/am335x-pdu001-u-boot.dtsi index fbb6a3ff6b..84a07bdef4 100644 --- a/arch/arm/dts/am335x-pdu001-u-boot.dtsi +++ b/arch/arm/dts/am335x-pdu001-u-boot.dtsi @@ -29,10 +29,18 @@ u-boot,dm-pre-reloc; }; +&mmc1 { + u-boot,dm-pre-reloc; +}; + &mmc1_pins { u-boot,dm-pre-reloc; }; +&mmc2 { + u-boot,dm-pre-reloc; +}; + &mmc2_pins { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts index 121e2c6207..3a5e952663 100644 --- a/arch/arm/dts/am335x-pdu001.dts +++ b/arch/arm/dts/am335x-pdu001.dts @@ -576,7 +576,7 @@ bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; - cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; &sham { diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi index 8d58cd4c91..d9243d5d3d 100644 --- a/arch/arm/dts/am335x-pxm2.dtsi +++ b/arch/arm/dts/am335x-pxm2.dtsi @@ -50,8 +50,6 @@ gpio_keys: restart-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; restart0 { diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts index c6cfbb8033..a5716a929f 100644 --- a/arch/arm/dts/am335x-rut.dts +++ b/arch/arm/dts/am335x-rut.dts @@ -36,8 +36,6 @@ gpio_keys: powerfail-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pwr-fail0 { @@ -190,12 +188,8 @@ &epwmss1 { status = "okay"; - - ehrpwm1: ehrpwm@48302200 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&epwmss1_pins>; - }; + pinctrl-names = "default"; + pinctrl-0 = <&epwmss1_pins>; }; &gpmc { diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi index afb4b3a7ba..95d5c9d136 100644 --- a/arch/arm/dts/am33xx-clocks.dtsi +++ b/arch/arm/dts/am33xx-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; @@ -163,7 +163,7 @@ clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; @@ -176,7 +176,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck { + dpll_core_m4_ck: dpll_core_m4_ck@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -185,7 +185,7 @@ ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck { + dpll_core_m5_ck: dpll_core_m5_ck@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -194,7 +194,7 @@ ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck { + dpll_core_m6_ck: dpll_core_m6_ck@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -203,14 +203,14 @@ ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -219,14 +219,14 @@ ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -243,14 +243,14 @@ clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck { + dpll_disp_ck: dpll_disp_ck@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck { + dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>; @@ -260,14 +260,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -292,14 +292,6 @@ clock-div = <4>; }; - cefuse_fck: cefuse_fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <1>; - reg = <0x0a20>; - }; - clk_24mhz: clk_24mhz { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -316,14 +308,6 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <1>; - reg = <0x014c>; - }; - l3_gclk: l3_gclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -332,14 +316,14 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk { + pruss_ocp_gclk: pruss_ocp_gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck { + mmu_fck: mmu_fck@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>; @@ -347,56 +331,56 @@ reg = <0x0914>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; + clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck { + usbotg_fck: usbotg_fck@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_ck>; @@ -412,7 +396,7 @@ clock-div = <2>; }; - ieee5000_fck: ieee5000_fck { + ieee5000_fck: ieee5000_fck@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -420,10 +404,10 @@ reg = <0x00e4>; }; - wdt1_fck: wdt1_fck { + wdt1_fck: wdt1_fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; @@ -483,53 +467,21 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; - gpio0_dbclk: gpio0_dbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&gpio0_dbclk_mux_ck>; - ti,bit-shift = <18>; - reg = <0x0408>; - }; - - gpio1_dbclk: gpio1_dbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00ac>; - }; - - gpio2_dbclk: gpio2_dbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b0>; - }; - - gpio3_dbclk: gpio3_dbclk { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ick>; - ti,bit-shift = <18>; - reg = <0x00b4>; - }; - - lcd_gclk: lcd_gclk { + lcd_gclk: lcd_gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; @@ -545,7 +497,7 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; @@ -553,7 +505,7 @@ reg = <0x052c>; }; - gfx_fck_div_ck: gfx_fck_div_ck { + gfx_fck_div_ck: gfx_fck_div_ck@52c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>; @@ -561,14 +513,14 @@ ti,max-div = <2>; }; - sysclkout_pre_ck: sysclkout_pre_ck { + sysclkout_pre_ck: sysclkout_pre_ck@700 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; reg = <0x0700>; }; - clkout2_div_ck: clkout2_div_ck { + clkout2_div_ck: clkout2_div_ck@700 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sysclkout_pre_ck>; @@ -577,59 +529,7 @@ reg = <0x0700>; }; - dbg_sysclk_ck: dbg_sysclk_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <19>; - reg = <0x0414>; - }; - - dbg_clka_ck: dbg_clka_ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_core_m4_ck>; - ti,bit-shift = <30>; - reg = <0x0414>; - }; - - stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <22>; - reg = <0x0414>; - }; - - trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; - ti,bit-shift = <20>; - reg = <0x0414>; - }; - - stm_clk_div_ck: stm_clk_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&stm_pmd_clock_mux_ck>; - ti,bit-shift = <27>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - - trace_clk_div_ck: trace_clk_div_ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&trace_pmd_clk_mux_ck>; - ti,bit-shift = <24>; - ti,max-div = <64>; - reg = <0x0414>; - ti,index-power-of-two; - }; - - clkout2_ck: clkout2_ck { + clkout2_ck: clkout2_ck@700 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout2_div_ck>; @@ -638,9 +538,88 @@ }; }; -&prcm_clockdomains { - clk_24mhz_clkdm: clk_24mhz_clkdm { - compatible = "ti,clockdomain"; - clocks = <&clkdiv32k_ick>; +&prcm { + l4_per_cm: l4_per_cm@0 { + compatible = "ti,omap4-cm"; + reg = <0x0 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x200>; + + l4_per_clkctrl: clk@14 { + compatible = "ti,clkctrl"; + reg = <0x14 0x13c>; + #clock-cells = <2>; + }; + }; + + l4_wkup_cm: l4_wkup_cm@400 { + compatible = "ti,omap4-cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + l4_wkup_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0xd4>; + #clock-cells = <2>; + }; + }; + + mpu_cm: mpu_cm@600 { + compatible = "ti,omap4-cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + mpu_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0x4>; + #clock-cells = <2>; + }; + }; + + l4_rtc_cm: l4_rtc_cm@800 { + compatible = "ti,omap4-cm"; + reg = <0x800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x100>; + + l4_rtc_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x4>; + #clock-cells = <2>; + }; + }; + + gfx_l3_cm: gfx_l3_cm@900 { + compatible = "ti,omap4-cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + gfx_l3_clkctrl: clk@4 { + compatible = "ti,clkctrl"; + reg = <0x4 0x4>; + #clock-cells = <2>; + }; + }; + + l4_cefuse_cm: l4_cefuse_cm@a00 { + compatible = "ti,omap4-cm"; + reg = <0xa00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa00 0x100>; + + l4_cefuse_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; }; }; diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index 42345375e6..d3dd6a16e7 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -10,12 +10,14 @@ #include #include - -#include "skeleton.dtsi" +#include / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; aliases { i2c0 = &i2c0; @@ -27,14 +29,16 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - d_can0 = &dcan0; - d_can1 = &dcan1; + d-can0 = &dcan0; + d-can1 = &dcan1; usb0 = &usb0; usb1 = &usb1; phy0 = &usb0_phy; phy1 = &usb1_phy; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; + spi0 = &spi0; + spi1 = &spi1; }; cpus { @@ -45,19 +49,7 @@ device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -66,9 +58,84 @@ }; }; - pmu { + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -80,6 +147,8 @@ mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; }; }; @@ -91,7 +160,6 @@ * the whole bus hierarchy. */ ocp { - u-boot,dm-spl; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -104,9 +172,21 @@ #size-cells = <1>; ranges = <0 0x44c00000 0x280000>; + wkup_m3: wkup_m3@100000 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x100000 0x4000>, + <0x180000 0x2000>; + reg-names = "umem", "dmem"; + ti,hwmods = "wkup_m3"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + prcm: prcm@200000 { - compatible = "ti,am3-prcm"; + compatible = "ti,am3-prcm", "simple-bus"; reg = <0x200000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x4000>; prcm_clocks: clocks { #address-cells = <1>; @@ -122,6 +202,7 @@ reg = <0x210000 0x2000>; #address-cells = <1>; #size-cells = <1>; + #pinctrl-cells = <1>; ranges = <0 0x210000 0x2000>; am33xx_pinmux: pinmux@800 { @@ -129,15 +210,17 @@ reg = <0x800 0x238>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; }; scm_conf: scm_conf@0 { - compatible = "syscon"; + compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0 0x800>; scm_clocks: clocks { #address-cells = <1>; @@ -145,6 +228,22 @@ }; }; + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + scm_clockdomains: clockdomains { }; }; @@ -158,12 +257,44 @@ }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = <12 13 14>; - #dma-cells = <1>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; }; gpio0: gpio@44e07000 { @@ -211,67 +342,61 @@ }; uart0: serial@44e09000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; - reg-shift = <2>; interrupts = <72>; status = "disabled"; - dmas = <&edma 26>, <&edma 27>; + dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; uart1: serial@48022000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; - reg-shift = <2>; interrupts = <73>; status = "disabled"; - dmas = <&edma 28>, <&edma 29>; + dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; uart2: serial@48024000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; - reg-shift = <2>; interrupts = <74>; status = "disabled"; - dmas = <&edma 30>, <&edma 31>; + dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; uart3: serial@481a6000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; - reg-shift = <2>; interrupts = <44>; status = "disabled"; }; uart4: serial@481a8000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; - reg-shift = <2>; interrupts = <45>; status = "disabled"; }; uart5: serial@481aa000 { - compatible = "ti,omap3-uart"; + compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; - reg-shift = <2>; interrupts = <46>; status = "disabled"; }; @@ -312,8 +437,8 @@ ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma_xbar 24 0 0 + &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; reg = <0x48060000 0x1000>; @@ -324,8 +449,8 @@ compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0 + &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; reg = <0x481d8000 0x1000>; @@ -377,7 +502,7 @@ status = "disabled"; }; - mailbox: mailbox@480C8000 { + mailbox: mailbox@480c8000 { compatible = "ti,omap4-mailbox"; reg = <0x480C8000 0x200>; interrupts = <77>; @@ -386,6 +511,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; @@ -397,6 +523,8 @@ interrupts = <67>; ti,hwmods = "timer1"; ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; }; timer2: timer@48040000 { @@ -404,6 +532,8 @@ reg = <0x48040000 0x400>; interrupts = <68>; ti,hwmods = "timer2"; + clocks = <&timer2_fck>; + clock-names = "fck"; }; timer3: timer@48042000 { @@ -451,6 +581,8 @@ interrupts = <75 76>; ti,hwmods = "rtc"; + clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clock-names = "int-clk"; }; spi0: spi@48030000 { @@ -461,10 +593,10 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 - &edma 17 - &edma 18 - &edma 19>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -477,10 +609,10 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -508,6 +640,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb0: usb@47401000 { @@ -556,6 +689,7 @@ reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; + #phy-cells = <0>; }; usb1: usb@47401800 { @@ -625,20 +759,24 @@ 0x48300200 0x48300200 0x80>; /* EHRPWM */ ecap0: ecap@48300100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; - ti,hwmods = "ecap0"; status = "disabled"; }; - ehrpwm0: ehrpwm@48300200 { - compatible = "ti,am33xx-ehrpwm"; + ehrpwm0: pwm@48300200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -655,20 +793,24 @@ 0x48302200 0x48302200 0x80>; /* EHRPWM */ ecap1: ecap@48302100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; - ti,hwmods = "ecap1"; status = "disabled"; }; - ehrpwm1: ehrpwm@48302200 { - compatible = "ti,am33xx-ehrpwm"; + ehrpwm1: pwm@48302200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; @@ -685,34 +827,36 @@ 0x48304200 0x48304200 0x80>; /* EHRPWM */ ecap2: ecap@48304100 { - compatible = "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; - ti,hwmods = "ecap2"; status = "disabled"; }; - ehrpwm2: ehrpwm@48304200 { - compatible = "ti,am33xx-ehrpwm"; + ehrpwm2: pwm@48304200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; status = "disabled"; }; }; mac: ethernet@4a100000 { - compatible = "ti,cpsw"; + compatible = "ti,am335x-cpsw","ti,cpsw"; ti,hwmods = "cpgmac0"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; - no_bd_ram = <0>; - rx_descs = <64>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; @@ -734,7 +878,7 @@ status = "disabled"; davinci_mdio: mdio@4a101000 { - compatible = "ti,davinci_mdio"; + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "davinci_mdio"; @@ -763,14 +907,21 @@ ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x10000>; /* 64k */ - }; + ranges = <0x0 0x40300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; - wkup_m3: wkup_m3@44d00000 { - compatible = "ti,am3353-wkup-m3"; - reg = <0x44d00000 0x4000 /* M3 UMEM */ - 0x44d80000 0x2000>; /* M3 DMEM */ - ti,hwmods = "wkup_m3"; - ti,no-reset-on-init; + pm_sram_code: pm-sram-code@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-sram-data@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; elm: elm@48080000 { @@ -795,6 +946,8 @@ interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; @@ -805,16 +958,32 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + interrupts = <101>; + sram = <&pm_sram_code + &pm_sram_data>; + ti,no-idle; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; @@ -823,7 +992,7 @@ ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; }; @@ -832,8 +1001,8 @@ ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; - dmas = <&edma 6>, - <&edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -846,12 +1015,12 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; - mcasp1: mcasp@4803C000 { + mcasp1: mcasp@4803c000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp1"; reg = <0x4803C000 0x2000>, @@ -860,8 +1029,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; @@ -874,4 +1043,4 @@ }; }; -/include/ "am33xx-clocks.dtsi" +#include "am33xx-clocks.dtsi" diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi new file mode 100644 index 0000000000..e841918c1c --- /dev/null +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + codec1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "tlv320aic23-hifi"; + + simple-audio-card,widgets = + "Microphone", "Mic In", + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "Line Out", "LOUT", + "Line Out", "ROUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic In"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcbsp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic23_1>; + system-clock-frequency = <12000000>; + }; + }; + + codec2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "tlv320aic23-hifi"; + + simple-audio-card,widgets = + "Microphone", "Mic In", + "Line", "Line In", + "Line", "Line Out"; + + simple-audio-card,routing = + "Line Out", "LOUT", + "Line Out", "ROUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic In"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master2>; + simple-audio-card,frame-master = <&sound_master2>; + + simple-audio-card,cpu { + sound-dai = <&mcbsp2>; + }; + + sound_master2: simple-audio-card,codec { + sound-dai = <&tlv320aic23_2>; + system-clock-frequency = <12000000>; + }; + }; + + expander-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + record { + label = "Record"; + /* linux,code = ; */ + gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; + }; + + play { + label = "Play"; + linux,code = ; + gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; + }; + + Stop { + label = "Stop"; + linux,code = ; + gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; + }; + + fwd { + label = "FWD"; + linux,code = ; + gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; + }; + + rwd { + label = "RWD"; + linux,code = ; + gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; + }; + + shift { + label = "Shift"; + linux,code = ; + gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; + }; + + Mode { + label = "Mode"; + linux,code = ; + gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; + }; + + Menu { + label = "Menu"; + linux,code = ; + gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; + }; + + Up { + label = "Up"; + linux,code = ; + gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; + }; + + Down { + label = "Down"; + linux,code = ; + gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c2 { + /* Audio codecs */ + tlv320aic23_1: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells= <0>; + status = "okay"; + }; + + tlv320aic23_2: codec@1b { + compatible = "ti,tlv320aic23"; + reg = <0x1b>; + #sound-dai-cells= <0>; + status = "okay"; + }; +}; + +&i2c3 { + /* Audio codecs */ + tlv320aic23_3: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells= <0>; + status = "okay"; + }; + + /* GPIO Expanders */ + tca6416_2: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; + }; + + tca6416_3: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; + }; + + /* TVP5146 Analog Video decoder input */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; + +&mcbsp1 { + status = "ok"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; +}; + +&mcbsp2 { + status = "ok"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; + +&omap3_pmx_core { + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ + OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ + >; + }; +}; diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index 98aadb0f81..1e2bb68231 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -9,6 +9,7 @@ #include "am3517.dtsi" #include "am3517-som.dtsi" +#include "am3517-evm-ui.dtsi" #include / { @@ -127,6 +128,7 @@ status = "okay"; pinctrl-names = "default"; enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ + vcc-supply = <&vdd_io_reg>; port { lcd_in: endpoint { @@ -154,6 +156,7 @@ bl: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; + power-supply = <&vdd_io_reg>; pinctrl-0 = <&backlight_pins>; pwms = <&pwm11 0 5000000 0>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; @@ -168,6 +171,13 @@ ti,timers = <&timer11>; #pwm-cells = <3>; }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ + #phy-cells = <0>; + }; }; &davinci_emac { @@ -203,6 +213,7 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&vdd_io_reg>; }; }; @@ -217,18 +228,24 @@ vmmc-supply = <&vmmc_fixed>; bus-width = <4>; wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */ -}; - -&mmc2 { - status = "disabled"; + cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ }; &mmc3 { status = "disabled"; }; +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -287,4 +304,32 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ >; }; + + hsusb1_rst_pins: pinmux_hsusb1_rst_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; + + hsusb1_pins: pinmux_hsusb1_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + >; + }; }; diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi index a6d5ff73c1..b1c988eed8 100644 --- a/arch/arm/dts/am3517-som.dtsi +++ b/arch/arm/dts/am3517-som.dtsi @@ -14,6 +14,32 @@ cpu0-supply = <&vdd_core_reg>; }; }; + + wl12xx_buffer: wl12xx_buf { + compatible = "regulator-fixed"; + regulator-name = "wl1271_buf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_buffer_pins>; + gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ + regulator-always-on; + vin-supply = <&vdd_1v8_reg>; + }; + + wl12xx_vmmc2: wl12xx_vmmc2 { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_wkup_pins>; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + vin-supply = <&wl12xx_buffer>; + }; }; &gpmc { @@ -64,7 +90,6 @@ regulators { vdd_core_reg: VDCDC1 { regulator-name = "vdd_core"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -72,7 +97,6 @@ vdd_io_reg: VDCDC2 { regulator-name = "vdd_io"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -80,7 +104,6 @@ vdd_1v8_reg: VDCDC3 { regulator-name = "vdd_1v8"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -88,7 +111,6 @@ vdd_usb18_reg: LDO1 { regulator-name = "vdd_usb18"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -96,7 +118,6 @@ vdd_usb33_reg: LDO2 { regulator-name = "vdd_usb33"; - compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -126,8 +147,63 @@ }; }; +&mmc2 { + interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; + + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&wl12xx_vmmc2>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + bluetooth { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ + max-speed = <3000000>; + }; +}; + &omap3_pmx_core { + wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ + OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ + OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + rtc_pins: pinmux_rtc_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ @@ -139,4 +215,23 @@ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ + OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ + >; + }; +}; + +&omap3_pmx_wkup { + + wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + >; + }; }; diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi index 4b6062b631..23ea381d36 100644 --- a/arch/arm/dts/am3517.dtsi +++ b/arch/arm/dts/am3517.dtsi @@ -91,6 +91,11 @@ }; }; +/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ +&usb_otg_hs { + status = "disabled"; +}; + &iva { status = "disabled"; }; diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi b/arch/arm/dts/am4372-generic-u-boot.dtsi index d485679de4..6ba5c16492 100644 --- a/arch/arm/dts/am4372-generic-u-boot.dtsi +++ b/arch/arm/dts/am4372-generic-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "am4372-u-boot.dtsi" + /{ ocp { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/am4372-u-boot.dtsi b/arch/arm/dts/am4372-u-boot.dtsi new file mode 100644 index 0000000000..99922ca030 --- /dev/null +++ b/arch/arm/dts/am4372-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&am43xx_control_usb2phy1 { + compatible = "ti,control-phy-usb2-am437", "syscon"; +}; + +&am43xx_control_usb2phy2 { + compatible = "ti,control-phy-usb2-am437", "syscon"; +}; + +&ocp2scp0 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus"; +}; + +&ocp2scp1 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus"; +}; + +&dwc3_1 { + u-boot,dm-spl; +}; + +&usb1 { + u-boot,dm-spl; +}; + +&usb2_phy1 { + u-boot,dm-spl; +}; + +&am43xx_control_usb2phy1 { + u-boot,dm-spl; +}; + +&ocp2scp0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index 3ffa8e016e..6f60a32999 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -108,8 +108,6 @@ compatible = "ti,am437-padconf", "pinctrl-single"; reg = <0x800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; @@ -119,8 +117,6 @@ scm_conf: scm_conf@0 { compatible = "syscon"; reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; scm_clocks: clocks { #address-cells = <1>; @@ -764,7 +760,8 @@ reg = <0x48038000 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <80>, <81>; + interrupts = , + ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8>, @@ -778,7 +775,8 @@ reg = <0x4803C000 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; - interrupts = <82>, <83>; + interrupts = , + ; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10>, @@ -807,6 +805,8 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi index 530f54989c..d950d32f17 100644 --- a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi @@ -7,6 +7,8 @@ * Based on "dra7.dtsi" */ +#include "am4372-u-boot.dtsi" + /{ ocp { u-boot,dm-spl; @@ -36,3 +38,7 @@ &phy_sel { u-boot,dm-spl; }; + +&i2c0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi index 0a3d79a372..3aa9195e44 100644 --- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "am4372-u-boot.dtsi" + /{ ocp { u-boot,dm-spl; diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts index e454647165..28e3e1ba32 100644 --- a/arch/arm/dts/am437x-idk-evm.dts +++ b/arch/arm/dts/am437x-idk-evm.dts @@ -106,8 +106,6 @@ compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins_default>; - #address-cells = <1>; - #size-cells = <0>; switch@0 { label = "power-button"; diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi index 0a3d79a372..3aa9195e44 100644 --- a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "am4372-u-boot.dtsi" + /{ ocp { u-boot,dm-spl; diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi new file mode 100644 index 0000000000..4b20610d83 --- /dev/null +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + spi1 = &spi1; + }; +}; + +ð0 { + phy-reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; +}; + +&spi1 { + u-boot,dm-spl; +}; + +&w25q32 { + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts new file mode 100644 index 0000000000..498105f25f --- /dev/null +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 SolidRun ltd + */ + +#include "armada-8040.dtsi" + +/ { + model = "ClearFog-GT-8K"; + compatible = "solidrun,clearfog-gt-8k", + "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cpm_i2c0; + i2c1 = &cpm_i2c1; + spi0 = &cps_spi1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + simple-bus { + compatible = "simple-bus"; + + reg_usb3h0_vbus: usb3-vbus0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_xhci_vbus_pins>; + regulator-name = "reg-usb3h0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <300000>; + shutdown-delay-us = <500000>; + regulator-force-boot-off; + gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */ + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&cpm_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins: + * [11] CLKOUT_MPP_11 (out) + * [23] LINK_RD_IN_CP2CP (in) + * [25] CLKOUT_MPP_25 (out) + * [29] AVS_FB_IN_CP2CP (in) + * [32, 33, 34] pci0/1/2 reset + * [35-38] CP0 I2C1 and I2C0 + * [39] GPIO reset button + * [40,41] LED0 and LED1 + * [43] 1512 phy reset + * [47] USB VBUS EN (active low) + * [48] FAN PWM + * [49] SFP+ present signal + * [50] TPM interrupt + * [51] WLAN0 disable + * [52] WLAN1 disable + * [53] LTE disable + * [54] NFC reset + * [55] Micro SD card detect + * [56-61] Micro SD + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0 0 0 0 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0xe 0xe 0xe 0xe + 0xe 0xe 0 >; + + cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { + marvell,pins = < 47 >; + marvell,function = <0>; + }; + + cps_1g_phy_reset: cps-1g-phy-reset { + marvell,pins = < 43 >; + marvell,function = <0>; + }; +}; + +/* uSD slot */ +&cpm_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_sdhci_pins>; + bus-width = <4>; + status = "okay"; +}; + +&cpm_pcie0 { + num-lanes = <1>; + status = "okay"; +}; + +&cpm_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cpm_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&cpm_sata0 { + status = "okay"; +}; + +&cpm_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0: PCIe0 (x1) + * Lane 1: Not connected + * Lane 2: SFI (10G) + * Lane 3: Not connected + * Lane 4: USB 3.0 host port1 (can be PCIe) + * Lane 5: Not connected + */ + phy0 { + phy-type = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + }; + phy4 { + phy-type = ; + }; + phy5 { + phy-type = ; + }; +}; + +&cpm_ethernet { + pinctrl-names = "default"; + status = "okay"; +}; + +/* 10G SFI SFP */ +&cpm_eth0 { + status = "okay"; + phy-mode = "sfi"; +}; + +&cps_sata0 { + status = "okay"; +}; + +&cps_usb3_0 { + vbus-supply = <®_usb3h0_vbus>; + status = "okay"; +}; + +&cps_utmi0 { + status = "okay"; +}; + +&cps_pinctl { + /* + * MPP Bus: + * [0-5] TDM + * [6] VHV Enable + * [7] CP1 SPI0 CSn1 (FXS) + * [8] CP1 SPI0 CSn0 (TPM) + * [9.11]CP1 SPI0 MOSI/MISO/CLK + * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) + * [14] CP1 SPI1 CS0n (64Mb SPI ROM) + * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) + * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) + * [24] Topaz switch reset + * [26] Buzzer + * [27] CP1 SMI MDIO + * [28] CP1 SMI MDC + * [29] CP0 10G SFP TX Disable + * [30] WPS button + * [31] Front panel button + * [32-62] = 0xff: Keep default CP1_shared_pins: + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x4 0x4 0x4 + 0x4 0x4 0x0 0x3 0x3 0x3 0x3 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x8 0x8 0x0 + 0x0 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; +}; + +&cps_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_spi1_pins>; + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor", "spi-flash"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +&cps_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: SATA 1 (RX swapped). Can be PCIe0 + * Lane 1: Not used + * Lane 2: USB HOST 0 + * Lane 3: SGMII1 - Connected to 1512 port + * Lane 4: Not used + * Lane 5: SGMII2 - Connected to Topaz switch + */ + phy0 { + phy-type = ; + phy-invert = ; + }; + phy1 { + phy-type = ; + }; + phy2 { + phy-type = ; + }; + phy3 { + phy-type = ; + phy-speed = ; + }; + phy4 { + phy-type = ; + }; + phy5 { + phy-type = ; + phy-speed = ; + }; +}; + +&cps_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cps_ethernet { + pinctrl-names = "default"; + pinctrl-0 = <&cps_1g_phy_reset>; + status = "okay"; +}; + +/* 1G SGMII */ +&cps_eth1 { + status = "okay"; + phy-mode = "sgmii"; + phy = <&phy0>; + phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>; +}; + +/* 2.5G to Topaz switch */ +&cps_eth2 { + status = "okay"; + phy-mode = "sgmii"; + phy-speed = <2500>; + phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index f912596c2c..7e8e2f707c 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -154,6 +154,12 @@ status = "okay"; }; +&cpm_mdio { + ge_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + &cpm_comphy { /* * CP0 Serdes Configuration: @@ -197,6 +203,16 @@ status = "okay"; }; +&cps_ethernet { + status = "okay"; +}; + +&cps_eth1 { + status = "okay"; + phy = <&ge_phy>; + phy-mode = "sgmii"; +}; + &cps_pinctl { /* * MPP Bus: diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index 723941ac0b..ebf44fd707 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -11,6 +11,11 @@ chosen { stdout-path = &uart5; }; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + }; }; &uart5 { @@ -36,3 +41,21 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>; +}; + +&mac1 { + status = "okay"; + + phy-mode = "rgmii"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; +}; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 7e0ad3a41a..98359bf924 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -11,6 +11,29 @@ #size-cells = <1>; interrupt-parent = <&vic>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,12 +45,80 @@ }; }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: flash-controller@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: flash-controller@1e631000 { + reg = < 0x1e631000 0xc4 + 0x38000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; @@ -37,18 +128,38 @@ }; mac0: ethernet@1e660000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; - no-hw-checksum; status = "disabled"; }; mac1: ethernet@1e680000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; - no-hw-checksum; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <5>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = <13>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2500-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <14>; + #ports = <2>; status = "disabled"; }; @@ -58,853 +169,24 @@ #size-cells = <1>; ranges; - clk_clkin: clk_clkin@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock"; - reg = <0x1e6e2070 0x04>; - }; - syscon: syscon@1e6e2000 { compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,g5-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; - pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; - - pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; - - pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; - - pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; - - pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; - - pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; - - pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; - - pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; - - pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; - - pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; - - pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; - - pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; - - pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; - - pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; - - pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; - - pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; - - pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; - - pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; - - pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; - - pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; - - pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; - - pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; - - pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; - - pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; - - pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; - }; - - pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; - }; - - pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; - }; - - pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; - }; - - pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; - }; - - pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; - - pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; - - pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; - - pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; - - pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; - - pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; - - pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; - - pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; - - pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; - - pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; - - pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; - - pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; - - pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; - - pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; - - pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; - - pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; - - pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; - - pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; - - pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; - - pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; - - pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; - - pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; - - pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; - - pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; - - pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; - - pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; - - pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; - - pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; - - pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; - - pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; - - pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; - - pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; - - pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; - - pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; - - pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; - - pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; - - pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; - - pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; - - pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; - - pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; - - pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; - - pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; - - pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; - - pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; - - pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; - - pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; - - pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; - - pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; - - pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; - - pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; - - pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; - - pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; - - pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; - - pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; - - pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; - - pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; - - pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; - - pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; - - pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; - - pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; - - pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; - - pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; - - pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; - - pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; - - pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; - - pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; - - pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; - - pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; - - pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; - - pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; - - pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; - - pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; - - pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; - - pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; - - pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; - - pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; - - pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; - - pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; - - pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; - - pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; - - pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; - - pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; - - pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; - - pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; - - pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; - - pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; - - pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; - - pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; - - pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; - - pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; - - pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; - - pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; - - pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; - - pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; - - pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; - - pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; - - pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; - - pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; - - pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; - - pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; - - pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; - - pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; - - pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; - - pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; - - pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; - - pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; - - pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; - - pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; - - pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; - - pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; - - pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; - - pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; - - pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; - - pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; - - pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; - - pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; - - pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; - - pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; - - pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; - - pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; - - pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; - - pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; - - pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; - - pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; - - pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; - - pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; - - pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; - - pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; - - pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; - }; }; - clk_hpll: clk_hpll@1e6e2024 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock"; - reg = <0x1e6e2024 0x4>; - clocks = <&clk_clkin>; - }; - - clk_ahb: clk_ahb@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_hpll>; - }; - - clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; - - clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; + rng: hwrng@1e6e2078 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2078 0x4>; + period = <1>; + quality = <100>; }; gfx: display@1e6e6000 { @@ -913,6 +195,13 @@ reg-io-width = <4>; }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x9000>; // 36K @@ -929,41 +218,61 @@ }; timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; - clocks = <&clk_apb>; }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + no-loopback-test; + status = "disabled"; + }; - wdt1: wdt@1e785000 { + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + no-loopback-test; + status = "disabled"; + }; + + wdt1: watchdog@1e785000 { compatible = "aspeed,wdt"; reg = <0x1e785000 0x1c>; interrupts = <27>; }; - wdt2: wdt@1e785020 { + wdt2: watchdog@1e785020 { compatible = "aspeed,wdt"; reg = <0x1e785020 0x1c>; interrupts = <27>; status = "disabled"; }; - wdt3: wdt@1e785040 { + wdt3: watchdog@1e785040 { compatible = "aspeed,wdt"; - reg = <0x1e785074 0x1c>; + reg = <0x1e785040 0x1c>; status = "disabled"; }; - uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + status = "disabled"; + }; + + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; + interrupts = <8>; no-loopback-test; status = "disabled"; }; @@ -974,7 +283,7 @@ #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + ranges = <0x0 0x1e789000 0x1000>; lpc_bmc: lpc-bmc@0 { compatible = "aspeed,ast2500-lpc-bmc"; @@ -984,70 +293,1118 @@ lpc_host: lpc-host@80 { compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; reg = <0x80 0x1e0>; + reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x80 0x1e0>; + ranges = <0x0 0x80 0x1e0>; - reg-io-width = <4>; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2500-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <8>; + status = "disabled"; + }; lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; + }; }; }; uart2: serial@1e78d000 { compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; + reg = <0x1e78d000 0x20>; reg-shift = <2>; interrupts = <32>; - clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; uart3: serial@1e78e000 { compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; + reg = <0x1e78e000 0x20>; reg-shift = <2>; interrupts = <33>; - clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; uart4: serial@1e78f000 { compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; + reg = <0x1e78f000 0x20>; reg-shift = <2>; interrupts = <34>; - clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; - uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; - - uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; }; }; }; }; + +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + }; + + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + }; + + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +}; + +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; + + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; + + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; + + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; + + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; + + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; + + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; + + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; + + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; + + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; + + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; + + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; + + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; + + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; + + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; + + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; + + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; + + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; + + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; + + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; + + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; + + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; + + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; + + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; + + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; + + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; + + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; + + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; + + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; + + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; + + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; + + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USB2AH"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USB11BHID"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USB2BH"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; +}; diff --git a/arch/arm/dts/at91sam9260-smartweb.dts b/arch/arm/dts/at91sam9260-smartweb.dts index e59781bf45..a22de2d927 100644 --- a/arch/arm/dts/at91sam9260-smartweb.dts +++ b/arch/arm/dts/at91sam9260-smartweb.dts @@ -89,6 +89,7 @@ }; watchdog@fffffd40 { + timeout-sec = <15>; status = "okay"; }; diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts index 7931c0af7b..cee228bb8c 100644 --- a/arch/arm/dts/at91sam9g20-taurus.dts +++ b/arch/arm/dts/at91sam9g20-taurus.dts @@ -98,6 +98,7 @@ }; watchdog@fffffd40 { + timeout-sec = <15>; status = "okay"; }; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi new file mode 100644 index 0000000000..d78d34d213 --- /dev/null +++ b/arch/arm/dts/bcm6858.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm6858"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + uart0: serial@ff800640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x0 0xff800640 0x0 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts new file mode 100644 index 0000000000..0c59f94710 --- /dev/null +++ b/arch/arm/dts/bcm968580xref.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +/dts-v1/; + +#include "bcm6858.dtsi" + +/ { + model = "Broadcom bcm68580xref"; + compatible = "broadcom,bcm68580xref", "brcm,bcm6858"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts index 0e82bb988f..a3c9b34672 100644 --- a/arch/arm/dts/da850-evm.dts +++ b/arch/arm/dts/da850-evm.dts @@ -27,6 +27,65 @@ spi0 = &spi1; }; + backlight: backlight-pwm { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + power-supply = <&backlight_lcd>; + compatible = "pwm-backlight"; + /* + * The PWM here corresponds to production hardware. The + * schematic needs to be 1015171 (15 March 2010), Rev A + * or newer. + */ + pwms = <&ecap2 0 50000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; + default-brightness-level = <7>; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, change the status below to 'disabled' then + * then change the status of the vpif below to 'okay' + */ + status = "okay"; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + + display-timings { + native-mode = <&timing0>; + timing0: 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <4>; + vsync-len = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -35,6 +94,15 @@ regulator-boot-on; }; + backlight_lcd: backlight-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ + enable-active-high; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "DA850/OMAP-L138 EVM"; @@ -63,6 +131,14 @@ }; }; +&ecap2 { + status = "okay"; +}; + +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -93,6 +169,10 @@ }; }; +&sata { + status = "okay"; +}; + &serial0 { status = "okay"; }; @@ -109,6 +189,10 @@ status = "okay"; }; +&lcdc { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <100000>; @@ -137,6 +221,12 @@ gpio-controller; #gpio-cells = <2>; }; + tca6416_bb: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; }; &wdt { @@ -336,5 +426,10 @@ &vpif { pinctrl-names = "default"; pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - status = "okay"; + /* + * The vpif and the LCD are mutually exclusive. + * To enable VPIF, disable the ti,tilcdc,panel then + * change the status below to 'okay' + */ + status = "disabled"; }; diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts index a1f4d6d5a5..0177e3ed20 100644 --- a/arch/arm/dts/da850-lcdk.dts +++ b/arch/arm/dts/da850-lcdk.dts @@ -21,8 +21,8 @@ stdout-path = "serial2:115200n8"; }; - memory { - device_type = "memory"; + memory@c0000000 { + /* 128 MB DDR2 SDRAM @ 0xc0000000 */ reg = <0xc0000000 0x08000000>; }; @@ -123,6 +123,10 @@ }; }; +&ref_clk { + clock-frequency = <24000000>; +}; + &pmx_core { status = "okay"; @@ -175,6 +179,11 @@ status = "okay"; }; +&sata_refclk { + status = "okay"; + clock-frequency = <100000000>; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi index c66cf78953..47aa53ba6b 100644 --- a/arch/arm/dts/da850.dtsi +++ b/arch/arm/dts/da850.dtsi @@ -7,10 +7,19 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include "skeleton.dtsi" #include / { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x0>; + }; + arm { #address-cells = <1>; #size-cells = <1>; @@ -23,6 +32,25 @@ reg = <0xfffee000 0x2000>; }; }; + clocks: clocks { + ref_clk: ref_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref_clk"; + }; + sata_refclk: sata_refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sata_refclk"; + status = "disabled"; + }; + usb_refclkin: usb_refclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "usb_refclkin"; + status = "disabled"; + }; + }; dsp: dsp@11800000 { compatible = "ti,da850-dsp"; reg = <0x11800000 0x40000>, @@ -33,6 +61,8 @@ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; interrupt-parent = <&intc>; interrupts = <28>; + clocks = <&psc0 15>; + resets = <&psc0 15>; status = "disabled"; }; soc@1c00000 { @@ -43,17 +73,57 @@ ranges = <0x0 0x01c00000 0x400000>; interrupt-parent = <&intc>; + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, + <&pll0_sysclk 4>, <&pll0_sysclk 6>, + <&async1_clk>; + clock-names = "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", + "async1"; + }; + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>, <&pll1_sysclk 3>; + clock-names = "clksrc", "extclksrc"; + + pll0_pllout: pllout { + #clock-cells = <0>; + }; + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + pll0_auxclk: auxclk { + #clock-cells = <0>; + }; + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; pmx_core: pinmux@14120 { compatible = "pinctrl-single"; reg = <0x14120 0x50>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <2>; pinctrl-single,bit-per-mux; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 17 0x8>, + <&range 17 8 0x4>, + <&range 26 8 0x4>, + <&range 34 80 0x8>, + <&range 129 31 0x8>; status = "disabled"; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + serial0_rtscts_pins: pinmux_serial0_rtscts_pins { pinctrl-single,bits = < /* UART0_RTS UART0_CTS */ @@ -264,8 +334,41 @@ usb_phy: usb-phy { compatible = "ti,da830-usb-phy"; #phy-cells = <1>; + clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; + clock-names = "usb0_clk48", "usb1_clk48"; status = "disabled"; }; + usb_phy_clk: usb-phy-clocks { + compatible = "ti,da830-usb-phy-clocks"; + #clock-cells = <1>; + clocks = <&psc1 1>, <&usb_refclkin>, + <&pll0_auxclk>; + clock-names = "fck", "usb_refclkin", "auxclk"; + }; + ehrpwm_tbclk: ehrpwm_tbclk { + compatible = "ti,da830-tbclksync"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-names = "fck"; + }; + div4p5_clk: div4.5 { + compatible = "ti,da830-div4p5ena"; + #clock-cells = <0>; + clocks = <&pll0_pllout>; + clock-names = "pll0_pllout"; + }; + async1_clk: async1 { + compatible = "ti,da850-async1-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 3>, <&div4p5_clk>; + clock-names = "pll0_sysclk3", "div4.5"; + }; + async3_clk: async3 { + compatible = "ti,da850-async3-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + }; }; edma0: edma@0 { compatible = "ti,edma3-tpcc"; @@ -277,18 +380,21 @@ #dma-cells = <2>; ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + power-domains = <&psc0 0>; }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc0 2>; }; edma1: edma@230000 { compatible = "ti,edma3-tpcc"; @@ -300,12 +406,14 @@ #dma-cells = <2>; ti,tptcs = <&edma1_tptc0 7>; + power-domains = <&psc1 0>; }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; + power-domains = <&psc1 21>; }; serial0: serial@42000 { compatible = "ti,da830-uart", "ns16550a"; @@ -313,6 +421,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <25>; + clocks = <&psc0 9>; + power-domains = <&psc0 9>; status = "disabled"; }; serial1: serial@10c000 { @@ -321,6 +431,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <53>; + clocks = <&psc1 12>; + power-domains = <&psc1 12>; status = "disabled"; }; serial2: serial@10d000 { @@ -329,6 +441,8 @@ reg-io-width = <4>; reg-shift = <2>; interrupts = <61>; + clocks = <&psc1 13>; + power-domains = <&psc1 13>; status = "disabled"; }; rtc0: rtc@23000 { @@ -336,6 +450,8 @@ reg = <0x23000 0x1000>; interrupts = <19 19>; + clocks = <&pll0_auxclk>; + clock-names = "int-clk"; status = "disabled"; }; i2c0: i2c@22000 { @@ -344,6 +460,7 @@ interrupts = <15>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pll0_auxclk>; status = "disabled"; }; i2c1: i2c@228000 { @@ -352,11 +469,21 @@ interrupts = <51>; #address-cells = <1>; #size-cells = <0>; + clocks = <&psc1 11>; + power-domains = <&psc1 11>; status = "disabled"; }; + clocksource: timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <12>, <13>; + interrupt-names = "tint12", "tint34"; + clocks = <&pll0_auxclk>; + }; wdt: wdt@21000 { compatible = "ti,davinci-wdt"; reg = <0x21000 0x1000>; + clocks = <&pll0_auxclk>; status = "disabled"; }; mmc0: mmc@40000 { @@ -367,12 +494,14 @@ interrupts = <16>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; + clocks = <&psc0 5>; status = "disabled"; }; vpif: video@217000 { compatible = "ti,da850-vpif"; reg = <0x217000 0x1000>; interrupts = <92>; + power-domains = <&psc1 9>; status = "disabled"; /* VPIF capture port */ @@ -395,6 +524,7 @@ interrupts = <72>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; + clocks = <&psc1 18>; status = "disabled"; }; ehrpwm0: pwm@300000 { @@ -402,6 +532,9 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ehrpwm1: pwm@302000 { @@ -409,6 +542,9 @@ "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; + clocks = <&psc1 17>, <&ehrpwm_tbclk>; + clock-names = "fck", "tbclk"; + power-domains = <&psc1 17>; status = "disabled"; }; ecap0: ecap@306000 { @@ -416,6 +552,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap1: ecap@307000 { @@ -423,6 +562,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; ecap2: ecap@308000 { @@ -430,6 +572,9 @@ "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; + clocks = <&psc1 20>; + clock-names = "fck"; + power-domains = <&psc1 20>; status = "disabled"; }; spi0: spi@41000 { @@ -442,6 +587,8 @@ interrupts = <20>; dmas = <&edma0 14 0>, <&edma0 15 0>; dma-names = "rx", "tx"; + clocks = <&psc0 4>; + power-domains = <&psc0 4>; status = "disabled"; }; spi1: spi@30e000 { @@ -454,6 +601,8 @@ interrupts = <56>; dmas = <&edma0 18 0>, <&edma0 19 0>; dma-names = "rx", "tx"; + clocks = <&psc1 10>; + power-domains = <&psc1 10>; status = "disabled"; }; usb0: usb@200000 { @@ -465,6 +614,8 @@ dr_mode = "otg"; phys = <&usb_phy 0>; phy-names = "usb-phy"; + clocks = <&psc1 1>; + clock-ranges; status = "disabled"; #address-cells = <1>; @@ -488,6 +639,7 @@ interrupts = <58>; #dma-cells = <2>; #dma-channels = <4>; + power-domains = <&psc1 1>; status = "okay"; }; }; @@ -495,13 +647,31 @@ compatible = "ti,da850-ahci"; reg = <0x218000 0x2000>, <0x22c018 0x4>; interrupts = <67>; + clocks = <&psc1 8>, <&sata_refclk>; + clock-names = "fck", "refclk"; status = "disabled"; }; + pll1: clock-controller@21a000 { + compatible = "ti,da850-pll1"; + reg = <0x21a000 0x1000>; + clocks = <&ref_clk>; + clock-names = "clksrc"; + + pll1_sysclk: sysclk { + #clock-cells = <1>; + }; + pll1_obsclk: obsclk { + #clock-cells = <0>; + }; + }; mdio: mdio@224000 { compatible = "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x224000 0x1000>; + clocks = <&psc1 5>; + clock-names = "fck"; + power-domains = <&psc1 5>; status = "disabled"; }; eth0: ethernet@220000 { @@ -517,6 +687,8 @@ 35 36 >; + clocks = <&psc1 5>; + power-domains = <&psc1 5>; status = "disabled"; }; usb1: usb@225000 { @@ -525,6 +697,7 @@ interrupts = <59>; phys = <&usb_phy 1>; phy-names = "usb-phy"; + clocks = <&psc1 2>; status = "disabled"; }; gpio: gpio@226000 { @@ -532,16 +705,169 @@ gpio-controller; #gpio-cells = <2>; reg = <0x226000 0x1000>; - interrupts = <42 IRQ_TYPE_EDGE_BOTH - 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH - 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH - 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH - 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; + interrupts = <42 43 44 45 46 47 48 49 50>; ti,ngpio = <144>; ti,davinci-gpio-unbanked = <0>; + clocks = <&psc1 3>; + clock-names = "gpio"; status = "disabled"; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx_core 0 15 1>, + <&pmx_core 1 14 1>, + <&pmx_core 2 13 1>, + <&pmx_core 3 12 1>, + <&pmx_core 4 11 1>, + <&pmx_core 5 10 1>, + <&pmx_core 6 9 1>, + <&pmx_core 7 8 1>, + <&pmx_core 8 7 1>, + <&pmx_core 9 6 1>, + <&pmx_core 10 5 1>, + <&pmx_core 11 4 1>, + <&pmx_core 12 3 1>, + <&pmx_core 13 2 1>, + <&pmx_core 14 1 1>, + <&pmx_core 15 0 1>, + <&pmx_core 16 39 1>, + <&pmx_core 17 38 1>, + <&pmx_core 18 37 1>, + <&pmx_core 19 36 1>, + <&pmx_core 20 35 1>, + <&pmx_core 21 34 1>, + <&pmx_core 22 33 1>, + <&pmx_core 23 32 1>, + <&pmx_core 24 24 1>, + <&pmx_core 25 22 1>, + <&pmx_core 26 21 1>, + <&pmx_core 27 20 1>, + <&pmx_core 28 19 1>, + <&pmx_core 29 18 1>, + <&pmx_core 30 17 1>, + <&pmx_core 31 16 1>, + <&pmx_core 32 55 1>, + <&pmx_core 33 54 1>, + <&pmx_core 34 53 1>, + <&pmx_core 35 52 1>, + <&pmx_core 36 51 1>, + <&pmx_core 37 50 1>, + <&pmx_core 38 49 1>, + <&pmx_core 39 48 1>, + <&pmx_core 40 47 1>, + <&pmx_core 41 46 1>, + <&pmx_core 42 45 1>, + <&pmx_core 43 44 1>, + <&pmx_core 44 43 1>, + <&pmx_core 45 42 1>, + <&pmx_core 46 41 1>, + <&pmx_core 47 40 1>, + <&pmx_core 48 71 1>, + <&pmx_core 49 70 1>, + <&pmx_core 50 69 1>, + <&pmx_core 51 68 1>, + <&pmx_core 52 67 1>, + <&pmx_core 53 66 1>, + <&pmx_core 54 65 1>, + <&pmx_core 55 64 1>, + <&pmx_core 56 63 1>, + <&pmx_core 57 62 1>, + <&pmx_core 58 61 1>, + <&pmx_core 59 60 1>, + <&pmx_core 60 59 1>, + <&pmx_core 61 58 1>, + <&pmx_core 62 57 1>, + <&pmx_core 63 56 1>, + <&pmx_core 64 87 1>, + <&pmx_core 65 86 1>, + <&pmx_core 66 85 1>, + <&pmx_core 67 84 1>, + <&pmx_core 68 83 1>, + <&pmx_core 69 82 1>, + <&pmx_core 70 81 1>, + <&pmx_core 71 80 1>, + <&pmx_core 72 70 1>, + <&pmx_core 73 78 1>, + <&pmx_core 74 77 1>, + <&pmx_core 75 76 1>, + <&pmx_core 76 75 1>, + <&pmx_core 77 74 1>, + <&pmx_core 78 73 1>, + <&pmx_core 79 72 1>, + <&pmx_core 80 103 1>, + <&pmx_core 81 102 1>, + <&pmx_core 82 101 1>, + <&pmx_core 83 100 1>, + <&pmx_core 84 99 1>, + <&pmx_core 85 98 1>, + <&pmx_core 86 97 1>, + <&pmx_core 87 96 1>, + <&pmx_core 88 95 1>, + <&pmx_core 89 94 1>, + <&pmx_core 90 93 1>, + <&pmx_core 91 92 1>, + <&pmx_core 92 91 1>, + <&pmx_core 93 90 1>, + <&pmx_core 94 89 1>, + <&pmx_core 95 88 1>, + <&pmx_core 96 158 1>, + <&pmx_core 97 157 1>, + <&pmx_core 98 156 1>, + <&pmx_core 99 155 1>, + <&pmx_core 100 154 1>, + <&pmx_core 101 129 1>, + <&pmx_core 102 113 1>, + <&pmx_core 103 112 1>, + <&pmx_core 104 111 1>, + <&pmx_core 105 110 1>, + <&pmx_core 106 109 1>, + <&pmx_core 107 108 1>, + <&pmx_core 108 107 1>, + <&pmx_core 109 106 1>, + <&pmx_core 110 105 1>, + <&pmx_core 111 104 1>, + <&pmx_core 112 145 1>, + <&pmx_core 113 144 1>, + <&pmx_core 114 143 1>, + <&pmx_core 115 142 1>, + <&pmx_core 116 141 1>, + <&pmx_core 117 140 1>, + <&pmx_core 118 139 1>, + <&pmx_core 119 138 1>, + <&pmx_core 120 137 1>, + <&pmx_core 121 136 1>, + <&pmx_core 122 135 1>, + <&pmx_core 123 134 1>, + <&pmx_core 124 133 1>, + <&pmx_core 125 132 1>, + <&pmx_core 126 131 1>, + <&pmx_core 127 130 1>, + <&pmx_core 128 159 1>, + <&pmx_core 129 31 1>, + <&pmx_core 130 30 1>, + <&pmx_core 131 20 1>, + <&pmx_core 132 28 1>, + <&pmx_core 133 27 1>, + <&pmx_core 134 26 1>, + <&pmx_core 135 23 1>, + <&pmx_core 136 153 1>, + <&pmx_core 137 152 1>, + <&pmx_core 138 151 1>, + <&pmx_core 139 150 1>, + <&pmx_core 140 149 1>, + <&pmx_core 141 148 1>, + <&pmx_core 142 147 1>, + <&pmx_core 143 146 1>; + }; + psc1: clock-controller@227000 { + compatible = "ti,da850-psc1"; + reg = <0x227000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, + <&async3_clk>; + clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; }; pinconf: pin-controller@22c00c { compatible = "ti,da850-pupd"; @@ -556,6 +882,7 @@ reg-names = "mpu", "dat"; interrupts = <54>; interrupt-names = "common"; + power-domains = <&psc1 7>; status = "disabled"; dmas = <&edma0 1 1>, <&edma0 0 1>; @@ -567,6 +894,9 @@ reg = <0x213000 0x1000>; interrupts = <52>; max-pixelclock = <37500>; + clocks = <&psc1 16>; + clock-names = "fck"; + power-domains = <&psc1 16>; status = "disabled"; }; }; @@ -578,6 +908,9 @@ reg = <0x68000000 0x00008000>; ranges = <0 0 0x60000000 0x08000000 1 0 0x68000000 0x00008000>; + clocks = <&psc0 3>; + clock-names = "aemif"; + clock-ranges; status = "disabled"; }; memctrl: memory-controller@b0000000 { diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi index 276211e1ee..fe58faf2f7 100644 --- a/arch/arm/dts/dm816x.dtsi +++ b/arch/arm/dts/dm816x.dtsi @@ -90,8 +90,6 @@ dm816x_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xf>; @@ -127,8 +125,6 @@ }; scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; }; scrm_clockdomains: clockdomains { diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index 8b695442b1..e542a79076 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -60,9 +60,26 @@ }; i2c@12C70000 { - soundcodec@1a { + wm8994: soundcodec@1a { reg = <0x1a>; - compatible = "wolfson,wm8994-codec"; + u-boot,i2c-offset-len = <2>; + compatible = "wolfson,wm8994"; + #sound-dai-cells = <1>; + }; + }; + + sound { + compatible = "google,smdk5250-audio-wm8994"; + + samsung,model = "SMDK5250-I2S-WM8994"; + samsung,audio-codec = <&wm8994>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&wm8994 0>; }; }; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 29c13c1257..7587dc0ff2 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -40,7 +40,6 @@ mmc3 = "/mmc@12230000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; - i2s = "/sound@3830000"; }; memory { @@ -88,7 +87,7 @@ ro-boot { label = "u-boot"; - reg = <0x6000 0x9a000>; + reg = <0x6000 0xb0000>; read-only; type = "blob boot,dtb"; required; @@ -214,9 +213,10 @@ }; }; - soundcodec@22 { - reg = <0x22>; - compatible = "maxim,max98095-codec"; + max98095: codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + #sound-dai-cells = <1>; }; }; @@ -273,9 +273,20 @@ }; }; - sound@3830000 { - samsung,codec-type = "max98095"; + sound { + compatible = "google,snow-audio-max98095"; + + samsung,model = "Snow-I2S-MAX98095"; + samsung,audio-codec = <&max98095>; codec-enable-gpio = <&gpx1 7 GPIO_ACTIVE_HIGH>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98095 0>; + }; }; sound@12d60000 { diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index 7633d36874..191e12af6a 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -34,7 +34,6 @@ mmc0 = "/mmc@12200000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; - i2s = "/sound@3830000"; }; memory { @@ -639,10 +638,27 @@ }; }; - soundcodec@20 { - reg = <0x20>; - compatible = "maxim,max98088-codec"; + max98095: soundcodec@10 { + reg = <0x10>; + compatible = "maxim,max98095"; + #sound-dai-cells = <1>; }; + + sound { + compatible = "google,spring-audio-max98095"; + + samsung,model = "Spring-I2S-MAX98095"; + samsung,audio-codec = <&max98095>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98095 0>; + }; + }; + }; #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 502c687802..66c5b6dca9 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -78,9 +78,12 @@ #size-cells = <0>; }; - sound@3830000 { - compatible = "samsung,exynos-sound"; - reg = <0x3830000 0x50>; + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + samsung,idma-addr = <0x03000000>; + #clock-cells = <1>; + #sound-dai-cells = <1>; samsung,i2s-epll-clock-frequency = <192000000>; samsung,i2s-sampling-rate = <48000>; samsung,i2s-bits-per-sample = <16>; @@ -90,9 +93,11 @@ samsung,i2s-id = <0>; }; - sound@12d60000 { - compatible = "samsung,exynos-sound"; + i2s1: i2s@12d60000 { + compatible = "samsung,s5pv210-i2s"; reg = <0x12d60000 0x20>; + #clock-cells = <1>; + #sound-dai-cells = <1>; samsung,i2s-epll-clock-frequency = <192000000>; samsung,i2s-sampling-rate = <48000>; samsung,i2s-bits-per-sample = <16>; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index c86f9d9035..4a96a18110 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -67,12 +67,28 @@ }; }; + sound { + compatible = "google,peach-audio-max98090"; + + samsung,model = "PEACH-I2S-MAX98090"; + samsung,audio-codec = <&max98090>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; + i2c@12CD0000 { /* i2c7 */ clock-frequency = <100000>; - soundcodec@20 { - reg = <0x20>; - compatible = "maxim,max98090-codec"; - }; + max98090: soundcodec@10 { + reg = <0x10>; + compatible = "maxim,max98090"; + #sound-dai-cells = <1>; + }; edp-lvds-bridge@48 { compatible = "parade,ps8625"; diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index cab5ddb61f..7a5da674fb 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -82,9 +82,26 @@ }; i2c@12C70000 { - soundcodec@1a { + wm8994: soundcodec@1a { reg = <0x1a>; - compatible = "wolfson,wm8994-codec"; + u-boot,i2c-offset-len = <2>; + compatible = "wolfson,wm8994"; + #sound-dai-cells = <1>; + }; + }; + + sound { + compatible = "samsung,smdk5420-audio-wm8994"; + + samsung,model = "Snow-I2S-MAX98095"; + samsung,audio-codec = <&wm8994>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&wm8994 0>; }; }; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 09bef56e6c..221da8b485 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -104,6 +104,20 @@ interrupts = <0 203 0>; }; + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + #sound-dai-cells = <1>; + samsung,idma-addr = <0x03000000>; + samsung,i2s-epll-clock-frequency = <192000000>; + samsung,i2s-sampling-rate = <48000>; + samsung,i2s-bits-per-sample = <16>; + samsung,i2s-channels = <2>; + samsung,i2s-lr-clk-framesize = <256>; + samsung,i2s-bit-clk-framesize = <32>; + samsung,i2s-id = <0>; + }; + mmc@12200000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 7498519d6c..63c0b186e4 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -79,12 +79,28 @@ }; }; + sound { + compatible = "google,peach-audio-max98090"; + + samsung,model = "PEACH-I2S-MAX98090"; + samsung,audio-codec = <&max98090>; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; + i2c@12CD0000 { /* i2c7 */ clock-frequency = <100000>; - soundcodec@20 { - reg = <0x20>; - compatible = "maxim,max98090-codec"; - }; + max98090: soundcodec@10 { + reg = <0x10>; + compatible = "maxim,max98090"; + #sound-dai-cells = <1>; + }; }; sound@3830000 { diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts new file mode 100644 index 0000000000..4a08099b3c --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index ba36853b1b..ada8a859b1 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -76,3 +76,7 @@ &lpuart0 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 136de245f3..ba30fd262a 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -39,3 +39,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 7687d12091..5ac10e05d7 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -291,5 +291,13 @@ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1046a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 4>; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 36116f7944..4ea451c1b6 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -104,3 +104,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 0be3f8d025..f30bbb7247 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -37,3 +37,7 @@ reg = <1>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 72d755a18c..9455e03466 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -150,4 +150,12 @@ ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1088a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + status = "disabled"; + }; + }; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index fbd6c78e9f..39fbc1b79c 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -64,3 +64,7 @@ reg = <0>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 541bcd37a0..e7567cfa23 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -32,3 +32,7 @@ reg = <0>; }; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 2d537ae606..5c0769bc99 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -156,4 +156,12 @@ ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 0x4>; /* Level high type */ + status = "disabled"; + }; + }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000000..b407dc6e13 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi b/arch/arm/dts/hi3798cv200-u-boot.dtsi index 709ae1cbc9..7844c5208c 100644 --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi @@ -17,12 +17,6 @@ }; &uart0 { - status = "disabled"; + clock = <75000000>; + status = "okay"; }; - -/{ - chosen { - stdout-path = ""; - }; -}; - diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 2409344df4..adcd6341e4 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -8,13 +8,13 @@ &cbass_main { gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x01800000 0x10000>, /* GICD */ - <0x01880000 0x90000>; /* GICR */ + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0x90000>; /* GICR */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt @@ -23,9 +23,50 @@ gic_its: gic-its@18200000 { compatible = "arm,gic-v3-its"; - reg = <0x01820000 0x10000>; + reg = <0x00 0x01820000 0x00 0x10000>; msi-controller; #msi-cells = <1>; }; }; + + secure_proxy_main: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x32c00000 0x00 0x100000>, + <0x00 0x32400000 0x00 0x100000>, + <0x00 0x32800000 0x00 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + }; }; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi new file mode 100644 index 0000000000..8c611d16df --- /dev/null +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family MCU Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_mcu { + mcu_uart0: serial@40a00000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; + }; +}; diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi new file mode 100644 index 0000000000..8d7b47f9df --- /dev/null +++ b/arch/arm/dts/k3-am65-wakeup.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_wakeup { + dmsc: dmsc { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,am654-uart"; + reg = <0x42300000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <48000000>; + current-speed = <115200>; + }; +}; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi index cede1fa098..3d4bf369d0 100644 --- a/arch/arm/dts/k3-am65.dtsi +++ b/arch/arm/dts/k3-am65.dtsi @@ -16,6 +16,14 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + }; + chosen { }; firmware { @@ -46,38 +54,38 @@ cbass_main: interconnect@100000 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ - <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ - <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ - <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ - <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ /* MCUSS Range */ - <0x28380000 0x00 0x28380000 0x03880000>, - <0x40200000 0x00 0x40200000 0x00900100>, - <0x42040000 0x00 0x42040000 0x03ac2400>, - <0x45100000 0x00 0x45100000 0x00c24000>, - <0x46000000 0x00 0x46000000 0x00200000>, - <0x47000000 0x00 0x47000000 0x00068400>; + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; cbass_mcu: interconnect@28380000 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ - <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ - <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ - <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x46000000 0x46000000 0x00200000>, /* CPSW */ - <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ + <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */ cbass_wakeup: interconnect@42040000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; /* WKUP Basic peripherals */ - ranges = <0x42040000 0x42040000 0x03ac2400>; + ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; }; }; }; @@ -85,3 +93,5 @@ /* Now include the peripherals for each bus segments */ #include "k3-am65-main.dtsi" +#include "k3-am65-mcu.dtsi" +#include "k3-am65-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi new file mode 100644 index 0000000000..e861cb7c67 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated by the AM65x_DRA80xM EMIF Tool: + * http://www.ti.com/lit/pdf/spracj0 + * Configuration Parameters + * Memory Type: DDR4 + * Data Rate: 1600 + * ECC Enabled: No + * Data Width: 32 + */ +#define DDR_PLL_FREQUENCY 400000000 +#define DDRCTL_MSTR 0x41040010 +#define DDRCTL_RFSHCTL0 0x00210070 +#define DDRCTL_ECCCFG0 0x00000000 +#define DDRCTL_RFSHTMG 0x0061008C +#define DDRCTL_CRCPARCTL0 0x00008000 +#define DDRCTL_CRCPARCTL1 0x1A000000 +#define DDRCTL_CRCPARCTL2 0x0048051E +#define DDRCTL_INIT0 0x400100C4 +#define DDRCTL_INIT1 0x004F0000 +#define DDRCTL_INIT3 0x02140501 +#define DDRCTL_INIT4 0x00000020 +#define DDRCTL_INIT5 0x00100000 +#define DDRCTL_INIT6 0x00000480 +#define DDRCTL_INIT7 0x000004E8 +#define DDRCTL_DRAMTMG0 0x0C0A1B0D +#define DDRCTL_DRAMTMG1 0x00030313 +#define DDRCTL_DRAMTMG2 0x0506050A +#define DDRCTL_DRAMTMG3 0x0000400C +#define DDRCTL_DRAMTMG4 0x06020206 +#define DDRCTL_DRAMTMG5 0x04040302 +#define DDRCTL_DRAMTMG6 0x00000004 +#define DDRCTL_DRAMTMG7 0x00000404 +#define DDRCTL_DRAMTMG8 0x03030C05 +#define DDRCTL_DRAMTMG9 0x00020208 +#define DDRCTL_DRAMTMG10 0x001C180A +#define DDRCTL_DRAMTMG11 0x1106010E +#define DDRCTL_DRAMTMG12 0x00020008 +#define DDRCTL_DRAMTMG13 0x0B100002 +#define DDRCTL_DRAMTMG14 0x00000000 +#define DDRCTL_DRAMTMG15 0x0000003F +#define DDRCTL_DRAMTMG17 0x00500028 +#define DDRCTL_ZQCTL0 0x21000040 +#define DDRCTL_ZQCTL1 0x0202FAF0 +#define DDRCTL_DFITMG0 0x04888206 +#define DDRCTL_DFITMG1 0x000A0606 +#define DDRCTL_DFITMG2 0x00000604 +#define DDRCTL_DFIMISC 0x00000001 +#define DDRCTL_ADDRMAP0 0x001F1F1F +#define DDRCTL_ADDRMAP1 0x003F0808 +#define DDRCTL_ADDRMAP2 0x00000000 +#define DDRCTL_ADDRMAP3 0x00000000 +#define DDRCTL_ADDRMAP4 0x00001F1F +#define DDRCTL_ADDRMAP5 0x08080808 +#define DDRCTL_ADDRMAP6 0x08080808 +#define DDRCTL_ADDRMAP7 0x00000F0F +#define DDRCTL_ADDRMAP8 0x00000A0A +#define DDRCTL_ADDRMAP9 0x00000000 +#define DDRCTL_ADDRMAP10 0x00000000 +#define DDRCTL_ADDRMAP11 0x001F1F00 +#define DDRCTL_DQMAP0 0x00000000 +#define DDRCTL_DQMAP1 0x00000000 +#define DDRCTL_DQMAP4 0x00000000 +#define DDRCTL_DQMAP5 0x00000000 +#define DDRCTL_PWRCTL 0x00000000 +#define DDRCTL_RANKCTL 0x00000000 +#define DDRCTL_ODTCFG 0x0600060C +#define DDRCTL_ODTMAP 0x00000001 +#define DDRPHY_PGCR0 0x07001E00 +#define DDRPHY_PGCR1 0x020046C0 +#define DDRPHY_PGCR2 0x00F0BFE0 +#define DDRPHY_PGCR3 0x55AA0080 +#define DDRPHY_PGCR6 0x00013001 +#define DDRPHY_PTR2 0x00083DEF +#define DDRPHY_PTR3 0x00061A80 +#define DDRPHY_PTR4 0x00000120 +#define DDRPHY_PTR5 0x00027100 +#define DDRPHY_PTR6 0x04000320 +#define DDRPHY_PLLCR0 0x021c4000 +#define DDRPHY_DXCCR 0x00000038 +#define DDRPHY_DSGCR 0x02A0C129 +#define DDRPHY_DCR 0x0000040C +#define DDRPHY_DTPR0 0x041A0B06 +#define DDRPHY_DTPR1 0x28140000 +#define DDRPHY_DTPR2 0x0034E300 +#define DDRPHY_DTPR3 0x02800800 +#define DDRPHY_DTPR4 0x31180805 +#define DDRPHY_DTPR5 0x00250B06 +#define DDRPHY_DTPR6 0x00000505 +#define DDRPHY_ZQCR 0x008A2A58 +#define DDRPHY_ZQ0PR0 0x000077DD +#define DDRPHY_ZQ1PR0 0x000077DD +#define DDRPHY_MR0 0x00000214 +#define DDRPHY_MR1 0x00000501 +#define DDRPHY_MR2 0x00000000 +#define DDRPHY_MR3 0x00000020 +#define DDRPHY_MR4 0x00000000 +#define DDRPHY_MR5 0x00000480 +#define DDRPHY_MR6 0x000004E8 +#define DDRPHY_MR11 0x00000000 +#define DDRPHY_MR12 0x00000000 +#define DDRPHY_MR13 0x00000000 +#define DDRPHY_MR14 0x00000000 +#define DDRPHY_MR22 0x00000000 +#define DDRPHY_VTCR0 0xF3C32028 +#define DDRPHY_DX8SL0PLLCR0 0x021c4000 +#define DDRPHY_DX8SL1PLLCR0 0x021c4000 +#define DDRPHY_DX8SL2PLLCR0 0x021c4000 +#define DDRPHY_DTCR0 0x8000B1C7 +#define DDRPHY_DTCR1 0x00010236 +#define DDRPHY_ACIOCR5 0x04800000 +#define DDRPHY_IOVCR0 0x0F0C0C0C +#define DDRPHY_DX0GCR0 0x00000000 +#define DDRPHY_DX0GCR1 0x00000000 +#define DDRPHY_DX0GCR2 0x00000000 +#define DDRPHY_DX0GCR3 0x00000000 +#define DDRPHY_DX1GCR0 0x00000000 +#define DDRPHY_DX1GCR1 0x00000000 +#define DDRPHY_DX1GCR2 0x00000000 +#define DDRPHY_DX1GCR3 0x00000000 +#define DDRPHY_DX2GCR0 0x40700204 +#define DDRPHY_DX2GCR1 0x00007FFF +#define DDRPHY_DX2GCR2 0x00000000 +#define DDRPHY_DX2GCR3 0xFFC0010B +#define DDRPHY_DX3GCR0 0x40700204 +#define DDRPHY_DX3GCR1 0x00007FFF +#define DDRPHY_DX3GCR2 0x00000000 +#define DDRPHY_DX3GCR3 0xFFC0010B +#define DDRPHY_DX4GCR0 0x40703220 +#define DDRPHY_DX4GCR1 0x55556000 +#define DDRPHY_DX4GCR2 0xAAAA0000 +#define DDRPHY_DX4GCR3 0xFFE18587 +#define DDRPHY_DX0GCR4 0x0E00B03C +#define DDRPHY_DX1GCR4 0x0E00B03C +#define DDRPHY_DX2GCR4 0x0E00B03C +#define DDRPHY_DX3GCR4 0x0E00B03C +#define DDRPHY_DX4GCR4 0x0E00B03C +#define DDRPHY_PGCR5 0x01010004 +#define DDRPHY_DX0GCR5 0x00000049 +#define DDRPHY_DX1GCR5 0x00000049 +#define DDRPHY_DX2GCR5 0x00000049 +#define DDRPHY_DX3GCR5 0x00000049 +#define DDRPHY_DX4GCR5 0x00000049 +#define DDRPHY_DX0GTR0 0x00020002 +#define DDRPHY_DX1GTR0 0x00020002 +#define DDRPHY_DX2GTR0 0x00020002 +#define DDRPHY_DX3GTR0 0x00020002 +#define DDRPHY_DX4GTR0 0x00020002 +#define DDRPHY_ODTCR 0x00010000 +#define DDRPHY_DX8SL0IOCR 0x04800000 +#define DDRPHY_DX8SL1IOCR 0x04800000 +#define DDRPHY_DX8SL2IOCR 0x04800000 +#define DDRPHY_DX8SL0DXCTL2 0x00141830 +#define DDRPHY_DX8SL1DXCTL2 0x00141830 +#define DDRPHY_DX8SL2DXCTL2 0x00141830 diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index d4ecb3be10..143eb6d630 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -17,56 +17,10 @@ &cbass_main{ u-boot,dm-spl; - secure_proxy: secure_proxy@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x32c00000 0x100000>, - <0x32400000 0x100000>, - <0x32800000 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - dmsc: dmsc { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - /* - * In case of rare platforms that does not use am6 as - * system master, use /delete-property/ - */ - ti,system-reboot-controller; - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy 11>, - <&secure_proxy 13>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <1>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - }; - }; main_pmx0: pinmux@11c000 { compatible = "pinctrl-single"; - reg = <0x11c000 0x2e4>; + reg = <0x0 0x11c000 0x0 0x2e4>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; @@ -74,28 +28,16 @@ main_pmx1: pinmux@11c2e8 { compatible = "pinctrl-single"; - reg = <0x11c2e8 0x24>; + reg = <0x0 0x11c2e8 0x0 0x24>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; - main_uart0: serial@2800000 { - compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; - reg = <0x02800000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - status = "disabled"; - u-boot,dm-pre-reloc; - }; - sdhci0: sdhci@04F80000 { compatible = "arasan,sdhci-5.1"; - reg = <0x4F80000 0x1000>, - <0x4F90000 0x400>; + reg = <0x0 0x4F80000 0x0 0x1000>, + <0x0 0x4F90000 0x0 0x400>; clocks = <&k3_clks 47 1>; power-domains = <&k3_pds 47>; max-frequency = <25000000>; @@ -103,8 +45,8 @@ sdhci1: sdhci@04FA0000 { compatible = "arasan,sdhci-5.1"; - reg = <0x4FA0000 0x1000>, - <0x4FB0000 0x400>; + reg = <0x0 0x4FA0000 0x0 0x1000>, + <0x0 0x4FB0000 0x0 0x400>; clocks = <&k3_clks 48 1>; power-domains = <&k3_pds 48>; max-frequency = <25000000>; @@ -112,12 +54,31 @@ }; -&secure_proxy { +&cbass_mcu { + u-boot,dm-spl; + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x4301c000 0x0 0x118>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&secure_proxy_main { u-boot,dm-spl; }; &dmsc { u-boot,dm-spl; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; }; &k3_pds { @@ -141,6 +102,7 @@ AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ >; + u-boot,dm-spl; }; main_mmc0_pins_default: main_mmc0_pins_default { @@ -157,6 +119,7 @@ AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ >; + u-boot,dm-spl; }; main_mmc1_pins_default: main_mmc1_pins_default { @@ -170,6 +133,7 @@ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ >; + u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi new file mode 100644 index 0000000000..964eb173eb --- /dev/null +++ b/arch/arm/dts/k3-am654-ddr.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/ { + memorycontroller: memorycontroller@0298e000 { + compatible = "ti,am654-ddrss"; + reg = <0x0 0x0298e000 0x0 0x200>, + <0x0 0x02980000 0x0 0x4000>, + <0x0 0x02988000 0x0 0x2000>; + reg-names = "ss", "ctl", "phy"; + clocks = <&k3_clks 20 0>; + power-domains = <&k3_pds 20>, + <&k3_pds 244>; + assigned-clocks = <&k3_clks 20 1>; + assigned-clock-rates = ; + u-boot,dm-spl; + + ti,ctl-reg = < + DDRCTL_DFIMISC + DDRCTL_DFITMG0 + DDRCTL_DFITMG1 + DDRCTL_DFITMG2 + DDRCTL_INIT0 + DDRCTL_INIT1 + DDRCTL_INIT3 + DDRCTL_INIT4 + DDRCTL_INIT5 + DDRCTL_INIT6 + DDRCTL_INIT7 + DDRCTL_MSTR + DDRCTL_ODTCFG + DDRCTL_ODTMAP + DDRCTL_RANKCTL + DDRCTL_RFSHCTL0 + DDRCTL_RFSHTMG + DDRCTL_ZQCTL0 + DDRCTL_ZQCTL1 + >; + + ti,ctl-crc = < + DDRCTL_CRCPARCTL0 + DDRCTL_CRCPARCTL1 + DDRCTL_CRCPARCTL2 + >; + + ti,ctl-ecc = < + DDRCTL_ECCCFG0 + >; + + ti,ctl-map = < + DDRCTL_ADDRMAP0 + DDRCTL_ADDRMAP1 + DDRCTL_ADDRMAP2 + DDRCTL_ADDRMAP3 + DDRCTL_ADDRMAP4 + DDRCTL_ADDRMAP5 + DDRCTL_ADDRMAP6 + DDRCTL_ADDRMAP7 + DDRCTL_ADDRMAP8 + DDRCTL_ADDRMAP9 + DDRCTL_ADDRMAP10 + DDRCTL_ADDRMAP11 + DDRCTL_DQMAP0 + DDRCTL_DQMAP1 + DDRCTL_DQMAP4 + DDRCTL_DQMAP5 + >; + + ti,ctl-pwr = < + DDRCTL_PWRCTL + >; + + ti,ctl-timing = < + DDRCTL_DRAMTMG0 + DDRCTL_DRAMTMG1 + DDRCTL_DRAMTMG2 + DDRCTL_DRAMTMG3 + DDRCTL_DRAMTMG4 + DDRCTL_DRAMTMG5 + DDRCTL_DRAMTMG6 + DDRCTL_DRAMTMG7 + DDRCTL_DRAMTMG8 + DDRCTL_DRAMTMG9 + DDRCTL_DRAMTMG11 + DDRCTL_DRAMTMG12 + DDRCTL_DRAMTMG13 + DDRCTL_DRAMTMG14 + DDRCTL_DRAMTMG15 + DDRCTL_DRAMTMG17 + >; + + ti,phy-cfg = < + DDRPHY_DCR + DDRPHY_DSGCR + DDRPHY_DX0GCR0 + DDRPHY_DX0GCR1 + DDRPHY_DX0GCR2 + DDRPHY_DX0GCR3 + DDRPHY_DX0GCR4 + DDRPHY_DX0GCR5 + DDRPHY_DX0GTR0 + DDRPHY_DX1GCR0 + DDRPHY_DX1GCR1 + DDRPHY_DX1GCR2 + DDRPHY_DX1GCR3 + DDRPHY_DX1GCR4 + DDRPHY_DX1GCR5 + DDRPHY_DX1GTR0 + DDRPHY_DX2GCR0 + DDRPHY_DX2GCR1 + DDRPHY_DX2GCR2 + DDRPHY_DX2GCR3 + DDRPHY_DX2GCR4 + DDRPHY_DX2GCR5 + DDRPHY_DX2GTR0 + DDRPHY_DX3GCR0 + DDRPHY_DX3GCR1 + DDRPHY_DX3GCR2 + DDRPHY_DX3GCR3 + DDRPHY_DX3GCR4 + DDRPHY_DX3GCR5 + DDRPHY_DX3GTR0 + DDRPHY_DX4GCR0 + DDRPHY_DX4GCR1 + DDRPHY_DX4GCR2 + DDRPHY_DX4GCR3 + DDRPHY_DX4GCR4 + DDRPHY_DX4GCR5 + DDRPHY_DX4GTR0 + DDRPHY_DX8SL0DXCTL2 + DDRPHY_DX8SL0IOCR + DDRPHY_DX8SL0PLLCR0 + DDRPHY_DX8SL1DXCTL2 + DDRPHY_DX8SL1IOCR + DDRPHY_DX8SL1PLLCR0 + DDRPHY_DX8SL2DXCTL2 + DDRPHY_DX8SL2IOCR + DDRPHY_DX8SL2PLLCR0 + DDRPHY_DXCCR + DDRPHY_ODTCR + DDRPHY_PGCR0 + DDRPHY_PGCR1 + DDRPHY_PGCR2 + DDRPHY_PGCR3 + DDRPHY_PGCR5 + DDRPHY_PGCR6 + >; + + ti,phy-ctl = < + DDRPHY_DTCR0 + DDRPHY_DTCR1 + DDRPHY_MR0 + DDRPHY_MR1 + DDRPHY_MR2 + DDRPHY_MR3 + DDRPHY_MR4 + DDRPHY_MR5 + DDRPHY_MR6 + DDRPHY_MR11 + DDRPHY_MR12 + DDRPHY_MR13 + DDRPHY_MR14 + DDRPHY_MR22 + DDRPHY_PLLCR0 + DDRPHY_VTCR0 + >; + + ti,phy-ioctl = < + DDRPHY_ACIOCR5 + DDRPHY_IOVCR0 + >; + + ti,phy-timing = < + DDRPHY_DTPR0 + DDRPHY_DTPR1 + DDRPHY_DTPR2 + DDRPHY_DTPR3 + DDRPHY_DTPR4 + DDRPHY_DTPR5 + DDRPHY_DTPR6 + DDRPHY_PTR2 + DDRPHY_PTR3 + DDRPHY_PTR4 + DDRPHY_PTR5 + DDRPHY_PTR6 + >; + + ti,phy-zq = < + DDRPHY_ZQ0PR0 + DDRPHY_ZQ1PR0 + DDRPHY_ZQCR + >; + }; +}; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts new file mode 100644 index 0000000000..081a2eceb2 --- /dev/null +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am654.dtsi" +#include "k3-am654-base-board-u-boot.dtsi" +#include "k3-am654-base-board-ddr4-1600MHz.dtsi" +#include "k3-am654-ddr.dtsi" + +/ { + compatible = "ti,am654-evm", "ti,am654"; + model = "Texas Instruments AM654 R5 Base Board"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x0 0x00a90000 0x0 0x10>; + power-domains = <&k3_pds 61>, + <&k3_pds 202>; + resets = <&k3_reset 202 0>; + assigned-clocks = <&k3_clks 202 0>; + assigned-clock-rates = <800000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + vtt_supply: vtt_supply { + compatible = "regulator-gpio"; + regulator-name = "vtt"; + regulator-min-microvolt = <0>; + regulator-max-microvolt = <3300000>; + gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; + states = <0 0x0 3300000 0x1>; + u-boot,dm-spl; + }; +}; + +&cbass_main { + timer1: timer@40400000 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x40400000 0x0 0x80>; + ti,timer-alwon; + clock-frequency = <25000000>; + u-boot,dm-pre-reloc; + }; +}; + +&cbass_mcu { + mcu_secproxy: secproxy@28380000 { + compatible = "ti,am654-secure-proxy"; + reg = <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>, + <0x0 0x2a480000 0x0 0x80000>; + reg-names = "rt", "scfg", "target_data"; + #mbox-cells = <1>; + u-boot,dm-spl; + }; +}; + +&cbass_wakeup { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; + mbox-names = "tx", "rx"; + u-boot,dm-spl; + }; + + wkup_gpio0: wkup_gpio0@42110000 { + compatible = "ti,k2g-gpio", "ti,keystone-gpio"; + reg = <0x42110000 0x100>; + gpio-controller; + #gpio-cells = <2>; + ti,ngpio = <56>; + ti,davinci-gpio-unbanked = <0>; + clocks = <&k3_clks 59 0>; + clock-names = "gpio"; + u-boot,dm-spl; + }; + +}; + +&dmsc { + mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mbox-names = "tx", "rx", "notify"; + ti,host-id = <4>; + ti,secure-host; +}; + +&wkup_uart0 { + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; +}; + +&wkup_pmx0 { + u-boot,dm-spl; + wkup_uart0_pins_default: wkup_uart0_pins_default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + >; + u-boot,dm-spl; + }; + + wkup_vtt_pins_default: wkup_vtt_pins_default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */ + >; + u-boot,dm-spl; + }; +}; + +&memorycontroller { + vtt-supply = <&vtt_supply>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_vtt_pins_default>; +}; diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts index ad746c7311..6c9de25b94 100644 --- a/arch/arm/dts/keystone-k2g-evm.dts +++ b/arch/arm/dts/keystone-k2g-evm.dts @@ -33,6 +33,34 @@ }; }; +&keystone_usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; + compatible = "nop-phy"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&keystone_usb1 { + status = "okay"; +}; + +&usb1_phy { + compatible = "nop-phy"; + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + &gbe0 { phy-handle = <ðphy0>; }; diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi index 9bcfea6d86..ede7118120 100644 --- a/arch/arm/dts/keystone-k2g.dtsi +++ b/arch/arm/dts/keystone-k2g.dtsi @@ -85,7 +85,7 @@ }; qspi: qspi@2940000 { - compatible = "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0x02940000 0x1000>, @@ -201,5 +201,61 @@ status = "disabled"; clock-names = "fck"; }; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb0: keystone-dwc3@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + /*power-domains = <&k2g_pds 0x0016>;*/ + + usb0: usb@2690000 { + compatible = "snps,dwc3"; + reg = <0x2690000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + /*usb-phy = <&usb0_phy>;*/ + status = "disabled"; + }; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb1: keystone-dwc3@2580000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2580000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + /*power-domains = <&k2g_pds 0x0017>;*/ + + usb1: usb@2590000 { + compatible = "snps,dwc3"; + reg = <0x2590000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + /*usb-phy = <&usb1_phy>;*/ + status = "disabled"; + }; + }; }; }; diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts index 4cd72b5e61..32d0dc371f 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts @@ -15,18 +15,3 @@ model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3"; }; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts index 2aca9111c6..2428373952 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts @@ -15,18 +15,3 @@ model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; }; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi index 03485509c8..98b682a808 100644 --- a/arch/arm/dts/logicpd-som-lv.dtsi +++ b/arch/arm/dts/logicpd-som-lv.dtsi @@ -129,7 +129,7 @@ }; &mmc3 { - interrupts-extended = <&intc 94>; + interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; pinctrl-0 = <&mmc3_pins &wl127x_gpio>; pinctrl-names = "default"; vmmc-supply = <&wl12xx_vmmc>; @@ -232,20 +232,6 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - tsc2004_pins: pinmux_tsc2004_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ @@ -267,6 +253,33 @@ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; }; &uart2 { diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts index 9d5d53fbe9..c39cf2ca54 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts @@ -35,7 +35,7 @@ * jumpering combinations for the long run. */ &mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; + interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; pinctrl-names = "default"; vmmc-supply = <&wl12xx_vmmc>; diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi new file mode 100644 index 0000000000..c46eb3f38d --- /dev/null +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +/* wifi module */ +&sd_emmc_b { + status = "disabled"; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts new file mode 100644 index 0000000000..18778ada7b --- /dev/null +++ b/arch/arm/dts/meson-axg-s400.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-axg.dtsi" +#include + +/ { + compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; + model = "Amlogic Meson AXG S400 Development Board"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-next { + label = "Next"; + linux,code = ; + press-threshold-microvolt = <1116000>; /* 62% */ + }; + + button-prev { + label = "Previous"; + linux,code = ; + press-threshold-microvolt = <900000>; /* 50% */ + }; + + button-wifi { + label = "Wifi"; + linux,code = ; + press-threshold-microvolt = <684000>; /* 38% */ + }; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <468000>; /* 26% */ + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <252000>; /* 14% */ + }; + + button-voice { + label = "Voice"; + linux,code = ; + press-threshold-microvolt = <0>; /* 0% */ + }; + }; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + linein: audio-codec@0 { + #sound-dai-cells = <0>; + compatible = "everest,es7241"; + VDDA-supply = <&vcc_3v3>; + VDDP-supply = <&vcc_3v3>; + VDDD-supply = <&vcc_3v3>; + status = "okay"; + sound-name-prefix = "Linein"; + }; + + lineout: audio-codec@1 { + #sound-dai-cells = <0>; + compatible = "everest,es7154"; + VDD-supply = <&vcc_3v3>; + PVDD-supply = <&vcc_5v>; + status = "okay"; + sound-name-prefix = "Lineout"; + }; + + spdif_dit: audio-codec@2 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + dmics: audio-codec@3 { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <7>; + wakeup-delay-ms = <50>; + status = "okay"; + sound-name-prefix = "MIC"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + usb_pwr: regulator-usb_pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + speaker-leds { + compatible = "gpio-leds"; + + aled1 { + label = "speaker:aled1"; + gpios = <&gpio_speaker 7 0>; + }; + + aled2 { + label = "speaker:aled2"; + gpios = <&gpio_speaker 6 0>; + }; + + aled3 { + label = "speaker:aled3"; + gpios = <&gpio_speaker 5 0>; + }; + + aled4 { + label = "speaker:aled4"; + gpios = <&gpio_speaker 4 0>; + }; + + aled5 { + label = "speaker:aled5"; + gpios = <&gpio_speaker 3 0>; + }; + + aled6 { + label = "speaker:aled6"; + gpios = <&gpio_speaker 2 0>; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "AXG-S400"; + audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, + <&tdmin_lb>, <&tdmout_c>; + audio-widgets = "Line", "Lineout", + "Line", "Linein", + "Speaker", "Speaker1 Left", + "Speaker", "Speaker1 Right"; + audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "SPDIFOUT IN 0", "FRDDR_A OUT 3", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "SPDIFOUT IN 1", "FRDDR_B OUT 3", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "SPDIFOUT IN 2", "FRDDR_C OUT 3", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 2", "TDM_C Capture", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 2", "TDM_C Capture", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 2", "TDM_C Capture", + "TDMIN_C IN 5", "TDM_C Loopback", + "TDMIN_LB IN 2", "TDM_C Loopback", + "TDMIN_LB IN 5", "TDM_C Capture", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "TODDR_A IN 4", "PDM Capture", + "TODDR_B IN 4", "PDM Capture", + "TODDR_C IN 4", "PDM Capture", + "TODDR_A IN 6", "TDMIN_LB OUT", + "TODDR_B IN 6", "TDMIN_LB OUT", + "TODDR_C IN 6", "TDMIN_LB OUT", + "Lineout", "Lineout AOUTL", + "Lineout", "Lineout AOUTR", + "Speaker1 Left", "SPK1 OUT_A", + "Speaker1 Left", "SPK1 OUT_B", + "Speaker1 Right", "SPK1 OUT_C", + "Speaker1 Right", "SPK1 OUT_D", + "Linein AINL", "Linein", + "Linein AINR", "Linein"; + assigned-clocks = <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <589824000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link@0 { + sound-dai = <&frddr_a>; + }; + + dai-link@1 { + sound-dai = <&frddr_b>; + }; + + dai-link@2 { + sound-dai = <&frddr_c>; + }; + + dai-link@3 { + sound-dai = <&toddr_a>; + }; + + dai-link@4 { + sound-dai = <&toddr_b>; + }; + + dai-link@5 { + sound-dai = <&toddr_c>; + }; + + dai-link@6 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-rx-mask-1 = <1 1>; + mclk-fs = <256>; + + codec@0 { + sound-dai = <&lineout>; + }; + + codec@1 { + sound-dai = <&speaker_amp1>; + }; + + codec@2 { + sound-dai = <&linein>; + }; + + }; + + dai-link@7 { + sound-dai = <&spdifout>; + + codec { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link@8 { + sound-dai = <&pdm>; + + codec { + sound-dai = <&dmics>; + }; + }; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ + }; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_y_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_z_pins>; + pinctrl-names = "default"; + + speaker_amp1: audio-codec@1b { + compatible = "ti,tas5707"; + reg = <0x1b>; + reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcc_3v3>; + DVDD-supply = <&vcc_3v3>; + PVDD_A-supply = <&main_12v>; + PVDD_B-supply = <&main_12v>; + PVDD_C-supply = <&main_12v>; + PVDD_D-supply = <&main_12v>; + sound-name-prefix = "SPK1"; + }; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; + pinctrl-names = "default"; + + gpio_speaker: gpio-controller@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&vddao_3v3>; + }; +}; + +&pdm { + pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, + <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_x20_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* wifi module */ +&sd_emmc_b { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "disabled"; + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <180000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&spdifout { + pinctrl-0 = <&spdif_out_a20_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_a { + pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, + <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_b { + pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, + <&tdmb_din3_pins>, <&mclk_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmif_c { + pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, + <&tdmc_din1_pins>, <&tdmc_dout2_pins>, + <&mclk_c_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmin_lb { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>; + pinctrl-names = "default"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi new file mode 100644 index 0000000000..df017dbd2e --- /dev/null +++ b/arch/arm/dts/meson-axg.dtsi @@ -0,0 +1,1589 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "amlogic,meson-axg"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + tdmif_a: audio-controller@0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller@1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller@2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + ao_alt_xtal: ao_alt_xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <32000000>; + clock-output-names = "ao_alt_xtal"; + #clock-cells = <0>; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + status = "disabled"; + }; + + pdm: audio-controller@ff632000 { + compatible = "amlogic,axg-pdm"; + reg = <0x0 0xff632000 0x0 0x34>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM"; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + status = "disabled"; + }; + + periphs: bus@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng@18 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x18 0x0 0x4>; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; + }; + + pinctrl_periphs: pinctrl@480 { + compatible = "amlogic,meson-axg-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@480 { + reg = <0x0 0x00480 0x0 0x40>, + <0x0 0x004e8 0x0 0x14>, + <0x0 0x00520 0x0 0x14>, + <0x0 0x00430 0x0 0x3c>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 86>; + }; + + i2c0_pins: i2c0 { + mux { + groups = "i2c0_sck", + "i2c0_sda"; + function = "i2c0"; + }; + }; + + i2c1_x_pins: i2c1_x { + mux { + groups = "i2c1_sck_x", + "i2c1_sda_x"; + function = "i2c1"; + }; + }; + + i2c1_z_pins: i2c1_z { + mux { + groups = "i2c1_sck_z", + "i2c1_sda_z"; + function = "i2c1"; + }; + }; + + i2c2_a_pins: i2c2_a { + mux { + groups = "i2c2_sck_a", + "i2c2_sda_a"; + function = "i2c2"; + }; + }; + + i2c2_x_pins: i2c2_x { + mux { + groups = "i2c2_sck_x", + "i2c2_sda_x"; + function = "i2c2"; + }; + }; + + i2c3_a6_pins: i2c3_a6 { + mux { + groups = "i2c3_sda_a6", + "i2c3_sck_a7"; + function = "i2c3"; + }; + }; + + i2c3_a12_pins: i2c3_a12 { + mux { + groups = "i2c3_sda_a12", + "i2c3_sck_a13"; + function = "i2c3"; + }; + }; + + i2c3_a19_pins: i2c3_a19 { + mux { + groups = "i2c3_sda_a19", + "i2c3_sck_a20"; + function = "i2c3"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd", + "emmc_ds"; + function = "emmc"; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + + eth_rgmii_x_pins: eth-x-rgmii { + mux { + groups = "eth_mdio_x", + "eth_mdc_x", + "eth_rgmii_rx_clk_x", + "eth_rx_dv_x", + "eth_rxd0_x", + "eth_rxd1_x", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_x", + "eth_txd0_x", + "eth_txd1_x", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; + + eth_rgmii_y_pins: eth-y-rgmii { + mux { + groups = "eth_mdio_y", + "eth_mdc_y", + "eth_rgmii_rx_clk_y", + "eth_rx_dv_y", + "eth_rxd0_y", + "eth_rxd1_y", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen_y", + "eth_txd0_y", + "eth_txd1_y", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + }; + }; + + eth_rmii_x_pins: eth-x-rmii { + mux { + groups = "eth_mdio_x", + "eth_mdc_x", + "eth_rgmii_rx_clk_x", + "eth_rx_dv_x", + "eth_rxd0_x", + "eth_rxd1_x", + "eth_txen_x", + "eth_txd0_x", + "eth_txd1_x"; + function = "eth"; + }; + }; + + eth_rmii_y_pins: eth-y-rmii { + mux { + groups = "eth_mdio_y", + "eth_mdc_y", + "eth_rgmii_rx_clk_y", + "eth_rx_dv_y", + "eth_rxd0_y", + "eth_rxd1_y", + "eth_txen_y", + "eth_txd0_y", + "eth_txd1_y"; + function = "eth"; + }; + }; + + mclk_b_pins: mclk_b { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + mclk_c_pins: mclk_c { + mux { + groups = "mclk_c"; + function = "mclk_c"; + }; + }; + + pdm_dclk_a14_pins: pdm_dclk_a14 { + mux { + groups = "pdm_dclk_a14"; + function = "pdm"; + }; + }; + + pdm_dclk_a19_pins: pdm_dclk_a19 { + mux { + groups = "pdm_dclk_a19"; + function = "pdm"; + }; + }; + + pdm_din0_pins: pdm_din0 { + mux { + groups = "pdm_din0"; + function = "pdm"; + }; + }; + + pdm_din1_pins: pdm_din1 { + mux { + groups = "pdm_din1"; + function = "pdm"; + }; + }; + + pdm_din2_pins: pdm_din2 { + mux { + groups = "pdm_din2"; + function = "pdm"; + }; + }; + + pdm_din3_pins: pdm_din3 { + mux { + groups = "pdm_din3"; + function = "pdm"; + }; + }; + + pwm_a_a_pins: pwm_a_a { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_a_x18_pins: pwm_a_x18 { + mux { + groups = "pwm_a_x18"; + function = "pwm_a"; + }; + }; + + pwm_a_x20_pins: pwm_a_x20 { + mux { + groups = "pwm_a_x20"; + function = "pwm_a"; + }; + }; + + pwm_a_z_pins: pwm_a_z { + mux { + groups = "pwm_a_z"; + function = "pwm_a"; + }; + }; + + pwm_b_a_pins: pwm_b_a { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_b_x_pins: pwm_b_x { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_z_pins: pwm_b_z { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + + pwm_c_a_pins: pwm_c_a { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_c_x10_pins: pwm_c_x10 { + mux { + groups = "pwm_c_x10"; + function = "pwm_c"; + }; + }; + + pwm_c_x17_pins: pwm_c_x17 { + mux { + groups = "pwm_c_x17"; + function = "pwm_c"; + }; + }; + + pwm_d_x11_pins: pwm_d_x11 { + mux { + groups = "pwm_d_x11"; + function = "pwm_d"; + }; + }; + + pwm_d_x16_pins: pwm_d_x16 { + mux { + groups = "pwm_d_x16"; + function = "pwm_d"; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + + spdif_in_z_pins: spdif_in_z { + mux { + groups = "spdif_in_z"; + function = "spdif_in"; + }; + }; + + spdif_in_a1_pins: spdif_in_a1 { + mux { + groups = "spdif_in_a1"; + function = "spdif_in"; + }; + }; + + spdif_in_a7_pins: spdif_in_a7 { + mux { + groups = "spdif_in_a7"; + function = "spdif_in"; + }; + }; + + spdif_in_a19_pins: spdif_in_a19 { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + spdif_in_a20_pins: spdif_in_a20 { + mux { + groups = "spdif_in_a20"; + function = "spdif_in"; + }; + }; + + spdif_out_a1_pins: spdif_out_a1 { + mux { + groups = "spdif_out_a1"; + function = "spdif_out"; + }; + }; + + spdif_out_a11_pins: spdif_out_a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + }; + }; + + spdif_out_a19_pins: spdif_out_a19 { + mux { + groups = "spdif_out_a19"; + function = "spdif_out"; + }; + }; + + spdif_out_a20_pins: spdif_out_a20 { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdif_out_z_pins: spdif_out_z { + mux { + groups = "spdif_out_z"; + function = "spdif_out"; + }; + }; + + spi0_pins: spi0 { + mux { + groups = "spi0_miso", + "spi0_mosi", + "spi0_clk"; + function = "spi0"; + }; + }; + + spi0_ss0_pins: spi0_ss0 { + mux { + groups = "spi0_ss0"; + function = "spi0"; + }; + }; + + spi0_ss1_pins: spi0_ss1 { + mux { + groups = "spi0_ss1"; + function = "spi0"; + }; + }; + + spi0_ss2_pins: spi0_ss2 { + mux { + groups = "spi0_ss2"; + function = "spi0"; + }; + }; + + spi1_a_pins: spi1_a { + mux { + groups = "spi1_miso_a", + "spi1_mosi_a", + "spi1_clk_a"; + function = "spi1"; + }; + }; + + spi1_ss0_a_pins: spi1_ss0_a { + mux { + groups = "spi1_ss0_a"; + function = "spi1"; + }; + }; + + spi1_ss1_pins: spi1_ss1 { + mux { + groups = "spi1_ss1"; + function = "spi1"; + }; + }; + + spi1_x_pins: spi1_x { + mux { + groups = "spi1_miso_x", + "spi1_mosi_x", + "spi1_clk_x"; + function = "spi1"; + }; + }; + + spi1_ss0_x_pins: spi1_ss0_x { + mux { + groups = "spi1_ss0_x"; + function = "spi1"; + }; + }; + + tdma_din0_pins: tdma_din0 { + mux { + groups = "tdma_din0"; + function = "tdma"; + }; + }; + + tdma_dout0_x14_pins: tdma_dout0_x14 { + mux { + groups = "tdma_dout0_x14"; + function = "tdma"; + }; + }; + + tdma_dout0_x15_pins: tdma_dout0_x15 { + mux { + groups = "tdma_dout0_x15"; + function = "tdma"; + }; + }; + + tdma_dout1_pins: tdma_dout1 { + mux { + groups = "tdma_dout1"; + function = "tdma"; + }; + }; + + tdma_din1_pins: tdma_din1 { + mux { + groups = "tdma_din1"; + function = "tdma"; + }; + }; + + tdma_fs_pins: tdma_fs { + mux { + groups = "tdma_fs"; + function = "tdma"; + }; + }; + + tdma_fs_slv_pins: tdma_fs_slv { + mux { + groups = "tdma_fs_slv"; + function = "tdma"; + }; + }; + + tdma_sclk_pins: tdma_sclk { + mux { + groups = "tdma_sclk"; + function = "tdma"; + }; + }; + + tdma_sclk_slv_pins: tdma_sclk_slv { + mux { + groups = "tdma_sclk_slv"; + function = "tdma"; + }; + }; + + tdmb_din0_pins: tdmb_din0 { + mux { + groups = "tdmb_din0"; + function = "tdmb"; + }; + }; + + tdmb_din1_pins: tdmb_din1 { + mux { + groups = "tdmb_din1"; + function = "tdmb"; + }; + }; + + tdmb_din2_pins: tdmb_din2 { + mux { + groups = "tdmb_din2"; + function = "tdmb"; + }; + }; + + tdmb_din3_pins: tdmb_din3 { + mux { + groups = "tdmb_din3"; + function = "tdmb"; + }; + }; + + tdmb_dout0_pins: tdmb_dout0 { + mux { + groups = "tdmb_dout0"; + function = "tdmb"; + }; + }; + + tdmb_dout1_pins: tdmb_dout1 { + mux { + groups = "tdmb_dout1"; + function = "tdmb"; + }; + }; + + tdmb_dout2_pins: tdmb_dout2 { + mux { + groups = "tdmb_dout2"; + function = "tdmb"; + }; + }; + + tdmb_dout3_pins: tdmb_dout3 { + mux { + groups = "tdmb_dout3"; + function = "tdmb"; + }; + }; + + tdmb_fs_pins: tdmb_fs { + mux { + groups = "tdmb_fs"; + function = "tdmb"; + }; + }; + + tdmb_fs_slv_pins: tdmb_fs_slv { + mux { + groups = "tdmb_fs_slv"; + function = "tdmb"; + }; + }; + + tdmb_sclk_pins: tdmb_sclk { + mux { + groups = "tdmb_sclk"; + function = "tdmb"; + }; + }; + + tdmb_sclk_slv_pins: tdmb_sclk_slv { + mux { + groups = "tdmb_sclk_slv"; + function = "tdmb"; + }; + }; + + tdmc_fs_pins: tdmc_fs { + mux { + groups = "tdmc_fs"; + function = "tdmc"; + }; + }; + + tdmc_fs_slv_pins: tdmc_fs_slv { + mux { + groups = "tdmc_fs_slv"; + function = "tdmc"; + }; + }; + + tdmc_sclk_pins: tdmc_sclk { + mux { + groups = "tdmc_sclk"; + function = "tdmc"; + }; + }; + + tdmc_sclk_slv_pins: tdmc_sclk_slv { + mux { + groups = "tdmc_sclk_slv"; + function = "tdmc"; + }; + }; + + tdmc_din0_pins: tdmc_din0 { + mux { + groups = "tdmc_din0"; + function = "tdmc"; + }; + }; + + tdmc_din1_pins: tdmc_din1 { + mux { + groups = "tdmc_din1"; + function = "tdmc"; + }; + }; + + tdmc_din2_pins: tdmc_din2 { + mux { + groups = "tdmc_din2"; + function = "tdmc"; + }; + }; + + tdmc_din3_pins: tdmc_din3 { + mux { + groups = "tdmc_din3"; + function = "tdmc"; + }; + }; + + tdmc_dout0_pins: tdmc_dout0 { + mux { + groups = "tdmc_dout0"; + function = "tdmc"; + }; + }; + + tdmc_dout1_pins: tdmc_dout1 { + mux { + groups = "tdmc_dout1"; + function = "tdmc"; + }; + }; + + tdmc_dout2_pins: tdmc_dout2 { + mux { + groups = "tdmc_dout2"; + function = "tdmc"; + }; + }; + + tdmc_dout3_pins: tdmc_dout3 { + mux { + groups = "tdmc_dout3"; + function = "tdmc"; + }; + }; + + uart_a_pins: uart_a { + mux { + groups = "uart_tx_a", + "uart_rx_a"; + function = "uart_a"; + }; + }; + + uart_a_cts_rts_pins: uart_a_cts_rts { + mux { + groups = "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + uart_b_x_pins: uart_b_x { + mux { + groups = "uart_tx_b_x", + "uart_rx_b_x"; + function = "uart_b"; + }; + }; + + uart_b_x_cts_rts_pins: uart_b_x_cts_rts { + mux { + groups = "uart_cts_b_x", + "uart_rts_b_x"; + function = "uart_b"; + }; + }; + + uart_b_z_pins: uart_b_z { + mux { + groups = "uart_tx_b_z", + "uart_rx_b_z"; + function = "uart_b"; + }; + }; + + uart_b_z_cts_rts_pins: uart_b_z_cts_rts { + mux { + groups = "uart_cts_b_z", + "uart_rts_b_z"; + function = "uart_b"; + }; + }; + + uart_ao_b_z_pins: uart_ao_b_z { + mux { + groups = "uart_ao_tx_b_z", + "uart_ao_rx_b_z"; + function = "uart_ao_b_z"; + }; + }; + + uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { + mux { + groups = "uart_ao_cts_b_z", + "uart_ao_rts_b_z"; + function = "uart_ao_b_z"; + }; + }; + }; + }; + + hiubus: bus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x1c00>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; + + sysctrl: system-controller@0 { + compatible = "amlogic,meson-axg-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,axg-clkc"; + #clock-cells = <1>; + }; + }; + }; + + mailbox: mailbox@ff63dc00 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0xff63dc00 0 0x400>; + interrupts = , + , + ; + #mbox-cells = <1>; + }; + + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + toddr_a: audio-controller@100 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x100 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_A"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_A>; + resets = <&arb AXG_ARB_TODDR_A>; + status = "disabled"; + }; + + toddr_b: audio-controller@140 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x140 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_B"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_B>; + resets = <&arb AXG_ARB_TODDR_B>; + status = "disabled"; + }; + + toddr_c: audio-controller@180 { + compatible = "amlogic,axg-toddr"; + reg = <0x0 0x180 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_C"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_TODDR_C>; + resets = <&arb AXG_ARB_TODDR_C>; + status = "disabled"; + }; + + frddr_a: audio-controller@1c0 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x1c0 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_A"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + resets = <&arb AXG_ARB_FRDDR_A>; + status = "disabled"; + }; + + frddr_b: audio-controller@200 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x200 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_B"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; + resets = <&arb AXG_ARB_FRDDR_B>; + status = "disabled"; + }; + + frddr_c: audio-controller@240 { + compatible = "amlogic,axg-frddr"; + reg = <0x0 0x240 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_C"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; + resets = <&arb AXG_ARB_FRDDR_C>; + status = "disabled"; + }; + + arb: reset-controller@280 { + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,axg-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + }; + + aobus: bus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + sysctrl_AO: sys-ctrl@0 { + compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; + reg = <0x0 0x0 0x0 0x100>; + + clkc_AO: clock-controller { + compatible = "amlogic,meson-axg-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-axg-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0x00014 0x0 0x8>, + <0x0 0x0002c 0x0 0x4>, + <0x0 0x00024 0x0 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 15>; + }; + + i2c_ao_sck_4_pins: i2c_ao_sck_4 { + mux { + groups = "i2c_ao_sck_4"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sck_8_pins: i2c_ao_sck_8 { + mux { + groups = "i2c_ao_sck_8"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sck_10_pins: i2c_ao_sck_10 { + mux { + groups = "i2c_ao_sck_10"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_5_pins: i2c_ao_sda_5 { + mux { + groups = "i2c_ao_sda_5"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_9_pins: i2c_ao_sda_9 { + mux { + groups = "i2c_ao_sda_9"; + function = "i2c_ao"; + }; + }; + + i2c_ao_sda_11_pins: i2c_ao_sda_11 { + mux { + groups = "i2c_ao_sda_11"; + function = "i2c_ao"; + }; + }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_ao_tx_a", + "uart_ao_rx_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { + mux { + groups = "uart_ao_cts_a", + "uart_ao_rts_a"; + function = "uart_ao_a"; + }; + }; + + uart_ao_b_pins: uart_ao_b { + mux { + groups = "uart_ao_tx_b", + "uart_ao_rx_b"; + function = "uart_ao_b"; + }; + }; + + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { + mux { + groups = "uart_ao_cts_b", + "uart_ao_rts_b"; + function = "uart_ao_b"; + }; + }; + }; + + sec_AO: ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x02000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = ; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x05000 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_AO_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-axg-ao-pwm"; + reg = <0x0 0x07000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8000 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8000 0x0 0x20>; + interrupts = ; + status = "disabled"; + }; + + saradc: adc@9000 { + compatible = "amlogic,meson-axg-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x9000 0x0 0x38>; + #io-channel-cells = <1>; + interrupts = ; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_SAR_ADC>, + <&clkc_AO CLKID_AO_SAR_ADC_CLK>, + <&clkc_AO CLKID_AO_SAR_ADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x25000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; + + reset: reset-controller@1004 { + compatible = "amlogic,meson-axg-reset"; + reg = <0x0 0x01004 0x0 0x9c>; + #reset-cells = <1>; + }; + + gpio_intc: interrupt-controller@f080 { + compatible = "amlogic,meson-gpio-intc"; + reg = <0x0 0xf080 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + status = "disabled"; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-axg-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + spicc0: spi@13000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x13000 0x0 0x3c>; + interrupts = ; + clocks = <&clkc CLKID_SPICC0>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@15000 { + compatible = "amlogic,meson-axg-spicc"; + reg = <0x0 0x15000 0x0 0x3c>; + interrupts = ; + clocks = <&clkc CLKID_SPICC1>; + clock-names = "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1c000 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1d000 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1e000 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1f000 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart_B: serial@23000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x23000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + uart_A: serial@24000 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x0 0x24000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + + apb: bus@ffe00000 { + compatible = "simple-bus"; + reg = <0x0 0xffe00000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; + + sd_emmc_b: sd@5000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x5000 0x0 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_c: mmc@7000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x7000 0x0 0x800>; + interrupts = ; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; + }; + + sram: sram@fffc0000 { + compatible = "amlogic,meson-axg-sram", "mmio-sram"; + reg = <0x0 0xfffc0000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfffc0000 0x20000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-axg-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 3c31e21cbe..f1e5cdbade 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -35,10 +35,16 @@ no-map; }; + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved_alt: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0xbc00000>; + size = <0x0 0x10000000>; alignment = <0x0 0x400000>; linux,cma-default; }; @@ -338,7 +344,7 @@ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; pwrc_vpu: power-controller-vpu { @@ -417,6 +423,19 @@ }; }; + dmcbus: bus@c8838000 { + compatible = "simple-bus"; + reg = <0x0 0xc8838000 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x0 0x48 0x0 0x14>; + }; + }; + hiubus: bus@c883c000 { compatible = "simple-bus"; reg = <0x0 0xc883c000 0x0 0x2000>; @@ -425,7 +444,7 @@ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; reg = <0 0 0 0x400>; }; @@ -457,21 +476,21 @@ sd_emmc_a: mmc@70000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x2000>; + reg = <0x0 0x70000 0x0 0x800>; interrupts = ; status = "disabled"; }; sd_emmc_b: mmc@72000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x2000>; + reg = <0x0 0x72000 0x0 0x800>; interrupts = ; status = "disabled"; }; sd_emmc_c: mmc@74000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x2000>; + reg = <0x0 0x74000 0x0 0x800>; interrupts = ; status = "disabled"; }; diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts index 7d5709c37e..cbe99bd4e0 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts @@ -106,6 +106,42 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + /* CVBS is available on CON1 pin 36, disabled by default */ + cvbs-connector { + compatible = "composite-video-connector"; + status = "disabled"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; }; ðmac { @@ -137,6 +173,18 @@ }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 562c26a0ba..1ade7e4868 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -307,11 +307,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { +&sysctrl { + clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -391,7 +390,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -716,6 +715,7 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { @@ -723,6 +723,7 @@ <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -730,6 +731,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -749,12 +751,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi index eb327664a4..6aaafff674 100644 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ b/arch/arm/dts/meson-gxl-mali.dtsi @@ -6,7 +6,7 @@ &apb { mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; reg = <0x0 0xc0000 0x0 0x40000>; interrupts = , , diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index 3e3eb31748..90a56af967 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -13,7 +13,7 @@ / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Libre Technology CC"; + model = "Libre Computer Board AML-S905X-CC"; aliases { serial0 = &uart_AO; @@ -234,9 +234,6 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; max-frequency = <100000000>; disable-wp; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 3bd405079b..a1b31013ab 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -191,8 +191,8 @@ }; &usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; + /* + * HDMI_5V is also used as supply for the USB VBUS. + */ + phy-supply = <&hdmi_5v>; }; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index dba365ed4b..8f0bb3c44b 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -13,14 +13,6 @@ / { compatible = "amlogic,meson-gxl"; - reserved-memory { - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - soc { usb0: usb@c9000000 { status = "disabled"; @@ -267,11 +259,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { - compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; +&sysctrl { + clkc: clock-controller { + compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -346,7 +337,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -725,13 +716,15 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -739,6 +732,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -758,12 +752,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 0868da476e..313f88f875 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -209,10 +209,34 @@ #cooling-cells = <2>; }; +&cpu1 { + #cooling-cells = <2>; +}; + +&cpu2 { + #cooling-cells = <2>; +}; + +&cpu3 { + #cooling-cells = <2>; +}; + &cpu4 { #cooling-cells = <2>; }; +&cpu5 { + #cooling-cells = <2>; +}; + +&cpu6 { + #cooling-cells = <2>; +}; + +&cpu7 { + #cooling-cells = <2>; +}; + ðmac { pinctrl-0 = <ð_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi new file mode 100644 index 0000000000..f50f4ef1b9 --- /dev/null +++ b/arch/arm/dts/mt7623.dtsi @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt7623"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + clocks = <&infracfg CLK_INFRA_CPUSEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + clock-frequency = <1300000000>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc32k: oscillator-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + + clk26m: oscillator-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt7623-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt7623-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt7623-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pinctrl: pinctrl@10005000 { + compatible = "mediatek,mt7623-pinctrl"; + reg = <0x10005000 0x1000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7623-scpsys"; + #power-domain-cells = <1>; + reg = <0x10006000 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x100>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&watchdog>; + }; + + timer0: timer@10008000 { + compatible = "mediatek,timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>; + clock-names = "system-clk"; + u-boot,dm-pre-reloc; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7623-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + uart3: serial@11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7623-mmc"; + reg = <0x11230000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC30_0_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7623-mmc"; + reg = <0x11240000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7623-ethsys"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts new file mode 100644 index 0000000000..84a77fde44 --- /dev/null +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7623.dtsi" + +/ { + model = "Bananapi BPI-R2"; + compatible = "bananapi,bpi-r2", "mediatek,mt7623"; + + chosen { + stdout-path = &uart2; + tick-timer = &timer0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bpi-r2:pio:blue"; + gpios = <&gpio 241 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green { + label = "bpi-r2:pio:green"; + gpios = <&gpio 240 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red { + label = "bpi-r2:pio:red"; + gpios = <&gpio 239 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + cd-gpios = <&gpio 261 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&pinctrl { + ephy_default: ephy_default { + mux { + function = "eth"; + groups = "mdc_mdio", "ephy"; + }; + + conf { + pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2", + "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0", + "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV", + "MDC", "MDIO"; + drive-strength = <12>; + mediatek,tdsel = <5>; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + mux { + function = "msdc"; + groups = "msdc1", "msdc1_wp_0"; + }; + + conf-cmd-data { + pins = "MSDC1_DAT0", "MSDC1_DAT1", "MSDC1_DAT2", + "MSDC1_DAT3", "MSDC1_DAT3", "MSDC1_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC1_CLK"; + drive-strength = <4>; + }; + + conf-wp { + pins = "EINT7"; + input-enable; + bias-pull-up; + }; + }; + + uart0_pins_a: uart0-default { + mux { + function = "uart"; + groups = "uart0_0_txd_rxd"; + }; + }; + + uart1_pins_a: uart1-default { + mux { + function = "uart"; + groups = "uart1_0_txd_rxd"; + }; + }; + + uart2_pins_a: uart2-default { + mux { + function = "uart"; + groups = "uart2_0_txd_rxd"; + }; + }; + + uart2_pins_b: uart2-alt { + mux { + function = "uart"; + groups = "uart2_1_txd_rxd"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi new file mode 100644 index 0000000000..1ef5568518 --- /dev/null +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#include +/ { + binman { + filename = "u-boot-mtk.bin"; + pad-byte = <0xff>; + +#ifdef CONFIG_SPL + blob { + filename = "spl/u-boot-spl-mtk.bin"; + size = ; + }; + + u-boot-img { + }; +#endif + }; +}; diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts new file mode 100644 index 0000000000..a6d28a060f --- /dev/null +++ b/arch/arm/dts/mt7629-rfb.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7629.dtsi" + +/ { + model = "MediaTek MT7629 RFB"; + compatible = "mediatek,mt7629-rfb", "mediatek,mt7629"; + + aliases { + spi0 = &qspi; + }; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; +}; + +&pinctrl { + qspi_pins: qspi-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0-default { + mux { + function = "uart"; + groups = "uart0_txd_rxd"; + }; + }; + + watchdog_pins: watchdog-default { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_pins>; + status = "okay"; + + spi-flash@0{ + compatible = "spi-flash"; + reg = <0>; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi new file mode 100644 index 0000000000..e6052bbdcf --- /dev/null +++ b/arch/arm/dts/mt7629.dtsi @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt7629"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt6589-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1250000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1250000000>; + }; + }; + + clk20m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "clk20m"; + }; + + clk40m: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <20000000>; + arm,cpu-registers-not-fw-configured; + }; + + infracfg: syscon@10000000 { + compatible = "mediatek,mt7629-infracfg", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pericfg: syscon@10002000 { + compatible = "mediatek,mt7629-pericfg", "syscon"; + reg = <0x10002000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + timer0: timer@10004000 { + compatible = "mediatek,timer"; + reg = <0x10004000 0x80>; + interrupts = ; + clocks = <&topckgen CLK_TOP_10M_SEL>, + <&topckgen CLK_TOP_CLKXTAL_D4>; + clock-names = "mux", "src"; + u-boot,dm-pre-reloc; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7629-scpsys"; + reg = <0x10006000 0x1000>; + clocks = <&topckgen CLK_TOP_HIF_SEL>; + clock-names = "hif_sel"; + assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; + #power-domain-cells = <1>; + infracfg = <&infracfg>; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt7629-mcucfg", "syscon"; + reg = <0x10200000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,sysirq"; + reg = <0x10200a80 0x20>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + dramc: dramc@10203000 { + compatible = "mediatek,mt7629-dramc"; + reg = <0x10203000 0x600>, /* EMI */ + <0x10213000 0x1000>, /* DDRPHY */ + <0x10214000 0xd00>; /* DRAMC_AO */ + clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>, + <&topckgen CLK_TOP_SYSPLL1_D8>, + <&topckgen CLK_TOP_MEM_SEL>, + <&topckgen CLK_TOP_DMPLL>; + clock-names = "phy", "phy_mux", "mem", "mem_mux"; + u-boot,dm-pre-reloc; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7629-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + topckgen: clock-controller@10210000 { + compatible = "mediatek,mt7629-topckgen"; + reg = <0x10210000 0x1000>; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + watchdog: watchdog@10212000 { + compatible = "mediatek,wdt"; + reg = <0x10212000 0x600>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&watchdog>; + }; + + pinctrl: pinctrl@10217000 { + compatible = "mediatek,mt7629-pinctrl"; + reg = <0x10217000 0x8000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + u-boot,dm-pre-reloc; + }; + + uart1: serial@11003000 { + compatible = "mediatek,hsuart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,hsuart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2_PD>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + status = "disabled"; + }; + + qspi: qspi@11014000 { + compatible = "mediatek,mt7629-qspi"; + reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; + reg-names = "reg_base", "mem_base"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7629-ethsys", "syscon"; + reg = <0x1b000000 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@1b128000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b128000 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@1b130000 { + compatible = "mediatek,mt7629-sgmiisys", "syscon"; + reg = <0x1b130000 0x1000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi index bf2684cb61..1eb50cd438 100644 --- a/arch/arm/dts/omap5-u-boot.dtsi +++ b/arch/arm/dts/omap5-u-boot.dtsi @@ -15,6 +15,10 @@ ocp { u-boot,dm-spl; + ocp2scp@4a080000 { + compatible = "ti,omap-ocp2scp", "simple-bus"; + }; + ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp", "simple-bus"; }; @@ -91,3 +95,7 @@ &gpio7 { u-boot,dm-spl; }; + +&i2c1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts index dcda98c6ae..50312e752e 100644 --- a/arch/arm/dts/r8a7790-lager.dts +++ b/arch/arm/dts/r8a7790-lager.dts @@ -899,9 +899,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep0: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -926,6 +923,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi index ed09e56c36..0925bdca43 100644 --- a/arch/arm/dts/r8a7790.dtsi +++ b/arch/arm/dts/r8a7790.dtsi @@ -76,12 +76,12 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -101,6 +101,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu2: cpu@2 { @@ -112,6 +122,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu3: cpu@3 { @@ -123,6 +143,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu4: cpu@100 { @@ -199,6 +229,24 @@ clock-frequency = <0>; }; + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -215,6 +263,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7790-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; @@ -440,7 +498,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1541,7 +1599,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -1612,6 +1670,33 @@ resets = <&cpg 127>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 117>; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; @@ -1770,10 +1855,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts index be96bfd4f3..ce22db01fb 100644 --- a/arch/arm/dts/r8a7791-koelsch.dts +++ b/arch/arm/dts/r8a7791-koelsch.dts @@ -640,6 +640,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sata0 { status = "okay"; }; @@ -847,9 +852,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -868,9 +870,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dts index 797fa9d6e7..275f6b4375 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dts +++ b/arch/arm/dts/r8a7791-porter-u-boot.dts @@ -11,3 +11,8 @@ &scif0 { u-boot,dm-pre-reloc; }; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts index fa9a57d770..f02036e5de 100644 --- a/arch/arm/dts/r8a7791-porter.dts +++ b/arch/arm/dts/r8a7791-porter.dts @@ -374,13 +374,41 @@ &i2c6 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; + + pmic@5a { + compatible = "dlg,da9063l"; + reg = <0x5a>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; }; &sata0 { status = "okay"; }; +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + /* composite video input */ &vin0 { status = "okay"; @@ -388,9 +416,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -483,6 +508,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi index d728738ba8..991ac6feed 100644 --- a/arch/arm/dts/r8a7791.dtsi +++ b/arch/arm/dts/r8a7791.dtsi @@ -75,11 +75,11 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -98,6 +98,16 @@ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { @@ -123,6 +133,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -139,6 +156,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7791-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; @@ -404,7 +431,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1618,6 +1645,24 @@ resets = <&cpg 127>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; diff --git a/arch/arm/dts/r8a7792-blanche.dts b/arch/arm/dts/r8a7792-blanche.dts index 023d870bed..f92301290b 100644 --- a/arch/arm/dts/r8a7792-blanche.dts +++ b/arch/arm/dts/r8a7792-blanche.dts @@ -236,6 +236,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e26dede30..63a978ec81 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -82,6 +82,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -98,6 +105,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7792-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", "renesas,rcar-gen2-gpio"; @@ -338,7 +355,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts index 9c893458ce..6b2f3a4fd1 100644 --- a/arch/arm/dts/r8a7793-gose.dts +++ b/arch/arm/dts/r8a7793-gose.dts @@ -596,6 +596,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; @@ -755,9 +760,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -777,9 +779,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180_out>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi index 8201b4e8d1..620a570307 100644 --- a/arch/arm/dts/r8a7793.dtsi +++ b/arch/arm/dts/r8a7793.dtsi @@ -67,10 +67,10 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -89,6 +89,17 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; }; L2_CA15: cache-controller-0 { @@ -107,6 +118,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -123,6 +141,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7793-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; @@ -389,7 +417,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1287,6 +1315,24 @@ resets = <&cpg 408>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7793"; reg = <0 0xfeb00000 0 0x40000>; diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts index af3c67eb02..ef7e2a837d 100644 --- a/arch/arm/dts/r8a7794-alt.dts +++ b/arch/arm/dts/r8a7794-alt.dts @@ -178,6 +178,12 @@ }; }; }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; }; /* @@ -327,6 +333,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; @@ -372,9 +383,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts index 50dad43c10..daec965889 100644 --- a/arch/arm/dts/r8a7794-silk.dts +++ b/arch/arm/dts/r8a7794-silk.dts @@ -472,9 +472,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -537,6 +534,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi index 0cc07b30d1..ea2ca4bdaf 100644 --- a/arch/arm/dts/r8a7794.dtsi +++ b/arch/arm/dts/r8a7794.dtsi @@ -100,6 +100,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -116,6 +123,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7794-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; @@ -345,7 +362,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1320,6 +1337,15 @@ resets = <&cpg 128>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7794"; reg = <0 0xfeb00000 0 0x40000>; diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts index 06bd4f24ca..ebbd234d78 100644 --- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts @@ -7,3 +7,35 @@ #include "r8a7795-h3ulcb.dts" #include "r8a7795-u-boot.dtsi" + +/ { + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; +}; + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts index 666fbf5a83..8be5e41a51 100644 --- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts @@ -7,3 +7,31 @@ #include "r8a7795-salvator-x.dts" #include "r8a7795-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a7795-salvator-x.dts index 36373d6cce..446822f575 100644 --- a/arch/arm/dts/r8a7795-salvator-x.dts +++ b/arch/arm/dts/r8a7795-salvator-x.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Salvator-X board + * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 * * Copyright (C) 2015 Renesas Electronics Corp. */ @@ -53,6 +53,12 @@ status = "okay"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2>; /* HDMI1 */ +}; + &hdmi0 { status = "okay"; @@ -63,6 +69,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; @@ -80,6 +92,12 @@ remote-endpoint = <&hdmi1_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi1_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint2>; + }; + }; }; }; @@ -91,6 +109,34 @@ status = "okay"; }; +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + rsnd_port2: port@2 { + rsnd_endpoint2: endpoint { + remote-endpoint = <&dw_hdmi1_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint2>; + frame-master = <&rsnd_endpoint2>; + + playback = <&ssi3>; + }; + }; + }; +}; + &pfc { usb2_pins: usb2 { groups = "usb2"; diff --git a/arch/arm/dts/r8a7795-u-boot.dtsi b/arch/arm/dts/r8a7795-u-boot.dtsi index 526966ab24..cc22c57ae3 100644 --- a/arch/arm/dts/r8a7795-u-boot.dtsi +++ b/arch/arm/dts/r8a7795-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7795", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index af77bfe4e4..c87eed77de 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -27,131 +27,6 @@ i2c7 = &i2c_dvfs; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -237,6 +112,131 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -244,18 +244,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -268,6 +256,18 @@ <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -288,24 +288,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; @@ -434,6 +417,11 @@ resets = <&cpg 905>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -449,20 +437,25 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7795-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; }; intc_ex: interrupt-controller@e61c0000 { @@ -481,153 +474,335 @@ resets = <&cpg 407>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: mmu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vp1: mmu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vc1: mmu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_pv2: mmu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = ; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_pv3: mmu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; - ipmmu_mp0: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 520>; status = "disabled"; }; - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 519>; + status = "disabled"; }; - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 518>; + status = "disabled"; }; - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + hsusb3: usb@e659c000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe659c000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, + <&usb_dmac3 0>, <&usb_dmac3 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy3>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac2: dma-controller@e6460000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6460000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac3: dma-controller@e6470000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6470000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 329>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 329>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7795-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; }; dmac0: dma-controller@e6700000 { @@ -756,88 +931,141 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + #iommu-cells = <1>; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7795_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp0: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv2: mmu@fd960000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv3: mmu@fd970000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vc1: mmu@fe6f0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: mmu@febe0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + }; + + ipmmu_vp1: mmu@fe980000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; }; avb: ethernet@e6800000 { @@ -943,6 +1171,494 @@ }; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7795", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin7>; + }; + }; + }; + }; + drif00: rif@e6f40000 { compatible = "renesas,r8a7795-drif", "renesas,rcar-gen3-drif"; @@ -1063,457 +1779,6 @@ status = "disabled"; }; - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1708,31 +1973,104 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; }; - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; }; - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; }; xhci0: usb@ee000000 { @@ -1756,161 +2094,51 @@ status = "disabled"; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a7795", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; + ohci2: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; + ohci3: usb@ee0e0000 { + compatible = "generic-ohci"; + reg = <0 0xee0e0000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 700>; + phys = <&usb2_phy3>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>; - #phy-cells = <0>; status = "disabled"; }; @@ -1966,88 +2194,129 @@ status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; + #phy-cells = <0>; status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; + #phy-cells = <0>; status = "disabled"; }; - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; + usb2_phy2: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; + #phy-cells = <0>; status = "disabled"; }; - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; + usb2_phy3: usb-phy@ee0e0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0e0200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 700>; - phys = <&usb2_phy3>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>; + #phy-cells = <0>; status = "disabled"; }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 314>; status = "disabled"; }; - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3>; - phy-names = "usb"; + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>; + resets = <&cpg 313>; status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + iommus = <&ipmmu_hc 2>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7795", "renesas,pcie-rcar-gen3"; @@ -2142,24 +2411,24 @@ resets = <&cpg 820>; }; - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; }; - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; }; fcpf0: fcp@fe950000 { @@ -2180,6 +2449,69 @@ iommus = <&ipmmu_vp1 1>; }; + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 606>; + iommus = <&ipmmu_vp1 7>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 611>; + iommus = <&ipmmu_vp0 8>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 610>; + iommus = <&ipmmu_vp1 9>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi1 10>; + }; + vspbd: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -2191,13 +2523,48 @@ renesas,fcp = <&fcpvb0>; }; - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 624>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; }; vspi0: vsp@fe9a0000 { @@ -2211,15 +2578,6 @@ renesas,fcp = <&fcpvi0>; }; - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - vspi1: vsp@fe9b0000 { compatible = "renesas,vsp2"; reg = <0 0xfe9b0000 0 0x8000>; @@ -2231,93 +2589,137 @@ renesas,fcp = <&fcpvi1>; }; - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 610>; - iommus = <&ipmmu_vp1 9>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; + csi20: csi2@fea80000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 623>; + resets = <&cpg 714>; + status = "disabled"; - renesas,fcp = <&fcpvd0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; }; - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; + csi41: csi2@feab0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeab0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 622>; + resets = <&cpg 715>; + status = "disabled"; - renesas,fcp = <&fcpvd1>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 621>; + reg = <1>; - renesas,fcp = <&fcpvd2>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; + csi41vin4: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin4csi41>; + }; + csi41vin5: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin5csi41>; + }; + csi41vin6: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin6csi41>; + }; + csi41vin7: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin7csi41>; + }; + }; + }; }; hdmi0: hdmi@fead0000 { @@ -2342,6 +2744,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2367,6 +2773,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2417,38 +2827,12 @@ }; }; - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>; - }; - thermal-zones { sensor_thermal1: sensor-thermal1 { polling-delay-passive = <250>; @@ -2458,12 +2842,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2484,12 +2868,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2510,12 +2894,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2529,6 +2913,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts index a1d13ccf28..4e960081f9 100644 --- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts @@ -7,3 +7,35 @@ #include "r8a7796-m3ulcb.dts" #include "r8a7796-u-boot.dtsi" + +/ { + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; +}; + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts index 7a8ad27795..44b2f9fb37 100644 --- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts @@ -7,3 +7,31 @@ #include "r8a7796-salvator-x.dts" #include "r8a7796-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts index 62aa27dbfd..052d72acc8 100644 --- a/arch/arm/dts/r8a7796-salvator-x.dts +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Salvator-X board + * Device Tree Source for the Salvator-X board with R-Car M3-W * * Copyright (C) 2016 Renesas Electronics Corp. */ @@ -37,6 +37,11 @@ "dclkin.0", "dclkin.1", "dclkin.2"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1>; /* HDMI0 */ +}; + &hdmi0 { status = "okay"; @@ -47,9 +52,32 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; &hdmi0_con { remote-endpoint = <&rcar_dw_hdmi0_out>; }; + +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a7796-u-boot.dtsi b/arch/arm/dts/r8a7796-u-boot.dtsi index 7cc60bc54a..4655259afe 100644 --- a/arch/arm/dts/r8a7796-u-boot.dtsi +++ b/arch/arm/dts/r8a7796-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7796", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 011f0e596a..bf860f06d6 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the r8a7796 SoC * - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2017 Renesas Electronics Corp. */ #include @@ -57,107 +57,6 @@ clock-frequency = <0>; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; @@ -224,6 +123,107 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -231,13 +231,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -247,6 +240,13 @@ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -259,31 +259,14 @@ clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; @@ -418,100 +401,6 @@ reg = <0 0xe6060000 0 0x50c>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -527,17 +416,27 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7796-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a7796-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; #interrupt-cells = <2>; @@ -554,92 +453,6 @@ resets = <&cpg 407>; }; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; @@ -755,226 +568,19 @@ status = "disabled"; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; + i2c_dvfs: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1066,6 +672,452 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7796-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7796_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7796_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7796-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -1225,440 +1277,382 @@ status = "disabled"; }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; + }; + + drif00: rif@e6f40000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; }; - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; + drif01: rif@e6f50000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; }; - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; + drif10: rif@e6f60000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; + drif11: rif@e6f70000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; + drif20: rif@e6f80000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; status = "disabled"; }; - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + drif21: rif@e6f90000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; status = "disabled"; }; - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; status = "disabled"; }; - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion= <&ohci0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion= <&ohci1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <0>; - status = "disabled"; - }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a7796", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; - }; - rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1853,16 +1847,335 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7796", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7796-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + imr-lx4@fe860000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 823>; + }; + + imr-lx4@fe870000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 822>; }; fdp1@fe940000 { @@ -1883,6 +2196,50 @@ resets = <&cpg 615>; }; + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 607>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 611>; + iommus = <&ipmmu_vc0 19>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; + }; + vspb: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -1894,12 +2251,37 @@ renesas,fcp = <&fcpvb0>; }; - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 607>; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; }; vspi0: vsp@fe9a0000 { @@ -1913,73 +2295,115 @@ renesas,fcp = <&fcpvi0>; }; - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; + csi20: csi2@fea80000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; }; - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 623>; + resets = <&cpg 716>; + status = "disabled"; - renesas,fcp = <&fcpvd0>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 622>; + reg = <1>; - renesas,fcp = <&fcpvd1>; - }; + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; + }; }; hdmi0: hdmi@fead0000 { @@ -2004,6 +2428,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2047,33 +2475,10 @@ }; }; - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; }; thermal-zones { @@ -2085,12 +2490,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2111,12 +2516,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2137,12 +2542,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2156,6 +2561,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index 06002b629a..9e0cd26f40 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -7,3 +7,34 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; + status = "okay"; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/r8a77965-salvator-x.dts b/arch/arm/dts/r8a77965-salvator-x.dts index 75d890d91d..340a3c72b6 100644 --- a/arch/arm/dts/r8a77965-salvator-x.dts +++ b/arch/arm/dts/r8a77965-salvator-x.dts @@ -19,3 +19,31 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x21_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index f0023114d1..cbd29b3aed 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -10,3 +10,112 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77965", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 311>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + #phy-cells = <0>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77965", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + }; +}; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 7a5d68be13..ef8cdc6a16 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -8,8 +8,9 @@ * Copyright (C) 2016 Renesas Electronics Corp. */ -#include +#include #include +#include #define CPG_AUDIO_CLK_I 10 @@ -19,58 +20,16 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; i2c7 = &i2c_dvfs; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc 0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc 1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc 12>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -101,10 +60,47 @@ clock-frequency = <0>; }; - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A77965_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A77965_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A77965_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ clock-frequency = <0>; }; @@ -115,27 +111,6 @@ clock-frequency = <0>; }; - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - pmu_a57 { compatible = "arm,cortex-a57-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -144,28 +119,153 @@ <&a57_1>; }; - soc { + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77965-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc 32>; - resets = <&cpg 408>; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a77965", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; pfc: pin-controller@e6060000 { @@ -188,135 +288,25 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77965-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc 32>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc 32>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc 32>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc 32>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc 32>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc 32>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc 32>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc 32>; - resets = <&cpg 905>; + tsc: thermal@e6198000 { + compatible = "renesas,r8a77965-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; }; intc_ex: interrupt-controller@e61c0000 { @@ -331,10 +321,287 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 407>; }; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77965", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77965-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; @@ -363,7 +630,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; @@ -397,7 +664,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; @@ -431,107 +698,99 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 207>; - status = "disabled"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 206>; - status = "disabled"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc 32>; - resets = <&cpg 310>; - status = "disabled"; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 204>; - status = "disabled"; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77965_PD_A3IR>; + #iommu-cells = <1>; }; - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 203>; - status = "disabled"; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 202>; - status = "disabled"; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77965_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77965_PD_A3VP>; + #iommu-cells = <1>; }; avb: ethernet@e6800000 { @@ -571,7 +830,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; @@ -579,247 +838,489 @@ status = "disabled"; }; - csi20: csi2@fea80000 { - reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - csi40: csi2@feaa0000 { - reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vin0: video@e6ef0000 { - reg = <0 0xe6ef0000 0 0x1000>; - /* placeholder */ - }; - - vin1: video@e6ef1000 { - reg = <0 0xe6ef1000 0 0x1000>; - /* placeholder */ - }; - - vin2: video@e6ef2000 { - reg = <0 0xe6ef2000 0 0x1000>; - /* placeholder */ - }; - - vin3: video@e6ef3000 { - reg = <0 0xe6ef3000 0 0x1000>; - /* placeholder */ - }; - - vin4: video@e6ef4000 { - reg = <0 0xe6ef4000 0 0x1000>; - /* placeholder */ - }; - - vin5: video@e6ef5000 { - reg = <0 0xe6ef5000 0 0x1000>; - /* placeholder */ - }; - - vin6: video@e6ef6000 { - reg = <0 0xe6ef6000 0 0x1000>; - /* placeholder */ - }; - - vin7: video@e6ef7000 { - reg = <0 0xe6ef7000 0 0x1000>; - /* placeholder */ - }; - - ohci0: usb@ee080000 { - reg = <0 0xee080000 0 0x100>; - /* placeholder */ - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion= <&ohci0>; - power-domains = <&sysc 32>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc 32>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion= <&ohci1>; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - reg = <0 0xe6500000 0 0x40>; - /* placeholder */ - }; - - i2c1: i2c@e6508000 { - reg = <0 0xe6508000 0 0x40>; - /* placeholder */ - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0xe6510000 0 0x40>; - /* placeholder */ - }; - - i2c3: i2c@e66d0000 { - reg = <0 0xe66d0000 0 0x40>; - /* placeholder */ - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0xe66d8000 0 0x40>; - /* placeholder */ - }; - - i2c5: i2c@e66e0000 { - reg = <0 0xe66e0000 0 0x40>; - /* placeholder */ - }; - - i2c6: i2c@e66e8000 { - reg = <0 0xe66e8000 0 0x40>; - /* placeholder */ - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc 32>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 8>; #pwm-cells = <2>; - /* placeholder */ + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e32000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e33000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e34000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e35000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; reg = <0 0xe6e36000 0 8>; - /* placeholder */ + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; }; - du: display@feb00000 { - reg = <0 0xfeb00000 0 0x80000>, - <0 0xfeb90000 0 0x14>; - /* placeholder */ + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; - du_out_hdmi0: endpoint { + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; }; }; }; }; - hsusb: usb@e6590000 { - reg = <0 0xe6590000 0 0x100>; - /* placeholder */ + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; }; - pciec0: pcie@fe000000 { - reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; }; - pciec1: pcie@ee800000 { - reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; }; rcar_sound: sound@ec500000 { @@ -850,80 +1351,17 @@ ssi1: ssi-1 { }; }; - }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - #phy-cells = <0>; - status = "disabled"; - }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77965", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77965"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77965"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77965"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77965"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 311>; - status = "disabled"; - }; - - usb3_phy0: usb-phy@e65ee000 { - reg = <0 0xe65ee000 0 0x90>; - #phy-cells = <0>; - /* placeholder */ - }; - - usb3_peri0: usb@ee020000 { - reg = <0 0xee020000 0 0x400>; - /* placeholder */ + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; }; xhci0: usb@ee000000 { @@ -932,14 +1370,541 @@ reg = <0 0xee000000 0 0xc00>; interrupts = ; clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; - wdt0: watchdog@e6020000 { - reg = <0 0xe6020000 0 0x0c>; - /* placeholder */ + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77965-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 615>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 607>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 611>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a77965-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a77965-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + }; + }; + + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a77965-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A77965_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77965"; + reg = <0 0xfeb00000 0 0x80000>; + reg-names = "du"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + status = "disabled"; + + vsps = <&vspd0 0 &vspd1 0 &vspd0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dts index 7ab71a1c65..5b17f1d1f0 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dts +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dts @@ -7,3 +7,48 @@ #include "r8a77970-eagle.dts" #include "r8a77970-u-boot.dtsi" +#include + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + +}; + +&phy0 { + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index 5dcad63492..b6d5332157 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "r8a77970.dtsi" -#include / { model = "Renesas Eagle board based on r8a77970"; @@ -17,7 +16,6 @@ aliases { serial0 = &scif0; ethernet0 = &avb; - spi0 = &rpc; }; chosen { @@ -30,11 +28,57 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + d3p3: regulator-fixed { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + + vcc-supply = <&d3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; }; &avb { - pinctrl-0 = <&avb0_pins>; + pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; + renesas,no-ether-link; phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -45,7 +89,16 @@ reg = <0>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; }; }; @@ -70,14 +123,49 @@ gpio-controller; #gpio-cells = <2>; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; }; i2c0_pins: i2c0 { @@ -91,25 +179,6 @@ }; }; -&rpc { - num-cs = <1>; - status = "okay"; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - - flash0: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - reg = <0>; - status = "okay"; - }; -}; - &rwdt { timeout-sec = <60>; status = "okay"; @@ -121,3 +190,19 @@ status = "okay"; }; + +&du { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index 8fb7fe92db..2903fdb523 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77970", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 8dc599edfa..a0808c90ab 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -38,6 +38,16 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; + power-domains = <&sysc R8A77970_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc R8A77970_PD_CA53_SCU>; @@ -60,11 +70,25 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -72,7 +96,7 @@ clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -80,23 +104,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; @@ -107,75 +114,6 @@ status = "disabled"; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77970", "renesas,rcar-gen3-gpio"; @@ -266,6 +204,32 @@ resets = <&cpg 907>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77970"; + reg = <0 0xe6060000 0 0x504>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; @@ -282,67 +246,6 @@ resets = <&cpg 407>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a77970", "renesas,rcar-gen3-i2c"; @@ -499,6 +402,77 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77970-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77970_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77970", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_rt 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77970", "renesas,rcar-gen3-scif", @@ -570,65 +544,358 @@ status = "disabled"; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; }; - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77970", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77970_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a77970-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77970"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = ; + clocks = <&cpg CPG_MOD 724>; + clock-names = "du.0"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 724>; + vsps = <&vspd0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a77970-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = + <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 8d4ea88a91..b030d5c649 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -7,3 +7,180 @@ #include "r8a77990-ebisu.dts" #include "r8a77990-u-boot.dtsi" + +/ { + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sdhi3_pins: sd2 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + + sdhi3_pins_uhs: sd2_uhs { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi0 { + /* full size SD */ + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; + max-frequency = <208000000>; +}; + +&sdhi1 { + /* microSD */ + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; + max-frequency = <208000000>; +}; + +&sdhi3 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 5e3c195d4c..2bc3a4884b 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -28,24 +28,6 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; }; &avb { @@ -73,10 +55,11 @@ clock-frequency = <48000000>; }; -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; +&ohci0 { + status = "okay"; +}; +&pfc { avb_pins: avb { mux { groups = "avb_link", "avb_mii"; @@ -84,65 +67,35 @@ }; }; - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi3_pins: sd2 { - groups = "sdhi3_data8", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sdhi3_pins_uhs: sd2_uhs { - groups = "sdhi3_data8", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; + usb0_pins: usb { + groups = "usb0_b"; function = "usb0"; }; + + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; }; -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-name = "default"; - - status = "okay"; -}; - -&sdhi0 { - status = "okay"; -}; - -&sdhi1 { - status = "okay"; -}; - -&sdhi3 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; +&rwdt { + timeout-sec = <60>; status = "okay"; }; &scif2 { - pinctrl-0 = <&scif2_pins>; + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&xhci0 { + pinctrl-0 = <&usb30_pins>; pinctrl-names = "default"; status = "okay"; diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 564c258e92..288e57e4bc 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -6,3 +6,37 @@ */ #include "r8a779x-u-boot.dtsi" + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77990", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee100000 0 0x2000>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee120000 0 0x2000>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee160000 0 0x2000>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index ad20ea14cd..ae89260baa 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -18,16 +18,24 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a53_0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0>; + reg = <0>; device_type = "cpu"; power-domains = <&sysc 5>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; + a53_1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + device_type = "cpu"; + power-domains = <&sysc 6>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller-0 { compatible = "cache"; power-domains = <&sysc 21>; @@ -45,8 +53,9 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; }; psci { @@ -61,6 +70,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77990-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc 32>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77990", "renesas,rcar-gen3-gpio"; @@ -166,43 +185,6 @@ resets = <&cpg 906>; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7790", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; @@ -223,40 +205,97 @@ reg = <0 0xe6160000 0 0x0200>; }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee100000 0 0x2000>; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee120000 0 0x2000>; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee160000 0 0x2000>; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - status = "disabled"; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77990-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77990_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77990", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = , , , @@ -310,6 +349,54 @@ status = "disabled"; }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77990", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77990", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -320,7 +407,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; @@ -331,21 +418,13 @@ compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77990", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; }; timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts index 711d487a8e..a8e8f2669d 100644 --- a/arch/arm/dts/r8a77995-draak.dts +++ b/arch/arm/dts/r8a77995-draak.dts @@ -56,6 +56,27 @@ }; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -79,6 +100,12 @@ regulator-boot-on; regulator-always-on; }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -88,7 +115,7 @@ &pfc { avb0_pins: avb { mux { - groups = "avb0_link", "avb0_mdc", "avb0_mii"; + groups = "avb0_link", "avb0_mdio", "avb0_mii"; function = "avb0"; }; }; @@ -139,6 +166,11 @@ groups = "usb0"; function = "usb0"; }; + + vin4_pins_cvbs: vin4 { + groups = "vin4_data8", "vin4_sync", "vin4_clk"; + function = "vin4"; + }; }; &i2c0 { @@ -151,6 +183,77 @@ reg = <0x50>; pagesize = <8>; }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, link it to + * VIN4 here. + */ + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, leave HDMI + * not connected here. + */ + adv7612_out: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; + }; }; &i2c1 { @@ -164,6 +267,11 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x12_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + ports { port@0 { endpoint { @@ -243,3 +351,23 @@ timeout-sec = <60>; status = "okay"; }; + +&vin4 { + pinctrl-0 = <&vin4_pins_cvbs>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin4_in: endpoint { + remote-endpoint = <&adv7180_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index e0852c8df2..1f6efafb8b 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -6,3 +6,13 @@ */ #include "r8a779x-u-boot.dtsi" + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77995", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index 1d49279ac9..1efef62182 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -15,9 +15,11 @@ #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -48,48 +50,29 @@ clock-frequency = <0>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; @@ -100,88 +83,116 @@ status = "disabled"; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - #iommu-cells = <1>; - status = "disabled"; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 9>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - #iommu-cells = <1>; - status = "disabled"; + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - #iommu-cells = <1>; - status = "disabled"; + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - #iommu-cells = <1>; - status = "disabled"; + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 10>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - #iommu-cells = <1>; - status = "disabled"; + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - #iommu-cells = <1>; - status = "disabled"; + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - #iommu-cells = <1>; - status = "disabled"; + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a77995", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 14>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 906>; }; - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - #iommu-cells = <1>; - status = "disabled"; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77995"; + reg = <0 0xe6060000 0 0x508>; }; - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { compatible = "renesas,r8a77995-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -197,22 +208,24 @@ reg = <0 0xe6160000 0 0x0200>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77995-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77995"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; #interrupt-cells = <2>; @@ -229,6 +242,133 @@ resets = <&cpg 407>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77995-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77995", "renesas,rcar-dmac"; @@ -301,173 +441,85 @@ dma-channels = <8>; }; - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 9>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 912>; + #iommu-cells = <1>; }; - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 911>; + #iommu-cells = <1>; }; - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 910>; + #iommu-cells = <1>; }; - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 909>; + #iommu-cells = <1>; }; - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 908>; + #iommu-cells = <1>; }; - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 907>; + #iommu-cells = <1>; }; - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 14>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 906>; + #iommu-cells = <1>; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; + #iommu-cells = <1>; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; + #iommu-cells = <1>; }; - canfd: can@e66c0000 { - compatible = "renesas,r8a77995-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; + #iommu-cells = <1>; }; avb: ethernet@e6800000 { @@ -516,87 +568,35 @@ status = "disabled"; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; + can0: can@e6c30000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; + resets = <&cpg 916>; status = "disabled"; }; - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; + can1: can@e6c38000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 915>; status = "disabled"; }; @@ -640,15 +640,188 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77995"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; }; @@ -665,18 +838,6 @@ status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - usb2_phy0: usb-phy@ee080200 { compatible = "renesas,usb2-phy-r8a77995", "renesas,rcar-gen3-usb2-phy"; @@ -689,6 +850,35 @@ status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77995", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + vspbs: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -699,6 +889,26 @@ renesas,fcp = <&fcpvb0>; }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 622>; + renesas,fcp = <&fcpvd1>; + }; + fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -708,16 +918,6 @@ iommus = <&ipmmu_vp0 5>; }; - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - fcpvd0: fcp@fea27000 { compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; @@ -727,16 +927,6 @@ iommus = <&ipmmu_vi0 8>; }; - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; @@ -781,12 +971,28 @@ }; }; - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77995", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; }; }; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index ce75bd5d28..04902c0bd3 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -150,8 +150,6 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts new file mode 100644 index 0000000000..4af0e4e383 --- /dev/null +++ b/arch/arm/dts/rk3399-ficus.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-ddr3-1600.dtsi" + +/ { + model = "96boards RK3399 Ficus"; + compatible = "vamrs,ficus", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_sys>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 15 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 6e7e1e3528..8304f67192 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -95,6 +95,8 @@ regulator-name = "usbhub_enable"; enable-active-low; gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -146,16 +148,6 @@ regulator-always-on; }; - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-low; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - }; - vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -180,10 +172,7 @@ regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; - - /* for rockchip boot on */ - rockchip,pwm_id= <2>; - rockchip,pwm_voltage = <1000000>; + regulator-init-microvolt = <950000>; }; }; @@ -218,7 +207,8 @@ i2c-scl-falling-time-ns = <4>; clock-frequency = <400000>; - vdd_gpu: fan535555@60 { + vdd_gpu: vdd_gpu { + status = "okay"; compatible = "fcs,fan53555"; reg = <0x60>; vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; @@ -420,7 +410,8 @@ status = "okay"; clock-frequency = <400000>; - vdd_cpu_b: fan53555@60 { + vdd_cpu_b: vdd_cpu_b { + status = "okay"; compatible = "fcs,fan53555"; reg = <0x60>; vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; @@ -503,7 +494,7 @@ &sdmmc { u-boot,dm-pre-reloc; clock-frequency = <150000000>; - clock-freq-min-max = <100000 150000000>; + max-frequency = <40000000>; supports-sd; bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts new file mode 100644 index 0000000000..25c58b4261 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi new file mode 100644 index 0000000000..51644d6d02 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Linaro Ltd. + */ + +#include +#include +#include "rk3399.dtsi" + +/ { + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 0>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + card-detect-delay = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi new file mode 100644 index 0000000000..d14e833d22 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi @@ -0,0 +1,1536 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2018 Manivannan Sadhasivam + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + 0x1d191519 + 0x14040808 + 0x00000002 + 0x00006226 + 0x00000054 + 0x00000000 + 800 + 6 + 2 + 9 + 1 + 0x00000700 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x00001f40 + 0x00000050 + 0x00027100 + 0x00000320 + 0x01001f40 + 0x00000000 + 0x00000101 + 0x00020100 + 0x000000a0 + 0x00000190 + 0x00000000 + 0x06180000 + 0x00061800 + 0x04000618 + 0x33080004 + 0x280f0622 + 0x22330800 + 0x00280f06 + 0x06223308 + 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a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index a55a6c6eb9..21f156782f 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1598,14 +1598,19 @@ drive-strength = <12>; }; - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; }; - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; }; pcfg_pull_up_2ma: pcfg-pull-up-2ma { @@ -1613,14 +1618,52 @@ drive-strength = <2>; }; + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_up_18ma: pcfg-pull-up-18ma { + bias-pull-up; + drive-strength = <18>; + }; + + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_down_8ma: pcfg-pull-down-8ma { + bias-pull-down; + drive-strength = <8>; + }; + pcfg_pull_down_12ma: pcfg-pull-down-12ma { bias-pull-down; drive-strength = <12>; }; - pcfg_pull_none_13ma: pcfg-pull-none-13ma { - bias-disable; - drive-strength = <13>; + pcfg_pull_down_18ma: pcfg-pull-down-18ma { + bias-pull-down; + drive-strength = <18>; + }; + + pcfg_pull_down_20ma: pcfg-pull-down-20ma { + bias-pull-down; + drive-strength = <20>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; }; clock { diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts new file mode 100644 index 0000000000..32b95940b0 --- /dev/null +++ b/arch/arm/dts/rv1108-elgin-r1.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Elgin RV1108 R1 board"; + compatible = "elgin,rv1108-elgin", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&emmc { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi index acfd97e18d..215d885225 100644 --- a/arch/arm/dts/rv1108.dtsi +++ b/arch/arm/dts/rv1108.dtsi @@ -121,8 +121,35 @@ }; grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon"; + compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; reg = <0x10300000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rv1108-usb2phy"; + reg = <0x100 0x0c>; + clocks = <&cru SCLK_USBPHY>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usbphy"; + rockchip,usbgrf = <&usbgrf>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = ; + interrupt-names = "otg-mux"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; saradc: saradc@1038c000 { @@ -141,6 +168,11 @@ reg = <0x20060000 0x1000>; }; + usbgrf: syscon@202a0000 { + compatible = "rockchip,rv1108-usbgrf", "syscon"; + reg = <0x202a0000 0x1000>; + }; + cru: clock-controller@20200000 { compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; @@ -200,12 +232,19 @@ }; usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb", + compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x30180000 0x40000>; interrupts = ; - hnp-srp-disable; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -427,6 +466,35 @@ }; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index a36e0ebca0..7d3d866a00 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for common parts of Salvator-X board variants * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* @@ -36,7 +33,7 @@ / { aliases { serial0 = &scif2; - serial1 = &scif1; + serial1 = &hscif1; ethernet0 = &avb; }; @@ -66,6 +63,29 @@ enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; }; + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + reg_1p8v: regulator0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -93,20 +113,12 @@ regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; + sound_card: sound { + compatible = "audio-graph-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; + label = "rcar-sound"; - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; + dais = <&rsnd_port0>; }; vbus0_usb2: regulator-vbus0-usb2 { @@ -268,6 +280,37 @@ }; }; +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&adv7482_txb>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -295,6 +338,15 @@ clock-frequency = <32768>; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -322,6 +374,12 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; + + port { + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; }; cs2000: clk_multiplier@4f { @@ -359,6 +417,55 @@ shunt-resistor-micro-ohms = <5000>; }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70>; + + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gpio6>; + interrupt-names = "intrq1", "intrq2"; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + + port@b { + reg = <11>; + + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; + }; + }; }; &i2c_dvfs { @@ -376,6 +483,8 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-level; regulators { dvfs: dvfs { @@ -387,6 +496,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &ohci0 { @@ -416,12 +531,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; @@ -437,6 +552,11 @@ function = "du"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + i2c2_pins: i2c2 { groups = "i2c2_a"; function = "i2c2"; @@ -480,13 +600,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; - power-source = <1800>; + power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -581,10 +701,18 @@ <&audio_clk_c>, <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; + ports { + rsnd_port0: port@0 { + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4613_endpoint>; + + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; }; }; }; @@ -594,7 +722,8 @@ pinctrl-names = "default"; uart-has-rtscts; - status = "okay"; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ }; &scif2 { @@ -689,7 +818,39 @@ clock-frequency = <100000000>; }; -&wdt0 { +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&rwdt { timeout-sec = <60>; status = "okay"; }; diff --git a/arch/arm/dts/salvator-x.dtsi b/arch/arm/dts/salvator-x.dtsi index 468868c8ed..ddee50e646 100644 --- a/arch/arm/dts/salvator-x.dtsi +++ b/arch/arm/dts/salvator-x.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "salvator-common.dtsi" @@ -20,6 +17,8 @@ }; &i2c4 { + clock-frequency = <400000>; + versaclock5: clock-generator@6a { compatible = "idt,5p49v5923"; reg = <0x6a>; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 314449478d..2458d6707d 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera + * Copyright (C) 2012 Altera */ -#include "skeleton.dtsi" #include / { @@ -11,34 +10,26 @@ #size-cells = <1>; aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; timer1 = &timer1; timer2 = &timer2; timer3 = &timer3; - spi0 = &qspi; - spi1 = &spi0; - spi2 = &spi1; }; cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-smp"; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; @@ -46,6 +37,15 @@ }; }; + pmu: pmu@ff111000 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 176 4>, <0 177 4>; + interrupt-affinity = <&cpu0>, <&cpu1>; + reg = <0xff111000 0x1000>, + <0xff113000 0x1000>; + }; + intc: intc@fffed000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -63,7 +63,7 @@ ranges; amba { - compatible = "arm,amba-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -87,6 +87,14 @@ }; }; + base_fpga_region { + compatible = "fpga-region"; + fpga-mgr = <&fpgamgr0>; + + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + can0: can@ffc00000 { compatible = "bosch,d_can"; reg = <0xffc00000 0x1000>; @@ -131,7 +139,7 @@ compatible = "fixed-clock"; }; - main_pll: main_pll { + main_pll: main_pll@40 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -139,7 +147,7 @@ clocks = <&osc1>; reg = <0x40>; - mpuclk: mpuclk { + mpuclk: mpuclk@48 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -147,7 +155,7 @@ reg = <0x48>; }; - mainclk: mainclk { + mainclk: mainclk@4c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -155,29 +163,29 @@ reg = <0x4C>; }; - dbg_base_clk: dbg_base_clk { + dbg_base_clk: dbg_base_clk@50 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; + clocks = <&main_pll>, <&osc1>; div-reg = <0xe8 0 9>; reg = <0x50>; }; - main_qspi_clk: main_qspi_clk { + main_qspi_clk: main_qspi_clk@54 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; reg = <0x54>; }; - main_nand_sdmmc_clk: main_nand_sdmmc_clk { + main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; reg = <0x58>; }; - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; @@ -185,7 +193,7 @@ }; }; - periph_pll: periph_pll { + periph_pll: periph_pll@80 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -193,42 +201,42 @@ clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; reg = <0x80>; - emac0_clk: emac0_clk { + emac0_clk: emac0_clk@88 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x88>; }; - emac1_clk: emac1_clk { + emac1_clk: emac1_clk@8c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x8C>; }; - per_qspi_clk: per_qsi_clk { + per_qspi_clk: per_qsi_clk@90 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x90>; }; - per_nand_mmc_clk: per_nand_mmc_clk { + per_nand_mmc_clk: per_nand_mmc_clk@94 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x94>; }; - per_base_clk: per_base_clk { + per_base_clk: per_base_clk@98 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; reg = <0x98>; }; - h2f_usr1_clk: h2f_usr1_clk { + h2f_usr1_clk: h2f_usr1_clk@9c { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&periph_pll>; @@ -236,7 +244,7 @@ }; }; - sdram_pll: sdram_pll { + sdram_pll: sdram_pll@c0 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; @@ -244,28 +252,28 @@ clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; reg = <0xC0>; - ddr_dqs_clk: ddr_dqs_clk { + ddr_dqs_clk: ddr_dqs_clk@c8 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xC8>; }; - ddr_2x_dqs_clk: ddr_2x_dqs_clk { + ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xCC>; }; - ddr_dq_clk: ddr_dq_clk { + ddr_dq_clk: ddr_dq_clk@d0 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; reg = <0xD0>; }; - h2f_usr2_clk: h2f_usr2_clk { + h2f_usr2_clk: h2f_usr2_clk@d4 { #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&sdram_pll>; @@ -312,7 +320,7 @@ l3_sp_clk: l3_sp_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; + clocks = <&l3_mp_clk>; div-reg = <0x64 2 2>; }; @@ -343,7 +351,7 @@ dbg_clk: dbg_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; + clocks = <&dbg_at_clk>; div-reg = <0x68 2 2>; clk-gate = <0x60 5>; }; @@ -446,6 +454,14 @@ clk-phase = <0 135>; }; + sdmmc_clk_divided: sdmmc_clk_divided { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&sdmmc_clk>; + clk-gate = <0xa0 8>; + fixed-divider = <4>; + }; + nand_x_clk: nand_x_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; @@ -453,10 +469,17 @@ clk-gate = <0xa0 9>; }; + nand_ecc_clk: nand_ecc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&nand_x_clk>; + clk-gate = <0xa0 9>; + }; + nand_clk: nand_clk { #clock-cells = <0>; compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clocks = <&nand_x_clk>; clk-gate = <0xa0 10>; fixed-divider = <4>; }; @@ -467,8 +490,58 @@ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + ddr_dqs_clk_gate: ddr_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dqs_clk>; + clk-gate = <0xd8 0>; + }; + + ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_2x_dqs_clk>; + clk-gate = <0xd8 1>; + }; + + ddr_dq_clk_gate: ddr_dq_clk_gate { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&ddr_dq_clk>; + clk-gate = <0xd8 2>; + }; + + h2f_user2_clk: h2f_user2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr2_clk>; + clk-gate = <0xd8 3>; + }; + }; - }; + }; + + fpga_bridge0: fpga_bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + + fpga_bridge1: fpga_bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + + fpgamgr0: fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x4>; + interrupts = <0 175 4>; + }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; @@ -477,12 +550,14 @@ interrupts = <0 115 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; + clocks = <&emac_0_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -493,60 +568,14 @@ interrupts = <0 120 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; + clocks = <&emac_1_clk>; clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; snps,multicast-filter-bins = <256>; snps,perfect-filter-entries = <128>; - status = "disabled"; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C0_RESET>; - reset-names = "i2c"; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C1_RESET>; - reset-names = "i2c"; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C2_RESET>; - reset-names = "i2c"; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - clocks = <&l4_sp_clk>; - resets = <&rst I2C3_RESET>; - reset-names = "i2c"; - interrupts = <0 161 0x4>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <4096>; status = "disabled"; }; @@ -555,12 +584,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -576,12 +604,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -597,12 +624,11 @@ #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; - clocks = <&per_base_clk>; + clocks = <&l4_mp_clk>; status = "disabled"; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; - bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; @@ -613,15 +639,68 @@ }; }; - sdr: sdr@ffc25000 { - compatible = "syscon"; - reg = <0xffc25000 0x1000>; + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + resets = <&rst I2C0_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; }; - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + resets = <&rst I2C1_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + resets = <&rst I2C2_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + resets = <&rst I2C3_RESET>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + eccmgr: eccmgr { + compatible = "altr,socfpga-ecc-manager"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + l2-ecc@ffd08140 { + compatible = "altr,socfpga-l2-ecc"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocram-ecc@ffd08144 { + compatible = "altr,socfpga-ocram-ecc"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; }; L2: l2-cache@fffef000 { @@ -632,36 +711,89 @@ cache-level = <2>; arm,tag-latency = <1 1 1>; arm,data-latency = <2 1 1>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <0>; + arm,prefetch-offset = <7>; }; - mmc0: dwmmc0@ff704000 { + l3regs@0xff800000 { + compatible = "altr,l3regs", "syscon"; + reg = <0xff800000 0x1000>; + }; + + mmc: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; fifo-depth = <0x400>; #address-cells = <1>; #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + status = "disabled"; + }; + + nand0: nand@ff900000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xff900000 0x100000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0x0 0x90 0x4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; + status = "disabled"; + }; + + ocram: sram@ffff0000 { + compatible = "mmio-sram"; + reg = <0xffff0000 0x10000>; }; qspi: spi@ff705000 { - compatible = "cadence,qspi"; - #address-cells = <1>; + compatible = "cdns,qspi-nor"; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; + <0xffa00000 0x1000>; interrupts = <0 151 4>; - clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; cdns,fifo-depth = <128>; cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; - bus-num = <2>; + clocks = <&qspi_clk>; status = "disabled"; }; + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + altr,modrst-offset = <0x10>; + }; + + scu: snoop-control-unit@fffec000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xfffec000 0x100>; + }; + + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + spi0: spi@fff00000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; @@ -669,10 +801,7 @@ reg = <0xfff00000 0x1000>; interrupts = <0 154 4>; num-cs = <4>; - bus-num = <0>; - tx-dma-channel = <&pdma 16>; - rx-dma-channel = <&pdma 17>; - clocks = <&per_base_clk>; + clocks = <&spi_m_clk>; status = "disabled"; }; @@ -681,20 +810,22 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfff01000 0x1000>; - interrupts = <0 156 4>; + interrupts = <0 155 4>; num-cs = <4>; - bus-num = <1>; - tx-dma-channel = <&pdma 20>; - rx-dma-channel = <&pdma 21>; - clocks = <&per_base_clk>; + clocks = <&spi_m_clk>; status = "disabled"; }; + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf04>; + interrupts = <1 13 0xf01>; clocks = <&mpu_periph_clk>; }; @@ -704,6 +835,8 @@ reg = <0xffc08000 0x1000>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; }; timer1: timer1@ffc09000 { @@ -712,6 +845,8 @@ reg = <0xffc09000 0x1000>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; }; timer2: timer2@ffd00000 { @@ -720,6 +855,8 @@ reg = <0xffd00000 0x1000>; clocks = <&osc1>; clock-names = "timer"; + resets = <&rst OSC1TIMER0_RESET>; + reset-names = "timer"; }; timer3: timer3@ffd01000 { @@ -728,6 +865,8 @@ reg = <0xffd01000 0x1000>; clocks = <&osc1>; clock-names = "timer"; + resets = <&rst OSC1TIMER1_RESET>; + reset-names = "timer"; }; uart0: serial0@ffc02000 { @@ -737,7 +876,9 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; - clock-frequency = <100000000>; + dmas = <&pdma 28>, + <&pdma 29>; + dma-names = "tx", "rx"; }; uart1: serial1@ffc03000 { @@ -747,16 +888,12 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; - clock-frequency = <100000000>; + dmas = <&pdma 30>, + <&pdma 31>; + dma-names = "tx", "rx"; }; - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; - - usbphy0: usbphy@0 { + usbphy0: usbphy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; status = "okay"; @@ -768,6 +905,8 @@ interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -779,6 +918,8 @@ interrupts = <0 128 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -799,10 +940,5 @@ clocks = <&osc1>; status = "disabled"; }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; }; }; diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 46f2fd4b69..2c5249c1eb 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -748,7 +748,7 @@ }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor", "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi index b117383d75..22dbf07afc 100644 --- a/arch/arm/dts/socfpga_arria5.dtsi +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation */ /dts-v1/; @@ -19,13 +19,10 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - drvsel = <3>; - smplsel = <0>; }; sysmgr@ffd08000 { @@ -33,3 +30,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..c44d1ee2fa --- /dev/null +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2013 Altera Corporation + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 6f4de2f563..90e676e701 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2013 Altera Corporation */ #include "socfpga_arria5.dtsi" @@ -10,22 +10,44 @@ compatible = "altr,socfpga-arria5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; aliases { - /* this allow the ethaddr uboot environment variable contents - * to be added to the gmac1 device tree blob. - */ + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ ethernet0 = &gmac1; - udc0 = &usb1; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&porta 0 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 11 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&porta 17 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&porta 18 1>; + }; }; regulator_3_3v: 3-3-v-regulator { @@ -34,10 +56,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { @@ -54,8 +72,28 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; @@ -72,35 +110,42 @@ &mmc0 { vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; - bus-width = <4>; - u-boot,dm-pre-reloc; -}; - -&usb1 { status = "okay"; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q00@0 { - u-boot,dm-pre-reloc; + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; }; }; -&uart0 { - u-boot,dm-pre-reloc; +&usb1 { + status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 8f356cb580..319a71e41e 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012 Altera Corporation */ /dts-v1/; @@ -19,13 +19,10 @@ }; mmc0: dwmmc0@ff704000 { - num-slots = <1>; broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - drvsel = <3>; - smplsel = <0>; }; sysmgr@ffd08000 { @@ -33,3 +30,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index 139a70f265..a387071674 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -47,9 +47,20 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; - bus-width = <4>; u-boot,dm-pre-reloc; }; @@ -61,3 +72,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi new file mode 100644 index 0000000000..08d81da169 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index d504150edd..67076e1b1c 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -1,32 +1,43 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright Altera Corporation (C) 2015 + * Copyright Altera Corporation (C) 2015. All rights reserved. */ #include "socfpga_cyclone5.dtsi" / { - model = "Terasic DE0-Nano(Atlas)"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + model = "Terasic DE-0(Atlas)"; + compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - aliases { - ethernet0 = &gmac1; - udc0 = &usb1; - }; - - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - soc { - u-boot,dm-pre-reloc; + aliases { + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 24 0>; + linux,default-trigger = "heartbeat"; + }; }; }; @@ -34,14 +45,20 @@ status = "okay"; phy-mode = "rgmii"; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - txen-skew-ps = <0>; - txc-skew-ps = <1860>; - rxdv-skew-ps = <420>; - rxc-skew-ps = <1680>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + + max-frame-size = <3800>; }; &gpio0 { @@ -58,8 +75,9 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; - dxl345: adxl345@0 { + adxl345: adxl345@53 { compatible = "adi,adxl345"; reg = <0x53>; @@ -69,14 +87,15 @@ }; &mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&uart0 { status = "okay"; - u-boot,dm-pre-reloc; }; &usb1 { status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index d4dd9e9bca..e9105743ea 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -58,6 +58,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; @@ -70,3 +82,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index f62292284d..4f076bce93 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; @@ -68,3 +80,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 4e94d86114..b7054bfd5a 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -55,6 +55,10 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + &i2c0 { status = "okay"; @@ -107,3 +111,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi new file mode 100644 index 0000000000..9436e0fa8b --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2012 Altera Corporation + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&can0 { + status = "okay"; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index c28be67bb9..6f138b2b26 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -1,31 +1,53 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012 Altera Corporation */ #include "socfpga_cyclone5.dtsi" / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; aliases { - /* this allow the ethaddr uboot environment variable contents + /* this allow the ethaddr uboot environmnet variable contents * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; - udc0 = &usb1; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 15 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 14 1>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 13 1>; + }; + + hps3 { + label = "hps_led3"; + gpios = <&portb 12 1>; + }; }; regulator_3_3v: 3-3-v-regulator { @@ -34,10 +56,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; +}; - soc { - u-boot,dm-pre-reloc; - }; +&can0 { + status = "okay"; }; &gmac1 { @@ -68,6 +90,14 @@ &i2c0 { status = "okay"; + clock-frequency = <100000>; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; eeprom@51 { compatible = "atmel,24c32"; @@ -82,39 +112,55 @@ }; &mmc0 { - status = "okay"; - u-boot,dm-pre-reloc; - cd-gpios = <&portb 18 0>; vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; + status = "okay"; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; flash0: n25q00@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ + compatible = "n25q00"; + reg = <0>; /* chip select */ spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + +&spi0 { + status = "okay"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <1000000>; }; }; &usb1 { status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi new file mode 100644 index 0000000000..648f1bd01d --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2013 Steffen Trumtrar + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index c7a6cf2db8..c155ff02eb 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -1,32 +1,121 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Steffen Trumtrar + * Copyright (C) 2013 Steffen Trumtrar */ #include "socfpga_cyclone5.dtsi" / { model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - aliases { - ethernet0 = &gmac1; - udc0 = &usb1; - }; - - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - soc { - u-boot,dm-pre-reloc; + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:blue:led0"; + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:blue:led1"; + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led2 { + label = "hps:blue:led2"; + gpios = <&portb 26 0>; /* HPS_GPIO55 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:blue:led3"; + gpios = <&portb 27 0>; /* HPS_GPIO56 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&portc 20 0>; /* HPS_GPI7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; /* SW_LID */ + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&portc 19 0>; /* HPS_GPI6 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x5>; /* SW_DOCK */ + }; + + hps_sw2 { + label = "hps_sw2"; + gpios = <&portc 18 0>; /* HPS_GPI5 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ + }; + + hps_sw3 { + label = "hps_sw3"; + gpios = <&portc 17 0>; /* HPS_GPI4 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xc>; /* SW_ROTATE_LOCK */ + }; + + hps_hkey0 { + label = "hps_hkey0"; + gpios = <&portc 21 1>; /* HPS_GPI8 */ + linux,code = <187>; /* KEY_F17 */ + }; + + hps_hkey1 { + label = "hps_hkey1"; + gpios = <&portc 22 1>; /* HPS_GPI9 */ + linux,code = <188>; /* KEY_F18 */ + }; + + hps_hkey2 { + label = "hps_hkey2"; + gpios = <&portc 23 1>; /* HPS_GPI10 */ + linux,code = <189>; /* KEY_F19 */ + }; + + hps_hkey3 { + label = "hps_hkey3"; + gpios = <&portc 24 1>; /* HPS_GPI11 */ + linux,code = <190>; /* KEY_F20 */ + }; + }; + + regulator_3_3v: vcc3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; }; @@ -44,46 +133,50 @@ rxc-skew-ps = <2000>; }; -&gpio0 { +&gpio0 { /* GPIO 0..29 */ status = "okay"; }; -&gpio1 { +&gpio1 { /* GPIO 30..57 */ status = "okay"; }; -&gpio2 { +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; -&i2c0 { +&i2c1 { status = "okay"; - rtc: rtc@68 { - compatible = "stm,m41t82"; - reg = <0x68>; + accel1: accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; }; }; &mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; status = "okay"; - u-boot,dm-pre-reloc; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q00@0 { - u-boot,dm-pre-reloc; + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q00"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; @@ -94,7 +187,3 @@ &usb1 { status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi new file mode 100644 index 0000000000..31bd1dba0f --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2014 Steffen Trumtrar + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q256a", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&usb1 { + status = "okay"; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 8cde9906a0..93c3fa4a48 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Steffen Trumtrar + * Copyright (C) 2014 Steffen Trumtrar */ #include "socfpga_cyclone5.dtsi" @@ -9,83 +9,88 @@ model = "EBV SOCrates"; compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + aliases { + ethernet0 = &gmac1; + }; + chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - aliases { - /* - * This allows the ethaddr uboot environment variable - * contents to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - udc0 = &usb1; - }; - - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - soc { - u-boot,dm-pre-reloc; + leds: gpio-leds { }; }; &gmac1 { - status = "okay"; phy-mode = "rgmii"; + status = "okay"; +}; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; }; &i2c0 { status = "okay"; rtc: rtc@68 { - compatible = "stm,m41t82"; + compatible = "st,m41t82"; reg = <0x68>; }; }; -&mmc0 { +&leds { + compatible = "gpio-leds"; + + led0 { + label = "led:green:heartbeat"; + gpios = <&porta 28 1>; + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "led:green:D7"; + gpios = <&portb 19 1>; + }; + + led2 { + label = "led:green:D8"; + gpios = <&portb 25 1>; + }; +}; + +&mmc { status = "okay"; - u-boot,dm-pre-reloc; }; &qspi { status = "okay"; + u-boot,dm-pre-reloc; - flash0: n25q00@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + status = "okay"; + u-boot,dm-pre-reloc; }; }; - -&usb1 { - disable-over-current; - status = "okay"; -}; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 86c61fe081..6a6c29be79 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -50,6 +50,18 @@ status = "okay"; }; +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + &i2c0 { status = "okay"; speed-mode = <0>; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi new file mode 100644 index 0000000000..360b946ba2 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * U-Boot additions + * + * Copyright (C) 2015 Marek Vasut + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb0; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; + + n25q128@0 { + compatible = "n25q128", "spi-flash"; + u-boot,dm-pre-reloc; + }; + n25q00@1 { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index 85ab56379f..355b3dbf43 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,100 +1,238 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) /* * Copyright (C) 2015 Marek Vasut */ #include "socfpga_cyclone5.dtsi" +#include +#include / { model = "samtec VIN|ING FPGA"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "earlyprintk"; stdout-path = "serial0:115200n8"; }; - aliases { - ethernet0 = &gmac1; - udc0 = &usb0; - }; - - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - soc { - u-boot,dm-pre-reloc; + aliases { + /* + * This allow the ethaddr uboot environment variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + ethernet1 = &gmac0; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_temp0 { + label = "BTN_0"; /* TEMP_OS */ + gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */ + linux,code = ; + }; + + hps_hkey0 { + label = "BTN_1"; /* DIS_PWR */ + gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */ + linux,code = ; + }; + + hps_hkey1 { + label = "hps_hkey1"; /* POWER_DOWN */ + gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ + linux,code = ; + }; + }; + + regulator-usb-nrst { + compatible = "regulator-fixed"; + regulator-name = "usb_nrst"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; }; }; &gmac1 { status = "okay"; phy-mode = "rgmii"; + phy-handle = <&phy1>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <10000 10000 10000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + }; + }; }; -&gpio0 { +&gpio0 { /* GPIO 0..29 */ status = "okay"; }; -&gpio1 { +&gpio1 { /* GPIO 30..57 */ status = "okay"; }; -&gpio2 { +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; &i2c0 { status = "okay"; - rtc: rtc@68 { - compatible = "stm,m41t82"; - reg = <0x68>; + gpio: pca9557@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + temp: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + at24@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + + i2cswitch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@6 { /* Backplane EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@7 { /* Power board EEPROM */ + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + eeprom@51 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + at24@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; }; }; &qspi { status = "okay"; - u-boot,dm-pre-reloc; - flash0: n25q128@0 { - u-boot,dm-pre-reloc; + n25q128@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128", "spi-flash"; - reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q128"; + reg = <0>; /* chip select */ + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; }; - flash1: n25q00@1 { - u-boot,dm-pre-reloc; + n25q00@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00", "spi-flash"; - reg = <1>; /* chip select */ - spi-max-frequency = <50000000>; + compatible = "n25q00"; + reg = <1>; /* chip select */ + spi-max-frequency = <100000000>; m25p,fast-read; - page-size = <256>; - block-size = <16>; /* 2^16, 64KB */ + + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; @@ -103,13 +241,11 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { + dr_mode = "peripheral"; status = "okay"; }; - -&uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index f8b7701167..7a9b742d36 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -365,6 +365,14 @@ usb33d-supply = <&usb33>; }; +&hwspinlock { + status = "okay"; +}; + +&pinctrl { + hwlocks = <&hwspinlock 0>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 33c5981869..37cadfa30c 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -690,6 +690,15 @@ status = "disabled"; }; + hwspinlock: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwspinlock"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index bceac09154..98bd5dfc70 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -26,7 +26,7 @@ }; qspi: spi@80203000 { - compatible = "cadence,qspi"; + compatible = "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0x80203000 0x100>, diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts index f3b4e93ece..6cb2b7f0c8 100644 --- a/arch/arm/dts/sun50i-a64-amarula-relic.dts +++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts @@ -22,11 +22,11 @@ stdout-path = "serial0:115200n8"; }; - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ }; }; @@ -34,10 +34,34 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dcdc1>; + /* + * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but + * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with + * 0Ohm register to vcc-io-wifi so eldo1 is used. + */ + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */ + interrupt-names = "host-wake"; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; cap-mmc-hw-reset; @@ -48,9 +72,138 @@ status = "okay"; }; +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ + }; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi-dsi-sensor"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "dovdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; @@ -61,5 +214,6 @@ &usbphy { usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus-supply = <®_drivevbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index 0716b14411..ef1c90401b 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -86,6 +97,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -103,6 +118,17 @@ status = "okay"; }; +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -151,7 +177,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; + pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; vmmc-supply = <®_dcdc1>; bus-width = <8>; non-removable; @@ -296,9 +322,13 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts index e2dce48fa2..31884dbc88 100644 --- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts +++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts @@ -51,12 +51,44 @@ compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "nanopi-a64:blue:status"; + gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -67,6 +99,26 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + /* i2c1 connected with gpio headers like pine64, bananapi */ &i2c1 { pinctrl-names = "default"; @@ -78,6 +130,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -88,6 +147,24 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: wifi@1 { + reg = <1>; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; +}; + &ohci0 { status = "okay"; }; @@ -125,9 +202,9 @@ ®_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; ®_dcdc2 { @@ -195,9 +272,13 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index 3b3081b10e..f7a4bccaa5 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -51,6 +51,7 @@ compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -58,12 +59,74 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ + status = "okay"; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; }; +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdc1>; + allwinner,tx-delay-ps = <600>; + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -92,6 +155,14 @@ }; }; +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -100,6 +171,7 @@ reg = <0x3a3>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ }; }; @@ -142,10 +214,14 @@ /* DCDC3 is polyphased with DCDC2 */ +/* + * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal + * 1.35V that the PMIC can drive. + */ ®_dcdc5 { regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; regulator-name = "vcc-ddr3"; }; @@ -180,6 +256,11 @@ regulator-name = "vcc-wifi-io"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_eldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -214,8 +295,24 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + status = "okay"; + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; +}; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index bf42690a33..b0c64f7579 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -1,5 +1,6 @@ /* * Copyright (C) 2017 Jagan Teki + * Copyright (C) 2017-2018 Samuel Holland * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -51,23 +52,127 @@ compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; }; chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status { + label = "orangepi:green:status"; + gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */ + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */ + status = "okay"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; }; &ehci1 { status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_gmac_3v3>; + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { status = "okay"; }; @@ -89,9 +194,8 @@ #include "axp803.dtsi" ®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; regulator-name = "afvcc-csi"; }; @@ -163,12 +267,23 @@ regulator-name = "vcc-wifi-io"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + ®_eldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-name = "cpvdd"; }; +®_eldo3 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi"; +}; + ®_fldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -191,13 +306,65 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + m25p,fast-read; + status = "okay"; + }; +}; + +/* On debug connector */ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* Bluetooth */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +/* On Pi-2 connector, RTS/CTS optional */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +/* On Pi-2 connector, RTS/CTS optional */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; status = "okay"; }; &usbphy { + usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; - diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts new file mode 100644 index 0000000000..72d6961dc3 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2018 ARM Ltd. + */ + +#include "sun50i-a64-sopine-baseboard.dts" + +/ { + model = "Pine64 LTS"; + compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", + "allwinner,sun50i-a64"; +}; diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts index a75825798a..c077b6c1f4 100644 --- a/arch/arm/dts/sun50i-a64-pine64.dts +++ b/arch/arm/dts/sun50i-a64-pine64.dts @@ -62,6 +62,21 @@ chosen { stdout-path = "serial0:115200n8"; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&de { + status = "okay"; }; &ehci0 { @@ -82,6 +97,17 @@ }; +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -229,6 +255,10 @@ regulator-name = "vcc-rtc"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + /* On Euler connector */ &spdif { status = "disabled"; @@ -237,7 +267,7 @@ /* On Exp and Euler connectors */ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi new file mode 100644 index 0000000000..a99b7171d0 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Vasily Khoruzhick + * + */ + +/* The ANX6345 eDP-bridge is on r_i2c */ +&r_i2c { + anx6345: edp-bridge@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts new file mode 100644 index 0000000000..ec537c5297 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2018 Vasily Khoruzhick + * + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include +#include +#include + +/ { + model = "Pinebook"; + compatible = "pine64,pinebook", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + ethernet0 = &rtl8723cs; + }; + + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 0>; + brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; + default-brightness-level = <2>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + framebuffer-lcd { + panel-supply = <®_dc1sw>; + dvdd25-supply = <®_dldo2>; + dvdd12-supply = <®_fldo1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + lid_switch { + label = "Lid Switch"; + gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; +}; + +&ehci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + phys = <&usbphy 0>; + phy-names = "usb"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* The ANX6345 eDP-bridge is on r_i2c */ +&r_i2c { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pl89_pins>; + status = "okay"; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-csi"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-edp"; +}; + +®_dldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd-1v8-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; +}; + +&usbphy { + usb0_vbus-supply = <®_ldo_io0>; + usb1_vbus-supply = <®_ldo_io0>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts index abe179de35..53fcc9098d 100644 --- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts @@ -61,6 +61,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + reg_vcc1v8: vcc1v8 { compatible = "regulator-fixed"; regulator-name = "vcc1v8"; @@ -69,6 +80,10 @@ }; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -86,6 +101,17 @@ status = "okay"; }; +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -134,9 +160,13 @@ regulator-name = "vcc-wifi"; }; +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi index 43418bd881..6723b8695e 100644 --- a/arch/arm/dts/sun50i-a64-sopine.dtsi +++ b/arch/arm/dts/sun50i-a64-sopine.dtsi @@ -45,6 +45,8 @@ #include "sun50i-a64.dtsi" +#include + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -52,6 +54,7 @@ non-removable; disable-wp; bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; }; @@ -66,6 +69,18 @@ }; }; +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + #include "axp803.dtsi" ®_aldo2 { diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..ff41abc96a 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -43,9 +43,12 @@ */ #include +#include #include #include #include +#include +#include / { interrupt-parent = <&gic>; @@ -57,17 +60,21 @@ #size-cells = <1>; ranges; -/* - * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. - * However there is no support for this clock on A64 yet, so we depend - * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. - */ simplefb_lcd: framebuffer-lcd { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer0-lcd0"; clocks = <&ccu CLK_TCON0>, - <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; + <&display_clocks CLK_MIXER0>; + status = "disabled"; + }; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-hdmi"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; status = "disabled"; }; }; @@ -81,6 +88,7 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -88,6 +96,7 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -95,6 +104,7 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -102,7 +112,20 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; + next-level-cache = <&L2>; }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + de: display-engine { + compatible = "allwinner,sun50i-a64-display-engine"; + allwinner,pipelines = <&mixer0>, + <&mixer1>; + status = "disabled"; }; osc24M: osc24M_clk { @@ -168,10 +191,93 @@ #size-cells = <1>; ranges; + de2@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@100000 { + compatible = "allwinner,sun50i-a64-de2-mixer-0"; + reg = <0x100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@200000 { + compatible = "allwinner,sun50i-a64-de2-mixer-1"; + reg = <0x200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon1: endpoint { + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; + }; + }; + }; + syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-controller", + compatible = "allwinner,sun50i-a64-system-control", "syscon"; reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x28000>; + + de2_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c"; + reg = <0x0000 0x28000>; + }; + }; }; dma: dma-controller@1c02000 { @@ -185,6 +291,75 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun50i-a64-tcon-lcd", + "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun50i-a64-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + reg = <0>; + + tcon1_in_mixer1: endpoint { + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + }; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; @@ -227,6 +402,11 @@ #size-cells = <0>; }; + sid: eeprom@1c14000 { + compatible = "allwinner,sun50i-a64-sid"; + reg = <0x1c14000 0x400>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; @@ -356,7 +536,7 @@ }; mmc2_pins: mmc2-pins { - pins = "PC1", "PC5", "PC6", "PC8", "PC9", + pins = "PC5", "PC6", "PC8", "PC9", "PC10","PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; function = "mmc2"; @@ -364,6 +544,18 @@ bias-pull-up; }; + mmc2_ds_pin: mmc2-ds-pin { + pins = "PC1"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + pwm_pin: pwm_pin { + pins = "PD22"; + function = "pwm"; + }; + rmii_pins: rmii_pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; @@ -394,7 +586,7 @@ function = "spi1"; }; - uart0_pins_a: uart0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; }; @@ -474,15 +666,6 @@ status = "disabled"; }; - pwm: pwm@1c21400 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01c21400 0x8>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -617,8 +800,6 @@ clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; mdio: mdio { compatible = "snps,dwmac-mdio"; @@ -638,11 +819,69 @@ #interrupt-cells = <3>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun50i-a64-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon1: endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu 7>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = , ; + clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; }; r_intc: interrupt-controller@1f00c00 { @@ -664,6 +903,29 @@ #reset-cells = <1>; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01f03800 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -675,6 +937,16 @@ interrupt-controller; #interrupt-cells = <3>; + r_i2c_pl89_pins: r-i2c-pl89-pins { + pins = "PL8", "PL9"; + function = "s_i2c"; + }; + + r_pwm_pin: pwm { + pins = "PL10"; + function = "s_pwm"; + }; + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb"; diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 98862c7c72..3e0d5a9c09 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -207,6 +207,18 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts index e79cf3baf4..1238de25a9 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts @@ -105,7 +105,6 @@ }; }; -/* &spi0 { status = "okay"; @@ -117,7 +116,6 @@ spi-max-frequency = <40000000>; }; }; -*/ &ohci0 { status = "okay"; diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts new file mode 100644 index 0000000000..e098a2475f --- /dev/null +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2018 Jagan Teki + */ + +#include "sun50i-h6-orangepi.dtsi" + +/ { + model = "OrangePi Lite2"; + compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; +}; diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts index 0612c19cd9..12e17567ab 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts @@ -4,147 +4,9 @@ * Author: Jagan Teki */ -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include +#include "sun50i-h6-orangepi.dtsi" / { model = "OrangePi One Plus"; compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi new file mode 100644 index 0000000000..0612c19cd9 --- /dev/null +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2018 Amarula Solutions + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include + +/ { + model = "OrangePi One Plus"; + compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc25-dram"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index 0000000000..7d01f93226 --- /dev/null +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + sw4 { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + /* + * On the production batch of this board the card detect GPIO is + * high active (card inserted), although on the early samples it's + * low active. + */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + /* + * There're two micro-USB connectors, one is power-only and another is + * OTG. The Vbus of these two connectors are connected together, so + * the external USB device will be powered just by the power input + * from the power-only USB port. + */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index 41d57c76f2..f0096074a4 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -84,21 +84,30 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; @@ -111,6 +120,28 @@ }; soc { + system-control@1c00000 { + compatible = "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x80000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-h3-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + mali: gpu@1c40000 { compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; reg = <0x01c40000 0x10000>; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi index c3bff1105e..fc6131315c 100644 --- a/arch/arm/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -506,8 +506,6 @@ reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; mdio: mdio { diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index ab886650cd..0ead552d7e 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the R-Car Gen3 ULCB board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include @@ -24,15 +21,6 @@ stdout-path = "serial0:115200n8"; }; - cpld { - compatible = "renesas,ulcb-cpld"; - status = "okay"; - gpio-sck = <&gpio6 8 0>; - gpio-mosi = <&gpio6 7 0>; - gpio-miso = <&gpio6 10 0>; - gpio-sstbz = <&gpio2 3 0>; - }; - audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> @@ -252,6 +240,32 @@ &i2c_dvfs { status = "okay"; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-pulse; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ohci1 { @@ -264,12 +278,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; @@ -285,6 +299,11 @@ function = "i2c2"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -308,13 +327,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; - power-source = <1800>; + power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -425,7 +444,7 @@ status = "okay"; }; -&wdt0 { +&rwdt { timeout-sec = <60>; status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index d63b56e944..31ba52b14e 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -116,6 +116,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -432,6 +454,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -446,6 +470,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -460,6 +486,8 @@ <&mio_clk 14>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>; + phy-names = "usb"; + phys = <&usb_phy2>; has-transaction-translator; }; @@ -488,6 +516,27 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-ld11-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-ld11-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + }; }; soc-glue@5f900000 { @@ -571,7 +620,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index 1a5e7c24b9..9ca692ed1b 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -145,6 +145,10 @@ }; }; +&usb { + status = "okay"; +}; + &nand { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 440c2e6a63..406244a5c8 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -75,3 +75,7 @@ drive-strength = <9>; }; }; + +&usb { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 9970497039..b9ed613ace 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -224,6 +224,50 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi2: spi@54006200 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006200 0x100>; + interrupts = <0 229 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi3: spi@54006300 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006300 0x100>; + interrupts = <0 230 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -567,6 +611,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -634,6 +722,157 @@ }; }; + _usb: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, + <&pinctrl_usb2>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb_rst 15>; + phys = <&usb_hsphy0>, <&usb_hsphy1>, + <&usb_hsphy2>, <&usb_hsphy3>, + <&usb_ssphy0>, <&usb_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus0: regulator@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus1: regulator@110 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus2: regulator@120 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x120 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus3: regulator@130 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x130 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb_hsphy2: hs-phy@220 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x220 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus2>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb_hsphy3: hs-phy@230 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x230 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus3>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb_vbus0>; + }; + + usb_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 19>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 19>; + vbus-supply = <&usb_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb: usb@65b00000 { compatible = "socionext,uniphier-ld20-dwc3"; reg = <0x65b00000 0x1000>; @@ -660,7 +899,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index f505f643f7..b73d594b6d 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -381,7 +392,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index aeb47b0ffe..1fee5ffbfb 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -131,6 +131,26 @@ function = "sd1"; }; + pinctrl_spi0: spi0 { + groups = "spi0"; + function = "spi0"; + }; + + pinctrl_spi1: spi1 { + groups = "spi1"; + function = "spi1"; + }; + + pinctrl_spi2: spi2 { + groups = "spi2"; + function = "spi2"; + }; + + pinctrl_spi3: spi3 { + groups = "spi3"; + function = "spi3"; + }; + pinctrl_system_bus: system-bus { groups = "system_bus", "system_bus_cs1"; function = "system_bus"; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index bff90c256b..ce8ea7b79b 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -73,11 +73,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -92,10 +92,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 7f5b957f98..686dd3af7e 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -68,11 +68,11 @@ status = "okay"; }; -&usb0 { +&usb2 { status = "okay"; }; -&usb1 { +&usb3 { status = "okay"; }; @@ -87,10 +87,10 @@ }; }; -&usb2 { +&usb0 { status = "okay"; }; -&usb3 { +&usb1 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 8974844541..ef342088e1 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -71,6 +71,17 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -317,6 +328,8 @@ <&mio_clk 12>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>; + phy-names = "usb"; + phys = <&usb_phy0>; has-transaction-translator; }; @@ -331,6 +344,8 @@ <&mio_clk 13>; resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>; + phy-names = "usb"; + phys = <&usb_phy1>; has-transaction-translator; }; @@ -342,6 +357,34 @@ pinctrl: pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; + + usb-phy { + compatible = "socionext,uniphier-pro4-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + vbus-supply = <&usb0_vbus>; + }; + + usb_phy3: phy@3 { + reg = <3>; + #phy-cells = <0>; + vbus-supply = <&usb1_vbus>; + }; + }; }; soc-glue@5f900000 { @@ -434,6 +477,60 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 4>; + phys = <&usb_phy2>, <&usb0_ssphy>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x100>; + + usb0_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_ssphy: ss-phy@10 { + compatible = "socionext,uniphier-pro4-usb3-ssphy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus>; + }; + + usb0_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -452,6 +549,49 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 4>; + phys = <&usb_phy3>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pro4-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x100>; + + usb1_vbus: regulator@0 { + compatible = "socionext,uniphier-pro4-usb3-regulator"; + reg = <0 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_rst: reset@40 { + compatible = "socionext,uniphier-pro4-usb3-reset"; + reg = <0x40 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; @@ -478,7 +618,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 6e0ea7976e..9cad79d086 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -156,6 +156,28 @@ cache-level = <3>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -475,7 +497,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 63c1c2ce60..fa25ffd97f 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -167,6 +167,28 @@ cache-level = <2>; }; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -557,6 +579,103 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -575,6 +694,91 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs2-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs2-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs2-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 15>; + reset-names = "link"; + resets = <&sys_rst 15>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs2-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 20>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs2-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 15>, <&sys_clk 21>; + reset-names = "link", "phy"; + resets = <&sys_rst 15>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; @@ -601,7 +805,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index daf74531e4..f629c6a862 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -144,6 +144,28 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + + spi1: spi@54006100 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006100 0x100>; + interrupts = <0 216 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -384,6 +406,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -465,6 +531,109 @@ }; }; + _usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + /* FIXME: U-Boot own node */ usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -483,6 +652,101 @@ }; }; + _usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, + <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 21>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + /* FIXME: U-Boot own node */ usb1: usb@65d00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; @@ -509,7 +773,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 437265bb73..f7fcf6b459 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -63,6 +63,17 @@ cache-level = <2>; }; + spi: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + status = "disabled"; + reg = <0x54006000 0x100>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -385,7 +396,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 5198eee024..ad30059b9a 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -89,6 +89,12 @@ status = "disabled"; }; + iomuxc: iomuxc@40048000 { + compatible = "fsl,vf610-iomuxc"; + reg = <0x40048000 0x1000>; + fsl,mux_mask = <0x700000>; + }; + gpio0: gpio@40049000 { compatible = "fsl,vf610-gpio"; reg = <0x400ff000 0x40>; diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h new file mode 100644 index 0000000000..fcad7132c8 --- /dev/null +++ b/arch/arm/dts/vf610-pinfunc.h @@ -0,0 +1,810 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_VF610_PINFUNC_H +#define __DTS_VF610_PINFUNC_H + +/* + * The pin function ID for VF610 is a tuple of: + * + */ + +#define ALT0 0x0 +#define ALT1 0x1 +#define ALT2 0x2 +#define ALT3 0x3 +#define ALT4 0x4 +#define ALT5 0x5 +#define ALT6 0x6 +#define ALT7 0x7 + + +#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 +#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 +#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 +#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 +#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 +#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 +#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 +#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 +#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 +#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 +#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 +#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 +#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 +#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 +#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 +#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 +#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 +#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 +#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 +#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 +#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 +#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 +#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 +#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 +#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 +#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 +#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 +#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 +#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 +#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 +#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 +#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 +#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 +#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 +#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 +#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 +#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 +#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 +#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 +#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 +#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 +#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 +#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 +#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 +#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 +#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 +#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 +#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 +#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 +#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 +#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 +#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 +#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 +#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 +#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 +#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 +#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 +#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 +#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 +#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 +#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 +#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 +#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 +#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 +#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 +#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 +#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 +#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 +#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 +#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 +#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 +#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 +#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 +#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 +#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 +#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 +#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 +#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 +#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 +#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 +#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 +#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 +#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 +#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 +#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 +#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 +#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 +#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 +#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 +#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 +#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 +#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 +#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 +#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 +#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 +#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 +#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 +#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 +#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 +#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 +#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 +#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 +#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 +#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 +#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 +#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 +#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 +#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 +#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 +#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 +#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 +#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 +#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 +#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 +#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 +#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 +#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 +#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 +#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 +#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 +#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 +#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 +#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 +#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 +#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 +#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 +#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 +#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 +#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 +#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 +#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 +#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 +#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 +#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 +#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 +#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 +#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 +#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 +#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 +#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 +#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 +#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 +#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 +#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 +#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 +#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 +#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 +#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 +#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 +#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 +#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 +#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 +#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 +#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 +#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 +#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 +#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 +#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 +#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 +#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 +#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 +#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 +#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 +#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 +#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 +#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 +#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 +#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 +#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 +#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 +#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 +#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 +#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 +#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 +#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 +#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 +#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 +#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 +#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 +#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 +#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 +#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 +#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 +#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 +#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 +#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 +#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 +#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 +#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 +#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 +#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 +#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 +#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 +#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 +#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 +#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 +#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 +#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 +#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 +#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 +#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 +#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 +#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 +#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 +#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 +#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 +#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 +#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 +#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 +#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 +#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 +#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 +#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 +#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 +#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 +#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 +#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 +#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 +#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 +#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 +#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 +#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 +#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 +#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 +#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 +#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 +#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 +#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 +#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 +#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 +#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 +#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 +#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 +#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 +#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 +#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 +#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 +#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 +#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 +#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 +#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 +#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 +#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 +#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 +#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 +#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 +#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 +#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 +#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 +#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 +#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 +#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 +#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 +#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 +#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 +#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 +#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 +#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 +#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 +#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 +#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 +#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 +#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 +#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 +#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 +#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 +#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 +#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 +#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 +#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 +#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 +#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 +#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 +#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 +#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 +#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 +#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 +#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 +#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 +#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 +#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 +#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 +#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 +#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 +#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 +#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 +#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 +#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 +#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 +#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 +#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 +#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 +#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 +#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 +#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 +#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 +#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 +#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 +#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 +#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 +#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 +#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 +#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 +#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 +#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 +#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 +#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 +#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 +#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 +#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 +#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 +#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 +#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 +#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 +#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 +#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 +#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 +#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 +#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 +#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 +#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 +#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 +#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 +#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 +#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 +#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 +#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 +#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 +#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 +#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 +#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 +#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 +#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 +#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 +#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 +#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 +#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 +#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 +#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 +#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 +#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 +#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 +#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 +#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 +#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 +#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 +#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 +#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 +#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 +#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 +#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 +#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 +#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 +#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 +#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 +#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 +#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 +#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 +#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 +#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 +#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 +#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 +#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 +#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 +#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 +#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 +#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 +#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 +#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 +#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 +#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 +#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 +#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 +#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 +#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 +#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 +#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 +#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 +#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 +#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 +#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 +#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 +#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 +#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 +#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 +#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 +#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 +#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 +#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 +#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 +#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 +#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 +#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 +#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 +#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 +#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 +#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 +#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 +#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 +#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 +#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 +#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 +#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 +#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 +#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 +#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 +#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 +#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 +#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 +#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 +#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 +#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 +#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 +#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 +#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 +#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 +#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 +#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 +#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 +#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 +#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 +#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 +#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 +#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 +#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 +#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 +#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 +#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 +#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 +#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 +#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 +#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 +#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 +#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 +#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 +#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 +#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 +#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 +#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 +#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 +#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 +#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 +#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 +#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 +#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 +#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 +#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 +#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 +#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 +#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 +#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 +#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 +#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 +#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 +#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 +#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 +#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 +#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 +#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 +#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 +#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 +#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 +#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 +#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 +#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 +#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 +#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 +#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 +#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 +#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 +#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 +#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 +#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 +#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 +#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 +#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 +#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 +#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 +#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 +#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 +#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 +#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 +#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 +#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 +#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 +#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 +#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 +#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 +#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 +#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 +#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 +#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 +#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 +#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 +#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 +#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 +#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 +#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 +#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 +#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 +#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 +#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 +#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 +#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 +#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 +#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 +#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 +#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 +#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 +#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 +#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 +#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 +#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 +#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 +#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 +#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 +#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 +#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 +#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 +#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 +#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 +#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 +#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 +#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 +#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 +#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 +#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 +#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 +#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 +#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 +#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 +#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 +#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 +#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 +#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 +#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 +#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 +#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 +#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 +#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 +#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 +#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 +#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 +#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 +#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 +#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 +#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 +#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 +#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 +#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 +#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 +#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 +#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 +#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 +#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 +#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 +#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 +#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 +#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 +#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 +#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 +#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 +#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 +#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 +#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 +#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 +#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 +#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 +#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 +#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 +#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 +#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 +#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 +#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 +#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 +#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 +#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 +#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 +#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 +#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 +#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 +#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 +#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 +#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 +#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 +#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 +#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 +#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 +#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 +#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 +#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 +#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 +#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 +#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 +#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 +#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 +#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 +#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 +#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 +#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 +#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 +#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 +#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 +#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 +#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 +#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 +#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 +#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 +#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 +#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 +#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 +#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 +#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 +#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 +#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 +#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 +#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 +#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 +#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 +#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 +#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 +#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 +#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 +#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 +#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 +#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 +#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 +#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 +#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 +#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 +#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 +#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 +#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 +#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 +#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 +#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 +#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 +#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 +#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 +#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 +#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 +#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 +#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 +#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 +#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 +#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 +#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 +#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 +#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 +#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 +#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 +#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 +#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 +#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 +#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 +#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 +#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 +#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 +#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 +#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 +#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 +#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 +#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 +#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 +#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 +#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 +#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 +#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 +#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 +#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 +#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 +#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 +#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 +#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 +#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 +#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 +#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 +#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 +#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 +#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 +#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 +#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 +#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 +#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 +#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 +#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 +#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 +#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 +#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 +#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 +#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 +#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 +#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 +#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 +#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 +#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 +#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 +#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 +#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 +#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 +#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 +#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 +#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 +#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 +#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 +#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 +#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 +#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 +#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 +#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 +#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 +#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 +#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 +#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 +#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 +#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 +#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 +#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 +#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 +#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 +#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 +#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 +#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 +#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 +#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 +#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 +#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 +#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 +#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 +#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 +#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 +#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 +#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 +#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 +#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 +#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 +#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 +#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 +#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 +#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 +#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 +#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 +#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 +#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 +#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 +#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 +#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 +#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 +#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 +#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 +#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 +#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 +#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 +#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 +#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 +#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 +#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 +#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 +#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 +#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 +#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 +#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 +#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 +#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 +#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 +#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 +#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 +#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 +#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 +#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 +#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 +#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 +#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 +#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 +#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 + +#endif diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 62c899d504..fabef11647 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -185,7 +185,7 @@ #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 491fca944d..c2a98500d9 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -6,57 +6,14 @@ #ifndef _I2C_AM33XX_H_ #define _I2C_AM33XX_H_ +#include + #define I2C_BASE1 0x44E0B000 #define I2C_BASE2 0x4802A000 #define I2C_BASE3 0x4819C000 #define I2C_DEFAULT_BASE I2C_BASE1 -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[5]; - unsigned short sysc; /* 0x10 */ - unsigned short res3[9]; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - #define I2C_IP_CLK 48000000 #define I2C_INTERNAL_SAMPLING_CLK 12000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index bd4ca88e16..d4f80a24cd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 48d0ab163a..eaa9ed251e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,50 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ #ifndef _FSL_LAYERSCAPE_CPU_H #define _FSL_LAYERSCAPE_CPU_H -static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), - CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), - CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), - CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), - CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), - CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), - CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), - CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), - CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), - CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), - CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), - CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), - CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), - CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), - CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), - CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), - CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), - CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), - CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), -}; - -#ifndef CONFIG_SYS_DCACHE_OFF - #ifdef CONFIG_FSL_LSCH3 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -64,8 +44,15 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 @@ -90,282 +77,6 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif -#define EARLY_PGTABLE_SIZE 0x5000 -static struct mm_region early_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, -#ifdef CONFIG_FSL_IFC - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | -#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | -#endif - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif - {}, /* list terminator */ -}; - -static struct mm_region final_map[] = { -#ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_ARCH_LS2080A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - SYS_FSL_OCRAM_SPACE_SIZE, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE - }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, -#ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE - }, -#endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }, -#endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - {}, /* space holder for secure mem */ -#endif - {}, -}; -#endif /* !CONFIG_SYS_DCACHE_OFF */ - int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 69810769f7..68354ff546 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2015 Freescale Semiconductor, Inc. */ @@ -19,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -31,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -47,16 +58,35 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, + NXP_SRDS_3 = 2, }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8c10526a6c..4d0f16f21c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -677,6 +677,26 @@ struct ccsr_gpio { #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 +#ifdef CONFIG_TFABOOT +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 + +/* RCW SRC NAND */ +#define RCW_SRC_NAND_MASK (0x100) +#define RCW_SRC_NAND_VAL (0x100) +#define NAND_RESERVED_MASK (0xFC) +#define NAND_RESERVED_1 (0x0) +#define NAND_RESERVED_2 (0x80) + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_MASK (0x1F0) +#define NOR_8B_VAL (0x10) +#define NOR_16B_VAL (0x20) +#define SD_VAL (0x40) +#define QSPI_VAL1 (0x44) +#define QSPI_VAL2 (0x45) +#endif + uint get_svr(void); #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index b0cec74db0..0535224646 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -15,13 +15,19 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +51,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) @@ -82,6 +94,55 @@ #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#ifdef CONFIG_TFABOOT +#ifdef CONFIG_NXP_LSCH3_2 +/* RCW_SRC field in Power-On Reset Control Register 1 */ +#define RCW_SRC_MASK 0x07800000 +#define RCW_SRC_BIT 23 + +/* CFG_RCW_SRC[3:0] */ +#define RCW_SRC_TYPE_MASK 0x8 +#define RCW_SRC_ADDR_OFFSET_8MB 0x800000 + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ + +#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ +#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ +#define RCW_SRC_I2C1_VAL 0xa /* 0xa */ +#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ +#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ +#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ +#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ +#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ +#else +#define RCW_SRC_MASK (0xFF800000) +#define RCW_SRC_BIT 23 +/* CFG_RCW_SRC[6:0] */ +#define RCW_SRC_TYPE_MASK (0x70) + +/* RCW SRC HARDCODED */ +#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ +/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ + +/* RCW SRC NOR */ +#define RCW_SRC_NOR_VAL (0x20) +#define NOR_TYPE_MASK (0x10) +#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ +#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ + +/* RCW SRC Serial Flash + * 1. SERIAL NOR (QSPI) + * 2. OTHERS (SD/MMC, SPI, I2C1 + */ +#define RCW_SRC_SERIAL_MASK (0x7F) +#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ +#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ +#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ +#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ +#endif +#endif + /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) @@ -267,6 +328,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 61b6e4bf07..f5bef6d569 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -53,6 +53,28 @@ struct cpu_type { #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#ifdef CONFIG_TFABOOT +#define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18 + +phys_size_t tfa_get_dram_size(void); + +enum boot_src { + BOOT_SOURCE_RESERVED = 0, + BOOT_SOURCE_IFC_NOR, + BOOT_SOURCE_IFC_NAND, + BOOT_SOURCE_QSPI_NOR, + BOOT_SOURCE_QSPI_NAND, + BOOT_SOURCE_XSPI_NOR, + BOOT_SOURCE_XSPI_NAND, + BOOT_SOURCE_SD_MMC, + BOOT_SOURCE_SD_MMC2, + BOOT_SOURCE_I2C1_EXTENDED, +}; + +enum boot_src get_boot_src(void); +#endif #endif #define SVR_WO_E 0xFFFFFE #define SVR_LS1012A 0x870400 @@ -74,12 +96,18 @@ struct cpu_type { #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 8d002da3ed..e017d8b558 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2015-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -69,11 +70,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -82,6 +83,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 2af79659d2..667badbc06 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -24,7 +24,7 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8MQ 0x82 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ @@ -32,7 +32,7 @@ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 -#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8M 0x80 #define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ @@ -41,6 +41,7 @@ #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h similarity index 97% rename from arch/arm/include/asm/arch-mx8m/clock.h rename to arch/arm/include/asm/arch-imx8m/clock.h index 45cfea3018..e7c1670f6b 100644 --- a/arch/arm/include/asm/arch-mx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -10,6 +10,8 @@ #include +#define MHZ(X) ((X) * 1000000UL) + enum pll_clocks { ANATOP_ARM_PLL, ANATOP_GPU_PLL, @@ -631,6 +633,26 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h similarity index 65% rename from arch/arm/include/asm/arch-mx8m/crm_regs.h rename to arch/arm/include/asm/arch-imx8m/crm_regs.h index c128931289..c42e6685de 100644 --- a/arch/arm/include/asm/arch-mx8m/crm_regs.h +++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h @@ -3,7 +3,7 @@ * Copyright 2017 NXP */ -#ifndef _ASM_ARCH_MX8M_CRM_REGS_H -#define _ASM_ARCH_MX8M_CRM_REGS_H +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H +#define _ASM_ARCH_IMX8M_CRM_REGS_H /* Dummy header, some imx-common code needs this file */ #endif diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h new file mode 100644 index 0000000000..53d46256d8 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -0,0 +1,740 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H + +#include +#include +#include + +#define DDRC_DDR_SS_GPR0 0x3d000000 +#define DDRC_IPS_BASE_ADDR_0 0x3f400000 +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) + +struct ddrc_freq { + u32 res0[8]; + u32 derateen; + u32 derateint; + u32 res1[10]; + u32 rfshctl0; + u32 res2[4]; + u32 rfshtmg; + u32 rfshtmg1; + u32 res3[28]; + u32 init3; + u32 init4; + u32 res; + u32 init6; + u32 init7; + u32 res4[4]; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res5[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 res6[3]; + u32 dfitmg0; + u32 dfitmg1; + u32 res7[7]; + u32 dfitmg2; + u32 dfitmg3; + u32 res8[33]; + u32 odtcfg; +}; + +struct imx8m_ddrc_regs { + u32 mstr; + u32 stat; + u32 mstr1; + u32 res1; + u32 mrctrl0; + u32 mrctrl1; + u32 mrstat; + u32 mrctrl2; + u32 derateen; + u32 derateint; + u32 mstr2; + u32 res2; + u32 pwrctl; + u32 pwrtmg; + u32 hwlpctl; + u32 hwffcctl; + u32 hwffcstat; + u32 res3[3]; + u32 rfshctl0; + u32 rfshctl1; + u32 rfshctl2; + u32 rfshctl4; + u32 rfshctl3; + u32 rfshtmg; + u32 rfshtmg1; + u32 res4; + u32 ecccfg0; + u32 ecccfg1; + u32 eccstat; + u32 eccclr; + u32 eccerrcnt; + u32 ecccaddr0; + u32 ecccaddr1; + u32 ecccsyn0; + u32 ecccsyn1; + u32 ecccsyn2; + u32 eccbitmask0; + u32 eccbitmask1; + u32 eccbitmask2; + u32 eccuaddr0; + u32 eccuaddr1; + u32 eccusyn0; + u32 eccusyn1; + u32 eccusyn2; + u32 eccpoisonaddr0; + u32 eccpoisonaddr1; + u32 crcparctl0; + u32 crcparctl1; + u32 crcparctl2; + u32 crcparstat; + u32 init0; + u32 init1; + u32 init2; + u32 init3; + u32 init4; + u32 init5; + u32 init6; + u32 init7; + u32 dimmctl; + u32 rankctl; + u32 res5; + u32 chctl; + u32 dramtmg0; + u32 dramtmg1; + u32 dramtmg2; + u32 dramtmg3; + u32 dramtmg4; + u32 dramtmg5; + u32 dramtmg6; + u32 dramtmg7; + u32 dramtmg8; + u32 dramtmg9; + u32 dramtmg10; + u32 dramtmg11; + u32 dramtmg12; + u32 dramtmg13; + u32 dramtmg14; + u32 dramtmg15; + u32 dramtmg16; + u32 dramtmg17; + u32 res6[10]; + u32 mramtmg0; + u32 mramtmg1; + u32 mramtmg4; + u32 mramtmg9; + u32 zqctl0; + u32 zqctl1; + u32 zqctl2; + u32 zqstat; + u32 dfitmg0; + u32 dfitmg1; + u32 dfilpcfg0; + u32 dfilpcfg1; + u32 dfiupd0; + u32 dfiupd1; + u32 dfiupd2; + u32 res7; + u32 dfimisc; + u32 dfitmg2; + u32 dfitmg3; + u32 dfistat; + u32 dbictl; + u32 dfiphymstr; + u32 res8[14]; + u32 addrmap0; + u32 addrmap1; + u32 addrmap2; + u32 addrmap3; + u32 addrmap4; + u32 addrmap5; + u32 addrmap6; + u32 addrmap7; + u32 addrmap8; + u32 addrmap9; + u32 addrmap10; + u32 addrmap11; + u32 res9[4]; + u32 odtcfg; + u32 odtmap; + u32 res10[2]; + u32 sched; + u32 sched1; + u32 sched2; + u32 perfhpr1; + u32 res11; + u32 perflpr1; + u32 res12; + u32 perfwr1; + u32 res13[4]; + u32 dqmap0; + u32 dqmap1; + u32 dqmap2; + u32 dqmap3; + u32 dqmap4; + u32 dqmap5; + u32 res14[26]; + u32 dbg0; + u32 dbg1; + u32 dbgcam; + u32 dbgcmd; + u32 dbgstat; + u32 res15[3]; + u32 swctl; + u32 swstat; + u32 res16[2]; + u32 ocparcfg0; + u32 ocparcfg1; + u32 ocparcfg2; + u32 ocparcfg3; + u32 ocparstat0; + u32 ocparstat1; + u32 ocparwlog0; + u32 ocparwlog1; + u32 ocparwlog2; + u32 ocparawlog0; + u32 ocparawlog1; + u32 ocparrlog0; + u32 ocparrlog1; + u32 ocpararlog0; + u32 ocpararlog1; + u32 poisoncfg; + u32 poisonstat; + u32 adveccindex; + union { + u32 adveccstat; + u32 eccapstat; + }; + u32 eccpoisonpat0; + u32 eccpoisonpat1; + u32 eccpoisonpat2; + u32 res17[6]; + u32 caparpoisonctl; + u32 caparpoisonstat; + u32 res18[2]; + u32 dynbsmstat; + u32 res19[18]; + u32 pstat; + u32 pccfg; + struct { + u32 pcfgr; + u32 pcfgw; + u32 pcfgc; + struct { + u32 pcfgidmaskch0; + u32 pcfidvaluech0; + } pcfgid[16]; + u32 pctrl; + u32 pcfgqos0; + u32 pcfgqos1; + u32 pcfgwqos0; + u32 pcfgwqos1; + u32 res[4]; + } pcfg[16]; + struct { + u32 sarbase; + u32 sarsize; + } sar[4]; + u32 sbrctl; + u32 sbrstat; + u32 sbrwdata0; + u32 sbrwdata1; + u32 pdch; + u32 res20[755]; + /* umctl2_regs_dch1 */ + u32 ch1_stat; + u32 res21[2]; + u32 ch1_mrctrl0; + u32 ch1_mrctrl1; + u32 ch1_mrstat; + u32 ch1_mrctrl2; + u32 res22[4]; + u32 ch1_pwrctl; + u32 ch1_pwrtmg; + u32 ch1_hwlpctl; + u32 res23[15]; + u32 ch1_eccstat; + u32 ch1_eccclr; + u32 ch1_eccerrcnt; + u32 ch1_ecccaddr0; + u32 ch1_ecccaddr1; + u32 ch1_ecccsyn0; + u32 ch1_ecccsyn1; + u32 ch1_ecccsyn2; + u32 ch1_eccbitmask0; + u32 ch1_eccbitmask1; + u32 ch1_eccbitmask2; + u32 ch1_eccuaddr0; + u32 ch1_eccuaddr1; + u32 ch1_eccusyn0; + u32 ch1_eccusyn1; + u32 ch1_eccusyn2; + u32 res24[2]; + u32 ch1_crcparctl0; + u32 res25[2]; + u32 ch1_crcparstat; + u32 res26[46]; + u32 ch1_zqctl2; + u32 ch1_zqstat; + u32 res27[11]; + u32 ch1_dfistat; + u32 res28[33]; + u32 ch1_odtmap; + u32 res29[47]; + u32 ch1_dbg1; + u32 ch1_dbgcam; + u32 ch1_dbgcmd; + u32 ch1_dbgstat; + u32 res30[123]; + /* umctl2_regs_freq1 */ + struct ddrc_freq freq1; + u32 res31[109]; + /* umctl2_regs_addrmap_alt */ + u32 addrmap0_alt; + u32 addrmap1_alt; + u32 addrmap2_alt; + u32 addrmap3_alt; + u32 addrmap4_alt; + u32 addrmap5_alt; + u32 addrmap6_alt; + u32 addrmap7_alt; + u32 addrmap8_alt; + u32 addrmap9_alt; + u32 addrmap10_alt; + u32 addrmap11_alt; + u32 res32[758]; + /* umctl2_regs_freq2 */ + struct ddrc_freq freq2; + u32 res33[879]; + /* umctl2_regs_freq3 */ + struct ddrc_freq freq3; +}; + +struct imx8m_ddrphy_regs { + u32 reg[0xf0000]; +}; + +/* PHY State */ +enum pstate { + PS0, + PS1, + PS2, + PS3, +}; + +enum msg_response { + TRAIN_SUCCESS = 0x7, + TRAIN_STREAM_START = 0x8, + TRAIN_FAIL = 0xff, +}; + +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +void ddr_init(struct dram_timing_info *timing_info); +void ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); + +/* utils function for ddr phy training */ +void wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + +#endif diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h similarity index 63% rename from arch/arm/include/asm/arch-mx8m/gpio.h rename to arch/arm/include/asm/arch-imx8m/gpio.h index 2ba5643d05..2d9fbcb0e4 100644 --- a/arch/arm/include/asm/arch-mx8m/gpio.h +++ b/arch/arm/include/asm/arch-imx8m/gpio.h @@ -3,8 +3,8 @@ * Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_GPIO_H -#define __ASM_ARCH_MX8M_GPIO_H +#ifndef __ASM_ARCH_IMX8M_GPIO_H +#define __ASM_ARCH_IMX8M_GPIO_H #include diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h similarity index 99% rename from arch/arm/include/asm/arch-mx8m/imx-regs.h rename to arch/arm/include/asm/arch-imx8m/imx-regs.h index a3b06282b0..3facd5450c 100644 --- a/arch/arm/include/asm/arch-mx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -3,8 +3,8 @@ * Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_REGS_H__ -#define __ASM_ARCH_MX8M_REGS_H__ +#ifndef __ASM_ARCH_IMX8M_REGS_H__ +#define __ASM_ARCH_IMX8M_REGS_H__ #include diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h similarity index 99% rename from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h rename to arch/arm/include/asm/arch-imx8m/imx8mq_pins.h index 3ba4d15a2a..c71913f209 100644 --- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -3,8 +3,8 @@ * Copyright (C) 2017 NXP */ -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ -#define __ASM_ARCH_MX8MQ_PINS_H__ +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ +#define __ASM_ARCH_IMX8MQ_PINS_H__ #include diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h new file mode 100644 index 0000000000..caf5bafb6d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \ + (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */ diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h similarity index 82% rename from arch/arm/include/asm/arch-mx8m/sys_proto.h rename to arch/arm/include/asm/arch-imx8m/sys_proto.h index 01d6cd76c1..d328542ece 100644 --- a/arch/arm/include/asm/arch-mx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -3,8 +3,8 @@ * Copyright (C) 2017 NXP */ -#ifndef __ARCH_MX8M_SYS_PROTO_H -#define __ARCH_MX8M_SYS_PROTO_H +#ifndef __ARCH_IMX8M_SYS_PROTO_H +#define __ARCH_NMX8M_SYS_PROTO_H #include diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h b/arch/arm/include/asm/arch-mediatek/gpio.h new file mode 100644 index 0000000000..4ea1020634 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_GPIO_H +#define __MEDIATEK_GPIO_H + +#endif /* __MEDIATEK_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 0000000000..2530e78a5f --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x08000000 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h new file mode 100644 index 0000000000..d293f2a839 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/axg.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __AXG_H__ +#define __AXG_H__ + +#define AXG_AOBUS_BASE 0xff800000 +#define AXG_PERIPHS_BASE 0xff634400 +#define AXG_HIU_BASE 0xff63c000 +#define AXG_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) + +#define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) +#define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) +#define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) +#define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) + +#define AXG_AO_BOOT_DEVICE 0xF +#define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_MEM_SIZE_SHIFT 16 +#define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) + +#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) +#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) + +#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) +#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define AXG_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) + +#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __AXG_H__ */ diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h new file mode 100644 index 0000000000..a90fe55081 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/boot.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_BOOT_H__ +#define __MESON_BOOT_H__ + +/* Boot device */ +#define BOOT_DEVICE_RESERVED 0 +#define BOOT_DEVICE_EMMC 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_SPI 3 +#define BOOT_DEVICE_SD 4 +#define BOOT_DEVICE_USB 5 + +int meson_get_boot_device(void); + +#endif /* __MESON_BOOT_H__ */ diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h new file mode 100644 index 0000000000..1ef88e4fad --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-axg.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ +#ifndef _ARCH_MESON_CLOCK_AXG_H_ +#define _ARCH_MESON_CLOCK_AXG_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + +#endif diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock-gx.h similarity index 98% rename from arch/arm/include/asm/arch-meson/clock.h rename to arch/arm/include/asm/arch-meson/clock-gx.h index c0ff00fc9a..13a2e7688f 100644 --- a/arch/arm/include/asm/arch-meson/clock.h +++ b/arch/arm/include/asm/arch-meson/clock-gx.h @@ -3,8 +3,8 @@ * Copyright 2016 - AmLogic, Inc. * Copyright 2018 - Beniamino Galvani */ -#ifndef _ARCH_MESON_CLOCK_H_ -#define _ARCH_MESON_CLOCK_H_ +#ifndef _ARCH_MESON_CLOCK_GX_H_ +#define _ARCH_MESON_CLOCK_GX_H_ /* * Clock controller register offsets diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h index 1aa0872d53..08acc5cbf7 100644 --- a/arch/arm/include/asm/arch-meson/eth.h +++ b/arch/arm/include/asm/arch-meson/eth.h @@ -10,13 +10,13 @@ #include enum { - /* Use GXL Internal RMII PHY */ - MESON_GXL_USE_INTERNAL_RMII_PHY = 1, + /* Use Internal RMII PHY */ + MESON_USE_INTERNAL_RMII_PHY = 1, }; /* Configure the Ethernet MAC with the requested interface mode * with some optional flags. */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags); +void meson_eth_init(phy_interface_t mode, unsigned int flags); #endif /* __MESON_ETH_H__ */ diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h index 4bc9475d35..b781ba9475 100644 --- a/arch/arm/include/asm/arch-meson/gx.h +++ b/arch/arm/include/asm/arch-meson/gx.h @@ -21,6 +21,7 @@ #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) +#define GX_AO_BOOT_DEVICE 0xF #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 #define GX_AO_MEM_SIZE_SHIFT 16 #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h index 62818335d9..a65100aeb7 100644 --- a/arch/arm/include/asm/arch-meson/mem.h +++ b/arch/arm/include/asm/arch-meson/mem.h @@ -10,6 +10,7 @@ /* Configure the reserved memory zones exported by the secure registers * into EFI and DTB reserved memory entries. */ -void meson_gx_init_reserved_memory(void *fdt); +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size); +void meson_init_reserved_memory(void *fdt); #endif /* __MESON_MEM_H__ */ diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h deleted file mode 100644 index 7e4f6fbb64..0000000000 --- a/arch/arm/include/asm/arch-mx8m/ddr.h +++ /dev/null @@ -1,355 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __ASM_ARCH_MX8M_DDR_H -#define __ASM_ARCH_MX8M_DDR_H - -#define DDRC_DDR_SS_GPR0 0x3d000000 -#define DDRC_IPS_BASE_ADDR_0 0x3f400000 -#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) -#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) - -struct ddrc_freq { - u32 res0[8]; - u32 derateen; - u32 derateint; - u32 res1[10]; - u32 rfshctl0; - u32 res2[4]; - u32 rfshtmg; - u32 rfshtmg1; - u32 res3[28]; - u32 init3; - u32 init4; - u32 res; - u32 init6; - u32 init7; - u32 res4[4]; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res5[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 res6[3]; - u32 dfitmg0; - u32 dfitmg1; - u32 res7[7]; - u32 dfitmg2; - u32 dfitmg3; - u32 res8[33]; - u32 odtcfg; -}; - -struct imx8m_ddrc_regs { - u32 mstr; - u32 stat; - u32 mstr1; - u32 res1; - u32 mrctrl0; - u32 mrctrl1; - u32 mrstat; - u32 mrctrl2; - u32 derateen; - u32 derateint; - u32 mstr2; - u32 res2; - u32 pwrctl; - u32 pwrtmg; - u32 hwlpctl; - u32 hwffcctl; - u32 hwffcstat; - u32 res3[3]; - u32 rfshctl0; - u32 rfshctl1; - u32 rfshctl2; - u32 rfshctl4; - u32 rfshctl3; - u32 rfshtmg; - u32 rfshtmg1; - u32 res4; - u32 ecccfg0; - u32 ecccfg1; - u32 eccstat; - u32 eccclr; - u32 eccerrcnt; - u32 ecccaddr0; - u32 ecccaddr1; - u32 ecccsyn0; - u32 ecccsyn1; - u32 ecccsyn2; - u32 eccbitmask0; - u32 eccbitmask1; - u32 eccbitmask2; - u32 eccuaddr0; - u32 eccuaddr1; - u32 eccusyn0; - u32 eccusyn1; - u32 eccusyn2; - u32 eccpoisonaddr0; - u32 eccpoisonaddr1; - u32 crcparctl0; - u32 crcparctl1; - u32 crcparctl2; - u32 crcparstat; - u32 init0; - u32 init1; - u32 init2; - u32 init3; - u32 init4; - u32 init5; - u32 init6; - u32 init7; - u32 dimmctl; - u32 rankctl; - u32 res5; - u32 chctl; - u32 dramtmg0; - u32 dramtmg1; - u32 dramtmg2; - u32 dramtmg3; - u32 dramtmg4; - u32 dramtmg5; - u32 dramtmg6; - u32 dramtmg7; - u32 dramtmg8; - u32 dramtmg9; - u32 dramtmg10; - u32 dramtmg11; - u32 dramtmg12; - u32 dramtmg13; - u32 dramtmg14; - u32 dramtmg15; - u32 dramtmg16; - u32 dramtmg17; - u32 res6[10]; - u32 mramtmg0; - u32 mramtmg1; - u32 mramtmg4; - u32 mramtmg9; - u32 zqctl0; - u32 zqctl1; - u32 zqctl2; - u32 zqstat; - u32 dfitmg0; - u32 dfitmg1; - u32 dfilpcfg0; - u32 dfilpcfg1; - u32 dfiupd0; - u32 dfiupd1; - u32 dfiupd2; - u32 res7; - u32 dfimisc; - u32 dfitmg2; - u32 dfitmg3; - u32 dfistat; - u32 dbictl; - u32 dfiphymstr; - u32 res8[14]; - u32 addrmap0; - u32 addrmap1; - u32 addrmap2; - u32 addrmap3; - u32 addrmap4; - u32 addrmap5; - u32 addrmap6; - u32 addrmap7; - u32 addrmap8; - u32 addrmap9; - u32 addrmap10; - u32 addrmap11; - u32 res9[4]; - u32 odtcfg; - u32 odtmap; - u32 res10[2]; - u32 sched; - u32 sched1; - u32 sched2; - u32 perfhpr1; - u32 res11; - u32 perflpr1; - u32 res12; - u32 perfwr1; - u32 res13[4]; - u32 dqmap0; - u32 dqmap1; - u32 dqmap2; - u32 dqmap3; - u32 dqmap4; - u32 dqmap5; - u32 res14[26]; - u32 dbg0; - u32 dbg1; - u32 dbgcam; - u32 dbgcmd; - u32 dbgstat; - u32 res15[3]; - u32 swctl; - u32 swstat; - u32 res16[2]; - u32 ocparcfg0; - u32 ocparcfg1; - u32 ocparcfg2; - u32 ocparcfg3; - u32 ocparstat0; - u32 ocparstat1; - u32 ocparwlog0; - u32 ocparwlog1; - u32 ocparwlog2; - u32 ocparawlog0; - u32 ocparawlog1; - u32 ocparrlog0; - u32 ocparrlog1; - u32 ocpararlog0; - u32 ocpararlog1; - u32 poisoncfg; - u32 poisonstat; - u32 adveccindex; - union { - u32 adveccstat; - u32 eccapstat; - }; - u32 eccpoisonpat0; - u32 eccpoisonpat1; - u32 eccpoisonpat2; - u32 res17[6]; - u32 caparpoisonctl; - u32 caparpoisonstat; - u32 res18[2]; - u32 dynbsmstat; - u32 res19[18]; - u32 pstat; - u32 pccfg; - struct { - u32 pcfgr; - u32 pcfgw; - u32 pcfgc; - struct { - u32 pcfgidmaskch0; - u32 pcfidvaluech0; - } pcfgid[16]; - u32 pctrl; - u32 pcfgqos0; - u32 pcfgqos1; - u32 pcfgwqos0; - u32 pcfgwqos1; - u32 res[4]; - } pcfg[16]; - struct { - u32 sarbase; - u32 sarsize; - } sar[4]; - u32 sbrctl; - u32 sbrstat; - u32 sbrwdata0; - u32 sbrwdata1; - u32 pdch; - u32 res20[755]; - /* umctl2_regs_dch1 */ - u32 ch1_stat; - u32 res21[2]; - u32 ch1_mrctrl0; - u32 ch1_mrctrl1; - u32 ch1_mrstat; - u32 ch1_mrctrl2; - u32 res22[4]; - u32 ch1_pwrctl; - u32 ch1_pwrtmg; - u32 ch1_hwlpctl; - u32 res23[15]; - u32 ch1_eccstat; - u32 ch1_eccclr; - u32 ch1_eccerrcnt; - u32 ch1_ecccaddr0; - u32 ch1_ecccaddr1; - u32 ch1_ecccsyn0; - u32 ch1_ecccsyn1; - u32 ch1_ecccsyn2; - u32 ch1_eccbitmask0; - u32 ch1_eccbitmask1; - u32 ch1_eccbitmask2; - u32 ch1_eccuaddr0; - u32 ch1_eccuaddr1; - u32 ch1_eccusyn0; - u32 ch1_eccusyn1; - u32 ch1_eccusyn2; - u32 res24[2]; - u32 ch1_crcparctl0; - u32 res25[2]; - u32 ch1_crcparstat; - u32 res26[46]; - u32 ch1_zqctl2; - u32 ch1_zqstat; - u32 res27[11]; - u32 ch1_dfistat; - u32 res28[33]; - u32 ch1_odtmap; - u32 res29[47]; - u32 ch1_dbg1; - u32 ch1_dbgcam; - u32 ch1_dbgcmd; - u32 ch1_dbgstat; - u32 res30[123]; - /* umctl2_regs_freq1 */ - struct ddrc_freq freq1; - u32 res31[109]; - /* umctl2_regs_addrmap_alt */ - u32 addrmap0_alt; - u32 addrmap1_alt; - u32 addrmap2_alt; - u32 addrmap3_alt; - u32 addrmap4_alt; - u32 addrmap5_alt; - u32 addrmap6_alt; - u32 addrmap7_alt; - u32 addrmap8_alt; - u32 addrmap9_alt; - u32 addrmap10_alt; - u32 addrmap11_alt; - u32 res32[758]; - /* umctl2_regs_freq2 */ - struct ddrc_freq freq2; - u32 res33[879]; - /* umctl2_regs_freq3 */ - struct ddrc_freq freq3; -}; - -struct imx8m_ddrphy_regs { - u32 reg[0xf0000]; -}; - -/* PHY State */ -enum pstate { - PS0, - PS1, - PS2, - PS3, -}; - -enum msg_response { - TRAIN_SUCCESS = 0x7, - TRAIN_STREAM_START = 0x8, - TRAIN_FAIL = 0xff, -}; - -#endif diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h index 5ddaa0d485..b04c012656 100644 --- a/arch/arm/include/asm/arch-omap3/i2c.h +++ b/arch/arm/include/asm/arch-omap3/i2c.h @@ -8,51 +8,4 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short we; /* 0x0C */ - unsigned short res4; - unsigned short syss; /* 0x10 */ - unsigned short res4a; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; - unsigned short bufstat; /* 0x40 */ - unsigned short res16; - unsigned short oa1; /* 0x44 */ - unsigned short res17; - unsigned short oa2; /* 0x48 */ - unsigned short res18; - unsigned short oa3; /* 0x4c */ - unsigned short res19; - unsigned short actoa; /* 0x50 */ - unsigned short res20; - unsigned short sblock; /* 0x54 */ - unsigned short res21; -}; - #endif /* _OMAP3_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h index c60aac778e..c8f2f9716f 100644 --- a/arch/arm/include/asm/arch-omap4/i2c.h +++ b/arch/arm/include/asm/arch-omap4/i2c.h @@ -8,49 +8,4 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[5]; - unsigned short sysc; /* 0x10 */ - unsigned short res3[9]; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - #endif /* _OMAP4_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h index 60e2b4bfa0..9e1edcf2b7 100644 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -8,49 +8,4 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -struct i2c { - unsigned short revnb_lo; /* 0x00 */ - unsigned short res1; - unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[5]; - unsigned short sysc; /* 0x10 */ - unsigned short res3[9]; - unsigned short irqstatus_raw; /* 0x24 */ - unsigned short res4; - unsigned short stat; /* 0x28 */ - unsigned short res5; - unsigned short ie; /* 0x2C */ - unsigned short res6; - unsigned short irqenable_clr; /* 0x30 */ - unsigned short res7; - unsigned short iv; /* 0x34 */ - unsigned short res8[45]; - unsigned short syss; /* 0x90 */ - unsigned short res9; - unsigned short buf; /* 0x94 */ - unsigned short res10; - unsigned short cnt; /* 0x98 */ - unsigned short res11; - unsigned short data; /* 0x9C */ - unsigned short res13; - unsigned short res14; /* 0xA0 */ - unsigned short res15; - unsigned short con; /* 0xA4 */ - unsigned short res16; - unsigned short oa; /* 0xA8 */ - unsigned short res17; - unsigned short sa; /* 0xAC */ - unsigned short res18; - unsigned short psc; /* 0xB0 */ - unsigned short res19; - unsigned short scll; /* 0xB4 */ - unsigned short res20; - unsigned short sclh; /* 0xB8 */ - unsigned short res21; - unsigned short systest; /* 0xBC */ - unsigned short res22; - unsigned short bufstat; /* 0xC0 */ - unsigned short res23; -}; - #endif /* _OMAP5_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 1d5b3a07d0..0eb19ca86f 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -43,6 +43,12 @@ struct sysreset_reg { unsigned int glb_srst_snd_value; }; +struct softreset_reg { + void __iomem *base; + unsigned int sf_reset_offset; + unsigned int sf_reset_num; +}; + /** * clk_get_divisor() - Calculate the required clock divisior * diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index b18de9f7c2..15eeb9c440 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -69,16 +69,21 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) +#define LPLL_HZ (600*MHz) +#define BPLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (676*MHz) #define PMU_PCLK_HZ (48*MHz) -#define ACLKM_CORE_HZ (300*MHz) -#define ATCLK_CORE_HZ (300*MHz) -#define PCLK_DBG_HZ (100*MHz) +#define ACLKM_CORE_L_HZ (300*MHz) +#define ATCLK_CORE_L_HZ (300*MHz) +#define PCLK_DBG_L_HZ (100*MHz) + +#define ACLKM_CORE_B_HZ (300*MHz) +#define ATCLK_CORE_B_HZ (300*MHz) +#define PCLK_DBG_B_HZ (100*MHz) #define PERIHP_ACLK_HZ (148500*KHz) #define PERIHP_HCLK_HZ (148500*KHz) @@ -98,4 +103,13 @@ enum apll_l_frequencies { APLL_L_600_MHZ, }; +enum apll_b_frequencies { + APLL_B_600_MHZ, +}; + +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq); +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq); + #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 3cc2ed0187..7697e96a91 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -11,7 +11,11 @@ #define OSC_HZ (24 * 1000 * 1000) #define APLL_HZ (600 * 1000000) -#define GPLL_HZ (594 * 1000000) +#define GPLL_HZ (1188 * 1000000) +#define ACLK_PERI_HZ (148500000) +#define HCLK_PERI_HZ (148500000) +#define PCLK_PERI_HZ (74250000) +#define ACLK_BUS_HZ (148500000) struct rv1108_clk_priv { struct rv1108_cru *cru; @@ -80,6 +84,11 @@ enum { WORK_MODE_NORMAL = 1, DSMPD_SHIFT = 3, DSMPD_MASK = 1 << DSMPD_SHIFT, + INTEGER_MODE = 1, + GLOBAL_POWER_DOWN_SHIFT = 0, + GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, + GLOBAL_POWER_DOWN = 1, + GLOBAL_POWER_UP = 0, /* CLKSEL0_CON */ CORE_PLL_SEL_SHIFT = 8, @@ -90,11 +99,77 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON1 */ + PCLK_DBG_DIV_CON_SHIFT = 4, + PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, + ACLK_CORE_DIV_CON_SHIFT = 0, + ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, + + /* CLKSEL_CON2 */ + ACLK_BUS_PLL_SEL_SHIFT = 8, + ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, + ACLK_BUS_PLL_SEL_GPLL = 0, + ACLK_BUS_PLL_SEL_APLL = 1, + ACLK_BUS_PLL_SEL_DPLL = 2, + ACLK_BUS_DIV_CON_SHIFT = 0, + ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, + ACLK_BUS_DIV_CON_WIDTH = 5, + + /* CLKSEL_CON3 */ + PCLK_BUS_DIV_CON_SHIFT = 8, + PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, + HCLK_BUS_DIV_CON_SHIFT = 0, + HCLK_BUS_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON4 */ + CLK_DDR_PLL_SEL_SHIFT = 8, + CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, + CLK_DDR_DIV_CON_SHIFT = 0, + CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, + + /* CLKSEL_CON19 */ + CLK_I2C1_PLL_SEL_SHIFT = 15, + CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, + CLK_I2C1_PLL_SEL_DPLL = 0, + CLK_I2C1_PLL_SEL_GPLL = 1, + CLK_I2C1_DIV_CON_SHIFT = 8, + CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, + CLK_I2C0_PLL_SEL_SHIFT = 7, + CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, + CLK_I2C0_DIV_CON_SHIFT = 0, + CLK_I2C0_DIV_CON_MASK = 0x7f, + I2C_DIV_CON_WIDTH = 7, + + /* CLKSEL_CON20 */ + CLK_I2C3_PLL_SEL_SHIFT = 15, + CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, + CLK_I2C3_PLL_SEL_DPLL = 0, + CLK_I2C3_PLL_SEL_GPLL = 1, + CLK_I2C3_DIV_CON_SHIFT = 8, + CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, + CLK_I2C2_DIV_CON_SHIFT = 0, + CLK_I2C2_DIV_CON_MASK = 0x7f, + /* CLKSEL_CON22 */ CLK_SARADC_DIV_CON_SHIFT= 0, CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL_CON23 */ + ACLK_PERI_PLL_SEL_SHIFT = 15, + ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, + ACLK_PERI_PLL_SEL_GPLL = 0, + ACLK_PERI_PLL_SEL_DPLL = 1, + PCLK_PERI_DIV_CON_SHIFT = 10, + PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, + HCLK_PERI_DIV_CON_SHIFT = 5, + HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, + ACLK_PERI_DIV_CON_SHIFT = 0, + ACLK_PERI_DIV_CON_MASK = 0x1f, + PERI_DIV_CON_WIDTH = 5, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, @@ -105,6 +180,17 @@ enum { MAC_CLK_DIV_MASK = 0x1f, MAC_CLK_DIV_SHIFT = 0, + /* CLKSEL25_CON */ + EMMC_PLL_SEL_SHIFT = 12, + EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, + EMMC_PLL_SEL_DPLL = 0, + EMMC_PLL_SEL_GPLL, + EMMC_PLL_SEL_OSC, + + /* CLKSEL26_CON */ + EMMC_CLK_DIV_SHIFT = 8, + EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, + /* CLKSEL27_CON */ SFC_PLL_SEL_SHIFT = 7, SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, @@ -112,5 +198,61 @@ enum { SFC_PLL_SEL_GPLL = 1, SFC_CLK_DIV_SHIFT = 0, SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, + + /* CLKSEL28_CON */ + ACLK_VIO1_PLL_SEL_SHIFT = 14, + ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, + VIO_PLL_SEL_DPLL = 0, + VIO_PLL_SEL_GPLL = 1, + ACLK_VIO1_CLK_DIV_SHIFT = 8, + ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, + CLK_VIO_DIV_CON_WIDTH = 5, + ACLK_VIO0_PLL_SEL_SHIFT = 6, + ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, + ACLK_VIO0_CLK_DIV_SHIFT = 0, + ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, + + /* CLKSEL29_CON */ + PCLK_VIO_CLK_DIV_SHIFT = 8, + PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, + HCLK_VIO_CLK_DIV_SHIFT = 0, + HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, + + /* CLKSEL32_CON */ + DCLK_VOP_SEL_SHIFT = 7, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_HDMI = 0, + DCLK_VOP_SEL_PLL = 1, + DCLK_VOP_PLL_SEL_SHIFT = 6, + DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_GPLL = 0, + DCLK_VOP_PLL_SEL_DPLL = 1, + DCLK_VOP_CLK_DIV_SHIFT = 0, + DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, + DCLK_VOP_DIV_CON_WIDTH = 6, + + /* SOFTRST1_CON*/ + DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, + DDRPHY_SRSTN_CLKDIV_REQ = 1, + DDRPHY_SRSTN_CLKDIV_DIS = 0, + DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, + DDRPHY_SRSTN_REQ_SHIFT = 1, + DDRPHY_SRSTN_REQ = 1, + DDRPHY_SRSTN_DIS = 0, + DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, + DDRPHY_PSRSTN_REQ_SHIFT = 2, + DDRPHY_PSRSTN_REQ = 1, + DDRPHY_PSRSTN_DIS = 0, + DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, + + /* SOFTRST2_CON*/ + DDRUPCTL_PSRSTN_REQ_SHIFT = 0, + DDRUPCTL_PSRSTN_REQ = 1, + DDRUPCTL_PSRSTN_DIS = 0, + DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, + DDRUPCTL_NSRSTN_REQ_SHIFT = 1, + DDRUPCTL_NSRSTN_REQ = 1, + DDRUPCTL_NSRSTN_DIS = 0, + DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h index 28a159c5b7..d05197670d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -205,4 +205,46 @@ enum { ATO_AE_SHIFT = 0, ATO_AE_MASK = 1, }; + +/* GRF_UOC_CON0 */ +enum { + SIDDQ_SHIFT = 13, + SIDDQ_MASK = 1 << SIDDQ_SHIFT, + + BYPASSSEL_SHIFT = 9, + BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, + + BYPASSDMEN_SHIFT = 8, + BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, + + UOC_DISABLE_SHIFT = 4, + UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, + + COMMON_ON_N_SHIFT = 0, + COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, +}; + +/* GRF_UOC_CON2 */ +enum { + SOFT_CON_SEL_SHIFT = 2, + SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, +}; + +/* GRF_UOC0_CON3 */ +enum { + TERMSEL_FULLSPEED_SHIFT = 5, + TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, + + XCVRSELECT_SHIFT = 3, + XCVRSELECT_FSTRANSC = 1, + XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, + + OPMODE_SHIFT = 1, + OPMODE_NODRIVING = 1, + OPMODE_MASK = 3 << OPMODE_SHIFT, + + SUSPENDN_SHIFT = 0, + SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, +}; + #endif diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h index 84859b1447..570e80a6ba 100644 --- a/arch/arm/include/asm/arch-stm32/gpio.h +++ b/arch/arm/include/asm/arch-stm32/gpio.h @@ -7,6 +7,8 @@ #ifndef _GPIO_H_ #define _GPIO_H_ +#define STM32_GPIOS_PER_BANK 16 + enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, STM32_GPIO_PORT_B, @@ -109,6 +111,9 @@ struct stm32_gpio_regs { struct stm32_gpio_priv { struct stm32_gpio_regs *regs; + unsigned int gpio_range; }; +int stm32_offset_to_index(struct udevice *dev, unsigned int offset); + #endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 6a5eafc3d3..2daf23f6f5 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -211,6 +211,7 @@ enum sunxi_gpio_number { #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2 #define SUN9I_GPN_R_RSB 3 diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index d98c53faaa..f2deafddd2 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -46,7 +46,9 @@ struct sunxi_mmc { u32 cbda; /* 0x94 */ u32 res2[26]; #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u32 res3[64]; + u32 res3[17]; + u32 samp_dl; + u32 res4[46]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; @@ -130,5 +132,7 @@ struct sunxi_mmc { #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) #define SUNXI_MMC_COMMON_RESET (1 << 18) +#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) + struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 62d00d15c2..4a573208df 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARMV8_MMU_H_ #define _ASM_ARMV8_MMU_H_ +#include + /* * block/section address mask and size definitions. */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 5df74728de..12bc7fbe06 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -160,7 +160,12 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define in_be32(a) in_arch(l,be32,a) #define in_be16(a) in_arch(w,be16,a) +#define out_32(a,v) __raw_writel(v,a) +#define out_16(a,v) __raw_writew(v,a) #define out_8(a,v) __raw_writeb(v,a) + +#define in_32(a) __raw_readl(a) +#define in_16(a) __raw_readw(a) #define in_8(a) __raw_readb(a) #define clrbits(type, addr, clear) \ @@ -180,6 +185,10 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define setbits_le32(addr, set) setbits(le32, addr, set) #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) +#define clrbits_32(addr, clear) clrbits(32, addr, clear) +#define setbits_32(addr, set) setbits(32, addr, set) +#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set) + #define clrbits_be16(addr, clear) clrbits(be16, addr, clear) #define setbits_be16(addr, set) setbits(be16, addr, set) #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) @@ -188,6 +197,10 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define setbits_le16(addr, set) setbits(le16, addr, set) #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) +#define clrbits_16(addr, clear) clrbits(16, addr, clear) +#define setbits_16(addr, set) setbits(16, addr, set) +#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set) + #define clrbits_8(addr, clear) clrbits(8, addr, clear) #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 63f4b33aeb..b899a4ff6f 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M #define PAD_CTL_DSE0 (0x0 << 0) #define PAD_CTL_DSE1 (0x1 << 0) #define PAD_CTL_DSE2 (0x2 << 0) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index d294c90646..b4c430a35c 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -73,7 +73,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index f8890b57da..8d6832a331 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -26,7 +26,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) -#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) @@ -42,6 +42,7 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #ifdef CONFIG_MX6 diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index d5a7a8bb61..bb33b4bc89 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -193,6 +193,10 @@ lr .req x30 SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ SCR_EL3_NS_EN) #endif + +#ifdef CONFIG_ARMV8_EA_EL3_FIRST + orr \tmp, \tmp, #SCR_EL3_EA_EN +#endif msr scr_el3, \tmp /* Return to the EL2_SP2 mode from EL3 */ diff --git a/arch/arm/include/asm/omap_i2c.h b/arch/arm/include/asm/omap_i2c.h new file mode 100644 index 0000000000..c1695cbbee --- /dev/null +++ b/arch/arm/include/asm/omap_i2c.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _OMAP_I2C_H +#define _OMAP_I2C_H + +#include + +#ifdef CONFIG_DM_I2C + +/* Information about a GPIO bank */ +struct omap_i2c_platdata { + ulong base; /* address of registers in physical memory */ + int speed; + int ip_rev; +}; + +#endif + +enum { + OMAP_I2C_REV_V1 = 0, + OMAP_I2C_REV_V2 = 1, +}; + +#endif /* _OMAP_I2C_H */ diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h index 875f1002af..b40ea005be 100644 --- a/arch/arm/include/asm/omap_musb.h +++ b/arch/arm/include/asm/omap_musb.h @@ -7,6 +7,7 @@ #ifndef __ASM_ARM_OMAP_MUSB_H #define __ASM_ARM_OMAP_MUSB_H +#include extern struct musb_platform_ops musb_dsps_ops; extern const struct musb_platform_ops am35x_ops; @@ -21,4 +22,11 @@ struct omap_musb_board_data { }; enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; + +struct ti_musb_platdata { + void *base; + void *ctrl_mod_base; + struct musb_hdrc_platform_data plat; +}; + #endif /* __ASM_ARM_OMAP_MUSB_H */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index c1f87f9caf..aed2e3c51e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -29,6 +29,7 @@ #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ +#define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */ #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ /* diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index f89e043f6e..bba1048499 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -57,19 +57,6 @@ /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK 0x4 - -#define MDIO_CONTROL_IDLE 0x80000000 -#define MDIO_CONTROL_ENABLE 0x40000000 -#define MDIO_CONTROL_FAULT_ENABLE 0x40000 -#define MDIO_CONTROL_FAULT 0x80000 -#define MDIO_USERACCESS0_GO 0x80000000 -#define MDIO_USERACCESS0_WRITE_READ 0x0 -#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 -#define MDIO_USERACCESS0_ACK 0x20000000 - #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) @@ -242,18 +229,4 @@ struct mdio_regs { u32 userphysel1; }; -struct eth_priv_t { - char int_name[32]; - int rx_flow; - int phy_addr; - int slave_port; - int sgmii_link_type; - phy_interface_t phy_if; - struct phy_device *phy_dev; -}; - -int keystone2_emac_initialize(struct eth_priv_t *eth_priv); -void sgmii_serdes_setup_156p25mhz(void); -void sgmii_serdes_shutdown(void); - #endif /* _KEYSTONE_NET_H_ */ diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S index 0db4360bcf..cb205fa30a 100644 --- a/arch/arm/lib/crt0_aarch64_efi.S +++ b/arch/arm/lib/crt0_aarch64_efi.S @@ -28,13 +28,13 @@ coff_header: .short 2 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ - .long 1 /* NumberOfSymbols */ + .long 0 /* NumberOfSymbols */ .short section_table - optional_header /* SizeOfOptionalHeader */ - /* - * Characteristics: IMAGE_FILE_DEBUG_STRIPPED | - * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED - */ - .short 0x206 + /* Characteristics */ + .short (IMAGE_FILE_EXECUTABLE_IMAGE | \ + IMAGE_FILE_LINE_NUMS_STRIPPED | \ + IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ + IMAGE_FILE_DEBUG_STRIPPED) optional_header: .short 0x20b /* PE32+ format */ .byte 0x02 /* MajorLinkerVersion */ diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S index 23db49f1fc..5470e2ff0e 100644 --- a/arch/arm/lib/crt0_arm_efi.S +++ b/arch/arm/lib/crt0_arm_efi.S @@ -27,16 +27,16 @@ coff_header: .short 2 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ - .long 1 /* NumberOfSymbols */ + .long 0 /* NumberOfSymbols */ .short section_table - optional_header /* SizeOfOptionalHeader */ - /* - * Characteristics: IMAGE_FILE_32BIT_MACHINE | - * IMAGE_FILE_DEBUG_STRIPPED | IMAGE_FILE_EXECUTABLE_IMAGE | - * IMAGE_FILE_LINE_NUMS_STRIPPED - */ - .short 0x306 + /* Characteristics */ + .short (IMAGE_FILE_EXECUTABLE_IMAGE | \ + IMAGE_FILE_LINE_NUMS_STRIPPED | \ + IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ + IMAGE_FILE_32BIT_MACHINE | \ + IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short 0x10b /* PE32+ format */ + .short 0x10b /* PE32 format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 0ca61210da..f7fb77235c 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -59,7 +59,7 @@ #endif ENTRY(memcpy) cmp r0, r1 - moveq pc, lr + bxeq lr enter r4, lr @@ -147,7 +147,8 @@ ENTRY(memcpy) str1b r0, r4, cs, abort=21f str1b r0, ip, cs, abort=21f - exit r4, pc + exit r4, lr + bx lr 9: rsb ip, ip, #4 cmp ip, #2 @@ -256,7 +257,8 @@ ENTRY(memcpy) .endm .macro copy_abort_end - ldmfd sp!, {r4, pc} + ldmfd sp!, {r4, lr} + bx lr .endm ENDPROC(memcpy) diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index eca78f8104..b714e93b3b 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -48,3 +48,13 @@ SECTIONS __bss_end = .; } >.sdram } + +#if defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__image_copy_end - __start < (CONFIG_SPL_MAX_SIZE), \ + "SPL image too big"); +#endif + +#if defined(CONFIG_SPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ + "SPL image BSS too big"); +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 99b0cc812d..cd2272367b 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -4,7 +4,7 @@ * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2018 Microchip Technology Inc. * * Watchdog Timer (WDT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. @@ -27,9 +27,13 @@ typedef struct at91_wdt { #endif +/* Watchdog Control Register */ +#define AT91_WDT_CR 0x00 #define AT91_WDT_CR_WDRSTT 1 #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ +/* Watchdog Mode Register*/ +#define AT91_WDT_MR 0X04 #define AT91_WDT_MR_WDV(x) (x & 0xfff) #define AT91_WDT_MR_WDFIEN 0x00001000 #define AT91_WDT_MR_WDRSTEN 0x00002000 diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 8bfb2a452b..6da6d41be2 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -11,7 +11,7 @@ #include #include -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) void at91_disable_wdt(void) { struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 8c368042a6..23ebaa99b1 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -76,7 +76,7 @@ void __weak spl_board_init(void) void board_init_f(ulong dummy) { lowlevel_clock_init(); -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) at91_disable_wdt(); #endif diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 597ff8c036..ef745c9477 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -98,7 +98,7 @@ void board_init_f(ulong dummy) configure_2nd_sram_as_l2_cache(); #endif -#if !defined(CONFIG_AT91SAM9_WATCHDOG) +#if !defined(CONFIG_WDT_AT91) /* disable watchdog */ at91_disable_wdt(); #endif diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c index 595e3ca149..7115d7bad2 100644 --- a/arch/arm/mach-davinci/dp83848.c +++ b/arch/arm/mach-davinci/dp83848.c @@ -12,7 +12,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c index 3d02274810..bfb7ff2689 100644 --- a/arch/arm/mach-davinci/et1011c.c +++ b/arch/arm/mach-davinci/et1011c.c @@ -9,7 +9,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c index 899cff0169..85b0c2620c 100644 --- a/arch/arm/mach-davinci/ksz8873.c +++ b/arch/arm/mach-davinci/ksz8873.c @@ -19,7 +19,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" int ksz8873_is_phy_connected(int phy_addr) { diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c index 170e4a5783..b54f67dbfe 100644 --- a/arch/arm/mach-davinci/lxt972.c +++ b/arch/arm/mach-davinci/lxt972.c @@ -13,7 +13,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 6a3cd44b5d..73aa4cdad3 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -345,7 +345,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) int i; struct clk_bit_info *info; - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) info = exynos542x_bit_info; else info = exynos5_bit_info; @@ -557,7 +557,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral) unsigned long clock_get_periph_rate(int peripheral) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos542x_get_periph_rate(peripheral); return exynos5_get_periph_rate(peripheral); } else { @@ -1317,6 +1317,19 @@ int exynos5_set_epll_clk(unsigned long rate) return 0; } +static int exynos5420_set_i2s_clk_source(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + + setbits_le32(&clk->src_top6, EXYNOS5420_CLK_SRC_MOUT_EPLL); + clrsetbits_le32(&clk->src_mau, EXYNOS5420_AUDIO0_SEL_MASK, + (EXYNOS5420_CLK_SRC_SCLK_EPLL)); + setbits_le32(EXYNOS5_AUDIOSS_BASE, 1 << 0); + + return 0; +} + int exynos5_set_i2s_clk_source(unsigned int i2s_id) { struct exynos5_clock *clk = @@ -1575,7 +1588,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else if (cpu_is_exynos4()) { @@ -1691,7 +1704,7 @@ void set_mmc_clk(int dev_index, unsigned int div) div -= 1; if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1739,7 +1752,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } @@ -1758,8 +1771,12 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, int set_i2s_clk_source(unsigned int i2s_id) { - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_source(i2s_id); + if (cpu_is_exynos5()) { + if (proid_is_exynos542x()) + return exynos5420_set_i2s_clk_source(); + else + return exynos5_set_i2s_clk_source(i2s_id); + } return 0; } diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index e63ef64523..1cb8d391e7 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -968,7 +968,7 @@ static void exynos5420_system_clock_init(void) void system_clock_init(void) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 2829fb269e..4e3702b928 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void) CACHE_TAG_RAM_LATENCY_2_CYCLES | CACHE_DATA_RAM_LATENCY_2_CYCLES; - if (proid_is_exynos5420() || proid_is_exynos5422()) { + if (proid_is_exynos542x()) { val |= CACHE_ECC_AND_PARITY | CACHE_TAG_RAM_LATENCY_3_CYCLES | CACHE_DATA_RAM_LATENCY_3_CYCLES; @@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void) { uint32_t val; - if (proid_is_exynos5420() || proid_is_exynos5422()) { + if (proid_is_exynos542x()) { mrc_l2_aux_ctlr(val); val |= CACHE_ENABLE_FORCE_L2_LOGIC | CACHE_DISABLE_CLEAN_EVICT; diff --git a/arch/arm/mach-exynos/include/mach/clock.h b/arch/arm/mach-exynos/include/mach/clock.h index edf62bdf85..e4c706adea 100644 --- a/arch/arm/mach-exynos/include/mach/clock.h +++ b/arch/arm/mach-exynos/include/mach/clock.h @@ -1370,10 +1370,13 @@ struct set_epll_con_val { #define AUDIO_1_RATIO_MASK 0x0f #define AUDIO0_SEL_MASK 0xf +#define EXYNOS5420_AUDIO0_SEL_MASK (0x3 << 28) #define AUDIO1_SEL_MASK 0xf #define CLK_SRC_SCLK_EPLL 0x7 +#define EXYNOS5420_CLK_SRC_SCLK_EPLL (0x6 << 28) #define CLK_SRC_MOUT_EPLL (1<<12) +#define EXYNOS5420_CLK_SRC_MOUT_EPLL BIT(20) #define AUDIO_CLKMUX_ASS (1<<0) /* CON0 bit-fields */ diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index aeb3755fe6..766edeeb29 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -268,6 +268,8 @@ IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) IS_EXYNOS_TYPE(exynos5422, 0x5422) +#define proid_is_exynos542x() (proid_is_exynos5420() || proid_is_exynos5422()) + #define SAMSUNG_BASE(device, base) \ static inline unsigned long __attribute__((no_instrument_function)) \ samsung_get_base_##device(void) \ @@ -277,7 +279,7 @@ static inline unsigned long __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420() || proid_is_exynos5422()) \ + if (proid_is_exynos542x()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index 272e00bae8..f9975d7919 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h @@ -1397,7 +1397,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1414,7 +1414,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 4837781957..48f13c7648 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -58,7 +58,7 @@ struct exynos5_sysreg { /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ - "msr cpsr_c, #0x13|0xC0\n\t" : : ) + "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0)) /* Set program counter with the given value */ #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index f6743ca0f6..b24f1bb8f4 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -378,6 +378,20 @@ static void exynos5_i2s_config(int peripheral) } } +static void exynos5420_i2s_config(int peripheral) +{ + int i; + + switch (peripheral) { + case PERIPH_ID_I2S0: + for (i = 0; i < 5; i++) + gpio_cfg_pin(EXYNOS5420_GPIO_Z0 + i, + S5P_GPIO_FUNC(0x02)); + break; + } +} + + void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; @@ -550,6 +564,9 @@ static int exynos5420_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C10: exynos5420_i2c_config(peripheral); break; + case PERIPH_ID_I2S0: + exynos5420_i2s_config(peripheral); + break; case PERIPH_ID_PWM0: gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); break; @@ -863,7 +880,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 63c410acef..f2a6c00dd6 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -124,7 +124,7 @@ static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) void set_usbdrd_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5422()) + if (proid_is_exynos542x()) exynos5420_set_usbdev_phy_ctrl(enable); else exynos5_set_usbdrd_phy_ctrl(enable); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 53d9e5f42b..d236e40510 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,12 +5,14 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) obj-y = iomux-v3.o endif -ifeq ($(SOC),$(filter $(SOC),mx8m)) +ifeq ($(SOC),$(filter $(SOC),imx8m)) +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o @@ -22,7 +24,7 @@ obj-y += cpu.o speed.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif @@ -104,7 +106,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image -DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) +DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) +else ifeq ($(CONFIG_ARCH_IMX8M), y) +IMAGE_TYPE := imx8mimage +IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh +DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi) else IMAGE_TYPE := imximage DEPFILE_EXISTS := 0 @@ -129,6 +135,26 @@ ifeq ($(DEPFILE_EXISTS),0) endif endif +ifdef CONFIG_ARM64 +ifeq ($(CONFIG_ARCH_IMX8M), y) +SPL: + +MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \ + -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) +flash.bin: MKIMAGEOUTPUT = flash.log + +spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE +ifeq ($(DEPFILE_EXISTS),0) + $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1 +endif + +flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE +ifeq ($(DEPFILE_EXISTS),0) + $(call if_changed,mkimage) +endif +endif + +else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) SPL: MKIMAGEOUTPUT = SPL.log @@ -160,6 +186,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \ spl/u-boot-nand-spl.imx: SPL FORCE $(call if_changed,u-boot-nand-spl_imx) +endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) @@ -169,5 +196,5 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ -obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index dcdaced991..80d9ff48a4 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -62,7 +62,7 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) case 0x00100: return "WDOG2"; case 0x00200: @@ -142,8 +142,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_MX8MQ: - return "8MQ"; /* Quad-core version of the mx8m */ + case MXC_CPU_IMX8MQ: + return "8MQ"; /* Quad-core version of the imx8m */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) } #endif -#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -300,7 +300,7 @@ void arch_preboot_os(void) #endif } -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M void set_chipselect_size(int const cs_size) { unsigned int reg; @@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) /* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING @@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) enum boot_device get_boot_device(void) { struct bootrom_sw_info **p = @@ -438,7 +438,7 @@ enum boot_device get_boot_device(void) case BOOT_TYPE_SPINOR: boot_dev = SPI_NOR_BOOT; break; -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M case BOOT_TYPE_USB: boot_dev = USB_BOOT; break; diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index b88acd13da..dbfd692fa3 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } +static ulong get_image_ivt_offset(ulong img_addr) +{ + const void *buf; + + buf = map_sysmem(img_addr, 0); + switch (genimg_get_format(buf)) { +#if defined(CONFIG_IMAGE_FORMAT_LEGACY) + case IMAGE_FORMAT_LEGACY: + return (image_get_image_size((image_header_t *)img_addr) + + 0x1000 - 1) & ~(0x1000 - 1); +#endif +#if IMAGE_ENABLE_FIT + case IMAGE_FORMAT_FIT: + return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1); +#endif + default: + return 0; + } +} + static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, length, ivt_offset; int rcode = 0; - if (argc < 4) + if (argc < 3) return CMD_RET_USAGE; addr = simple_strtoul(argv[1], NULL, 16); length = simple_strtoul(argv[2], NULL, 16); - ivt_offset = simple_strtoul(argv[3], NULL, 16); + if (argc == 3) + ivt_offset = get_image_ivt_offset(addr); + else + ivt_offset = simple_strtoul(argv[3], NULL, 16); rcode = imx_hab_authenticate_image(addr, length, ivt_offset); if (rcode == 0) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig new file mode 100644 index 0000000000..317dee9bc1 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -0,0 +1,23 @@ +if ARCH_IMX8M + +config IMX8M + bool + select ROM_UNIFIED_SECTIONS + +config SYS_SOC + default "imx8m" + +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_IMX8MQ_EVK + bool "imx8mq_evk" + select IMX8M + select IMX8M_LPDDR4 + +endchoice + +source "board/freescale/imx8mq_evk/Kconfig" + +endif diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile similarity index 100% rename from arch/arm/mach-imx/mx8m/Makefile rename to arch/arm/mach-imx/imx8m/Makefile diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c similarity index 85% rename from arch/arm/mach-imx/mx8m/clock.c rename to arch/arm/mach-imx/imx8m/clock.c index fe32e1c3f1..3766d988ba 100644 --- a/arch/arm/mach-imx/mx8m/clock.c +++ b/arch/arm/mach-imx/imx8m/clock.c @@ -525,41 +525,127 @@ u32 imx_get_fecclk(void) return get_root_clk(ENET_AXI_CLK_ROOT); } -#ifdef CONFIG_SPL_BUILD -void dram_pll_init(void) +static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, + CLK_ROOT_PRE_DIV2), +}; + +void dram_enable_bypass(ulong clk_val) +{ + int i; + struct dram_bypass_clk_setting *config; + + for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { + if (clk_val == imx8mq_dram_bypass_tbl[i].clk) + break; + } + + if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { + printf("No matched freq table %lu\n", clk_val); + return; + } + + config = &imx8mq_dram_bypass_tbl[i]; + + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | + CLK_ROOT_PRE_DIV(config->alt_pre_div)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | + CLK_ROOT_PRE_DIV(config->apb_pre_div)); + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); +} + +void dram_disable_bypass(void) +{ + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(ulong pll_val) { - struct src *src = (struct src *)SRC_BASE_ADDR; - void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; - u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; u32 val; - int ret; + void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; + void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; - setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7)); - setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5)); + /* Bypass */ + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); - pwdn_mask = SSCG_PLL_PD_MASK; - pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; - bypass1 = SSCG_PLL_BYPASS1_MASK; - bypass2 = SSCG_PLL_BYPASS2_MASK; - - /* Enable DDR1 and DDR2 domain */ - writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); - writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); + switch (pll_val) { + case MHZ(800): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(0); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(600): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(400): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(167): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(3); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); + val |= SSCG_PLL_REF_DIVR2_VAL(30); + writel(val, pll_cfg_reg2); + break; + default: + break; + } /* Clear power down bit */ - clrbits_le32(pll_control_reg, pwdn_mask); + clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK); /* Eanble ARM_PLL/SYS_PLL */ - setbits_le32(pll_control_reg, pll_clke); + setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK); /* Clear bypass */ - clrbits_le32(pll_control_reg, bypass1); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); __udelay(100); - clrbits_le32(pll_control_reg, bypass2); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); /* Wait lock */ - ret = readl_poll_timeout(pll_control_reg, val, - val & SSCG_PLL_LOCK_MASK, 1); - if (ret) - printf("%s timeout\n", __func__); + while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK)) + ; } int frac_pll_init(u32 pll, enum frac_pll_out_val val) @@ -730,7 +816,7 @@ int clock_init(void) * Dump some clockes. */ #ifndef CONFIG_SPL_BUILD -int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, +int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; @@ -785,7 +871,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, + clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, "display clocks", "" ); diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c similarity index 100% rename from arch/arm/mach-imx/mx8m/clock_slice.c rename to arch/arm/mach-imx/imx8m/clock_slice.c diff --git a/arch/arm/mach-imx/imx8m/imximage.cfg b/arch/arm/mach-imx/imx8m/imximage.cfg new file mode 100644 index 0000000000..714b24273b --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage.cfg @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +SIGNED_HDMI signed_hdmi_imx8m.bin +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S similarity index 100% rename from arch/arm/mach-imx/mx8m/lowlevel_init.S rename to arch/arm/mach-imx/imx8m/lowlevel_init.S diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c similarity index 92% rename from arch/arm/mach-imx/mx8m/soc.c rename to arch/arm/mach-imx/imx8m/soc.c index 46873aa8dd..11251c5f9a 100644 --- a/arch/arm/mach-imx/mx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -77,6 +77,22 @@ static struct mm_region imx8m_mem_map[] = { .size = 0x100000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE + }, { + /* CAAM */ + .virt = 0x100000UL, + .phys = 0x100000UL, + .size = 0x8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* TCM */ + .virt = 0x7C0000UL, + .phys = 0x7C0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* OCRAM */ .virt = 0x900000UL, diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index a1ea5c13f1..18d7e6819c 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -17,15 +17,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) if (!boot_private_data) return -EINVAL; - stack = *(ulong *)boot_private_data; - pc = *(ulong *)(boot_private_data + 4); + stack = *(u32 *)boot_private_data; + pc = *(u32 *)(boot_private_data + 4); /* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); /* Enable M4 */ -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); #else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) int arch_auxiliary_core_check_up(u32 core_id) { -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); #else unsigned int val; diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh new file mode 100755 index 0000000000..77f7143263 --- /dev/null +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -0,0 +1,137 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for i.MX8MQ boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 [ [&2 + exit 0 +else + echo "$BL31 size: " >&2 + ls -lct $BL31 | awk '{print $5}' >&2 +fi + +BL32="tee.bin" + +if [ ! -f $BL32 ]; then + BL32=/dev/null +else + echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2 + echo "$BL32 size: " >&2 + ls -lct $BL32 | awk '{print $5}' >&2 +fi + +BL33="u-boot-nodtb.bin" + +if [ ! -f $BL33 ]; then + echo "ERROR: $BL33 file NOT found" >&2 + exit 0 +else + echo "u-boot-nodtb.bin size: " >&2 + ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2 +fi + +for dtname in $* +do + echo "$dtname size: " >&2 + ls -lct $dtname | awk '{print $5}' >&2 +done + + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("$BL33"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x40200000>; + }; + atf@1 { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$ATF_LOAD_ADDR>; + entry = <$ATF_LOAD_ADDR>; + }; +__HEADER_EOF + +if [ -f $BL32 ]; then +cat << __HEADER_EOF + tee@1 { + description = "TEE firmware"; + data = /incbin/("$BL32"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$TEE_LOAD_ADDR>; + entry = <$TEE_LOAD_ADDR>; + }; +__HEADER_EOF +fi + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config@1"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $* +do +if [ -f $BL32 ]; then +cat << __CONF_SECTION_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot@1"; + loadables = "atf@1", "tee@1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION_EOF +else +cat << __CONF_SECTION1_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot@1"; + loadables = "atf@1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION1_EOF +fi +cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 06c25bae36..e7cce46e03 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -182,6 +182,7 @@ config TARGET_DISPLAY5 config TARGET_EMBESTMX6BOARDS bool "embestmx6boards" select BOARD_LATE_INIT + select SUPPORT_SPL config TARGET_GE_BX50V3 bool "General Electric Bx50v3" diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig deleted file mode 100644 index 3a84c2f2b0..0000000000 --- a/arch/arm/mach-imx/mx8m/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -if ARCH_MX8M - -config MX8M - bool - select ROM_UNIFIED_SECTIONS - -config SYS_SOC - default "mx8m" - -endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index a20b30d154..58a92278df 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -96,8 +96,8 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) +/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { #if defined(CONFIG_MX7) @@ -126,6 +126,7 @@ u32 spl_boot_device(void) enum boot_device boot_device_spl = get_boot_device(); switch (boot_device_spl) { +#if defined(CONFIG_MX7) case SD1_BOOT: case MMC1_BOOT: case SD2_BOOT: @@ -133,6 +134,14 @@ u32 spl_boot_device(void) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_IMX8M) + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; +#endif case NAND_BOOT: return BOOT_DEVICE_NAND; case SPI_NOR_BOOT: @@ -143,7 +152,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ +#endif /* CONFIG_MX7 || CONFIG_IMX8M */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) @@ -220,14 +229,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) debug("image entry point: 0x%lX\n", spl_image->entry_point); - /* HAB looks for the CSF at the end of the authenticated data therefore, - * we need to subtract the size of the CSF from the actual filesize */ - offset = spl_image->size - CONFIG_CSF_SIZE; - if (!imx_hab_authenticate_image(spl_image->load_addr, - offset + IVT_SIZE + CSF_PAD_SIZE, - offset)) { + if (spl_image->flags & SPL_FIT_FOUND) { image_entry(); } else { + /* + * HAB looks for the CSF at the end of the authenticated + * data therefore, we need to subtract the size of the + * CSF from the actual filesize + */ + offset = spl_image->size - CONFIG_CSF_SIZE; + if (!imx_hab_authenticate_image(spl_image->load_addr, + offset + IVT_SIZE + + CSF_PAD_SIZE, offset)) { + image_entry(); + } else { + puts("spl: ERROR: image authentication fail\n"); + hang(); + } + } +} + +ulong board_spl_fit_size_align(ulong size) +{ + /* + * HAB authenticate_image requests the IVT offset is + * aligned to 0x1000 + */ + + size = ALIGN(size, 0x1000); + size += CONFIG_CSF_SIZE; + + return size; +} + +void board_spl_fit_post_load(ulong load_addr, size_t length) +{ + u32 offset = length - CONFIG_CSF_SIZE; + + if (imx_hab_authenticate_image(load_addr, + offset + IVT_SIZE + CSF_PAD_SIZE, + offset)) { puts("spl: ERROR: image authentication unsuccessful\n"); hang(); } diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 2df6197af7..e677a2e01b 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -47,5 +47,23 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. +config SYS_K3_KEY + string "Key used to generate x509 certificate" + help + This option enables to provide a custom key that can be used for + generating x509 certificate for spl binary. If not needed leave + it blank so that a random key is generated and used. + +config SYS_K3_BOOT_CORE_ID + int + default 16 + +config SYS_K3_SPL_ATF + bool "Start Cortex-A from SPL" + depends on SPL && CPU_V7R + help + Enabling this will try to start Cortex-A (typically with ATF) + after SPL from R5. + source "board/ti/am65x/Kconfig" endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index e9b7ee5210..bd4ab361b2 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -5,3 +5,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o +obj-y += common.o diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 68f0b8c011..e2fe00c422 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -10,6 +10,8 @@ #include #include #include +#include "common.h" +#include #ifdef CONFIG_SPL_BUILD static void mmr_unlock(u32 base, u32 partition) @@ -56,6 +58,10 @@ static void store_boot_index_from_rom(void) void board_init_f(ulong dummy) { +#if defined(CONFIG_K3_AM654_DDRSS) + struct udevice *dev; + int ret; +#endif /* * Cannot delay this further as there is a chance that * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. @@ -65,11 +71,23 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); +#ifdef CONFIG_CPU_V7R + setup_k3_mpu_regions(); +#endif + /* Init DM early in-order to invoke system controller */ spl_early_init(); /* Prepare console output */ preloader_console_init(); + +#ifdef CONFIG_K3_AM654_DDRSS + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +#endif } u32 spl_boot_mode(const u32 boot_device) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c new file mode 100644 index 0000000000..cc89d4a296 --- /dev/null +++ b/arch/arm/mach-k3/common.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: Common Architecture initialization + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include "common.h" +#include +#include + +#ifdef CONFIG_SYS_K3_SPL_ATF +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + int ret; + + /* + * It is assumed that remoteproc device 1 is the corresponding + * cortex A core which runs ATF. Make sure DT reflects the same. + */ + ret = rproc_dev_init(1); + if (ret) { + printf("%s: ATF failed to Initialize on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + ret = rproc_load(1, spl_image->entry_point, 0x200); + if (ret) { + printf("%s: ATF failed to load on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + /* Add an extra newline to differentiate the ATF logs from SPL*/ + printf("Starting ATF on ARM64 core...\n\n"); + + ret = rproc_start(1); + if (ret) { + printf("%s: ATF failed to start on rproc: ret= %d\n", + __func__, ret); + hang(); + } + + debug("ATF started. Wait indefiniely\n"); + while (1) + asm volatile("wfe"); +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h new file mode 100644 index 0000000000..ac7e80d9af --- /dev/null +++ b/arch/arm/mach-k3/common.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Architecture common definitions + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include + +void setup_k3_mpu_regions(void); diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index 9b86ddc715..be00d79fb0 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -5,6 +5,65 @@ ifdef CONFIG_SPL_BUILD +# Openssl is required to generate x509 certificate. +# Error out if openssl is not available. +ifeq ($(shell which openssl),) +$(error "No openssl in $(PATH), consider installing openssl") +endif + +SHA_VALUE= $(shell openssl dgst -sha512 -hex $(obj)/u-boot-spl.bin | sed -e "s/^.*= //g") +IMAGE_SIZE= $(shell cat $(obj)/u-boot-spl.bin | wc -c) +LOADADDR= $(shell echo $(CONFIG_SPL_TEXT_BASE) | sed -e "s/^0x//g") +MAX_SIZE= $(shell printf "%d" $(CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE)) + +# Parameters to get populated into the x509 template +SED_OPTS= -e s/TEST_IMAGE_LENGTH/$(IMAGE_SIZE)/ +SED_OPTS+= -e s/TEST_IMAGE_SHA_VAL/$(SHA_VALUE)/ +SED_OPTS+= -e s/TEST_CERT_TYPE/1/ # CERT_TYPE_PRIMARY_IMAGE_BIN +SED_OPTS+= -e s/TEST_BOOT_CORE/$(CONFIG_SYS_K3_BOOT_CORE_ID)/ +SED_OPTS+= -e s/TEST_BOOT_ARCH_WIDTH/32/ +SED_OPTS+= -e s/TEST_BOOT_ADDR/$(LOADADDR)/ + +# Command to generate ecparam key +quiet_cmd_genkey = OPENSSL $@ +cmd_genkey = openssl ecparam -out $@ -name prime256v1 -genkey + +# Command to generate x509 certificate +quiet_cmd_gencert = OPENSSL $@ +cmd_gencert = cat $(srctree)/tools/k3_x509template.txt | sed $(SED_OPTS) > u-boot-spl-x509.txt; \ + openssl req -new -x509 -key $(KEY) -nodes -outform DER -out $@ -config u-boot-spl-x509.txt -sha512 + +# If external key is not provided, generate key using openssl. +ifeq ($(CONFIG_SYS_K3_KEY), "") +KEY=u-boot-spl-eckey.pem +else +KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY)) +endif + +u-boot-spl-eckey.pem: FORCE + $(call if_changed,genkey) + +# tiboot3.bin is mandated by ROM and ROM only supports R5 boot. +# So restrict tiboot3.bin creation for CPU_V7R. +ifdef CONFIG_CPU_V7R +u-boot-spl-cert.bin: $(KEY) $(obj)/u-boot-spl.bin image_check FORCE + $(call if_changed,gencert) + +image_check: $(obj)/u-boot-spl.bin FORCE + @if [ $(IMAGE_SIZE) -gt $(MAX_SIZE) ]; then \ + echo "===============================================" >&2; \ + echo "ERROR: Final Image too big. " >&2; \ + echo "$< size = $(IMAGE_SIZE), max size = $(MAX_SIZE)" >&2; \ + echo "===============================================" >&2; \ + exit 1; \ + fi + +tiboot3.bin: u-boot-spl-cert.bin $(obj)/u-boot-spl.bin FORCE + $(call if_changed,cat) + +ALL-y += tiboot3.bin +endif + ifdef CONFIG_ARM64 SPL_ITS := u-boot-spl-k3.its $(SPL_ITS): FORCE diff --git a/arch/arm/mach-k3/include/mach/sys_proto.h b/arch/arm/mach-k3/include/mach/sys_proto.h new file mode 100644 index 0000000000..0b2007981a --- /dev/null +++ b/arch/arm/mach-k3/include/mach/sys_proto.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Andreas Dannenberg + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +void sdelay(unsigned long loops); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound); + +#endif diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S new file mode 100644 index 0000000000..70c5d1cade --- /dev/null +++ b/arch/arm/mach-k3/lowlevel_init.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include + +ENTRY(lowlevel_init) + + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + and r0, #0xff + cmp r0, #0x0 + bne park_cpu + bx lr +park_cpu: + wfi + b park_cpu + +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c new file mode 100644 index 0000000000..ee076ed877 --- /dev/null +++ b/arch/arm/mach-k3/r5_mpu.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: R5 MPU region definitions + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include +#include "common.h" + +struct mpu_region_config k3_mpu_regions[16] = { + /* + * Make all 4GB as Device Memory and not executable. We are overriding + * it with next region for any requirement. + */ + {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED, + REGION_4GB}, + + /* SPL code area marking it as WB and Write allocate. */ + {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_8MB}, + + /* U-Boot's code area marking it as WB and Write allocate */ + {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_2GB}, + {0x0, 3, 0x0, 0x0, 0x0, 0x0}, + {0x0, 4, 0x0, 0x0, 0x0, 0x0}, + {0x0, 5, 0x0, 0x0, 0x0, 0x0}, + {0x0, 6, 0x0, 0x0, 0x0, 0x0}, + {0x0, 7, 0x0, 0x0, 0x0, 0x0}, + {0x0, 8, 0x0, 0x0, 0x0, 0x0}, + {0x0, 9, 0x0, 0x0, 0x0, 0x0}, + {0x0, 10, 0x0, 0x0, 0x0, 0x0}, + {0x0, 11, 0x0, 0x0, 0x0, 0x0}, + {0x0, 12, 0x0, 0x0, 0x0, 0x0}, + {0x0, 13, 0x0, 0x0, 0x0, 0x0}, + {0x0, 14, 0x0, 0x0, 0x0, 0x0}, + {0x0, 15, 0x0, 0x0, 0x0, 0x0}, +}; + +void setup_k3_mpu_regions(void) +{ + setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions)); +} diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c index 2613092552..6eee9ad13a 100644 --- a/arch/arm/mach-keystone/ddr3_spd.c +++ b/arch/arm/mach-keystone/ddr3_spd.c @@ -403,6 +403,7 @@ static void init_ddr3param(struct ddr3_spd_cb *spd_cb, static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) { int ret; +#ifndef CONFIG_DM_I2C int old_bus; i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); @@ -413,7 +414,13 @@ static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256); i2c_set_bus_num(old_bus); +#else + struct udevice *dev; + ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256); +#endif if (ret) { printf("Cannot read DIMM params\n"); return 1; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 0000000000..7a733e95df --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,39 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7623 + bool "MediaTek MT7623 SoC" + select CPU_V7A + select ARCH_MISC_INIT + help + The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-450 graphics, several DDR3 options, + crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder, + video interfaces supporting HDMI and MIPI, and video codec support. + Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe, + I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM. + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + select CPU_V7A + select SPL + select ARCH_MISC_INIT + help + The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 + including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, + switch, USB3.0, PCIe, UART, SPI, I2C and PWM. + +endchoice + +source "board/mediatek/mt7623/Kconfig" +source "board/mediatek/mt7629/Kconfig" + +endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile new file mode 100644 index 0000000000..b5d3a379bc --- /dev/null +++ b/arch/arm/mach-mediatek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += cpu.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-$(CONFIG_TARGET_MT7623) += mt7623/ +obj-$(CONFIG_TARGET_MT7629) += mt7629/ diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c new file mode 100644 index 0000000000..b37e299b74 --- /dev/null +++ b/arch/arm/mach-mediatek/cpu.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include +#include +#include +#include + +int arch_misc_init(void) +{ + struct udevice *wdt; + int ret; + + ret = uclass_first_device_err(UCLASS_WDT, &wdt); + if (!ret) + wdt_stop(wdt); + + return 0; +} + +int arch_cpu_init(void) +{ + icache_enable(); + + return 0; +} + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} diff --git a/arch/arm/mach-mediatek/init.h b/arch/arm/mach-mediatek/init.h new file mode 100644 index 0000000000..1d896fbbf7 --- /dev/null +++ b/arch/arm/mach-mediatek/init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_INIT_H_ +#define __MEDIATEK_INIT_H_ + +extern int mtk_soc_early_init(void); + +#endif /* __MEDIATEK_INIT_H_ */ diff --git a/arch/arm/mach-mediatek/mt7623/Makefile b/arch/arm/mach-mediatek/mt7623/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c new file mode 100644 index 0000000000..0ee8c6664c --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include +#include +#include +#include + +#include "preloader.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct boot_argument *preloader_param; + +int mtk_soc_early_init(void) +{ + return 0; +} + +int dram_init(void) +{ + u32 i; + + if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + ((size_t)preloader_param % sizeof(size_t) == 0) && + preloader_param->magic == BOOT_ARGUMENT_MAGIC && + preloader_param->dram_rank_num <= + ARRAY_SIZE(preloader_param->dram_rank_size)) { + gd->ram_size = 0; + + for (i = 0; i < preloader_param->dram_rank_num; i++) + gd->ram_size += preloader_param->dram_rank_size[i]; + } else { + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + SZ_2G); + } + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1); + + return 0; +} diff --git a/arch/arm/mach-mediatek/mt7623/lowlevel_init.S b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S new file mode 100644 index 0000000000..afb94767ee --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include + +.extern preloader_param + +ENTRY(save_boot_params) + ldr r6, =preloader_param + str r4, [r6] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(lowlevel_init) + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-mediatek/mt7623/preloader.h b/arch/arm/mach-mediatek/mt7623/preloader.h new file mode 100644 index 0000000000..2d2c71ad4c --- /dev/null +++ b/arch/arm/mach-mediatek/mt7623/preloader.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __PRELOADER_H_ +#define __PRELOADER_H_ + +enum forbidden_mode { + F_FACTORY_MODE = 0x0001 +}; + +union lk_hdr { + struct { + u32 magic; + u32 size; + char name[32]; + u32 loadaddr; + }; + + u8 data[512]; +}; + +struct sec_limit { + unsigned int magic_num; + enum forbidden_mode forbid_mode; +}; + +enum bootmode { + NORMAL_BOOT = 0, + META_BOOT = 1, + RECOVERY_BOOT = 2, + SW_REBOOT = 3, + FACTORY_BOOT = 4, + ADVMETA_BOOT = 5, + ATE_FACTORY_BOOT = 6, + ALARM_BOOT = 7, + + KERNEL_POWER_OFF_CHARGING_BOOT = 8, + LOW_POWER_OFF_CHARGING_BOOT = 9, + + FAST_BOOT = 99, + DOWNLOAD_BOOT = 100, + UNKNOWN_BOOT +}; + +enum boot_reason { + BR_POWER_KEY = 0, + BR_USB, + BR_RTC, + BR_WDT, + BR_WDT_BY_PASS_PWK, + BR_TOOL_BY_PASS_PWK, + BR_2SEC_REBOOT, + BR_UNKNOWN +}; + +enum meta_com_type { + META_UNKNOWN_COM = 0, + META_UART_COM, + META_USB_COM +}; + +struct da_info_t { + u32 addr; + u32 arg1; + u32 arg2; + u32 len; + u32 sig_len; +}; + +struct boot_argument { + u32 magic; + enum bootmode boot_mode; + u32 e_flag; + u32 log_port; + u32 log_baudrate; + u8 log_enable; + u8 part_num; + u8 reserved[2]; + u32 dram_rank_num; + u32 dram_rank_size[4]; + u32 boot_reason; + enum meta_com_type meta_com_type; + u32 meta_com_id; + u32 boot_time; + struct da_info_t da_info; + struct sec_limit sec_limit; + union lk_hdr *part_info; + u8 md_type[4]; + u32 ddr_reserve_enable; + u32 ddr_reserve_success; + u32 chip_ver; + char pl_version[8]; +}; + +#define BOOT_ARGUMENT_MAGIC 0x504c504c + +#endif /* __PRELOADER_H_ */ diff --git a/arch/arm/mach-mediatek/mt7629/Makefile b/arch/arm/mach-mediatek/mt7629/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c new file mode 100644 index 0000000000..ba91a6eaa6 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define L2_CFG_BASE 0x10200000 +#define L2_CFG_SIZE 0x1000 +#define L2_SHARE_CFG_MP0 0x7f0 +#define L2_SHARE_MODE_OFF BIT(8) + +DECLARE_GLOBAL_DATA_PTR; + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1250000000, + [CLK_APMIXED_MAINPLL] = 1120000000, + [CLK_APMIXED_UNIV2PLL] = 1200000000, + [CLK_APMIXED_ETH1PLL] = 500000000, + [CLK_APMIXED_ETH2PLL] = 700000000, + [CLK_APMIXED_SGMIPLL] = 650000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + /* setup mcu bus */ + ret = uclass_get_device_by_driver(UCLASS_SYSCON, + DM_GET_DRIVER(mtk_mcucfg), &dev); + if (ret) + return ret; + + return 0; +} + +int mtk_soc_early_init(void) +{ + struct udevice *dev; + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + return 0; +} + +int mach_cpu_init(void) +{ + void __iomem *base; + + base = ioremap(L2_CFG_BASE, L2_CFG_SIZE); + + /* disable L2C shared mode */ + writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0); + + return 0; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + ret = ram_get_info(dev, &ram); + if (ret) + return ret; + + debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 hwcode, swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + hwcode = readl(chipid + APHW_CODE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1); + + return 0; +} diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S new file mode 100644 index 0000000000..3375796b79 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include + +#define WAIT_CODE_SRAM_BASE 0x0010ff00 + +#define SLAVE_JUMP_REG 0x10202034 +#define SLAVE1_MAGIC_REG 0x10202038 +#define SLAVE1_MAGIC_NUM 0x534c4131 + +#define GIC_CPU_BASE 0x10320000 + +ENTRY(lowlevel_init) + +#ifndef CONFIG_SPL_BUILD + /* Return to U-Boot via saved link register */ + mov pc, lr +#else + /* + * Arch timer : + * set CNTFRQ = 20Mhz, set CNTVOFF = 0 + */ + movw r0, #0x2d00 + movt r0, #0x131 + mcr p15, 0, r0, c14, c0, 0 + + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + + /* if MP core, handle secondary cores */ + mrc p15, 0, r0, c0, c0, 5 + ands r1, r0, #0x40000000 + bne go @ Go if UP + /* read slave CPU number */ + ands r0, r0, #0x0f + beq go @ Go if core0 on primary core tile + b secondary + +go: + /* master CPU */ + mov pc, lr + +secondary: + /* enable GIC as cores will be waken up by IPI */ + ldr r2, =GIC_CPU_BASE + mov r1, #0xf0 + str r1, [r2, #4] + mov r1, #1 + str r1, [r2, #0] + + ldr r1, [r2] + orr r1, #1 + str r1, [r2] + + /* copy wait code into SRAM */ + ldr r0, =slave_cpu_wait + ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns + ldr r0, =WAIT_CODE_SRAM_BASE + stm r0, {r1 - r8} + + /* pass args to slave_cpu_wait */ + ldr r0, =SLAVE1_MAGIC_REG + ldr r1, =SLAVE1_MAGIC_NUM + + /* jump to wait code in SRAM */ + ldr pc, =WAIT_CODE_SRAM_BASE + +#endif +ENDPROC(lowlevel_init) + +/* This function will be copied into SRAM */ +ENTRY(slave_cpu_wait) + wfi + ldr r2, [r0] + cmp r2, r1 + bne slave_cpu_wait + movw r0, #:lower16:SLAVE_JUMP_REG + movt r0, #:upper16:SLAVE_JUMP_REG + ldr r1, [r0] + mov pc, r1 +ENDPROC(slave_cpu_wait) diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c new file mode 100644 index 0000000000..9b3590ff3d --- /dev/null +++ b/arch/arm/mach-mediatek/spl.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include + +#include "init.h" + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + hang(); + + /* enable console uart printing */ + preloader_console_init(); + + /* soc early initialization */ + ret = mtk_soc_early_init(); + if (ret) + hang(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + return BOOT_DEVICE_SPI; +#elif defined(CONFIG_SPL_MMC_SUPPORT) + return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_SPL_NAND_SUPPORT) + return BOOT_DEVICE_NAND; +#elif defined(CONFIG_SPL_NOR_SUPPORT) + return BOOT_DEVICE_NOR; +#else + return BOOT_DEVICE_NONE; +#endif +} diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index cc943443b3..11077bc6cc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -1,89 +1,49 @@ if ARCH_MESON -config MESON_GXBB - bool "Support Meson GXBaby" +config MESON64_COMMON + bool select ARM64 select CLK select DM select DM_SERIAL + select SYSCON + select REGMAP + select BOARD_LATE_INIT imply CMD_DM + +config MESON_GX + bool + select MESON64_COMMON + +choice + prompt "Platform select" + default MESON_GXBB + +config MESON_GXBB + bool "GXBB" + select MESON_GX help - The Amlogic Meson GXBaby (S905) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. + Select this if your SoC is an S905 config MESON_GXL - bool "Support Meson GXL" - select ARM64 - select CLK - select DM - select DM_SERIAL - imply CMD_DM + bool "GXL" + select MESON_GX help - The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a - quad-core Cortex-A53 CPU and a Mali-450 GPU. + Select this if your SoC is an S905X/D or S805X config MESON_GXM - bool "Support Meson GXM" - select ARM64 - select CLK - select DM - select DM_SERIAL + bool "GXM" + select MESON_GX help - The Amlogic Meson GXM (S912) is an ARM SoC with an - octo-core Cortex-A53 CPU and a Mali-T860 GPU. + Select this if your SoC is an S912 -if MESON_GXBB - -config TARGET_ODROID_C2 - bool "ODROID-C2" +config MESON_AXG + bool "AXG" + select MESON64_COMMON help - ODROID-C2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD - slot, eMMC, IR receiver and a 40-pin GPIO header. + Select this if your SoC is an A113X/D -config TARGET_NANOPI_K2 - bool "NANOPI_K2" - help - NANOPI_K2 is a single board computer based on Meson GXBaby - with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB, - micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header. -endif - -if MESON_GXL - -config TARGET_P212 - bool "P212" - help - P212 is a reference dessign board based on Meson GXL S905X SoC - with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot, - eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module. - -config TARGET_LIBRETECH_CC - bool "LIBRETECH-CC" - help - LibreTech CC is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. - -config TARGET_KHADAS_VIM - bool "KHADAS-VIM" - help - Khadas VIM is a single board computer based on Meson GXL - with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. - -endif - -if MESON_GXM - -config TARGET_KHADAS_VIM2 - bool "KHADAS-VIM2" - help - Khadas VIM2 is a single board computer based on Meson GXM - with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot, - eMMC, IR receiver and a 40-pin GPIO header. - -endif +endchoice config SYS_SOC default "meson" @@ -91,16 +51,32 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x1000 -source "board/amlogic/odroid-c2/Kconfig" +config SYS_VENDOR + string "Vendor name" + default "amlogic" + help + This option contains information about board name. + Based on this option board// will + be used. -source "board/amlogic/nanopi-k2/Kconfig" +config SYS_BOARD + string "Board name" + default "odroid-c2" if MESON_GXBB + default "p212" if MESON_GXL + default "q200" if MESON_GXM + default "s400" if MESON_AXG + default "" + help + This option contains information about board name. + Based on this option board// will + be used. -source "board/amlogic/p212/Kconfig" - -source "board/amlogic/libretech-cc/Kconfig" - -source "board/amlogic/khadas-vim/Kconfig" - -source "board/amlogic/khadas-vim2/Kconfig" +config SYS_CONFIG_NAME + string "Board configuration name" + default "meson64" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 8ad9b3e575..b716e1a152 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -2,4 +2,6 @@ # # Copyright (c) 2016 Beniamino Galvani -obj-y += board.o sm.o eth.o +obj-y += board-common.o sm.o +obj-$(CONFIG_MESON_GX) += board-gx.o +obj-$(CONFIG_MESON_AXG) += board-axg.o diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c new file mode 100644 index 0000000000..173905e762 --- /dev/null +++ b/arch/arm/mach-meson/board-axg.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani + * (C) Copyright 2018 Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int meson_get_boot_device(void) +{ + return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; +} + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(AXG_AO_SEC_GP_CFG3); + + bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK) + >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(AXG_AO_SEC_GP_CFG5); + bl32_start = readl(AXG_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK) + >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region axg_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = axg_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | + AXG_ETH_REG_0_TX_PHASE(1) | + AXG_ETH_REG_0_TX_RATIO(4) | + AXG_ETH_REG_0_PHY_CLK_EN | + AXG_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | + AXG_ETH_REG_0_INVERT_RMII_CLK | + AXG_ETH_REG_0_CLK_EN); + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c new file mode 100644 index 0000000000..8c41301674 --- /dev/null +++ b/arch/arm/mach-meson/board-common.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +__weak int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + const fdt64_t *val; + int offset; + int len; + + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + + /* Use unaligned access since cache is still disabled */ + gd->ram_size = get_unaligned_be64(&val[1]); + + return 0; +} + +__weak int meson_ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + meson_init_reserved_memory(blob); + + return meson_ft_board_setup(blob, bd); +} + +void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) +{ + int ret; + + ret = fdt_add_mem_rsv(fdt, start, size); + if (ret) + printf("Could not reserve zone @ 0x%llx\n", start); + + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + efi_add_memory_map(start, + ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); + } +} + +static void meson_set_boot_source(void) +{ + const char *source; + + switch (meson_get_boot_device()) { + case BOOT_DEVICE_EMMC: + source = "emmc"; + break; + + case BOOT_DEVICE_NAND: + source = "nand"; + break; + + case BOOT_DEVICE_SPI: + source = "spi"; + break; + + case BOOT_DEVICE_SD: + source = "sd"; + break; + + case BOOT_DEVICE_USB: + source = "usb"; + break; + + default: + source = "unknown"; + } + + env_set("boot_source", source); +} + +__weak int meson_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + meson_set_boot_source(); + + return meson_board_late_init(); +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board-gx.c similarity index 59% rename from arch/arm/mach-meson/board.c rename to arch/arm/mach-meson/board-gx.c index d6c6253152..e41552db52 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board-gx.c @@ -1,64 +1,30 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 Beniamino Galvani + * (C) Copyright 2018 Neil Armstrong */ #include -#include -#include +#include +#include #include -#include -#include -#include -#include -#include +#include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +int meson_get_boot_device(void) { - const fdt64_t *val; - int offset; - int len; - - offset = fdt_path_offset(gd->fdt_blob, "/memory"); - if (offset < 0) - return -EINVAL; - - val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); - if (len < sizeof(*val) * 2) - return -EINVAL; - - /* Use unaligned access since cache is still disabled */ - gd->ram_size = get_unaligned_be64(&val[1]); - - return 0; + return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; } -phys_size_t get_effective_memsize(void) -{ - /* Size is reported in MiB, convert it in bytes */ - return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) - >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; -} - -static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) -{ - int ret; - - ret = fdt_add_mem_rsv(fdt, start, size); - if (ret) - printf("Could not reserve zone @ 0x%llx\n", start); - - if (IS_ENABLED(CONFIG_EFI_LOADER)) { - efi_add_memory_map(start, - ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -} - -void meson_gx_init_reserved_memory(void *fdt) +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) { u64 bl31_size, bl31_start; u64 bl32_size, bl32_start; @@ -70,7 +36,6 @@ void meson_gx_init_reserved_memory(void *fdt) * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL */ - reg = readl(GX_AO_SEC_GP_CFG3); bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK) @@ -102,9 +67,11 @@ void meson_gx_init_reserved_memory(void *fdt) meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); } -void reset_cpu(ulong addr) +phys_size_t get_effective_memsize(void) { - psci_system_reset(); + /* Size is reported in MiB, convert it in bytes */ + return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK) + >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M; } static struct mm_region gx_mem_map[] = { @@ -128,3 +95,44 @@ static struct mm_region gx_mem_map[] = { }; struct mm_region *mem_map = gx_mem_map; + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | + GX_ETH_REG_0_TX_PHASE(1) | + GX_ETH_REG_0_TX_RATIO(4) | + GX_ETH_REG_0_PHY_CLK_EN | + GX_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | + GX_ETH_REG_0_CLK_EN); + + /* Use GXL RMII Internal PHY */ + if (IS_ENABLED(CONFIG_MESON_GXL) && + (flags & MESON_USE_INTERNAL_RMII_PHY)) { + writel(0x10110181, GX_ETH_REG_2); + writel(0xe40908ff, GX_ETH_REG_3); + } + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c deleted file mode 100644 index 8b28bc8531..0000000000 --- a/arch/arm/mach-meson/eth.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include - -/* Configure the Ethernet MAC with the requested interface mode - * with some optional flags. - */ -void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) -{ - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - /* Set RGMII mode */ - setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF | - GX_ETH_REG_0_TX_PHASE(1) | - GX_ETH_REG_0_TX_RATIO(4) | - GX_ETH_REG_0_PHY_CLK_EN | - GX_ETH_REG_0_CLK_EN); - break; - - case PHY_INTERFACE_MODE_RMII: - /* Set RMII mode */ - out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK | - GX_ETH_REG_0_CLK_EN); - - /* Use GXL RMII Internal PHY */ - if (IS_ENABLED(CONFIG_MESON_GXL) && - (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { - writel(0x10110181, GX_ETH_REG_2); - writel(0xe40908ff, GX_ETH_REG_3); - } - - break; - - default: - printf("Invalid Ethernet interface mode\n"); - return; - } - - /* Enable power gate */ - clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK); -} diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 0bba5e4a07..a07b46895d 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -6,7 +6,6 @@ */ #include -#include #include #define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020 diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index f47273fde9..47bbf69944 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -45,15 +46,62 @@ const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) /* DRAM init code ... */ +#define MV_SIP_DRAM_SIZE 0x82000010 + +static u64 a8k_dram_scan_ap_sz(void) +{ + struct pt_regs pregs; + + pregs.regs[0] = MV_SIP_DRAM_SIZE; + pregs.regs[1] = SOC_REGS_PHY_BASE; + smc_call(&pregs); + + return pregs.regs[0]; +} + +static void a8k_dram_init_banksize(void) +{ + /* + * The firmware (ATF) leaves a 1G whole above the 3G mark for IO + * devices. Higher RAM is mapped at 4G. + * + * Config 2 DRAM banks: + * Bank 0 - max size 4G - 1G + * Bank 1 - ram size - 4G + 1G + */ + phys_size_t max_bank0_size = SZ_4G - SZ_1G; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size <= max_bank0_size) { + gd->bd->bi_dram[0].size = gd->ram_size; + return; + } + + gd->bd->bi_dram[0].size = max_bank0_size; + if (CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = SZ_4G; + gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + } +} + int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + if (CONFIG_IS_ENABLED(ARMADA_8K)) + a8k_dram_init_banksize(); + else + fdtdec_setup_memory_banksize(); return 0; } int dram_init(void) { + if (CONFIG_IS_ENABLED(ARMADA_8K)) { + gd->ram_size = a8k_dram_scan_ap_sz(); + if (gd->ram_size != 0) + return 0; + } + if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0d2d39878d..919d05c88c 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -261,6 +261,9 @@ int print_cpuinfo(void) case MV_88F68XX_A0_ID: puts("A0"); break; + case MV_88F68XX_B0_ID: + puts("B0"); + break; default: printf("?? (%x)", revid); break; @@ -280,10 +283,8 @@ int print_cpuinfo(void) * and sets the correct windows sizes and base addresses accordingly. * * These values are set in the scratch registers by the Marvell - * DDR3 training code, which is executed by the BootROM before the - * main payload (U-Boot) is executed. This training code is currently - * only available in the Marvell U-Boot version. It needs to be - * ported to mainline U-Boot SPL at some point. + * DDR3 training code, which is executed by the SPL before the + * main payload (U-Boot) is executed. */ static void update_sdram_window_sizes(void) { diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 6e2e14efe0..01577f469b 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -27,6 +27,7 @@ /* A38x revisions */ #define MV_88F68XX_Z1_ID 0x0 #define MV_88F68XX_A0_ID 0x4 +#define MV_88F68XX_B0_ID 0xa /* TCLK Core Clock definition */ #ifndef CONFIG_SYS_TCLK diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 50b2358266..365332d2b0 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -233,6 +233,7 @@ /* A38x revisions */ #define MV_88F68XX_Z1_ID 0x0 #define MV_88F68XX_A0_ID 0x4 +#define MV_88F68XX_B0_ID 0xa /* A39x revisions */ #define MV_88F69XX_Z1_ID 0x2 diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 3529607479..57284c4ae1 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -206,6 +206,7 @@ config TARGET_PDU001 bool "Support PDU001" select DM select DM_SERIAL + imply SPL_SEPARATE_BSS imply CMD_DM help Support for PDU001 platform developed by EETS GmbH. diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index f5f2bd5308..62158a9592 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -93,6 +94,20 @@ U_BOOT_DEVICES(am33xx_uarts) = { # endif }; +#ifdef CONFIG_DM_I2C +static const struct omap_i2c_platdata am33xx_i2c[] = { + { I2C_BASE1, 100000, OMAP_I2C_REV_V2}, + { I2C_BASE2, 100000, OMAP_I2C_REV_V2}, + { I2C_BASE3, 100000, OMAP_I2C_REV_V2}, +}; + +U_BOOT_DEVICES(am33xx_i2c) = { + { "i2c_omap", &am33xx_i2c[0] }, + { "i2c_omap", &am33xx_i2c[1] }, + { "i2c_omap", &am33xx_i2c[2] }, +}; +#endif + #ifdef CONFIG_DM_GPIO static const struct omap_gpio_platdata am33xx_gpio[] = { { 0, AM33XX_GPIO0_BASE }, @@ -159,7 +174,55 @@ int cpu_mmc_init(bd_t *bis) /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ - (!defined(CONFIG_DM_USB)) + (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \ + (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT)) + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL) +static struct ti_musb_platdata usb0 = { + .base = (void *)USB0_OTG_BASE, + .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0, + .plat = { + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + }, +}; + +static struct ti_musb_platdata usb1 = { + .base = (void *)USB1_OTG_BASE, + .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1, + .plat = { + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + }, +}; + +U_BOOT_DEVICES(am33xx_usbs) = { +#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL + { "ti-musb-peripheral", &usb0 }, +#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST + { "ti-musb-host", &usb0 }, +#endif +#if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL + { "ti-musb-peripheral", &usb1 }, +#elif CONFIG_AM335X_USB1_MODE == MUSB_HOST + { "ti-musb-host", &usb1 }, +#endif +}; + +int arch_misc_init(void) +{ + return 0; +} +#else static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* USB 2.0 PHY Control */ @@ -178,13 +241,6 @@ static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) } } -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - #ifdef CONFIG_AM335X_USB0 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on) { @@ -235,6 +291,7 @@ int arch_misc_init(void) #endif return 0; } +#endif #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ @@ -457,12 +514,15 @@ void early_system_init(void) #ifdef CONFIG_DEBUG_UART_OMAP debug_uart_init(); #endif -#ifdef CONFIG_TI_I2C_BOARD_DETECT - do_board_detect(); -#endif + #ifdef CONFIG_SPL_BUILD spl_early_init(); #endif + +#ifdef CONFIG_TI_I2C_BOARD_DETECT + do_board_detect(); +#endif + #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c index 0e7ad1d3af..ff1bfaf84b 100644 --- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -14,6 +14,7 @@ /** * clk_synthesizer_reg_read - Read register from synthesizer. + * dev: i2c bus device (not used if CONFIG_DM_I2C is not set) * @addr: addr within the i2c device * buf: Buffer to which value is to be read. * @@ -21,13 +22,14 @@ * be send along with enabling byte read more, and then read can happen. * Returns 0 on success */ -static int clk_synthesizer_reg_read(int addr, uint8_t *buf) +static int clk_synthesizer_reg_read(struct udevice *dev, int addr, u8 *buf) { int rc; /* Enable Bye read */ addr = addr | CLK_SYNTHESIZER_BYTE_MODE; +#ifndef CONFIG_DM_I2C /* Send the command byte */ rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); if (rc) @@ -35,26 +37,46 @@ static int clk_synthesizer_reg_read(int addr, uint8_t *buf) /* Read the Data */ return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); +#else + /* Send the command byte */ + rc = dm_i2c_reg_write(dev, addr, *buf); + if (rc) + printf("Failed to send command to clock synthesizer\n"); + + /* Read the Data */ + rc = dm_i2c_reg_read(dev, addr); + if (rc < 0) + return rc; + + *buf = (u8)rc; + return 0; +#endif + } /** * clk_synthesizer_reg_write - Write a value to register in synthesizer. + * dev: i2c bus device (not used if CONFIG_DM_I2C is not set) * @addr: addr within the i2c device * val: Value to be written in the addr. * * Enable the byte read mode in the address and start the i2c transfer. * Returns 0 on success */ -static int clk_synthesizer_reg_write(int addr, uint8_t val) +static int clk_synthesizer_reg_write(struct udevice *dev, int addr, u8 val) { - uint8_t cmd[2]; + u8 cmd[2]; int rc = 0; /* Enable byte write */ cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE; cmd[1] = val; +#ifndef CONFIG_DM_I2C rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2); +#else + rc = dm_i2c_write(dev, addr, cmd, 2); +#endif if (rc) printf("Clock synthesizer reg write failed at addr = 0x%x\n", addr); @@ -72,30 +94,42 @@ static int clk_synthesizer_reg_write(int addr, uint8_t val) int setup_clock_synthesizer(struct clk_synth *data) { int rc; - uint8_t val; - + u8 val = 0; + struct udevice *dev = NULL; +#ifndef CONFIG_DM_I2C rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR); if (rc) { printf("i2c probe failed at address 0x%x\n", CLK_SYNTHESIZER_I2C_ADDR); return rc; } - - rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val); +#else + rc = i2c_get_chip_for_busnum(0, CLK_SYNTHESIZER_I2C_ADDR, 1, &dev); + if (rc) { + printf("failed to get device for synthesizer at address 0x%x\n", + CLK_SYNTHESIZER_I2C_ADDR); + return rc; + } +#endif + rc = clk_synthesizer_reg_read(dev, CLK_SYNTHESIZER_ID_REG, &val); if (val != data->id) return rc; /* Crystal Load capacitor selection */ - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor); + rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_XCSEL, + data->capacitor); if (rc) return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux); + rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_MUX_REG, + data->mux); if (rc) return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); + rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_PDIV2_REG, + data->pdiv2); if (rc) return rc; - rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); + rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_PDIV3_REG, + data->pdiv3); if (rc) return rc; diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 790548ee79..5932d694d3 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -909,6 +909,7 @@ void prcm_init(void) enable_basic_uboot_clocks(); } +#if !defined(CONFIG_DM_I2C) void gpi2c_init(void) { static int gpi2c = 1; @@ -919,3 +920,4 @@ void gpi2c_init(void) gpi2c = 0; } } +#endif diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 1a24acb748..772b4c4db5 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -12,6 +12,7 @@ */ #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -171,6 +173,10 @@ void __weak init_package_revision(void) */ void early_system_init(void) { +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) + int ret; + int rescan; +#endif init_omap_revision(); hw_data_init(); init_package_revision(); @@ -186,6 +192,7 @@ void early_system_init(void) do_io_settings(); #endif setup_early_clocks(); + #ifdef CONFIG_SPL_BUILD /* * Save the boot parameters passed from romcode. @@ -193,11 +200,23 @@ void early_system_init(void) * to prevent overwrites. */ save_omap_boot_params(); -#endif - do_board_detect(); -#ifdef CONFIG_SPL_BUILD spl_early_init(); #endif + do_board_detect(); + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) + /* + * Board detection has been done. + * Let us see if another dtb wouldn't be a better match + * for our board + */ + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } +#endif + vcores_init(); #ifdef CONFIG_DEBUG_UART_OMAP debug_uart_init(); diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index e0d02fb4e5..0286b0daa3 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -3,18 +3,23 @@ if OMAP34XX # We only enable the clocks for the GPIO banks that a given board requies. config OMAP3_GPIO_2 bool + default y if CMD_GPIO config OMAP3_GPIO_3 bool + default y if CMD_GPIO config OMAP3_GPIO_4 bool + default y if CMD_GPIO config OMAP3_GPIO_5 bool + default y if CMD_GPIO config OMAP3_GPIO_6 bool + default y if CMD_GPIO choice prompt "OMAP3 board select" diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index 9a03bfa9d3..cb9e91ebc3 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -750,23 +750,23 @@ void per_clocks_enable(void) setbits_le32(&prcm_base->iclken_per, 0x00000800); #endif -#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO)) +#if defined(CONFIG_OMAP3_GPIO_2) setbits_le32(&prcm_base->fclken_per, 0x00002000); setbits_le32(&prcm_base->iclken_per, 0x00002000); #endif -#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO)) +#if defined(CONFIG_OMAP3_GPIO_3) setbits_le32(&prcm_base->fclken_per, 0x00004000); setbits_le32(&prcm_base->iclken_per, 0x00004000); #endif -#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO)) +#if defined(CONFIG_OMAP3_GPIO_4) setbits_le32(&prcm_base->fclken_per, 0x00008000); setbits_le32(&prcm_base->iclken_per, 0x00008000); #endif -#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO)) +#if defined(CONFIG_OMAP3_GPIO_5) setbits_le32(&prcm_base->fclken_per, 0x00010000); setbits_le32(&prcm_base->iclken_per, 0x00010000); #endif -#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO)) +#if defined(CONFIG_OMAP3_GPIO_6) setbits_le32(&prcm_base->fclken_per, 0x00020000); setbits_le32(&prcm_base->iclken_per, 0x00020000); #endif diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index d82023acf3..c6e5f75daf 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -13,6 +13,11 @@ config RCAR_GEN3 select ARM64 select PHY select CMD_CACHE + imply CMD_FS_UUID + imply CMD_GPT + imply CMD_UUID + imply CMD_MMC_SWRITE if MMC + imply SUPPORT_EMMC_RPMB if MMC endchoice diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index c9ebc9f40e..aa5be52dfd 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -5,9 +5,8 @@ */ #include #include +#include -/* R-Car Gen3 caches are enabled in memmap-gen3.c */ -#ifndef CONFIG_RCAR_GEN3 #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { @@ -16,6 +15,8 @@ int arch_cpu_init(void) } #endif +/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */ +#ifndef CONFIG_RCAR_GEN3 #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { @@ -67,19 +68,41 @@ static const struct { { 0x0, "CPU" }, }; -int print_cpuinfo(void) +static int rmobile_cpuinfo_idx(void) { int i = 0; u32 cpu_type = rmobile_get_cpu_type(); - for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) { - if (rmobile_cpuinfo[i].cpu_type == cpu_type) { - printf("CPU: Renesas Electronics %s rev %d.%d\n", - rmobile_cpuinfo[i].cpu_name, - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); + + for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) + if (rmobile_cpuinfo[i].cpu_type == cpu_type) break; - } - } + + return i; +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + int i, idx = rmobile_cpuinfo_idx(); + char cpu[10] = { 0 }; + + for (i = 0; i < sizeof(cpu); i++) + cpu[i] = tolower(rmobile_cpuinfo[idx].cpu_name[i]); + + env_set("platform", cpu); + + return 0; +} +#endif + +int print_cpuinfo(void) +{ + int i = rmobile_cpuinfo_idx(); + + printf("CPU: Renesas Electronics %s rev %d.%d\n", + rmobile_cpuinfo[i].cpu_name, rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index 7e29ccc351..1a9eb72bb9 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -21,7 +21,13 @@ static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = { }, { .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0x80000000UL, + .size = 0x03F00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x47E00000UL, + .phys = 0x47E00000UL, + .size = 0x78200000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -76,8 +82,16 @@ void enable_caches(void) /* Mark memory reserved by ATF as cacheable too. */ if (start == 0x48000000) { - start = 0x40000000ULL; - size += 0x08000000ULL; + /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */ + gen3_mem_map[i].virt = 0x40000000ULL; + gen3_mem_map[i].phys = 0x40000000ULL; + gen3_mem_map[i].size = 0x03F00000ULL; + gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + i++; + + start = 0x47E00000ULL; + size += 0x00200000ULL; } gen3_mem_map[i].virt = start; @@ -126,6 +140,8 @@ void enable_caches(void) gen3_mem_map[i].attrs = 0; } - icache_enable(); + if (!icache_status()) + icache_enable(); + dcache_enable(); } diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 145d96b1f0..6dc8e3a017 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,7 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM + select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -156,6 +157,14 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. +config ROCKCHIP_USB_UART + bool "Route uart output to usb pins" + help + Rockchip SoCs have the ability to route the signals of the debug + uart through the d+ and d- pins of a specific usb phy to enable + some form of closed-case debugging. With this option supported + SoCs will enable this routing as a debug measure. + config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 05706c472a..368302e1da 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o +obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 4e5690eae3..2012d9fe04 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * (C) Copyright 2015 Google, Inc + * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ #include #include diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 98ca971b88..3c6c3d3c09 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -92,23 +93,38 @@ static int setup_arm_clock(void) return ret; } -void board_init_f(ulong dummy) +void board_debug_uart_init(void) { - struct udevice *pinctrl, *dev; - int ret; - - /* Example code showing how to enable the debug UART on RK3188 */ -#ifdef EARLY_UART -#include /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + }; + + /* Enable early UART on the RK3188 */ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl, *dev; + int ret; + +#define EARLY_UART +#ifdef EARLY_UART /* * Debug UART can be used from here if required: * @@ -124,6 +140,25 @@ void board_init_f(ulong dummy) printch('\n'); #endif +#ifdef CONFIG_ROCKCHIP_USB_UART + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[0], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); +#endif + ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 43350e38b1..0198c6c65f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -202,13 +202,13 @@ void board_init_f(ulong dummy) ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { - debug("Pinctrl init failed: %d\n", ret); + pr_err("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { - debug("DRAM init failed: %d\n", ret); + pr_err("DRAM init failed: %d\n", ret); return; } } diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 415466a49b..8f18e33c76 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,31 @@ config TARGET_PUMA_RK3399 * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI * SPI, I2C, I2S, UART, GPIO, ... +config TARGET_ROCK960_RK3399 + bool "Vamrs Limited Rock960 board family" + help + Support for Rock960 board family by Vamrs Limited. This board + family consists of Rock960 (Consumer Edition) and Ficus + (Enterprise Edition) 96Boards. + + Common features implemented on both boards: + * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4) + * 16/32GB eMMC, uSD slot + * HDMI/DP/MIPI + * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons + + Additional features of Rock960: + * 2GiB/4GiB LPDDR3 RAM + * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + + Additional features of Ficus: + * 2GiB/4GiB DDR3 RAM + * Ethernet + * Dual SATA + * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + endchoice config SYS_SOC @@ -38,5 +63,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" +source "board/vamrs/rock960_rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c new file mode 100644 index 0000000000..3412f2c063 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1108-board.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2015 Google, Inc + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include +#include + +static struct dwc2_plat_otg_data rv1108_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + const void *blob = gd->fdt_blob; + bool matched = false; + int node, phy_node; + u32 grf_phy_offset; + const char *mode; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb"); + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3066-usb"); + } + + if (!matched) { + debug("usb_otg device not found\n"); + return -ENODEV; + } + + rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + node = fdtdec_lookup_phandle(blob, node, "phys"); + if (node <= 0) { + debug("phys node not found\n"); + return -ENODEV; + } + + phy_node = fdt_parent_offset(blob, node); + if (phy_node <= 0) { + debug("usb phy node not found\n"); + return -ENODEV; + } + + rv1108_otg_data.phy_of_node = phy_node; + grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); + + /* find the grf node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rv1108-grf"); + if (node <= 0) { + debug("grf node not found\n"); + return -ENODEV; + } + + rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node, + "reg"); + + return dwc2_udc_probe(&rv1108_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index e6cba66578..8883aeae7a 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -17,6 +17,11 @@ config TARGET_EVB_RV1108 * 10/100 Mbps Ethernet * camera interface compatible with imx323 / ov2710 / ov4689 +config TARGET_ELGIN_RV1108 + bool "ELGIN_RV1108" + help + RV1108 ELGIN is a board based on the Rockchip RV1108. + config SYS_SOC default "rockchip" @@ -24,5 +29,6 @@ config SYS_MALLOC_F_LEN default 0x400 source board/rockchip/evb_rv1108/Kconfig +source board/elgin/elgin_rv1108/Kconfig endif diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 650d53e4d9..a27138083a 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -48,6 +48,24 @@ size_t rockchip_sdram_size(phys_addr_t reg) rank, col, bk, cs0_row, bw, row_3_4); } + /* + * This is workaround for issue we can't get correct size for 4GB ram + * in 32bit system and available before we really need ram space + * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram). + * The size of 4GB is '0x1 00000000', and this value will be truncated + * to 0 in 32bit system, and system can not get correct ram size. + * Rockchip SoCs reserve a blob of space for peripheral near 4GB, + * and we are now setting SDRAM_MAX_SIZE as max available space for + * ram in 4GB, so we can use this directly to workaround the issue. + * TODO: + * 1. update correct value for SDRAM_MAX_SIZE as what dram + * controller sees. + * 2. update board_get_usable_ram_top() and dram_init_banksize() + * to reserve memory for peripheral space after previous update. + */ + if (size_mb > (SDRAM_MAX_SIZE >> 20)) + size_mb = (SDRAM_MAX_SIZE >> 20); + return (size_t)size_mb << 20; } diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 06f8527aa4..5e87371f8c 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE + select FPGA_STRATIX10 choice prompt "Altera SOCFPGA board select" diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index bb9e3faa29..2725e9fcc3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -6,6 +6,7 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000 #define SOCFPGA_STM_ADDRESS 0xfc000000 #define SOCFPGA_DAP_ADDRESS 0xff000000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 81a609d2f8..ae728a5df5 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -107,6 +107,12 @@ enum ALT_SDM_MBOX_RESP_CODE { #define RECONFIG_STATUS_PIN_STATUS 2 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 +/* Macros for specifying number of arguments in mailbox command */ +#define MBOX_NUM_ARGS(n, b) (((n) & 0xFF) << (b)) +#define MBOX_DIRECT_COUNT(n) MBOX_NUM_ARGS((n), 0) +#define MBOX_ARG_DESC_COUNT(n) MBOX_NUM_ARGS((n), 8) +#define MBOX_RESP_DESC_COUNT(n) MBOX_NUM_ARGS((n), 16) + #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 @@ -140,5 +146,6 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); - +int mbox_get_fpga_config_status(u32 cmd); +int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570a04..86d5d2b62b 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -6,6 +6,8 @@ #ifndef _MISC_H_ #define _MISC_H_ +#include + void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode); struct bsel { @@ -16,13 +18,20 @@ struct bsel { extern struct bsel bsel_str[]; #ifdef CONFIG_FPGA -void socfpga_fpga_add(void); +void socfpga_fpga_add(void *fpga_desc); #else -static inline void socfpga_fpga_add(void) {} +inline void socfpga_fpga_add(void *fpga_desc) {} #endif #ifdef CONFIG_TARGET_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); +static inline bool socfpga_is_booting_from_fpga(void) +{ + if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) && + (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS)) + return true; + return false; +} #endif #ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 0d906c3480..3c33223936 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -342,6 +342,54 @@ int mbox_reset_cold(void) return 0; } +/* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */ +static __always_inline int mbox_get_fpga_config_status_common(u32 cmd) +{ + u32 reconfig_status_resp_len; + u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN]; + int ret; + + reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN; + ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd, + MBOX_CMD_DIRECT, 0, NULL, 0, + &reconfig_status_resp_len, + reconfig_status_resp); + + if (ret) + return ret; + + /* Check for any error */ + ret = reconfig_status_resp[RECONFIG_STATUS_STATE]; + if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) + return ret; + + /* Make sure nStatus is not 0 */ + ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS]; + if (!(ret & RCF_PIN_STATUS_NSTATUS)) + return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; + + ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS]; + if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR) + return MBOX_CFGSTAT_STATE_ERROR_HARDWARE; + + if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) && + (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) && + !reconfig_status_resp[RECONFIG_STATUS_STATE]) + return 0; /* configuration success */ + + return MBOX_CFGSTAT_STATE_CONFIG; +} + +int mbox_get_fpga_config_status(u32 cmd) +{ + return mbox_get_fpga_config_status_common(cmd); +} + +int __secure mbox_get_fpga_config_status_psci(u32 cmd) +{ + return mbox_get_fpga_config_status_common(cmd); +} + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf) { diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index a4f6d5c1ac..78fbe28724 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -88,33 +88,11 @@ int overwrite_console(void) #endif #ifdef CONFIG_FPGA -/* - * FPGA programming support for SoC FPGA Cyclone V - */ -static Altera_desc altera_fpga[] = { - { - /* Family */ - Altera_SoCFPGA, - /* Interface type */ - fast_passive_parallel, - /* No limitation as additional data will be ignored */ - -1, - /* No device function table */ - NULL, - /* Base interface address specified in driver */ - NULL, - /* No cookie implementation */ - 0 - }, -}; - /* add device descriptor to FPGA device table */ -void socfpga_fpga_add(void) +void socfpga_fpga_add(void *fpga_desc) { - int i; fpga_init(); - for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) - fpga_add(fpga_altera, &altera_fpga[i]); + fpga_add(fpga_altera, fpga_desc); } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index f347ae857e..63b8c75d31 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -30,6 +30,27 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * FPGA programming support for SoC FPGA Arria 10 + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + #if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -73,7 +94,7 @@ void socfpga_sdram_remap_zero(void) int arch_early_init_r(void) { /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + socfpga_fpga_add(&altera_fpga[0]); return 0; } diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..04f237d100 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -34,6 +34,26 @@ static struct nic301_registers *nic301_regs = static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; +/* + * FPGA programming support for SoC FPGA Cyclone V + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + /* * DesignWare Ethernet initialization */ @@ -177,6 +197,8 @@ static void socfpga_nic301_slave_ns(void) void socfpga_sdram_remap_zero(void) { + u32 remap; + socfpga_nic301_slave_ns(); /* @@ -187,7 +209,12 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + remap = 0x1; /* remap.mpuzero */ + /* Keep fpga bridge enabled when running from FPGA onchip RAM */ + if (socfpga_is_booting_from_fpga()) + remap |= 0x8; /* remap.hps2fpga */ + writel(remap, &nic301_regs->remap); + writel(0x1, &pl310->pl310_addr_filter_start); } @@ -214,7 +241,7 @@ int arch_early_init_r(void) socfpga_sdram_remap_zero(); /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + socfpga_fpga_add(&altera_fpga[0]); #ifdef CONFIG_DESIGNWARE_SPI /* Get Designware SPI controller out of reset */ diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index e599362f14..113eace650 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -24,6 +24,26 @@ DECLARE_GLOBAL_DATA_PTR; static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +/* + * FPGA programming support for SoC FPGA Stratix 10 + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Intel_FPGA_Stratix10, + /* Interface type */ + secure_device_manager_mailbox, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + /* * DesignWare Ethernet initialization */ @@ -125,6 +145,8 @@ int arch_misc_init(void) int arch_early_init_r(void) { + socfpga_fpga_add(&altera_fpga[0]); + return 0; } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..ccdc661d05 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -92,8 +92,11 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); - /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); + + if (!socfpga_is_booting_from_fpga()) { + /* Put FPGA bridges into reset too. */ + socfpga_bridges_reset(1); + } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -163,5 +166,6 @@ void board_init_f(ulong dummy) hang(); } - socfpga_bridges_reset(1); + if (!socfpga_is_booting_from_fpga()) + socfpga_bridges_reset(1); } diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 8cfacc7a13..2b072cc65e 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -251,7 +251,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS, }; -struct socfpga_sdram_io_config io_config = { +static const struct socfpga_sdram_io_config io_config = { .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP, .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP, .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP, @@ -269,7 +269,7 @@ struct socfpga_sdram_io_config io_config = { .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS, }; -struct socfpga_sdram_misc_config misc_config = { +static const struct socfpga_sdram_misc_config misc_config = { .afi_rate_ratio = AFI_RATE_RATIO, .calib_lfifo_offset = CALIB_LFIFO_OFFSET, .calib_vfifo_offset = CALIB_VFIFO_OFFSET, diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 0e152efc04..d087a31389 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -417,7 +417,6 @@ U_BOOT_DRIVER(stm32mp_bsec) = { .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), .ops = &stm32mp_bsec_ops, - .flags = DM_FLAG_PRE_RELOC, }; /* bsec IP is not present in device tee, manage IP address by platdata */ diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 0e01f8e613..b8933587ad 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -306,7 +306,7 @@ static int setup_mac_address(void) ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET, otp, sizeof(otp)); - if (ret) + if (ret < 0) return ret; for (i = 0; i < 6; i++) @@ -344,7 +344,7 @@ static int setup_serial_number(void) ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET, otp, sizeof(otp)); - if (ret) + if (ret < 0) return ret; sprintf(serial_string, "%08x%08x%08x", otp[0], otp[1], otp[2]); diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h index 5151150b8d..5ca76d21ff 100644 --- a/arch/arm/mach-stm32mp/include/mach/gpio.h +++ b/arch/arm/mach-stm32mp/include/mach/gpio.h @@ -8,6 +8,8 @@ #define _STM32_GPIO_H_ #include +#define STM32_GPIOS_PER_BANK 16 + enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, STM32_GPIO_PORT_B, @@ -110,5 +112,9 @@ struct stm32_gpio_regs { struct stm32_gpio_priv { struct stm32_gpio_regs *regs; + unsigned int gpio_range; }; + +int stm32_offset_to_index(struct udevice *dev, unsigned int offset); + #endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6277abc3cc..3c54f5106d 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -230,6 +230,7 @@ config MACH_SUN8I_A83T select PHY_SUN4I_USB select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE + select MMC_SUNXI_HAS_MODE_SWITCH select SUPPORT_SPL config MACH_SUN8I_H3 @@ -278,8 +279,10 @@ config MACH_SUN50I select ARM64 select DM_I2C select PHY_SUN4I_USB + select SUN6I_PRCM select SUNXI_DE2 select SUNXI_GEN_SUN6I + select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 82f6f7f8e3..1628f3a7b6 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_SUNXI_DE2 + const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */ +#else const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ +#endif if (clk == 0) { clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index d9aa0c6d7e..1da2727f98 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -334,7 +334,7 @@ unsigned long sunxi_dram_init(void) struct dram_para para = { .cs1 = 0, .bank = 1, - .rank = 1, + .rank = 2, .rows = 15, .bus_width = 16, .page_size = 2048, diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 5d91d7e2c1..dea42de833 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -101,6 +101,9 @@ int pmic_bus_setbits(u8 reg, u8 bits) if (ret) return ret; + if ((val & bits) == bits) + return 0; + val |= bits; return pmic_bus_write(reg, val); } @@ -114,6 +117,9 @@ int pmic_bus_clrbits(u8 reg, u8 bits) if (ret) return ret; + if (!(val & bits)) + return 0; + val &= ~bits; return pmic_bus_write(reg, val); } diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c index 5c9467bfe8..62142821a5 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c +++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c @@ -6,11 +6,10 @@ #include #include #include +#include #include #include -#define SZ_4G 0x100000000ULL - /* * Size of a region that's large enough to hold the relocated U-Boot and all * other allocations made around it (stack, heap, page tables, etc.) diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 1b871c62ce..972dbe8ae5 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -66,20 +66,20 @@ int board_late_init(void) switch (uniphier_boot_device_raw()) { case BOOT_DEVICE_MMC1: printf("eMMC Boot"); - env_set("bootcmd", "run bootcmd_mmc0; run distro_bootcmd"); + env_set("bootdev", "emmc"); break; case BOOT_DEVICE_NAND: printf("NAND Boot"); - env_set("bootcmd", "run bootcmd_ubifs0; run distro_bootcmd"); + env_set("bootdev", "nand"); nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot"); - env_set("bootcmd", "run tftpboot; run distro_bootcmd"); + env_set("bootdev", "nor"); break; case BOOT_DEVICE_USB: printf("USB Boot"); - env_set("bootcmd", "run bootcmd_usb0; run distro_bootcmd"); + env_set("bootdev", "usb"); break; default: printf("Unknown"); diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6d646ef999..194f4f349e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -74,9 +79,12 @@ config ARCH_MT7620 imply CMD_DM select DISPLAY_CPUINFO select DM + imply DM_ETH + imply DM_GPIO select DM_SERIAL imply DM_SPI imply DM_SPI_FLASH + select ARCH_MISC_INIT select MIPS_TUNE_24KC select OF_CONTROL select ROM_EXCEPTION_VECTORS @@ -85,6 +93,12 @@ config ARCH_MT7620 select SUPPORTS_LITTLE_ENDIAN select SYSRESET +config ARCH_JZ47XX + bool "Support Ingenic JZ47xx" + select SUPPORT_SPL + select OF_CONTROL + select DM + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -135,7 +149,9 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" +source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mt7620/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 802244a06e..029d290f1e 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -13,8 +13,10 @@ libs-y += arch/mips/lib/ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips +machine-$(CONFIG_ARCH_JZ47XX) += jz47xx machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 22223a0f3e..9d3a84539a 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -25,12 +25,14 @@ ifdef CONFIG_32BIT PLATFORM_CPPFLAGS += -mabi=32 PLATFORM_LDFLAGS += -m $(32bit-emul) OBJCOPYFLAGS += -O $(32bit-bfd) +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 endif ifdef CONFIG_64BIT PLATFORM_CPPFLAGS += -mabi=64 PLATFORM_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) +CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 endif PLATFORM_CPPFLAGS += -D__MIPS__ @@ -65,3 +67,5 @@ PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list + +LDFLAGS_STANDALONE += --gc-sections diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index 5c56ab0289..a403ff729b 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} - int arch_cpu_init(void) { mips_cache_probe(); diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk deleted file mode 100644 index a0247596f5..0000000000 --- a/arch/mips/cpu/mips32/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, - -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ - -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk deleted file mode 100644 index cd96bbcce9..0000000000 --- a/arch/mips/cpu/mips64/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, - -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \ - -T $(srctree)/examples/standalone/mips64.lds diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index b447141f87..647d2bf0d5 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi index 85fb14b13b..37354324fe 100644 --- a/arch/mips/dts/ar933x.dtsi +++ b/arch/mips/dts/ar933x.dtsi @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include "skeleton.dtsi" / { @@ -68,7 +67,6 @@ uart0: uart@18020000 { compatible = "qca,ar9330-uart"; reg = <0x18020000 0x20>; - interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -103,7 +101,6 @@ spi0: spi@1f000000 { compatible = "qca,ar7100-spi"; reg = <0x1f000000 0x10>; - interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi index f75988be12..d678dab242 100644 --- a/arch/mips/dts/brcm,bcm6318.dtsi +++ b/arch/mips/dts/brcm,bcm6318.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -54,6 +55,12 @@ reg = <0x10000004 0x4>; #clock-cells = <1>; }; + + ubus_clk: ubus-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000008 0x4>; + #clock-cells = <1>; + }; }; ubus { @@ -182,5 +189,36 @@ status = "disabled"; }; + + enet: ethernet@10080000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10080000 0x8000>; + clocks = <&periph_clk BCM6318_CLK_ROBOSW250>, + <&periph_clk BCM6318_CLK_ROBOSW025>, + <&ubus_clk BCM6318_UCLK_ROBOSW>; + resets = <&periph_rst BCM6318_RST_ENETSW>, + <&periph_rst BCM6318_RST_EPHY>; + dmas = <&iudma BCM6318_DMA_ENETSW_RX>, + <&iudma BCM6318_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; + + iudma: dma-controller@10088000 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10088000 0x80>, + <0x10088200 0x80>, + <0x10088400 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 62c440e675..f8a72ef535 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -217,5 +218,42 @@ reg = <0x10003000 0x894>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10700000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10700000 0x10000>; + clocks = <&periph_clk BCM63268_CLK_GMAC>, + <&periph_clk BCM63268_CLK_ROBOSW>, + <&periph_clk BCM63268_CLK_ROBOSW250>, + <&timer_clk BCM63268_TCLK_EPHY1>, + <&timer_clk BCM63268_TCLK_EPHY2>, + <&timer_clk BCM63268_TCLK_EPHY3>, + <&timer_clk BCM63268_TCLK_GPHY>; + resets = <&periph_rst BCM63268_RST_ENETSW>, + <&periph_rst BCM63268_RST_EPHY>, + <&periph_rst BCM63268_RST_GPHY>; + dmas = <&iudma BCM63268_DMA_ENETSW_RX>, + <&iudma BCM63268_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,rgmii-override; + brcm,rgmii-timing; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index e00a2950e2..50beed4171 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -187,5 +188,34 @@ reg = <0x10003000 0x864>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6328_CLK_ROBOSW>; + resets = <&periph_rst BCM6328_RST_ENETSW>, + <&periph_rst BCM6328_RST_EPHY>; + dmas = <&iudma BCM6328_DMA_ENETSW_RX>, + <&iudma BCM6328_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <5>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index bbd58cf803..c547e949dd 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -130,5 +131,33 @@ reg = <0xfffe3100 0x38>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@fffe2400 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe2400 0x1c>, + <0xfffe2500 0x60>, + <0xfffe2600 0x60>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <6>; + resets = <&periph_rst BCM6338_RST_DMAMEM>; + }; + + enet: ethernet@fffe2800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe2800 0x2dc>; + clocks = <&periph_clk BCM6338_CLK_ENET>; + resets = <&periph_rst BCM6338_RST_ENET>; + dmas = <&iudma BCM6338_DMA_ENET_RX>, + <&iudma BCM6338_DMA_ENET_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index cc80bbc808..79e7bd892b 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -159,5 +160,46 @@ reg = <0xfffe2300 0x38>; u-boot,dm-pre-reloc; }; + + enet0: ethernet@fffe6000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6000 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET0_RX>, + <&iudma BCM6348_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe6800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6800 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET1_RX>, + <&iudma BCM6348_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe7000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe7000 0x1c>, + <0xfffe7100 0x40>, + <0xfffe7200 0x40>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&periph_clk BCM6348_CLK_ENET>; + resets = <&periph_rst BCM6348_RST_ENET>, + <&periph_rst BCM6348_RST_DMAMEM>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 0617b46e92..5e9c9ad769 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -190,5 +191,50 @@ status = "disabled"; }; + + enet0: ethernet@fffe4000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4000 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET0>; + dmas = <&iudma BCM6358_DMA_ENET0_RX>, + <&iudma BCM6358_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe4800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4800 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET1>; + dmas = <&iudma BCM6358_DMA_ENET1_RX>, + <&iudma BCM6358_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + iudma: dma-controller@fffe5000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe5000 0x24>, + <0xfffe5100 0x80>, + <0xfffe5200 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + clocks = <&periph_clk BCM6358_CLK_EMUSB>, + <&periph_clk BCM6358_CLK_USBSU>, + <&periph_clk BCM6358_CLK_EPHY>; + resets = <&periph_rst BCM6358_RST_ENET>, + <&periph_rst BCM6358_RST_EPHY>; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi index 3047b82b21..c77b80a4cc 100644 --- a/arch/mips/dts/brcm,bcm6362.dtsi +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -211,5 +212,36 @@ reg = <0x10003000 0x864>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@1000d800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x1000d800 0x80>, + <0x1000da00 0x80>, + <0x1000dc00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10e00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10e00000 0x10000>; + clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>, + <&periph_clk BCM6362_CLK_SWPKT_SAR>, + <&periph_clk BCM6362_CLK_ROBOSW>; + resets = <&periph_rst BCM6362_RST_ENETSW>, + <&periph_rst BCM6362_RST_EPHY>; + dmas = <&iudma BCM6362_DMA_ENETSW_RX>, + <&iudma BCM6362_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi index 65d769ab4f..89590d6ff9 100644 --- a/arch/mips/dts/brcm,bcm6368.dtsi +++ b/arch/mips/dts/brcm,bcm6368.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -192,5 +193,36 @@ status = "disabled"; }; + + iudma: dma-controller@10006800 { + compatible = "brcm,bcm6368-iudma"; + reg = <0x10006800 0x80>, + <0x10006a00 0x80>, + <0x10006c00 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + }; + + enet: ethernet@10f00000 { + compatible = "brcm,bcm6368-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10f00000 0x10000>; + clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>, + <&periph_clk BCM6368_CLK_SWPKT_SAR>, + <&periph_clk BCM6368_CLK_ROBOSW>; + resets = <&periph_rst BCM6368_RST_SWITCH>, + <&periph_rst BCM6368_RST_EPHY>; + dmas = <&iudma BCM6368_DMA_ENETSW_RX>, + <&iudma BCM6368_DMA_ENETSW_TX>; + dma-names = "rx", + "tx"; + brcm,num-ports = <6>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index 1018f9ee49..77d6a8e214 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -31,8 +31,6 @@ clocks { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; u-boot,dm-pre-reloc; periph_osc: periph-osc { diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts new file mode 100644 index 0000000000..8d6417af73 --- /dev/null +++ b/arch/mips/dts/ci20.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "jz4780.dtsi" + +/ { + compatible = "img,ci20", "ingenic,jz4780"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000 + 0x30000000 0x30000000>; + }; +}; + +&ext { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&nemc { + status = "okay"; + + nandc: nand-controller@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + ingenic,bch-controller = <&bch>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + nand@1 { + reg = <1>; + + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x0 0x0 0x800000>; + }; + + partition@0x800000 { + label = "u-boot"; + reg = <0x0 0x800000 0x0 0x200000>; + }; + + partition@0xa00000 { + label = "u-boot-env"; + reg = <0x0 0xa00000 0x0 0x200000>; + }; + + partition@0xc00000 { + label = "boot"; + reg = <0x0 0xc00000 0x0 0x4000000>; + }; + + partition@0x8c00000 { + label = "system"; + reg = <0x0 0x4c00000 0x1 0xfb400000>; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts index 45570189d0..eb60aaa8d5 100644 --- a/arch/mips/dts/comtrend,ar-5315u.dts +++ b/arch/mips/dts/comtrend,ar-5315u.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe4"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe2"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index e993b5cd89..03e3851ab1 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe1"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe2"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe3"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe4"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts index 25747ca95d..f6b8a94e25 100644 --- a/arch/mips/dts/comtrend,ct-5361.dts +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -34,6 +34,18 @@ }; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 8c6a4a1eac..512cb52de3 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -24,6 +24,38 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@0 { + compatible = "brcm,enetsw-port"; + reg = <0>; + label = "fe2"; + brcm,phy-id = <1>; + }; + + port@1 { + compatible = "brcm,enetsw-port"; + reg = <1>; + label = "fe3"; + brcm,phy-id = <2>; + }; + + port@2 { + compatible = "brcm,enetsw-port"; + reg = <2>; + label = "fe4"; + brcm,phy-id = <3>; + }; + + port@3 { + compatible = "brcm,enetsw-port"; + reg = <3>; + label = "fe1"; + brcm,phy-id = <4>; + }; +}; + &leds { status = "okay"; brcm,serial-leds; diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts index bd41dab9f8..7e835b28d2 100644 --- a/arch/mips/dts/comtrend,wap-5813n.dts +++ b/arch/mips/dts/comtrend,wap-5813n.dts @@ -54,6 +54,20 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/gardena-smart-gateway-mt7688.dts b/arch/mips/dts/gardena-smart-gateway-mt7688.dts index ee99c3d17c..d8d88686bb 100644 --- a/arch/mips/dts/gardena-smart-gateway-mt7688.dts +++ b/arch/mips/dts/gardena-smart-gateway-mt7688.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mt7628a.dtsi" +#include / { compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc"; @@ -21,8 +22,65 @@ reg = <0x0 0x08000000>; }; + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + chosen { - bootargs = "console=ttyS0,57600"; stdout-path = &uart0; }; }; diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index 60455c2ff8..6a7fc1df4b 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -93,6 +93,18 @@ status = "okay"; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/jz4780.dtsi b/arch/mips/dts/jz4780.dtsi new file mode 100644 index 0000000000..f62a7a95f8 --- /dev/null +++ b/arch/mips/dts/jz4780.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4780"; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4780-intc"; + reg = <0x10001000 0x50>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + rtc: rtc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: jz4780-cgu@10000000 { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&rtc>; + clock-names = "ext", "rtc"; + + #clock-cells = <1>; + }; + + mmc0: mmc@13450000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13450000 0x1000>; + + status = "disabled"; + + clocks = <&cgu JZ4780_CLK_MSC0>; + clock-names = "mmc"; + }; + + mmc1: mmc@13460000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13460000 0x1000>; + + clocks = <&cgu JZ4780_CLK_MSC1>; + clock-names = "mmc"; + + status = "disabled"; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10030000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <51>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART0>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10031000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <50>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART1>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart3: serial@10033000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10033000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <48>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART3>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart4: serial@10034000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10034000 0x100>; + reg-shift = <2>; + + interrupt-parent = <&intc>; + interrupts = <34>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART4>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + nemc: nemc@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000 + 2 0 0x1a000000 0x1000000 + 3 0 0x19000000 0x1000000 + 4 0 0x18000000 0x1000000 + 5 0 0x17000000 0x1000000 + 6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + status = "disabled"; + }; + + bch: bch@134d0000 { + compatible = "ingenic,jz4780-bch"; + reg = <0x134d0000 0x10000>; + + clocks = <&cgu JZ4780_CLK_BCH>; + + status = "disabled"; + }; +}; diff --git a/arch/mips/dts/linkit-smart-7688.dts b/arch/mips/dts/linkit-smart-7688.dts index df4bf907c6..c9db136f30 100644 --- a/arch/mips/dts/linkit-smart-7688.dts +++ b/arch/mips/dts/linkit-smart-7688.dts @@ -22,7 +22,6 @@ }; chosen { - bootargs = "console=ttyS0,57600"; stdout-path = &uart2; }; }; diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts new file mode 100644 index 0000000000..74f9274c21 --- /dev/null +++ b/arch/mips/dts/luton_pcb091.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,luton.dtsi" + +/ { + model = "Luton10 PCB091 Reference Board"; + compatible = "mscc,luton-pcb091", "mscc,luton"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + spi-cs-high; + }; +}; + diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi new file mode 100644 index 0000000000..6a4ad2a5be --- /dev/null +++ b/arch/mips/dts/mscc,luton.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,luton"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <208333333>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x60000000 0x10200000>; + + uart0: serial@10100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + + compatible = "ns16550a"; + reg = <0x10100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + gpio: pinctrl@70068 { + compatible = "mscc,luton-pinctrl"; + reg = <0x70068 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 32>; + + uart_pins: uart-pins { + pins = "GPIO_30", "GPIO_31"; + function = "uart"; + }; + + }; + + gpio_spi_bitbang: gpio@10000064 { + compatible = "mscc,spi-bitbang-gpio"; + reg = <0x10000064 0x4>; + gpio-controller; + #gpio-cells = <2>; + + }; + + spi0: spi-bitbang { + compatible = "spi-gpio"; + status = "okay"; + gpio-sck = <&gpio_spi_bitbang 6 0>; + gpio-miso = <&gpio_spi_bitbang 0 0>; + gpio-mosi = <&gpio_spi_bitbang 5 0>; + cs-gpios = <&gpio_spi_bitbang 1 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi new file mode 100644 index 0000000000..87b4736285 --- /dev/null +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,ocelot"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x70000000 0x2000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@0 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x0 0x2c>; + }; + + intc: interrupt-controller@70 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + spi0: spi-master@101000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-ssi"; + reg = <0x101000 0x40>; + num-chipselect = <4>; + bus-num = <0>; + reg-io-width = <4>; + reg-shift = <2>; + spi-max-frequency = <18000000>; /* input clock */ + clocks = <&ahb_clk>; + + status = "disabled"; + }; + + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + + gpio: pinctrl@1070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x1070034 0x68>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + + spi_cs1_pin: spi-cs1-pin { + pins = "GPIO_8"; + function = "si"; + }; + + spi_cs2_pin: spi-cs2-pin { + pins = "GPIO_9"; + function = "si"; + }; + + spi_cs3_pin: spi-cs3-pin { + pins = "GPIO_16"; + function = "si"; + }; + + spi_cs4_pin: spi-cs4-pin { + pins = "GPIO_17"; + function = "si"; + }; + }; + }; +}; diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi b/arch/mips/dts/mscc,ocelot_pcb.dtsi new file mode 100644 index 0000000000..90725d3b94 --- /dev/null +++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot.dtsi" + +/ { + compatible = "mscc,ocelot"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi_cs1_pin>; + pinctrl-names = "default"; + + spi-flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; + + spi-nand@1 { + compatible = "spi-nand"; + spi-max-frequency = <18000000>; /* input clock */ + reg = <1>; /* CS1 */ + }; +}; diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index c14259b170..1e7d0a6ec5 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -48,6 +48,17 @@ mask = <0x1>; }; + watchdog: watchdog@100 { + compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; + reg = <0x100 0x30>; + + resets = <&resetc 8>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <24>; + }; + intc: interrupt-controller@200 { compatible = "ralink,rt2880-intc"; reg = <0x200 0x100>; @@ -71,6 +82,38 @@ reg = <0x300 0x100>; }; + gpio@600 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; + reg = <0x600 0x100>; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio0: bank@0 { + reg = <0>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: bank@1 { + reg = <1>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: bank@2 { + reg = <2>; + compatible = "mtk,mt7621-gpio-bank"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x40>; @@ -120,6 +163,14 @@ }; }; + eth@10110000 { + compatible = "mediatek,mt7628-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + + syscon = <&sysc>; + }; + usb_phy: usb-phy@10120000 { compatible = "mediatek,mt7628-usbphy"; reg = <0x10120000 0x1000>; diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts index 322d1567ff..2b72491f0b 100644 --- a/arch/mips/dts/netgear,dgnd3700v2.dts +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -43,6 +43,20 @@ status = "okay"; }; +&enet { + status = "okay"; + + port@4 { + compatible = "brcm,enetsw-port"; + reg = <4>; + label = "rgmii"; + brcm,phy-id = <0xff>; + speed = <1000>; + full-duplex; + bypass-link; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts index e254ab1eaa..6de8584ea7 100644 --- a/arch/mips/dts/nexys4ddr.dts +++ b/arch/mips/dts/nexys4ddr.dts @@ -40,7 +40,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { - compatible = <0x0007c0f0 0xfffffff0>; device_type = "ethernet-phy"; reg = <1>; } ; diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts new file mode 100644 index 0000000000..47d305a614 --- /dev/null +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" + +/ { + model = "Ocelot PCB120 Reference Board"; + compatible = "mscc,ocelot-pcb120", "mscc,ocelot"; +}; diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts new file mode 100644 index 0000000000..17d8d326ce --- /dev/null +++ b/arch/mips/dts/ocelot_pcb123.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "mscc,ocelot_pcb.dtsi" + +/ { + model = "Ocelot PCB123 Reference Board"; + compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi index 599e809c47..ba29ea287e 100644 --- a/arch/mips/dts/qca953x.dtsi +++ b/arch/mips/dts/qca953x.dtsi @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang */ -#include #include "skeleton.dtsi" / { @@ -63,7 +62,6 @@ reg = <0x18020000 0x20>; reg-shift = <2>; clock-frequency = <25000000>; - interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -72,7 +70,6 @@ spi0: spi@1f000000 { compatible = "qca,ar7100-spi"; reg = <0x1f000000 0x10>; - interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts index 5300f8b6df..ec6846dd9f 100644 --- a/arch/mips/dts/sagem,f@st1704.dts +++ b/arch/mips/dts/sagem,f@st1704.dts @@ -39,6 +39,18 @@ }; }; +&enet { + status = "okay"; + phy = <&enetphy>; + phy-mode = "mii"; + + enetphy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio { status = "okay"; }; diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts index bdc6f8ae45..dfbc4148dc 100644 --- a/arch/mips/dts/sfr,nb4-ser.dts +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -53,6 +53,30 @@ status = "okay"; }; +&enet0 { + status = "okay"; + phy = <&enet0phy>; + phy-mode = "internal"; + + enet0phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 3161875441..98b67ccc8e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr) #endif } +#define MIPS32_WHICH_ICACHE 0x0 +#define MIPS32_FETCH_AND_LOCK 0x7 + +#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2)) + +/* Prefetch and lock instructions into cache */ +static inline void icache_lock(void *func, size_t len) +{ + int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; + + for (i = 0; i < lines; i++) { + asm volatile (" cache %0, %1(%2)" + : /* No Output */ + : "I" ICACHE_LOAD_LOCK, + "n" (i * ARCH_DMA_MINALIGN), + "r" (func) + : /* No Clobbers */); + } +} #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 957442effd..7c40e415c7 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -547,6 +547,28 @@ __BUILD_CLRSETBITS(bwlq, sfx, end, type) #define __to_cpu(v) (v) #define cpu_to__(v) (v) +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v),a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le64(a, v) out_arch(q, le64, a, v) +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le64(a) in_arch(q, le64, a) +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be64(a, v) out_arch(q, be64, a, v) +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be64(a) in_arch(q, be64, a) +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + BUILD_CLRSETBITS(b, 8, _, u8) BUILD_CLRSETBITS(w, le16, le16, u16) BUILD_CLRSETBITS(w, be16, be16, u16) diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b7eac323cd..539d0a566d 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -7,7 +7,7 @@ #ifndef _ASM_MACH_GENERIC_SPACES_H #define _ASM_MACH_GENERIC_SPACES_H -#include +#include /* * This gives the physical RAM offset. diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 48fa1f1f7f..f80311e64e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1013,9 +1013,7 @@ do { \ #define __read_64bit_c0_split(source, sel) \ ({ \ unsigned long long __val; \ - unsigned long __flags; \ \ - local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -1034,16 +1032,12 @@ do { \ "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ - local_irq_restore(__flags); \ \ __val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -1064,7 +1058,6 @@ do { \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - local_irq_restore(__flags); \ } while (0) #define __readx_32bit_c0_register(source) \ @@ -2005,6 +1998,17 @@ static inline unsigned int get_ebase_cpunum(void) return read_c0_ebase() & 0x3ff; } +static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, + u32 low1) +{ + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); + tlb_write_indexed(); +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_MIPSREGS_H */ diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h new file mode 100644 index 0000000000..0a847edec8 --- /dev/null +++ b/arch/mips/include/asm/spl.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, + */ +#ifndef _ASM_SPL_H_ +#define _ASM_SPL_H_ + +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, + BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_NONE +}; + +#ifndef CONFIG_DM +extern gd_t gdata; +#endif + +#endif diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index f4bfbdc693..88438b9576 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -7,4 +7,6 @@ void exc_handler(void); void except_vec3_generic(void); void except_vec_ejtag_debug(void); +int arch_misc_init(void); + #endif /* _U_BOOT_MIPS_H_ */ diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 521996599e..b259a931c9 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -25,7 +25,6 @@ config SOC_BMIPS_BCM3380 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_WATCHDOG help This supports BMIPS BCM3380 family. @@ -36,7 +35,6 @@ config SOC_BMIPS_BCM6318 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6318 family. @@ -47,7 +45,6 @@ config SOC_BMIPS_BCM6328 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6328 family including BCM63281 and BCM63283. @@ -58,7 +55,6 @@ config SOC_BMIPS_BCM6338 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6338 family. @@ -69,7 +65,6 @@ config SOC_BMIPS_BCM6348 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_WATCHDOG help This supports BMIPS BCM6348 family. @@ -80,7 +75,6 @@ config SOC_BMIPS_BCM6358 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6358 family including BCM6358 and BCM6359. @@ -91,7 +85,6 @@ config SOC_BMIPS_BCM6368 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6368 family including BCM6368 and BCM6369. @@ -102,7 +95,6 @@ config SOC_BMIPS_BCM6362 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6362 family including BCM6361 and BCM6362. @@ -113,7 +105,6 @@ config SOC_BMIPS_BCM63268 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM63268 family including BCM63168, BCM63169, @@ -125,7 +116,6 @@ config SOC_BMIPS_BCM6838 select MIPS_TUNE_4KC select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 - select SWAP_IO_SPACE select SYSRESET_SYSCON help This supports BMIPS BCM6838 family including BCM68380, BCM68381, diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig new file mode 100644 index 0000000000..dcaac01628 --- /dev/null +++ b/arch/mips/mach-jz47xx/Kconfig @@ -0,0 +1,26 @@ +menu "Ingenic JZ47xx platforms" + depends on ARCH_JZ47XX + +config SYS_SOC + default "jz47xx" + +config SOC_JZ4780 + bool + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + help + Support for Ingenic JZ4780 family SoCs. + +choice + prompt "Board select" + +config TARGET_JZ4780_CI20 + bool "Creator CI20 Reference Board" + select SOC_JZ4780 + +endchoice + +source "board/imgtec/ci20/Kconfig" + +endmenu diff --git a/arch/mips/mach-jz47xx/Makefile b/arch/mips/mach-jz47xx/Makefile new file mode 100644 index 0000000000..dbb8229f78 --- /dev/null +++ b/arch/mips/mach-jz47xx/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +extra-$(CONFIG_SPL_BUILD) := start.o + +obj-$(CONFIG_SOC_JZ4780) += jz4780/ diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h new file mode 100644 index 0000000000..4422e503ed --- /dev/null +++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * JZ4780 definitions + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#ifndef __JZ4780_H__ +#define __JZ4780_H__ + +/* AHB0 BUS Devices */ +#define DDRC_BASE 0xb3010000 + +/* AHB2 BUS Devices */ +#define NEMC_BASE 0xb3410000 +#define BCH_BASE 0xb34d0000 + +/* APB BUS Devices */ +#define CPM_BASE 0xb0000000 +#define TCU_BASE 0xb0002000 +#define WDT_BASE 0xb0002000 +#define GPIO_BASE 0xb0010000 +#define UART0_BASE 0xb0030000 +#define UART1_BASE 0xb0031000 +#define UART2_BASE 0xb0032000 +#define UART3_BASE 0xb0033000 +#define MSC0_BASE 0xb3450000 +#define MSC1_BASE 0xb3460000 +#define MSC2_BASE 0xb3470000 + +/* + * GPIO + */ +/* n = 0,1,2,3,4,5 */ +#define GPIO_PXPIN(n) (0x00 + (n) * 0x100) +#define GPIO_PXINT(n) (0x10 + (n) * 0x100) +#define GPIO_PXINTS(n) (0x14 + (n) * 0x100) +#define GPIO_PXINTC(n) (0x18 + (n) * 0x100) +#define GPIO_PXMASK(n) (0x20 + (n) * 0x100) +#define GPIO_PXMASKS(n) (0x24 + (n) * 0x100) +#define GPIO_PXMASKC(n) (0x28 + (n) * 0x100) +#define GPIO_PXPAT1(n) (0x30 + (n) * 0x100) +#define GPIO_PXPAT1S(n) (0x34 + (n) * 0x100) +#define GPIO_PXPAT1C(n) (0x38 + (n) * 0x100) +#define GPIO_PXPAT0(n) (0x40 + (n) * 0x100) +#define GPIO_PXPAT0S(n) (0x44 + (n) * 0x100) +#define GPIO_PXPAT0C(n) (0x48 + (n) * 0x100) +#define GPIO_PXFLG(n) (0x50 + (n) * 0x100) +#define GPIO_PXFLGC(n) (0x54 + (n) * 0x100) +#define GPIO_PXOEN(n) (0x60 + (n) * 0x100) +#define GPIO_PXOENS(n) (0x64 + (n) * 0x100) +#define GPIO_PXOENC(n) (0x68 + (n) * 0x100) +#define GPIO_PXPEN(n) (0x70 + (n) * 0x100) +#define GPIO_PXPENS(n) (0x74 + (n) * 0x100) +#define GPIO_PXPENC(n) (0x78 + (n) * 0x100) +#define GPIO_PXDS(n) (0x80 + (n) * 0x100) +#define GPIO_PXDSS(n) (0x84 + (n) * 0x100) +#define GPIO_PXDSC(n) (0x88 + (n) * 0x100) + +/* PLL setup */ +#define JZ4780_SYS_EXTAL 48000000 +#define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000) +#define JZ4780_SYS_MEM_DIV 3 +#define JZ4780_SYS_AUDIO_SPEED (768 * 1000000) + +#define JZ4780_APLL_M 1 +#define JZ4780_APLL_N 1 +#define JZ4780_APLL_OD 1 + +#define JZ4780_MPLL_M (JZ4780_SYS_MEM_SPEED / JZ4780_SYS_EXTAL * 2) +#define JZ4780_MPLL_N 2 +#define JZ4780_MPLL_OD 1 + +#define JZ4780_EPLL_M (JZ4780_SYS_AUDIO_SPEED * 2 / JZ4780_SYS_EXTAL) +#define JZ4780_EPLL_N 1 +#define JZ4780_EPLL_OD 2 + +#define JZ4780_VPLL_M ((888 * 1000000) * 2 / JZ4780_SYS_EXTAL) +#define JZ4780_VPLL_N 1 +#define JZ4780_VPLL_OD 2 + +#ifndef __ASSEMBLY__ + +u32 sdram_size(int bank); + +const u32 jz4780_clk_get_efuse_clk(void); +void jz4780_clk_ungate_ethernet(void); +void jz4780_clk_ungate_mmc(void); +void jz4780_clk_ungate_uart(const unsigned int uart); + +void jz4780_efuse_read(size_t addr, size_t count, u8 *buf); +void jz4780_efuse_init(u32 ahb2_rate); + +void jz4780_tcu_wdt_start(void); + +#ifdef CONFIG_SPL_BUILD +int jz_mmc_init(void __iomem *base); +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __JZ4780_H__ */ diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h new file mode 100644 index 0000000000..92d431bd04 --- /dev/null +++ b/arch/mips/mach-jz47xx/include/mach/jz4780_dram.h @@ -0,0 +1,456 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * JZ4780 DDR initialization - parameters definitions + * + * Copyright (c) 2015 Imagination Technologies + * Author: Matt Redfearn + */ + +#ifndef __JZ4780_DRAM_H__ +#define __JZ4780_DRAM_H__ + +/* + * DDR + */ +#define DDRC_ST 0x0 +#define DDRC_CFG 0x4 +#define DDRC_CTRL 0x8 +#define DDRC_LMR 0xc +#define DDRC_REFCNT 0x18 +#define DDRC_DQS 0x1c +#define DDRC_DQS_ADJ 0x20 +#define DDRC_MMAP0 0x24 +#define DDRC_MMAP1 0x28 +#define DDRC_MDELAY 0x2c +#define DDRC_CKEL 0x30 +#define DDRC_PMEMCTRL0 0x54 +#define DDRC_PMEMCTRL1 0x50 +#define DDRC_PMEMCTRL2 0x58 +#define DDRC_PMEMCTRL3 0x5c + +#define DDRC_TIMING(n) (0x60 + 4 * (n)) +#define DDRC_REMMAP(n) (0x9c + 4 * (n)) + +/* + * DDR PHY + */ +#define DDR_MEM_PHY_BASE 0x20000000 +#define DDR_PHY_OFFSET 0x1000 + +#define DDRP_PIR 0x4 +#define DDRP_PGCR 0x8 +#define DDRP_PGSR 0xc + +#define DDRP_PTR0 0x18 +#define DDRP_PTR1 0x1c +#define DDRP_PTR2 0x20 + +#define DDRP_ACIOCR 0x24 +#define DDRP_DXCCR 0x28 +#define DDRP_DSGCR 0x2c +#define DDRP_DCR 0x30 + +#define DDRP_DTPR0 0x34 +#define DDRP_DTPR1 0x38 +#define DDRP_DTPR2 0x3c +#define DDRP_MR0 0x40 +#define DDRP_MR1 0x44 +#define DDRP_MR2 0x48 +#define DDRP_MR3 0x4c + +#define DDRP_ODTCR 0x50 +#define DDRP_DTAR 0x54 +#define DDRP_DTDR0 0x58 +#define DDRP_DTDR1 0x5c + +#define DDRP_DCUAR 0xc0 +#define DDRP_DCUDR 0xc4 +#define DDRP_DCURR 0xc8 +#define DDRP_DCULR 0xcc +#define DDRP_DCUGCR 0xd0 +#define DDRP_DCUTPR 0xd4 +#define DDRP_DCUSR0 0xd8 +#define DDRP_DCUSR1 0xdc + +#define DDRP_ZQXCR0(n) (0x180 + ((n) * 0x10)) +#define DDRP_ZQXCR1(n) (0x184 + ((n) * 0x10)) +#define DDRP_ZQXSR0(n) (0x188 + ((n) * 0x10)) +#define DDRP_ZQXSR1(n) (0x18c + ((n) * 0x10)) + +#define DDRP_DXGCR(n) (0x1c0 + ((n) * 0x40)) +#define DDRP_DXGSR0(n) (0x1c4 + ((n) * 0x40)) +#define DDRP_DXGSR1(n) (0x1c8 + ((n) * 0x40)) +#define DDRP_DXDQSTR(n) (0x1d4 + ((n) * 0x40)) + +/* DDRC Status Register */ +#define DDRC_ST_ENDIAN BIT(7) +#define DDRC_ST_DPDN BIT(5) +#define DDRC_ST_PDN BIT(4) +#define DDRC_ST_AREF BIT(3) +#define DDRC_ST_SREF BIT(2) +#define DDRC_ST_CKE1 BIT(1) +#define DDRC_ST_CKE0 BIT(0) + +/* DDRC Configure Register */ +#define DDRC_CFG_ROW1_BIT 27 +#define DDRC_CFG_ROW1_MASK (0x7 << DDRC_CFG_ROW1_BIT) +#define DDRC_CFG_COL1_BIT 24 +#define DDRC_CFG_COL1_MASK (0x7 << DDRC_CFG_COL1_BIT) +#define DDRC_CFG_BA1 BIT(23) +#define DDRC_CFG_IMBA BIT(22) +#define DDRC_CFG_BL_8 BIT(21) + +#define DDRC_CFG_TYPE_BIT 17 +#define DDRC_CFG_TYPE_MASK (0x7 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_DDR1 (2 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_MDDR (3 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_DDR2 (4 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_LPDDR2 (5 << DDRC_CFG_TYPE_BIT) +#define DDRC_CFG_TYPE_DDR3 (6 << DDRC_CFG_TYPE_BIT) + +#define DDRC_CFG_ODT_EN BIT(16) + +#define DDRC_CFG_MPRT BIT(15) + +#define DDRC_CFG_ROW_BIT 11 +#define DDRC_CFG_ROW_MASK (0x7 << DDRC_CFG_ROW_BIT) +#define DDRC_CFG_ROW_12 (0 << DDRC_CFG_ROW_BIT) +#define DDRC_CFG_ROW_13 (1 << DDRC_CFG_ROW_BIT) +#define DDRC_CFG_ROW_14 (2 << DDRC_CFG_ROW_BIT) + +#define DDRC_CFG_COL_BIT 8 +#define DDRC_CFG_COL_MASK (0x7 << DDRC_CFG_COL_BIT) +#define DDRC_CFG_COL_8 (0 << DDRC_CFG_COL_BIT) +#define DDRC_CFG_COL_9 (1 << DDRC_CFG_COL_BIT) +#define DDRC_CFG_COL_10 (2 << DDRC_CFG_COL_BIT) +#define DDRC_CFG_COL_11 (3 << DDRC_CFG_COL_BIT) + +#define DDRC_CFG_CS1EN BIT(7) +#define DDRC_CFG_CS0EN BIT(6) +#define DDRC_CFG_CL_BIT 2 +#define DDRC_CFG_CL_MASK (0xf << DDRC_CFG_CL_BIT) +#define DDRC_CFG_CL_3 (0 << DDRC_CFG_CL_BIT) +#define DDRC_CFG_CL_4 (1 << DDRC_CFG_CL_BIT) +#define DDRC_CFG_CL_5 (2 << DDRC_CFG_CL_BIT) +#define DDRC_CFG_CL_6 (3 << DDRC_CFG_CL_BIT) + +#define DDRC_CFG_BA BIT(1) +#define DDRC_CFG_DW BIT(0) + +/* DDRC Control Register */ +#define DDRC_CTRL_DFI_RST BIT(23) +#define DDRC_CTRL_DLL_RST BIT(22) +#define DDRC_CTRL_CTL_RST BIT(21) +#define DDRC_CTRL_CFG_RST BIT(20) +#define DDRC_CTRL_ACTPD BIT(15) +#define DDRC_CTRL_PDT_BIT 12 +#define DDRC_CTRL_PDT_MASK (0x7 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_DIS (0 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_8 (1 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_16 (2 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_32 (3 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_64 (4 << DDRC_CTRL_PDT_BIT) +#define DDRC_CTRL_PDT_128 (5 << DDRC_CTRL_PDT_BIT) + +#define DDRC_CTRL_PRET_BIT 8 +#define DDRC_CTRL_PRET_MASK (0x7 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_DIS (0 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_8 (1 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_16 (2 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_32 (3 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_64 (4 << DDRC_CTRL_PRET_BIT) +#define DDRC_CTRL_PRET_128 (5 << DDRC_CTRL_PRET_BIT) + +#define DDRC_CTRL_DPD BIT(6) +#define DDRC_CTRL_SR BIT(5) +#define DDRC_CTRL_UNALIGN BIT(4) +#define DDRC_CTRL_ALH BIT(3) +#define DDRC_CTRL_RDC BIT(2) +#define DDRC_CTRL_CKE BIT(1) +#define DDRC_CTRL_RESET BIT(0) + +/* DDRC Load-Mode-Register */ +#define DDRC_LMR_DDR_ADDR_BIT 16 +#define DDRC_LMR_DDR_ADDR_MASK (0x3fff << DDRC_LMR_DDR_ADDR_BIT) + +#define DDRC_LMR_BA_BIT 8 +#define DDRC_LMR_BA_MASK (0x7 << DDRC_LMR_BA_BIT) +/* For DDR2 */ +#define DDRC_LMR_BA_MRS (0 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_EMRS1 (1 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_EMRS2 (2 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_EMRS3 (3 << DDRC_LMR_BA_BIT) +/* For mobile DDR */ +#define DDRC_LMR_BA_M_MRS (0 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_M_EMRS (2 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_M_SR (1 << DDRC_LMR_BA_BIT) +/* For Normal DDR1 */ +#define DDRC_LMR_BA_N_MRS (0 << DDRC_LMR_BA_BIT) +#define DDRC_LMR_BA_N_EMRS (1 << DDRC_LMR_BA_BIT) + +#define DDRC_LMR_CMD_BIT 4 +#define DDRC_LMR_CMD_MASK (0x3 << DDRC_LMR_CMD_BIT) +#define DDRC_LMR_CMD_PREC (0 << DDRC_LMR_CMD_BIT) +#define DDRC_LMR_CMD_AUREF (1 << DDRC_LMR_CMD_BIT) +#define DDRC_LMR_CMD_LMR (2 << DDRC_LMR_CMD_BIT) + +#define DDRC_LMR_START BIT(0) + +/* DDRC Timing Config Register 1 */ +#define DDRC_TIMING1_TRTP_BIT 24 +#define DDRC_TIMING1_TRTP_MASK (0x3f << DDRC_TIMING1_TRTP_BIT) +#define DDRC_TIMING1_TWTR_BIT 16 +#define DDRC_TIMING1_TWTR_MASK (0x3f << DDRC_TIMING1_TWTR_BIT) +#define DDRC_TIMING1_TWTR_1 (0 << DDRC_TIMING1_TWTR_BIT) +#define DDRC_TIMING1_TWTR_2 (1 << DDRC_TIMING1_TWTR_BIT) +#define DDRC_TIMING1_TWTR_3 (2 << DDRC_TIMING1_TWTR_BIT) +#define DDRC_TIMING1_TWTR_4 (3 << DDRC_TIMING1_TWTR_BIT) +#define DDRC_TIMING1_TWR_BIT 8 +#define DDRC_TIMING1_TWR_MASK (0x3f << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_1 (0 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_2 (1 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_3 (2 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_4 (3 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_5 (4 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWR_6 (5 << DDRC_TIMING1_TWR_BIT) +#define DDRC_TIMING1_TWL_BIT 0 +#define DDRC_TIMING1_TWL_MASK (0x3f << DDRC_TIMING1_TWL_BIT) + +/* DDRC Timing Config Register 2 */ +#define DDRC_TIMING2_TCCD_BIT 24 +#define DDRC_TIMING2_TCCD_MASK (0x3f << DDRC_TIMING2_TCCD_BIT) +#define DDRC_TIMING2_TRAS_BIT 16 +#define DDRC_TIMING2_TRAS_MASK (0x3f << DDRC_TIMING2_TRAS_BIT) +#define DDRC_TIMING2_TRCD_BIT 8 +#define DDRC_TIMING2_TRCD_MASK (0x3f << DDRC_TIMING2_TRCD_BIT) +#define DDRC_TIMING2_TRL_BIT 0 +#define DDRC_TIMING2_TRL_MASK (0x3f << DDRC_TIMING2_TRL_BIT) + +/* DDRC Timing Config Register 3 */ +#define DDRC_TIMING3_ONUM 27 +#define DDRC_TIMING3_TCKSRE_BIT 24 +#define DDRC_TIMING3_TCKSRE_MASK (0x3f << DDRC_TIMING3_TCKSRE_BIT) +#define DDRC_TIMING3_TRP_BIT 16 +#define DDRC_TIMING3_TRP_MASK (0x3f << DDRC_TIMING3_TRP_BIT) +#define DDRC_TIMING3_TRRD_BIT 8 +#define DDRC_TIMING3_TRRD_MASK (0x3f << DDRC_TIMING3_TRRD_BIT) +#define DDRC_TIMING3_TRRD_DISABLE (0 << DDRC_TIMING3_TRRD_BIT) +#define DDRC_TIMING3_TRRD_2 (1 << DDRC_TIMING3_TRRD_BIT) +#define DDRC_TIMING3_TRRD_3 (2 << DDRC_TIMING3_TRRD_BIT) +#define DDRC_TIMING3_TRRD_4 (3 << DDRC_TIMING3_TRRD_BIT) +#define DDRC_TIMING3_TRC_BIT 0 +#define DDRC_TIMING3_TRC_MASK (0x3f << DDRC_TIMING3_TRC_BIT) + +/* DDRC Timing Config Register 4 */ +#define DDRC_TIMING4_TRFC_BIT 24 +#define DDRC_TIMING4_TRFC_MASK (0x3f << DDRC_TIMING4_TRFC_BIT) +#define DDRC_TIMING4_TEXTRW_BIT 21 +#define DDRC_TIMING4_TEXTRW_MASK (0x7 << DDRC_TIMING4_TEXTRW_BIT) +#define DDRC_TIMING4_TRWCOV_BIT 19 +#define DDRC_TIMING4_TRWCOV_MASK (0x3 << DDRC_TIMING4_TRWCOV_BIT) +#define DDRC_TIMING4_TCKE_BIT 16 +#define DDRC_TIMING4_TCKE_MASK (0x7 << DDRC_TIMING4_TCKE_BIT) +#define DDRC_TIMING4_TMINSR_BIT 8 +#define DDRC_TIMING4_TMINSR_MASK (0xf << DDRC_TIMING4_TMINSR_BIT) +#define DDRC_TIMING4_TXP_BIT 4 +#define DDRC_TIMING4_TXP_MASK (0x7 << DDRC_TIMING4_TXP_BIT) +#define DDRC_TIMING4_TMRD_BIT 0 +#define DDRC_TIMING4_TMRD_MASK (0x3 << DDRC_TIMING4_TMRD_BIT) + +/* DDRC Timing Config Register 5 */ +#define DDRC_TIMING5_TCTLUPD_BIT 24 +#define DDRC_TIMING4_TCTLUPD_MASK (0x3f << DDRC_TIMING5_TCTLUDP_BIT) +#define DDRC_TIMING5_TRTW_BIT 16 +#define DDRC_TIMING5_TRTW_MASK (0x3f << DDRC_TIMING5_TRTW_BIT) +#define DDRC_TIMING5_TRDLAT_BIT 8 +#define DDRC_TIMING5_TRDLAT_MASK (0x3f << DDRC_TIMING5_TRDLAT_BIT) +#define DDRC_TIMING5_TWDLAT_BIT 0 +#define DDRC_TIMING5_TWDLAT_MASK (0x3f << DDRC_TIMING5_TWDLAT_BIT) + +/* DDRC Timing Config Register 6 */ +#define DDRC_TIMING6_TXSRD_BIT 24 +#define DDRC_TIMING6_TXSRD_MASK (0x3f << DDRC_TIMING6_TXSRD_BIT) +#define DDRC_TIMING6_TFAW_BIT 16 +#define DDRC_TIMING6_TFAW_MASK (0x3f << DDRC_TIMING6_TFAW_BIT) +#define DDRC_TIMING6_TCFGW_BIT 8 +#define DDRC_TIMING6_TCFGW_MASK (0x3f << DDRC_TIMING6_TCFGW_BIT) +#define DDRC_TIMING6_TCFGR_BIT 0 +#define DDRC_TIMING6_TCFGR_MASK (0x3f << DDRC_TIMING6_TCFGR_BIT) + +/* DDRC Auto-Refresh Counter */ +#define DDRC_REFCNT_CON_BIT 16 +#define DDRC_REFCNT_CON_MASK (0xff << DDRC_REFCNT_CON_BIT) +#define DDRC_REFCNT_CNT_BIT 8 +#define DDRC_REFCNT_CNT_MASK (0xff << DDRC_REFCNT_CNT_BIT) +#define DDRC_REFCNT_CLKDIV_BIT 1 +#define DDRC_REFCNT_CLKDIV_MASK (0x7 << DDRC_REFCNT_CLKDIV_BIT) +#define DDRC_REFCNT_REF_EN BIT(0) + +/* DDRC DQS Delay Control Register */ +#define DDRC_DQS_ERROR BIT(29) +#define DDRC_DQS_READY BIT(28) +#define DDRC_DQS_AUTO BIT(23) +#define DDRC_DQS_DET BIT(24) +#define DDRC_DQS_SRDET BIT(25) +#define DDRC_DQS_CLKD_BIT 16 +#define DDRC_DQS_CLKD_MASK (0x3f << DDRC_DQS_CLKD_BIT) +#define DDRC_DQS_WDQS_BIT 8 +#define DDRC_DQS_WDQS_MASK (0x3f << DDRC_DQS_WDQS_BIT) +#define DDRC_DQS_RDQS_BIT 0 +#define DDRC_DQS_RDQS_MASK (0x3f << DDRC_DQS_RDQS_BIT) + +/* DDRC DQS Delay Adjust Register */ +#define DDRC_DQS_ADJWDQS_BIT 8 +#define DDRC_DQS_ADJWDQS_MASK (0x1f << DDRC_DQS_ADJWDQS_BIT) +#define DDRC_DQS_ADJRDQS_BIT 0 +#define DDRC_DQS_ADJRDQS_MASK (0x1f << DDRC_DQS_ADJRDQS_BIT) + +/* DDRC Memory Map Config Register */ +#define DDRC_MMAP_BASE_BIT 8 +#define DDRC_MMAP_BASE_MASK (0xff << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP_MASK_BIT 0 +#define DDRC_MMAP_MASK_MASK (0xff << DDRC_MMAP_MASK_BIT) + +#define DDRC_MMAP0_BASE (0x20 << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP1_BASE_64M (0x24 << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP1_BASE_128M (0x28 << DDRC_MMAP_BASE_BIT) +#define DDRC_MMAP1_BASE_256M (0x30 << DDRC_MMAP_BASE_BIT) + +#define DDRC_MMAP_MASK_64_64 (0xfc << DDRC_MMAP_MASK_BIT) +#define DDRC_MMAP_MASK_128_128 (0xf8 << DDRC_MMAP_MASK_BIT) +#define DDRC_MMAP_MASK_256_256 (0xf0 << DDRC_MMAP_MASK_BIT) + +/* DDRP PHY Initialization Register */ +#define DDRP_PIR_INIT BIT(0) +#define DDRP_PIR_DLLSRST BIT(1) +#define DDRP_PIR_DLLLOCK BIT(2) +#define DDRP_PIR_ZCAL BIT(3) +#define DDRP_PIR_ITMSRST BIT(4) +#define DDRP_PIR_DRAMRST BIT(5) +#define DDRP_PIR_DRAMINT BIT(6) +#define DDRP_PIR_QSTRN BIT(7) +#define DDRP_PIR_EYETRN BIT(8) +#define DDRP_PIR_DLLBYP BIT(17) +/* DDRP PHY General Configurate Register */ +#define DDRP_PGCR_ITMDMD BIT(0) +#define DDRP_PGCR_DQSCFG BIT(1) +#define DDRP_PGCR_DFTCMP BIT(2) +#define DDRP_PGCR_DFTLMT_BIT 3 +#define DDRP_PGCR_DTOSEL_BIT 5 +#define DDRP_PGCR_CKEN_BIT 9 +#define DDRP_PGCR_CKDV_BIT 12 +#define DDRP_PGCR_CKINV BIT(14) +#define DDRP_PGCR_RANKEN_BIT 18 +#define DDRP_PGCR_ZCKSEL_32 (2 << 22) +#define DDRP_PGCR_PDDISDX BIT(24) +/* DDRP PHY General Status Register */ +#define DDRP_PGSR_IDONE BIT(0) +#define DDRP_PGSR_DLDONE BIT(1) +#define DDRP_PGSR_ZCDONE BIT(2) +#define DDRP_PGSR_DIDONE BIT(3) +#define DDRP_PGSR_DTDONE BIT(4) +#define DDRP_PGSR_DTERR BIT(5) +#define DDRP_PGSR_DTIERR BIT(6) +#define DDRP_PGSR_DFTEERR BIT(7) +/* DDRP DRAM Configuration Register */ +#define DDRP_DCR_TYPE_BIT 0 +#define DDRP_DCR_TYPE_MASK (0x7 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_TYPE_MDDR (0 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_TYPE_DDR (1 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_TYPE_DDR2 (2 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_TYPE_DDR3 (3 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_TYPE_LPDDR2 (4 << DDRP_DCR_TYPE_BIT) +#define DDRP_DCR_DDR8BNK_BIT 3 +#define DDRP_DCR_DDR8BNK_MASK (1 << DDRP_DCR_DDR8BNK_BIT) +#define DDRP_DCR_DDR8BNK (1 << DDRP_DCR_DDR8BNK_BIT) +#define DDRP_DCR_DDR8BNK_DIS (0 << DDRP_DCR_DDR8BNK_BIT) + +#define DRP_DTRP1_RTODT BIT(11) + +#define DDRP_DXGCR_DXEN BIT(0) + +#define DDRP_ZQXCR_ZDEN_BIT 28 +#define DDRP_ZQXCR_ZDEN (1 << DDRP_ZQXCR_ZDEN_BIT) +#define DDRP_ZQXCR_PULLUP_IMPE_BIT 5 +#define DDRP_ZQXCR_PULLDOWN_IMPE_BIT 0 + +/* DDR3 Mode Register Set */ +#define DDR3_MR0_BL_BIT 0 +#define DDR3_MR0_BL_MASK (3 << DDR3_MR0_BL_BIT) +#define DDR3_MR0_BL_8 (0 << DDR3_MR0_BL_BIT) +#define DDR3_MR0_BL_fly (1 << DDR3_MR0_BL_BIT) +#define DDR3_MR0_BL_4 (2 << DDR3_MR0_BL_BIT) +#define DDR3_MR0_BT_BIT 3 +#define DDR3_MR0_BT_MASK (1 << DDR3_MR0_BT_BIT) +#define DDR3_MR0_BT_SEQ (0 << DDR3_MR0_BT_BIT) +#define DDR3_MR0_BT_INTER (1 << DDR3_MR0_BT_BIT) +#define DDR3_MR0_WR_BIT 9 + +#define DDR3_MR1_DLL_DISABLE 1 +#define DDR3_MR1_DIC_6 (0 << 5 | 0 << 1) +#define DDR3_MR1_DIC_7 (0 << 5 | BIT(1)) +#define DDR3_MR1_RTT_DIS (0 << 9 | 0 << 6 | 0 << 2) +#define DDR3_MR1_RTT_4 (0 << 9 | 0 << 6 | BIT(2)) +#define DDR3_MR1_RTT_2 (0 << 9 | BIT(6) | 0 << 2) +#define DDR3_MR1_RTT_6 (0 << 9 | BIT(6) | BIT(2)) +#define DDR3_MR1_RTT_12 (BIT(9) | 0 << 6 | 0 << 2) +#define DDR3_MR1_RTT_8 (BIT(9) | 0 << 6 | BIT(2)) + +#define DDR3_MR2_CWL_BIT 3 + +/* Parameters common to all RAM devices used */ + +/* Chip Select */ +/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */ +#define DDR_CS0EN 1 +/* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */ +#define DDR_CS1EN 0 + +/* ROW : 12 to 18 row address, 1G only 512MB */ +#define DDR_ROW 15 +/* COL : 8 to 14 column address */ +#define DDR_COL 10 +/* Banks each chip: 0-4bank, 1-8bank */ +#define DDR_BANK8 1 +/* 0 - 16-bit data width, 1 - 32-bit data width */ +#define DDR_DW32 1 + +/* Refresh period: 64ms / 32768 = 1.95 us , 2 ^ 15 = 32768 */ +#define DDR_tREFI 7800 +/* Clock Divider */ +#define DDR_CLK_DIV 1 + +/* DDR3 Burst length: 0 - 8 burst, 2 - 4 burst , 1 - 4 or 8 (on the fly) */ +#define DDR_BL 8 + +/* CAS latency: 5 to 14, tCK */ +#define DDR_CL 6 +/* DDR3 only: CAS Write Latency, 5 to 8 */ +#define DDR_tCWL (DDR_CL - 1) + +/* Structure representing per-RAM type configuration */ + +struct jz4780_ddr_config { + u32 timing[6]; /* Timing1..6 register value */ + + /* DDR PHY control */ + u16 mr0; /* Mode Register 0 */ + u16 mr1; /* Mode Register 1 */ + + u32 ptr0; /* PHY Timing Register 0 */ + u32 ptr1; /* PHY Timing Register 1 */ + u32 ptr2; /* PHY Timing Register 1 */ + + u32 dtpr0; /* DRAM Timing Parameters Register 0 */ + u32 dtpr1; /* DRAM Timing Parameters Register 1 */ + u32 dtpr2; /* DRAM Timing Parameters Register 2 */ + + u8 pullup; /* PHY pullup impedance */ + u8 pulldn; /* PHY pulldown impedance */ +}; + +void pll_init(void); +void sdram_init(void); + +#endif /* __JZ4780_DRAM_H__ */ + diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h b/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h new file mode 100644 index 0000000000..37f0892f7b --- /dev/null +++ b/arch/mips/mach-jz47xx/include/mach/jz4780_gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __JZ4780_GPIO_H__ +#define __JZ4780_GPIO_H__ + +#define JZ_GPIO(bank, pin) ((32 * (bank)) + (pin)) + +int jz47xx_gpio_get_value(unsigned int gpio); +void jz47xx_gpio_direction_input(unsigned int gpio); +void jz47xx_gpio_direction_output(unsigned int gpio, int value); + +#endif diff --git a/arch/mips/mach-jz47xx/jz4780/Makefile b/arch/mips/mach-jz47xx/jz4780/Makefile new file mode 100644 index 0000000000..5b3c354327 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := gpio.o jz4780.o pll.o reset.o sdram.o timer.o diff --git a/arch/mips/mach-jz47xx/jz4780/TODO b/arch/mips/mach-jz47xx/jz4780/TODO new file mode 100644 index 0000000000..99ad6225b0 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/TODO @@ -0,0 +1,4 @@ +- dm gpio driver +- ethernet driver for the dm9000 +- reduce the hundreds of definitions of register addresses to the ones really needed in assembly or SPL. +- define the remaining register base addresses as physical addresses and establish a mapping with ioremap_nocache() diff --git a/arch/mips/mach-jz47xx/jz4780/gpio.c b/arch/mips/mach-jz47xx/jz4780/gpio.c new file mode 100644 index 0000000000..cee2328ab1 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/gpio.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include + +int jz47xx_gpio_get_value(unsigned int gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); +} + +void jz47xx_gpio_direction_input(unsigned int gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); +} + +void jz47xx_gpio_direction_output(unsigned int gpio, int value) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); + writel(BIT(pin), gpio_regs + + (value ? GPIO_PXPAT0S(port) : GPIO_PXPAT0C(port))); +} diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c new file mode 100644 index 0000000000..dbd328cb49 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 common routines + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +/* Pointer to the global data structure for SPL */ +DECLARE_GLOBAL_DATA_PTR; +gd_t gdata __attribute__ ((section(".bss"))); + +void board_init_f(ulong dummy) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + struct mmc *mmc; + unsigned long count; + struct image_header *header; + int ret; + + /* Set global data pointer */ + gd = &gdata; + + timer_init(); + pll_init(); + sdram_init(); + enable_caches(); + + /* Clear the BSS */ + memset(__bss_start, 0, (char *)&__bss_end - __bss_start); + + gd->flags |= GD_FLG_SPL_INIT; + + ret = mmc_initialize(NULL); + if (ret) + hang(); + + mmc = find_mmc_device(BOOT_DEVICE_MMC1); + if (ret) + hang(); + + ret = mmc_init(mmc); + if (ret) + hang(); + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + count = blk_dread(mmc_get_blk_desc(mmc), + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, + 0x800, header); + if (count == 0) + hang(); + + image_entry_noargs_t image_entry = + (image_entry_noargs_t)CONFIG_SYS_TEXT_BASE; + + image_entry(); + + hang(); +} +#endif /* CONFIG_SPL_BUILD */ + +ulong board_get_usable_ram_top(ulong total_size) +{ + return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); +} + +int print_cpuinfo(void) +{ + printf("CPU: Ingenic JZ4780\n"); + return 0; +} diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c new file mode 100644 index 0000000000..9a46198f36 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/pll.c @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 PLL setup + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include + +#define CPM_CPCCR 0x00 +#define CPM_LCR 0x04 +#define CPM_RSR 0x08 +#define CPM_CPPCR 0x0c +#define CPM_CPAPCR 0x10 +#define CPM_CPMPCR 0x14 +#define CPM_CPEPCR 0x18 +#define CPM_CPVPCR 0x1c +#define CPM_CLKGR0 0x20 +#define CPM_OPCR 0x24 +#define CPM_CLKGR1 0x28 +#define CPM_DDCDR 0x2c +#define CPM_VPUCDR 0x30 +#define CPM_CPSPR 0x34 +#define CPM_CPSPPR 0x38 +#define CPM_USBPCR 0x3c +#define CPM_USBRDT 0x40 +#define CPM_USBVBFIL 0x44 +#define CPM_USBPCR1 0x48 +#define CPM_USBCDR 0x50 +#define CPM_LPCDR 0x54 +#define CPM_I2SCDR 0x60 +#define CPM_LPCDR1 0x64 +#define CPM_MSCCDR 0x68 +#define CPM_UHCCDR 0x6c +#define CPM_SSICDR 0x74 +#define CPM_CIMCDR 0x7c +#define CPM_PCMCDR 0x84 +#define CPM_GPUCDR 0x88 +#define CPM_HDMICDR 0x8c +#define CPM_I2S1CDR 0xa0 +#define CPM_MSCCDR1 0xa4 +#define CPM_MSCCDR2 0xa8 +#define CPM_BCHCDR 0xac +#define CPM_SPCR0 0xb8 +#define CPM_SPCR1 0xbc +#define CPM_CPCSR 0xd4 +#define CPM_PSWCST(n) ((0x4 * (n)) + 0x90) + +/* Clock control register */ +#define CPM_CPCCR_SEL_SRC_BIT 30 +#define CPM_CPCCR_SEL_SRC_MASK (0x3 << CPM_CPCCR_SEL_SRC_BIT) +#define CPM_SRC_SEL_STOP 0 +#define CPM_SRC_SEL_APLL 1 +#define CPM_SRC_SEL_EXCLK 2 +#define CPM_SRC_SEL_RTCLK 3 +#define CPM_CPCCR_SEL_CPLL_BIT 28 +#define CPM_CPCCR_SEL_CPLL_MASK (0x3 << CPM_CPCCR_SEL_CPLL_BIT) +#define CPM_CPCCR_SEL_H0PLL_BIT 26 +#define CPM_CPCCR_SEL_H0PLL_MASK (0x3 << CPM_CPCCR_SEL_H0PLL_BIT) +#define CPM_CPCCR_SEL_H2PLL_BIT 24 +#define CPM_CPCCR_SEL_H2PLL_MASK (0x3 << CPM_CPCCR_SEL_H2PLL_BIT) +#define CPM_PLL_SEL_STOP 0 +#define CPM_PLL_SEL_SRC 1 +#define CPM_PLL_SEL_MPLL 2 +#define CPM_PLL_SEL_EPLL 3 +#define CPM_CPCCR_CE_CPU (0x1 << 22) +#define CPM_CPCCR_CE_AHB0 (0x1 << 21) +#define CPM_CPCCR_CE_AHB2 (0x1 << 20) +#define CPM_CPCCR_PDIV_BIT 16 +#define CPM_CPCCR_PDIV_MASK (0xf << CPM_CPCCR_PDIV_BIT) +#define CPM_CPCCR_H2DIV_BIT 12 +#define CPM_CPCCR_H2DIV_MASK (0xf << CPM_CPCCR_H2DIV_BIT) +#define CPM_CPCCR_H0DIV_BIT 8 +#define CPM_CPCCR_H0DIV_MASK (0x0f << CPM_CPCCR_H0DIV_BIT) +#define CPM_CPCCR_L2DIV_BIT 4 +#define CPM_CPCCR_L2DIV_MASK (0x0f << CPM_CPCCR_L2DIV_BIT) +#define CPM_CPCCR_CDIV_BIT 0 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) + +/* Clock Status register */ +#define CPM_CPCSR_H2DIV_BUSY BIT(2) +#define CPM_CPCSR_H0DIV_BUSY BIT(1) +#define CPM_CPCSR_CDIV_BUSY BIT(0) + +/* PLL control register */ +#define CPM_CPPCR_PLLST_BIT 0 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) + +/* XPLL control register */ +#define CPM_CPXPCR_XPLLM_BIT 19 +#define CPM_CPXPCR_XPLLM_MASK (0x1fff << CPM_CPXPCR_XPLLM_BIT) +#define CPM_CPXPCR_XPLLN_BIT 13 +#define CPM_CPXPCR_XPLLN_MASK (0x3f << CPM_CPXPCR_XPLLN_BIT) +#define CPM_CPXPCR_XPLLOD_BIT 9 +#define CPM_CPXPCR_XPLLOD_MASK (0xf << CPM_CPXPCR_XPLLOD_BIT) +#define CPM_CPXPCR_XLOCK BIT(6) +#define CPM_CPXPCR_XPLL_ON BIT(4) +#define CPM_CPXPCR_XF_MODE BIT(3) +#define CPM_CPXPCR_XPLLBP BIT(1) +#define CPM_CPXPCR_XPLLEN BIT(0) + +/* CPM scratch protected register */ +#define CPM_CPSPPR_BIT 0 +#define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT) + +/* USB parameter control register */ +#define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/ +#define CPM_USBPCR_AVLD_REG BIT(30) +#define CPM_USBPCR_IDPULLUP_MASK_BIT 28 +#define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT) +#define CPM_USBPCR_INCR_MASK BIT(27) +#define CPM_USBPCR_CLK12_EN BIT(26) +#define CPM_USBPCR_COMMONONN BIT(25) +#define CPM_USBPCR_VBUSVLDEXT BIT(24) +#define CPM_USBPCR_VBUSVLDEXTSEL BIT(23) +#define CPM_USBPCR_POR BIT(22) +#define CPM_USBPCR_SIDDQ BIT(21) +#define CPM_USBPCR_OTG_DISABLE BIT(20) +#define CPM_USBPCR_COMPDISTUNE_BIT 17 +#define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT) +#define CPM_USBPCR_OTGTUNE_BIT 14 +#define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT) +#define CPM_USBPCR_SQRXTUNE_BIT 11 +#define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT) +#define CPM_USBPCR_TXFSLSTUNE_BIT 7 +#define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT) +#define CPM_USBPCR_TXPREEMPHTUNE BIT(6) +#define CPM_USBPCR_TXRISETUNE_BIT 4 +#define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT) +#define CPM_USBPCR_TXVREFTUNE_BIT 0 +#define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT) + +/* DDR memory clock divider register */ +#define CPM_DDRCDR_DCS_BIT 30 +#define CPM_DDRCDR_DCS_MASK (0x3 << CPM_DDRCDR_DCS_BIT) +#define CPM_DDRCDR_DCS_STOP (0x0 << CPM_DDRCDR_DCS_BIT) +#define CPM_DDRCDR_DCS_SRC (0x1 << CPM_DDRCDR_DCS_BIT) +#define CPM_DDRCDR_DCS_MPLL (0x2 << CPM_DDRCDR_DCS_BIT) +#define CPM_DDRCDR_CE_DDR BIT(29) +#define CPM_DDRCDR_DDR_BUSY BIT(28) +#define CPM_DDRCDR_DDR_STOP BIT(27) +#define CPM_DDRCDR_DDRDIV_BIT 0 +#define CPM_DDRCDR_DDRDIV_MASK (0xf << CPM_DDRCDR_DDRDIV_BIT) + +/* USB reset detect timer register */ +#define CPM_USBRDT_VBFIL_LD_EN BIT(25) +#define CPM_USBRDT_IDDIG_EN BIT(24) +#define CPM_USBRDT_IDDIG_REG BIT(23) +#define CPM_USBRDT_USBRDT_BIT 0 +#define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT) + +/* USB OTG PHY clock divider register */ +#define CPM_USBCDR_UCS BIT(31) +#define CPM_USBCDR_UPCS BIT(30) +#define CPM_USBCDR_CEUSB BIT(29) +#define CPM_USBCDR_USB_BUSY BIT(28) +#define CPM_USBCDR_OTGDIV_BIT 0 +#define CPM_USBCDR_OTGDIV_MASK (0xff << CPM_USBCDR_OTGDIV_BIT) + +/* I2S device clock divider register */ +#define CPM_I2SCDR_I2CS BIT(31) +#define CPM_I2SCDR_I2PCS BIT(30) +#define CPM_I2SCDR_I2SDIV_BIT 0 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) + +/* LCD0 pix clock divider register */ +#define CPM_LPCDR_LPCS_BIT 30 +#define CPM_LPCDR_LPCS_MASK (0x3 << CPM_LPCDR_LPCS_BIT) +#define CPM_LPCDR_CELCD BIT(28) +#define CPM_LPCDR_LCD_BUSY BIT(27) +#define CPM_LPCDR_LCD_STOP BIT(26) +#define CPM_LPCDR_PIXDIV_BIT 0 +#define CPM_LPCDR_PIXDIV_MASK (0xff << CPM_LPCDR_PIXDIV_BIT) + +/* MSC clock divider register */ +#define CPM_MSCCDR_MPCS_BIT 30 +#define CPM_MSCCDR_MPCS_MASK (3 << CPM_MSCCDR_MPCS_BIT) +#define CPM_MSCCDR_MPCS_STOP (0x0 << CPM_MSCCDR_MPCS_BIT) +#define CPM_MSCCDR_MPCS_SRC (0x1 << CPM_MSCCDR_MPCS_BIT) +#define CPM_MSCCDR_MPCS_MPLL (0x2 << CPM_MSCCDR_MPCS_BIT) +#define CPM_MSCCDR_CE BIT(29) +#define CPM_MSCCDR_MSC_BUSY BIT(28) +#define CPM_MSCCDR_MSC_STOP BIT(27) +#define CPM_MSCCDR_MSC_CLK0_SEL BIT(15) +#define CPM_MSCCDR_MSCDIV_BIT 0 +#define CPM_MSCCDR_MSCDIV_MASK (0xff << CPM_MSCCDR_MSCDIV_BIT) + +/* UHC 48M clock divider register */ +#define CPM_UHCCDR_UHCS_BIT 30 +#define CPM_UHCCDR_UHCS_MASK (0x3 << CPM_UHCCDR_UHCS_BIT) +#define CPM_UHCCDR_UHCS_SRC (0x0 << CPM_UHCCDR_UHCS_BIT) +#define CPM_UHCCDR_UHCS_MPLL (0x1 << CPM_UHCCDR_UHCS_BIT) +#define CPM_UHCCDR_UHCS_EPLL (0x2 << CPM_UHCCDR_UHCS_BIT) +#define CPM_UHCCDR_UHCS_OTG (0x3 << CPM_UHCCDR_UHCS_BIT) +#define CPM_UHCCDR_CE_UHC BIT(29) +#define CPM_UHCCDR_UHC_BUSY BIT(28) +#define CPM_UHCCDR_UHC_STOP BIT(27) +#define CPM_UHCCDR_UHCDIV_BIT 0 +#define CPM_UHCCDR_UHCDIV_MASK (0xff << CPM_UHCCDR_UHCDIV_BIT) + +/* SSI clock divider register */ +#define CPM_SSICDR_SCS BIT(31) +#define CPM_SSICDR_SSIDIV_BIT 0 +#define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT) + +/* CIM MCLK clock divider register */ +#define CPM_CIMCDR_CIMDIV_BIT 0 +#define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT) + +/* GPS clock divider register */ +#define CPM_GPSCDR_GPCS BIT(31) +#define CPM_GPSCDR_GPSDIV_BIT 0 +#define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT) + +/* PCM device clock divider register */ +#define CPM_PCMCDR_PCMS BIT(31) +#define CPM_PCMCDR_PCMPCS BIT(30) +#define CPM_PCMCDR_PCMDIV_BIT 0 +#define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT) + +/* GPU clock divider register */ +#define CPM_GPUCDR_GPCS BIT(31) +#define CPM_GPUCDR_GPUDIV_BIT 0 +#define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT) + +/* HDMI clock divider register */ +#define CPM_HDMICDR_HPCS_BIT 30 +#define CPM_HDMICDR_HPCS_MASK (0x3 << CPM_HDMICDR_HPCS_BIT) +#define CPM_HDMICDR_CEHDMI BIT(29) +#define CPM_HDMICDR_HDMI_BUSY BIT(28) +#define CPM_HDMICDR_HDMI_STOP BIT(26) +#define CPM_HDMICDR_HDMIDIV_BIT 0 +#define CPM_HDMICDR_HDMIDIV_MASK (0xff << CPM_HDMICDR_HDMIDIV_BIT) + +/* Low Power Control Register */ +#define CPM_LCR_PD_SCPU BIT(31) +#define CPM_LCR_PD_VPU BIT(30) +#define CPM_LCR_PD_GPU BIT(29) +#define CPM_LCR_PD_GPS BIT(28) +#define CPM_LCR_SCPUS BIT(27) +#define CPM_LCR_VPUS BIT(26) +#define CPM_LCR_GPUS BIT(25) +#define CPM_LCR_GPSS BIT(24) +#define CPM_LCR_GPU_IDLE BIT(20) +#define CPM_LCR_PST_BIT 8 +#define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT) +#define CPM_LCR_DOZE_DUTY_BIT 3 +#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) +#define CPM_LCR_DOZE_ON BIT(2) +#define CPM_LCR_LPM_BIT 0 +#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) +#define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) +#define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) + +/* Clock Gate Register0 */ +#define CPM_CLKGR0_DDR1 BIT(31) +#define CPM_CLKGR0_DDR0 BIT(30) +#define CPM_CLKGR0_IPU BIT(29) +#define CPM_CLKGR0_LCD1 BIT(28) +#define CPM_CLKGR0_LCD BIT(27) +#define CPM_CLKGR0_CIM BIT(26) +#define CPM_CLKGR0_I2C2 BIT(25) +#define CPM_CLKGR0_UHC BIT(24) +#define CPM_CLKGR0_MAC BIT(23) +#define CPM_CLKGR0_GPS BIT(22) +#define CPM_CLKGR0_PDMAC BIT(21) +#define CPM_CLKGR0_SSI2 BIT(20) +#define CPM_CLKGR0_SSI1 BIT(19) +#define CPM_CLKGR0_UART3 BIT(18) +#define CPM_CLKGR0_UART2 BIT(17) +#define CPM_CLKGR0_UART1 BIT(16) +#define CPM_CLKGR0_UART0 BIT(15) +#define CPM_CLKGR0_SADC BIT(14) +#define CPM_CLKGR0_KBC BIT(13) +#define CPM_CLKGR0_MSC2 BIT(12) +#define CPM_CLKGR0_MSC1 BIT(11) +#define CPM_CLKGR0_OWI BIT(10) +#define CPM_CLKGR0_TSSI BIT(9) +#define CPM_CLKGR0_AIC BIT(8) +#define CPM_CLKGR0_SCC BIT(7) +#define CPM_CLKGR0_I2C1 BIT(6) +#define CPM_CLKGR0_I2C0 BIT(5) +#define CPM_CLKGR0_SSI0 BIT(4) +#define CPM_CLKGR0_MSC0 BIT(3) +#define CPM_CLKGR0_OTG BIT(2) +#define CPM_CLKGR0_BCH BIT(1) +#define CPM_CLKGR0_NEMC BIT(0) + +/* Clock Gate Register1 */ +#define CPM_CLKGR1_P1 BIT(15) +#define CPM_CLKGR1_X2D BIT(14) +#define CPM_CLKGR1_DES BIT(13) +#define CPM_CLKGR1_I2C4 BIT(12) +#define CPM_CLKGR1_AHB BIT(11) +#define CPM_CLKGR1_UART4 BIT(10) +#define CPM_CLKGR1_HDMI BIT(9) +#define CPM_CLKGR1_OTG1 BIT(8) +#define CPM_CLKGR1_GPVLC BIT(7) +#define CPM_CLKGR1_AIC1 BIT(6) +#define CPM_CLKGR1_COMPRES BIT(5) +#define CPM_CLKGR1_GPU BIT(4) +#define CPM_CLKGR1_PCM BIT(3) +#define CPM_CLKGR1_VPU BIT(2) +#define CPM_CLKGR1_TSSI1 BIT(1) +#define CPM_CLKGR1_I2C3 BIT(0) + +/* Oscillator and Power Control Register */ +#define CPM_OPCR_O1ST_BIT 8 +#define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT) +#define CPM_OPCR_SPENDN BIT(7) +#define CPM_OPCR_GPSEN BIT(6) +#define CPM_OPCR_SPENDH BIT(5) +#define CPM_OPCR_O1SE BIT(4) +#define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ +#define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ + +/* Reset Status Register */ +#define CPM_RSR_P0R BIT(2) +#define CPM_RSR_WR BIT(1) +#define CPM_RSR_PR BIT(0) + +/* BCH clock divider register */ +#define CPM_BCHCDR_BPCS_BIT 30 +#define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_CE_BCH BIT(29) +#define CPM_BCHCDR_BCH_BUSY BIT(28) +#define CPM_BCHCDR_BCH_STOP BIT(27) +#define CPM_BCHCDR_BCHCDR_BIT 0 +#define CPM_BCHCDR_BCHCDR_MASK (0x7 << CPM_BCHCDR_BCHCDR_BIT) + +/* CPM scratch pad protected register(CPSPPR) */ +#define CPSPPR_CPSPR_WRITABLE 0x00005a5a +#define RECOVERY_SIGNATURE 0x1a1a /* means "RECY" */ +#define RECOVERY_SIGNATURE_SEC 0x800 /* means "RECY" */ + +#define REBOOT_SIGNATURE 0x3535 /* means reboot */ + +/* XPLL control register */ +#define XLOCK (1 << 6) +#define XPLL_ON (1 << 4) +#define XF_MODE (1 << 3) +#define XPLLBP (1 << 1) +#define XPLLEN (1 << 0) + +enum PLLS { + EXTCLK = 0, + APLL, + MPLL, + EPLL, + VPLL, +}; + +#define M_N_OD(m, n, od) \ + ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9)) + +struct cgu_pll_select { + u8 reg; + u8 pll; + u8 pll_shift; +}; + +static void pll_init_one(int pll, int m, int n, int od) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4); + + setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN); + + /* FIXME */ + while (!(readl(pll_reg) & XPLL_ON)) + ; +} + +static void cpu_mux_select(int pll) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + u32 clk_ctrl; + unsigned int selectplls[] = { + CPM_PLL_SEL_STOP, + CPM_PLL_SEL_SRC, + CPM_PLL_SEL_MPLL, + CPM_PLL_SEL_EPLL + }; + + /* Init CPU, L2CACHE, AHB0, AHB2, APB clock */ + clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | + ((6 - 1) << CPM_CPCCR_H2DIV_BIT) | + ((3 - 1) << CPM_CPCCR_H0DIV_BIT) | + ((2 - 1) << CPM_CPCCR_L2DIV_BIT) | + ((1 - 1) << CPM_CPCCR_CDIV_BIT); + + if (CONFIG_SYS_MHZ >= 1000) + clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; + else + clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT; + + clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); + + while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY | + CPM_CPCSR_H0DIV_BUSY | CPM_CPCSR_H2DIV_BUSY)) + ; + + clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | + (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) | + (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT); + if (pll == APLL) + clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; + else + clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; + + clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); +} + +static void ddr_mux_select(int pll) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + int selectplls[] = { CPM_DDRCDR_DCS_STOP, + CPM_DDRCDR_DCS_SRC, + CPM_DDRCDR_DCS_MPLL}; + + writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), + cpm_regs + CPM_DDCDR); + + while (readl(cpm_regs + CPM_DDCDR) & CPM_DDRCDR_DDR_BUSY) + ; + + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0); + + mdelay(200); +} + +static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + unsigned int selectplls[] = {0, 1, 2, 3, 2, 6}; + int i; + + for (i = 0; i < num; i++) + writel(selectplls[cgu[i].pll] << cgu[i].pll_shift, + cpm_regs + cgu[i].reg); +} + +void pll_init(void) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + struct cgu_pll_select cgu_mux[] = { + { CPM_MSCCDR, MPLL, 30 }, + { CPM_LPCDR, VPLL, 30 }, + { CPM_LPCDR1, VPLL, 30 }, + { CPM_GPUCDR, MPLL, 30 }, + { CPM_HDMICDR, VPLL, 30 }, + { CPM_I2SCDR, EPLL, 30 }, + { CPM_BCHCDR, MPLL, 30 }, + { CPM_VPUCDR, 0x1, 30 }, + { CPM_UHCCDR, 0x3, 30 }, + { CPM_CIMCDR, 0x1, 31 }, + { CPM_PCMCDR, 0x5, 29 }, + { CPM_SSICDR, 0x3, 30 }, + }; + + /* PLL stable time set to default -- 1ms */ + clrsetbits_le32(cpm_regs + CPM_CPPCR, 0xfffff, (16 << 8) | 0x20); + + pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD); + pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD); + pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD); + pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD); + + cpu_mux_select(MPLL); + ddr_mux_select(MPLL); + cgu_mux_init(cgu_mux, ARRAY_SIZE(cgu_mux)); +} + +const u32 jz4780_clk_get_efuse_clk(void) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + u32 cpccr = readl(cpm_regs + CPM_CPCCR); + u32 ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >> + CPM_CPCCR_H2DIV_BIT) + 1; + return JZ4780_SYS_MEM_SPEED / ahb2_div; +} + +void jz4780_clk_ungate_ethernet(void) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC); + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC); +} + +void jz4780_clk_ungate_mmc(void) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + u32 msc_cdr = JZ4780_SYS_MEM_SPEED / 24000000 / 2 - 1; + + msc_cdr |= CPM_MSCCDR_MPCS_MPLL | CPM_MSCCDR_CE; + writel(msc_cdr, cpm_regs + CPM_MSCCDR); + writel(msc_cdr, cpm_regs + CPM_MSCCDR1); + writel(msc_cdr, cpm_regs + CPM_MSCCDR2); + + /* The wait_for_bit() won't fit, thus unbounded loop here. */ + while (readl(cpm_regs + CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY) + ; +} + +void jz4780_clk_ungate_uart(const unsigned int uart) +{ + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + + if (uart == 0) + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0); + else if (uart == 1) + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1); + else if (uart == 2) + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2); + else if (uart == 3) + clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3); + else if (uart == 4) + clrbits_le32(cpm_regs + CPM_CLKGR1, CPM_CLKGR1_UART4); + else + printf("%s[%i]: Invalid UART %d\n", __func__, __LINE__, uart); +} diff --git a/arch/mips/mach-jz47xx/jz4780/reset.c b/arch/mips/mach-jz47xx/jz4780/reset.c new file mode 100644 index 0000000000..73af34721f --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/reset.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 common routines + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include + +/* WDT */ +#define WDT_TDR 0x00 +#define WDT_TCER 0x04 +#define WDT_TCNT 0x08 +#define WDT_TCSR 0x0C + +/* Register definition */ +#define WDT_TCSR_PRESCALE_BIT 3 +#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) + #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_EXT_EN BIT(2) +#define WDT_TCSR_RTC_EN BIT(1) +#define WDT_TCSR_PCK_EN BIT(0) + +#define WDT_TCER_TCEN BIT(0) + +void _machine_restart(void) +{ + void __iomem *wdt_regs = (void __iomem *)WDT_BASE; + + /* EXTAL as the timer clock input. */ + writew(WDT_TCSR_PRESCALE1 | WDT_TCSR_EXT_EN, wdt_regs + WDT_TCSR); + + /* Reset the WDT counter and timeout. */ + writew(0, wdt_regs + WDT_TCNT); + writew(0, wdt_regs + WDT_TDR); + + jz4780_tcu_wdt_start(); + + /* WDT start */ + writeb(WDT_TCER_TCEN, wdt_regs + WDT_TCER); + + for (;;) + ; +} diff --git a/arch/mips/mach-jz47xx/jz4780/sdram.c b/arch/mips/mach-jz47xx/jz4780/sdram.c new file mode 100644 index 0000000000..5b25c8d002 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/sdram.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 DDR initialization + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + * + * Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot + * Copyright (c) 2006-2013 Ingenic Semiconductor + */ + +#include +#include +#include +#include + +static const u32 get_mem_clk(void) +{ + const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) / + (JZ4780_MPLL_N * JZ4780_MPLL_OD); + return mpll_out / JZ4780_SYS_MEM_DIV; +} + +u32 sdram_size(int cs) +{ + u32 dw = DDR_DW32 ? 4 : 2; + u32 banks = DDR_BANK8 ? 8 : 4; + u32 size = 0; + + if ((cs == 0) && DDR_CS0EN) { + size = (1 << (DDR_ROW + DDR_COL)) * dw * banks; + if (DDR_CS1EN && (size > 0x20000000)) + size = 0x20000000; + } else if ((cs == 1) && DDR_CS1EN) { + size = (1 << (DDR_ROW + DDR_COL)) * dw * banks; + } + + return size; +} + +static void ddr_cfg_init(void) +{ + void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; + u32 ddrc_cfg, tmp; + + tmp = DDR_CL; + if (tmp) + tmp--; + if (tmp > 4) + tmp = 4; + + ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA | + DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) | + ((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) | + (DDR_CS0EN << 6) | (DDR_BANK8 << 1) | + ((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) | + (DDR_CS1EN << 7) | (DDR_BANK8 << 23); + + if (DDR_BL > 4) + ddrc_cfg |= BIT(21); + + writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG); +} + +static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config) +{ + void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; + void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET; + unsigned int count = 0, i; + u32 reg, mask; + + writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR); + + writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0); + writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1); + writel(0, ddr_phy_regs + DDRP_ODTCR); + writel(0, ddr_phy_regs + DDRP_MR2); + + writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); + writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1); + writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2); + + writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0); + writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1); + writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2); + + writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) | + (2 << DDRP_PGCR_CKDV_BIT) | + (DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT | + DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX, + ddr_phy_regs + DDRP_PGCR); + + for (i = 0; i < 8; i++) + clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9); + + count = 0; + mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE; + for (;;) { + reg = readl(ddr_phy_regs + DDRP_PGSR); + if ((reg == mask) || (reg == 0x1f)) + break; + if (count++ == 10000) + hang(); + } + + /* DQS extension and early set to 1 */ + clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4); + + /* 500 pull up and 500 pull down */ + clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4); + + /* Initialise phy */ + writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST, + ddr_phy_regs + DDRP_PIR); + + count = 0; + mask |= DDRP_PGSR_DIDONE; + for (;;) { + reg = readl(ddr_phy_regs + DDRP_PGSR); + if ((reg == mask) || (reg == 0x1f)) + break; + if (count++ == 20000) + hang(); + } + + writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR); + + count = 0; + mask |= DDRP_PGSR_DTDONE; + for (;;) { + reg = readl(ddr_phy_regs + DDRP_PGSR); + if (reg == mask) + break; + if (count++ != 50000) + continue; + reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR; + if (reg) + hang(); + count = 0; + } + + /* Override impedance */ + clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff, + ((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) | + ((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) | + DDRP_ZQXCR_ZDEN); +} + +#define JZBIT(bit) ((bit % 4) * 8) +#define JZMASK(bit) (0x1f << JZBIT(bit)) + +static void remap_swap(int a, int b) +{ + void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; + u32 remmap[2], tmp[2]; + + remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4)); + remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4)); + + tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a); + tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b); + + remmap[0] &= ~JZMASK(a); + remmap[1] &= ~JZMASK(b); + + writel(remmap[0] | (tmp[1] << JZBIT(a)), + ddr_ctl_regs + DDRC_REMMAP(a / 4)); + writel(remmap[1] | (tmp[0] << JZBIT(b)), + ddr_ctl_regs + DDRC_REMMAP(b / 4)); +} + +static void mem_remap(void) +{ + u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12; + u32 num = DDR_BANK8 ? 3 : 2; + + if (DDR_CS0EN && DDR_CS1EN) + num++; + + for (; num > 0; num--) + remap_swap(0 + num - 1, start + num - 1); +} + +/* Fetch DRAM config from board file */ +__weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void) +{ + return NULL; +} + +void sdram_init(void) +{ + const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config(); + void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; + void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET; + void __iomem *cpm_regs = (void __iomem *)CPM_BASE; + u32 mem_clk, tmp, i; + u32 mem_base0, mem_base1; + u32 mem_mask0, mem_mask1; + u32 mem_size0, mem_size1; + + if (!ddr_config) + hang(); + + /* Reset DLL in DDR PHY */ + writel(0x3, cpm_regs + 0xd0); + mdelay(400); + writel(0x1, cpm_regs + 0xd0); + mdelay(400); + + /* Enter reset */ + writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL); + + mem_clk = get_mem_clk(); + + tmp = 1000000000 / mem_clk; + if (1000000000 % mem_clk) + tmp++; + tmp = DDR_tREFI / tmp; + tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1; + if (tmp > 0xff) + tmp = 0xff; + if (tmp < 1) + tmp = 1; + + writel(0x0, ddr_ctl_regs + DDRC_CTRL); + + writel(0x150000, ddr_phy_regs + DDRP_DTAR); + ddr_phy_init(ddr_config); + + writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); + writel(0x0, ddr_ctl_regs + DDRC_CTRL); + + ddr_cfg_init(); + + for (i = 0; i < 6; i++) + writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i)); + + mem_size0 = sdram_size(0); + mem_size1 = sdram_size(1); + + if (!mem_size1 && mem_size0 > 0x20000000) { + mem_base0 = 0x0; + mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK; + } else { + mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff; + mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK; + } + + if (mem_size1) { + mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK; + mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff; + } else { + mem_mask1 = 0; + mem_base1 = 0xff; + } + + writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0, + ddr_ctl_regs + DDRC_MMAP0); + writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1, + ddr_ctl_regs + DDRC_MMAP1); + writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); + writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN | + (tmp << DDRC_REFCNT_CON_BIT), + ddr_ctl_regs + DDRC_REFCNT); + writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) | + (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1), + ddr_ctl_regs + DDRC_CTRL); + mem_remap(); + clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40); +} diff --git a/arch/mips/mach-jz47xx/jz4780/timer.c b/arch/mips/mach-jz47xx/jz4780/timer.c new file mode 100644 index 0000000000..a689b9d71a --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/timer.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 timer + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include +#include +#include + +#define TCU_TSR 0x1C /* Timer Stop Register */ +#define TCU_TSSR 0x2C /* Timer Stop Set Register */ +#define TCU_TSCR 0x3C /* Timer Stop Clear Register */ +#define TCU_TER 0x10 /* Timer Counter Enable Register */ +#define TCU_TESR 0x14 /* Timer Counter Enable Set Register */ +#define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */ +#define TCU_TFR 0x20 /* Timer Flag Register */ +#define TCU_TFSR 0x24 /* Timer Flag Set Register */ +#define TCU_TFCR 0x28 /* Timer Flag Clear Register */ +#define TCU_TMR 0x30 /* Timer Mask Register */ +#define TCU_TMSR 0x34 /* Timer Mask Set Register */ +#define TCU_TMCR 0x38 /* Timer Mask Clear Register */ +/* n = 0,1,2,3,4,5 */ +#define TCU_TDFR(n) (0x40 + (n) * 0x10) /* Timer Data Full Reg */ +#define TCU_TDHR(n) (0x44 + (n) * 0x10) /* Timer Data Half Reg */ +#define TCU_TCNT(n) (0x48 + (n) * 0x10) /* Timer Counter Reg */ +#define TCU_TCSR(n) (0x4C + (n) * 0x10) /* Timer Control Reg */ + +#define TCU_OSTCNTL 0xe4 +#define TCU_OSTCNTH 0xe8 +#define TCU_OSTCSR 0xec +#define TCU_OSTCNTHBUF 0xfc + +/* Register definitions */ +#define TCU_TCSR_PWM_SD BIT(9) +#define TCU_TCSR_PWM_INITL_HIGH BIT(8) +#define TCU_TCSR_PWM_EN BIT(7) +#define TCU_TCSR_PRESCALE_BIT 3 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_EXT_EN BIT(2) +#define TCU_TCSR_RTC_EN BIT(1) +#define TCU_TCSR_PCK_EN BIT(0) + +#define TCU_TER_TCEN5 BIT(5) +#define TCU_TER_TCEN4 BIT(4) +#define TCU_TER_TCEN3 BIT(3) +#define TCU_TER_TCEN2 BIT(2) +#define TCU_TER_TCEN1 BIT(1) +#define TCU_TER_TCEN0 BIT(0) + +#define TCU_TESR_TCST5 BIT(5) +#define TCU_TESR_TCST4 BIT(4) +#define TCU_TESR_TCST3 BIT(3) +#define TCU_TESR_TCST2 BIT(2) +#define TCU_TESR_TCST1 BIT(1) +#define TCU_TESR_TCST0 BIT(0) + +#define TCU_TECR_TCCL5 BIT(5) +#define TCU_TECR_TCCL4 BIT(4) +#define TCU_TECR_TCCL3 BIT(3) +#define TCU_TECR_TCCL2 BIT(2) +#define TCU_TECR_TCCL1 BIT(1) +#define TCU_TECR_TCCL0 BIT(0) + +#define TCU_TFR_HFLAG5 BIT(21) +#define TCU_TFR_HFLAG4 BIT(20) +#define TCU_TFR_HFLAG3 BIT(19) +#define TCU_TFR_HFLAG2 BIT(18) +#define TCU_TFR_HFLAG1 BIT(17) +#define TCU_TFR_HFLAG0 BIT(16) +#define TCU_TFR_FFLAG5 BIT(5) +#define TCU_TFR_FFLAG4 BIT(4) +#define TCU_TFR_FFLAG3 BIT(3) +#define TCU_TFR_FFLAG2 BIT(2) +#define TCU_TFR_FFLAG1 BIT(1) +#define TCU_TFR_FFLAG0 BIT(0) + +#define TCU_TFSR_HFLAG5 BIT(21) +#define TCU_TFSR_HFLAG4 BIT(20) +#define TCU_TFSR_HFLAG3 BIT(19) +#define TCU_TFSR_HFLAG2 BIT(18) +#define TCU_TFSR_HFLAG1 BIT(17) +#define TCU_TFSR_HFLAG0 BIT(16) +#define TCU_TFSR_FFLAG5 BIT(5) +#define TCU_TFSR_FFLAG4 BIT(4) +#define TCU_TFSR_FFLAG3 BIT(3) +#define TCU_TFSR_FFLAG2 BIT(2) +#define TCU_TFSR_FFLAG1 BIT(1) +#define TCU_TFSR_FFLAG0 BIT(0) + +#define TCU_TFCR_HFLAG5 BIT(21) +#define TCU_TFCR_HFLAG4 BIT(20) +#define TCU_TFCR_HFLAG3 BIT(19) +#define TCU_TFCR_HFLAG2 BIT(18) +#define TCU_TFCR_HFLAG1 BIT(17) +#define TCU_TFCR_HFLAG0 BIT(16) +#define TCU_TFCR_FFLAG5 BIT(5) +#define TCU_TFCR_FFLAG4 BIT(4) +#define TCU_TFCR_FFLAG3 BIT(3) +#define TCU_TFCR_FFLAG2 BIT(2) +#define TCU_TFCR_FFLAG1 BIT(1) +#define TCU_TFCR_FFLAG0 BIT(0) + +#define TCU_TMR_HMASK5 BIT(21) +#define TCU_TMR_HMASK4 BIT(20) +#define TCU_TMR_HMASK3 BIT(19) +#define TCU_TMR_HMASK2 BIT(18) +#define TCU_TMR_HMASK1 BIT(17) +#define TCU_TMR_HMASK0 BIT(16) +#define TCU_TMR_FMASK5 BIT(5) +#define TCU_TMR_FMASK4 BIT(4) +#define TCU_TMR_FMASK3 BIT(3) +#define TCU_TMR_FMASK2 BIT(2) +#define TCU_TMR_FMASK1 BIT(1) +#define TCU_TMR_FMASK0 BIT(0) + +#define TCU_TMSR_HMST5 BIT(21) +#define TCU_TMSR_HMST4 BIT(20) +#define TCU_TMSR_HMST3 BIT(19) +#define TCU_TMSR_HMST2 BIT(18) +#define TCU_TMSR_HMST1 BIT(17) +#define TCU_TMSR_HMST0 BIT(16) +#define TCU_TMSR_FMST5 BIT(5) +#define TCU_TMSR_FMST4 BIT(4) +#define TCU_TMSR_FMST3 BIT(3) +#define TCU_TMSR_FMST2 BIT(2) +#define TCU_TMSR_FMST1 BIT(1) +#define TCU_TMSR_FMST0 BIT(0) + +#define TCU_TMCR_HMCL5 BIT(21) +#define TCU_TMCR_HMCL4 BIT(20) +#define TCU_TMCR_HMCL3 BIT(19) +#define TCU_TMCR_HMCL2 BIT(18) +#define TCU_TMCR_HMCL1 BIT(17) +#define TCU_TMCR_HMCL0 BIT(16) +#define TCU_TMCR_FMCL5 BIT(5) +#define TCU_TMCR_FMCL4 BIT(4) +#define TCU_TMCR_FMCL3 BIT(3) +#define TCU_TMCR_FMCL2 BIT(2) +#define TCU_TMCR_FMCL1 BIT(1) +#define TCU_TMCR_FMCL0 BIT(0) + +#define TCU_TSR_WDTS BIT(16) +#define TCU_TSR_STOP5 BIT(5) +#define TCU_TSR_STOP4 BIT(4) +#define TCU_TSR_STOP3 BIT(3) +#define TCU_TSR_STOP2 BIT(2) +#define TCU_TSR_STOP1 BIT(1) +#define TCU_TSR_STOP0 BIT(0) + +#define TCU_TSSR_WDTSS BIT(16) +#define TCU_TSSR_STPS5 BIT(5) +#define TCU_TSSR_STPS4 BIT(4) +#define TCU_TSSR_STPS3 BIT(3) +#define TCU_TSSR_STPS2 BIT(2) +#define TCU_TSSR_STPS1 BIT(1) +#define TCU_TSSR_STPS0 BIT(0) + +#define TCU_TSSR_WDTSC BIT(16) +#define TCU_TSSR_STPC5 BIT(5) +#define TCU_TSSR_STPC4 BIT(4) +#define TCU_TSSR_STPC3 BIT(3) +#define TCU_TSSR_STPC2 BIT(2) +#define TCU_TSSR_STPC1 BIT(1) +#define TCU_TSSR_STPC0 BIT(0) + +#define TER_OSTEN BIT(15) + +#define OSTCSR_CNT_MD BIT(15) +#define OSTCSR_SD BIT(9) +#define OSTCSR_PRESCALE_16 (0x2 << 3) +#define OSTCSR_EXT_EN BIT(2) + +int timer_init(void) +{ + void __iomem *regs = (void __iomem *)TCU_BASE; + + writel(OSTCSR_SD, regs + TCU_OSTCSR); + reset_timer(); + writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16, + regs + TCU_OSTCSR); + writew(TER_OSTEN, regs + TCU_TESR); + return 0; +} + +void reset_timer(void) +{ + void __iomem *regs = (void __iomem *)TCU_BASE; + + writel(0, regs + TCU_OSTCNTH); + writel(0, regs + TCU_OSTCNTL); +} + +static u64 get_timer64(void) +{ + void __iomem *regs = (void __iomem *)TCU_BASE; + u32 low = readl(regs + TCU_OSTCNTL); + u32 high = readl(regs + TCU_OSTCNTHBUF); + + return ((u64)high << 32) | low; +} + +ulong get_timer(ulong base) +{ + return lldiv(get_timer64(), 3000) - base; +} + +void __udelay(unsigned long usec) +{ + /* OST count increments at 3MHz */ + u64 end = get_timer64() + ((u64)usec * 3); + + while (get_timer64() < end) + ; +} + +unsigned long long get_ticks(void) +{ + return get_timer64(); +} + +void jz4780_tcu_wdt_start(void) +{ + void __iomem *tcu_regs = (void __iomem *)TCU_BASE; + + /* Enable WDT clock */ + writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR); +} diff --git a/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds b/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds new file mode 100644 index 0000000000..347cabc450 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + .text : + { + __image_copy_start = .; + arch/mips/mach-jz47xx/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.sbss.*) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } >.sdram + + /DISCARD/ : { + *(.dynbss) + *(.dynstr) + *(.dynamic) + *(.interp) + *(.hash) + *(.gnu.*) + *(.plt) + *(.got.plt) + *(.rel.plt) + *(.rel.dyn) + } +} diff --git a/arch/mips/mach-jz47xx/start.S b/arch/mips/mach-jz47xx/start.S new file mode 100644 index 0000000000..760d021549 --- /dev/null +++ b/arch/mips/mach-jz47xx/start.S @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Startup Code for MIPS32 XBURST CPU-core + * + * Copyright (c) 2010 Xiangfu Liu + */ + +#include +#include +#include +#include +#include +#include +#include + + .set noreorder + + .globl _start + .text +_start: +#ifdef CONFIG_SPL_BUILD + + /* magic value ("MSPL") */ + .word 0x4d53504c + + /* Invalidate BTB */ + mfc0 t0, CP0_CONFIG, 7 + nop + ori t0, 2 + mtc0 t0, CP0_CONFIG, 7 + nop + + /* + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 + */ + li t0, 0x0040FC04 + mtc0 t0, CP0_STATUS + + /* CAUSE register */ + /* IV=1, use the specical interrupt vector (0x200) */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + +#ifdef CONFIG_SOC_JZ4780 + /* enable bridge radical mode */ + la t0, CPM_BASE + lw t1, 0x24(t0) + ori t1, t1, 0x22 + sw t1, 0x24(t0) +#endif + + /* Set up stack */ + li sp, CONFIG_SPL_STACK + + b board_init_f + nop + +#ifdef CONFIG_SOC_JZ4780 + + .globl enable_caches + .ent enable_caches +enable_caches: + mtc0 zero, CP0_TAGLO + mtc0 zero, CP0_TAGHI + + li t0, KSEG0 + addu t1, t0, CONFIG_SYS_DCACHE_SIZE +1: + cache INDEX_STORE_TAG_D, 0(t0) + bne t0, t1, 1b + addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE + + li t0, KSEG0 + addu t1, t0, CONFIG_SYS_ICACHE_SIZE +2: + cache INDEX_STORE_TAG_I, 0(t0) + bne t0, t1, 2b + addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE + + /* Invalidate BTB */ + mfc0 t0, CP0_CONFIG, 7 + nop + ori t0, 2 + mtc0 t0, CP0_CONFIG, 7 + nop + + /* Enable caches */ + li t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + nop + + jr ra + nop + + .end enable_caches + +#endif /* CONFIG_SOC_JZ4780 */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 0000000000..0e35b77c9d --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select MIPS_TUNE_24KC + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs. + +config SOC_LUTON + bool + select SOC_VCOREIII + help + This supports MSCC Luton family of SOCs. + +config SYS_CONFIG_NAME + default "vcoreiii" + +choice + prompt "Board select" + +config TARGET_OCELOT_PCB120 + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb120 + +config TARGET_OCELOT_PCB123 + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb123 + +config TARGET_LUTON_PCB091 + bool "MSCC PCB091 Reference Board" + select SOC_LUTON + select MSCC_BITBANG_SPI_GPIO + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + luton_pcb091 +endchoice + +choice + prompt "DDR type" + +config DDRTYPE_H5TQ4G63MFR + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" + +config DDRTYPE_MT41K256M16 + bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)" + +config DDRTYPE_H5TQ1G63BFA + bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)" + +config DDRTYPE_MT41J128M16HA + bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)" + +config DDRTYPE_MT41K128M16JT + bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)" + +config DDRTYPE_MT47H128M8HQ + bool "Micron MT47H128M8-3 (1Gbit, DDR-533@CL4 @ 4.80ns 16Mbisx8x8)" + +endchoice + +source "board/mscc/ocelot/Kconfig" + +source "board/mscc/luton/Kconfig" + +endmenu diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile new file mode 100644 index 0000000000..6c60f26ca4 --- /dev/null +++ b/arch/mips/mach-mscc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +CFLAGS_cpu.o += -finline-limit=64000 + +obj-y += cpu.o dram.o reset.o lowlevel_init.o +obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c new file mode 100644 index 0000000000..5be8ff69d5 --- /dev/null +++ b/arch/mips/mach-mscc/cpu.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include + +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#define MSCC_RAM_TLB_SIZE SZ_64M +#define MSCC_ATTRIB2 MMU_REGIO_INVAL +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#define MSCC_RAM_TLB_SIZE SZ_64M +#define MSCC_ATTRIB2 MMU_REGIO_RW +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#define MSCC_RAM_TLB_SIZE SZ_256M +#define MSCC_ATTRIB2 MMU_REGIO_INVAL +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#define MSCC_RAM_TLB_SIZE SZ_256M +#define MSCC_ATTRIB2 MMU_REGIO_RW +#else +#define MSCC_RAM_TLB_SIZE SZ_512M +#define MSCC_ATTRIB2 MMU_REGIO_RW +#endif + +/* NOTE: lowlevel_init() function does not have access to the + * stack. Thus, all called functions must be inlined, and (any) local + * variables must be kept in registers. + */ +void vcoreiii_tlb_init(void) +{ + register int tlbix = 0; + + /* + * Unlike most of the MIPS based SoCs, the IO register address + * are not in KSEG0. The mainline linux kernel built in legacy + * mode needs to access some of the registers very early in + * the boot and make the assumption that the bootloader has + * already configured them, so we have to match this + * expectation. + */ + create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, + MMU_REGIO_RW); +#ifdef CONFIG_SOC_LUTON + create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, + MMU_REGIO_RW); +#endif + +#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO + /* + * If U-Boot is located in NOR then we want to be able to use + * the data cache in order to boot in a decent duration + */ + create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, + MMU_REGIO_RO_C); + create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, + MMU_REGIO_RO_C); + + /* + * Using cache for RAM also helps to improve boot time. Thanks + * to this the time to relocate U-Boot in RAM went from 2.092 + * secs to 0.104 secs. + */ + create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, + MSCC_ATTRIB2); + + /* Enable caches by clearing the bit ERL, which is set on reset */ + write_c0_status(read_c0_status() & ~BIT(2)); +#endif /* CONFIG_SYS_TEXT_BASE */ +} + +int mach_cpu_init(void) +{ + /* Speed up NOR flash access */ +#ifdef CONFIG_SOC_LUTON + writel(ICPU_PI_MST_CFG_TRISTATE_CTRL + + ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); + + writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + + ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); +#else + writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + + ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); + /* + * Legacy and mainline linux kernel expect that the + * interruption map was set as it was done by redboot. + */ + writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); + writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); + writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); + writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); +#endif + return 0; +} diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c new file mode 100644 index 0000000000..309007c14e --- /dev/null +++ b/arch/mips/mach-mscc/dram.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include + +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline int vcoreiii_train_bytelane(void) +{ + int ret; + + ret = hal_vcoreiii_train_bytelane(0); + +#ifdef CONFIG_SOC_OCELOT + if (ret) + return ret; + ret = hal_vcoreiii_train_bytelane(1); +#endif + + return ret; +} + +int vcoreiii_ddr_init(void) +{ + int res; + + if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) + & ICPU_MEMCTRL_STAT_INIT_DONE)) { + hal_vcoreiii_init_memctl(); + hal_vcoreiii_wait_memctl(); + if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane()) + hal_vcoreiii_ddr_failed(); + } +#if (CONFIG_SYS_TEXT_BASE != 0x20000000) + res = dram_check(); + if (res == 0) + hal_vcoreiii_ddr_verified(); + else + hal_vcoreiii_ddr_failed(); + + /* Clear boot-mode and read-back to activate/verify */ + clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_BOOT_MODE_ENA); + readl(BASE_CFG + ICPU_GENERAL_CTRL); +#else + res = 0; +#endif + return res; +} + +int print_cpuinfo(void) +{ + printf("MSCC VCore-III MIPS 24Kec\n"); + + return 0; +} + +int dram_init(void) +{ + while (vcoreiii_ddr_init()) + ; + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/mips/mach-mscc/include/ioremap.h b/arch/mips/mach-mscc/include/ioremap.h new file mode 100644 index 0000000000..9024364a57 --- /dev/null +++ b/arch/mips/mach-mscc/include/ioremap.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __ASM_MACH_MSCC_IOREMAP_H +#define __ASM_MACH_MSCC_IOREMAP_H + +#include +#include + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_vcoreiii_internal_registers(phys_addr_t offset) +{ + if ((offset >= MSCC_IO_ORIGIN1_OFFSET && + offset < (MSCC_IO_ORIGIN1_OFFSET + MSCC_IO_ORIGIN1_SIZE)) || + (offset >= MSCC_IO_ORIGIN2_OFFSET && + offset < (MSCC_IO_ORIGIN2_OFFSET + MSCC_IO_ORIGIN2_SIZE))) + return 1; + + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_vcoreiii_internal_registers(offset)) + return (void __iomem *)offset; + + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_vcoreiii_internal_registers((unsigned long)addr); +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_MSCC_IOREMAP_H */ diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h new file mode 100644 index 0000000000..931ecd7985 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __ASM_MACH_COMMON_H +#define __ASM_MACH_COMMON_H + +#if defined(CONFIG_SOC_OCELOT) +#include +#include +#include +#elif defined(CONFIG_SOC_LUTON) +#include +#include +#include +#else +#error Unsupported platform +#endif + +#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ +#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ +#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ +#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ + +#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ + +#endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h new file mode 100644 index 0000000000..f445e63a35 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -0,0 +1,814 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +#include +#include +#include +#include + +#define MIPS_VCOREIII_MEMORY_DDR3 +#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE + +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ + +/* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 13 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 2437 +#define VC3_MPAR_tRAS_min 12 +#define VC3_MPAR_CL 6 +#define VC3_MPAR_tWTR 4 +#define VC3_MPAR_tRC 16 +#define VC3_MPR_tFAW 16 +#define VC3_MPAR_tRP 5 +#define VC3_MPAR_tRRD 4 +#define VC3_MPAR_tRCD 5 +#define VC3_MPAR_tMRD 4 +#define VC3_MPAR_tRFC 35 +#define VC3_MPAR_CWL 5 +#define VC3_MPAR_tXPR 38 +#define VC3_MPAR_tMOD 12 +#define VC3_MPAR_tDLLK 512 +#define VC3_MPAR_tWR 5 + +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) /* Validation board */ + +/* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 14 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 2437 +#define VC3_MPAR_tRAS_min 12 +#define VC3_MPAR_CL 5 +#define VC3_MPAR_tWTR 4 +#define VC3_MPAR_tRC 16 +#define VC3_MPAR_tFAW 16 +#define VC3_MPAR_tRP 5 +#define VC3_MPAR_tRRD 4 +#define VC3_MPAR_tRCD 5 +#define VC3_MPAR_tMRD 4 +#define VC3_MPAR_tRFC 50 +#define VC3_MPAR_CWL 5 +#define VC3_MPAR_tXPR 54 +#define VC3_MPAR_tMOD 12 +#define VC3_MPAR_tDLLK 512 +#define VC3_MPAR_tWR 5 + +#elif defined(CONFIG_DDRTYPE_MT41K256M16) /* JR2 Validation board */ + +/* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 15 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 2437 +#define VC3_MPAR_tRAS_min 12 +#define VC3_MPAR_CL 5 +#define VC3_MPAR_tWTR 4 +#define VC3_MPAR_tRC 16 +#define VC3_MPAR_tFAW 16 +#define VC3_MPAR_tRP 5 +#define VC3_MPAR_tRRD 4 +#define VC3_MPAR_tRCD 5 +#define VC3_MPAR_tMRD 4 +#define VC3_MPAR_tRFC 82 +#define VC3_MPAR_CWL 5 +#define VC3_MPAR_tXPR 85 +#define VC3_MPAR_tMOD 12 +#define VC3_MPAR_tDLLK 512 +#define VC3_MPAR_tWR 5 + +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) /* JR2 Reference board */ + +/* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 15 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 2437 +#define VC3_MPAR_tRAS_min 12 +#define VC3_MPAR_CL 6 +#define VC3_MPAR_tWTR 4 +#define VC3_MPAR_tRC 17 +#define VC3_MPAR_tFAW 16 +#define VC3_MPAR_tRP 5 +#define VC3_MPAR_tRRD 4 +#define VC3_MPAR_tRCD 5 +#define VC3_MPAR_tMRD 4 +#define VC3_MPAR_tRFC 82 +#define VC3_MPAR_CWL 5 +#define VC3_MPAR_tXPR 85 +#define VC3_MPAR_tMOD 12 +#define VC3_MPAR_tDLLK 512 +#define VC3_MPAR_tWR 5 + +#elif defined(CONFIG_DDRTYPE_MT41K128M16JT) + +/* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 14 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 2437 +#define VC3_MPAR_tRAS_min 12 +#define VC3_MPAR_CL 6 +#define VC3_MPAR_tWTR 4 +#define VC3_MPAR_tRC 16 +#define VC3_MPAR_tFAW 16 +#define VC3_MPAR_tRP 5 +#define VC3_MPAR_tRRD 4 +#define VC3_MPAR_tRCD 5 +#define VC3_MPAR_tMRD 4 +#define VC3_MPAR_tRFC 82 +#define VC3_MPAR_CWL 5 +#define VC3_MPAR_tXPR 85 +#define VC3_MPAR_tMOD 12 +#define VC3_MPAR_tDLLK 512 +#define VC3_MPAR_tWR 5 + +#elif defined(CONFIG_DDRTYPE_MT47H128M8HQ) /* Luton10/26 Refboards */ + +/* Micron 1Gb MT47H128M8-3 16Meg x 8 x 8 banks, DDR-533@CL4 @ 4.80ns */ +#define VC3_MPAR_bank_addr_cnt 3 +#define VC3_MPAR_row_addr_cnt 14 +#define VC3_MPAR_col_addr_cnt 10 +#define VC3_MPAR_tREFI 1625 +#define VC3_MPAR_tRAS_min 9 +#define VC3_MPAR_CL 4 +#define VC3_MPAR_tWTR 2 +#define VC3_MPAR_tRC 12 +#define VC3_MPAR_tFAW 8 +#define VC3_MPAR_tRP 4 +#define VC3_MPAR_tRRD 2 +#define VC3_MPAR_tRCD 4 + +#define VC3_MPAR_tRPA 4 +#define VC3_MPAR_tRP 4 + +#define VC3_MPAR_tMRD 2 +#define VC3_MPAR_tRFC 27 + +#define VC3_MPAR__400_ns_dly 84 + +#define VC3_MPAR_tWR 4 +#undef MIPS_VCOREIII_MEMORY_DDR3 +#else + +#error Unknown DDR system configuration - please add! + +#endif + +#ifdef CONFIG_SOC_OCELOT +#define MIPS_VCOREIII_MEMORY_16BIT 1 +#endif + +#define MIPS_VCOREIII_MEMORY_SSTL_ODT 7 +#define MIPS_VCOREIII_MEMORY_SSTL_DRIVE 7 +#define VCOREIII_DDR_DQS_MODE_CALIBRATE + +#ifdef MIPS_VCOREIII_MEMORY_16BIT +#define VC3_MPAR_16BIT 1 +#else +#define VC3_MPAR_16BIT 0 +#endif + +#ifdef MIPS_VCOREIII_MEMORY_DDR3 +#define VC3_MPAR_DDR3_MODE 1 /* DDR3 */ +#define VC3_MPAR_BURST_LENGTH 8 /* Always 8 (1) for DDR3 */ +#ifdef MIPS_VCOREIII_MEMORY_16BIT +#define VC3_MPAR_BURST_SIZE 1 /* Always 1 for DDR3/16bit */ +#else +#define VC3_MPAR_BURST_SIZE 0 +#endif +#else +#define VC3_MPAR_DDR3_MODE 0 /* DDR2 */ +#ifdef MIPS_VCOREIII_MEMORY_16BIT +#define VC3_MPAR_BURST_LENGTH 4 /* in DDR2 16-bit mode, use burstlen 4 */ +#else +#define VC3_MPAR_BURST_LENGTH 8 /* For 8-bit IF we must run burst-8 */ +#endif +#define VC3_MPAR_BURST_SIZE 0 /* Always 0 for DDR2 */ +#endif + +#define VC3_MPAR_RL VC3_MPAR_CL +#if !defined(MIPS_VCOREIII_MEMORY_DDR3) +#define VC3_MPAR_WL (VC3_MPAR_RL - 1) +#define VC3_MPAR_MD VC3_MPAR_tMRD +#define VC3_MPAR_ID VC3_MPAR__400_ns_dly +#define VC3_MPAR_SD VC3_MPAR_tXSRD +#define VC3_MPAR_OW (VC3_MPAR_WL - 2) +#define VC3_MPAR_OR (VC3_MPAR_WL - 3) +#define VC3_MPAR_RP (VC3_MPAR_bank_addr_cnt < 3 ? VC3_MPAR_tRP : VC3_MPAR_tRPA) +#define VC3_MPAR_FAW (VC3_MPAR_bank_addr_cnt < 3 ? 1 : VC3_MPAR_tFAW) +#define VC3_MPAR_BL (VC3_MPAR_BURST_LENGTH == 4 ? 2 : 4) +#define MSCC_MEMPARM_MR0 \ + (VC3_MPAR_BURST_LENGTH == 8 ? 3 : 2) | (VC3_MPAR_CL << 4) | \ + ((VC3_MPAR_tWR - 1) << 9) +/* DLL-on, Full-OD, AL=0, RTT=off, nDQS-on, RDQS-off, out-en */ +#define MSCC_MEMPARM_MR1 0x382 +#define MSCC_MEMPARM_MR2 0 +#define MSCC_MEMPARM_MR3 0 +#else +#define VC3_MPAR_WL VC3_MPAR_CWL +#define VC3_MPAR_MD VC3_MPAR_tMOD +#define VC3_MPAR_ID VC3_MPAR_tXPR +#define VC3_MPAR_SD VC3_MPAR_tDLLK +#define VC3_MPAR_OW 2 +#define VC3_MPAR_OR 2 +#define VC3_MPAR_RP VC3_MPAR_tRP +#define VC3_MPAR_FAW VC3_MPAR_tFAW +#define VC3_MPAR_BL 4 +#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9) +/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */ +#define MSCC_MEMPARM_MR1 0x0040 +#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3) +#define MSCC_MEMPARM_MR3 0 +#endif /* MIPS_VCOREIII_MEMORY_DDR3 */ + +#define MSCC_MEMPARM_MEMCFG \ + ((MIPS_VCOREIII_DDR_SIZE > SZ_512M) ? \ + ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS : 0) | \ + (VC3_MPAR_16BIT ? ICPU_MEMCTRL_CFG_DDR_WIDTH : 0) | \ + (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \ + (VC3_MPAR_BURST_SIZE ? ICPU_MEMCTRL_CFG_BURST_SIZE : 0) | \ + (VC3_MPAR_BURST_LENGTH == 8 ? ICPU_MEMCTRL_CFG_BURST_LEN : 0) | \ + (VC3_MPAR_bank_addr_cnt == 3 ? ICPU_MEMCTRL_CFG_BANK_CNT : 0) | \ + ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) | \ + ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1) + +#ifdef CONFIG_SOC_OCELOT +#define MSCC_MEMPARM_PERIOD \ + ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) | \ + ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI) + +#define MSCC_MEMPARM_TIMING0 \ + ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \ + VC3_MPAR_WL) | \ + ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(VC3_MPAR_BL - 1) | \ + ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(VC3_MPAR_BL) | \ + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \ + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_WL + \ + VC3_MPAR_BL + \ + VC3_MPAR_tWR - 1) | \ + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BL - 1) | \ + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_WL - 1) | \ + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3) + +#define MSCC_MEMPARM_TIMING1 \ + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \ + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_FAW - 1) | \ + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_RP - 1) | \ + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \ + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \ + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_WL + \ + VC3_MPAR_BL + \ + VC3_MPAR_tWTR - 1) + +#define MSCC_MEMPARM_TIMING2 \ + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_RP - 1) | \ + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_MD - 1) | \ + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \ + ICPU_MEMCTRL_TIMING2_INIT_DLY(VC3_MPAR_ID - 1) + +#define MSCC_MEMPARM_TIMING3 \ + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_WL + \ + VC3_MPAR_tWTR - 1) |\ + ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(VC3_MPAR_OR - 1) | \ + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_OW - 1) | \ + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3) + +#else +#define MSCC_MEMPARM_PERIOD \ + ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(1) | \ + ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI) + +#define MSCC_MEMPARM_TIMING0 \ + ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(VC3_MPAR_tRAS_min - 1) | \ + ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \ + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \ + VC3_MPAR_tWR) | \ + ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(VC3_MPAR_BURST_LENGTH == 8 ? 3 : 1) | \ + ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(VC3_MPAR_CL - 3) | \ + ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3) + +#define MSCC_MEMPARM_TIMING1 \ + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(VC3_MPAR_tRC - 1) | \ + ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(VC3_MPAR_tFAW - 1) | \ + ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(VC3_MPAR_tRP - 1) | \ + ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \ + ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(VC3_MPAR_tRCD - 1) | \ + ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \ + (VC3_MPAR_BURST_LENGTH == 8 ? 2 : 0) + \ + VC3_MPAR_tWTR) +#define MSCC_MEMPARM_TIMING2 \ + ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(VC3_MPAR_tRPA - 1) | \ + ICPU_MEMCTRL_TIMING2_MDSET_DLY(VC3_MPAR_tMRD - 1) | \ + ICPU_MEMCTRL_TIMING2_REF_DLY(VC3_MPAR_tRFC - 1) | \ + ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(VC3_MPAR__400_ns_dly) + +#define MSCC_MEMPARM_TIMING3 \ + ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(VC3_MPAR_CL - 1) | \ + ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(VC3_MPAR_CL - 1) | \ + ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_CL - 1) + +#endif + +enum { + DDR_TRAIN_OK, + DDR_TRAIN_CONTINUE, + DDR_TRAIN_ERROR, +}; + +/* + * We actually have very few 'pause' possibilities apart from + * these assembly nops (at this very early stage). + */ +#define PAUSE() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop") + +/* NB: Assumes inlining as no stack is available! */ +static inline void set_dly(u32 bytelane, u32 dly) +{ + register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); + + r &= ~ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M; + r |= ICPU_MEMCTRL_DQS_DLY_DQS_DLY(dly); + writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); +} + +static inline bool incr_dly(u32 bytelane) +{ + register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); + + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) { + writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); + return true; + } + + return false; +} + +static inline bool adjust_dly(int adjust) +{ + register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); + + if (ICPU_MEMCTRL_DQS_DLY_DQS_DLY(r) < 31) { + writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); + return true; + } + + return false; +} + +/* NB: Assumes inlining as no stack is available! */ +static inline void center_dly(u32 bytelane, u32 start) +{ + register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start; + + writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); +} + +static inline void memphy_soft_reset(void) +{ + setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST); + PAUSE(); + clrbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST); + PAUSE(); +} + +#ifdef CONFIG_SOC_OCELOT +static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd }; + +static inline void sleep_100ns(u32 val) +{ + /* Set the timer tick generator to 100 ns */ + writel(VCOREIII_TIMER_DIVIDER - 1, BASE_CFG + ICPU_TIMER_TICK_DIV); + + /* Set the timer value */ + writel(val, BASE_CFG + ICPU_TIMER_VALUE(0)); + + /* Enable timer 0 for one-shot */ + writel(ICPU_TIMER_CTRL_ONE_SHOT_ENA | ICPU_TIMER_CTRL_TIMER_ENA, + BASE_CFG + ICPU_TIMER_CTRL(0)); + + /* Wait for timer 0 to reach 0 */ + while (readl(BASE_CFG + ICPU_TIMER_VALUE(0)) != 0) + ; +} + +static inline void hal_vcoreiii_ddr_reset_assert(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); + sleep_100ns(10000); +} + +static inline void hal_vcoreiii_ddr_reset_release(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); + sleep_100ns(10000); +} + +/* + * DDR memory sanity checking failed, tally and do hard reset + * + * NB: Assumes inlining as no stack is available! + */ +static inline void hal_vcoreiii_ddr_failed(void) +{ + register u32 reset; + + writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); + + clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + + /* We have to execute the reset function from cache. Indeed, + * the reboot workaround in _machine_restart() will change the + * SPI NOR into SW bitbang. + * + * This will render the CPU unable to execute directly from + * the NOR, which is why the reset instructions are prefetched + * into the I-cache. + * + * When failing the DDR initialization we are executing from + * NOR. + * + * The last instruction in _machine_restart() will reset the + * MIPS CPU (and the cache), and the CPU will start executing + * from the reset vector. + */ + reset = KSEG0ADDR(_machine_restart); + icache_lock((void *)reset, 128); + asm volatile ("jr %0"::"r" (reset)); + + panic("DDR init failed\n"); +} + +/* + * DDR memory sanity checking done, possibly enable ECC. + * + * NB: Assumes inlining as no stack is available! + */ +static inline void hal_vcoreiii_ddr_verified(void) +{ +#ifdef MIPS_VCOREIII_MEMORY_ECC + /* Finally, enable ECC */ + register u32 val = readl(BASE_CFG + ICPU_MEMCTRL_CFG); + + val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA; + val &= ~ICPU_MEMCTRL_CFG_BURST_SIZE; + + writel(val, BASE_CFG + ICPU_MEMCTRL_CFG); +#endif + + /* Reset Status register - sticky bits */ + writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT); +} + +/* NB: Assumes inlining as no stack is available! */ +static inline int look_for(u32 bytelane) +{ + register u32 i; + + /* Reset FIFO in case any previous access failed */ + for (i = 0; i < sizeof(training_data); i++) { + register u32 byte; + + memphy_soft_reset(); + /* Reset sticky bits */ + writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), + BASE_CFG + ICPU_MEMCTRL_STAT); + /* Read data */ + byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane + + (i * 4)); + + /* + * Prevent the compiler reordering the instruction so + * the read of RAM happens after the check of the + * errors. + */ + rmb(); + if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) & + (ICPU_MEMCTRL_STAT_RDATA_MASKED | + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) { + /* Noise on the line */ + goto read_error; + } + /* If mismatch, increment DQS - if possible */ + if (byte != training_data[i]) { + read_error: + if (!incr_dly(bytelane)) + return DDR_TRAIN_ERROR; + return DDR_TRAIN_CONTINUE; + } + } + return DDR_TRAIN_OK; +} + +/* NB: Assumes inlining as no stack is available! */ +static inline int look_past(u32 bytelane) +{ + register u32 i; + + /* Reset FIFO in case any previous access failed */ + for (i = 0; i < sizeof(training_data); i++) { + register u32 byte; + + memphy_soft_reset(); + /* Ack sticky bits */ + writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), + BASE_CFG + ICPU_MEMCTRL_STAT); + byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane + + (i * 4)); + /* + * Prevent the compiler reordering the instruction so + * the read of RAM happens after the check of the + * errors. + */ + rmb(); + if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) & + (ICPU_MEMCTRL_STAT_RDATA_MASKED | + ICPU_MEMCTRL_STAT_RDATA_DUMMY)) { + /* Noise on the line */ + goto read_error; + } + /* Bail out when we see first mismatch */ + if (byte != training_data[i]) { + read_error: + return DDR_TRAIN_OK; + } + } + /* All data compares OK, increase DQS and retry */ + if (!incr_dly(bytelane)) + return DDR_TRAIN_ERROR; + + return DDR_TRAIN_CONTINUE; +} + +static inline int hal_vcoreiii_train_bytelane(u32 bytelane) +{ + register int res; + register u32 dqs_s; + + set_dly(bytelane, 0); /* Start training at DQS=0 */ + while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE) + ; + if (res != DDR_TRAIN_OK) + return res; + + dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); + while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE) + ; + if (res != DDR_TRAIN_OK) + return res; + /* Reset FIFO - for good measure */ + memphy_soft_reset(); + /* Adjust to center [dqs_s;cur] */ + center_dly(bytelane, dqs_s); + return DDR_TRAIN_OK; +} + +/* This algorithm is converted from the TCL training algorithm used + * during silicon simulation. + * NB: Assumes inlining as no stack is available! + */ +static inline int hal_vcoreiii_init_dqs(void) +{ +#define MAX_DQS 32 + register u32 i, j; + + for (i = 0; i < MAX_DQS; i++) { + set_dly(0, i); /* Byte-lane 0 */ + for (j = 0; j < MAX_DQS; j++) { + __maybe_unused register u32 byte; + + set_dly(1, j); /* Byte-lane 1 */ + /* Reset FIFO in case any previous access failed */ + memphy_soft_reset(); + writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), + BASE_CFG + ICPU_MEMCTRL_STAT); + byte = __raw_readb((void __iomem *)MSCC_DDR_TO); + byte = __raw_readb((void __iomem *)(MSCC_DDR_TO + 1)); + if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & + (ICPU_MEMCTRL_STAT_RDATA_MASKED | + ICPU_MEMCTRL_STAT_RDATA_DUMMY))) + return 0; + } + } + return -1; +} + +static inline int dram_check(void) +{ + register u32 i; + + for (i = 0; i < 8; i++) { + __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); + if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i) + return 1; + } + return 0; +} +#else /* Luton */ + +static inline void sleep_100ns(u32 val) +{ +} + +static inline void hal_vcoreiii_ddr_reset_assert(void) +{ + setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST); + setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); +} + +static inline void hal_vcoreiii_ddr_reset_release(void) +{ +} + +static inline void hal_vcoreiii_ddr_failed(void) +{ + register u32 memphy_cfg = readl(BASE_CFG + ICPU_MEMPHY_CFG); + + /* Do a fifo reset and start over */ + writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST, + BASE_CFG + ICPU_MEMPHY_CFG); + writel(memphy_cfg & ~ICPU_MEMPHY_CFG_PHY_FIFO_RST, + BASE_CFG + ICPU_MEMPHY_CFG); + writel(memphy_cfg | ICPU_MEMPHY_CFG_PHY_FIFO_RST, + BASE_CFG + ICPU_MEMPHY_CFG); +} + +static inline void hal_vcoreiii_ddr_verified(void) +{ +} + +static inline int look_for(u32 data) +{ + register u32 byte = __raw_readb((void __iomem *)MSCC_DDR_TO); + + if (data != byte) { + if (!incr_dly(0)) + return DDR_TRAIN_ERROR; + return DDR_TRAIN_CONTINUE; + } + + return DDR_TRAIN_OK; +} + +/* This algorithm is converted from the TCL training algorithm used + * during silicon simulation. + * NB: Assumes inlining as no stack is available! + */ +static inline int hal_vcoreiii_train_bytelane(u32 bytelane) +{ + register int res; + + set_dly(bytelane, 0); /* Start training at DQS=0 */ + while ((res = look_for(0xff)) == DDR_TRAIN_CONTINUE) + ; + if (res != DDR_TRAIN_OK) + return res; + + set_dly(bytelane, 0); /* Start training at DQS=0 */ + while ((res = look_for(0x00)) == DDR_TRAIN_CONTINUE) + + ; + + if (res != DDR_TRAIN_OK) + return res; + + adjust_dly(-3); + + return DDR_TRAIN_OK; +} + +static inline int hal_vcoreiii_init_dqs(void) +{ + return 0; +} + +static inline int dram_check(void) +{ + register u32 i; + + for (i = 0; i < 8; i++) { + __raw_writel(~i, (void __iomem *)(MSCC_DDR_TO + (i * 4))); + + if (__raw_readl((void __iomem *)(MSCC_DDR_TO + (i * 4))) != ~i) + return 1; + } + + return 0; +} +#endif + +/* + * NB: Called *early* to init memory controller - assumes inlining as + * no stack is available! + */ +static inline void hal_vcoreiii_init_memctl(void) +{ + /* Ensure DDR is in reset */ + hal_vcoreiii_ddr_reset_assert(); + + /* Wait maybe not needed, but ... */ + PAUSE(); + + /* Drop sys ctl memory controller forced reset */ + clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); + + PAUSE(); + + /* Drop Reset, enable SSTL */ + writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, BASE_CFG + ICPU_MEMPHY_CFG); + PAUSE(); + + /* Start the automatic SSTL output and ODT drive-strength calibration */ + writel(ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(MIPS_VCOREIII_MEMORY_SSTL_ODT) | + /* drive strength */ + ICPU_MEMPHY_ZCAL_ZCAL_PROG(MIPS_VCOREIII_MEMORY_SSTL_DRIVE) | + /* Start calibration process */ + ICPU_MEMPHY_ZCAL_ZCAL_ENA, BASE_CFG + ICPU_MEMPHY_ZCAL); + + /* Wait for ZCAL to clear */ + while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA) + ; +#ifdef CONFIG_SOC_OCELOT + /* Check no ZCAL_ERR */ + if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT) + & ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR) + hal_vcoreiii_ddr_failed(); +#endif + /* Drive CL, CK, ODT */ + setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_ODT_OE | + ICPU_MEMPHY_CFG_PHY_CK_OE | ICPU_MEMPHY_CFG_PHY_CL_OE); + + /* Initialize memory controller */ + writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG); + writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD); + +#ifdef CONFIG_SOC_OCELOT + writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0); +#else /* Luton */ + clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1)); + setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0); +#endif + + writel(MSCC_MEMPARM_TIMING1, BASE_CFG + ICPU_MEMCTRL_TIMING1); + writel(MSCC_MEMPARM_TIMING2, BASE_CFG + ICPU_MEMCTRL_TIMING2); + writel(MSCC_MEMPARM_TIMING3, BASE_CFG + ICPU_MEMCTRL_TIMING3); + writel(MSCC_MEMPARM_MR0, BASE_CFG + ICPU_MEMCTRL_MR0_VAL); + writel(MSCC_MEMPARM_MR1, BASE_CFG + ICPU_MEMCTRL_MR1_VAL); + writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL); + writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL); + +#ifdef CONFIG_SOC_OCELOT + /* Termination setup - enable ODT */ + writel(ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA | + /* Assert ODT0 for any write */ + ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(3), + BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL); + + /* Release Reset from DDR */ + hal_vcoreiii_ddr_reset_release(); + + writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7)); +#else /* Luton */ + /* Termination setup - disable ODT */ + writel(0, BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL); + +#endif +} + +static inline void hal_vcoreiii_wait_memctl(void) +{ + /* Now, rip it! */ + writel(ICPU_MEMCTRL_CTRL_INITIALIZE, BASE_CFG + ICPU_MEMCTRL_CTRL); + + while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) + & ICPU_MEMCTRL_STAT_INIT_DONE)) + ; + + /* Settle...? */ + sleep_100ns(10000); +#ifdef CONFIG_SOC_OCELOT + /* Establish data contents in DDR RAM for training */ + + __raw_writel(0xcacafefe, ((void __iomem *)MSCC_DDR_TO)); + __raw_writel(0x22221111, ((void __iomem *)MSCC_DDR_TO + 0x4)); + __raw_writel(0x44443333, ((void __iomem *)MSCC_DDR_TO + 0x8)); + __raw_writel(0x66665555, ((void __iomem *)MSCC_DDR_TO + 0xC)); + __raw_writel(0x88887777, ((void __iomem *)MSCC_DDR_TO + 0x10)); + __raw_writel(0xaaaa9999, ((void __iomem *)MSCC_DDR_TO + 0x14)); + __raw_writel(0xccccbbbb, ((void __iomem *)MSCC_DDR_TO + 0x18)); + __raw_writel(0xeeeedddd, ((void __iomem *)MSCC_DDR_TO + 0x1C)); +#else + __raw_writel(0xff, ((void __iomem *)MSCC_DDR_TO)); +#endif +} +#endif /* __ASM_MACH_DDR_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h new file mode 100644 index 0000000000..19f02ede66 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_H_ +#define _MSCC_OCELOT_H_ + +#include +#include + +/* + * Target offset base(s) + */ +#define MSCC_IO_ORIGIN1_OFFSET 0x60000000 +#define MSCC_IO_ORIGIN1_SIZE 0x01000000 +#define MSCC_IO_ORIGIN2_OFFSET 0x70000000 +#define MSCC_IO_ORIGIN2_SIZE 0x00200000 +#define BASE_CFG ((void __iomem *)0x70000000) +#define BASE_DEVCPU_GCB ((void __iomem *)0x60070000) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h new file mode 100644 index 0000000000..8c0b612325 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_H_ + +#define PERF_SOFT_RST 0x90 + +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h new file mode 100644 index 0000000000..9233f037bb --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_ICPU_CFG_H_ +#define _MSCC_OCELOT_ICPU_CFG_H_ + +#define ICPU_GPR(x) (0x4 * (x)) +#define ICPU_GPR_RSZ 0x4 + +#define ICPU_RESET 0x20 + +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) +#define ICPU_RESET_CORE_RST_PROTECT BIT(2) +#define ICPU_RESET_CORE_RST_FORCE BIT(1) +#define ICPU_RESET_MEM_RST_FORCE BIT(0) + +#define ICPU_GENERAL_CTRL 0x24 + +#define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6) +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5) +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4) +#define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3) +#define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2) +#define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1) + +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) + +#define ICPU_PI_MST_CFG 0x2c + +#define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7) +#define ICPU_PI_MST_CFG_CLK_POL BIT(6) +#define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5) +#define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) +#define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0) + +#define ICPU_SPI_MST_CFG 0x50 + +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) + +#define ICPU_SW_MODE 0x64 + +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12) +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10) +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0) + +#define ICPU_INTR_ENA 0x88 + +#define ICPU_INTR_IRQ0_ENA 0x98 +#define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0) + +#define ICPU_MEMCTRL_CTRL 0x234 + +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2) +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) + +#define ICPU_MEMCTRL_CFG 0x238 + +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_STAT 0x23C + +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) + +#define ICPU_MEMCTRL_REF_PERIOD 0x240 + +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) + +#define ICPU_MEMCTRL_TIMING0 0x248 + +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_TIMING1 0x24c + +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_TIMING2 0x250 + +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0)) +#define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0) + +#define ICPU_MEMCTRL_TIMING3 0x254 + +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_MR0_VAL 0x258 + +#define ICPU_MEMCTRL_MR1_VAL 0x25c + +#define ICPU_MEMCTRL_MR2_VAL 0x260 + +#define ICPU_MEMCTRL_MR3_VAL 0x264 + +#define ICPU_MEMCTRL_TERMRES_CTRL 0x268 + +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) + +#define ICPU_MEMCTRL_DQS_DLY(x) (0x270) + +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) + +#define ICPU_MEMPHY_CFG 0x278 + +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0) +#define ICPU_MEMPHY_DQ_DLY_TRM 0x180 +#define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 + +#define ICPU_MEMPHY_ZCAL 0x294 + +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h new file mode 100644 index 0000000000..2cb2135d37 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Microsemi Ocelot Switch driver + * + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_H_ +#define _MSCC_OCELOT_H_ + +#include +#include + +/* + * Target offset base(s) + */ +#define MSCC_IO_ORIGIN1_OFFSET 0x70000000 +#define MSCC_IO_ORIGIN1_SIZE 0x00200000 +#define MSCC_IO_ORIGIN2_OFFSET 0x71000000 +#define MSCC_IO_ORIGIN2_SIZE 0x01000000 +#define BASE_CFG ((void __iomem *)0x70000000) +#define BASE_DEVCPU_GCB ((void __iomem *)0x71070000) + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h new file mode 100644 index 0000000000..f8aa97ba26 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ +#define _MSCC_OCELOT_DEVCPU_GCB_H_ + +#define PERF_SOFT_RST 0x8 + +#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2) +#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) +#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0) + +#define PERF_GPIO_OUT_SET 0x34 + +#define PERF_GPIO_OUT_CLR 0x38 + +#define PERF_GPIO_OE 0x44 + +#endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h new file mode 100644 index 0000000000..04cf70bec3 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _MSCC_OCELOT_ICPU_CFG_H_ +#define _MSCC_OCELOT_ICPU_CFG_H_ + +#define ICPU_GPR(x) (0x4 * (x)) +#define ICPU_GPR_RSZ 0x4 + +#define ICPU_RESET 0x20 + +#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) +#define ICPU_RESET_CORE_RST_PROTECT BIT(2) +#define ICPU_RESET_CORE_RST_FORCE BIT(1) +#define ICPU_RESET_MEM_RST_FORCE BIT(0) + +#define ICPU_GENERAL_CTRL 0x24 + +#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14) +#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13) +#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12) +#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11) +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10) +#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(9) +#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(8) +#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(7) +#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(6) +#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4) +#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) +#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3) +#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2) +#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1) +#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) +#define ICPU_SPI_MST_CFG 0x3c + +#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11) +#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) +#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) +#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) +#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) + +#define ICPU_SW_MODE 0x50 + +#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) +#define ICPU_SW_MODE_SW_SPI_SCK BIT(12) +#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) +#define ICPU_SW_MODE_SW_SPI_SDO BIT(10) +#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) +#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) +#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) +#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) +#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) +#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) +#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) +#define ICPU_SW_MODE_SW_SPI_SDI BIT(0) + +#define ICPU_INTR_ENA 0x88 + +#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x)) +#define ICPU_DST_INTR_MAP_RSZ 0x4 + +#define ICPU_DST_INTR_IDENT 0xa8 +#define ICPU_DST_INTR_IDENT_RSZ 0x4 + +#define ICPU_TIMER_TICK_DIV 0xe8 +#define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) + +#define ICPU_TIMER_CTRL(x) (0x104 + 0x4 * (x)) +#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3) +#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2) +#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1) +#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0) + +#define ICPU_MEMCTRL_CTRL 0x110 +#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) +#define ICPU_MEMCTRL_CTRL_MDSET BIT(2) +#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) +#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) + +#define ICPU_MEMCTRL_CFG 0x114 + +#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) +#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) +#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) +#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) +#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) +#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) +#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) +#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) +#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) +#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_STAT 0x118 + +#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) +#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) +#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) +#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) +#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) +#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) + +#define ICPU_MEMCTRL_REF_PERIOD 0x11c + +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) +#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) +#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) + +#define ICPU_MEMCTRL_TIMING0 0x124 + +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) +#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) +#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) +#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) +#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_TIMING1 0x128 + +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) +#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_TIMING2 0x12c + +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) +#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) +#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) +#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) +#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) +#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0)) +#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0) + +#define ICPU_MEMCTRL_TIMING3 0x130 + +#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) +#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) +#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) +#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) +#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) +#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) + +#define ICPU_MEMCTRL_MR0_VAL 0x138 + +#define ICPU_MEMCTRL_MR1_VAL 0x13c + +#define ICPU_MEMCTRL_MR2_VAL 0x140 + +#define ICPU_MEMCTRL_MR3_VAL 0x144 + +#define ICPU_MEMCTRL_TERMRES_CTRL 0x148 + +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) +#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) +#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) + +#define ICPU_MEMCTRL_DQS_DLY(x) (0x150 + 0x4 * (x)) +#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4 + +#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) +#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) + +#define ICPU_MEMPHY_CFG 0x160 + +#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) +#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) +#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) +#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) +#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) +#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) +#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) +#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) +#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) +#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) +#define ICPU_MEMPHY_CFG_PHY_RST BIT(0) + +#define ICPU_MEMPHY_ZCAL 0x188 + +#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) +#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) +#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) + +#define ICPU_MEMPHY_ZCAL_STAT 0x18c + +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12)) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8)) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6)) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4)) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2)) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1) +#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0) +#endif diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h new file mode 100644 index 0000000000..fdb554f551 --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/tlb.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __ASM_MACH_TLB_H +#define __ASM_MACH_TLB_H + +#include +#include +#include + +#define TLB_HI_MASK 0xffffe000 +#define TLB_LO_MASK 0x3fffffff /* Masks off Fill bits */ +#define TLB_LO_SHIFT 6 /* PFN Start bit */ + +#define PAGEMASK_SHIFT 13 + +#define MMU_PAGE_CACHED (3 << 3) /* C(5:3) Cache Coherency Attributes */ +#define MMU_PAGE_UNCACHED (2 << 3) /* C(5:3) Cache Coherency Attributes */ +#define MMU_PAGE_DIRTY BIT(2) /* = Writeable */ +#define MMU_PAGE_VALID BIT(1) +#define MMU_PAGE_GLOBAL BIT(0) +#define MMU_REGIO_RO_C (MMU_PAGE_CACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL) +#define MMU_REGIO_RO (MMU_PAGE_UNCACHED | MMU_PAGE_VALID | MMU_PAGE_GLOBAL) +#define MMU_REGIO_RW (MMU_PAGE_DIRTY | MMU_REGIO_RO) +#define MMU_REGIO_INVAL (MMU_PAGE_GLOBAL) + +#define TLB_COUNT_MASK GENMASK(5, 0) +#define TLB_COUNT_OFF 25 + +static inline u32 get_tlb_count(void) +{ + register u32 config1; + + config1 = read_c0_config1(); + config1 >>= TLB_COUNT_OFF; + config1 &= TLB_COUNT_MASK; + + return 1 + config1; +} + +static inline void create_tlb(int index, u32 offset, u32 size, u32 tlb_attrib1, + u32 tlb_attrib2) +{ + register u32 tlb_mask, tlb_lo0, tlb_lo1; + + tlb_mask = ((size >> 12) - 1) << PAGEMASK_SHIFT; + tlb_lo0 = tlb_attrib1 | (offset >> TLB_LO_SHIFT); + tlb_lo1 = tlb_attrib2 | ((offset + size) >> TLB_LO_SHIFT); + + write_one_tlb(index, tlb_mask, offset & TLB_HI_MASK, + tlb_lo0 & TLB_LO_MASK, tlb_lo1 & TLB_LO_MASK); +} +#endif /* __ASM_MACH_TLB_H */ diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S new file mode 100644 index 0000000000..dfbe06766c --- /dev/null +++ b/arch/mips/mach-mscc/lowlevel_init.S @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include + + .set noreorder + .extern vcoreiii_tlb_init +#ifdef CONFIG_SOC_LUTON + .extern pll_init +#endif + +LEAF(lowlevel_init) + /* + * As we have no stack yet, we can assume the restricted + * luxury of the sX-registers without saving them + */ + move s0,ra + + jal vcoreiii_tlb_init + nop +#ifdef CONFIG_SOC_LUTON + jal pll_init + nop +#endif + jr s0 + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mscc/lowlevel_init_luton.S b/arch/mips/mach-mscc/lowlevel_init_luton.S new file mode 100644 index 0000000000..8a528fa83a --- /dev/null +++ b/arch/mips/mach-mscc/lowlevel_init_luton.S @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include + +#define BASE_MACRO 0x600a0000 +#define REG_OFFSET(t, o) (t + (o*4)) +#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x) +#define BIT(nr) (1 << (nr)) + +#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6) +#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0) +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2) +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0) +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6) +#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6) + + .set noreorder +LEAF(pll_init) + /* Make sure PLL is locked */ + lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 + andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS + bne v1, zero, 1f + nop + + /* Black magic from frontend */ + li v1, 0x00610400 + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 + + li v1, 0x00610c00 + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 + + li v1, 0x00610800 + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 + + li v1, 0x00610000 + sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 + + /* Wait for lock */ +2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 + andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS + /* Keep looping if zero (no lock bit yet) */ + beq v1, zero, 2b + nop + + /* Setup PLL CPU clock divider for 416MHz */ +1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 + + /* Keep reserved bits */ + li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV + and v0, v0, v1 + + /* Set code 6 ~ 416.66 MHz */ + ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6) + + sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 + jr ra + nop + END(pll_init) diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c new file mode 100644 index 0000000000..390bbd086a --- /dev/null +++ b/arch/mips/mach-mscc/reset.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include + +#include +#include + +#include + +void _machine_restart(void) +{ + register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; + (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); + + /* Make sure VCore is NOT protected from reset */ + clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); + + /* Change to SPI bitbang for SPI reset workaround... */ + writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | + ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); + + /* Do the global reset */ + writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); + + while (1) + ; /* NOP */ +} diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig index 13a7bd2cc0..4ebcb4b053 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mt7620/Kconfig @@ -24,6 +24,7 @@ choice config BOARD_GARDENA_SMART_GATEWAY_MT7688 bool "Gardena Smart Gateway" depends on SOC_MT7620 + select BOARD_LATE_INIT select SUPPORTS_BOOT_RAM help Gardena Smart Gateway boards have a MT7688 SoC with 128 MiB of RAM diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c index 457f09f32c..9e0ca716f7 100644 --- a/arch/mips/mach-mt7620/cpu.c +++ b/arch/mips/mach-mt7620/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -67,3 +68,54 @@ int print_cpuinfo(void) return 0; } + +#ifdef CONFIG_WATCHDOG +static struct udevice *watchdog_dev; + +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + static ulong next_reset; + ulong now; + + if (!watchdog_dev) + return; + + now = get_timer(0); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + next_reset = now + 1000; /* reset every 1000ms */ + wdt_reset(watchdog_dev); + } +} +#endif + +int arch_misc_init(void) +{ + /* + * It has been noticed, that sometimes the d-cache is not in a + * "clean-state" when U-Boot is running on MT7688. This was + * detected when using the ethernet driver (which uses d-cache) + * and a TFTP command does not complete. Flushing the complete + * d-cache (again?) here seems to fix this issue. + */ + flush_dcache_range(gd->bd->bi_memstart, + gd->bd->bi_memstart + gd->ram_size - 1); + +#ifdef CONFIG_WATCHDOG + /* Init watchdog */ + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { + debug("Watchdog: Not found by seq!\n"); + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Watchdog: Not found!\n"); + return 0; + } + } + + wdt_start(watchdog_dev, 60000, 0); /* 60 seconds */ + printf("Watchdog: Started\n"); +#endif + + return 0; +} diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S index 1a50f160fe..aa707e0de6 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -108,6 +108,12 @@ CPLL_READY: sw t3, 0(t0) CPLL_DONE: + /* Reset MC */ + lw t2, 0x34(s0) + ori t2, BIT(10) + sw t2, 0x34(s0) + nop + /* * SDR and DDR initialization: delay 200us */ diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk index c5520fd8d8..12cec368d3 100644 --- a/arch/nds32/config.mk +++ b/arch/nds32/config.mk @@ -12,8 +12,8 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := nds32le-linux- endif -CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \ - -T $(srctree)/examples/standalone/nds32.lds +CONFIG_STANDALONE_LOAD_ADDR = 0x300000 +LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/nds32.lds PLATFORM_RELFLAGS += -fno-common -mrelax PLATFORM_RELFLAGS += -gdwarf-2 diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index aa9457f5e4..cf966e2132 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -200,14 +200,6 @@ update_gp: jal turnoff_watchdog #endif -/* - * Do CPU critical regs init only at reboot, - * not when booting from ram - */ -#ifdef CONFIG_INIT_CRITICAL - jal cpu_init_crit ! Do CPU critical regs init -#endif - /* * Set stackpointer in internal RAM to call board_init_f * $sp must be 8-byte alignment for ABI compliance. @@ -318,49 +310,6 @@ call_board_init_r: /* jump to it ... */ jr $lp /* jump to board_init_r() */ -/* - * Initialize CPU critical registers - * - * 1. Setup control registers - * 1.1 Mask all IRQs - * 1.2 Flush cache and TLB - * 1.3 Disable MMU and cache - * 2. Setup memory timing - */ - -cpu_init_crit: - - move $r0, $lp /* push ra */ - - /* Disable Interrupts by clear GIE in $PSW reg */ - setgie.d - - /* Flush caches and TLB */ - /* Invalidate caches */ - jal invalidate_icac - jal invalidate_dcac - - /* Flush TLB */ - mfsr $p0, $MMU_CFG - andi $p0, $p0, 0x3 ! MMPS - li $p1, 0x2 ! TLB MMU - bne $p0, $p1, 1f - tlbop flushall ! Flush TLB - -1: - ! Disable MMU, Dcache - ! Whitiger is MMU disabled when reset - ! Disable the D$ - mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg - li $p1, DIS_DCAC - and $p0, $p0, $p1 ! Set DC_EN bit - mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg - isb - - move $lp, $r0 -2: - ret - /* * Invalidate I$ */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 8dde4beeea..b8bdaaec2f 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -144,9 +144,11 @@ in_flash: ori r2, r2, CONFIG_SYS_DER@l mtspr DER, r2 - /* set up the stack in internal DPRAM */ + /* set up the stack on top of internal DPRAM */ lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + stw r0, -4(r3) + stw r0, -8(r3) addi r1, r3, -8 bl board_init_f_alloc_reserve diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index a19aa56300..172bed4c20 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb +dtb-$(CONFIG_MCR3000) += mcr3000.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts new file mode 100644 index 0000000000..5abf111dc5 --- /dev/null +++ b/arch/powerpc/dts/mcr3000.dts @@ -0,0 +1,22 @@ +/* + * MCR3000 Device Tree Source + * + * Copyright 2017 CS Systemes d'Information + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + }; + SERIAL: smc@0 { + compatible = "fsl,pq1-smc"; + }; + + chosen { + stdout-path = &SERIAL; + }; +}; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 849a69aced..c9c9964630 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -18,13 +18,6 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ -#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) -# ifndef CONFIG_HARD_SPI -# define CONFIG_HARD_SPI -# endif -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h index cd6d31c71a..60a7d37d30 100644 --- a/arch/powerpc/include/asm/spl.h +++ b/arch/powerpc/include/asm/spl.h @@ -8,7 +8,4 @@ #define BOOT_DEVICE_NOR 1 -/* Linker symbols */ -extern char __bss_start[], __bss_end[]; - #endif diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168ca3de7c..c45e4d73a8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -16,31 +16,104 @@ config TARGET_QEMU_VIRT endchoice +# board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -choice - prompt "CPU selection" - default CPU_RISCV_32 +# platform-specific options below +source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/qemu/Kconfig" -config CPU_RISCV_32 - bool "RISC-V 32-bit" +# architecture-specific options below + +choice + prompt "Base ISA" + default ARCH_RV32I + +config ARCH_RV32I + bool "RV32I" select 32BIT help - Choose this option to build an U-Boot for RISCV32 architecture. + Choose this option to target the RV32I base integer instruction set. -config CPU_RISCV_64 - bool "RISC-V 64-bit" +config ARCH_RV64I + bool "RV64I" select 64BIT + select PHYS_64BIT help - Choose this option to build an U-Boot for RISCV64 architecture. + Choose this option to target the RV64I base integer instruction set. endchoice +choice + prompt "Code Model" + default CMODEL_MEDLOW + +config CMODEL_MEDLOW + bool "medium low code model" + help + U-Boot and its statically defined symbols must lie within a single 2 GiB + address range and must lie between absolute addresses -2 GiB and +2 GiB. + +config CMODEL_MEDANY + bool "medium any code model" + help + U-Boot and its statically defined symbols must be within any single 2 GiB + address range. + +endchoice + +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + +config RISCV_ISA_C + bool "Emit compressed instructions" + default y + help + Adds "C" to the ISA subsets that the toolchain is allowed to emit + when building U-Boot, which results in compressed instructions in the + U-Boot binary. + +config RISCV_ISA_A + def_bool y + config 32BIT bool config 64BIT bool +config SIFIVE_CLINT + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The SiFive CLINT block holds memory-mapped control and status registers + associated with software and timer interrupts. + +config RISCV_RDTIME + bool + default y if RISCV_SMODE + help + The provides the riscv_get_time() API that is implemented using the + standard rdtime instruction. This is the case for S-mode U-Boot, and + is useful for processors that support rdtime in M-mode too. + +config SYS_MALLOC_F_LEN + default 0x1000 + endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8fb6a889d8..0b80eb8d86 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -3,6 +3,33 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation +ifeq ($(CONFIG_ARCH_RV64I),y) + ARCH_BASE = rv64im + ABI = lp64 +endif +ifeq ($(CONFIG_ARCH_RV32I),y) + ARCH_BASE = rv32im + ABI = ilp32 +endif +ifeq ($(CONFIG_RISCV_ISA_A),y) + ARCH_A = a +endif +ifeq ($(CONFIG_RISCV_ISA_C),y) + ARCH_C = c +endif +ifeq ($(CONFIG_CMODEL_MEDLOW),y) + CMODEL = medlow +endif +ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany +endif + +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + +PLATFORM_CPPFLAGS += $(ARCH_FLAGS) +CFLAGS_EFI += $(ARCH_FLAGS) + head-y := arch/riscv/cpu/start.o libs-y += arch/riscv/cpu/ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index ed9eb0c24c..ff4fe64001 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -14,24 +14,21 @@ 64bit-emul := elf64lriscv ifdef CONFIG_32BIT -PLATFORM_CPPFLAGS += -march=rv32ima -mabi=ilp32 PLATFORM_LDFLAGS += -m $(32bit-emul) -CFLAGS_EFI += -march=rv32ima -mabi=ilp32 EFI_LDS := elf_riscv32_efi.lds endif ifdef CONFIG_64BIT -PLATFORM_CPPFLAGS += -march=rv64ima -mabi=lp64 PLATFORM_LDFLAGS += -m $(64bit-emul) -CFLAGS_EFI += -march=rv64ima -mabi=lp64 EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ - -T $(srctree)/examples/standalone/riscv.lds +CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 +LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/riscv.lds PLATFORM_CPPFLAGS += -ffixed-gp -fpic -PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections +PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ + -fdata-sections LDFLAGS_u-boot += --gc-sections -static -pie EFI_CRT0 := crt0_riscv_efi.o diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 2cc6757fcf..6bf6f911c6 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -4,4 +4,4 @@ extra-y = start.o -obj-y += cpu.o +obj-y += cpu.o mtrap.o diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig new file mode 100644 index 0000000000..e9dbca2fae --- /dev/null +++ b/arch/riscv/cpu/ax25/Kconfig @@ -0,0 +1,14 @@ +config RISCV_NDS + bool + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. + +if RISCV_NDS + +config RISCV_NDS_CACHE + bool "AndeStar V5 families specific cache support" + help + Provide Andes Technology AndeStar V5 families specific cache support. + +endif diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index 2ab0342fe8..318baccb09 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -4,3 +4,4 @@ # Rick Chen, Andes Technology Corporation obj-y := cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c new file mode 100644 index 0000000000..8d6ae170b8 --- /dev/null +++ b/arch/riscv/cpu/ax25/cache.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include + +void icache_enable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void icache_disable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "fence.i\n\t" + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void dcache_enable(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void dcache_disable(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "fence\n\t" + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS_CACHE + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index fddcc156c3..76689b21d3 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,6 +6,7 @@ /* CPU specific code */ #include +#include /* * cleanup_before_linux() is called just before we call linux @@ -18,6 +19,9 @@ int cleanup_before_linux(void) disable_interrupts(); /* turn off I/D-cache */ + cache_flush(); + icache_disable(); + dcache_disable(); return 0; } diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ae57fb8313..e662140427 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -4,46 +4,92 @@ */ #include +#include +#include +#include #include +#include +#include -enum { - ISA_INVALID = 0, - ISA_32BIT, - ISA_64BIT, - ISA_128BIT -}; - -static const char * const isa_bits[] = { - [ISA_INVALID] = NULL, - [ISA_32BIT] = "32", - [ISA_64BIT] = "64", - [ISA_128BIT] = "128" -}; +/* + * prior_stage_fdt_address must be stored in the data section since it is used + * before the bss section is available. + */ +phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); static inline bool supports_extension(char ext) { +#ifdef CONFIG_CPU + struct udevice *dev; + char desc[32]; + + uclass_find_first_device(UCLASS_CPU, &dev); + if (!dev) { + debug("unable to find the RISC-V cpu device\n"); + return false; + } + if (!cpu_get_desc(dev, desc, sizeof(desc))) { + /* skip the first 4 characters (rv32|rv64) */ + if (strchr(desc + 4, ext)) + return true; + } + + return false; +#else /* !CONFIG_CPU */ +#ifdef CONFIG_RISCV_MMODE return csr_read(misa) & (1 << (ext - 'a')); +#else /* !CONFIG_RISCV_MMODE */ +#warning "There is no way to determine the available extensions in S-mode." +#warning "Please convert your board to use the RISC-V CPU driver." + return false; +#endif /* CONFIG_RISCV_MMODE */ +#endif /* CONFIG_CPU */ } -int print_cpuinfo(void) +static int riscv_cpu_probe(void) { - char name[32]; - char *s = name; - int bit; +#ifdef CONFIG_CPU + int ret; - s += sprintf(name, "rv"); - bit = csr_read(misa) >> (sizeof(long) * 8 - 2); - s += sprintf(s, isa_bits[bit]); - - supports_extension('i') ? *s++ = 'i' : 'r'; - supports_extension('m') ? *s++ = 'm' : 'i'; - supports_extension('a') ? *s++ = 'a' : 's'; - supports_extension('f') ? *s++ = 'f' : 'c'; - supports_extension('d') ? *s++ = 'd' : '-'; - supports_extension('c') ? *s++ = 'c' : 'v'; - *s++ = '\0'; - - printf("CPU: %s\n", name); + /* probe cpus so that RISC-V timer can be bound */ + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("RISC-V cpus probe failed\n", ret); +#endif return 0; } + +int arch_cpu_init_dm(void) +{ + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + /* Enable FPU */ + if (supports_extension('d') || supports_extension('f')) { + csr_set(MODE_PREFIX(status), MSTATUS_FS); + csr_write(fcsr, 0); + } + + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + /* + * Enable perf counters for cycle, time, + * and instret counters only + */ + csr_write(mcounteren, GENMASK(2, 0)); + + /* Disable paging */ + if (supports_extension('s')) + csr_write(satp, 0); + } + + return 0; +} + +int arch_early_init_r(void) +{ + return riscv_cpu_probe(); +} diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S new file mode 100644 index 0000000000..407ecfa9c0 --- /dev/null +++ b/arch/riscv/cpu/mtrap.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * M-mode Trap Handler Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + * + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#endif + + .text + + /* trap entry */ + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32 * REGBYTES + SREG x1, 1 * REGBYTES(sp) + SREG x2, 2 * REGBYTES(sp) + SREG x3, 3 * REGBYTES(sp) + SREG x4, 4 * REGBYTES(sp) + SREG x5, 5 * REGBYTES(sp) + SREG x6, 6 * REGBYTES(sp) + SREG x7, 7 * REGBYTES(sp) + SREG x8, 8 * REGBYTES(sp) + SREG x9, 9 * REGBYTES(sp) + SREG x10, 10 * REGBYTES(sp) + SREG x11, 11 * REGBYTES(sp) + SREG x12, 12 * REGBYTES(sp) + SREG x13, 13 * REGBYTES(sp) + SREG x14, 14 * REGBYTES(sp) + SREG x15, 15 * REGBYTES(sp) + SREG x16, 16 * REGBYTES(sp) + SREG x17, 17 * REGBYTES(sp) + SREG x18, 18 * REGBYTES(sp) + SREG x19, 19 * REGBYTES(sp) + SREG x20, 20 * REGBYTES(sp) + SREG x21, 21 * REGBYTES(sp) + SREG x22, 22 * REGBYTES(sp) + SREG x23, 23 * REGBYTES(sp) + SREG x24, 24 * REGBYTES(sp) + SREG x25, 25 * REGBYTES(sp) + SREG x26, 26 * REGBYTES(sp) + SREG x27, 27 * REGBYTES(sp) + SREG x28, 28 * REGBYTES(sp) + SREG x29, 29 * REGBYTES(sp) + SREG x30, 30 * REGBYTES(sp) + SREG x31, 31 * REGBYTES(sp) + csrr a0, MODE_PREFIX(cause) + csrr a1, MODE_PREFIX(epc) + mv a2, sp + jal handle_trap + csrw MODE_PREFIX(epc), a0 + + LREG x1, 1 * REGBYTES(sp) + LREG x3, 3 * REGBYTES(sp) + LREG x4, 4 * REGBYTES(sp) + LREG x5, 5 * REGBYTES(sp) + LREG x6, 6 * REGBYTES(sp) + LREG x7, 7 * REGBYTES(sp) + LREG x8, 8 * REGBYTES(sp) + LREG x9, 9 * REGBYTES(sp) + LREG x10, 10 * REGBYTES(sp) + LREG x11, 11 * REGBYTES(sp) + LREG x12, 12 * REGBYTES(sp) + LREG x13, 13 * REGBYTES(sp) + LREG x14, 14 * REGBYTES(sp) + LREG x15, 15 * REGBYTES(sp) + LREG x16, 16 * REGBYTES(sp) + LREG x17, 17 * REGBYTES(sp) + LREG x18, 18 * REGBYTES(sp) + LREG x19, 19 * REGBYTES(sp) + LREG x20, 20 * REGBYTES(sp) + LREG x21, 21 * REGBYTES(sp) + LREG x22, 22 * REGBYTES(sp) + LREG x23, 23 * REGBYTES(sp) + LREG x24, 24 * REGBYTES(sp) + LREG x25, 25 * REGBYTES(sp) + LREG x26, 26 * REGBYTES(sp) + LREG x27, 27 * REGBYTES(sp) + LREG x28, 28 * REGBYTES(sp) + LREG x29, 29 * REGBYTES(sp) + LREG x30, 30 * REGBYTES(sp) + LREG x31, 31 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) + addi sp, sp, 32 * REGBYTES + MODE_PREFIX(ret) diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig new file mode 100644 index 0000000000..f48751e6de --- /dev/null +++ b/arch/riscv/cpu/qemu/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +config QEMU_RISCV + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply SIFIVE_CLINT if RISCV_MMODE + imply CMD_CPU diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index 6c7a32755a..ad2950ce40 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -4,6 +4,7 @@ */ #include +#include /* * cleanup_before_linux() is called just before we call linux @@ -15,7 +16,20 @@ int cleanup_before_linux(void) { disable_interrupts(); - /* turn off I/D-cache */ + cache_flush(); return 0; } + +/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ +static const struct udevice_id riscv_virtio_soc_ids[] = { + { .compatible = "riscv-virtio-soc" }, + { } +}; + +U_BOOT_DRIVER(riscv_virtio_soc) = { + .name = "riscv_virtio_soc", + .id = UCLASS_SIMPLE_BUS, + .of_match = riscv_virtio_soc_ids, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 7cd7755190..81ea52b170 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -14,58 +14,48 @@ #include #include #include +#include #ifdef CONFIG_32BIT -#define LREG lw -#define SREG sw -#define REGBYTES 4 +#define LREG lw +#define SREG sw +#define REGBYTES 4 #define RELOC_TYPE R_RISCV_32 #define SYM_INDEX 0x8 #define SYM_SIZE 0x10 #else -#define LREG ld -#define SREG sd -#define REGBYTES 8 +#define LREG ld +#define SREG sd +#define REGBYTES 8 #define RELOC_TYPE R_RISCV_64 #define SYM_INDEX 0x20 #define SYM_SIZE 0x18 #endif -.section .text +.section .text .globl _start _start: - j handle_reset + /* save hart id and dtb pointer */ + mv s0, a0 + mv s1, a1 -nmi_vector: - j nmi_vector + la t0, trap_entry + csrw MODE_PREFIX(tvec), t0 -trap_vector: - j trap_entry + /* mask all interrupts */ + csrw MODE_PREFIX(ie), zero -.global trap_entry -handle_reset: - li t0, CONFIG_SYS_SDRAM_BASE - SREG a2, 0(t0) - la t0, trap_entry - csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 - -/* - * Do CPU critical regs init only at reboot, - * not when booting from ram - */ -#ifdef CONFIG_INIT_CRITICAL - jal cpu_init_crit /* Do CPU critical regs init */ -#endif + /* Enable cache */ + jal icache_enable + jal dcache_enable /* * Set stackpointer in internal/ex RAM to call board_init_f */ call_board_init_f: - li t0, -16 - li t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 /* force 16 byte alignment */ + li t0, -16 + li t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 /* force 16 byte alignment */ #ifdef CONFIG_DEBUG_UART jal debug_uart_init @@ -75,11 +65,18 @@ call_board_init_f_0: mv a0, sp jal board_init_f_alloc_reserve mv sp, a0 + + la t0, prior_stage_fdt_address + SREG s1, 0(t0) + jal board_init_f_init_reserve - mv a0, zero /* a0 <-- boot_flags = 0 */ - la t5, board_init_f - jr t5 /* jump to board_init_f() */ + /* save the boot hart id to global_data */ + SREG s0, GD_BOOT_HART(gp) + + mv a0, zero /* a0 <-- boot_flags = 0 */ + la t5, board_init_f + jr t5 /* jump to board_init_f() */ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -90,203 +87,118 @@ call_board_init_f_0: */ .globl relocate_code relocate_code: - mv s2, a0 /* save addr_sp */ - mv s3, a1 /* save addr of gd */ - mv s4, a2 /* save addr of destination */ + mv s2, a0 /* save addr_sp */ + mv s3, a1 /* save addr of gd */ + mv s4, a2 /* save addr of destination */ /* *Set up the stack */ stack_setup: - mv sp, s2 - la t0, _start - sub t6, s4, t0 /* t6 <- relocation offset */ - beq t0, s4, clear_bss /* skip relocation */ + mv sp, s2 + la t0, _start + sub t6, s4, t0 /* t6 <- relocation offset */ + beq t0, s4, clear_bss /* skip relocation */ - mv t1, s4 /* t1 <- scratch for copy_loop */ - la t3, __bss_start - sub t3, t3, t0 /* t3 <- __bss_start_ofs */ - add t2, t0, t3 /* t2 <- source end address */ + mv t1, s4 /* t1 <- scratch for copy_loop */ + la t3, __bss_start + sub t3, t3, t0 /* t3 <- __bss_start_ofs */ + add t2, t0, t3 /* t2 <- source end address */ copy_loop: - LREG t5, 0(t0) - addi t0, t0, REGBYTES - SREG t5, 0(t1) - addi t1, t1, REGBYTES - blt t0, t2, copy_loop + LREG t5, 0(t0) + addi t0, t0, REGBYTES + SREG t5, 0(t1) + addi t1, t1, REGBYTES + blt t0, t2, copy_loop /* * Update dynamic relocations after board_init_f */ fix_rela_dyn: - la t1, __rel_dyn_start - la t2, __rel_dyn_end - beq t1, t2, clear_bss - add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ - add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ + la t1, __rel_dyn_start + la t2, __rel_dyn_end + beq t1, t2, clear_bss + add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ + add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ /* * skip first reserved entry: address, type, addend */ - bne t1, t2, 7f + bne t1, t2, 7f 6: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ - bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ - LREG t3, -(REGBYTES*3)(t1) - LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ + bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ + LREG t3, -(REGBYTES*3)(t1) + LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) 7: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b + addi t1, t1, (REGBYTES*3) + ble t1, t2, 6b 8: - la t4, __dyn_sym_start - add t4, t4, t6 + la t4, __dyn_sym_start + add t4, t4, t6 9: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ - andi t5, t5, 0xFF /* t5 <--- relocation type */ - li t3, RELOC_TYPE - bne t5, t3, 10f /* skip non-addned entries */ + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ + andi t5, t5, 0xFF /* t5 <--- relocation type */ + li t3, RELOC_TYPE + bne t5, t3, 10f /* skip non-addned entries */ - LREG t3, -(REGBYTES*3)(t1) - li t5, SYM_SIZE - mul t0, t0, t5 - add s1, t4, t0 - LREG t5, REGBYTES(s1) - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) + LREG t3, -(REGBYTES*3)(t1) + li t5, SYM_SIZE + mul t0, t0, t5 + add s5, t4, t0 + LREG t5, REGBYTES(s5) + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) 10: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 9b + addi t1, t1, (REGBYTES*3) + ble t1, t2, 9b /* * trap update */ - la t0, trap_entry - add t0, t0, t6 - csrw mtvec, t0 + la t0, trap_entry + add t0, t0, t6 + csrw MODE_PREFIX(tvec), t0 clear_bss: - la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ - add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ - la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ - add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ - beq t0, t1, call_board_init_r + la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ + add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ + la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ + add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ + beq t0, t1, call_board_init_r clbss_l: - SREG t2, 0(t0) /* clear loop... */ - addi t0, t0, REGBYTES - bne t0, t1, clbss_l + SREG zero, 0(t0) /* clear loop... */ + addi t0, t0, REGBYTES + bne t0, t1, clbss_l /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ call_board_init_r: - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ + jal invalidate_icache_all + jal flush_dcache_all + la t0, board_init_r + mv t4, t0 /* offset of board_init_r() */ + add t4, t4, t6 /* real address of board_init_r() */ /* * setup parameters for board_init_r */ - mv a0, s3 /* gd_t */ - mv a1, s4 /* dest_addr */ + mv a0, s3 /* gd_t */ + mv a1, s4 /* dest_addr */ /* * jump to it ... */ - jr t4 /* jump to board_init_r() */ - -/* - * trap entry - */ -trap_entry: - addi sp, sp, -32*REGBYTES - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - -/* - * Remain in M-mode after mret - */ - li t0, MSTATUS_MPP - csrs mstatus, t0 - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - addi sp, sp, 32*REGBYTES - mret - -#ifdef CONFIG_INIT_CRITICAL -cpu_init_crit: - ret -#endif + jr t4 /* jump to board_init_r() */ diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index a1b06ffc6f..b400defb38 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350.dtb targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts new file mode 100644 index 0000000000..0679827313 --- /dev/null +++ b/arch/riscv/dts/ae350_32.dts @@ -0,0 +1,229 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "andestech,a25"; + model = "andestech,a25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <60000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdc"; + mmu-type = "riscv,sv32"; + clock-frequency = <60000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "andestech,riscv-ae350-soc"; + ranges; + + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe4000000 0x2000000>; + riscv,ndev=<71>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + }; + + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xe6400000 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; + + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0xe6000000 0x100000>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + clock-frequency = <60000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0xf0c00000 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0xe0200000 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0xe0400000 0x1000>; + }; + + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0xf0d00000 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe007000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe006000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe005000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe004000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe003000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe002000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe001000 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0xfe000000 0x1000>; + compatible = "virtio,mmio"; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x88000000 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <4 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350_64.dts similarity index 58% rename from arch/riscv/dts/ae350.dts rename to arch/riscv/dts/ae350_64.dts index 4717ae88bc..e48c298645 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -12,15 +12,14 @@ }; chosen { - bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <10000000>; - + timebase-frequency = <60000000>; CPU0: cpu@0 { device_type = "cpu"; reg = <0>; @@ -29,7 +28,8 @@ riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv39"; clock-frequency = <60000000>; - + d-cache-size = <0x8000>; + d-cache-line-size = <32>; CPU0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -48,13 +48,6 @@ #size-cells = <2>; compatible = "andestech,riscv-ae350-soc"; ranges; - }; - - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; @@ -62,7 +55,7 @@ #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<31>; + riscv,ndev=<71>; interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; }; @@ -76,6 +69,13 @@ interrupts-extended = <&CPU0_intc 3>; }; + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; + }; + spiclk: virt_100mhz { #clock-cells = <0>; compatible = "fixed-clock"; @@ -85,7 +85,7 @@ timer0: timer@f0400000 { compatible = "andestech,atcpit100"; reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <40000000>; + clock-frequency = <60000000>; interrupts = <3 4>; interrupt-parent = <&plic0>; }; @@ -119,11 +119,89 @@ interrupt-parent = <&plic0>; }; + dma0: dma@f0c00000 { + compatible = "andestech,atcdmac300"; + reg = <0x0 0xf0c00000 0x0 0x1000>; + interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; + dma-channels = <8>; + interrupt-parent = <&plic0>; + }; + + lcd0: lcd@e0200000 { + compatible = "andestech,atflcdc100"; + reg = <0x0 0xe0200000 0x0 0x1000>; + interrupts = <20 4>; + interrupt-parent = <&plic0>; + }; + smc0: smc@e0400000 { compatible = "andestech,atfsmc020"; reg = <0x0 0xe0400000 0x0 0x1000>; }; + snd0: snd@f0d00000 { + compatible = "andestech,atfac97"; + reg = <0x0 0xf0d00000 0x0 0x1000>; + interrupts = <17 4>; + interrupt-parent = <&plic0>; + }; + + virtio_mmio@fe007000 { + interrupts = <0x17 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe007000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe006000 { + interrupts = <0x16 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe006000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe005000 { + interrupts = <0x15 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe005000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe004000 { + interrupts = <0x14 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe004000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe003000 { + interrupts = <0x13 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe003000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe002000 { + interrupts = <0x12 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe002000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe001000 { + interrupts = <0x11 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe001000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@fe000000 { + interrupts = <0x10 0x4>; + interrupt-parent = <0x2>; + reg = <0x0 0xfe000000 0x0 0x1000>; + compatible = "virtio,mmio"; + }; + nor@0,0 { compatible = "cfi-flash"; reg = <0x0 0x88000000 0x0 0x1000>; @@ -138,9 +216,8 @@ #size-cells = <0>; num-cs = <1>; clocks = <&spiclk>; - interrupts = <3 4>; + interrupts = <4 4>; interrupt-parent = <&plic0>; - flash@0 { compatible = "spi-flash"; spi-max-frequency = <50000000>; diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h new file mode 100644 index 0000000000..a3f60a8458 --- /dev/null +++ b/arch/riscv/include/asm/barrier.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2013 Regents of the University of California + * Copyright (C) 2017 SiFive + * + * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on + * arch/arm/include/asm/barrier.h + */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#ifndef __ASSEMBLY__ + +#define nop() __asm__ __volatile__ ("nop") + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +/* These barriers do not need to enforce ordering on devices, just memory. */ +#define __smp_mb() RISCV_FENCE(rw,rw) +#define __smp_rmb() RISCV_FENCE(r,r) +#define __smp_wmb() RISCV_FENCE(w,w) + +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define __smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + ___p1; \ +}) + +/* + * This is a very specific barrier: it's currently only used in two places in + * the kernel, both in the scheduler. See include/linux/spinlock.h for the two + * orderings it guarantees, but the "critical section is RCsc" guarantee + * mandates a barrier on RISC-V. The sequence looks like: + * + * lr.aq lock + * sc lock <= LOCKED + * smp_mb__after_spinlock() + * // critical section + * lr lock + * sc.rl lock <= UNLOCKED + * + * The AQ/RL pair provides a RCpc critical section, but there's not really any + * way we can take advantage of that here because the ordering is only enforced + * on that one lock. Thus, we're just doing a full fence. + */ +#define smp_mb__after_spinlock() RISCV_FENCE(rw,rw) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BARRIER_H */ diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ca83dd67c2..ec8fe201d3 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,6 +7,9 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +/* cache */ +void cache_flush(void); + /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * We use that value for aligning DMA buffers unless the board config has diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 50fccea5c8..86136f542c 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -8,6 +8,8 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include + /* Status register flags */ #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ @@ -59,10 +61,12 @@ #ifndef __ASSEMBLY__ +#define xcsr(csr) #csr + #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -71,7 +75,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " xcsr(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -80,7 +84,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -88,7 +92,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -97,7 +101,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -105,7 +109,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -114,7 +118,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce640..772668c74e 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -7,6 +7,12 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H +#ifdef CONFIG_RISCV_SMODE +#define MODE_PREFIX(__suffix) s##__suffix +#else +#define MODE_PREFIX(__suffix) m##__suffix +#endif + #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 @@ -79,6 +85,21 @@ #define IRQ_COP 12 #define IRQ_HOST 13 +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FETCH_ACCESS 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_BREAKPOINT 3 +#define CAUSE_MISALIGNED_LOAD 4 +#define CAUSE_LOAD_ACCESS 5 +#define CAUSE_MISALIGNED_STORE 6 +#define CAUSE_STORE_ACCESS 7 +#define CAUSE_USER_ECALL 8 +#define CAUSE_SUPERVISOR_ECALL 9 +#define CAUSE_MACHINE_ECALL 11 +#define CAUSE_FETCH_PAGE_FAULT 12 +#define CAUSE_LOAD_PAGE_FAULT 13 +#define CAUSE_STORE_PAGE_FAULT 15 + #define DEFAULT_RSTVEC 0x00001000 #define DEFAULT_NMIVEC 0x00001004 #define DEFAULT_MTVEC 0x00001010 @@ -146,6 +167,227 @@ #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) +/* CSR numbers */ +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 + +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 + +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf + +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 + +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f + +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 + #endif /* __riscv */ #endif /* RISCV_CSR_ENCODING_H */ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 4d5d623725..a3a342c6e1 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -12,6 +12,10 @@ /* Architecture-specific global data */ struct arch_global_data { + long boot_hart; /* boot hart id */ +#ifdef CONFIG_SIFIVE_CLINT + void __iomem *clint; /* clint base address */ +#endif }; #include diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index f4a76d8720..acf5a96449 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -10,22 +10,13 @@ #ifdef __KERNEL__ #include +#include #include static inline void sync(void) { } -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - #ifdef CONFIG_ARCH_MAP_SYSMEM static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) { @@ -48,24 +39,6 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) } #endif -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ -} - -static inline phys_addr_t virt_to_phys(void *vaddr) -{ - return (phys_addr_t)(vaddr); -} - /* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w @@ -74,12 +47,12 @@ static inline phys_addr_t virt_to_phys(void *vaddr) #define __arch_getb(a) (*(unsigned char *)(a)) #define __arch_getw(a) (*(unsigned short *)(a)) #define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long *)(a)) +#define __arch_getq(a) (*(unsigned long long *)(a)) #define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) #define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) #define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long *)(a) = (v)) +#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) #define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writew(v, a) __arch_putw(v, a) @@ -91,13 +64,9 @@ static inline phys_addr_t virt_to_phys(void *vaddr) #define __raw_readl(a) __arch_getl(a) #define __raw_readq(a) __arch_getq(a) -/* - * TODO: The kernel offers some more advanced versions of barriers, it might - * have some advantages to use them instead of the simple one here. - */ -#define dmb() __asm__ __volatile__ ("" : : : "memory") -#define __iormb() dmb() -#define __iowmb() dmb() +#define dmb() mb() +#define __iormb() rmb() +#define __iowmb() wmb() static inline void writeb(u8 val, volatile void __iomem *addr) { @@ -152,7 +121,7 @@ static inline u32 readl(const volatile void __iomem *addr) static inline u64 readq(const volatile void __iomem *addr) { - u32 val; + u64 val; val = __arch_getq(addr); __iormb(); @@ -487,4 +456,7 @@ out: #endif /* __mem_isa */ #endif /* __KERNEL__ */ + +#include + #endif /* __ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h index 7438dbeb03..0fc052082a 100644 --- a/arch/riscv/include/asm/posix_types.h +++ b/arch/riscv/include/asm/posix_types.h @@ -37,10 +37,10 @@ typedef unsigned short __kernel_gid_t; #ifdef __GNUC__ typedef __SIZE_TYPE__ __kernel_size_t; #else -typedef unsigned int __kernel_size_t; +typedef unsigned long __kernel_size_t; #endif -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h new file mode 100644 index 0000000000..d311ee6b45 --- /dev/null +++ b/arch/riscv/include/asm/syscon.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +#ifndef _ASM_SYSCON_H +#define _ASM_SYSCON_H + +/* + * System controllers in a RISC-V system + * + * So far only SiFive's Core Local Interruptor (CLINT) is defined. + */ +enum { + RISCV_NONE, + RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ +}; + +#endif /* _ASM_SYSCON_H */ diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index bd8627196d..403cf9a48f 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -21,7 +21,11 @@ typedef unsigned short umode_t; */ #ifdef __KERNEL__ +#ifdef CONFIG_ARCH_RV64I +#define BITS_PER_LONG 64 +#else #define BITS_PER_LONG 32 +#endif #include diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b58db89752..edfa61690c 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -9,6 +9,8 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_RISCV_RDTIME) += rdtime.o +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c new file mode 100644 index 0000000000..e0b71f5691 --- /dev/null +++ b/arch/riscv/lib/asm-offsets.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * From arch/x86/lib/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + */ + +#include +#include + +int main(void) +{ + DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); + + return 0; +} diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index a7a9fb921b..f36b8702ef 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -8,10 +8,14 @@ #include #include +#include +#include #include -#include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -24,26 +28,41 @@ int arch_fixup_fdt(void *blob) return 0; } -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +/** + * announce_and_cleanup() - Print message and prepare for kernel boot + * + * @fake: non-zero to do everything except actually boot + */ +static void announce_and_cleanup(int fake) { - void (*kernel)(ulong hart, void *dtb); + printf("\nStarting kernel ...%s\n\n", fake ? + "(fake run for tracing)" : ""); + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); +#ifdef CONFIG_BOOTSTAGE_FDT + bootstage_fdt_add_report(); +#endif +#ifdef CONFIG_BOOTSTAGE_REPORT + bootstage_report(); +#endif + +#ifdef CONFIG_USB_DEVICE + udc_disconnect(); +#endif + + board_quiesce_devices(); /* - * allow the PREP bootm subcommand, it is required for bootm to work + * Call remove function of all devices with a removal flag set. + * This may be useful for last-stage operations, like cancelling + * of DMA operation or releasing device internal buffers. */ - if (flag & BOOTM_STATE_OS_PREP) - return 0; + dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - kernel = (void (*)(ulong, void *))images->ep; - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong)kernel); + cleanup_before_linux(); +} +static void boot_prep_linux(bootm_headers_t *images) +{ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); @@ -52,17 +71,56 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) hang(); } #endif + } else { + printf("Device tree not found or missing FDT support\n"); + hang(); + } +} + +static void boot_jump_linux(bootm_headers_t *images, int flag) +{ + void (*kernel)(ulong hart, void *dtb); + int fake = (flag & BOOTM_STATE_OS_FAKE_GO); + + kernel = (void (*)(ulong, void *))images->ep; + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + debug("## Transferring control to kernel (at address %08lx) ...\n", + (ulong)kernel); + + announce_and_cleanup(fake); + + if (!fake) { + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + kernel(gd->arch.boot_hart, images->ft_addr); + } +} + +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + /* No need for those on RISC-V */ + if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE) + return -1; + + if (flag & BOOTM_STATE_OS_PREP) { + boot_prep_linux(images); + return 0; } - /* we assume that the kernel is in place */ - printf("\nStarting kernel ...\n\n"); + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + boot_jump_linux(images, flag); + return 0; + } - cleanup_before_linux(); - - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - kernel(csr_read(mhartid), images->ft_addr); - - /* does not return */ - - return 1; + boot_prep_linux(images); + boot_jump_linux(images, flag); + return 0; +} + +int do_bootm_vxworks(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + return do_bootm_linux(flag, argc, argv, images); } diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 1d67c49c2c..ae5c60716f 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -6,44 +6,68 @@ #include +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); +} + +void flush_dcache_all(void) +{ + asm volatile ("fence" :::"memory"); +} void flush_dcache_range(unsigned long start, unsigned long end) { + flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) { + /* + * RISC-V does not have an instruction for invalidating parts of the + * instruction cache. Invalidate all of it instead. + */ + invalidate_icache_all(); } void invalidate_dcache_range(unsigned long start, unsigned long end) { + flush_dcache_all(); +} + +void cache_flush(void) +{ + invalidate_icache_all(); + flush_dcache_all(); } void flush_cache(unsigned long addr, unsigned long size) { + invalidate_icache_all(); + flush_dcache_all(); } -void icache_enable(void) +__weak void icache_enable(void) { } -void icache_disable(void) +__weak void icache_disable(void) { } -int icache_status(void) +__weak int icache_status(void) { return 0; } -void dcache_enable(void) +__weak void dcache_enable(void) { } -void dcache_disable(void) +__weak void dcache_disable(void) { } -int dcache_status(void) +__weak int dcache_status(void) { return 0; } diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 18f61f515a..b7b5329e1f 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -41,13 +41,13 @@ coff_header: .short 2 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ - .long 1 /* NumberOfSymbols */ + .long 0 /* NumberOfSymbols */ .short section_table - optional_header /* SizeOfOptionalHeader */ - /* - * Characteristics: IMAGE_FILE_DEBUG_STRIPPED | - * IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_LINE_NUMS_STRIPPED - */ - .short 0x206 + /* Characteristics */ + .short (IMAGE_FILE_EXECUTABLE_IMAGE | \ + IMAGE_FILE_LINE_NUMS_STRIPPED | \ + IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ + IMAGE_FILE_DEBUG_STRIPPED) optional_header: .short 0x20b /* PE32+ format */ .byte 0x02 /* MajorLinkerVersion */ diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 0a0995a7af..e185933b01 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -12,7 +12,36 @@ #include #include -static void _exit_trap(int code, uint epc, struct pt_regs *regs); +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) +{ + static const char * const exception_code[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault", + }; + + if (code < ARRAY_SIZE(exception_code)) { + printf("exception code: %ld , %s , epc %lx , ra %lx\n", + code, exception_code[code], epc, regs->ra); + } else { + printf("Reserved\n"); + } + + hang(); +} int interrupt_init(void) { @@ -34,17 +63,30 @@ int disable_interrupts(void) return 0; } -uint handle_trap(uint mcause, uint epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) { - uint is_int; + ulong is_irq, irq; - is_int = (mcause & MCAUSE_INT); - if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - external_interrupt(0); /* handle_m_ext_interrupt */ - else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) - timer_interrupt(0); /* handle_m_timer_interrupt */ - else - _exit_trap(mcause, epc, regs); + is_irq = (cause & MCAUSE_INT); + irq = (cause & ~MCAUSE_INT); + + if (is_irq) { + switch (irq) { + case IRQ_M_EXT: + case IRQ_S_EXT: + external_interrupt(0); /* handle external interrupt */ + break; + case IRQ_M_TIMER: + case IRQ_S_TIMER: + timer_interrupt(0); /* handle timer interrupt */ + break; + default: + _exit_trap(cause, epc, regs); + break; + }; + } else { + _exit_trap(cause, epc, regs); + } return epc; } @@ -59,17 +101,3 @@ __attribute__((weak)) void external_interrupt(struct pt_regs *regs) __attribute__((weak)) void timer_interrupt(struct pt_regs *regs) { } - -static void _exit_trap(int code, uint epc, struct pt_regs *regs) -{ - static const char * const exception_code[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned" - }; - - printf("exception code: %d , %s , epc %08x , ra %08lx\n", - code, exception_code[code], epc, regs->ra); -} diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c new file mode 100644 index 0000000000..e128d7fce6 --- /dev/null +++ b/arch/riscv/lib/rdtime.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Anup Patel + * Copyright (C) 2018, Bin Meng + * + * The riscv_get_time() API implementation that is using the + * standard rdtime instruction. + */ + +#include + +/* Implement the API required by RISC-V timer driver */ +int riscv_get_time(u64 *time) +{ +#ifdef CONFIG_64BIT + u64 n; + + __asm__ __volatile__ ( + "rdtime %0" + : "=r" (n)); + + *time = n; +#else + u32 lo, hi, tmp; + + __asm__ __volatile__ ( + "1:\n" + "rdtimeh %0\n" + "rdtime %1\n" + "rdtimeh %2\n" + "bne %0, %2, 1b" + : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); + + *time = ((u64)hi << 32) | lo; +#endif + + return 0; +} diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 8f5a6a23aa..72bc9241f6 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -6,7 +6,7 @@ #include #include -#ifdef CONFIG_CPU_RISCV_64 +#ifdef CONFIG_ARCH_RV64I #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) #else diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c new file mode 100644 index 0000000000..d24e0d585b --- /dev/null +++ b/arch/riscv/lib/sifive_clint.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). + * The CLINT block holds memory-mapped control and status registers + * associated with software and timer interrupts. + */ + +#include +#include +#include +#include +#include +#include + +/* MSIP registers */ +#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) +/* mtime compare register */ +#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base) + 0xbff8) + +DECLARE_GLOBAL_DATA_PTR; + +#define CLINT_BASE_GET(void) \ + do { \ + long *ret; \ + \ + if (!gd->arch.clint) { \ + ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \ + if (IS_ERR(ret)) \ + return PTR_ERR(ret); \ + gd->arch.clint = ret; \ + } \ + } while (0) + +int riscv_get_time(u64 *time) +{ + CLINT_BASE_GET(); + + *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); + + return 0; +} + +int riscv_set_timecmp(int hart, u64 cmp) +{ + CLINT_BASE_GET(); + + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); + + return 0; +} + +int riscv_send_ipi(int hart) +{ + CLINT_BASE_GET(); + + writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + +int riscv_clear_ipi(int hart) +{ + CLINT_BASE_GET(); + + writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + +static const struct udevice_id sifive_clint_ids[] = { + { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, + { } +}; + +U_BOOT_DRIVER(sifive_clint) = { + .name = "sifive_clint", + .id = UCLASS_SYSCON, + .of_match = sifive_clint_ids, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index 261079441c..f6cf859f24 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -head-y := arch/sandbox/cpu/start.o - +head-y := arch/sandbox/cpu/start.o arch/sandbox/cpu/os.o +head-$(CONFIG_SANDBOX_SDL) += arch/sandbox/cpu/sdl.o libs-y += arch/sandbox/cpu/ libs-y += arch/sandbox/lib/ diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 95f9e3ff63..7226b7be42 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -17,11 +17,12 @@ PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) endif endif -cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds \ +cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \ -Wl,--start-group $(u-boot-main) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ + $(patsubst $(obj)/%,%,$(u-boot-spl-init)) \ -Wl,--start-group $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \ $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections) diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 8fe681844d..bac96447d5 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -5,10 +5,11 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y := cpu.o os.o start.o state.o +obj-y := cpu.o state.o +extra-y := start.o os.o +extra-$(CONFIG_SANDBOX_SDL) += sdl.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o -obj-$(CONFIG_SANDBOX_SDL) += sdl.o # os.c is build in the system environment, so needs standard includes # CFLAGS_REMOVE_os.o cannot be used to drop header include path diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 6098945049..fdfb209f77 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -2,7 +2,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. */ -#define DEBUG + #include #include #include @@ -105,8 +105,8 @@ void *phys_to_virt(phys_addr_t paddr) state = state_get_current(); list_for_each_entry(mentry, &state->mapmem_head, sibling_node) { if (mentry->tag == paddr) { - printf("%s: Used map from %lx to %p\n", __func__, - (ulong)paddr, mentry->ptr); + debug("%s: Used map from %lx to %p\n", __func__, + (ulong)paddr, mentry->ptr); return mentry->ptr; } } @@ -152,7 +152,7 @@ phys_addr_t virt_to_phys(void *ptr) __func__, ptr, (ulong)gd->ram_size); os_abort(); } - printf("%s: Used map from %p to %lx\n", __func__, ptr, mentry->tag); + debug("%s: Used map from %p to %lx\n", __func__, ptr, mentry->tag); return mentry->tag; } diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index 75bfaa4c90..8d05bc2eda 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,8 @@ #include #include +#include + struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void) { return (struct sandbox_eth_raw_if_nameindex *)if_nameindex(); @@ -71,7 +74,7 @@ static int _raw_packet_start(struct eth_sandbox_raw_priv *priv, /* Prepare device struct */ priv->local_bind_sd = -1; - priv->device = malloc(sizeof(struct sockaddr_ll)); + priv->device = os_malloc(sizeof(struct sockaddr_ll)); if (priv->device == NULL) return -ENOMEM; device = priv->device; @@ -144,7 +147,7 @@ static int _local_inet_start(struct eth_sandbox_raw_priv *priv) /* Prepare device struct */ priv->local_bind_sd = -1; priv->local_bind_udp_port = 0; - priv->device = malloc(sizeof(struct sockaddr_in)); + priv->device = os_malloc(sizeof(struct sockaddr_in)); if (priv->device == NULL) return -ENOMEM; device = priv->device; @@ -279,7 +282,7 @@ int sandbox_eth_raw_os_recv(void *packet, int *length, void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv) { - free(priv->device); + os_free(priv->device); priv->device = NULL; close(priv->sd); priv->sd = -1; diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 07e46471fe..a8d01e4001 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -98,9 +98,8 @@ void os_exit(int exit_code) exit(exit_code); } -int os_write_file(const char *name, const void *buf, int size) +int os_write_file(const char *fname, const void *buf, int size) { - char fname[256]; int fd; fd = os_open(fname, OS_O_WRONLY | OS_O_CREAT | OS_O_TRUNC); @@ -110,14 +109,53 @@ int os_write_file(const char *name, const void *buf, int size) } if (os_write(fd, buf, size) != size) { printf("Cannot write to file '%s'\n", fname); + os_close(fd); return -EIO; } os_close(fd); - printf("Write '%s', size %#x (%d)\n", name, size, size); return 0; } +int os_read_file(const char *fname, void **bufp, int *sizep) +{ + off_t size; + int ret = -EIO; + int fd; + + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Cannot open file '%s'\n", fname); + goto err; + } + size = os_lseek(fd, 0, OS_SEEK_END); + if (size < 0) { + printf("Cannot seek to end of file '%s'\n", fname); + goto err; + } + if (os_lseek(fd, 0, OS_SEEK_SET) < 0) { + printf("Cannot seek to start of file '%s'\n", fname); + goto err; + } + *bufp = os_malloc(size); + if (!*bufp) { + printf("Not enough memory to read file '%s'\n", fname); + ret = -ENOMEM; + goto err; + } + if (os_read(fd, *bufp, size) != size) { + printf("Cannot read from file '%s'\n", fname); + goto err; + } + os_close(fd); + *sizep = size; + + return 0; +err: + os_close(fd); + return ret; +} + /* Restore tty state when we exit */ static struct termios orig_term; static bool term_setup; @@ -174,7 +212,12 @@ void *os_malloc(size_t length) struct os_mem_hdr *hdr; int page_size = getpagesize(); - hdr = mmap(NULL, length + page_size, + /* + * Use an address that is hopefully available to us so that pointers + * to this memory are fairly obvious. If we end up with a different + * address, that's fine too. + */ + hdr = mmap((void *)0x10000000, length + page_size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); if (hdr == MAP_FAILED) @@ -338,7 +381,7 @@ void os_dirent_free(struct os_dirent_node *node) while (node) { next = node->next; - free(node); + os_free(node); node = next; } } @@ -363,7 +406,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) /* Create a buffer upfront, with typically sufficient size */ dirlen = strlen(dirname) + 2; len = dirlen + 256; - fname = malloc(len); + fname = os_malloc(len); if (!fname) { ret = -ENOMEM; goto done; @@ -376,7 +419,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) ret = errno; break; } - next = malloc(sizeof(*node) + strlen(entry->d_name) + 1); + next = os_malloc(sizeof(*node) + strlen(entry->d_name) + 1); if (!next) { os_dirent_free(head); ret = -ENOMEM; @@ -385,10 +428,10 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) if (dirlen + strlen(entry->d_name) > len) { len = dirlen + strlen(entry->d_name); old_fname = fname; - fname = realloc(fname, len); + fname = os_realloc(fname, len); if (!fname) { - free(old_fname); - free(next); + os_free(old_fname); + os_free(next); os_dirent_free(head); ret = -ENOMEM; goto done; @@ -422,7 +465,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp) done: closedir(dir); - free(fname); + os_free(fname); return ret; } @@ -520,20 +563,48 @@ static int make_exec(char *fname, const void *data, int size) return 0; } -static int add_args(char ***argvp, const char *add_args[], int count) +/** + * add_args() - Allocate a new argv with the given args + * + * This is used to create a new argv array with all the old arguments and some + * new ones that are passed in + * + * @argvp: Returns newly allocated args list + * @add_args: Arguments to add, each a string + * @count: Number of arguments in @add_args + * @return 0 if OK, -ENOMEM if out of memory + */ +static int add_args(char ***argvp, char *add_args[], int count) { - char **argv; + char **argv, **ap; int argc; - for (argv = *argvp, argc = 0; (*argvp)[argc]; argc++) + for (argc = 0; (*argvp)[argc]; argc++) ; - argv = malloc((argc + count + 1) * sizeof(char *)); + argv = os_malloc((argc + count + 1) * sizeof(char *)); if (!argv) { printf("Out of memory for %d argv\n", count); return -ENOMEM; } - memcpy(argv, *argvp, argc * sizeof(char *)); + for (ap = *argvp, argc = 0; *ap; ap++) { + char *arg = *ap; + + /* Drop args that we don't want to propagate */ + if (*arg == '-' && strlen(arg) == 2) { + switch (arg[1]) { + case 'j': + case 'm': + ap++; + continue; + } + } else if (!strcmp(arg, "--rm_memory")) { + ap++; + continue; + } + argv[argc++] = arg; + } + memcpy(argv + argc, add_args, count * sizeof(char *)); argv[argc + count] = NULL; @@ -541,21 +612,27 @@ static int add_args(char ***argvp, const char *add_args[], int count) return 0; } -int os_jump_to_image(const void *dest, int size) +/** + * os_jump_to_file() - Jump to a new program + * + * This saves the memory buffer, sets up arguments to the new process, then + * execs it. + * + * @fname: Filename to exec + * @return does not return on success, any return value is an error + */ +static int os_jump_to_file(const char *fname) { struct sandbox_state *state = state_get_current(); - char fname[30], mem_fname[30]; + char mem_fname[30]; int fd, err; - const char *extra_args[5]; + char *extra_args[5]; char **argv = state->argv; + int argc; #ifdef DEBUG - int argc, i; + int i; #endif - err = make_exec(fname, dest, size); - if (err) - return err; - strcpy(mem_fname, "/tmp/u-boot.mem.XXXXXX"); fd = mkstemp(mem_fname); if (fd < 0) @@ -568,14 +645,16 @@ int os_jump_to_image(const void *dest, int size) os_fd_restore(); extra_args[0] = "-j"; - extra_args[1] = fname; + extra_args[1] = (char *)fname; extra_args[2] = "-m"; extra_args[3] = mem_fname; - extra_args[4] = "--rm_memory"; - err = add_args(&argv, extra_args, - sizeof(extra_args) / sizeof(extra_args[0])); + argc = 4; + if (state->ram_buf_rm) + extra_args[argc++] = "--rm_memory"; + err = add_args(&argv, extra_args, argc); if (err) return err; + argv[0] = (char *)fname; #ifdef DEBUG for (i = 0; argv[i]; i++) @@ -586,11 +665,26 @@ int os_jump_to_image(const void *dest, int size) os_exit(2); err = execv(fname, argv); - free(argv); + os_free(argv); + if (err) { + perror("Unable to run image"); + printf("Image filename '%s'\n", fname); + return err; + } + + return unlink(fname); +} + +int os_jump_to_image(const void *dest, int size) +{ + char fname[30]; + int err; + + err = make_exec(fname, dest, size); if (err) return err; - return unlink(fname); + return os_jump_to_file(fname); } int os_find_u_boot(char *fname, int maxlen) @@ -641,9 +735,10 @@ int os_find_u_boot(char *fname, int maxlen) } /* Look for 'u-boot' in the parent directory of spl/ */ - p = strstr(fname, "/spl/"); + p = strstr(fname, "spl/"); if (p) { - strcpy(p, p + 4); + /* Remove the "spl" characters */ + memmove(p, p + 4, strlen(p + 4) + 1); fd = os_open(fname, O_RDONLY); if (fd >= 0) { close(fd); @@ -656,17 +751,7 @@ int os_find_u_boot(char *fname, int maxlen) int os_spl_to_uboot(const char *fname) { - struct sandbox_state *state = state_get_current(); - char *argv[state->argc + 1]; - int ret; - - memcpy(argv, state->argv, sizeof(char *) * (state->argc + 1)); - argv[0] = (char *)fname; - ret = execv(fname, argv); - if (ret) - return ret; - - return unlink(fname); + return os_jump_to_file(fname); } void os_localtime(struct rtc_time *rt) diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c index adcb73826f..f668f5379a 100644 --- a/arch/sandbox/cpu/sdl.c +++ b/arch/sandbox/cpu/sdl.c @@ -4,11 +4,26 @@ */ #include +#include #include #include -#include #include +/** + * struct buf_info - a data buffer holding audio data + * + * @pos: Current position playing in audio buffer + * @size: Size of data in audio buffer (0=empty) + * @alloced: Allocated size of audio buffer (max size it can hold) + * @data: Audio data + */ +struct buf_info { + uint pos; + uint size; + uint alloced; + uint8_t *data; +}; + static struct sdl_info { SDL_Surface *screen; int width; @@ -16,11 +31,12 @@ static struct sdl_info { int depth; int pitch; uint frequency; - uint audio_pos; - uint audio_size; - uint8_t *audio_data; + uint sample_rate; bool audio_active; bool inited; + int cur_buf; + struct buf_info buf[2]; + bool running; } sdl; static void sandbox_sdl_poll_events(void) @@ -238,24 +254,37 @@ int sandbox_sdl_key_pressed(int keycode) void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) { + struct buf_info *buf; int avail; + int i; - avail = sdl.audio_size - sdl.audio_pos; - if (avail < len) - len = avail; + for (i = 0; i < 2; i++) { + buf = &sdl.buf[sdl.cur_buf]; + avail = buf->size - buf->pos; + if (avail <= 0) { + sdl.cur_buf = 1 - sdl.cur_buf; + continue; + } + if (avail > len) + avail = len; - SDL_MixAudio(stream, sdl.audio_data + sdl.audio_pos, len, - SDL_MIX_MAXVOLUME); - sdl.audio_pos += len; + SDL_MixAudio(stream, buf->data + buf->pos, avail, + SDL_MIX_MAXVOLUME); + buf->pos += avail; + len -= avail; - /* Loop if we are at the end */ - if (sdl.audio_pos == sdl.audio_size) - sdl.audio_pos = 0; + /* Move to next buffer if we are at the end */ + if (buf->pos == buf->size) + buf->size = 0; + else + break; + } } -int sandbox_sdl_sound_init(void) +int sandbox_sdl_sound_init(int rate, int channels) { SDL_AudioSpec wanted; + int i; if (sandbox_sdl_ensure_init()) return -1; @@ -263,40 +292,28 @@ int sandbox_sdl_sound_init(void) if (sdl.audio_active) return 0; - /* - * At present all sandbox sounds crash. This is probably due to - * symbol name conflicts with U-Boot. We can remove the malloc() - * probles with: - * - * #define USE_DL_PREFIX - * - * and get this: - * - * Assertion 'e->pollfd->fd == e->fd' failed at pulse/mainloop.c:676, - * function dispatch_pollfds(). Aborting. - * - * The right solution is probably to make U-Boot's names private or - * link os.c and sdl.c against their libraries before liking with - * U-Boot. TBD. For now sound is disabled. - */ - printf("(Warning: sandbox sound disabled)\n"); - return 0; - /* Set the audio format */ - wanted.freq = 22050; + wanted.freq = rate; wanted.format = AUDIO_S16; - wanted.channels = 1; /* 1 = mono, 2 = stereo */ + wanted.channels = channels; wanted.samples = 1024; /* Good low-latency value for callback */ wanted.callback = sandbox_sdl_fill_audio; wanted.userdata = NULL; - sdl.audio_size = sizeof(uint16_t) * wanted.freq; - sdl.audio_data = malloc(sdl.audio_size); - if (!sdl.audio_data) { - printf("%s: Out of memory\n", __func__); - return -1; + for (i = 0; i < 2; i++) { + struct buf_info *buf = &sdl.buf[i]; + + buf->alloced = sizeof(uint16_t) * wanted.freq * wanted.channels; + buf->data = malloc(buf->alloced); + if (!buf->data) { + printf("%s: Out of memory\n", __func__); + if (i == 1) + free(sdl.buf[0].data); + return -1; + } + buf->pos = 0; + buf->size = 0; } - sdl.audio_pos = 0; if (SDL_InitSubSystem(SDL_INIT_AUDIO) < 0) { printf("Unable to initialize SDL audio: %s\n", SDL_GetError()); @@ -309,32 +326,51 @@ int sandbox_sdl_sound_init(void) goto err; } sdl.audio_active = true; + sdl.sample_rate = wanted.freq; + sdl.cur_buf = 0; + sdl.running = 0; return 0; err: - free(sdl.audio_data); + for (i = 0; i < 2; i++) + free(sdl.buf[i].data); return -1; } -int sandbox_sdl_sound_start(uint frequency) +int sandbox_sdl_sound_play(const void *data, uint size) { + struct buf_info *buf; + if (!sdl.audio_active) - return -1; - sdl.frequency = frequency; - sound_create_square_wave((unsigned short *)sdl.audio_data, - sdl.audio_size, frequency); - sdl.audio_pos = 0; - SDL_PauseAudio(0); + return 0; + + buf = &sdl.buf[0]; + if (buf->size) + buf = &sdl.buf[1]; + while (buf->size) + usleep(1000); + + if (size > buf->alloced) + return -E2BIG; + + memcpy(buf->data, data, size); + buf->size = size; + buf->pos = 0; + if (!sdl.running) { + SDL_PauseAudio(0); + sdl.running = 1; + } return 0; } int sandbox_sdl_sound_stop(void) { - if (!sdl.audio_active) - return -1; - SDL_PauseAudio(1); + if (sdl.running) { + SDL_PauseAudio(1); + sdl.running = 0; + } return 0; } diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 42c149a498..2ca4cd6e35 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -37,12 +37,43 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return ret; } - /* Hopefully this will not return */ - return os_spl_to_uboot(fname); + /* Set up spl_image to boot from jump_to_image_no_args() */ + spl_image->arg = strdup(fname); + if (!spl_image->arg) + return log_msg_ret("Setup exec filename", -ENOMEM); + + return 0; } SPL_LOAD_IMAGE_METHOD("sandbox", 0, BOOT_DEVICE_BOARD, spl_board_load_image); void spl_board_init(void) { + struct sandbox_state *state = state_get_current(); + struct udevice *dev; + preloader_console_init(); + if (state->show_of_platdata) { + /* + * Scan all the devices so that we can output their platform + * data. See sandbox_spl_probe(). + */ + printf("Scanning misc devices\n"); + for (uclass_first_device(UCLASS_MISC, &dev); + dev; + uclass_next_device(&dev)) + ; + } +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + const char *fname = spl_image->arg; + + if (fname) { + os_fd_restore(); + os_spl_to_uboot(fname); + } else { + printf("No filename provided for U-Boot\n"); + } + hang(); } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 2ee3b48565..2f5e6e9518 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -180,6 +180,7 @@ static int sandbox_cmdline_cb_memory(struct sandbox_state *state, printf("Failed to read RAM buffer '%s': %d\n", arg, err); return err; } + state->ram_buf_read = true; return 0; } @@ -283,6 +284,15 @@ static int sandbox_cmdline_cb_log_level(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(log_level, 'L', 1, "Set log level (0=panic, 7=debug)"); +static int sandbox_cmdline_cb_show_of_platdata(struct sandbox_state *state, + const char *arg) +{ + state->show_of_platdata = true; + + return 0; +} +SANDBOX_CMDLINE_OPT(show_of_platdata, 0, "Show of-platdata in SPL"); + int board_run_command(const char *cmdline) { printf("## Commands are disabled. Please enable CONFIG_CMDLINE.\n"); @@ -292,10 +302,26 @@ int board_run_command(const char *cmdline) static void setup_ram_buf(struct sandbox_state *state) { + /* Zero the RAM buffer if we didn't read it, to keep valgrind happy */ + if (!state->ram_buf_read) { + memset(state->ram_buf, '\0', state->ram_size); + printf("clear %p %x\n", state->ram_buf, state->ram_size); + } + gd->arch.ram_buf = state->ram_buf; gd->ram_size = state->ram_size; } +void state_show(struct sandbox_state *state) +{ + char **p; + + printf("Arguments:\n"); + for (p = state->argv; *p; p++) + printf("%s ", *p); + printf("\n"); +} + int main(int argc, char *argv[]) { struct sandbox_state *state; diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds index f97abdfa05..de65b01b33 100644 --- a/arch/sandbox/cpu/u-boot-spl.lds +++ b/arch/sandbox/cpu/u-boot-spl.lds @@ -14,7 +14,7 @@ SECTIONS } __u_boot_sandbox_option_start = .; - _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) } + _u_boot_sandbox_getopt : { KEEP(*(.u_boot_sandbox_getopt)) } __u_boot_sandbox_option_end = .; __bss_start = .; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index fb866e8807..ae3189ec8c 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -18,8 +18,14 @@ stdout-path = "/serial"; }; + audio: audio-codec { + compatible = "sandbox,audio-codec"; + #sound-dai-cells = <1>; + }; + cros_ec: cros-ec { reg = <0 0>; + u-boot,dm-pre-reloc; compatible = "google,cros-ec-sandbox"; /* @@ -27,6 +33,7 @@ * that the STM32L flash erases to 0, not 0xff. */ flash { + u-boot,dm-pre-reloc; image-pos = <0x08000000>; size = <0x20000>; erase-value = <0>; @@ -59,6 +66,7 @@ }; gpio_a: gpios@0 { + u-boot,dm-pre-reloc; gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <1>; @@ -67,6 +75,7 @@ }; gpio_b: gpios@1 { + u-boot,dm-pre-reloc; gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <2>; @@ -91,19 +100,11 @@ eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; - emul { - compatible = "sandbox,i2c-eeprom"; - sandbox,filename = "i2c.bin"; - sandbox,size = <128>; - }; }; rtc_0: rtc@43 { reg = <0x43>; compatible = "sandbox-rtc"; - emul { - compatible = "sandbox,i2c-rtc"; - }; }; sandbox_pmic: sandbox_pmic { reg = <0x40>; @@ -112,6 +113,28 @@ mc34708: pmic@41 { reg = <0x41>; }; + + i2c_emul: emul { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff>; + compatible = "sandbox,i2c-emul-parent"; + emul-eeprom { + reg = <0x2c>; + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <256>; + }; + emul0 { + reg = <0x43>; + compatible = "sandbox,i2c-rtc"; + }; + }; + }; + + i2s: i2s { + compatible = "sandbox,i2s"; + #sound-dai-cells = <1>; }; lcd { @@ -177,13 +200,26 @@ compatible = "sandbox,reset"; }; + sound { + compatible = "sandbox,sound"; + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&audio 0>; + }; + }; + spi@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; reg = <0 0>; compatible = "sandbox,spi"; cs-gpios = <0>, <&gpio_a 0>; firmware_storage_spi: flash@0 { + u-boot,dm-pre-reloc; reg = <0>; compatible = "spansion,m25p16", "sandbox,spi-flash"; spi-max-frequency = <40000000>; @@ -239,6 +275,7 @@ }; tpm { + u-boot,dm-pre-reloc; compatible = "google,sandbox-tpm"; }; @@ -256,6 +293,7 @@ /* Needs to be available prior to relocation */ uart0: serial { + u-boot,dm-spl; compatible = "sandbox,serial"; sandbox,text-colour = "cyan"; pinctrl-names = "default"; @@ -350,3 +388,10 @@ #include "cros-ec-keyboard.dtsi" #include "sandbox_pmic.dtsi" + +&cros_ec { + u-boot,dm-pre-reloc; + keyboard-controller { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 2c6d351381..d30fd62a2a 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -90,19 +90,11 @@ eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; - emul { - compatible = "sandbox,i2c-eeprom"; - sandbox,filename = "i2c.bin"; - sandbox,size = <128>; - }; }; rtc_0: rtc@43 { reg = <0x43>; compatible = "sandbox-rtc"; - emul { - compatible = "sandbox,i2c-rtc"; - }; }; sandbox_pmic: sandbox_pmic { reg = <0x40>; @@ -111,6 +103,19 @@ mc34708: pmic@41 { reg = <0x41>; }; + + i2c_emul: emul { + reg = <0xff>; + compatible = "sandbox,i2c-emul-parent"; + emul-eeprom { + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <256>; + }; + emul0 { + compatible = "sandbox,i2c-rtc"; + }; + }; }; lcd { diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi index 5ecafaab36..565c382ed4 100644 --- a/arch/sandbox/dts/sandbox_pmic.dtsi +++ b/arch/sandbox/dts/sandbox_pmic.dtsi @@ -11,40 +11,6 @@ &sandbox_pmic { compatible = "sandbox,pmic"; - pmic_emul { - compatible = "sandbox,i2c-pmic"; - - /* - * Default PMICs register values are set by macro - * VAL2REG(min, step, value) [uV/uA] - * VAL2OMREG(mode id) - * reg-defaults - byte array - */ - reg-defaults = /bits/ 8 < - /* BUCK1 */ - VAL2REG(800000, 25000, 1000000) - VAL2REG(150000, 25000, 150000) - VAL2OMREG(BUCK_OM_OFF) - /* BUCK2 */ - VAL2REG(750000, 50000, 3000000) - VAL2REG(150000, 25000, 150000) - VAL2OMREG(0) - /* LDO1 */ - VAL2REG(800000, 25000, 1600000) - VAL2REG(100000, 50000, 150000) - VAL2OMREG(LDO_OM_OFF) - /* LDO2 */ - VAL2REG(750000, 50000, 3000000) - VAL2REG(150000, 25000, 150000) - VAL2OMREG(0) - /* reg[12:15] - not used */ - 0x00 - 0x00 - 0x00 - 0x00 - >; - }; - buck1 { regulator-name = "SUPPLY_1.2V"; regulator-min-microvolt = <1200000>; @@ -84,10 +50,45 @@ &mc34708 { compatible = "fsl,mc34708"; +}; - pmic_emul { +&i2c_emul { + emul_pmic0: pmic-emul0 { compatible = "sandbox,i2c-pmic"; + /* + * Default PMICs register values are set by macro + * VAL2REG(min, step, value) [uV/uA] + * VAL2OMREG(mode id) + * reg-defaults - byte array + */ + reg-defaults = /bits/ 8 < + /* BUCK1 */ + VAL2REG(800000, 25000, 1000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(BUCK_OM_OFF) + /* BUCK2 */ + VAL2REG(750000, 50000, 3000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(0) + /* LDO1 */ + VAL2REG(800000, 25000, 1600000) + VAL2REG(100000, 50000, 150000) + VAL2OMREG(LDO_OM_OFF) + /* LDO2 */ + VAL2REG(750000, 50000, 3000000) + VAL2REG(150000, 25000, 150000) + VAL2OMREG(0) + /* reg[12:15] - not used */ + 0x00 + 0x00 + 0x00 + 0x00 + >; + }; + + emul_pmic1: pmic-emul1 { + compatible = "sandbox,i2c-pmic"; reg-defaults = /bits/ 8 < 0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08 0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18 diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 57e0dd7663..3790b4c520 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -42,6 +42,11 @@ osd0 = "/osd"; }; + audio: audio-codec { + compatible = "sandbox,audio-codec"; + #sound-dai-cells = <1>; + }; + cros_ec: cros-ec { reg = <0 0>; compatible = "google,cros-ec-sandbox"; @@ -82,6 +87,8 @@ test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>, <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>, <&gpio_b 9 0xc 3 2 1>; + int-value = <1234>; + uint-value = <(-1234)>; }; junk { @@ -186,6 +193,10 @@ compatible = "denx,u-boot-fdt-test"; }; + h-test { + compatible = "denx,u-boot-fdt-test1"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; @@ -262,35 +273,45 @@ eeprom@2c { reg = <0x2c>; compatible = "i2c-eeprom"; - emul { - compatible = "sandbox,i2c-eeprom"; - sandbox,filename = "i2c.bin"; - sandbox,size = <256>; - }; + sandbox,emul = <&emul_eeprom>; }; rtc_0: rtc@43 { reg = <0x43>; compatible = "sandbox-rtc"; - emul { - compatible = "sandbox,i2c-rtc"; - }; + sandbox,emul = <&emul0>; }; rtc_1: rtc@61 { reg = <0x61>; compatible = "sandbox-rtc"; - emul { + sandbox,emul = <&emul1>; + }; + + i2c_emul: emul { + reg = <0xff>; + compatible = "sandbox,i2c-emul-parent"; + emul_eeprom: emul-eeprom { + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <256>; + }; + emul0: emul0 { + compatible = "sandbox,i2c-rtc"; + }; + emul1: emull { compatible = "sandbox,i2c-rtc"; }; }; sandbox_pmic: sandbox_pmic { reg = <0x40>; + sandbox,emul = <&emul_pmic0>; }; mc34708: pmic@41 { reg = <0x41>; + sandbox,emul = <&emul_pmic1>; }; }; @@ -346,14 +367,22 @@ cpu-test1 { compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; }; cpu-test2 { compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; }; cpu-test3 { compatible = "sandbox,cpu_sandbox"; + u-boot,dm-pre-reloc; + }; + + i2s: i2s { + compatible = "sandbox,i2s"; + #sound-dai-cells = <1>; }; misc-test { @@ -443,6 +472,8 @@ test4 { compatible = "denx,u-boot-probe-test"; + first-syscon = <&syscon0>; + second-sys-ctrl = <&another_system_controller>; }; }; @@ -509,6 +540,17 @@ compatible = "sandbox,smem"; }; + sound { + compatible = "sandbox,sound"; + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&audio 0>; + }; + }; + spi@0 { #address-cells = <1>; #size-cells = <0>; @@ -523,12 +565,12 @@ }; }; - syscon@0 { + syscon0: syscon@0 { compatible = "sandbox,syscon0"; - reg = <0x10 4>; + reg = <0x10 16>; }; - syscon@1 { + another_system_controller: syscon@1 { compatible = "sandbox,syscon1"; reg = <0x20 5 0x28 6 @@ -673,6 +715,7 @@ dev@0,0 { compatible = "denx,u-boot-fdt-dummy"; reg = <0 0x0 0x1000>; + reg-names = "sandbox-dummy-0"; }; dev@1,100 { @@ -712,6 +755,30 @@ sandbox_tee { compatible = "sandbox,tee"; }; + + sandbox_virtio1 { + compatible = "sandbox,virtio1"; + }; + + sandbox_virtio2 { + compatible = "sandbox,virtio2"; + }; + + pinctrl { + compatible = "sandbox,pinctrl"; + }; + + hwspinlock@0 { + compatible = "sandbox,hwspinlock"; + }; + + dma: dma { + compatible = "sandbox,dma"; + #dma-cells = <1>; + + dmas = <&dma 0>, <&dma 1>, <&dma 2>; + dma-names = "m2m", "tx0", "rx0"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/handoff.h b/arch/sandbox/include/asm/handoff.h new file mode 100644 index 0000000000..be4e7b0fae --- /dev/null +++ b/arch/sandbox/include/asm/handoff.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Architecture-specific SPL handoff information for sandbox + * + * Copyright 2018 Google, Inc + * Written by Simon Glass + */ + +#ifndef __handoff_h +#define __handoff_h + +#define TEST_HANDOFF_MAGIC 0x14f93c7b + +struct arch_spl_handoff { + ulong magic; /* Used for testing */ +}; + +#endif diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h index 1c4380c592..1027b59e73 100644 --- a/arch/sandbox/include/asm/sdl.h +++ b/arch/sandbox/include/asm/sdl.h @@ -54,12 +54,12 @@ int sandbox_sdl_scan_keys(int key[], int max_keys); int sandbox_sdl_key_pressed(int keycode); /** - * sandbox_sdl_sound_start() - start playing a sound + * sandbox_sdl_sound_play() - Play a sound * - * @frequency: Frequency of sounds in Hertz - * @return 0 if OK, -ENODEV if no sound is available + * @data: Data to play (typically 16-bit) + * @count: Number of bytes in data */ -int sandbox_sdl_sound_start(uint frequency); +int sandbox_sdl_sound_play(const void *data, uint count); /** * sandbox_sdl_sound_stop() - stop playing a sound @@ -71,9 +71,11 @@ int sandbox_sdl_sound_stop(void); /** * sandbox_sdl_sound_init() - set up the sound system * + * @rate: Sample rate to use + * @channels: Number of channels to use (1=mono, 2=stereo) * @return 0 if OK, -ENODEV if no sound is available */ -int sandbox_sdl_sound_init(void); +int sandbox_sdl_sound_init(int rate, int channels); #else static inline int sandbox_sdl_init_display(int width, int height, @@ -102,12 +104,17 @@ static inline int sandbox_sdl_sound_start(uint frequency) return -ENODEV; } +int sandbox_sdl_sound_play(const void *data, uint count) +{ + return -ENODEV; +} + static inline int sandbox_sdl_sound_stop(void) { return -ENODEV; } -static inline int sandbox_sdl_sound_init(void) +int sandbox_sdl_sound_init(int rate, int channels) { return -ENODEV; } diff --git a/arch/sandbox/include/asm/sound.h b/arch/sandbox/include/asm/sound.h deleted file mode 100644 index a6015b0f60..0000000000 --- a/arch/sandbox/include/asm/sound.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013 Google, Inc - */ - -#ifndef __SANDBOX_SOUND_H -#define __SANDBOX_SOUND_H - -int sound_play(unsigned int msec, unsigned int frequency); - -int sound_init(const void *blob); - -#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index dcb6d5f568..c724827f6c 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -89,6 +89,8 @@ struct sandbox_state { bool skip_delays; /* Ignore any time delays (for test) */ bool show_test_output; /* Don't suppress stdout in tests */ int default_log_level; /* Default log level for sandbox */ + bool show_of_platdata; /* Show of-platdata in SPL */ + bool ram_buf_read; /* true if we read the RAM buffer */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] @@ -99,6 +101,7 @@ struct sandbox_state { ulong next_tag; /* Next address tag to allocate */ struct list_head mapmem_head; /* struct sandbox_mapmem_entry */ + bool hwspinlock; /* Hardware Spinlock status */ }; /* Minimum space we guarantee in the state FDT when calling read/write*/ @@ -241,6 +244,13 @@ bool state_get_skip_delays(void); */ void state_reset_for_test(struct sandbox_state *state); +/** + * state_show() - Show information about the sandbox state + * + * @param state Sandbox state to show + */ +void state_show(struct sandbox_state *state); + /** * Initialize the test system state */ diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 8e60f80ae7..74f9618822 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -113,4 +113,52 @@ int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen); int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp, uint *duty_nsp, bool *enablep, bool *polarityp); +/** + * sandbox_sf_set_block_protect() - Set the BP bits of the status register + * + * @dev: Device to update + * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7) + */ +void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask); + +/** + * sandbox_get_codec_params() - Read back codec parameters + * + * This reads back the parameters set by audio_codec_set_params() for the + * sandbox audio driver. Arguments are as for that function. + */ +void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep, + int *mclk_freqp, int *bits_per_samplep, + uint *channelsp); + +/** + * sandbox_get_i2s_sum() - Read back the sum of the audio data so far + * + * This data is provided to the sandbox driver by the I2S tx_data() method. + * + * @dev: Device to check + * @return sum of audio data + */ +int sandbox_get_i2s_sum(struct udevice *dev); + +/** + * sandbox_get_setup_called() - Returns the number of times setup(*) was called + * + * This is used in the sound test + * + * @dev: Device to check + * @return call count for the setup() method + */ +int sandbox_get_setup_called(struct udevice *dev); + +/** + * sandbox_get_sound_sum() - Read back the sum of the sound data so far + * + * This data is provided to the sandbox driver by the sound play() method. + * + * @dev: Device to check + * @return sum of audio data + */ +int sandbox_get_sound_sum(struct udevice *dev); + #endif diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 92abee17ad..6ef44638ab 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -9,7 +9,7 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) -CONFIG_STANDALONE_LOAD_ADDR += -EB +LDFLAGS_STANDALONE += -EB endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a1c18d26e1..e052093775 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -729,13 +729,22 @@ config PCIE_ECAM_SIZE maximum number of PCI buses as defined by the PCI specification. config I8259_PIC - bool + bool "Enable Intel 8259 compatible interrupt controller" default y help Intel 8259 ISA compatible chipset incorporates two 8259 (master and slave) interrupt controllers. Include this to have U-Boot set up the interrupt correctly. +config APIC + bool "Enable Intel Advanced Programmable Interrupt Controller" + default y + help + The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible + for catching interrupts and distributing them to one or more CPU + cores. In most cases there are some LAPICs (local) for each core and + one I/O APIC. This conjunction is found on most modern x86 systems. + config PINCTRL_ICH6 bool help diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 8151e476d4..b5e8f46297 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -34,7 +34,7 @@ PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) # This is used in the top-level Makefile which does not include # PLATFORM_LDFLAGS -LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined +LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ -j .rel -j .rela -j .reloc @@ -65,7 +65,7 @@ CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI) ifeq ($(CONFIG_EFI_APP),y) PLATFORM_CPPFLAGS += $(CFLAGS_EFI) -LDFLAGS_FINAL += -znocombreloc -shared +LDFLAGS_FINAL += -znocombreloc -shared -s LDSCRIPT := $(LDSCRIPT_EFI) else diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f862d8c071..54668aab24 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ -obj-y += lapic.o ioapic.o +obj-$(CONFIG_APIC) += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 56e98131d7..2eb917283b 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -203,4 +203,5 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_baytrail_probe, .ops = &cpu_x86_baytrail_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 02b3169cf5..232fa40eb5 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -764,4 +764,5 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { .probe = cpu_x86_broadwell_probe, .ops = &cpu_x86_broadwell_ops, .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index aaf0d07192..4c6ed0bfb2 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -77,7 +77,8 @@ int last_stage_init(void) timestamp_add_to_bootstage(); /* start usb so that usb keyboard can be used as input device */ - usb_init(); + if (CONFIG_IS_ENABLED(USB_KEYBOARD)) + usb_init(); board_final_cleanup(); diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 2b6cc9f22d..1aaf851bb4 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -94,4 +94,5 @@ U_BOOT_DRIVER(cpu_x86_drv) = { .of_match = cpu_x86_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index c323c7b19a..225aef7bf6 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -166,7 +166,8 @@ int reserve_arch(void) int last_stage_init(void) { /* start usb so that usb keyboard can be used as input device */ - usb_init(); + if (CONFIG_IS_ENABLED(USB_KEYBOARD)) + usb_init(); return 0; } diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index ed8423e079..1ea415b876 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -264,7 +264,9 @@ int interrupt_init(void) i8259_init(); #endif +#ifdef CONFIG_APIC lapic_setup(); +#endif /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 33e5c6263d..6edc3e233c 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -478,4 +478,5 @@ U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_model_206ax_probe, .ops = &cpu_x86_model_206ax_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/tangier/sysreset.c b/arch/x86/cpu/tangier/sysreset.c index e762ee1b81..b03bc28f93 100644 --- a/arch/x86/cpu/tangier/sysreset.c +++ b/arch/x86/cpu/tangier/sysreset.c @@ -44,5 +44,4 @@ U_BOOT_DRIVER(tangier_sysreset) = { .id = UCLASS_SYSRESET, .of_match = tangier_sysreset_ids, .ops = &tangier_sysreset_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 95fae036f6..e3b65cff66 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -303,6 +303,57 @@ struct acpi_mcfg_mmconfig { /* ACPI global NVS structure */ struct acpi_global_nvs; +/* DBG2 definitions are partially used for SPCR interface_type */ + +/* Types for port_type field */ + +#define ACPI_DBG2_SERIAL_PORT 0x8000 +#define ACPI_DBG2_1394_PORT 0x8001 +#define ACPI_DBG2_USB_PORT 0x8002 +#define ACPI_DBG2_NET_PORT 0x8003 + +/* Subtypes for port_subtype field */ + +#define ACPI_DBG2_16550_COMPATIBLE 0x0000 +#define ACPI_DBG2_16550_SUBSET 0x0001 +#define ACPI_DBG2_ARM_PL011 0x0003 +#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D +#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E +#define ACPI_DBG2_ARM_DCC 0x000F +#define ACPI_DBG2_BCM2835 0x0010 + +#define ACPI_DBG2_1394_STANDARD 0x0000 + +#define ACPI_DBG2_USB_XHCI 0x0000 +#define ACPI_DBG2_USB_EHCI 0x0001 + +#define ACPI_DBG2_UNKNOWN 0x00FF + +/* SPCR (Serial Port Console Redirection table) */ +struct __packed acpi_spcr { + struct acpi_table_header header; + u8 interface_type; + u8 reserved[3]; + struct acpi_gen_regaddr serial_port; + u8 interrupt_type; + u8 pc_interrupt; + u32 interrupt; /* Global system interrupt */ + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved1; + u16 pci_device_id; /* Must be 0xffff if not PCI device */ + u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ + u8 pci_bus; + u8 pci_device; + u8 pci_function; + u32 pci_flags; + u8 pci_segment; + u32 reserved2; +}; + /* These can be used by the target port */ void acpi_fill_header(struct acpi_table_header *header, char *signature); diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl index 7abea4bb96..353b879918 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/platform.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl @@ -21,6 +21,19 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +Scope (_SB) +{ + /* Real Time Clock */ + Device (RTC0) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 0x01, 0x08) + }) + } +} + /* ACPI global NVS */ #include "global_nvs.asl" diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 48193ba957..e166e510cb 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -295,16 +295,16 @@ Device (PCI0) Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () + Name (RBUF, ResourceTemplate() { - UartSerialBus (0x0001C200, DataBitsEight, StopBitsOne, + UartSerialBus(0x0001C200, DataBitsEight, StopBitsOne, 0xFC, LittleEndian, ParityTypeNone, FlowControlHardware, 0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , ) - GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0, + GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 } - GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 } - GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 } }) Return (RBUF) @@ -328,7 +328,7 @@ Device (FLIS) Name (_DDN, "Intel Merrifield Family-Level Interface Shim") Name (RBUF, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000, ) + Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000) PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 } PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 } PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 } diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index c05c6bf8a2..81def0afd3 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -241,6 +241,72 @@ static inline void sync(void) #define __iormb() dmb() #define __iowmb() dmb() +/* + * Read/write from/to an (offsettable) iomem cookie. It might be a PIO + * access or a MMIO access, these functions don't care. The info is + * encoded in the hardware mapping set up by the mapping functions + * (or the cookie itself, depending on implementation and hw). + * + * The generic routines don't assume any hardware mappings, and just + * encode the PIO/MMIO as part of the cookie. They coldly assume that + * the MMIO IO mappings are not in the low address range. + * + * Architectures for which this is not true can't use this generic + * implementation and should do their own copy. + */ + +/* + * We assume that all the low physical PIO addresses (0-0xffff) always + * PIO. That means we can do some sanity checks on the low bits, and + * don't need to just take things for granted. + */ +#define PIO_RESERVED 0x10000UL + +/* + * Ugly macros are a way of life. + */ +#define IO_COND(addr, is_pio, is_mmio) do { \ + unsigned long port = (unsigned long __force)addr; \ + if (port >= PIO_RESERVED) { \ + is_mmio; \ + } else { \ + is_pio; \ + } \ +} while (0) + +static inline u8 ioread8(const volatile void __iomem *addr) +{ + IO_COND(addr, return inb(port), return readb(addr)); + return 0xff; +} + +static inline u16 ioread16(const volatile void __iomem *addr) +{ + IO_COND(addr, return inw(port), return readw(addr)); + return 0xffff; +} + +static inline u32 ioread32(const volatile void __iomem *addr) +{ + IO_COND(addr, return inl(port), return readl(addr)); + return 0xffffffff; +} + +static inline void iowrite8(u8 value, volatile void __iomem *addr) +{ + IO_COND(addr, outb(value, port), writeb(value, addr)); +} + +static inline void iowrite16(u16 value, volatile void __iomem *addr) +{ + IO_COND(addr, outw(value, port), writew(value, addr)); +} + +static inline void iowrite32(u32 value, volatile void __iomem *addr) +{ + IO_COND(addr, outl(value, port), writel(value, addr)); +} + #include #endif /* _ASM_IO_H */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index e48c9b9574..79bc2000bd 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -336,6 +337,115 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); } +static void acpi_create_spcr(struct acpi_spcr *spcr) +{ + struct acpi_table_header *header = &(spcr->header); + struct serial_device_info serial_info = {0}; + ulong serial_address, serial_offset; + uint serial_config; + uint serial_width; + int access_size; + int space_id; + int ret; + + /* Fill out header fields */ + acpi_fill_header(header, "SPCR"); + header->length = sizeof(struct acpi_spcr); + header->revision = 2; + + ret = serial_getinfo(&serial_info); + if (ret) + serial_info.type = SERIAL_CHIP_UNKNOWN; + + /* Encode chip type */ + switch (serial_info.type) { + case SERIAL_CHIP_16550_COMPATIBLE: + spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE; + break; + case SERIAL_CHIP_UNKNOWN: + default: + spcr->interface_type = ACPI_DBG2_UNKNOWN; + break; + } + + /* Encode address space */ + switch (serial_info.addr_space) { + case SERIAL_ADDRESS_SPACE_MEMORY: + space_id = ACPI_ADDRESS_SPACE_MEMORY; + break; + case SERIAL_ADDRESS_SPACE_IO: + default: + space_id = ACPI_ADDRESS_SPACE_IO; + break; + } + + serial_width = serial_info.reg_width * 8; + serial_offset = serial_info.reg_offset << serial_info.reg_shift; + serial_address = serial_info.addr + serial_offset; + + /* Encode register access size */ + switch (serial_info.reg_shift) { + case 0: + access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 1: + access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 2: + access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 3: + access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS; + break; + default: + access_size = ACPI_ACCESS_SIZE_UNDEFINED; + break; + } + + debug("UART type %u @ %lx\n", spcr->interface_type, serial_address); + + /* Fill GAS */ + spcr->serial_port.space_id = space_id; + spcr->serial_port.bit_width = serial_width; + spcr->serial_port.bit_offset = 0; + spcr->serial_port.access_size = access_size; + spcr->serial_port.addrl = lower_32_bits(serial_address); + spcr->serial_port.addrh = upper_32_bits(serial_address); + + /* Encode baud rate */ + switch (serial_info.baudrate) { + case 9600: + spcr->baud_rate = 3; + break; + case 19200: + spcr->baud_rate = 4; + break; + case 57600: + spcr->baud_rate = 6; + break; + case 115200: + spcr->baud_rate = 7; + break; + default: + spcr->baud_rate = 0; + break; + } + + ret = serial_getconfig(&serial_config); + if (ret) + serial_config = SERIAL_DEFAULT_CONFIG; + + spcr->parity = SERIAL_GET_PARITY(serial_config); + spcr->stop_bits = SERIAL_GET_STOP(serial_config); + + /* No PCI devices for now */ + spcr->pci_device_id = 0xffff; + spcr->pci_vendor_id = 0xffff; + + /* Fix checksum */ + header->checksum = table_compute_checksum((void *)spcr, header->length); +} + /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ @@ -350,6 +460,7 @@ ulong write_acpi_tables(ulong start) struct acpi_fadt *fadt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; + struct acpi_spcr *spcr; int i; current = start; @@ -438,6 +549,13 @@ ulong write_acpi_tables(ulong start) acpi_add_table(rsdp, mcfg); current = ALIGN(current, 16); + debug("ACPI: * SPCR\n"); + spcr = (struct acpi_spcr *)current; + acpi_create_spcr(spcr); + current += spcr->header.length; + acpi_add_table(rsdp, spcr); + current = ALIGN(current, 16); + debug("current = %x\n", current); acpi_rsdp_addr = (unsigned long)rsdp; diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index 297067df71..39f8deaed1 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -64,7 +64,8 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) irq_handlers[irq].arg = arg; irq_handlers[irq].count = 0; - unmask_irq(irq); + if (CONFIG_IS_ENABLED(I8259_PIC)) + unmask_irq(irq); if (status) enable_interrupts(); @@ -83,7 +84,8 @@ void irq_free_handler(int irq) status = disable_interrupts(); - mask_irq(irq); + if (CONFIG_IS_ENABLED(I8259_PIC)) + mask_irq(irq); irq_handlers[irq].handler = NULL; irq_handlers[irq].arg = NULL; @@ -104,14 +106,16 @@ void do_irq(int hw_irq) } if (irq_handlers[irq].handler) { - mask_irq(irq); + if (CONFIG_IS_ENABLED(I8259_PIC)) + mask_irq(irq); irq_handlers[irq].handler(irq_handlers[irq].arg); irq_handlers[irq].count++; - unmask_irq(irq); - specific_eoi(irq); - + if (CONFIG_IS_ENABLED(I8259_PIC)) { + unmask_irq(irq); + specific_eoi(irq); + } } else { if ((irq & 7) != 7) { spurious_irq_cnt++; diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c index e05928f322..dcbd4835b3 100644 --- a/board/8dtech/eco5pk/eco5pk.c +++ b/board/8dtech/eco5pk/eco5pk.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include "eco5pk.h" diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index bb69ea3489..44cb302f70 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -21,4 +21,8 @@ config ENV_SIZE config ENV_OFFSET default 0x140000 if ENV_IS_IN_SPI_FLASH +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_NDS + endif diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS index 508c6ace72..b0a99e4ac4 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ax25-ae350/MAINTAINERS @@ -3,4 +3,5 @@ M: Rick Chen S: Maintained F: board/AndesTech/ax25-ae350/ F: include/configs/ax25-ae350.h -F: configs/ax25-ae350_defconfig +F: configs/ae350_rv32_defconfig +F: configs/ae350_rv64_defconfig diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 5f4ca0f5a7..d343453f22 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; +extern phys_addr_t prior_stage_fdt_address; /* * Miscellaneous platform dependent initializations */ @@ -66,7 +67,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { - void **ptr = (void *)CONFIG_SYS_SDRAM_BASE; + void **ptr = (void *)&prior_stage_fdt_address; if (fdt_magic(*ptr) == FDT_MAGIC) return (void *)*ptr; diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 160d30cd79..1f7650cb36 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -212,7 +212,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_NORMAL, /* temperature */ MV_DDR_TIM_2T} }, /* timing */ @@ -234,7 +234,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_8GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_NORMAL, /* temperature */ MV_DDR_TIM_2T} }, /* timing */ diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index 92d7ae77f0..bc18fe6ddf 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -67,7 +67,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866L, /* speed_bin */ MV_DDR_DEV_WIDTH_8BIT, /* memory_width */ MV_DDR_DIE_CAP_2GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index a8cfe8af0a..9368bce26c 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -88,7 +88,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866L, /* speed_bin */ MV_DDR_DEV_WIDTH_8BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ diff --git a/board/amlogic/khadas-vim/Kconfig b/board/amlogic/khadas-vim/Kconfig deleted file mode 100644 index 0fa8db97ea..0000000000 --- a/board/amlogic/khadas-vim/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KHADAS_VIM - -config SYS_BOARD - default "khadas-vim" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "khadas-vim" - -endif diff --git a/board/amlogic/khadas-vim/MAINTAINERS b/board/amlogic/khadas-vim/MAINTAINERS deleted file mode 100644 index 024220a526..0000000000 --- a/board/amlogic/khadas-vim/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KHADAS-VIM -M: Neil Armstrong -S: Maintained -F: board/amlogic/khadas-vim/ -F: include/configs/khadas-vim.h -F: configs/khadas-vim_defconfig diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c deleted file mode 100644 index 692bf2add3..0000000000 --- a/board/amlogic/khadas-vim/khadas-vim.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/khadas-vim2/Kconfig b/board/amlogic/khadas-vim2/Kconfig deleted file mode 100644 index d0af36264d..0000000000 --- a/board/amlogic/khadas-vim2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KHADAS_VIM2 - -config SYS_BOARD - default "khadas-vim2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "khadas-vim2" - -endif diff --git a/board/amlogic/libretech-cc/Kconfig b/board/amlogic/libretech-cc/Kconfig deleted file mode 100644 index 7a6f9169bd..0000000000 --- a/board/amlogic/libretech-cc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LIBRETECH_CC - -config SYS_BOARD - default "libretech-cc" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "libretech-cc" - -endif diff --git a/board/amlogic/libretech-cc/MAINTAINERS b/board/amlogic/libretech-cc/MAINTAINERS deleted file mode 100644 index 398ce57db2..0000000000 --- a/board/amlogic/libretech-cc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -LIBRETECH-CC -M: Neil Armstrong -S: Maintained -F: board/amlogic/libretech-cc/ -F: include/configs/libretech-cc.h -F: configs/libretech-cc_defconfig diff --git a/board/amlogic/libretech-cc/Makefile b/board/amlogic/libretech-cc/Makefile deleted file mode 100644 index 3b0adf8bf5..0000000000 --- a/board/amlogic/libretech-cc/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2016 BayLibre, SAS -# Author: Neil Armstrong - -obj-y := libretech-cc.o diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c deleted file mode 100644 index ccab1272c5..0000000000 --- a/board/amlogic/libretech-cc/libretech-cc.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/nanopi-k2/Kconfig b/board/amlogic/nanopi-k2/Kconfig deleted file mode 100644 index 374bda200c..0000000000 --- a/board/amlogic/nanopi-k2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_NANOPI_K2 - -config SYS_BOARD - default "nanopi-k2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "nanopi-k2" - -endif diff --git a/board/amlogic/nanopi-k2/MAINTAINERS b/board/amlogic/nanopi-k2/MAINTAINERS deleted file mode 100644 index 0452bd1fa1..0000000000 --- a/board/amlogic/nanopi-k2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -NANOPI-K2 -M: Neil Armstrong -S: Maintained -F: board/amlogic/nanopi-k2/ -F: include/configs/nanopi-k2.h -F: configs/nanopi-k2_defconfig diff --git a/board/amlogic/nanopi-k2/Makefile b/board/amlogic/nanopi-k2/Makefile deleted file mode 100644 index 7d9b666e76..0000000000 --- a/board/amlogic/nanopi-k2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2018 Thomas McKahan -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := nanopi-k2.o diff --git a/board/amlogic/nanopi-k2/nanopi-k2.c b/board/amlogic/nanopi-k2/nanopi-k2.c deleted file mode 100644 index ae29dd6fa4..0000000000 --- a/board/amlogic/nanopi-k2/nanopi-k2.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2018 Thomas McKahan - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define EFUSE_SN_OFFSET 20 -#define EFUSE_SN_SIZE 16 -#define EFUSE_MAC_OFFSET 52 -#define EFUSE_MAC_SIZE 6 - -int board_init(void) -{ - return 0; -} - -int misc_init_r(void) -{ - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - ssize_t len; - - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, - mac_addr, EFUSE_MAC_SIZE); - if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - } - - if (!env_get("serial#")) { - len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, - EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) - env_set("serial#", serial); - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig deleted file mode 100644 index 2b16889b07..0000000000 --- a/board/amlogic/odroid-c2/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ODROID_C2 - -config SYS_BOARD - default "odroid-c2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "odroid-c2" - -endif diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS index 699850fd0c..6a853066d7 100644 --- a/board/amlogic/odroid-c2/MAINTAINERS +++ b/board/amlogic/odroid-c2/MAINTAINERS @@ -1,6 +1,8 @@ ODROID-C2 M: Beniamino Galvani +M: Neil Armstrong S: Maintained F: board/amlogic/odroid-c2/ F: include/configs/odroid-c2.h +F: configs/nanopi-k2_defconfig F: configs/odroid-c2_defconfig diff --git a/board/amlogic/nanopi-k2/README b/board/amlogic/odroid-c2/README.nanopi-k2 similarity index 100% rename from board/amlogic/nanopi-k2/README rename to board/amlogic/odroid-c2/README.nanopi-k2 diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README.odroid-c2 similarity index 100% rename from board/amlogic/odroid-c2/README rename to board/amlogic/odroid-c2/README.odroid-c2 diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index 2a2755c387..62f0f4c871 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -17,18 +17,13 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, @@ -40,16 +35,9 @@ int misc_init_r(void) if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); - if (len == EFUSE_SN_SIZE) + if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/p212/Kconfig b/board/amlogic/p212/Kconfig deleted file mode 100644 index 720c92b1ee..0000000000 --- a/board/amlogic/p212/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P212 - -config SYS_BOARD - default "p212" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "p212" - -endif diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index 6575f17e14..07ca6f204d 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -3,4 +3,6 @@ M: Neil Armstrong S: Maintained F: board/amlogic/p212/ F: include/configs/p212.h +F: configs/khadas-vim_defconfig +F: configs/libretech-cc_defconfig F: configs/p212_defconfig diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/p212/README.khadas-vim similarity index 100% rename from board/amlogic/khadas-vim/README rename to board/amlogic/p212/README.khadas-vim diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/p212/README.libretech-cc similarity index 100% rename from board/amlogic/libretech-cc/README rename to board/amlogic/p212/README.libretech-cc diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README.p212 similarity index 100% rename from board/amlogic/p212/README rename to board/amlogic/p212/README.p212 diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index 00e07d77ad..546c4d9c86 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -18,19 +18,14 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RMII, - MESON_GXL_USE_INTERNAL_RMII_PHY); + meson_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_USE_INTERNAL_RMII_PHY); if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, @@ -48,10 +43,3 @@ int misc_init_r(void) return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/khadas-vim2/MAINTAINERS b/board/amlogic/q200/MAINTAINERS similarity index 54% rename from board/amlogic/khadas-vim2/MAINTAINERS rename to board/amlogic/q200/MAINTAINERS index ca63e311c6..be86386619 100644 --- a/board/amlogic/khadas-vim2/MAINTAINERS +++ b/board/amlogic/q200/MAINTAINERS @@ -1,6 +1,6 @@ -KHADAS-VIM2 +Q200 M: Neil Armstrong S: Maintained -F: board/amlogic/khadas-vim2/ -F: include/configs/khadas-vim2.h +F: board/amlogic/q200/ +F: include/configs/q200.h F: configs/khadas-vim2_defconfig diff --git a/board/amlogic/khadas-vim/Makefile b/board/amlogic/q200/Makefile similarity index 85% rename from board/amlogic/khadas-vim/Makefile rename to board/amlogic/q200/Makefile index 558c0769b7..fd78fd068a 100644 --- a/board/amlogic/khadas-vim/Makefile +++ b/board/amlogic/q200/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2016 BayLibre, SAS # Author: Neil Armstrong -obj-y := khadas-vim.o +obj-y := q200.o diff --git a/board/amlogic/khadas-vim2/README b/board/amlogic/q200/README.khadas-vim2 similarity index 100% rename from board/amlogic/khadas-vim2/README rename to board/amlogic/q200/README.khadas-vim2 diff --git a/board/amlogic/q200/README.q200 b/board/amlogic/q200/README.q200 new file mode 100644 index 0000000000..55d730a0d2 --- /dev/null +++ b/board/amlogic/q200/README.q200 @@ -0,0 +1,102 @@ +U-Boot for Amlogic Q200 +======================= + +Q200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz + - ARM Mali T860 GPU + - 2/3GB DDR4 SDRAM + - 10/100/1000 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host, 1 x USB 2.0 Device + - 16GB/32GB/64GB eMMC + - 2MB SPI Flash + - microSD + - SDIO Wifi Module, Bluetooth + - IR receiver + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make khadas-vim2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make gxm_q200_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/khadas-vim2/khadas-vim2.c b/board/amlogic/q200/q200.c similarity index 85% rename from board/amlogic/khadas-vim2/khadas-vim2.c rename to board/amlogic/q200/q200.c index ff56569f17..6db1b26e08 100644 --- a/board/amlogic/khadas-vim2/khadas-vim2.c +++ b/board/amlogic/q200/q200.c @@ -18,18 +18,13 @@ #define EFUSE_MAC_OFFSET 52 #define EFUSE_MAC_SIZE 6 -int board_init(void) -{ - return 0; -} - int misc_init_r(void) { u8 mac_addr[EFUSE_MAC_SIZE]; char serial[EFUSE_SN_SIZE]; ssize_t len; - meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); /* Reset PHY on GPIOZ_14 */ clrbits_le32(GX_GPIO_EN(3), BIT(14)); @@ -53,10 +48,3 @@ int misc_init_r(void) return 0; } - -int ft_board_setup(void *blob, bd_t *bd) -{ - meson_gx_init_reserved_memory(blob); - - return 0; -} diff --git a/board/amlogic/s400/MAINTAINERS b/board/amlogic/s400/MAINTAINERS new file mode 100644 index 0000000000..9ca9836016 --- /dev/null +++ b/board/amlogic/s400/MAINTAINERS @@ -0,0 +1,6 @@ +S400 +M: Neil Armstrong +S: Maintained +F: board/amlogic/s400/ +F: include/configs/s400.h +F: configs/s400_defconfig diff --git a/board/amlogic/khadas-vim2/Makefile b/board/amlogic/s400/Makefile similarity index 84% rename from board/amlogic/khadas-vim2/Makefile rename to board/amlogic/s400/Makefile index 4e7c9a0592..bf03862b90 100644 --- a/board/amlogic/khadas-vim2/Makefile +++ b/board/amlogic/s400/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2016 BayLibre, SAS # Author: Neil Armstrong -obj-y := khadas-vim2.o +obj-y := s400.o diff --git a/board/amlogic/s400/README b/board/amlogic/s400/README new file mode 100644 index 0000000000..ab21998dc8 --- /dev/null +++ b/board/amlogic/s400/README @@ -0,0 +1,110 @@ +U-Boot for Amlogic S400 +======================= + +S400 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz + - 1GB DDR4 SDRAM + - 10/100 Ethernet + - 2 x USB 2.0 Host + - eMMC + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connectors + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - eMMC + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make s400_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make axg_s400_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + > mkdir fip + + > cp $FIPDIR/axg/bl2.bin fip/ + > cp $FIPDIR/axg/acs.bin fip/ + > cp $FIPDIR/axg/bl21.bin fip/ + > cp $FIPDIR/axg/bl30.bin fip/ + > cp $FIPDIR/axg/bl301.bin fip/ + > cp $FIPDIR/axg/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $FIPDIR/axg/aml_encrypt_axg --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c new file mode 100644 index 0000000000..02a0e9286c --- /dev/null +++ b/board/amlogic/s400/s400.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int misc_init_r(void) +{ + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + + return 0; +} diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c index 0f0c8a4a97..bf2586d326 100644 --- a/board/armadeus/apf27/apf27.c +++ b/board/armadeus/apf27/apf27.c @@ -16,8 +16,8 @@ #include #include #include +#include #include "apf27.h" -#include "crc.h" #include "fpga.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/armltd/integrator/README b/board/armltd/integrator/README index 5a0e934924..af9dcc1f4f 100644 --- a/board/armltd/integrator/README +++ b/board/armltd/integrator/README @@ -36,9 +36,7 @@ In case c) it may be necessary for U-Boot to perform CM dependent initialization Configuring U-Boot : ------------------ The makefile contains targets for Integrator platforms of both types -fitted with all current variants of CM. If these targets are to be used with -boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure -that the CM is correctly configured. +fitted with all current variants of CM. There are also targets independent of CM. These may not be suitable for boot process c) above. They have been preserved for backward compatibility with diff --git a/board/broadcom/bcm968580xref/Kconfig b/board/broadcom/bcm968580xref/Kconfig new file mode 100644 index 0000000000..b5730367a2 --- /dev/null +++ b/board/broadcom/bcm968580xref/Kconfig @@ -0,0 +1,17 @@ +if ARCH_BCM6858 + +config SYS_VENDOR + default "broadcom" + +config SYS_BOARD + default "bcm968580xref" + +config SYS_CONFIG_NAME + default "broadcom_bcm968580xref" + +endif + +config TARGET_BCM968580XREF + bool "Support Broadcom bcm968580xref" + depends on ARCH_BCM6858 + select ARM64 diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS new file mode 100644 index 0000000000..1ecdfbc0bb --- /dev/null +++ b/board/broadcom/bcm968580xref/MAINTAINERS @@ -0,0 +1,6 @@ +BROADCOM BCM968580XREF +M: Philippe Reynes +S: Maintained +F: board/broadcom/bcm968580xref/ +F: include/configs/broadcom_bcm968580xref.h +F: configs/bcm968580_ram_defconfig diff --git a/board/broadcom/bcm968580xref/Makefile b/board/broadcom/bcm968580xref/Makefile new file mode 100644 index 0000000000..5cd393b196 --- /dev/null +++ b/board/broadcom/bcm968580xref/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm968580xref.o diff --git a/board/broadcom/bcm968580xref/bcm968580xref.c b/board/broadcom/bcm968580xref/bcm968580xref.c new file mode 100644 index 0000000000..2e547f5170 --- /dev/null +++ b/board/broadcom/bcm968580xref/bcm968580xref.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include +#include +#include + +#ifdef CONFIG_ARM64 +#include + +static struct mm_region broadcom_bcm968580xref_mem_map[] = { + { + /* RAM */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* SoC */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0xff80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = broadcom_bcm968580xref_mem_map; +#endif + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + printf("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c index ffbeb14ed0..d26ac35b44 100644 --- a/board/cssi/MCR3000/MCR3000.c +++ b/board/cssi/MCR3000/MCR3000.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -143,3 +145,17 @@ int board_early_init_f(void) return 0; } + +int board_early_init_r(void) +{ + struct udevice *watchdog_dev = NULL; + + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Cannot find watchdog!\n"); + } else { + puts("Enabling watchdog.\n"); + wdt_start(watchdog_dev, 0xffff, 0); + } + + return 0; +} diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds index a32c0e721e..70aef3241c 100644 --- a/board/cssi/MCR3000/u-boot.lds +++ b/board/cssi/MCR3000/u-boot.lds @@ -19,7 +19,6 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) arch/powerpc/lib/built-in.o (.text*) - board/cssi/MCR3000/built-in.o (.text*) drivers/net/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; @@ -69,6 +68,12 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; + /* + * _end - This is end of u-boot.bin image. + * dtb will be appended here to make u-boot-dtb.bin + */ + _end = .; + . = ALIGN(4096); __init_begin = .; .text.init : { *(.text.init) } diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS index 59589867b3..b77a5f6622 100644 --- a/board/davinci/da8xxevm/MAINTAINERS +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -1,13 +1,16 @@ -DA850_AM18XXEVM BOARD +DA850_EVM BOARD M: Adam Ford S: Maintained F: board/davinci/da8xxevm/ F: include/configs/da850evm.h -F: configs/da850_am18xxevm_defconfig F: configs/da850evm_defconfig F: configs/da850evm_nand_defconfig F: configs/da850evm_direct_nor_defconfig +AM18XXEVM BOARD +S: Orphan +F: configs/da850_am18xxevm_defconfig + OMAPL138_LCDK BOARD M: Peter Howard S: Maintained diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index b4b8081c90..b857a5a935 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -209,7 +209,6 @@ void am33xx_spl_board_init(void) const struct dpll_params *get_dpll_ddr_params(void) { enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); return &dpll_ddr; } diff --git a/board/elgin/elgin_rv1108/Kconfig b/board/elgin/elgin_rv1108/Kconfig new file mode 100644 index 0000000000..be9243164a --- /dev/null +++ b/board/elgin/elgin_rv1108/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ELGIN_RV1108 + +config SYS_BOARD + default "elgin_rv1108" + +config SYS_VENDOR + default "elgin" + +config SYS_CONFIG_NAME + default "elgin_rv1108" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/elgin/elgin_rv1108/MAINTAINERS b/board/elgin/elgin_rv1108/MAINTAINERS new file mode 100644 index 0000000000..7747490163 --- /dev/null +++ b/board/elgin/elgin_rv1108/MAINTAINERS @@ -0,0 +1,6 @@ +ELGIN-RV1108 +M: Otavio Salvador +S: Maintained +F: board/elgin/elgin_rv1108 +F: include/configs/elgin_rv1108.h +F: configs/elgin-rv1108_defconfig diff --git a/board/elgin/elgin_rv1108/Makefile b/board/elgin/elgin_rv1108/Makefile new file mode 100644 index 0000000000..382218006a --- /dev/null +++ b/board/elgin/elgin_rv1108/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += elgin_rv1108.o diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c new file mode 100644 index 0000000000..3abc514412 --- /dev/null +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C)Copyright 2016 Rockchip Electronics Co., Ltd + * Authors: Andy Yan + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + int node; + struct rv1108_grf *grf; + enum { + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART2_SOUT_M0, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART2_SIN_M0, + }; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); + grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + /* Elgin board use UART2 m0 for debug*/ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D2_MASK | GPIO2D1_MASK, + GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | + GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); + rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); + + return 0; +} + +#define MODEM_ENABLE_GPIO 111 + +int board_init(void) +{ + gpio_request(MODEM_ENABLE_GPIO, "modem_enable"); + gpio_direction_output(MODEM_ENABLE_GPIO, 0); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x60000000; + gd->bd->bi_dram[0].size = 0x8000000; + + return 0; +} diff --git a/board/embest/mx6boards/MAINTAINERS b/board/embest/mx6boards/MAINTAINERS index 0ffd4668b4..02756c58b3 100644 --- a/board/embest/mx6boards/MAINTAINERS +++ b/board/embest/mx6boards/MAINTAINERS @@ -5,3 +5,4 @@ F: board/embest/mx6boards/ F: include/configs/embestmx6boards.h F: configs/marsboard_defconfig F: configs/riotboard_defconfig +F: configs/riotboard_spl_defconfig diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index 8930c36fe6..fed92aa88a 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -608,3 +608,51 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include + +void board_init_f(ulong dummy) +{ + u32 cputype = cpu_type(get_cpu_rev()); + + switch (cputype) { + case MXC_CPU_MX6SOLO: + board_type = BOARD_IS_RIOTBOARD; + break; + case MXC_CPU_MX6D: + board_type = BOARD_IS_MARSBOARD; + break; + } + arch_cpu_init(); + + /* setup GP timer */ + timer_init(); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + setup_iomux_uart(); + preloader_console_init(); +#endif +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; +} + +/* + * In order to jump to standard u-boot shell, you have to connect pin 5 of J13 + * to pin 3 (ground). + */ +int spl_start_uboot(void) +{ + int gpio_key = IMX_GPIO_NR(4, 16); + + gpio_direction_input(gpio_key); + if (gpio_get_value(gpio_key) == 0) + return 1; + else + return 0; +} + +#endif diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig new file mode 100644 index 0000000000..02ae4d9884 --- /dev/null +++ b/board/emulation/qemu-arm/Kconfig @@ -0,0 +1,13 @@ +if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT + +config SYS_TEXT_BASE + default 0x00000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + imply VIRTIO_MMIO + imply VIRTIO_PCI + imply VIRTIO_NET + imply VIRTIO_BLK + +endif diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 812c90636d..e1f4709c4c 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -2,8 +2,12 @@ /* * Copyright (c) 2017 Tuomas Tynkkynen */ + #include +#include #include +#include +#include #ifdef CONFIG_ARM64 #include @@ -58,6 +62,12 @@ struct mm_region *mem_map = qemu_arm64_mem_map; int board_init(void) { + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + return 0; } diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index af23363fcf..0d865acf10 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,10 +13,26 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE - default 0x80000000 + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select QEMU_RISCV imply SYS_NS16550 + imply VIRTIO_MMIO + imply VIRTIO_NET + imply VIRTIO_BLK + imply CMD_PING + imply CMD_FS_GENERIC + imply DOS_PARTITION + imply EFI_PARTITION + imply ISO_PARTITION + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply BOARD_LATE_INIT + imply OF_BOARD_SETUP + imply SIFIVE_SERIAL endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index 3c6eb4f844..c701c83d77 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -4,4 +4,6 @@ S: Maintained F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig +F: configs/qemu-riscv32_smode_defconfig F: configs/qemu-riscv64_defconfig +F: configs/qemu-riscv64_smode_defconfig diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 041e716c9b..d6167aaef1 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -4,20 +4,86 @@ */ #include +#include #include - -#define MROM_FDT_ADDR 0x1020 +#include +#include int board_init(void) { + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + return 0; } -void *board_fdt_blob_setup(void) +int board_late_init(void) { - /* - * QEMU loads a generated DTB for us immediately - * after the reset vectors in the MROM - */ - return (void *)MROM_FDT_ADDR; + ulong kernel_start; + ofnode chosen_node; + int ret; + + chosen_node = ofnode_path("/chosen"); + if (!ofnode_valid(chosen_node)) { + debug("No chosen node found, can't get kernel start address\n"); + return 0; + } + +#ifdef CONFIG_ARCH_RV64I + ret = ofnode_read_u64(chosen_node, "riscv,kernel-start", + (u64 *)&kernel_start); +#else + ret = ofnode_read_u32(chosen_node, "riscv,kernel-start", + (u32 *)&kernel_start); +#endif + if (ret) { + debug("Can't find kernel start address in device tree\n"); + return 0; + } + + env_set_hex("kernel_start", kernel_start); + + return 0; +} + +/* + * QEMU specifies the location of Linux (supplied with the -kernel argument) + * in the device tree using the riscv,kernel-start and riscv,kernel-end + * properties. We currently rely on the SBI implementation of BBL to run + * Linux and therefore embed Linux as payload in BBL. This causes an issue, + * because BBL detects the kernel properties in the device tree and ignores + * the Linux payload as a result. To work around this issue, we clear the + * kernel properties before booting Linux. + * + * This workaround can be removed, once we do not require BBL for its SBI + * implementation anymore. + */ +int ft_board_setup(void *blob, bd_t *bd) +{ + int chosen_offset, ret; + + chosen_offset = fdt_path_offset(blob, "/chosen"); + if (chosen_offset < 0) + return 0; + +#ifdef CONFIG_ARCH_RV64I + ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-start", 0); +#else + ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-start", 0); +#endif + if (ret) + return ret; + +#ifdef CONFIG_ARCH_RV64I + ret = fdt_setprop_u64(blob, chosen_offset, "riscv,kernel-end", 0); +#else + ret = fdt_setprop_u32(blob, chosen_offset, "riscv,kernel-end", 0); +#endif + if (ret) + return ret; + + return 0; } diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index 41a27dd933..6d19299d8b 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -21,5 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select QEMU select BOARD_ROMSIZE_KB_1024 + imply VIRTIO_PCI + imply VIRTIO_NET + imply VIRTIO_BLK endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index eb5cf88dd2..0ca389c9ae 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -318,6 +318,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_LTC(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; + int count = 100, temp = 0; /* Scale up to the LTC resolution is 1/4096V */ vdd = (vdd * 4096) / 1000; @@ -343,7 +344,9 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) printf("VID: Couldn't read sensor abort VID adjust\n"); return -1; } - } while (vdd_last != vdd_target); + count--; + temp = vdd_last - vdd_target; + } while ((abs(temp) > 2) && (count > 0)); return vdd_last; } @@ -379,6 +382,42 @@ int adjust_vdd(ulong vdd_override) int ret, i2caddress; unsigned long vdd_string_override; char *vdd_string; +#ifdef CONFIG_ARCH_LX2160A + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; +#else #ifdef CONFIG_ARCH_LS1088A static const uint16_t vdd[32] = { 10250, @@ -450,6 +489,7 @@ int adjust_vdd(ulong vdd_override) 0, /* reserved */ 0, /* reserved */ }; +#endif #endif struct vdd_drive { u8 vid; diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig new file mode 100644 index 0000000000..421b081c76 --- /dev/null +++ b/board/freescale/imx8mq_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_EVK + +config SYS_BOARD + default "imx8mq_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_evk" + +endif diff --git a/board/freescale/imx8mq_evk/MAINTAINERS b/board/freescale/imx8mq_evk/MAINTAINERS new file mode 100644 index 0000000000..a2e320cb10 --- /dev/null +++ b/board/freescale/imx8mq_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MQ EVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8mq_evk/ +F: include/configs/imx8mq_evk.h +F: configs/imx8mq_evk_defconfig diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile new file mode 100644 index 0000000000..cf046963d2 --- /dev/null +++ b/board/freescale/imx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README new file mode 100644 index 0000000000..07dbfb01fe --- /dev/null +++ b/board/freescale/imx8mq_evk/README @@ -0,0 +1,36 @@ +U-Boot for the NXP i.MX8MQ EVK board + +Quick Start +==================== +- Build the ARM Trusted firmware binary +- Get ddr and hdmi fimware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +==================== +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.14.62_1.0.0_beta +$ make PLAT=imx8mq bl31 + +Get the ddr and hdmi firmware +==================== +Note: srctree is U-Boot source directory +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin +$ chmod +x firmware-imx-7.9.bin +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree) +$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee) + +Build U-Boot +==================== +$ export ARCH=arm64 +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make imx8mq_evk_defconfig +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==================== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c new file mode 100644 index 0000000000..54e0c38431 --- /dev/null +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c new file mode 100644 index 0000000000..f7ea799343 --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -0,0 +1,1320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + { DDRC_PERFLPR1(0), 0x00000009 }, + { DDRC_PERFWR1(0), 0x02005574 }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + { DDRC_PCFGQOS0_0(0), 0x01110d00 }, + { DDRC_PCFGQOS1_0(0), 0x00620790 }, + { DDRC_PCFGWQOS0_0(0), 0x00100001 }, + { DDRC_PCFGWQOS1_0(0), 0x0000041f }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14*/ + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, + /* MR1 */ + { 0x54038, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14 */ + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + /* { 0x5403d, 0x500 } */ + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + /* PHY Ron/Rtt */ + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + /* MR4/MR3 */ + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, + /* MR12/MR11 */ + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ }, + /* self:0x4d28//MR14/MR13 */ + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ + /* self:0x4d28//MR14/MR13 */ + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file mode 100644 index 0000000000..ec68edaf69 --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0xd }, + { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x4 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x70 }, + { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x1ff8 }, + { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, + { 0x900e0, 0x50 }, + { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x60 }, + { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, + { 0x900e6, 0x8 }, + { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0x8 }, + { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, + { 0x900ec, 0xa }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x6e }, + { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x0 }, + { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, + { 0x900fb, 0x1ff8 }, + { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, + { 0x90101, 0x78 }, + { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, + { 0x90104, 0x68 }, + { 0x90105, 0x790 }, + { 0x90106, 0x16a }, + { 0x90107, 0x8 }, + { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0x8 }, + { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, + { 0x9010d, 0xa }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x58 }, + { 0x90111, 0x0 }, + { 0x90112, 0x68 }, + { 0x90113, 0x0 }, + { 0x90114, 0x408 }, + { 0x90115, 0x169 }, + { 0x90116, 0x0 }, + { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, + { 0x9011c, 0x0 }, + { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, + { 0x9011f, 0x80 }, + { 0x90120, 0x790 }, + { 0x90121, 0x16a }, + { 0x90122, 0x18 }, + { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, + { 0x90125, 0xa }, + { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, + { 0x90128, 0x8 }, + { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, + { 0x9012b, 0xf }, + { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, + { 0x9012e, 0xc }, + { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, + { 0x90131, 0x9 }, + { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, + { 0x90134, 0x0 }, + { 0x90135, 0x408 }, + { 0x90136, 0x169 }, + { 0x90137, 0x0 }, + { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, + { 0x9013a, 0x8 }, + { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, + { 0x9013d, 0x0 }, + { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, + { 0x90140, 0xb7 }, + { 0x90141, 0x790 }, + { 0x90142, 0x16a }, + { 0x90143, 0x1f }, + { 0x90144, 0x0 }, + { 0x90145, 0x68 }, + { 0x90146, 0x8 }, + { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, + { 0x90149, 0xf }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0xc }, + { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x408 }, + { 0x90151, 0x169 }, + { 0x90152, 0x0 }, + { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, + { 0x90155, 0x8 }, + { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, + { 0x90158, 0x3 }, + { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, + { 0x9015b, 0x20 }, + { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, + { 0x90161, 0x8 }, + { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, + { 0x90164, 0x0 }, + { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, + { 0x90167, 0x10 }, + { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, + { 0x90170, 0x8 }, + { 0x90171, 0x448 }, + { 0x90172, 0x109 }, + { 0x90173, 0xf }, + { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x47 }, + { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, + { 0x90185, 0x8 }, + { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, + { 0x90188, 0x0 }, + { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, + { 0x9018b, 0x8 }, + { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, + { 0x9018e, 0x8 }, + { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x6c }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c new file mode 100644 index 0000000000..e6cbc34b0d --- /dev/null +++ b/board/freescale/imx8mq_evk/spl.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_b0; + +void spl_dram_init(void) +{ + /* ddr init */ + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + /* set SW3A standby mode to off */ + pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg &= ~0xf; + reg |= APS_OFF; + pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + + return 0; +} +#endif + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg index 9d39f25bf6..bbffb1a88f 100644 --- a/board/freescale/imx8qxp_mek/imximage.cfg +++ b/board/freescale/imx8qxp_mek/imximage.cfg @@ -7,7 +7,6 @@ */ #define __ASSEMBLY__ -#include /* Boot from SD, sector size 0x400 */ BOOT_FROM SD 0x400 diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS index f3fcdb87ae..480b6bb325 100644 --- a/board/freescale/ls1012afrdm/MAINTAINERS +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -1,9 +1,13 @@ LS1012AFRDM BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012afrdm/ F: include/configs/ls1012afrdm.h F: configs/ls1012afrdm_qspi_defconfig +F: configs/ls1012afrdm_tfa_defconfig +F: configs/ls1012afrwy_tfa_defconfig +F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig LS1012AFRWY BOARD M: Bhaskar Upadhaya diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 5db1027717..b4c611e19f 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -80,6 +80,30 @@ int esdhc_status_fixup(void *blob, const char *compat) } #endif +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) { +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev & BOARD_REV_C) + gd->ram_size = SYS_SDRAM_SIZE_1024; + else + gd->ram_size = SYS_SDRAM_SIZE_512; +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + } + return 0; +} +#else int dram_init(void) { #ifdef CONFIG_TARGET_LS1012AFRWY @@ -122,6 +146,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) { @@ -139,7 +164,8 @@ int board_init(void) * Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index b702fb2740..8844557aae 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -16,6 +16,12 @@ config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40400000 +if CHAIN_OF_TRUST +config SYS_LS_PPA_ESBC_ADDR + hex "PPA Firmware HDR Addr" + default 0x40680000 +endif + if FSL_PFE config BOARD_SPECIFIC_OPTIONS # dummy @@ -33,6 +39,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS index 27c4affd30..dbd4670c3b 100644 --- a/board/freescale/ls1012aqds/MAINTAINERS +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -1,6 +1,9 @@ LS1012AQDS BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012aqds/ F: include/configs/ls1012aqds.h F: configs/ls1012aqds_qspi_defconfig +F: configs/ls1012aqds_tfa_defconfig +F: configs/ls1012aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 7102237756..a862fe6a93 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -18,12 +18,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -55,6 +57,16 @@ int checkboard(void) return 0; } +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else int dram_init(void) { static const struct fsl_mmdc_info mparam = { @@ -74,7 +86,6 @@ int dram_init(void) }; mmdc_init(&mparam); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ @@ -83,6 +94,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) { @@ -110,8 +122,9 @@ int board_init(void) /* Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); @@ -121,6 +134,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 4cd66bd548..51efd0fa37 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -33,6 +33,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS index a0a0d8dc24..60e184d10f 100644 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -1,9 +1,13 @@ LS1012ARDB BOARD M: Prabhakar Kushwaha +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1012ardb/ F: include/configs/ls1012ardb.h F: configs/ls1012ardb_qspi_defconfig +F: configs/ls1012ardb_tfa_defconfig +F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +F: configs/ls1012a2g5rdb_tfa_defconfig M: Sumit Garg S: Maintained diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 888f8500d4..f648a9040b 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -87,8 +87,19 @@ int checkboard(void) return 0; } +#ifdef CONFIG_TFABOOT int dram_init(void) { + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ +#ifndef CONFIG_TFABOOT static const struct fsl_mmdc_info mparam = { 0x05180000, /* mdctl */ 0x00030035, /* mdpdc */ @@ -106,6 +117,7 @@ int dram_init(void) }; mmdc_init(&mparam); +#endif gd->ram_size = CONFIG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) @@ -115,6 +127,7 @@ int dram_init(void) return 0; } +#endif int board_early_init_f(void) @@ -132,7 +145,8 @@ int board_init(void) * Set CCI-400 control override register to enable barrier * transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index c828dacf9e..c08be1ee46 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -244,6 +244,7 @@ void board_init_f(ulong dummy) if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + timer_init(); dram_init(); /* Allow OCRAM access permission as R/W */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index dcd6d933ea..beb82cebb6 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -467,6 +467,7 @@ void board_init_f(ulong dummy) preloader_console_init(); + timer_init(); dram_init(); /* Allow OCRAM access permission as R/W */ diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 3c8e8c24f7..9fb6cc85cd 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -1,5 +1,6 @@ LS1043AQDS BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1043aqds/ F: include/configs/ls1043aqds.h @@ -10,3 +11,5 @@ F: configs/ls1043aqds_sdcard_ifc_defconfig F: configs/ls1043aqds_sdcard_qspi_defconfig F: configs/ls1043aqds_qspi_defconfig F: configs/ls1043aqds_lpuart_defconfig +F: configs/ls1043aqds_tfa_defconfig +F: configs/ls1043aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index efc441a917..d29a3ad797 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -108,6 +108,16 @@ found: #endif } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -131,3 +141,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 44cc509b53..45f006dab7 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -46,8 +47,135 @@ enum { #define CFG_UART_MUX_SHIFT 1 #define CFG_LPUART_EN 0x1 +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif + int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -55,6 +183,12 @@ int checkboard(void) puts("Board: LS1043AQDS, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -73,6 +207,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -156,7 +293,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -386,3 +524,10 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 88fe42e1e8..ed62396760 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS1043A BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1043ardb/ F: board/freescale/ls1043ardb/ls1043ardb.c @@ -7,6 +8,8 @@ F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig +F: configs/ls1043ardb_tfa_defconfig +F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig LS1043A_SECURE_BOOT BOARD M: Ruchika Gupta diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 7bc0f568ff..784e482f32 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void) } #endif +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) +#ifdef CONFIG_SYS_DDR_RAW_TIMING + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = 0x80000000; +#endif + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -236,3 +249,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index f31f0ec515..fbd9a2691b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -27,6 +27,104 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor", + CONFIG_SYS_NOR_CSPR, + CONFIG_SYS_NOR_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "cpld", + CONFIG_SYS_CPLD_CSPR, + CONFIG_SYS_CPLD_CSPR_EXT, + CONFIG_SYS_CPLD_AMASK, + CONFIG_SYS_CPLD_CSOR, + { + CONFIG_SYS_CPLD_FTIM0, + CONFIG_SYS_CPLD_FTIM1, + CONFIG_SYS_CPLD_FTIM2, + CONFIG_SYS_CPLD_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif int board_early_init_f(void) { fsl_lsch2_early_init_f(); @@ -38,6 +136,9 @@ int board_early_init_f(void) int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; @@ -47,6 +148,12 @@ int checkboard(void) printf("Board: LS1043ARDB, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -64,6 +171,9 @@ int checkboard(void) printf("Invalid setting of SW4\n"); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS index 76190c6383..39a48da95a 100644 --- a/board/freescale/ls1046aqds/MAINTAINERS +++ b/board/freescale/ls1046aqds/MAINTAINERS @@ -1,5 +1,6 @@ LS1046AQDS BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1046aqds/ F: include/configs/ls1046aqds.h @@ -9,6 +10,8 @@ F: configs/ls1046aqds_sdcard_ifc_defconfig F: configs/ls1046aqds_sdcard_qspi_defconfig F: configs/ls1046aqds_qspi_defconfig F: configs/ls1046aqds_lpuart_defconfig +F: configs/ls1046aqds_tfa_defconfig +F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig M: Sumit Garg S: Maintained diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 08f7610e69..45b1f373a7 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -92,6 +92,16 @@ found: popts->cpo_sample = 0x70; } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -116,3 +126,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 0da82381af..b71c1746bb 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,12 +33,140 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CONFIG_SYS_NAND_CSPR, + CONFIG_SYS_NAND_CSPR_EXT, + CONFIG_SYS_NAND_AMASK, + CONFIG_SYS_NAND_CSOR, + { + CONFIG_SYS_NAND_FTIM0, + CONFIG_SYS_NAND_FTIM1, + CONFIG_SYS_NAND_FTIM2, + CONFIG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CONFIG_SYS_NOR0_CSPR, + CONFIG_SYS_NOR0_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CONFIG_SYS_NOR1_CSPR, + CONFIG_SYS_NOR1_CSPR_EXT, + CONFIG_SYS_NOR_AMASK, + CONFIG_SYS_NOR_CSOR, + { + CONFIG_SYS_NOR_FTIM0, + CONFIG_SYS_NOR_FTIM1, + CONFIG_SYS_NOR_FTIM2, + CONFIG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CONFIG_SYS_FPGA_CSPR, + CONFIG_SYS_FPGA_CSPR_EXT, + CONFIG_SYS_FPGA_AMASK, + CONFIG_SYS_FPGA_CSOR, + { + CONFIG_SYS_FPGA_FTIM0, + CONFIG_SYS_FPGA_FTIM1, + CONFIG_SYS_FPGA_FTIM2, + CONFIG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif + enum { MUX_TYPE_GPIO, }; int checkboard(void) { +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif char buf[64]; #ifndef CONFIG_SD_BOOT u8 sw; @@ -45,6 +174,12 @@ int checkboard(void) puts("Board: LS1046AQDS, boot from "); +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + #ifdef CONFIG_SD_BOOT puts("SD\n"); #else @@ -63,6 +198,9 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifdef CONFIG_TFABOOT + } +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -153,7 +291,8 @@ int dram_init(void) */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); fsl_initdram(); -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif @@ -342,3 +481,10 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_TFABOOT +void *env_sf_get_env_addr(void) +{ + return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index aac649a942..8b4b45e9ed 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -1,5 +1,6 @@ LS1046A BOARD M: Mingkai Hu +M: Rajesh Bhagat S: Maintained F: board/freescale/ls1046ardb/ F: board/freescale/ls1046ardb/ls1046ardb.c @@ -8,6 +9,8 @@ F: configs/ls1046ardb_qspi_defconfig F: configs/ls1046ardb_qspi_spl_defconfig F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig +F: configs/ls1046ardb_tfa_defconfig +F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig LS1046A_SECURE_BOOT BOARD M: Ruchika Gupta diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index 82b1b1d9ea..321222d68d 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -97,6 +97,17 @@ found: popts->cpo_sample = 0x61; } +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else int fsl_initdram(void) { phys_size_t dram_size; @@ -117,3 +128,4 @@ int fsl_initdram(void) return 0; } +#endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 517a8ceed9..1e2ad98c6e 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #include #include @@ -67,6 +67,24 @@ int init_func_vid(void) } #endif +int is_pb_board(void) +{ + u8 board_id; + + board_id = QIXIS_READ(id); + if (board_id == LS1088ARDB_PB_BOARD) + return 1; + else + return 0; +} + +int fixup_ls1088ardb_pb_banner(void *fdt) +{ + fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); + + return 0; +} + #if !defined(CONFIG_SPL_BUILD) int checkboard(void) { @@ -79,7 +97,10 @@ int checkboard(void) #ifdef CONFIG_TARGET_LS1088AQDS printf("Board: LS1088A-QDS, "); #else - printf("Board: LS1088A-RDB, "); + if (is_pb_board()) + printf("Board: LS1088ARDB-PB, "); + else + printf("Board: LS1088A-RDB, "); #endif sw = QIXIS_READ(arch); @@ -585,6 +606,8 @@ int ft_board_setup(void *blob, bd_t *bd) if (err) return err; #endif + if (is_pb_board()) + fixup_ls1088ardb_pb_banner(blob); return 0; } diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 4ec0af4d1c..d40ed3742e 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -273,7 +273,7 @@ void spi_cs_deactivate(struct spi_slave *slave) iopd->dat |= SPI_CS_MASK; } -#endif /* CONFIG_HARD_SPI */ +#endif #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index 5ff546f505..6e11077977 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -4,14 +4,295 @@ */ #include -#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT76XX_AGPIO_CFG 0x1000003c + +#define FACTORY_DATA_OFFS 0xc0000 +#define FACTORY_DATA_SECT_SIZE 0x10000 +#if ((CONFIG_ENV_OFFSET_REDUND + CONFIG_ENV_SIZE_REDUND) > FACTORY_DATA_OFFS) +#error "U-Boot image with environment too big (overlapping with factory-data)!" +#endif +#define FACTORY_DATA_USER_OFFS 0x140 +#define FACTORY_DATA_SIZE 0x1f0 +#define FACTORY_DATA_CRC_LEN (FACTORY_DATA_SIZE - \ + FACTORY_DATA_USER_OFFS - sizeof(u32)) + +#define FACTORY_DATA_MAGIC 0xCAFEBABE + +struct factory_data_values { + u8 pad_1[4]; + u8 wifi_mac[6]; /* offs: 0x004: binary value */ + u8 pad_2[30]; + u8 eth_mac[6]; /* offs: 0x028: binary value */ + u8 pad_3[FACTORY_DATA_USER_OFFS - 4 - 6 - 30 - 6]; + /* User values start here at offset 0x140 */ + u32 crc; + u32 magic; + u32 version; + char ipr_id[UUID_STR_LEN]; /* UUID as string w/o ending \0 */ + char hqv_id[UUID_STR_LEN]; /* UUID as string w/o ending \0 */ + char unielec_id[UUID_STR_LEN]; /* UUID as string w/o ending \0 */ +}; int board_early_init_f(void) { - /* - * Nothing to be done here for this board (no UART setup etc) - * right now. We might need some pin muxing, so lets keep this - * function for now. - */ + void __iomem *gpio_mode; + + /* Configure digital vs analog GPIOs */ + gpio_mode = ioremap_nocache(MT76XX_AGPIO_CFG, 0x100); + iowrite32(0x00fe01ff, gpio_mode); + return 0; } + +static bool prepare_uuid_var(const char *fd_ptr, const char *env_var_name, + char errorchar) +{ + char str[UUID_STR_LEN + 1] = { 0 }; /* Enough for UUID stuff */ + bool env_updated = false; + char *env; + int i; + + memcpy(str, fd_ptr, UUID_STR_LEN); + + /* Convert non-ascii character to 'X' */ + for (i = 0; i < UUID_STR_LEN; i++) { + if (!(isascii(str[i]) && isprint(str[i]))) + str[i] = errorchar; + } + + env = env_get(env_var_name); + if (strcmp(env, str)) { + env_set(env_var_name, str); + env_updated = true; + } + + return env_updated; +} + +static void factory_data_env_config(void) +{ + struct factory_data_values *fd; + struct spi_flash *sf; + int env_updated = 0; + char str[UUID_STR_LEN + 1]; /* Enough for UUID stuff */ + char *env; + u8 *buf; + u32 crc; + int ret; + u8 *ptr; + + buf = malloc(FACTORY_DATA_SIZE); + if (!buf) { + printf("F-Data:Unable to allocate buffer\n"); + return; + } + + /* + * Get values from factory-data area in SPI NOR + */ + sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!sf) { + printf("F-Data:Unable to access SPI NOR flash\n"); + goto err_free; + } + + ret = spi_flash_read(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SIZE, + (void *)buf); + if (ret) { + printf("F-Data:Unable to read factory-data from SPI NOR\n"); + goto err_spi_flash; + } + + fd = (struct factory_data_values *)buf; + + if (fd->magic != FACTORY_DATA_MAGIC) + printf("F-Data:Magic value not correct\n"); + + crc = crc32(0, (u8 *)&fd->magic, FACTORY_DATA_CRC_LEN); + if (crc != fd->crc) + printf("F-Data:CRC not correct\n"); + else + printf("F-Data:factory-data version %x detected\n", + fd->version); + + /* Handle wifi_mac env variable */ + ptr = fd->wifi_mac; + sprintf(str, "%pM", ptr); + if (!is_valid_ethaddr(ptr)) + printf("F-Data:Invalid MAC addr: wifi_mac %s\n", str); + + env = env_get("wifiaddr"); + if (strcmp(env, str)) { + env_set("wifiaddr", str); + env_updated = 1; + } + + /* Handle eth_mac env variable */ + ptr = fd->eth_mac; + sprintf(str, "%pM", ptr); + if (!is_valid_ethaddr(ptr)) + printf("F-Data:Invalid MAC addr: eth_mac %s\n", str); + + env = env_get("ethaddr"); + if (strcmp(env, str)) { + env_set("ethaddr", str); + env_updated = 1; + } + + /* Handle UUID env variables */ + env_updated |= prepare_uuid_var(fd->ipr_id, "linuxmoduleid", 'X'); + env_updated |= prepare_uuid_var(fd->hqv_id, "linuxmodulehqvid", '\0'); + env_updated |= prepare_uuid_var(fd->unielec_id, + "linuxmoduleunielecid", '\0'); + + /* Check if the environment was updated and needs to get stored */ + if (env_updated != 0) { + printf("F-Data:Values don't match env values -> saving\n"); + env_save(); + } else { + debug("F-Data:Values match current env values\n"); + } + +err_spi_flash: + spi_flash_free(sf); + +err_free: + free(buf); +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + factory_data_env_config(); + + return 0; +} + +static void copy_or_generate_uuid(char *fd_ptr, const char *env_var_name) +{ + char str[UUID_STR_LEN + 1] = { 0 }; /* Enough for UUID stuff */ + char *env; + + /* Don't use the UUID dest place, as the \0 char won't fit */ + env = env_get(env_var_name); + if (env) + strncpy(str, env, UUID_STR_LEN); + else + gen_rand_uuid_str(str, UUID_STR_FORMAT_STD); + + memcpy(fd_ptr, str, UUID_STR_LEN); +} + +/* + * Helper function to provide some sane factory-data values for testing + * purpose, when these values are not programmed correctly + */ +int do_fd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct factory_data_values *fd; + struct spi_flash *sf; + u8 *buf; + int ret = CMD_RET_FAILURE; + + buf = malloc(FACTORY_DATA_SECT_SIZE); + if (!buf) { + printf("F-Data:Unable to allocate buffer\n"); + return CMD_RET_FAILURE; + } + + sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!sf) { + printf("F-Data:Unable to access SPI NOR flash\n"); + goto err_free; + } + + /* Generate the factory-data struct */ + + /* Fist read complete sector into buffer */ + ret = spi_flash_read(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE, + (void *)buf); + if (ret) { + printf("F-Data:spi_flash_read failed (%d)\n", ret); + goto err_spi_flash; + } + + fd = (struct factory_data_values *)buf; + fd->magic = FACTORY_DATA_MAGIC; + fd->version = 0x1; + + /* Use existing MAC and UUID values or generate some random ones */ + if (!eth_env_get_enetaddr("wifiaddr", fd->wifi_mac)) { + net_random_ethaddr(fd->wifi_mac); + /* to get a different seed value for the MAC address */ + mdelay(10); + } + + if (!eth_env_get_enetaddr("ethaddr", fd->eth_mac)) + net_random_ethaddr(fd->eth_mac); + + copy_or_generate_uuid(fd->ipr_id, "linuxmoduleid"); + copy_or_generate_uuid(fd->hqv_id, "linuxmodulehqvid"); + copy_or_generate_uuid(fd->unielec_id, "linuxmoduleunielecid"); + + printf("New factory-data values:\n"); + printf("wifiaddr=%pM\n", fd->wifi_mac); + printf("ethaddr=%pM\n", fd->eth_mac); + + /* + * We don't have the \0 char at the end, so we need to specify the + * length in the printf format instead + */ + printf("linuxmoduleid=%." __stringify(UUID_STR_LEN) "s\n", fd->ipr_id); + printf("linuxmodulehqvid=%." __stringify(UUID_STR_LEN) "s\n", + fd->hqv_id); + printf("linuxmoduleunielecid=%." __stringify(UUID_STR_LEN) "s\n", + fd->unielec_id); + + fd->crc = crc32(0, (u8 *)&fd->magic, FACTORY_DATA_CRC_LEN); + + ret = spi_flash_erase(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE); + if (ret) { + printf("F-Data:spi_flash_erase failed (%d)\n", ret); + goto err_spi_flash; + } + + ret = spi_flash_write(sf, FACTORY_DATA_OFFS, FACTORY_DATA_SECT_SIZE, + buf); + if (ret) { + printf("F-Data:spi_flash_write failed (%d)\n", ret); + goto err_spi_flash; + } + + printf("F-Data:factory-data values written to SPI NOR flash\n"); + +err_spi_flash: + spi_flash_free(sf); + +err_free: + free(buf); + + return ret; +} + +U_BOOT_CMD( + fd_write, 1, 0, do_fd_write, + "Write test factory-data values to SPI NOR", + "\n" +); diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 824a08f12a..86051aedf8 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -34,6 +34,19 @@ DECLARE_GLOBAL_DATA_PTR; #define DB_GP_88F68XX_GPP_POL_LOW 0x0 #define DB_GP_88F68XX_GPP_POL_MID 0x0 +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure @@ -51,7 +64,7 @@ static struct mv_ddr_topology_map ddr_topology_map = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */ - DDR_FREQ_533, /* frequency */ + MV_DDR_FREQ_533, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ @@ -266,18 +279,22 @@ int board_fix_fdt(void *rw_fdt_blob) int last_stage_init(void) { + struct udevice *tpm; + int ret; + #ifndef CONFIG_SPL_BUILD ccdc_eth_init(); #endif - if (tpm_init() || tpm_startup(TPM_ST_CLEAR) || - tpm_continue_self_test()) { + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) || + tpm_continue_self_test(tpm)) { return 1; } mdelay(37); - flush_keys(); - load_and_run_keyprog(); + flush_keys(tpm); + load_and_run_keyprog(tpm); return 0; } diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c index 34c4df71b2..82b84284ef 100644 --- a/board/gdsys/a38x/hre.c +++ b/board/gdsys/a38x/hre.c @@ -93,19 +93,20 @@ static const uint8_t vendor[] = "Guntermann & Drunck"; /** * @brief get the size of a given (TPM) NV area + * @param tpm TPM device * @param index NV index of the area to get size for * @param size pointer to the size * @return 0 on success, != 0 on error */ -static int get_tpm_nv_size(uint32_t index, uint32_t *size) +static int get_tpm_nv_size(struct udevice *tpm, uint32_t index, uint32_t *size) { uint32_t err; uint8_t info[72]; uint8_t *ptr; uint16_t v16; - err = tpm_get_capability(TPM_CAP_NV_INDEX, index, - info, sizeof(info)); + err = tpm_get_capability(tpm, TPM_CAP_NV_INDEX, index, + info, sizeof(info)); if (err) { printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n", index, err); @@ -128,13 +129,14 @@ static int get_tpm_nv_size(uint32_t index, uint32_t *size) /** * @brief search for a key by usage auth and pub key hash. + * @param tpm TPM device * @param auth usage auth of the key to search for * @param pubkey_digest (SHA1) hash of the pub key structure of the key * @param[out] handle the handle of the key iff found * @return 0 if key was found in TPM; != 0 if not. */ -static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], - uint32_t *handle) +static int find_key(struct udevice *tpm, const uint8_t auth[20], + const uint8_t pubkey_digest[20], uint32_t *handle) { uint16_t key_count; uint32_t key_handles[10]; @@ -146,7 +148,8 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], unsigned int i; /* fetch list of already loaded keys in the TPM */ - err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + err = tpm_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf, + sizeof(buf)); if (err) return -1; key_count = get_unaligned_be16(buf); @@ -157,7 +160,8 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], /* now search a(/ the) key which we can access with the given auth */ for (i = 0; i < key_count; ++i) { buf_len = sizeof(buf); - err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len); + err = tpm_get_pub_key_oiap(tpm, key_handles[i], auth, buf, + &buf_len); if (err && err != TPM_AUTHFAIL) return -1; if (err) @@ -173,20 +177,21 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], /** * @brief read CCDM common data from TPM NV + * @param tpm TPM device * @return 0 if CCDM common data was found and read, !=0 if something failed. */ -static int read_common_data(void) +static int read_common_data(struct udevice *tpm) { uint32_t size = 0; uint32_t err; uint8_t buf[256]; sha1_context ctx; - if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) || + if (get_tpm_nv_size(tpm, NV_COMMON_DATA_INDEX, &size) || size < NV_COMMON_DATA_MIN_SIZE) return 1; - err = tpm_nv_read_value(NV_COMMON_DATA_INDEX, - buf, min(sizeof(buf), size)); + err = tpm_nv_read_value(tpm, NV_COMMON_DATA_INDEX, + buf, min(sizeof(buf), size)); if (err) { printf("tpm_nv_read_value() failed: %u\n", err); return 1; @@ -235,6 +240,7 @@ static struct h_reg *get_hreg(uint8_t spec) /** * @brief get pointer of a hash register by specification and usage. + * @param tpm TPM device * @param spec specification of a hash register * @param mode access mode (read or write or read/write) * @return pointer to hash register if found and valid; NULL else. @@ -244,7 +250,8 @@ static struct h_reg *get_hreg(uint8_t spec) * The value of automatic registers (PCR register and fixed registers) is * loaded or computed on read access. */ -static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode) +static struct h_reg *access_hreg(struct udevice *tpm, uint8_t spec, + enum access_mode mode) { struct h_reg *result; @@ -261,13 +268,13 @@ static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode) if (mode & HREG_RD) { if (!result->valid) { if (IS_PCR_HREG(spec)) { - hre_tpm_err = tpm_pcr_read(HREG_IDX(spec), + hre_tpm_err = tpm_pcr_read(tpm, HREG_IDX(spec), result->digest, 20); result->valid = (hre_tpm_err == TPM_SUCCESS); } else if (IS_FIX_HREG(spec)) { switch (HREG_IDX(spec)) { case FIX_HREG_DEVICE_ID_HASH: - read_common_data(); + read_common_data(tpm); break; case FIX_HREG_VENDOR: memcpy(result->digest, vendor, 20); @@ -337,18 +344,19 @@ static void *compute_extend(void *_dst, const void *_src, size_t n) return _dst; } -static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg, - const void *key, size_t key_size) +static int hre_op_loadkey(struct udevice *tpm, struct h_reg *src_reg, + struct h_reg *dst_reg, const void *key, + size_t key_size) { uint32_t parent_handle; uint32_t key_handle; if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid) return -1; - if (find_key(src_reg->digest, dst_reg->digest, &parent_handle)) + if (find_key(tpm, src_reg->digest, dst_reg->digest, &parent_handle)) return -1; - hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size, - src_reg->digest, &key_handle); + hre_tpm_err = tpm_load_key2_oiap(tpm, parent_handle, key, key_size, + src_reg->digest, &key_handle); if (hre_tpm_err) { hre_err = HRE_E_TPM_FAILURE; return -1; @@ -359,11 +367,13 @@ static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg, /** * @brief executes the next opcode on the hash register engine. + * @param tpm TPM device * @param[in,out] ip pointer to the opcode (instruction pointer) * @param[in,out] code_size (remaining) size of the code * @return new instruction pointer on success, NULL on error. */ -static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size) +static const uint8_t *hre_execute_op(struct udevice *tpm, const uint8_t **ip, + size_t *code_size) { bool dst_modified = false; uint32_t ins; @@ -394,10 +404,11 @@ static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size) if ((opcode & 0x80) && (data_size + 4) > *code_size) return NULL; - src_reg = access_hreg(src_spec, HREG_RD); + src_reg = access_hreg(tpm, src_spec, HREG_RD); if (hre_err || hre_tpm_err) return NULL; - dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR); + dst_reg = access_hreg(tpm, dst_spec, + (opcode & 0x40) ? HREG_RDWR : HREG_WR); if (hre_err || hre_tpm_err) return NULL; @@ -453,7 +464,7 @@ do_bin_func: dst_modified = true; break; case HRE_LOADKEY: - if (hre_op_loadkey(src_reg, dst_reg, data, data_size)) + if (hre_op_loadkey(tpm, src_reg, dst_reg, data, data_size)) return NULL; break; default: @@ -461,8 +472,8 @@ do_bin_func: } if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) { - hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest, - dst_reg->digest); + hre_tpm_err = tpm_extend(tpm, HREG_IDX(dst_spec), + dst_reg->digest, dst_reg->digest); if (hre_tpm_err) { hre_err = HRE_E_TPM_FAILURE; return NULL; @@ -481,11 +492,12 @@ end: /** * @brief runs a program on the hash register engine. + * @param tpm TPM device * @param code pointer to the (HRE) code. * @param code_size size of the code (in bytes). * @return 0 on success, != 0 on failure. */ -int hre_run_program(const uint8_t *code, size_t code_size) +int hre_run_program(struct udevice *tpm, const uint8_t *code, size_t code_size) { size_t code_left; const uint8_t *ip = code; @@ -494,7 +506,7 @@ int hre_run_program(const uint8_t *code, size_t code_size) hre_tpm_err = 0; hre_err = HRE_E_OK; while (code_left > 0) - if (!hre_execute_op(&ip, &code_left)) + if (!hre_execute_op(tpm, &ip, &code_left)) return -1; return hre_err; diff --git a/board/gdsys/a38x/hre.h b/board/gdsys/a38x/hre.h index b562928a64..da983aa452 100644 --- a/board/gdsys/a38x/hre.h +++ b/board/gdsys/a38x/hre.h @@ -32,6 +32,6 @@ enum { }; int hre_verify_program(struct key_program *prg); -int hre_run_program(const uint8_t *code, size_t code_size); +int hre_run_program(struct udevice *tpm, const uint8_t *code, size_t code_size); #endif /* __HRE_H */ diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c index 1fb5306b50..291edc340d 100644 --- a/board/gdsys/a38x/keyprogram.c +++ b/board/gdsys/a38x/keyprogram.c @@ -12,7 +12,7 @@ #include "hre.h" -int flush_keys(void) +int flush_keys(struct udevice *tpm) { u16 key_count; u8 buf[288]; @@ -21,13 +21,15 @@ int flush_keys(void) uint i; /* fetch list of already loaded keys in the TPM */ - err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + err = tpm_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf, + sizeof(buf)); if (err) return -1; key_count = get_unaligned_be16(buf); ptr = buf + 2; for (i = 0; i < key_count; ++i, ptr += 4) { - err = tpm_flush_specific(get_unaligned_be32(ptr), TPM_RT_KEY); + err = tpm_flush_specific(tpm, get_unaligned_be32(ptr), + TPM_RT_KEY); if (err && err != TPM_KEY_OWNER_CONTROL) return err; } @@ -121,7 +123,7 @@ struct key_program *parse_and_check_keyprog(u8 *progdata) return result; } -int load_and_run_keyprog(void) +int load_and_run_keyprog(struct udevice *tpm) { char *cmd = NULL; u8 *binprog = NULL; @@ -144,7 +146,7 @@ int load_and_run_keyprog(void) if (!prog) return 1; - if (hre_run_program(prog->code, prog->code_size)) { + if (hre_run_program(tpm, prog->code, prog->code_size)) { free(prog); return 1; } diff --git a/board/gdsys/a38x/keyprogram.h b/board/gdsys/a38x/keyprogram.h index a4877c73a8..06889c67e4 100644 --- a/board/gdsys/a38x/keyprogram.h +++ b/board/gdsys/a38x/keyprogram.h @@ -7,7 +7,7 @@ #ifndef __KEYPROGRAM_H #define __KEYPROGRAM_H -int load_and_run_keyprog(void); -int flush_keys(void); +int load_and_run_keyprog(struct udevice *tpm); +int flush_keys(struct udevice *tpm); #endif /* __KEYPROGRAM_H */ diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 7e082dff05..6ac956caca 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -11,6 +11,7 @@ #endif #include +#include #include #include #include @@ -141,6 +142,19 @@ static int hre_err = HRE_E_OK; #define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10) #define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7)) +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + static const uint8_t vendor[] = "Guntermann & Drunck"; /** @@ -245,15 +259,15 @@ static u8 *get_image_location(void) * @param size pointer to the size * @return 0 on success, != 0 on error */ -static int get_tpm_nv_size(uint32_t index, uint32_t *size) +static int get_tpm_nv_size(struct udevice *tpm, uint32_t index, uint32_t *size) { uint32_t err; uint8_t info[72]; uint8_t *ptr; uint16_t v16; - err = tpm_get_capability(TPM_CAP_NV_INDEX, index, - info, sizeof(info)); + err = tpm_get_capability(tpm, TPM_CAP_NV_INDEX, index, + info, sizeof(info)); if (err) { printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n", index, err); @@ -281,8 +295,8 @@ static int get_tpm_nv_size(uint32_t index, uint32_t *size) * @param[out] handle the handle of the key iff found * @return 0 if key was found in TPM; != 0 if not. */ -static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], - uint32_t *handle) +static int find_key(struct udevice *tpm, const uint8_t auth[20], + const uint8_t pubkey_digest[20], uint32_t *handle) { uint16_t key_count; uint32_t key_handles[10]; @@ -294,7 +308,8 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], unsigned int i; /* fetch list of already loaded keys in the TPM */ - err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + err = tpm_get_capability(tpm, TPM_CAP_HANDLE, TPM_RT_KEY, buf, + sizeof(buf)); if (err) return -1; key_count = get_unaligned_be16(buf); @@ -305,7 +320,8 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], /* now search a(/ the) key which we can access with the given auth */ for (i = 0; i < key_count; ++i) { buf_len = sizeof(buf); - err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len); + err = tpm_get_pub_key_oiap(tpm, key_handles[i], auth, buf, + &buf_len); if (err && err != TPM_AUTHFAIL) return -1; if (err) @@ -323,18 +339,18 @@ static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20], * @brief read CCDM common data from TPM NV * @return 0 if CCDM common data was found and read, !=0 if something failed. */ -static int read_common_data(void) +static int read_common_data(struct udevice *tpm) { uint32_t size; uint32_t err; uint8_t buf[256]; sha1_context ctx; - if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) || + if (get_tpm_nv_size(tpm, NV_COMMON_DATA_INDEX, &size) || size < NV_COMMON_DATA_MIN_SIZE) return 1; - err = tpm_nv_read_value(NV_COMMON_DATA_INDEX, - buf, min(sizeof(buf), size)); + err = tpm_nv_read_value(tpm, NV_COMMON_DATA_INDEX, + buf, min(sizeof(buf), size)); if (err) { printf("tpm_nv_read_value() failed: %u\n", err); return 1; @@ -467,7 +483,8 @@ static struct h_reg *get_hreg(uint8_t spec) * The value of automatic registers (PCR register and fixed registers) is * loaded or computed on read access. */ -static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode) +static struct h_reg *access_hreg(struct udevice *tpm, uint8_t spec, + enum access_mode mode) { struct h_reg *result; @@ -484,13 +501,13 @@ static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode) if (mode & HREG_RD) { if (!result->valid) { if (IS_PCR_HREG(spec)) { - hre_tpm_err = tpm_pcr_read(HREG_IDX(spec), + hre_tpm_err = tpm_pcr_read(tpm, HREG_IDX(spec), result->digest, 20); result->valid = (hre_tpm_err == TPM_SUCCESS); } else if (IS_FIX_HREG(spec)) { switch (HREG_IDX(spec)) { case FIX_HREG_DEVICE_ID_HASH: - read_common_data(); + read_common_data(tpm); break; case FIX_HREG_SELF_HASH: ccdm_compute_self_hash(); @@ -566,18 +583,19 @@ static void *compute_extend(void *_dst, const void *_src, size_t n) return _dst; } -static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg, - const void *key, size_t key_size) +static int hre_op_loadkey(struct udevice *tpm, struct h_reg *src_reg, + struct h_reg *dst_reg, const void *key, + size_t key_size) { uint32_t parent_handle; uint32_t key_handle; if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid) return -1; - if (find_key(src_reg->digest, dst_reg->digest, &parent_handle)) + if (find_key(tpm, src_reg->digest, dst_reg->digest, &parent_handle)) return -1; - hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size, - src_reg->digest, &key_handle); + hre_tpm_err = tpm_load_key2_oiap(tpm, parent_handle, key, key_size, + src_reg->digest, &key_handle); if (hre_tpm_err) { hre_err = HRE_E_TPM_FAILURE; return -1; @@ -593,7 +611,8 @@ static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg, * @param[in,out] code_size (remaining) size of the code * @return new instruction pointer on success, NULL on error. */ -static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size) +static const uint8_t *hre_execute_op(struct udevice *tpm, const uint8_t **ip, + size_t *code_size) { bool dst_modified = false; uint32_t ins; @@ -624,10 +643,11 @@ static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size) if ((opcode & 0x80) && (data_size + 4) > *code_size) return NULL; - src_reg = access_hreg(src_spec, HREG_RD); + src_reg = access_hreg(tpm, src_spec, HREG_RD); if (hre_err || hre_tpm_err) return NULL; - dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR); + dst_reg = access_hreg(tpm, dst_spec, + (opcode & 0x40) ? HREG_RDWR : HREG_WR); if (hre_err || hre_tpm_err) return NULL; @@ -683,7 +703,7 @@ do_bin_func: dst_modified = true; break; case HRE_LOADKEY: - if (hre_op_loadkey(src_reg, dst_reg, data, data_size)) + if (hre_op_loadkey(tpm, src_reg, dst_reg, data, data_size)) return NULL; break; default: @@ -691,8 +711,8 @@ do_bin_func: } if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) { - hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest, - dst_reg->digest); + hre_tpm_err = tpm_extend(tpm, HREG_IDX(dst_spec), + dst_reg->digest, dst_reg->digest); if (hre_tpm_err) { hre_err = HRE_E_TPM_FAILURE; return NULL; @@ -715,7 +735,8 @@ end: * @param code_size size of the code (in bytes). * @return 0 on success, != 0 on failure. */ -static int hre_run_program(const uint8_t *code, size_t code_size) +static int hre_run_program(struct udevice *tpm, const uint8_t *code, + size_t code_size) { size_t code_left; const uint8_t *ip = code; @@ -724,7 +745,7 @@ static int hre_run_program(const uint8_t *code, size_t code_size) hre_tpm_err = 0; hre_err = HRE_E_OK; while (code_left > 0) - if (!hre_execute_op(&ip, &code_left)) + if (!hre_execute_op(tpm, &ip, &code_left)) return -1; return hre_err; @@ -929,26 +950,27 @@ static const uint8_t prg_stage1_prepare[] = { 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */ }; -static int first_stage_actions(void) +static int first_stage_actions(struct udevice *tpm) { int result = 0; struct key_program *sd_prg = NULL; puts("CCDM S1: start actions\n"); #ifndef CCDM_SECOND_STAGE - if (tpm_continue_self_test()) + if (tpm_continue_self_test(tpm)) goto failure; #else - tpm_continue_self_test(); + tpm_continue_self_test(tpm); #endif mdelay(37); - if (hre_run_program(prg_stage1_prepare, sizeof(prg_stage1_prepare))) + if (hre_run_program(tpm, prg_stage1_prepare, + sizeof(prg_stage1_prepare))) goto failure; sd_prg = load_sd_key_program(); if (sd_prg) { - if (hre_run_program(sd_prg->code, sd_prg->code_size)) + if (hre_run_program(tpm, sd_prg->code, sd_prg->code_size)) goto failure; puts("SD code run successfully\n"); } else { @@ -969,19 +991,22 @@ end: #ifdef CCDM_FIRST_STAGE static int first_stage_init(void) { - int res = 0; + struct udevice *tpm; + int ret; + puts("CCDM S1\n"); - if (tpm_init() || tpm_startup(TPM_ST_CLEAR)) + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR)) return 1; - res = first_stage_actions(); + ret = first_stage_actions(tpm); #ifndef CCDM_SECOND_STAGE - if (!res) { + if (!ret) { if (bl2_entry) (*bl2_entry)(); - res = 1; + ret = 1; } #endif - return res; + return ret; } #endif @@ -1021,24 +1046,28 @@ static int second_stage_init(void) char *mac_path = NULL; ulong image_addr; loff_t image_size; + struct udevice *tpm; uint32_t err; + int ret; printf("CCDM S2\n"); - if (tpm_init()) + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm)) return 1; - err = tpm_startup(TPM_ST_CLEAR); + err = tpm_startup(tpm, TPM_ST_CLEAR); if (err != TPM_INVALID_POSTINIT) did_first_stage_run = false; #ifdef CCDM_AUTO_FIRST_STAGE - if (!did_first_stage_run && first_stage_actions()) + if (!did_first_stage_run && first_stage_actions(tpm)) goto failure; #else if (!did_first_stage_run) goto failure; #endif - if (hre_run_program(prg_stage2_prepare, sizeof(prg_stage2_prepare))) + if (hre_run_program(tpm, prg_stage2_prepare, + sizeof(prg_stage2_prepare))) goto failure; /* run "prepboot" from env to get "mmcdev" set */ @@ -1083,12 +1112,12 @@ static int second_stage_init(void) } puts("CCDM image OK\n"); - hre_run_program(prg_stage2_success, sizeof(prg_stage2_success)); + hre_run_program(tpm, prg_stage2_success, sizeof(prg_stage2_success)); goto end; failure: result = 1; - hre_run_program(prg_stage_fail, sizeof(prg_stage_fail)); + hre_run_program(tpm, prg_stage_fail, sizeof(prg_stage_fail)); end: if (hmac_blob) free(hmac_blob); diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig index 993b055930..05938560ab 100644 --- a/board/ge/bx50v3/Kconfig +++ b/board/ge/bx50v3/Kconfig @@ -15,4 +15,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "ge_bx50v3" +source "board/ge/common/Kconfig" + endif diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 245852510f..079d302fbe 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -33,20 +33,9 @@ #include "../../../drivers/net/e1000.h" DECLARE_GLOBAL_DATA_PTR; -struct vpd_cache; - static int confidx = 3; /* Default to b850v3. */ static struct vpd_cache vpd; -#ifndef CONFIG_SYS_I2C_EEPROM_ADDR -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#endif - -#ifndef CONFIG_SYS_I2C_EEPROM_BUS -#define CONFIG_SYS_I2C_EEPROM_BUS 4 -#endif - #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS) @@ -569,6 +558,7 @@ int overwrite_console(void) #define VPD_MAC_ADDRESS_LENGTH 6 struct vpd_cache { + bool is_read; u8 product_id; u8 has; unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; @@ -578,11 +568,9 @@ struct vpd_cache { /* * Extracts MAC and product information from the VPD. */ -static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, +static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type, size_t size, u8 const *data) { - struct vpd_cache *vpd = (struct vpd_cache *)userdata; - if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && size >= 1) { vpd->product_id = data[0]; @@ -606,6 +594,11 @@ static void process_vpd(struct vpd_cache *vpd) int fec_index = -1; int i210_index = -1; + if (!vpd->is_read) { + printf("VPD wasn't read"); + return; + } + switch (vpd->product_id) { case VPD_PRODUCT_B450: env_set("confidx", "1"); @@ -631,35 +624,6 @@ static void process_vpd(struct vpd_cache *vpd) eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); } -static int read_vpd(uint eeprom_bus) -{ - int res; - int size = 1024; - uint8_t *data; - unsigned int current_i2c_bus = i2c_get_bus_num(); - - res = i2c_set_bus_num(eeprom_bus); - if (res < 0) - return res; - - data = (uint8_t *)malloc(size); - if (!data) - return -ENOMEM; - - res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size); - - if (res == 0) { - memset(&vpd, 0, sizeof(vpd)); - vpd_reader(size, data, &vpd, vpd_callback); - } - - free(data); - - i2c_set_bus_num(current_i2c_bus); - return res; -} - int board_eth_init(bd_t *bis) { setup_iomux_enet(); @@ -718,9 +682,10 @@ int board_init(void) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); - read_vpd(CONFIG_SYS_I2C_EEPROM_BUS); - - set_confidx(&vpd); + if (!read_vpd(&vpd, vpd_callback)) { + vpd.is_read = true; + set_confidx(&vpd); + } gpio_direction_output(SUS_S3_OUT, 1); gpio_direction_output(WIFI_EN, 1); diff --git a/board/ge/common/Kconfig b/board/ge/common/Kconfig new file mode 100644 index 0000000000..637b264954 --- /dev/null +++ b/board/ge/common/Kconfig @@ -0,0 +1,14 @@ +config SYS_VPD_EEPROM_I2C_ADDR + hex "I2C address of the EEPROM device used for VPD" + help + VPD = Vital Product Data + +config SYS_VPD_EEPROM_I2C_BUS + int "I2C bus of the EEPROM device used for VPD." + +config SYS_VPD_EEPROM_SIZE + int "Size in bytes of the EEPROM device used for VPD" + +config SYS_VPD_EEPROM_I2C_ADDR_LEN + int "Number of bytes to use for VPD EEPROM address" + default 1 diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c index c471583be8..12410d9b71 100644 --- a/board/ge/common/vpd_reader.c +++ b/board/ge/common/vpd_reader.c @@ -5,6 +5,7 @@ #include "vpd_reader.h" +#include #include #include @@ -105,9 +106,9 @@ static const size_t HEADER_BLOCK_ECC_LEN = 4; static const u8 ECC_BLOCK_ID = 0xFF; -int vpd_reader(size_t size, u8 *data, void *userdata, - int (*fn)(void *userdata, u8 id, u8 version, u8 type, - size_t size, u8 const *data)) +static int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata, + int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type, + size_t size, u8 const *data)) { if (size < HEADER_BLOCK_LEN || !data || !fn) return -EINVAL; @@ -194,3 +195,33 @@ int vpd_reader(size_t size, u8 *data, void *userdata, return ret; } } + +int read_vpd(struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, u8 id, u8 version, + u8 type, size_t size, u8 const *data)) +{ + static const size_t size = CONFIG_SYS_VPD_EEPROM_SIZE; + + int res; + u8 *data; + unsigned int current_i2c_bus = i2c_get_bus_num(); + + res = i2c_set_bus_num(CONFIG_SYS_VPD_EEPROM_I2C_BUS); + if (res < 0) + return res; + + data = malloc(size); + if (!data) + return -ENOMEM; + + res = i2c_read(CONFIG_SYS_VPD_EEPROM_I2C_ADDR, 0, + CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN, + data, size); + if (res == 0) + res = vpd_reader(size, data, cache, process_block); + + free(data); + + i2c_set_bus_num(current_i2c_bus); + return res; +} diff --git a/board/ge/common/vpd_reader.h b/board/ge/common/vpd_reader.h index e60acf3d07..3045b7e21e 100644 --- a/board/ge/common/vpd_reader.h +++ b/board/ge/common/vpd_reader.h @@ -5,12 +5,18 @@ #include "common.h" +struct vpd_cache; + /* - * Read VPD from given data, verify content, and call callback - * for each vital product data block. + * Read VPD from given data, verify content, call callback for each vital + * product data block. + * + * cache: structure used by process block to store VPD information + * process_block: callback called for each VPD data block * * Returns Non-zero on error. Negative numbers encode errno. */ -int vpd_reader(size_t size, u8 *data, void *userdata, - int (*fn)(void *userdata, u8 id, u8 version, u8 type, - size_t size, u8 const *data)); +int read_vpd(struct vpd_cache *cache, + int (*process_block)(struct vpd_cache *, + u8 id, u8 version, u8 type, + size_t size, u8 const *data)); diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig index 6dc3818cb7..bebb2fab01 100644 --- a/board/ge/mx53ppd/Kconfig +++ b/board/ge/mx53ppd/Kconfig @@ -13,4 +13,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "mx53ppd" +source "board/ge/common/Kconfig" + endif diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cf278e8f47..23bfe55541 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -40,13 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */ -#define VPD_EEPROM_BUS 2 - -/* Address of 24C08 EEPROM. */ -#define VPD_EEPROM_ADDR 0x50 -#define VPD_EEPROM_ADDR_LEN 1 - static u32 mx53_dram_size[2]; phys_size_t get_effective_memsize(void) @@ -297,10 +290,10 @@ struct vpd_cache { /* * Extracts MAC and product information from the VPD. */ -static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size, - u8 const *data) +static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version, + u8 type, size_t size, u8 const *data) { - struct vpd_cache *vpd = (struct vpd_cache *)userdata; + struct vpd_cache *vpd = userdata; if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && size >= 1) { @@ -328,35 +321,6 @@ static void process_vpd(struct vpd_cache *vpd) eth_env_set_enetaddr("ethaddr", vpd->mac1); } -static int read_vpd(uint eeprom_bus) -{ - struct vpd_cache vpd; - int res; - int size = 1024; - u8 *data; - unsigned int current_i2c_bus = i2c_get_bus_num(); - - res = i2c_set_bus_num(eeprom_bus); - if (res < 0) - return res; - - data = malloc(size); - if (!data) - return -ENOMEM; - - res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size); - if (res == 0) { - memset(&vpd, 0, sizeof(vpd)); - vpd_reader(size, data, &vpd, vpd_callback); - process_vpd(&vpd); - } - - free(data); - - i2c_set_bus_num(current_i2c_bus); - return res; -} - int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -389,8 +353,14 @@ int misc_init_r(void) int board_late_init(void) { int res; + struct vpd_cache vpd; - read_vpd(VPD_EEPROM_BUS); + memset(&vpd, 0, sizeof(vpd)); + res = read_vpd(&vpd, vpd_callback); + if (!res) + process_vpd(&vpd); + else + printf("Can't read VPD"); res = clock_1GHz(); if (res != 0) diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 73a7d8281c..dc0de620fc 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -69,13 +68,6 @@ static void enable_board_pin_mux(void) } #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#ifndef CONFIG_DM_SERIAL -struct serial_device *default_serial_console(void) -{ - return &eserial1_device; -} -#endif - #ifndef CONFIG_SKIP_LOWLEVEL_INIT void set_uart_mux_conf(void) { @@ -150,56 +142,3 @@ int board_late_init(void) return 0; } #endif - -#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \ - !defined(CONFIG_SPL_BUILD) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - } -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; - - writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - - return n; -} -#endif diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS index 0cc01c8321..622e5cb18e 100644 --- a/board/hisilicon/poplar/MAINTAINERS +++ b/board/hisilicon/poplar/MAINTAINERS @@ -1,5 +1,6 @@ Poplar BOARD M: Jorge Ramirez-Ortiz +M: Shawn Guo S: Maintained F: board/hisilicon/poplar F: include/configs/poplar.h diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index 9e8eac7838..8adc750962 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -35,6 +35,7 @@ static struct mm_region poplar_mem_map[] = { struct mm_region *mem_map = poplar_mem_map; +#if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct pl01x_serial_platdata serial_platdata = { .base = REG_BASE_UART0, .type = TYPE_PL010, @@ -45,6 +46,7 @@ U_BOOT_DEVICE(poplar_serial) = { .name = "serial_pl01x", .platdata = &serial_platdata, }; +#endif int checkboard(void) { diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a411d4e7f6..d547af4b05 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -208,4 +208,4 @@ void spi_cs_deactivate(struct spi_slave *slave) /* deactivate the spi_cs */ setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); } -#endif /* CONFIG_HARD_SPI */ +#endif diff --git a/board/imgtec/ci20/Kconfig b/board/imgtec/ci20/Kconfig new file mode 100644 index 0000000000..82bf65d64f --- /dev/null +++ b/board/imgtec/ci20/Kconfig @@ -0,0 +1,15 @@ +if TARGET_JZ4780_CI20 + +config SYS_BOARD + default "ci20" + +config SYS_VENDOR + default "imgtec" + +config SYS_CONFIG_NAME + default "ci20" + +config SYS_TEXT_BASE + default 0x80000000 + +endif diff --git a/board/imgtec/ci20/MAINTAINERS b/board/imgtec/ci20/MAINTAINERS new file mode 100644 index 0000000000..dca6bf3537 --- /dev/null +++ b/board/imgtec/ci20/MAINTAINERS @@ -0,0 +1,6 @@ +Creator CI20 BOARD +M: Ezequiel Garcia +S: Maintained +F: board/imgtec/ci20/ +F: include/configs/ci20.h +F: configs/ci20_mmc_defconfig diff --git a/board/imgtec/ci20/Makefile b/board/imgtec/ci20/Makefile new file mode 100644 index 0000000000..7843b46791 --- /dev/null +++ b/board/imgtec/ci20/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := ci20.o diff --git a/board/imgtec/ci20/README b/board/imgtec/ci20/README new file mode 100644 index 0000000000..07d89d7e2b --- /dev/null +++ b/board/imgtec/ci20/README @@ -0,0 +1,10 @@ +CI20 U-Boot + +Installation to an SD card: + Repartition your card with an MBR such that the first partition starts at an + offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image + to the card like so: + + dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1 + dd if=u-boot-dtb.img of=/dev/sdX obs=1K seek=14 + sync diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c new file mode 100644 index 0000000000..9811ef559f --- /dev/null +++ b/board/imgtec/ci20/ci20.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CI20 setup code + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ci20_otp { + u32 serial_number; + u32 date; + u8 manufacturer[2]; + u8 mac[6]; +} __packed; + +static void ci20_mux_mmc(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* setup MSC1 pins */ + writel(0x30f00000, gpio_regs + GPIO_PXINTC(4)); + writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4)); + writel(0x30f00000, gpio_regs + GPIO_PXPENC(4)); + jz4780_clk_ungate_mmc(); +} + +#ifndef CONFIG_SPL_BUILD + +static void ci20_mux_eth(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + +#ifdef CONFIG_NAND + /* setup pins (some already setup for NAND) */ + writel(0x04030000, gpio_regs + GPIO_PXINTC(0)); + writel(0x04030000, gpio_regs + GPIO_PXMASKC(0)); + writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x04030000, gpio_regs + GPIO_PXPENS(0)); +#else + /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */ + writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0)); + writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); + writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); +#endif +} + +static void ci20_mux_jtag(void) +{ +#ifdef CONFIG_JTAG + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* enable JTAG */ + writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); + writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0)); +#endif +} + +static void ci20_mux_nand(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* setup pins */ + writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0)); + writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0)); + writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); + writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); + writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); + + /* FRB0_N */ + jz47xx_gpio_direction_input(JZ_GPIO(0, 20)); + writel(20, gpio_regs + GPIO_PXPENS(0)); + + /* disable write protect */ + jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1); +} + +static void ci20_mux_uart(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + + /* UART0 */ + writel(0x9, gpio_regs + GPIO_PXINTC(5)); + writel(0x9, gpio_regs + GPIO_PXMASKC(5)); + writel(0x9, gpio_regs + GPIO_PXPAT1C(5)); + writel(0x9, gpio_regs + GPIO_PXPAT0C(5)); + writel(0x9, gpio_regs + GPIO_PXPENC(5)); + jz4780_clk_ungate_uart(0); + + /* UART 1 and 2 */ + jz4780_clk_ungate_uart(1); + jz4780_clk_ungate_uart(2); + +#ifndef CONFIG_JTAG + /* UART3 */ + writel(1 << 12, gpio_regs + GPIO_PXINTC(3)); + writel(1 << 12, gpio_regs + GPIO_PXMASKS(3)); + writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3)); + writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3)); + writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); + writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); + writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); + writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0)); + writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0)); + jz4780_clk_ungate_uart(3); +#endif + + /* UART4 */ + writel(0x100400, gpio_regs + GPIO_PXINTC(2)); + writel(0x100400, gpio_regs + GPIO_PXMASKC(2)); + writel(0x100400, gpio_regs + GPIO_PXPAT1S(2)); + writel(0x100400, gpio_regs + GPIO_PXPAT0C(2)); + writel(0x100400, gpio_regs + GPIO_PXPENC(2)); + jz4780_clk_ungate_uart(4); +} + +int board_early_init_f(void) +{ + ci20_mux_jtag(); + ci20_mux_uart(); + + ci20_mux_eth(); + ci20_mux_mmc(); + ci20_mux_nand(); + + /* SYS_POWER_IND high (LED blue, VBUS off) */ + jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0); + + /* LEDs off */ + jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0); + jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0); + jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0); + jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0); + + return 0; +} + +int misc_init_r(void) +{ + const u32 efuse_clk = jz4780_clk_get_efuse_clk(); + struct ci20_otp otp; + char manufacturer[3]; + + /* Read the board OTP data */ + jz4780_efuse_init(efuse_clk); + jz4780_efuse_read(0x18, 16, (u8 *)&otp); + + /* Set MAC address */ + if (!is_valid_ethaddr(otp.mac)) { + /* no MAC assigned, generate one from the unique chip ID */ + jz4780_efuse_read(0x8, 4, &otp.mac[0]); + jz4780_efuse_read(0x12, 2, &otp.mac[4]); + otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01; + } + eth_env_set_enetaddr("ethaddr", otp.mac); + + /* Put other board information into the environment */ + env_set_ulong("serial#", otp.serial_number); + env_set_ulong("board_date", otp.date); + manufacturer[0] = otp.manufacturer[0]; + manufacturer[1] = otp.manufacturer[1]; + manufacturer[2] = 0; + env_set("board_mfr", manufacturer); + + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + /* Enable clock */ + jz4780_clk_ungate_ethernet(); + + /* Enable power (PB25) */ + jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1); + + /* Reset (PF12) */ + mdelay(10); + jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0); + mdelay(10); + jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1); + mdelay(10); + + return dm9000_initialize(bis); +} +#endif /* CONFIG_DRIVER_DM9000 */ +#endif + +static u8 ci20_revision(void) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int val; + + jz47xx_gpio_direction_input(JZ_GPIO(2, 18)); + jz47xx_gpio_direction_input(JZ_GPIO(2, 19)); + + /* Enable pullups */ + writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2)); + + /* Read PC18/19 for version */ + val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) | + ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1); + + if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */ + return 1; + if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */ + return 2; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(0) + sdram_size(1); + return 0; +} + +/* U-Boot common routines */ +int checkboard(void) +{ + printf("Board: Creator CI20 (rev.%d)\n", ci20_revision()); + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#if defined(CONFIG_SPL_MMC_SUPPORT) +int board_mmc_init(bd_t *bd) +{ + ci20_mux_mmc(); + return jz_mmc_init((void __iomem *)MSC0_BASE); +} +#endif + +static const struct jz4780_ddr_config K4B2G0846Q_48_config = { + .timing = { + (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | + (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), + + (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) | + (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), + + (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | + (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | + (21 << DDRC_TIMING3_TRC_BIT), + + (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | + (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) | + (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), + + (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | + (4 << DDRC_TIMING5_TWDLAT_BIT), + + (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) | + (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), + }, + + /* PHY */ + /* Mode Register 0 */ + .mr0 = 0x420, +#ifdef SDRAM_DISABLE_DLL + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), +#else + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), +#endif + + .ptr0 = 0x002000d4, + .ptr1 = 0x02230d40, + .ptr2 = 0x04013880, + + .dtpr0 = 0x2a8f6690, + .dtpr1 = 0x00400860, + .dtpr2 = 0x10042a00, + + .pullup = 0x0b, + .pulldn = 0x0b, +}; + +static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = { + .timing = { + (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | + (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), + + (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) | + (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), + + (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | + (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | + (22 << DDRC_TIMING3_TRC_BIT), + + (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | + (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) | + (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), + + (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | + (4 << DDRC_TIMING5_TWDLAT_BIT), + + (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) | + (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), + }, + + /* PHY */ + /* Mode Register 0 */ + .mr0 = 0x420, +#ifdef SDRAM_DISABLE_DLL + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), +#else + .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), +#endif + + .ptr0 = 0x002000d4, + .ptr1 = 0x02d30d40, + .ptr2 = 0x04013880, + + .dtpr0 = 0x2c906690, + .dtpr1 = 0x005608a0, + .dtpr2 = 0x10042a00, + + .pullup = 0x0e, + .pulldn = 0x0e, +}; + +#if (CONFIG_SYS_MHZ != 1200) +#error No DDR configuration for CPU speed +#endif + +const struct jz4780_ddr_config *jz4780_get_ddr_config(void) +{ + const int board_revision = ci20_revision(); + + if (board_revision == 2) + return &K4B2G0846Q_48_config; + else /* Fall back to H5TQ2G83CFR RAM */ + return &H5TQ2G83CFR_48_config; +} +#endif diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 341678319a..8c0864bcdd 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -33,18 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_GPP_POL_LOW 0x0 #define BOARD_GPP_POL_MID 0x0 -/* IO expander on Marvell GP board includes e.g. fan enabling */ -struct marvell_io_exp { - u8 addr; - u8 val; -}; - -static struct marvell_io_exp io_exp[] = { - {6, 0xf9}, - {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */ - {6, 0xb9} -}; - static struct serdes_map board_serdes_map[] = { {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -78,7 +66,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_8GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ @@ -123,29 +111,9 @@ int board_early_init_f(void) int board_init(void) { - int i; - /* Address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - /* Init I2C IO expanders */ - for (i = 0; i < ARRAY_SIZE(io_exp); i++) { - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev); - if (ret) { - printf("Cannot find I2C: %d\n", ret); - return 0; - } - - ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1); - if (ret) { - printf("Failed to set IO expander via I2C\n"); - return -EIO; - } - } - return 0; } diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 691d38fdf2..144e6f68a4 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -164,61 +164,6 @@ void spl_board_prepare_for_linux(void) } #endif -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_USB_MUSB_OMAP2PLUS -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_ULPI, -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HOST) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_MUSB_GADGET) - .mode = MUSB_PERIPHERAL, -#else -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" -#endif - .config = &musb_config, - .power = 100, - .platform_ops = &omap2430_ops, - .board_data = &musb_board_data, -}; -#endif - -#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) -/* Call usb_stop() before starting the kernel */ -void show_boot_progress(int val) -{ - if (val == BOOTSTAGE_ID_RUN_OS) - usb_stop(); -} - -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED -}; - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} - -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); -} - -#endif /* CONFIG_USB_EHCI_HCD */ -#endif /* !DM_USB*/ /* * Routine: misc_init_r * Description: Configure board specific parts @@ -227,12 +172,6 @@ int misc_init_r(void) { twl4030_power_init(); omap_die_id_display(); - -#if !CONFIG_IS_ENABLED(DM_USB) -#ifdef CONFIG_USB_MUSB_OMAP2PLUS - musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); -#endif -#endif return 0; } diff --git a/board/mediatek/mt7623/Kconfig b/board/mediatek/mt7623/Kconfig new file mode 100644 index 0000000000..a8c670e71f --- /dev/null +++ b/board/mediatek/mt7623/Kconfig @@ -0,0 +1,13 @@ +if TARGET_MT7623 + +config SYS_BOARD + default "mt7623" + +config SYS_CONFIG_NAME + default "mt7623" + +config MTK_BROM_HEADER_INFO + string + default "lk=1" + +endif diff --git a/board/mediatek/mt7623/MAINTAINERS b/board/mediatek/mt7623/MAINTAINERS new file mode 100644 index 0000000000..eeb0375d70 --- /dev/null +++ b/board/mediatek/mt7623/MAINTAINERS @@ -0,0 +1,7 @@ +MT7623 +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: board/mediatek/mt7623 +F: include/configs/mt7623.h +F: configs/mt7623n_bpir2_defconfig diff --git a/board/mediatek/mt7623/Makefile b/board/mediatek/mt7623/Makefile new file mode 100644 index 0000000000..2b42071c47 --- /dev/null +++ b/board/mediatek/mt7623/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7623_rfb.o diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c new file mode 100644 index 0000000000..08468b50ea --- /dev/null +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} diff --git a/board/mediatek/mt7629/Kconfig b/board/mediatek/mt7629/Kconfig new file mode 100644 index 0000000000..6055164b52 --- /dev/null +++ b/board/mediatek/mt7629/Kconfig @@ -0,0 +1,17 @@ +if TARGET_MT7629 + +config SYS_BOARD + default "mt7629" + +config SYS_CONFIG_NAME + default "mt7629" + +config MTK_SPL_PAD_SIZE + hex + default 0x10000 + +config MTK_BROM_HEADER_INFO + string + default "media=nor" + +endif diff --git a/board/mediatek/mt7629/MAINTAINERS b/board/mediatek/mt7629/MAINTAINERS new file mode 100644 index 0000000000..424f115167 --- /dev/null +++ b/board/mediatek/mt7629/MAINTAINERS @@ -0,0 +1,7 @@ +MT7629 +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: board/mediatek/mt7629 +F: include/configs/mt7629.h +F: configs/mt7629_rfb_defconfig diff --git a/board/mediatek/mt7629/Makefile b/board/mediatek/mt7629/Makefile new file mode 100644 index 0000000000..83ccbba8c4 --- /dev/null +++ b/board/mediatek/mt7629/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7629_rfb.o diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c new file mode 100644 index 0000000000..08468b50ea --- /dev/null +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig new file mode 100644 index 0000000000..e1199808d5 --- /dev/null +++ b/board/mscc/luton/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +if SOC_LUTON + +config SYS_VENDOR + default "mscc" + +config SYS_BOARD + default "luton" + +config SYS_CONFIG_NAME + default "luton" + +endif diff --git a/board/mscc/luton/Makefile b/board/mscc/luton/Makefile new file mode 100644 index 0000000000..b27f7c7739 --- /dev/null +++ b/board/mscc/luton/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +obj-$(CONFIG_SOC_LUTON) := luton.o diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c new file mode 100644 index 0000000000..41fc6d56a7 --- /dev/null +++ b/board/mscc/luton/luton.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include + +#define MSCC_GPIO_ALT0 0x88 +#define MSCC_GPIO_ALT1 0x8C + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ + /* too early for the pinctrl driver, so configure the UART pins here */ + setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31)); +} + +int board_early_init_r(void) +{ + /* Prepare SPI controller to be used in master mode */ + writel(0, BASE_CFG + ICPU_SW_MODE); + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + return 0; +} diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig new file mode 100644 index 0000000000..9ddc0880b1 --- /dev/null +++ b/board/mscc/ocelot/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +config SYS_VENDOR + default "mscc" + +if SOC_OCELOT + +config SYS_BOARD + default "ocelot" + +config SYS_CONFIG_NAME + default "ocelot" + +endif diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile new file mode 100644 index 0000000000..9f28c81268 --- /dev/null +++ b/board/mscc/ocelot/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +obj-$(CONFIG_SOC_OCELOT) := ocelot.o + diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c new file mode 100644 index 0000000000..d521a61957 --- /dev/null +++ b/board/mscc/ocelot/ocelot.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MSCC_GPIO_ALT0 0x54 +#define MSCC_GPIO_ALT1 0x58 + +void external_cs_manage(struct udevice *dev, bool enable) +{ + u32 cs = spi_chip_select(dev); + /* IF_SI0_OWNER, select the owner of the SI interface + * Encoding: 0: SI Slave + * 1: SI Boot Master + * 2: SI Master Controller + */ + if (!enable) { + writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); + } else { + writel(0, BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); + } +} + +void board_debug_uart_init(void) +{ + /* too early for the pinctrl driver, so configure the UART pins here */ + setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7)); + clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7)); +} + +int board_early_init_r(void) +{ + /* Prepare SPI controller to be used in master mode */ + writel(0, BASE_CFG + ICPU_SW_MODE); + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, + ICPU_GENERAL_CTRL_IF_SI_OWNER_M, + ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + return 0; +} diff --git a/board/qualcomm/dragonboard820c/MAINTAINERS b/board/qualcomm/dragonboard820c/MAINTAINERS index 56c997e1f9..a157033bf0 100644 --- a/board/qualcomm/dragonboard820c/MAINTAINERS +++ b/board/qualcomm/dragonboard820c/MAINTAINERS @@ -1,5 +1,5 @@ DRAGONBOARD820C BOARD -M: Jorge Ramirez-Ortiz +M: Jorge Ramirez-Ortiz S: Maintained F: board/qualcomm/dragonboard820c/ F: include/configs/dragonboard820c.h diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 649127c5bf..153a1fdcb7 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -68,14 +68,7 @@ struct msg_get_clock_rate { #endif /* - * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ - * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 - * http://git.drogon.net/?p=wiringPi;a=blob;f=wiringPi/wiringPi.c;h=503151f61014418b9c42f4476a6086f75cd4e64b;hb=refs/heads/master#l922 - * - * In http://lists.denx.de/pipermail/u-boot/2016-January/243752.html - * ("[U-Boot] [PATCH] rpi: fix up Model B entries") Dom Cobley at the RPi - * Foundation stated that the following source was accurate: - * https://github.com/AndrewFromMelbourne/raspberry_pi_revision + * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md */ struct rpi_model { const char *name; @@ -145,6 +138,11 @@ static const struct rpi_model rpi_models_new_scheme[] = { DTB_DIR "bcm2837-rpi-3-b-plus.dtb", true, }, + [0xE] = { + "3 Model A+", + DTB_DIR "bcm2837-rpi-3-a-plus.dtb", + false, + }, }; static const struct rpi_model rpi_models_old_scheme[] = { diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 8b15267d7b..8f0247e046 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -31,7 +31,6 @@ void s_init(void) { } -#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ #define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ @@ -100,3 +99,25 @@ void reset_cpu(ulong addr) writel(RST_CODE, RST_CA57RESCNT); #endif } + +#ifdef CONFIG_MULTI_DTB_FIT +int board_fit_config_name_match(const char *name) +{ + /* PRR driver is not available yet */ + u32 cpu_type = rmobile_get_cpu_type(); + + if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && + !strcmp(name, "r8a7795-salvator-x-u-boot")) + return 0; + + if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && + !strcmp(name, "r8a7796-salvator-x-u-boot")) + return 0; + + if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && + !strcmp(name, "r8a77965-salvator-x-u-boot")) + return 0; + + return -1; +} +#endif diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 63550af1f0..81d6f8f6f2 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -30,8 +30,6 @@ void s_init(void) { } -#define GSX_MSTP112 BIT(12) /* 3DG */ -#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ #define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ @@ -84,3 +82,21 @@ int dram_init_banksize(void) return 0; } + +#ifdef CONFIG_MULTI_DTB_FIT +int board_fit_config_name_match(const char *name) +{ + /* PRR driver is not available yet */ + u32 cpu_type = rmobile_get_cpu_type(); + + if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && + !strcmp(name, "r8a7795-h3ulcb-u-boot")) + return 0; + + if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && + !strcmp(name, "r8a7796-m3ulcb-u-boot")) + return 0; + + return -1; +} +#endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index c4b6baedf0..6fd26a3a91 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -306,14 +306,16 @@ int checkboard(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - stdio_print_current_devices(); + struct udevice *dev; + int ret; - if (cros_ec_get_error()) { + stdio_print_current_devices(); + ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); + if (ret && ret != -ENODEV) { /* Force console on */ gd->flags &= ~GD_FLG_SILENT; - printf("cros-ec communications failure %d\n", - cros_ec_get_error()); + printf("cros-ec communications failure %d\n", ret); puts("\nPlease reset with Power+Refresh\n\n"); panic("Cannot init cros-ec device"); return -1; diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index a28fc9f36c..9b09404294 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -247,25 +247,28 @@ sudo /path/to/u-boot -D DHCP .... -set autoload no -set ethact eth1 +setenv autoload no +setenv ethrotate no +setenv ethact eth1 dhcp PING .... -set autoload no -set ethact eth1 +setenv autoload no +setenv ethrotate no +setenv ethact eth1 dhcp ping $gatewayip TFTP .... -set autoload no -set ethact eth1 +setenv autoload no +setenv ethrotate no +setenv ethact eth1 dhcp -set serverip WWW.XXX.YYY.ZZZ +setenv serverip WWW.XXX.YYY.ZZZ tftpboot u-boot.bin The bridge also supports (to a lesser extent) the localhost interface, 'lo'. @@ -287,7 +290,8 @@ operation being tested on the lo interface. TFTP .... -set ethact eth5 +setenv ethrotate no +setenv ethact eth5 tftpboot u-boot.bin @@ -418,7 +422,19 @@ coverage in U-Boot is limited, as we need to work to improve it. Note that many of these tests are implemented as commands which you can run natively on your board if desired (and enabled). -It would be useful to have a central script to run all of these. +To run all tests use "make check". + + +Memory Map +---------- + +Sandbox has its own emulated memory starting at 0. Here are some of the things +that are mapped into that memory: + + 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree + e000 CONFIG_BLOBLIST_ADDR Blob list + 10000 CONFIG_MALLOC_F_ADDR Early memory allocation + -- Simon Glass diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 0e87674826..397e7561d4 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -59,12 +59,15 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - if (cros_ec_get_error()) { + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); + if (ret && ret != -ENODEV) { /* Force console on */ gd->flags &= ~GD_FLG_SILENT; - printf("cros-ec communications failure %d\n", - cros_ec_get_error()); + printf("cros-ec communications failure %d\n", ret); puts("\nPlease reset with Power+Refresh\n\n"); panic("Cannot init cros-ec device"); return -1; diff --git a/board/seeed/linkit-smart-7688/board.c b/board/seeed/linkit-smart-7688/board.c index a28abc00b8..d3d3d50c2c 100644 --- a/board/seeed/linkit-smart-7688/board.c +++ b/board/seeed/linkit-smart-7688/board.c @@ -6,12 +6,15 @@ #include #include -#define MT76XX_GPIO1_MODE 0xb0000060 +#define MT76XX_GPIO1_MODE 0x10000060 void board_debug_uart_init(void) { + void __iomem *gpio_mode; + /* Select UART2 mode instead of GPIO mode (default) */ - clrbits_le32((void __iomem *)MT76XX_GPIO1_MODE, GENMASK(27, 26)); + gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100); + clrbits_le32(gpio_mode, GENMASK(27, 26)); } int board_early_init_f(void) diff --git a/board/solidrun/clearfog/MAINTAINERS b/board/solidrun/clearfog/MAINTAINERS index 298e5011c7..6646d96206 100644 --- a/board/solidrun/clearfog/MAINTAINERS +++ b/board/solidrun/clearfog/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/soldrun/clearfog/ F: include/configs/clearfog.h F: configs/clearfog_defconfig +F: configs/clearfog_gt_8k_defconfig diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 4e1386c8a2..1742aa8921 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -65,7 +65,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1600K, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ MV_DDR_DIE_CAP_4GBIT, /* mem_size */ - DDR_FREQ_800, /* frequency */ + MV_DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_DEFAULT} }, /* timing */ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 2f95976445..9b6e0c4c21 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -149,6 +149,11 @@ S: Maintained F: configs/Bananapi_m2m_defconfig F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts +BANANAPI M2 ZERO BOARD +M: Icenowy Zheng +S: Maintained +F: configs/bananapi_m2_zero_defconfig + BANANAPI M64 M: Jagan Teki S: Maintained @@ -330,6 +335,11 @@ S: Maintained F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +ORANGEPI LITE2 BOARD +M: Jagan Teki +S: Maintained +F: configs/orangepi_lite2_defconfig + ORANGEPI ONE PLUS BOARD M: Jagan Teki S: Maintained @@ -370,10 +380,16 @@ M: Hauke Mehrtens S: Maintained F: configs/orangepi_r1_defconfig +PINEBOOK BOARD: +M: Vasily Khoruzhick +S: Maintained +F: configs/pinebook_defconfig + PINE64 BOARDS M: Andre Przywara S: Maintained F: configs/pine64_plus_defconfig +F: configs/pine64-lts_defconfig PINE H64 BOARD M: Icenowy Zheng diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64 index bba2e01b60..258921af22 100644 --- a/board/sunxi/README.sunxi64 +++ b/board/sunxi/README.sunxi64 @@ -12,8 +12,13 @@ file describes how to make full use of the 64-bit capabilities. Quick Start / Overview ====================== - Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below) + $ cd /src/arm-trusted-firmware + $ make PLAT=sun50i_a64 DEBUG=1 bl31 - Build U-Boot (see "SPL/U-Boot" below) + $ export BL31=/path/to/bl31.bin + $ make pine64_plus_defconfig && make -j5 - Transfer to an uSD card (see "microSD card" below) + $ dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1 - Boot and enjoy! Building the firmware @@ -29,14 +34,18 @@ to build it first. ARM Trusted Firmware (ATF) ---------------------------- -Checkout the "allwinner" branch from the github repository [1] and build it: +Checkout the latest master branch from the official ATF repository [1] and +build it: $ export CROSS_COMPILE=aarch64-linux-gnu- -$ make PLAT=sun50iw1p1 DEBUG=1 bl31 -The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the +$ make PLAT=sun50i_a64 DEBUG=1 bl31 +The resulting binary is build/sun50i_a64/debug/bl31.bin. Either put the location of this file into the BL31 environment variable or copy this to the root of your U-Boot build directory (or create a symbolic link). -$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin +$ export BL31=/src/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin (adjust the actual path accordingly) +The platform target "sun50i_a64" covers all boards with either an Allwinner +A64 or H5 SoC (since they are very similar). For boards with an Allwinner H6 +SoC use "sun50i_h6". If you run into size issues with the resulting U-Boot image file, it might help to use a release build, by using "DEBUG=0" when building bl31.bin. @@ -59,7 +68,8 @@ $ make pine64_plus_defconfig $ make This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb, -which contains the rest of the firmware. +which contains the rest of the firmware. u-boot-sunxi-with-spl.bin joins those +two components in one convenient image file. Boot process @@ -91,6 +101,9 @@ by using the USB-OTG interface and a host port on another computer. As the FEL mode is controlled by the boot ROM, it expects to be running in AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the feature is disabled in the configuration at the moment. +The repository in [3] contains FEL capable SPL binaries, built using an +off-tree branch to generate 32-bit ARM code (along with instructions +how to re-create them). microSD card ------------ @@ -165,6 +178,6 @@ Then write this image to a microSD card, replacing /dev/sdx with the right device file (see above): $ dd if=firmware.img of=/dev/sdx bs=8k seek=1 -[1] https://github.com/apritzel/arm-trusted-firmware.git +[1] https://github.com/ARM-software/arm-trusted-firmware.git [2] git://github.com/linux-sunxi/sunxi-tools.git [3] https://github.com/apritzel/pine64/ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b196d48674..f022f365e9 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -28,7 +28,7 @@ #endif #include #include -#include +#include #include #include #include @@ -168,10 +168,16 @@ void i2c_init_board(void) #endif #ifdef CONFIG_R_I2C_ENABLE +#ifdef CONFIG_MACH_SUN50I + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif +#endif } #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) @@ -657,7 +663,7 @@ int g_dnl_board_usb_cable_connected(void) struct phy phy; int ret; - ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev); + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); if (ret) { pr_err("%s: Cannot find USB device\n", __func__); return ret; diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index c95f7af7a7..ffa7c154b5 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -109,3 +109,11 @@ void smp_kick_all_cpus(void) writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); } #endif + +int checkboard(void) +{ + printf("Board: ARC Software Development Platform AXS%s\n", + is_isa_arcv2() ? "103" : "101"); + + return 0; +}; diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index b5ec7f17ec..c0770b58c1 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -7,10 +7,46 @@ #include #include +#include + DECLARE_GLOBAL_DATA_PTR; -#define ARC_PERIPHERAL_BASE 0xF0000000 -#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0x10000) +#define ARC_PERIPHERAL_BASE 0xF0000000 + +#define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84) +#define CGU_ARC_FMEAS_ARC_START BIT(31) +#define CGU_ARC_FMEAS_ARC_DONE BIT(30) +#define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0) +#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0 +#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15 + +#define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000) + +int mach_cpu_init(void) +{ + int rcnt, fcnt; + u32 data; + + /* Start frequency measurement */ + writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC); + + /* Poll DONE bit */ + do { + data = readl(CGU_ARC_FMEAS_ARC); + } while (!(data & CGU_ARC_FMEAS_ARC_DONE)); + + /* Amount of reference 100 MHz clocks */ + rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) & + CGU_ARC_FMEAS_ARC_CNT_MASK); + + /* Amount of CPU clocks */ + fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) & + CGU_ARC_FMEAS_ARC_CNT_MASK); + + gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000; + + return 0; +} int board_mmc_init(bd_t *bis) { @@ -24,7 +60,7 @@ int board_mmc_init(bd_t *bis) memset(host, 0, sizeof(struct dwmci_host)); host->name = "Synopsys Mobile storage"; - host->ioaddr = (void *)SDIO_BASE; + host->ioaddr = SDIO_BASE; host->buswidth = 4; host->dev_index = 0; host->bus_hz = 50000000; @@ -42,31 +78,32 @@ int board_mmc_getcd(struct mmc *mmc) } #define CREG_BASE 0xF0001000 -#define CREG_BOOT_OFFSET 0 -#define CREG_BOOT_WP_OFFSET 8 +#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0) +#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0) +#define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8) -#define CGU_BASE 0xF0000000 -#define CGU_IP_SW_RESET 0x0FF0 +/* Bits in CREG_BOOT register */ +#define CREG_BOOT_WP_BIT BIT(8) void reset_cpu(ulong addr) { - writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET)); + writel(1, CREG_IP_SW_RESET); while (1) ; /* loop forever till reset */ } static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET)); + u32 creg_boot = readl(CREG_BOOT); if (!strcmp(argv[1], "unlock")) - creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET); + creg_boot &= ~CREG_BOOT_WP_BIT; else if (!strcmp(argv[1], "lock")) - creg_boot |= BIT(CREG_BOOT_WP_OFFSET); + creg_boot |= CREG_BOOT_WP_BIT; else return CMD_RET_USAGE; - writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET)); + writel(creg_boot, CREG_BOOT); return CMD_RET_SUCCESS; } @@ -97,3 +134,12 @@ U_BOOT_CMD( "rom unlock - Unlock non-volatile memory for writing\n" "emsdp rom lock - Lock non-volatile memory to prevent writing\n" ); + +int checkboard(void) +{ + int version = readl(CREG_IP_VERSION); + + printf("Board: ARC EM Software Development Platform v%d.%d\n", + (version >> 16) & 0xff, version & 0xff); + return 0; +}; diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index b6aefdbe6d..8a2c201477 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -1054,10 +1054,8 @@ int board_mmc_init(bd_t *bis) return 0; } -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) +int checkboard(void) { - printf("CPU: ARC HS38 v2.1c\n"); + puts("Board: Synopsys ARC HS Development Kit\n"); return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ +}; diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index f8838fb3ce..8424e09bd3 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -189,13 +189,3 @@ int checkboard(void) puts("Board: Synopsys IoT Development Kit\n"); return 0; }; - -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ - char mhz[8]; - - printf("CPU: ARC EM9D at %s MHz\n", strmhz(mhz, gd->cpu_clk)); - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 13845251af..d67f94ad47 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -70,8 +70,9 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; void do_board_detect(void) { enable_i2c0_pin_mux(); +#ifndef CONFIG_DM_I2C i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - +#endif if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS)) printf("ti_i2c_eeprom_init failed\n"); @@ -328,8 +329,14 @@ static void scale_vcores_bone(int freq) if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) return; +#ifndef CONFIG_DM_I2C if (i2c_probe(TPS65217_CHIP_PM)) return; +#else + if (power_tps65217_init(0)) + return; +#endif + /* * On Beaglebone White we need to ensure we have AC power @@ -421,9 +428,13 @@ void scale_vcores_generic(int freq) * 1.10V. For MPU voltage we need to switch based on * the frequency we are running at. */ +#ifndef CONFIG_DM_I2C if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) return; - +#else + if (power_tps65910_init(0)) + return; +#endif /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. @@ -451,8 +462,10 @@ void gpi2c_init(void) if (first_time) { enable_i2c0_pin_mux(); +#ifndef CONFIG_DM_I2C i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +#endif first_time = false; } } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 41333f93f4..04f4b8e693 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -329,12 +329,23 @@ static unsigned short detect_daughter_board_profile(void) { unsigned short val; +#ifndef CONFIG_DM_I2C if (i2c_probe(I2C_CPLD_ADDR)) return PROFILE_NONE; if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) return PROFILE_NONE; +#else + struct udevice *dev = NULL; + int rc; + rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev); + if (rc) + return PROFILE_NONE; + rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2); + if (rc) + return PROFILE_NONE; +#endif return (1 << (val & PROFILE_MASK)); } diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 2a59b06035..536c5b88ed 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -43,6 +43,8 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_TI_I2C_BOARD_DETECT void do_board_detect(void) { + /* Ensure I2C is initialized for EEPROM access*/ + gpi2c_init(); if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS)) printf("ti_i2c_eeprom_init failed\n"); @@ -386,8 +388,13 @@ void scale_vcores_generic(u32 m) { int mpu_vdd, ddr_volt; +#ifndef CONFIG_DM_I2C if (i2c_probe(TPS65218_CHIP_PM)) return; +#else + if (power_tps65218_init(0)) + return; +#endif switch (m) { case 1000: @@ -439,8 +446,13 @@ void scale_vcores_idk(u32 m) { int mpu_vdd; +#ifndef CONFIG_DM_I2C if (i2c_probe(TPS62362_I2C_ADDR)) return; +#else + if (power_tps62362_init(0)) + return; +#endif switch (m) { case 1000: @@ -462,14 +474,12 @@ void scale_vcores_idk(u32 m) puts("Unknown MPU clock, not scaling\n"); return; } - /* Set VDD_MPU voltage */ if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { printf("%s failure\n", __func__); return; } } - void gpi2c_init(void) { /* When needed to be invoked prior to BSS initialization */ @@ -477,8 +487,10 @@ void gpi2c_init(void) if (first_time) { enable_i2c0_pin_mux(); +#ifndef CONFIG_DM_I2C i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +#endif first_time = false; } } @@ -614,20 +626,32 @@ void sdram_init(void) /* setup board specific PMIC */ int power_init_board(void) { - struct pmic *p; - + int rc; +#ifndef CONFIG_DM_I2C + struct pmic *p = NULL; +#endif if (board_is_idk()) { - power_tps62362_init(I2C_PMIC); + rc = power_tps62362_init(0); + if (rc) + goto done; +#ifndef CONFIG_DM_I2C p = pmic_get("TPS62362"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS62362\n"); + if (!p || pmic_probe(p)) + goto done; +#endif + puts("PMIC: TPS62362\n"); } else { - power_tps65218_init(I2C_PMIC); + rc = power_tps65218_init(0); + if (rc) + goto done; +#ifndef CONFIG_DM_I2C p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS65218\n"); + if (!p || pmic_probe(p)) + goto done; +#endif + puts("PMIC: TPS65218\n"); } - +done: return 0; } @@ -681,6 +705,19 @@ int board_init(void) } #ifdef CONFIG_BOARD_LATE_INIT +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) +static int device_okay(const char *path) +{ + int node; + + node = fdt_path_offset(gd->fdt_blob, path); + if (node < 0) + return 0; + + return fdtdec_get_is_enabled(gd->fdt_blob, node); +} +#endif + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -693,10 +730,18 @@ int board_late_init(void) if (get_device_type() == HS_DEVICE) env_set("boot_fit", "1"); #endif + +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) + if (device_okay("/ocp/omap_dwc3@48380000")) + enable_usb_clocks(0); + if (device_okay("/ocp/omap_dwc3@483c0000")) + enable_usb_clocks(1); +#endif return 0; } #endif +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) #ifdef CONFIG_USB_DWC3 static struct dwc3_device usb_otg_ss1 = { .maximum_speed = USB_SPEED_HIGH, @@ -799,6 +844,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ +#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ #ifdef CONFIG_DRIVER_TI_CPSW diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 177a3246c3..7063345dcc 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -623,7 +623,7 @@ void am57x_idk_lcd_detect(void) { int r = -ENODEV; char *idk_lcd = "no"; - uint8_t buf = 0; + struct udevice *dev; /* Only valid for IDKs */ if (board_is_x15() || board_is_am572x_evm()) @@ -633,32 +633,29 @@ void am57x_idk_lcd_detect(void) if (board_is_am571x_idk() && !am571x_idk_needs_lcd()) goto out; - r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS); - if (r) { - printf("%s: Failed to set bus address to %d: %d\n", - __func__, OSD_TS_FT_BUS_ADDRESS, r); - goto out; - } - r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS); + r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS, + OSD_TS_FT_CHIP_ADDRESS, 1, &dev); if (r) { + printf("%s: Failed to get I2C device %d/%d (ret %d)\n", + __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, + r); /* AM572x IDK has no explicit settings for optional LCD kit */ - if (board_is_am571x_idk()) { + if (board_is_am571x_idk()) printf("%s: Touch screen detect failed: %d!\n", __func__, r); - } goto out; } /* Read FT ID */ - r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1); - if (r) { + r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID); + if (r < 0) { printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n", __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, r); goto out; } - switch (buf) { + switch (r) { case OSD_TS_FT_ID_5606: idk_lcd = "osd101t2045"; break; @@ -667,7 +664,7 @@ void am57x_idk_lcd_detect(void) break; default: printf("%s: Unidentifed Touch screen ID 0x%02x\n", - __func__, buf); + __func__, r); /* we will let default be "no lcd" */ } out: @@ -675,6 +672,19 @@ out: return; } +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) +static int device_okay(const char *path) +{ + int node; + + node = fdt_path_offset(gd->fdt_blob, path); + if (node < 0) + return 0; + + return fdtdec_get_is_enabled(gd->fdt_blob, node); +} +#endif + int board_late_init(void) { setup_board_eeprom_env(); @@ -714,6 +724,12 @@ int board_late_init(void) board_ti_set_ethaddr(2); #endif +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) + if (device_okay("/ocp/omap_dwc3_1@48880000")) + enable_usb_clocks(0); + if (device_okay("/ocp/omap_dwc3_2@488c0000")) + enable_usb_clocks(1); +#endif return 0; } @@ -864,93 +880,6 @@ int spl_start_uboot(void) } #endif -#ifdef CONFIG_USB_DWC3 -static struct dwc3_device usb_otg_ss2 = { - .maximum_speed = USB_SPEED_HIGH, - .base = DRA7_USB_OTG_SS2_BASE, - .tx_fifo_resize = false, - .index = 1, -}; - -static struct dwc3_omap_device usb_otg_ss2_glue = { - .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 1, -}; - -static struct ti_usb_phy_device usb_phy2_device = { - .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, - .index = 1, -}; - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif /* CONFIG_USB_DWC3 */ - -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) -int board_usb_init(int index, enum usb_init_type init) -{ - enable_usb_clocks(index); - switch (index) { - case 0: - if (init == USB_INIT_DEVICE) { - printf("port %d can't be used as device\n", index); - disable_usb_clocks(index); - return -EINVAL; - } - break; - case 1: - if (init == USB_INIT_DEVICE) { -#ifdef CONFIG_USB_DWC3 - usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); -#endif - } else { - printf("port %d can't be used as host\n", index); - disable_usb_clocks(index); - return -EINVAL; - } - - break; - default: - printf("Invalid Controller Index\n"); - } - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ -#ifdef CONFIG_USB_DWC3 - switch (index) { - case 0: - case 1: - if (init == USB_INIT_DEVICE) { - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); - } - break; - default: - printf("Invalid Controller Index\n"); - } -#endif - disable_usb_clocks(index); - return 0; -} -#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ - #ifdef CONFIG_DRIVER_TI_CPSW /* Delay value to add to calibrated value */ diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 591600483e..d4b36dbb42 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -12,6 +12,14 @@ config TARGET_AM654_A53_EVM select ARM64 select SOC_K3_AM6 +config TARGET_AM654_R5_EVM + bool "TI K3 based AM654 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select SOC_K3_AM6 + select K3_AM654_DDRSS + imply SYS_K3_SPL_ATF + endchoice if TARGET_AM654_A53_EVM @@ -26,3 +34,19 @@ config SYS_CONFIG_NAME default "am65x_evm" endif + +if TARGET_AM654_R5_EVM + +config SYS_BOARD + default "am65x" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am65x_evm" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/am65x/MAINTAINERS b/board/ti/am65x/MAINTAINERS index ca1ce58f72..7c52e7599e 100644 --- a/board/ti/am65x/MAINTAINERS +++ b/board/ti/am65x/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/ti/am65x/ F: include/configs/am65x_evm.h F: configs/am65x_evm_a53_defconfig +F: configs/am65x_evm_r5_defconfig diff --git a/board/ti/am65x/README b/board/ti/am65x/README index e7f4ff6578..0b82bd557b 100644 --- a/board/ti/am65x/README +++ b/board/ti/am65x/README @@ -37,13 +37,13 @@ instead use Flacon boot flow to reduce boot time. | +--------+ | | | | : | | | | +--------+ | +-----------+ | | -| | *rom* |----------|-->| Reset rls | | | +| | *ROM* |----------|-->| Reset rls | | | | +--------+ | +-----------+ | | | | | | : | | -| | rom | | : | | +| | ROM | | : | | | |services| | : | | | | | | +-------------+ | | -| | | | | *R5 rom* | | | +| | | | | *R5 ROM* | | | | | | | +-------------+ | | | | |<---------|---|Load and auth| | | | | | | | tiboot3.bin | | | @@ -52,17 +52,25 @@ instead use Flacon boot flow to reduce boot time. | | | | : | | | | | | : | | | | | | +-------------+ | | -| | Start | | | *R5 SPL* | | | -| | System | | +-------------+ | | -| |Firmware|<---------|---|Load and auth| | | -| +--------+ | | sysfw bin | | | -| : | +-------------+ | | -| +---------+ | | DDR | | | -| | *SYSFW* | | | config | | | -| +---------+ | +-------------+ | | -| | |<--------|---| Load | | | -| | | | | tispl.bin | | | +| | | | | *R5 SPL* | | | +| | | | +-------------+ | | +| | | | | Load | | | +| | | | | sysfw.itb | | | +| | Start | | +-------------+ | | +| | System |<---------|---| Start | | | +| |Firmware| | | SYSFW | | | +| +--------+ | +-------------+ | | +| : | | | | | +| +---------+ | | Load | | | +| | *SYSFW* | | | system | | | +| +---------+ | | Config data | | | +| | |<--------|---| | | | | | | | +-------------+ | | +| | | | | | | | +| | | | | DDR | | | +| | | | | config | | | +| | | | +-------------+ | | +| | | | | | | | | | |<--------|---| Start A53 | | | | | | | | and Reset | | | | | | | +-------------+ | | @@ -82,7 +90,7 @@ instead use Flacon boot flow to reduce boot time. | | | | | +-----------+ | | | | | | : | | | | | | +-----------+ | -| | |<--------|-----------------------|---->| *u-boot* | | +| | |<--------|-----------------------|---->| *U-Boot* | | | | | | | +-----------+ | | | | | | | prompt | | | | | | | +-----------+ | @@ -96,9 +104,8 @@ requests DMSC to get these services done as shown in the above diagram. Sources: -------- 1. SYSFW: - System Firmware repo is closed source and the binaries are delivered - to users with NDA. Please contact TI to get the System Firmware - Binary named ti-sci-firmware-am6x.bin that runs on AM65x SoC. + Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git + Branch: master 2. ATF: Tree: https://github.com/ARM-software/arm-trusted-firmware.git @@ -115,9 +122,7 @@ Sources: Build procedure: ---------------- 1. SYSFW: - ROM expects a signed binary that contains the X509 certificate. So -the binary ti-sci-firmware-am6x.bin cannot be uses as-is and needs to be signed. -Contact TI on the procedure to sign the system firmware binary. +$ make CROSS_COMPILE=arm-linux-gnueabihf- 2. ATF: $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed @@ -128,14 +133,79 @@ $ make PLATFORM=k3-am65x CFG_ARM64_core=y 4. U-Boot: 4.1. R5: - TBD. +$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5 +$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 4.2. A53: $ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53 -$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53 +$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a53 Target Images -------------- Copy the below images to an SD card and boot: +- sysfw.itb from step 1 - tiboot3.bin from step 4.1 - tispl.bin, u-boot.img from 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A53 ATF | | + | +-------------------+ | + | | | | + | | A53 OPTEE | | + | +-------------------+ | + | | | | + | | A53 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + +- sysfw.itb + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | sysfw.bin | | + | +-------------------+ | + | | | | + | | board config | | + | +-------------------+ | + | | | | + | | PM config | | + | +-------------------+ | + | | | | + | | RM config | | + | +-------------------+ | + | | | | + | | Secure config | | + | +-------------------+ | + +-----------------------+ diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index c475f106b2..e258e22f37 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -14,42 +14,7 @@ #include "board_detect.h" -#if defined(CONFIG_DM_I2C_COMPAT) -/** - * ti_i2c_set_alen - Set chip's i2c address length - * @bus_addr - I2C bus number - * @dev_addr - I2C eeprom id - * @alen - I2C address length in bytes - * - * DM_I2C by default sets the address length to be used to 1. This - * function allows this address length to be changed to match the - * eeprom used for board detection. - */ -int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen) -{ - struct udevice *dev; - struct udevice *bus; - int rc; - - rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus); - if (rc) - return rc; - rc = i2c_get_chip(bus, dev_addr, 1, &dev); - if (rc) - return rc; - rc = i2c_set_chip_offset_len(dev, alen); - if (rc) - return rc; - - return 0; -} -#else -int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen) -{ - return 0; -} -#endif - +#if !defined(CONFIG_DM_I2C) /** * ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device * @i2c_bus: i2c bus number to initialize @@ -82,18 +47,9 @@ static int __maybe_unused ti_i2c_eeprom_init(int i2c_bus, int dev_addr) static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset, uchar *ep, int epsize) { - int bus_num, rc, alen; - - bus_num = i2c_get_bus_num(); - - alen = 2; - - rc = ti_i2c_set_alen(bus_num, dev_addr, alen); - if (rc) - return rc; - - return i2c_read(dev_addr, offset, alen, ep, epsize); + return i2c_read(dev_addr, offset, 2, ep, epsize); } +#endif /** * ti_eeprom_string_cleanup() - Handle eeprom programming errors @@ -122,9 +78,57 @@ __weak void gpi2c_init(void) static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, u32 header, u32 size, uint8_t *ep) { - u32 byte, hdr_read; + u32 hdr_read; int rc; +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + struct udevice *bus; + + rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus); + if (rc) + return rc; + rc = i2c_get_chip(bus, dev_addr, 1, &dev); + if (rc) + return rc; + + /* + * Read the header first then only read the other contents. + */ + rc = i2c_set_chip_offset_len(dev, 2); + if (rc) + return rc; + + rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); + if (rc) + return rc; + + /* Corrupted data??? */ + if (hdr_read != header) { + rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); + /* + * read the eeprom header using i2c again, but use only a + * 1 byte address (some legacy boards need this..) + */ + if (rc) { + rc = i2c_set_chip_offset_len(dev, 1); + if (rc) + return rc; + + rc = dm_i2c_read(dev, 0, (uint8_t *)&hdr_read, 4); + } + if (rc) + return rc; + } + if (hdr_read != header) + return -1; + + rc = dm_i2c_read(dev, 0, ep, size); + if (rc) + return rc; +#else + u32 byte; + gpi2c_init(); rc = ti_i2c_eeprom_init(bus_addr, dev_addr); if (rc) @@ -135,10 +139,6 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, */ byte = 2; - rc = ti_i2c_set_alen(bus_addr, dev_addr, byte); - if (rc) - return rc; - rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); if (rc) return rc; @@ -152,10 +152,6 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, */ byte = 1; if (rc) { - rc = ti_i2c_set_alen(bus_addr, dev_addr, byte); - if (rc) - return rc; - rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4); } @@ -168,7 +164,7 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, rc = i2c_read(dev_addr, 0x0, byte, ep, size); if (rc) return rc; - +#endif return 0; } diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index bbe54450ae..d69641e3a0 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -646,6 +646,19 @@ int dram_init_banksize(void) return 0; } +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) +static int device_okay(const char *path) +{ + int node; + + node = fdt_path_offset(gd->fdt_blob, path); + if (node < 0) + return 0; + + return fdtdec_get_is_enabled(gd->fdt_blob, node); +} +#endif + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -684,6 +697,12 @@ int board_late_init(void) */ if (board_is_dra71x_evm()) palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7); +#endif +#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) + if (device_okay("/ocp/omap_dwc3_1@48880000")) + enable_usb_clocks(0); + if (device_okay("/ocp/omap_dwc3_2@488c0000")) + enable_usb_clocks(1); #endif return 0; } @@ -896,110 +915,6 @@ const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) } #endif -#ifdef CONFIG_USB_DWC3 -static struct dwc3_device usb_otg_ss1 = { - .maximum_speed = USB_SPEED_SUPER, - .base = DRA7_USB_OTG_SS1_BASE, - .tx_fifo_resize = false, - .index = 0, -}; - -static struct dwc3_omap_device usb_otg_ss1_glue = { - .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 0, -}; - -static struct ti_usb_phy_device usb_phy1_device = { - .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, - .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, - .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, - .index = 0, -}; - -static struct dwc3_device usb_otg_ss2 = { - .maximum_speed = USB_SPEED_SUPER, - .base = DRA7_USB_OTG_SS2_BASE, - .tx_fifo_resize = false, - .index = 1, -}; - -static struct dwc3_omap_device usb_otg_ss2_glue = { - .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 1, -}; - -static struct ti_usb_phy_device usb_phy2_device = { - .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, - .index = 1, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - enable_usb_clocks(index); - switch (index) { - case 0: - if (init == USB_INIT_DEVICE) { - usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - } - - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - dwc3_uboot_init(&usb_otg_ss1); - break; - case 1: - if (init == USB_INIT_DEVICE) { - usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - } - - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); - break; - default: - printf("Invalid Controller Index\n"); - } - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - switch (index) { - case 0: - case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); - break; - default: - printf("Invalid Controller Index\n"); - } - disable_usb_clocks(index); - return 0; -} - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) int spl_start_uboot(void) { diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index d81c8e621f..eed62e9cac 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -59,66 +59,30 @@ int dram_init(void) return 0; } +struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (struct image_header *)(CONFIG_SYS_TEXT_BASE); +} + int board_init(void) { +#if CONFIG_IS_ENABLED(DM_USB) + int rc = psc_enable_module(KS2_LPSC_USB); + + if (rc) + puts("Cannot enable USB0 module"); +#ifdef KS2_LPSC_USB_1 + rc = psc_enable_module(KS2_LPSC_USB_1); + if (rc) + puts("Cannot enable USB1 module"); +#endif +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -#ifndef CONFIG_DM_ETH -int get_eth_env_param(char *env_name) -{ - char *env; - int res = -1; - - env = env_get(env_name); - if (env) - res = simple_strtol(env, NULL, 0); - - return res; -} - -int board_eth_init(bd_t *bis) -{ - int j; - int res; - int port_num; - char link_type_name[32]; - - if (cpu_is_k2g()) - writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); - - /* By default, select PA PLL clock as PA clock source */ -#ifndef CONFIG_SOC_K2G - if (psc_enable_module(KS2_LPSC_PA)) - return -1; -#endif - if (psc_enable_module(KS2_LPSC_CPGMAC)) - return -1; - if (psc_enable_module(KS2_LPSC_CRYPTO)) - return -1; - - if (cpu_is_k2e() || cpu_is_k2l()) - pll_pa_clk_sel(); - - port_num = get_num_eth_ports(); - - for (j = 0; j < port_num; j++) { - sprintf(link_type_name, "sgmii%d_link_type", j); - res = get_eth_env_param(link_type_name); - if (res >= 0) - eth_priv_cfg[j].sgmii_link_type = res; - - keystone2_emac_initialize(ð_priv_cfg[j]); - } - - return 0; -} -#endif -#endif - #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index 250b649d45..d0cfbf5a75 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -12,8 +12,6 @@ #include #include "../common/board_detect.h" -extern struct eth_priv_t eth_priv_cfg[]; - #if defined(CONFIG_TI_I2C_BOARD_DETECT) static inline int board_is_k2g_gp(void) { @@ -38,7 +36,6 @@ static inline int board_is_k2g_ice(void) } #endif -int get_num_eth_ports(void); void spl_init_keystone_plls(void); #endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index f86a8363c4..ecd4a42df4 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -89,80 +89,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2E_EMAC0", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC1", - .rx_flow = 8, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC2", - .rx_flow = 16, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC3", - .rx_flow = 24, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC4", - .rx_flow = 32, - .phy_addr = 4, - .slave_port = 5, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC5", - .rx_flow = 40, - .phy_addr = 5, - .slave_port = 6, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC6", - .rx_flow = 48, - .phy_addr = 6, - .slave_port = 7, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC7", - .rx_flow = 56, - .phy_addr = 7, - .slave_port = 8, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #if defined(CONFIG_MULTI_DTB_FIT) int board_fit_config_name_match(const char *name) { diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 9bc94fb69e..39a782e479 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -251,6 +251,7 @@ int board_fit_config_name_match(const char *name) #if defined(CONFIG_DTB_RESELECT) static int k2g_alt_board_detect(void) { +#ifndef CONFIG_DM_I2C int rc; rc = i2c_set_bus_num(1); @@ -260,7 +261,17 @@ static int k2g_alt_board_detect(void) rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS); if (rc) return rc; +#else + struct udevice *bus, *dev; + int rc; + rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + if (rc) + return rc; + rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev); + if (rc) + return rc; +#endif ti_i2c_eeprom_am_set("66AK2GGP", "1.0X"); return 0; @@ -354,24 +365,6 @@ void spl_init_keystone_plls(void) } #endif -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2G_EMAC", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_TI_SECURE_DEVICE void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size) { diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index abc89d84bd..4c0acd627f 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -96,48 +96,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2HK_EMAC", - .rx_flow = 22, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC1", - .rx_flow = 23, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC2", - .rx_flow = 24, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC3", - .rx_flow = 25, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index c28fad51b6..e49d8b3482 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -84,48 +84,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2L_EMAC", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC1", - .rx_flow = 8, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC2", - .rx_flow = 16, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC3", - .rx_flow = 32, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig new file mode 100644 index 0000000000..cacc53f378 --- /dev/null +++ b/board/vamrs/rock960_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK960_RK3399 + +config SYS_BOARD + default "rock960_rk3399" + +config SYS_VENDOR + default "vamrs" + +config SYS_CONFIG_NAME + default "rock960_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS new file mode 100644 index 0000000000..22b2db925a --- /dev/null +++ b/board/vamrs/rock960_rk3399/MAINTAINERS @@ -0,0 +1,11 @@ +ROCK960-RK3399 +M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org +S: Maintained +F: board/rockchip/rock960_rk3399 +F: include/configs/rock960_rk3399.h +F: configs/rock960-rk3399_defconfig + +FICUS EE +M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org +S: Maintained +F: configs/ficus-rk3399_defconfig diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile new file mode 100644 index 0000000000..6c3e475b3a --- /dev/null +++ b/board/vamrs/rock960_rk3399/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Manivannan Sadhasivam +# + +obj-y += rock960-rk3399.o diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README new file mode 100644 index 0000000000..d14399090e --- /dev/null +++ b/board/vamrs/rock960_rk3399/README @@ -0,0 +1,152 @@ +Contents +======== + +1. Introduction +2. Get the Source and prebuild binary +3. Compile the U-Boot +4. Compile the rkdeveloptool +5. Package the image + 5.1. Package the image for U-Boot SPL(option 1) + 5.2. Package the image for Rockchip miniloader(option 2) +6. Bootloader storage options +7. Flash the image to eMMC + 7.1. Flash the image with U-Boot SPL(option 1) + 7.2. Flash the image with Rockchip miniloader(option 2) +8. Create a bootable SD/MMC +9. And that is it + +Introduction +============ + +Rock960 board family consists of Rock960 (Consumer Edition) and +Ficus (Enterprise Edition) 96Boards featuring Rockchip RK3399 SoC. + +Common features implemented on both boards: + * CPU: ARMv8 64bit Big-Little architecture, + * Big: dual-core Cortex-A72 + * Little: quad-core Cortex-A53 + * IRAM: 200KB + * eMMC: 16/32GB eMMC 5.1 + * PMU: RK808 + * SD/MMC + * Display: HDMI/DP/MIPI + * Low Speed Expansion Connector + * High Speed Expansion Connector + +Additional features of Rock960: + * DRAM: 2GB/4GB LPDDR3 @ 1866MHz + * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + +Additional features of Ficus: + * DRAM: 2GB/4GB DDR3 @ 1600MHz + * Ethernet + * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), + 1x USB 3.0 type C OTG + +Here is the step-by-step to boot to U-Boot on Rock960 boards. + +Get the Source and prebuild binary +================================== + + > git clone https://github.com/96rocks/rkbin.git + > git clone https://github.com/rockchip-linux/rkdeveloptool.git + +Compile the U-Boot +================== + + > cd ../u-boot + > cp ../rkbin/rk33/rk3399_bl31_v1.00.elf ./bl31.elf + > export ARCH=arm64 + > export CROSS_COMPILE=aarch64-linux-gnu- + > make rock960-rk3399_defconfig + > make + > make u-boot.itb + +Compile the rkdeveloptool +========================= + +Follow instructions in latest README + > cd ../rkdeveloptool + > autoreconf -i + > ./configure + > make + > sudo make install + +Package the image +================= + +Package the image for U-Boot SPL(option 1) +-------------------------------- + > cd .. + > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img + + Get idbspl.img in this step. + +Package the image for Rockchip miniloader(option 2) +------------------------------------------ + > cd ../rkbin + > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000 + + > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img + > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img + + Get uboot.img and idbloader.img in this step. + +Bootloader storage options +========================== + +There are a few different storage options for the bootloader. +This document explores two of these: eMMC and removable SD/MMC. + +Flash the image to eMMC +======================= + +Flash the image with U-Boot SPL(option 1) +------------------------------- +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin + > rkdeveloptool wl 64 u-boot/idbspl.img + > rkdeveloptool wl 0x4000 u-boot/u-boot.itb + > rkdeveloptool rd + +Flash the image with Rockchip miniloader(option 2) +---------------------------------------- +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin + > rkdeveloptool wl 0x40 idbloader.img + > rkdeveloptool wl 0x4000 uboot.img + > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img + > rkdeveloptool rd + +Create a bootable SD/MMC +======================== + +The idbspl.img contains the first stage, and the u-boot.img the second stage. +As explained in the Rockchip partition table reference [1], the first stage +(aka loader1) start sector is 64, and the second stage start sector is 16384. + +Each sector is 512 bytes, which means the first stage offset is 32 KiB, +and the second stage offset is 8 MiB. + +Note: the second stage location is actually not as per the spec, +but defined by the SPL. Mainline SPL defines an 8 MiB offset for the second +stage. + +Assuming the SD card is exposed by device /dev/mmcblk0, the commands +to write the two stages are: + + > dd if=idbspl.img of=/dev/mmcblk0 bs=1k seek=32 + > dd if=u-boot.itb of=/dev/mmcblk0 bs=1k seek=8192 + +Setting up the kernel and rootfs is beyond the scope of this document. + +And that is it +============== + +You should be able to get U-Boot log in console/UART2(baurdrate 1500000) + +For more detail, please reference [2]. + +[1] http://opensource.rock-chips.com/wiki_Partitions +[2] http://opensource.rock-chips.com/wiki_Boot_option diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c new file mode 100644 index 0000000000..d3775b2219 --- /dev/null +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + int ret; + + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); + + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); + return; +err: + printf("%s: Error %d\n", __func__, ret); + + /* No way to report error here */ + hang(); +} diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index df0a2d2b7a..c5949ad267 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -35,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -/* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 +/* GPIO that controls DIP switch and mPCIe slot */ #define DIP_S1 44 #define MPCIE_SW 100 @@ -248,9 +246,6 @@ const struct ctrl_ioregs ioregs_baltos = { void sdram_init(void) { - gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); - gpio_direction_output(GPIO_DDR_VTT_EN, 1); - config_ddr(400, &ioregs_baltos, &ddr3_baltos_data, &ddr3_baltos_cmd_ctrl_data, diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c index 94410ae35e..9c5542ea02 100644 --- a/board/vscom/baltos/mux.c +++ b/board/vscom/baltos/mux.c @@ -34,7 +34,6 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; @@ -46,11 +45,6 @@ static struct module_pin_mux i2c1_pin_mux[] = { {-1}, }; -static struct module_pin_mux gpio0_7_pin_mux[] = { - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ - {-1}, -}; - static struct module_pin_mux rmii1_pin_mux[] = { {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ @@ -114,7 +108,6 @@ void enable_i2c1_pin_mux(void) void enable_board_pin_mux() { configure_module_pin_mux(i2c1_pin_mux); - configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii2_pin_mux); configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); diff --git a/cmd/Kconfig b/cmd/Kconfig index ad14c9ce71..ea1a325eb3 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -445,6 +445,7 @@ config CRC32_VERIFY config CMD_EEPROM bool "eeprom - EEPROM subsystem" + depends on !DM_I2C || DM_I2C_COMPAT help (deprecated, needs conversion to driver model) Provides commands to read and write EEPROM (Electrically Erasable @@ -953,6 +954,14 @@ config CMD_PCMCIA about 1990. These devices are typically removable memory or network cards using a standard 68-pin connector. +config CMD_PINMUX + bool "pinmux - show pins muxing" + default y if PINCTRL + help + Parse all available pin-controllers and show pins muxing. This + is useful for debug purpoer to check the pin muxing and to know if + a pin is configured as a GPIO or as an alternate function. + config CMD_POWEROFF bool "poweroff" help @@ -1065,6 +1074,13 @@ config CMD_USB_MASS_STORAGE help USB mass storage support +config CMD_VIRTIO + bool "virtio" + depends on VIRTIO + default y if VIRTIO + help + VirtIO block device support + config CMD_AXI bool "axi" depends on AXI @@ -1365,6 +1381,14 @@ config CMD_CONITRACE Enable the 'conitrace' command which displays the codes received from the console input as hexadecimal numbers. +config CMD_CLS + bool "Enable clear screen command 'cls'" + depends on CFB_CONSOLE || DM_VIDEO || LCD || VIDEO + default y if LCD + help + Enable the 'cls' command which clears the screen contents + on video frame buffer. + config CMD_DISPLAY bool "Enable the 'display' command, for character displays" help diff --git a/cmd/Makefile b/cmd/Makefile index ac4830a692..15ae4d250f 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_CMD_BTRFS) += btrfs.o obj-$(CONFIG_CMD_CACHE) += cache.o obj-$(CONFIG_CMD_CBFS) += cbfs.o obj-$(CONFIG_CMD_CLK) += clk.o +obj-$(CONFIG_CMD_CLS) += cls.o obj-$(CONFIG_CMD_CONFIG) += config.o obj-$(CONFIG_CMD_CONITRACE) += conitrace.o obj-$(CONFIG_CMD_CONSOLE) += console.o @@ -39,6 +40,7 @@ obj-$(CONFIG_CMD_CPU) += cpu.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o obj-$(CONFIG_CMD_DATE) += date.o obj-$(CONFIG_CMD_DEMO) += demo.o +obj-$(CONFIG_CMD_DM) += dm.o obj-$(CONFIG_CMD_SOUND) += sound.o ifdef CONFIG_POST obj-$(CONFIG_CMD_DIAG) += diag.o @@ -103,6 +105,7 @@ ifdef CONFIG_PCI obj-$(CONFIG_CMD_PCI) += pci.o endif obj-y += pcmcia.o +obj-$(CONFIG_CMD_PINMUX) += pinmux.o obj-$(CONFIG_CMD_PXE) += pxe.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_CMD_QFW) += qfw.o @@ -114,6 +117,7 @@ obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o obj-$(CONFIG_SANDBOX) += host.o obj-$(CONFIG_CMD_SATA) += sata.o obj-$(CONFIG_CMD_NVME) += nvme.o +obj-$(CONFIG_SANDBOX) += sb.o obj-$(CONFIG_CMD_SF) += sf.o obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o @@ -135,6 +139,7 @@ obj-$(CONFIG_CMD_UBI) += ubi.o obj-$(CONFIG_CMD_UBIFS) += ubifs.o obj-$(CONFIG_CMD_UNIVERSE) += universe.o obj-$(CONFIG_CMD_UNZIP) += unzip.o +obj-$(CONFIG_CMD_VIRTIO) += virtio.o obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o obj-$(CONFIG_CMD_USB) += usb.o disk.o diff --git a/cmd/adc.c b/cmd/adc.c index c8857ed147..2d635acbd9 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -35,7 +35,7 @@ static int do_adc_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { struct udevice *dev; - unsigned int data_mask; + unsigned int data_mask, ch_mask; int ret, vss, vdd; if (argc < 2) @@ -49,6 +49,10 @@ static int do_adc_info(cmd_tbl_t *cmdtp, int flag, int argc, printf("ADC Device '%s' :\n", argv[1]); + ret = adc_channel_mask(dev, &ch_mask); + if (!ret) + printf("channel mask: %x\n", ch_mask); + ret = adc_data_mask(dev, &data_mask); if (!ret) printf("data mask: %x\n", data_mask); @@ -67,8 +71,9 @@ static int do_adc_info(cmd_tbl_t *cmdtp, int flag, int argc, static int do_adc_single(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct udevice *dev; unsigned int data; - int ret; + int ret, uV; if (argc < 3) return CMD_RET_USAGE; @@ -81,7 +86,62 @@ static int do_adc_single(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - printf("%u\n", data); + ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], &dev); + if (!ret && !adc_raw_to_uV(dev, data, &uV)) + printf("%u, %d uV\n", data, uV); + else + printf("%u\n", data); + + return CMD_RET_SUCCESS; +} + +static int do_adc_scan(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct adc_channel ch[ADC_MAX_CHANNEL]; + struct udevice *dev; + unsigned int ch_mask; + int i, chan, ret, uV; + + if (argc < 2) + return CMD_RET_USAGE; + + ret = uclass_get_device_by_name(UCLASS_ADC, argv[1], &dev); + if (ret) { + pr_err("Can't get the ADC %s: %d\n", argv[1], ret); + return CMD_RET_FAILURE; + } + + switch (argc) { + case 3: + ch_mask = simple_strtoul(argv[2], NULL, 0); + if (ch_mask) + break; + case 2: + ret = adc_channel_mask(dev, &ch_mask); + if (ret) { + pr_err("Can't get mask for %s: %d\n", dev->name, ret); + return CMD_RET_FAILURE; + } + break; + } + + ret = adc_channels_single_shot(dev->name, ch_mask, ch); + if (ret) { + pr_err("Can't get single shot for %s (chans mask: 0x%x): %d\n", + dev->name, ch_mask, ret); + return CMD_RET_FAILURE; + } + + for (chan = 0, i = 0; chan < ADC_MAX_CHANNEL; chan++) { + if (!(ch_mask & ADC_CHANNEL(chan))) + continue; + if (!adc_raw_to_uV(dev, ch[i].data, &uV)) + printf("[%02d]: %u, %d uV\n", ch[i].id, ch[i].data, uV); + else + printf("[%02d]: %u\n", ch[i].id, ch[i].data); + i++; + } return CMD_RET_SUCCESS; } @@ -90,6 +150,7 @@ static cmd_tbl_t cmd_adc_sub[] = { U_BOOT_CMD_MKENT(list, 1, 1, do_adc_list, "", ""), U_BOOT_CMD_MKENT(info, 2, 1, do_adc_info, "", ""), U_BOOT_CMD_MKENT(single, 3, 1, do_adc_single, "", ""), + U_BOOT_CMD_MKENT(scan, 3, 1, do_adc_scan, "", ""), }; static int do_adc(cmd_tbl_t *cmdtp, int flag, int argc, @@ -115,6 +176,7 @@ static int do_adc(cmd_tbl_t *cmdtp, int flag, int argc, static char adc_help_text[] = "list - list ADC devices\n" "adc info - Get ADC device info\n" - "adc single - Get Single data of ADC device channel"; + "adc single - Get Single data of ADC device channel\n" + "adc scan [channel mask] - Scan all [or masked] ADC channels"; U_BOOT_CMD(adc, 4, 1, do_adc, "ADC sub-system", adc_help_text); diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 60b438766d..cbeba6ba28 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; __maybe_unused static void print_num(const char *name, ulong value) { - printf("%-12s= 0x%08lX\n", name, value); + printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value); } __maybe_unused @@ -348,7 +348,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, CONFIG_VAL(SYS_MALLOC_F_LEN)); #endif if (gd->fdt_blob) - printf("fdt_blob = %p\n", gd->fdt_blob); + print_num("fdt_blob", (ulong)gd->fdt_blob); return 0; } diff --git a/cmd/bmp.c b/cmd/bmp.c index 02bdf48b4d..b8af784590 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -124,8 +124,14 @@ static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char * const ar break; case 4: addr = simple_strtoul(argv[1], NULL, 16); - x = simple_strtoul(argv[2], NULL, 10); - y = simple_strtoul(argv[3], NULL, 10); + if (!strcmp(argv[2], "m")) + x = BMP_ALIGN_CENTER; + else + x = simple_strtoul(argv[2], NULL, 10); + if (!strcmp(argv[3], "m")) + y = BMP_ALIGN_CENTER; + else + y = simple_strtoul(argv[3], NULL, 10); break; default: return CMD_RET_USAGE; @@ -249,9 +255,11 @@ int bmp_display(ulong addr, int x, int y) if (!ret) { bool align = false; -# ifdef CONFIG_SPLASH_SCREEN_ALIGN - align = true; -# endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + if (CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN) || + x == BMP_ALIGN_CENTER || + y == BMP_ALIGN_CENTER) + align = true; + ret = video_bmp_display(dev, addr, x, y, align); } #elif defined(CONFIG_LCD) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 4d68d80748..38679ffc56 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -148,16 +148,16 @@ static void set_load_options(struct efi_loaded_image *loaded_image_info, /** * copy_fdt() - Copy the device tree to a new location available to EFI * - * The FDT is relocated into a suitable location within the EFI memory map. - * An additional 12KB is added to the space in case the device tree needs to be + * The FDT is copied to a suitable location within the EFI memory map. + * Additional 12 KiB are added to the space in case the device tree needs to be * expanded later with fdt_open_into(). * - * @fdt_addr: On entry, address of start of FDT. On exit, address of relocated - * FDT start - * @fdt_sizep: Returns new size of FDT, including - * @return new relocated address of FDT + * @fdtp: On entry a pointer to the flattened device tree. + * On exit a pointer to the copy of the flattened device tree. + * FDT start + * Return: status code */ -static efi_status_t copy_fdt(ulong *fdt_addrp, ulong *fdt_sizep) +static efi_status_t copy_fdt(void **fdtp) { unsigned long fdt_ram_start = -1L, fdt_pages; efi_status_t ret = 0; @@ -178,17 +178,19 @@ static efi_status_t copy_fdt(ulong *fdt_addrp, ulong *fdt_sizep) } /* - * Give us at least 4KB of breathing room in case the device tree needs - * to be expanded later. Round up to the nearest EFI page boundary. + * Give us at least 12 KiB of breathing room in case the device tree + * needs to be expanded later. */ - fdt = map_sysmem(*fdt_addrp, 0); - fdt_size = fdt_totalsize(fdt); - fdt_size += 4096 * 3; - fdt_size = ALIGN(fdt_size + EFI_PAGE_SIZE - 1, EFI_PAGE_SIZE); - fdt_pages = fdt_size >> EFI_PAGE_SHIFT; + fdt = *fdtp; + fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000); + fdt_size = fdt_pages << EFI_PAGE_SHIFT; - /* Safe fdt location is at 127MB */ - new_fdt_addr = fdt_ram_start + (127 * 1024 * 1024) + fdt_size; + /* + * Safe fdt location is at 127 MiB. + * On the sandbox convert from the sandbox address space. + */ + new_fdt_addr = (uintptr_t)map_sysmem(fdt_ram_start + 0x7f00000 + + fdt_size, 0); ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, EFI_RUNTIME_SERVICES_DATA, fdt_pages, &new_fdt_addr); @@ -203,13 +205,11 @@ static efi_status_t copy_fdt(ulong *fdt_addrp, ulong *fdt_sizep) goto done; } } - - new_fdt = map_sysmem(new_fdt_addr, fdt_size); + new_fdt = (void *)(uintptr_t)new_fdt_addr; memcpy(new_fdt, fdt, fdt_totalsize(fdt)); fdt_set_totalsize(new_fdt, fdt_size); - *fdt_addrp = new_fdt_addr; - *fdt_sizep = fdt_size; + *fdtp = (void *)(uintptr_t)new_fdt_addr; done: return ret; } @@ -277,7 +277,11 @@ static void efi_carve_out_dt_rsv(void *fdt) if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0) continue; - pages = ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT; + /* Convert from sandbox address space. */ + addr = (uintptr_t)map_sysmem(addr, 0); + + pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK)); + addr &= ~EFI_PAGE_MASK; if (!efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE, false)) printf("FDT memrsv map %d: Failed to add to map\n", i); @@ -287,7 +291,6 @@ static void efi_carve_out_dt_rsv(void *fdt) static efi_status_t efi_install_fdt(ulong fdt_addr) { bootm_headers_t img = { 0 }; - ulong fdt_pages, fdt_size, fdt_start; efi_status_t ret; void *fdt; @@ -297,36 +300,60 @@ static efi_status_t efi_install_fdt(ulong fdt_addr) return EFI_INVALID_PARAMETER; } + /* Create memory reservation as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); + /* Prepare fdt for payload */ - ret = copy_fdt(&fdt_addr, &fdt_size); + ret = copy_fdt(&fdt); if (ret) return ret; - unmap_sysmem(fdt); - fdt = map_sysmem(fdt_addr, 0); - fdt_size = fdt_totalsize(fdt); if (image_setup_libfdt(&img, fdt, 0, NULL)) { printf("ERROR: failed to process device tree\n"); return EFI_LOAD_ERROR; } - efi_carve_out_dt_rsv(fdt); - /* Link to it in the efi tables */ ret = efi_install_configuration_table(&efi_guid_fdt, fdt); if (ret != EFI_SUCCESS) return EFI_OUT_OF_RESOURCES; - /* And reserve the space in the memory map */ - fdt_start = fdt_addr; - fdt_pages = fdt_size >> EFI_PAGE_SHIFT; - - ret = efi_add_memory_map(fdt_start, fdt_pages, - EFI_BOOT_SERVICES_DATA, true); - return ret; } +static efi_status_t bootefi_run_prepare(const char *load_options_path, + struct efi_device_path *device_path, + struct efi_device_path *image_path, + struct efi_loaded_image_obj **image_objp, + struct efi_loaded_image **loaded_image_infop) +{ + efi_status_t ret; + + ret = efi_setup_loaded_image(device_path, image_path, image_objp, + loaded_image_infop); + if (ret != EFI_SUCCESS) + return ret; + + /* Transfer environment variable as load options */ + set_load_options(*loaded_image_infop, load_options_path); + + return 0; +} + +/** + * bootefi_run_finish() - finish up after running an EFI test + * + * @loaded_image_info: Pointer to a struct which holds the loaded image info + * @image_objj: Pointer to a struct which holds the loaded image object + */ +static void bootefi_run_finish(struct efi_loaded_image_obj *image_obj, + struct efi_loaded_image *loaded_image_info) +{ + efi_restore_gd(); + free(loaded_image_info->load_options); + efi_delete_handle(&image_obj->header); +} + /** * do_bootefi_exec() - execute EFI binary * @@ -345,7 +372,7 @@ static efi_status_t do_bootefi_exec(void *efi, efi_handle_t mem_handle = NULL; struct efi_device_path *memdp = NULL; efi_status_t ret; - struct efi_loaded_image_obj *image_handle = NULL; + struct efi_loaded_image_obj *image_obj = NULL; struct efi_loaded_image *loaded_image_info = NULL; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, @@ -354,7 +381,7 @@ static efi_status_t do_bootefi_exec(void *efi, /* * Special case for efi payload not loaded from disk, such as * 'bootefi hello' or for example payload loaded directly into - * memory via jtag, etc: + * memory via JTAG, etc: */ if (!device_path && !image_path) { printf("WARNING: using memory device/image path, this may confuse some payloads!\n"); @@ -367,27 +394,25 @@ static efi_status_t do_bootefi_exec(void *efi, */ ret = efi_create_handle(&mem_handle); if (ret != EFI_SUCCESS) - goto exit; + return ret; /* TODO: leaks device_path */ ret = efi_add_protocol(mem_handle, &efi_guid_device_path, device_path); if (ret != EFI_SUCCESS) - goto exit; + goto err_add_protocol; } else { assert(device_path && image_path); } - ret = efi_setup_loaded_image(device_path, image_path, &image_handle, - &loaded_image_info); - if (ret != EFI_SUCCESS) - goto exit; + ret = bootefi_run_prepare("bootargs", device_path, image_path, + &image_obj, &loaded_image_info); + if (ret) + goto err_prepare; - /* Transfer environment variable bootargs as load options */ - set_load_options(loaded_image_info, "bootargs"); /* Load the EFI payload */ - entry = efi_load_pe(image_handle, efi, loaded_image_info); + entry = efi_load_pe(image_obj, efi, loaded_image_info); if (!entry) { ret = EFI_LOAD_ERROR; - goto exit; + goto err_prepare; } if (memdp) { @@ -405,9 +430,9 @@ static efi_status_t do_bootefi_exec(void *efi, /* Call our payload! */ debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry); - if (setjmp(&image_handle->exit_jmp)) { - ret = image_handle->exit_status; - goto exit; + if (setjmp(&image_obj->exit_jmp)) { + ret = image_obj->exit_status; + goto err_prepare; } #ifdef CONFIG_ARM64 @@ -418,7 +443,7 @@ static efi_status_t do_bootefi_exec(void *efi, /* Move into EL2 and keep running there */ armv8_switch_to_el2((ulong)entry, - (ulong)image_handle, + (ulong)&image_obj->header, (ulong)&systab, 0, (ulong)efi_run_in_el2, ES_TO_AARCH64); @@ -435,7 +460,7 @@ static efi_status_t do_bootefi_exec(void *efi, secure_ram_addr(_do_nonsec_entry)( efi_run_in_hyp, (uintptr_t)entry, - (uintptr_t)image_handle, + (uintptr_t)&image_obj->header, (uintptr_t)&systab); /* Should never reach here, efi exits with longjmp */ @@ -443,18 +468,59 @@ static efi_status_t do_bootefi_exec(void *efi, } #endif - ret = efi_do_enter(image_handle, &systab, entry); + ret = efi_do_enter(&image_obj->header, &systab, entry); -exit: +err_prepare: /* image has returned, loaded-image obj goes *poof*: */ - if (image_handle) - efi_delete_handle(&image_handle->parent); + bootefi_run_finish(image_obj, loaded_image_info); + +err_add_protocol: if (mem_handle) efi_delete_handle(mem_handle); return ret; } +#ifdef CONFIG_CMD_BOOTEFI_SELFTEST +/** + * bootefi_test_prepare() - prepare to run an EFI test + * + * This sets things up so we can call EFI functions. This involves preparing + * the 'gd' pointer and setting up the load ed image data structures. + * + * @image_objp: loaded_image_infop: Pointer to a struct which will hold the + * loaded image object. This struct will be inited by this function before + * use. + * @loaded_image_infop: Pointer to a struct which will hold the loaded image + * info. This struct will be inited by this function before use. + * @path: File path to the test being run (often just the test name with a + * backslash before it + * @test_func: Address of the test function that is being run + * @load_options_path: U-Boot environment variable to use as load options + * @return 0 if OK, -ve on error + */ +static efi_status_t bootefi_test_prepare + (struct efi_loaded_image_obj **image_objp, + struct efi_loaded_image **loaded_image_infop, const char *path, + ulong test_func, const char *load_options_path) +{ + /* Construct a dummy device path */ + bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)test_func, + (uintptr_t)test_func); + if (!bootefi_device_path) + return EFI_OUT_OF_RESOURCES; + bootefi_image_path = efi_dp_from_file(NULL, 0, path); + if (!bootefi_image_path) + return EFI_OUT_OF_RESOURCES; + + return bootefi_run_prepare(load_options_path, bootefi_device_path, + bootefi_image_path, image_objp, + loaded_image_infop); +} + +#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */ + static int do_bootefi_bootmgr_exec(void) { struct efi_device_path *device_path, *file_path; @@ -527,29 +593,17 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_CMD_BOOTEFI_SELFTEST if (!strcmp(argv[1], "selftest")) { - struct efi_loaded_image_obj *image_handle; + struct efi_loaded_image_obj *image_obj; struct efi_loaded_image *loaded_image_info; - /* Construct a dummy device path. */ - bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, - (uintptr_t)&efi_selftest, - (uintptr_t)&efi_selftest); - bootefi_image_path = efi_dp_from_file(NULL, 0, "\\selftest"); - - r = efi_setup_loaded_image(bootefi_device_path, - bootefi_image_path, &image_handle, - &loaded_image_info); - if (r != EFI_SUCCESS) + if (bootefi_test_prepare(&image_obj, &loaded_image_info, + "\\selftest", (uintptr_t)&efi_selftest, + "efi_selftest")) return CMD_RET_FAILURE; - efi_save_gd(); - /* Transfer environment variable efi_selftest as load options */ - set_load_options(loaded_image_info, "efi_selftest"); /* Execute the test */ - r = efi_selftest(image_handle, &systab); - efi_restore_gd(); - free(loaded_image_info->load_options); - efi_delete_handle(&image_handle->parent); + r = efi_selftest(&image_obj->header, &systab); + bootefi_run_finish(image_obj, loaded_image_info); return r != EFI_SUCCESS; } else #endif @@ -608,45 +662,19 @@ U_BOOT_CMD( void efi_set_bootdev(const char *dev, const char *devnr, const char *path) { - char filename[32] = { 0 }; /* dp->str is u16[32] long */ - char *s; + struct efi_device_path *device, *image; + efi_status_t ret; /* efi_set_bootdev is typically called repeatedly, recover memory */ efi_free_pool(bootefi_device_path); efi_free_pool(bootefi_image_path); - /* If blk_get_device_part_str fails, avoid duplicate free. */ - bootefi_device_path = NULL; - bootefi_image_path = NULL; - if (strcmp(dev, "Net")) { - struct blk_desc *desc; - disk_partition_t fs_partition; - int part; - - part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, - 1); - if (part < 0) - return; - - bootefi_device_path = efi_dp_from_part(desc, part); + ret = efi_dp_from_name(dev, devnr, path, &device, &image); + if (ret == EFI_SUCCESS) { + bootefi_device_path = device; + bootefi_image_path = image; } else { -#ifdef CONFIG_NET - bootefi_device_path = efi_dp_from_eth(); -#endif + bootefi_device_path = NULL; + bootefi_image_path = NULL; } - - if (!path) - return; - - if (strcmp(dev, "Net")) { - /* Add leading / to fs paths, because they're absolute */ - snprintf(filename, sizeof(filename), "/%s", path); - } else { - snprintf(filename, sizeof(filename), "%s", path); - } - /* DOS style file path: */ - s = filename; - while ((s = strchr(s, '/'))) - *s++ = '\\'; - bootefi_image_path = efi_dp_from_file(NULL, 0, filename); } diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 21f353ffd3..7f88c1ed63 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -253,6 +253,7 @@ static struct bootmenu_data *bootmenu_create(int delay) int len; char *sep; + char *default_str; struct bootmenu_entry *entry; menu = malloc(sizeof(struct bootmenu_data)); @@ -263,6 +264,10 @@ static struct bootmenu_data *bootmenu_create(int delay) menu->active = 0; menu->first = NULL; + default_str = env_get("bootmenu_default"); + if (default_str) + menu->active = (int)simple_strtol(default_str, NULL, 10); + while ((option = bootmenu_getoption(i))) { sep = strchr(option, '='); if (!sep) { @@ -346,6 +351,12 @@ static struct bootmenu_data *bootmenu_create(int delay) } menu->count = i; + + if ((menu->active >= menu->count)||(menu->active < 0)) { //ensure active menuitem is inside menu + printf("active menuitem (%d) is outside menu (0..%d)\n",menu->active,menu->count-1); + menu->active=0; + } + return menu; cleanup: diff --git a/cmd/cbfs.c b/cmd/cbfs.c index ece790e56e..c118a952ac 100644 --- a/cmd/cbfs.c +++ b/cmd/cbfs.c @@ -112,12 +112,21 @@ static int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, printf(" %8d", file_cbfs_size(file)); switch (type) { + case CBFS_TYPE_BOOTBLOCK: + type_name = "bootblock"; + break; + case CBFS_TYPE_CBFSHEADER: + type_name = "cbfs header"; + break; case CBFS_TYPE_STAGE: type_name = "stage"; break; case CBFS_TYPE_PAYLOAD: type_name = "payload"; break; + case CBFS_TYPE_FIT: + type_name = "fit"; + break; case CBFS_TYPE_OPTIONROM: type_name = "option rom"; break; @@ -136,10 +145,31 @@ static int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, case CBFS_TYPE_MICROCODE: type_name = "microcode"; break; - case CBFS_COMPONENT_CMOS_DEFAULT: + case CBFS_TYPE_FSP: + type_name = "fsp"; + break; + case CBFS_TYPE_MRC: + type_name = "mrc"; + break; + case CBFS_TYPE_MMA: + type_name = "mma"; + break; + case CBFS_TYPE_EFI: + type_name = "efi"; + break; + case CBFS_TYPE_STRUCT: + type_name = "struct"; + break; + case CBFS_TYPE_CMOS_DEFAULT: type_name = "cmos default"; break; - case CBFS_COMPONENT_CMOS_LAYOUT: + case CBFS_TYPE_SPD: + type_name = "spd"; + break; + case CBFS_TYPE_MRC_CACHE: + type_name = "mrc cache"; + break; + case CBFS_TYPE_CMOS_LAYOUT: type_name = "cmos layout"; break; case -1: diff --git a/cmd/cls.c b/cmd/cls.c new file mode 100644 index 0000000000..f1ce6e8df1 --- /dev/null +++ b/cmd/cls.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * DENX Software Engineering, Anatolij Gustschin + * + * cls - clear screen command + */ +#include +#include +#include +#include +#include + +static int do_video_clear(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ +#if defined(CONFIG_DM_VIDEO) + struct udevice *dev; + + if (uclass_first_device_err(UCLASS_VIDEO, &dev)) + return CMD_RET_FAILURE; + + if (video_clear(dev)) + return CMD_RET_FAILURE; +#elif defined(CONFIG_CFB_CONSOLE) + video_clear(); +#elif defined(CONFIG_LCD) + lcd_clear(); +#else + return CMD_RET_FAILURE; +#endif + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(cls, 1, 1, do_video_clear, "clear screen", ""); diff --git a/test/dm/cmd_dm.c b/cmd/dm.c similarity index 100% rename from test/dm/cmd_dm.c rename to cmd/dm.c diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 4052cf494a..6c29b33ba3 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -66,11 +66,6 @@ __weak int eeprom_write_enable(unsigned dev_addr, int state) void eeprom_init(int bus) { - /* SPI EEPROM */ -#if defined(CONFIG_MPC8XX_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - spi_init_f(); -#endif - /* I2C EEPROM */ #if defined(CONFIG_SYS_I2C) if (bus >= 0) @@ -129,14 +124,23 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, { int ret = 0; - /* SPI */ -#if defined(CONFIG_MPC8XX_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) - if (read) - spi_read(addr, alen, buffer, len); - else - spi_write(addr, alen, buffer, len); -#else /* I2C */ +#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS) + struct udevice *dev; + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0], + alen - 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_EEPROM_BUS); + return CMD_RET_FAILURE; + } + + if (read) + ret = dm_i2c_read(dev, offset, buffer, len); + else + ret = dm_i2c_write(dev, offset, buffer, len); + +#else /* Non DM I2C support - will be removed */ #if defined(CONFIG_SYS_I2C_EEPROM_BUS) i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); #endif @@ -145,10 +149,10 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, ret = i2c_read(addr[0], offset, alen - 1, buffer, len); else ret = i2c_write(addr[0], offset, alen - 1, buffer, len); - +#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */ if (ret) - ret = 1; -#endif + ret = CMD_RET_FAILURE; + return ret; } diff --git a/cmd/fastboot.c b/cmd/fastboot.c index ae3a5f627f..0be83b78ac 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -51,7 +51,7 @@ static int do_fastboot_usb(int argc, char *const argv[], return CMD_RET_FAILURE; } - ret = board_usb_init(controller_index, USB_INIT_DEVICE); + ret = usb_gadget_initialize(controller_index); if (ret) { pr_err("USB init failed: %d\n", ret); return CMD_RET_FAILURE; @@ -82,7 +82,7 @@ static int do_fastboot_usb(int argc, char *const argv[], exit: g_dnl_unregister(); g_dnl_clear_detach(); - board_usb_cleanup(controller_index, USB_INIT_DEVICE); + usb_gadget_release(controller_index); return ret; #else diff --git a/cmd/fdt.c b/cmd/fdt.c index 8a19a3fdbf..10d8f3230b 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -73,6 +73,40 @@ static int fdt_value_env_set(const void *nodep, int len, const char *var) return 0; } +static const char * const fdt_member_table[] = { + "magic", + "totalsize", + "off_dt_struct", + "off_dt_strings", + "off_mem_rsvmap", + "version", + "last_comp_version", + "boot_cpuid_phys", + "size_dt_strings", + "size_dt_struct", +}; + +static int fdt_get_header_value(int argc, char * const argv[]) +{ + fdt32_t *fdtp = (fdt32_t *)working_fdt; + ulong val; + int i; + + if (argv[2][0] != 'g') + return CMD_RET_FAILURE; + + for (i = 0; i < ARRAY_SIZE(fdt_member_table); i++) { + if (strcmp(fdt_member_table[i], argv[4])) + continue; + + val = fdt32_to_cpu(fdtp[i]); + env_set_hex(argv[3], val); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + /* * Flattened Device Tree command, see the help for parameter definitions. */ @@ -202,7 +236,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) fdt_strerror(err)); return 1; } - working_fdt = newaddr; + set_working_fdt_addr((ulong)newaddr); #ifdef CONFIG_OF_SYSTEM_SETUP /* Call the board-specific fixup routine */ } else if (strncmp(argv[1], "sys", 3) == 0) { @@ -491,6 +525,9 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Display header info */ } else if (argv[1][0] == 'h') { + if (argc == 5) + return fdt_get_header_value(argc, argv); + u32 version = fdt_version(working_fdt); printf("magic:\t\t\t0x%x\n", fdt_magic(working_fdt)); printf("totalsize:\t\t0x%x (%d)\n", fdt_totalsize(working_fdt), @@ -1090,7 +1127,8 @@ static char fdt_help_text[] = "fdt set [] - Set [to ]\n" "fdt mknode - Create a new node after \n" "fdt rm [] - Delete the node or \n" - "fdt header - Display header info\n" + "fdt header [get ] - Display header info\n" + " get - get header member and store it in \n" "fdt bootcpu - Set boot cpuid\n" "fdt memory - Add/Update memory node\n" "fdt rsvmem print - Show current mem reserves\n" diff --git a/cmd/host.c b/cmd/host.c index 645dba4de8..f7d3eae5b1 100644 --- a/cmd/host.c +++ b/cmd/host.c @@ -167,11 +167,6 @@ static int do_host(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_USAGE; } -U_BOOT_CMD( - sb, 8, 1, do_host, - "Deprecated: use 'host' command instead.", "" -); - U_BOOT_CMD( host, 8, 1, do_host, "Miscellaneous host commands", diff --git a/cmd/i2c.c b/cmd/i2c.c index 56df8eb3bc..09c4ba9a1c 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -2023,6 +2023,7 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) static char i2c_help_text[] = #if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C) "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n" + "i2c " /* That's the prefix for the crc32 command below. */ #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" #if defined(CONFIG_SYS_I2C) || \ diff --git a/cmd/pinmux.c b/cmd/pinmux.c new file mode 100644 index 0000000000..6c8ec5164d --- /dev/null +++ b/cmd/pinmux.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include + +#define LIMIT_DEVNAME 30 + +static struct udevice *currdev; + +static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *name; + int ret; + + switch (argc) { + case 2: + name = argv[1]; + ret = uclass_get_device_by_name(UCLASS_PINCTRL, name, &currdev); + if (ret) { + printf("Can't get the pin-controller: %s!\n", name); + return CMD_RET_FAILURE; + } + case 1: + if (!currdev) { + printf("Pin-controller device is not set!\n"); + return CMD_RET_USAGE; + } + + printf("dev: %s\n", currdev->name); + } + + return CMD_RET_SUCCESS; +} + +static int show_pinmux(struct udevice *dev) +{ + char pin_name[PINNAME_SIZE]; + char pin_mux[PINMUX_SIZE]; + int pins_count; + int i; + int ret; + + pins_count = pinctrl_get_pins_count(dev); + + if (pins_count == -ENOSYS) { + printf("Ops get_pins_count not supported\n"); + return pins_count; + } + + for (i = 0; i < pins_count; i++) { + ret = pinctrl_get_pin_name(dev, i, pin_name, PINNAME_SIZE); + if (ret == -ENOSYS) { + printf("Ops get_pin_name not supported\n"); + return ret; + } + + ret = pinctrl_get_pin_muxing(dev, i, pin_mux, PINMUX_SIZE); + if (ret) { + printf("Ops get_pin_muxing error (%d)\n", ret); + return ret; + } + + printf("%-*s: %-*s\n", PINNAME_SIZE, pin_name, + PINMUX_SIZE, pin_mux); + } + + return 0; +} + +static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + int ret = CMD_RET_USAGE; + + if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) + return show_pinmux(currdev); + + if (argc < 2 || strcmp(argv[1], "-a")) + return ret; + + uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) { + /* insert a separator between each pin-controller display */ + printf("--------------------------\n"); + printf("%s:\n", dev->name); + ret = show_pinmux(dev); + if (ret < 0) + printf("Can't display pin muxing for %s\n", + dev->name); + } + + return ret; +} + +static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + + printf("| %-*.*s| %-*.*s| %s\n", + LIMIT_DEVNAME, LIMIT_DEVNAME, "Device", + LIMIT_DEVNAME, LIMIT_DEVNAME, "Driver", + "Parent"); + + uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) { + printf("| %-*.*s| %-*.*s| %s\n", + LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name, + LIMIT_DEVNAME, LIMIT_DEVNAME, dev->driver->name, + dev->parent->name); + } + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t pinmux_subcmd[] = { + U_BOOT_CMD_MKENT(dev, 2, 1, do_dev, "", ""), + U_BOOT_CMD_MKENT(list, 1, 1, do_list, "", ""), + U_BOOT_CMD_MKENT(status, 2, 1, do_status, "", ""), +}; + +static int do_pinmux(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cmd; + + argc--; + argv++; + + cmd = find_cmd_tbl(argv[0], pinmux_subcmd, ARRAY_SIZE(pinmux_subcmd)); + if (!cmd || argc > cmd->maxargs) + return CMD_RET_USAGE; + + return cmd->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD(pinmux, CONFIG_SYS_MAXARGS, 1, do_pinmux, + "show pin-controller muxing", + "list - list UCLASS_PINCTRL devices\n" + "pinmux dev [pincontroller-name] - select pin-controller device\n" + "pinmux status [-a] - print pin-controller muxing [for all]\n" +) diff --git a/cmd/rockusb.c b/cmd/rockusb.c index 8206643b27..e0c1480d6d 100644 --- a/cmd/rockusb.c +++ b/cmd/rockusb.c @@ -33,7 +33,7 @@ static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) dev_index = simple_strtoul(devnum, NULL, 0); rockusb_dev_init(devtype, dev_index); - ret = board_usb_init(controller_index, USB_INIT_DEVICE); + ret = usb_gadget_initialize(controller_index); if (ret) { printf("USB init failed: %d\n", ret); return CMD_RET_FAILURE; @@ -62,7 +62,7 @@ static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) exit: g_dnl_unregister(); g_dnl_clear_detach(); - board_usb_cleanup(controller_index, USB_INIT_DEVICE); + usb_gadget_release(controller_index); return ret; } diff --git a/cmd/sata.c b/cmd/sata.c index 4f0c6e0137..6d62ba8f74 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -51,7 +51,6 @@ int sata_probe(int devnum) { #ifdef CONFIG_AHCI struct udevice *dev; - struct udevice *blk; int rc; rc = uclass_get_device(UCLASS_AHCI, devnum, &dev); @@ -67,14 +66,6 @@ int sata_probe(int devnum) return CMD_RET_FAILURE; } - rc = blk_get_from_parent(dev, &blk); - if (!rc) { - struct blk_desc *desc = dev_get_uclass_platdata(blk); - - if (desc->lba > 0 && desc->blksz > 0) - part_init(desc); - } - return 0; #else return sata_initialize() < 0 ? CMD_RET_FAILURE : CMD_RET_SUCCESS; diff --git a/cmd/sb.c b/cmd/sb.c new file mode 100644 index 0000000000..5701e03797 --- /dev/null +++ b/cmd/sb.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, Google Inc. + * Written by Simon Glass + */ + +#include +#include +#include +#include + +static int do_sb_handoff(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ +#if CONFIG_IS_ENABLED(HANDOFF) + if (gd->spl_handoff) + printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic); + else + printf("SPL handoff info not received\n"); + + return 0; +#else + printf("Command not supported\n"); + + return CMD_RET_USAGE; +#endif +} + +static int do_sb_state(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct sandbox_state *state; + + state = state_get_current(); + state_show(state); + + return 0; +} + +static cmd_tbl_t cmd_sb_sub[] = { + U_BOOT_CMD_MKENT(handoff, 1, 0, do_sb_handoff, "", ""), + U_BOOT_CMD_MKENT(state, 1, 0, do_sb_state, "", ""), +}; + +static int do_sb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *c; + + /* Skip past 'sb' */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_sb_sub, ARRAY_SIZE(cmd_sb_sub)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + sb, 8, 1, do_sb, + "Sandbox status commands", + "handoff - Show handoff data received from SPL\n" + "sb state - Show sandbox state" +); diff --git a/cmd/sound.c b/cmd/sound.c index d1cbc14f8d..638f29df21 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -14,11 +15,14 @@ DECLARE_GLOBAL_DATA_PTR; /* Initilaise sound subsystem */ static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct udevice *dev; int ret; - ret = sound_init(gd->fdt_blob); + ret = uclass_first_device_err(UCLASS_SOUND, &dev); + if (!ret) + ret = sound_setup(dev); if (ret) { - printf("Initialise Audio driver failed\n"); + printf("Initialise Audio driver failed (ret=%d)\n", ret); return CMD_RET_FAILURE; } @@ -28,6 +32,7 @@ static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* play sound from buffer */ static int do_play(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct udevice *dev; int ret = 0; int msec = 1000; int freq = 400; @@ -37,9 +42,11 @@ static int do_play(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (argc > 2) freq = simple_strtoul(argv[2], NULL, 10); - ret = sound_play(msec, freq); + ret = uclass_first_device_err(UCLASS_SOUND, &dev); + if (!ret) + ret = sound_beep(dev, msec, freq); if (ret) { - printf("play failed"); + printf("Sound device failed to play (err=%d)\n", ret); return CMD_RET_FAILURE; } diff --git a/cmd/thordown.c b/cmd/thordown.c index 2615adad75..ce3660d174 100644 --- a/cmd/thordown.c +++ b/cmd/thordown.c @@ -30,7 +30,7 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) goto done; int controller_index = simple_strtoul(usb_controller, NULL, 0); - ret = board_usb_init(controller_index, USB_INIT_DEVICE); + ret = usb_gadget_initialize(controller_index); if (ret) { pr_err("USB init failed: %d\n", ret); ret = CMD_RET_FAILURE; @@ -55,7 +55,7 @@ int do_thor_down(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) exit: g_dnl_unregister(); - board_usb_cleanup(controller_index, USB_INIT_DEVICE); + usb_gadget_release(controller_index); done: dfu_free_entities(); diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index 56443862c2..89f2aa001b 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -264,10 +264,16 @@ int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) int do_tpm_init(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; + int rc; + if (argc != 1) return CMD_RET_USAGE; + rc = get_tpm(&dev); + if (rc) + return rc; - return report_return_code(tpm_init()); + return report_return_code(tpm_init(dev)); } int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index 69870002d4..b75e0933a1 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -14,7 +14,12 @@ static int do_tpm_startup(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum tpm_startup_type mode; + struct udevice *dev; + int rc; + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 2) return CMD_RET_USAGE; if (!strcasecmp("TPM_ST_CLEAR", argv[1])) { @@ -28,13 +33,19 @@ static int do_tpm_startup(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - return report_return_code(tpm_startup(mode)); + return report_return_code(tpm_startup(dev, mode)); } static int do_tpm_nv_define_space(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, perm, size; + struct udevice *dev; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 4) return CMD_RET_USAGE; @@ -42,22 +53,27 @@ static int do_tpm_nv_define_space(cmd_tbl_t *cmdtp, int flag, int argc, perm = simple_strtoul(argv[2], NULL, 0); size = simple_strtoul(argv[3], NULL, 0); - return report_return_code(tpm_nv_define_space(index, perm, size)); + return report_return_code(tpm_nv_define_space(dev, index, perm, size)); } static int do_tpm_nv_read_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, count, rc; + struct udevice *dev; void *data; + rc = get_tpm(&dev); + if (rc) + return rc; + if (argc != 4) return CMD_RET_USAGE; index = simple_strtoul(argv[1], NULL, 0); data = (void *)simple_strtoul(argv[2], NULL, 0); count = simple_strtoul(argv[3], NULL, 0); - rc = tpm_nv_read_value(index, data, count); + rc = tpm_nv_read_value(dev, index, data, count); if (!rc) { puts("area content:\n"); print_byte_string(data, count); @@ -69,10 +85,15 @@ static int do_tpm_nv_read_value(cmd_tbl_t *cmdtp, int flag, int argc, static int do_tpm_nv_write_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u32 index, rc; size_t count; void *data; + rc = get_tpm(&dev); + if (rc) + return rc; + if (argc != 3) return CMD_RET_USAGE; index = simple_strtoul(argv[1], NULL, 0); @@ -82,7 +103,7 @@ static int do_tpm_nv_write_value(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - rc = tpm_nv_write_value(index, data, count); + rc = tpm_nv_write_value(dev, index, data, count); free(data); return report_return_code(rc); @@ -91,8 +112,13 @@ static int do_tpm_nv_write_value(cmd_tbl_t *cmdtp, int flag, int argc, static int do_tpm_extend(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u32 index, rc; u8 in_digest[20], out_digest[20]; + struct udevice *dev; + u32 index, rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 3) return CMD_RET_USAGE; @@ -102,7 +128,7 @@ static int do_tpm_extend(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - rc = tpm_extend(index, in_digest, out_digest); + rc = tpm_extend(dev, index, in_digest, out_digest); if (!rc) { puts("PCR value after execution of the command:\n"); print_byte_string(out_digest, sizeof(out_digest)); @@ -115,15 +141,20 @@ static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, count, rc; + struct udevice *dev; void *data; + rc = get_tpm(&dev); + if (rc) + return rc; + if (argc != 4) return CMD_RET_USAGE; index = simple_strtoul(argv[1], NULL, 0); data = (void *)simple_strtoul(argv[2], NULL, 0); count = simple_strtoul(argv[3], NULL, 0); - rc = tpm_pcr_read(index, data, count); + rc = tpm_pcr_read(dev, index, data, count); if (!rc) { puts("Named PCR content:\n"); print_byte_string(data, count); @@ -135,27 +166,38 @@ static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc, static int do_tpm_tsc_physical_presence(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u16 presence; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 2) return CMD_RET_USAGE; presence = (u16)simple_strtoul(argv[1], NULL, 0); - return report_return_code(tpm_tsc_physical_presence(presence)); + return report_return_code(tpm_tsc_physical_presence(dev, presence)); } static int do_tpm_read_pubek(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u32 count, rc; void *data; + rc = get_tpm(&dev); + if (rc) + return rc; + if (argc != 3) return CMD_RET_USAGE; data = (void *)simple_strtoul(argv[1], NULL, 0); count = simple_strtoul(argv[2], NULL, 0); - rc = tpm_read_pubek(data, count); + rc = tpm_read_pubek(dev, data, count); if (!rc) { puts("pubek value:\n"); print_byte_string(data, count); @@ -167,13 +209,19 @@ static int do_tpm_read_pubek(cmd_tbl_t *cmdtp, int flag, int argc, static int do_tpm_physical_set_deactivated(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; u8 state; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 2) return CMD_RET_USAGE; state = (u8)simple_strtoul(argv[1], NULL, 0); - return report_return_code(tpm_physical_set_deactivated(state)); + return report_return_code(tpm_physical_set_deactivated(dev, state)); } static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc, @@ -182,6 +230,11 @@ static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc, u32 cap_area, sub_cap, rc; void *cap; size_t count; + struct udevice *dev; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 5) return CMD_RET_USAGE; @@ -190,7 +243,7 @@ static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc, cap = (void *)simple_strtoul(argv[3], NULL, 0); count = simple_strtoul(argv[4], NULL, 0); - rc = tpm_get_capability(cap_area, sub_cap, cap, count); + rc = tpm_get_capability(dev, cap_area, sub_cap, cap, count); if (!rc) { puts("capability information:\n"); print_byte_string(cap, count); @@ -232,6 +285,12 @@ static int do_tpm_nv_define(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, perm, size; + struct udevice *dev; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 4) return CMD_RET_USAGE; @@ -243,14 +302,20 @@ static int do_tpm_nv_define(cmd_tbl_t *cmdtp, int flag, int argc, index = simple_strtoul(argv[2], NULL, 0); perm = simple_strtoul(argv[3], NULL, 0); - return report_return_code(tpm_nv_define_space(index, perm, size)); + return report_return_code(tpm_nv_define_space(dev, index, perm, size)); } static int do_tpm_nv_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, count, err; + struct udevice *dev; void *data; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc < 3) return CMD_RET_USAGE; @@ -263,7 +328,7 @@ static int do_tpm_nv_read(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_USAGE; } - err = tpm_nv_read_value(index, data, count); + err = tpm_nv_read_value(dev, index, data, count); if (!err) { if (type_string_write_vars(argv[1], data, argv + 3)) { printf("Couldn't write to variables\n"); @@ -279,7 +344,13 @@ static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 index, count, err; + struct udevice *dev; void *data; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc < 3) return CMD_RET_USAGE; @@ -297,7 +368,7 @@ static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_USAGE; } - err = tpm_nv_write_value(index, data, count); + err = tpm_nv_write_value(dev, index, data, count); free(data); return report_return_code(err); @@ -309,8 +380,14 @@ static int do_tpm_oiap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 auth_handle, err; + struct udevice *dev; + int rc; - err = tpm_oiap(&auth_handle); + rc = get_tpm(&dev); + if (rc) + return rc; + + err = tpm_oiap(dev, &auth_handle); return report_return_code(err); } @@ -324,6 +401,11 @@ static int do_tpm_load_key_by_sha1(cmd_tbl_t *cmdtp, int flag, int argc, char * u8 usage_auth[DIGEST_LENGTH]; u8 parent_hash[DIGEST_LENGTH]; void *key; + struct udevice *dev; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc < 5) return CMD_RET_USAGE; @@ -360,6 +442,12 @@ static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag, int argc, u32 parent_handle, key_len, key_handle, err; u8 usage_auth[DIGEST_LENGTH]; void *key; + struct udevice *dev; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc < 5) return CMD_RET_USAGE; @@ -371,7 +459,7 @@ static int do_tpm_load_key2_oiap(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; parse_byte_string(argv[4], usage_auth, NULL); - err = tpm_load_key2_oiap(parent_handle, key, key_len, usage_auth, + err = tpm_load_key2_oiap(dev, parent_handle, key, key_len, usage_auth, &key_handle); if (!err) printf("Key handle is 0x%x\n", key_handle); @@ -386,6 +474,12 @@ static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag, int argc, u8 usage_auth[DIGEST_LENGTH]; u8 pub_key_buffer[TPM_PUBKEY_MAX_LENGTH]; size_t pub_key_len = sizeof(pub_key_buffer); + struct udevice *dev; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc < 3) return CMD_RET_USAGE; @@ -395,7 +489,7 @@ static int do_tpm_get_pub_key_oiap(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; parse_byte_string(argv[2], usage_auth, NULL); - err = tpm_get_pub_key_oiap(key_handle, usage_auth, pub_key_buffer, + err = tpm_get_pub_key_oiap(dev, key_handle, usage_auth, pub_key_buffer, &pub_key_len); if (!err) { printf("dump of received pub key structure:\n"); @@ -412,7 +506,13 @@ TPM_COMMAND_NO_ARG(tpm_end_oiap) static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; int type = 0; + int rc; + + rc = get_tpm(&dev); + if (rc) + return rc; if (argc != 3) return CMD_RET_USAGE; @@ -451,7 +551,7 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc, uint i; /* fetch list of already loaded resources in the TPM */ - err = tpm_get_capability(TPM_CAP_HANDLE, type, buf, + err = tpm_get_capability(dev, TPM_CAP_HANDLE, type, buf, sizeof(buf)); if (err) { printf("tpm_get_capability returned error %d.\n", err); @@ -460,7 +560,7 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc, res_count = get_unaligned_be16(buf); ptr = buf + 2; for (i = 0; i < res_count; ++i, ptr += 4) - tpm_flush_specific(get_unaligned_be32(ptr), type); + tpm_flush_specific(dev, get_unaligned_be32(ptr), type); } else { u32 handle = simple_strtoul(argv[2], NULL, 0); @@ -468,7 +568,7 @@ static int do_tpm_flush(cmd_tbl_t *cmdtp, int flag, int argc, printf("Illegal resource handle %s\n", argv[2]); return -1; } - tpm_flush_specific(cpu_to_be32(handle), type); + tpm_flush_specific(dev, cpu_to_be32(handle), type); } return 0; diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index ffbf35a75c..bb51834c47 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -16,7 +16,12 @@ static int do_tpm2_startup(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum tpm2_startup_types mode; + struct udevice *dev; + int ret; + ret = get_tpm(&dev); + if (ret) + return ret; if (argc != 2) return CMD_RET_USAGE; @@ -29,14 +34,19 @@ static int do_tpm2_startup(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - return report_return_code(tpm2_startup(mode)); + return report_return_code(tpm2_startup(dev, mode)); } static int do_tpm2_self_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum tpm2_yes_no full_test; + struct udevice *dev; + int ret; + ret = get_tpm(&dev); + if (ret) + return ret; if (argc != 2) return CMD_RET_USAGE; @@ -49,7 +59,7 @@ static int do_tpm2_self_test(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - return report_return_code(tpm2_self_test(full_test)); + return report_return_code(tpm2_self_test(dev, full_test)); } static int do_tpm2_clear(cmd_tbl_t *cmdtp, int flag, int argc, @@ -58,6 +68,12 @@ static int do_tpm2_clear(cmd_tbl_t *cmdtp, int flag, int argc, u32 handle = 0; const char *pw = (argc < 3) ? NULL : argv[2]; const ssize_t pw_sz = pw ? strlen(pw) : 0; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (argc < 2 || argc > 3) return CMD_RET_USAGE; @@ -72,7 +88,7 @@ static int do_tpm2_clear(cmd_tbl_t *cmdtp, int flag, int argc, else return CMD_RET_USAGE; - return report_return_code(tpm2_clear(handle, pw, pw_sz)); + return report_return_code(tpm2_clear(dev, handle, pw, pw_sz)); } static int do_tpm2_pcr_extend(cmd_tbl_t *cmdtp, int flag, int argc, @@ -88,7 +104,7 @@ static int do_tpm2_pcr_extend(cmd_tbl_t *cmdtp, int flag, int argc, if (argc != 3) return CMD_RET_USAGE; - ret = uclass_first_device_err(UCLASS_TPM, &dev); + ret = get_tpm(&dev); if (ret) return ret; @@ -99,7 +115,7 @@ static int do_tpm2_pcr_extend(cmd_tbl_t *cmdtp, int flag, int argc, if (index >= priv->pcr_count) return -EINVAL; - rc = tpm2_pcr_extend(index, digest); + rc = tpm2_pcr_extend(dev, index, digest); unmap_sysmem(digest); @@ -119,7 +135,7 @@ static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc, if (argc != 3) return CMD_RET_USAGE; - ret = uclass_first_device_err(UCLASS_TPM, &dev); + ret = get_tpm(&dev); if (ret) return ret; @@ -133,7 +149,7 @@ static int do_tpm_pcr_read(cmd_tbl_t *cmdtp, int flag, int argc, data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0); - rc = tpm2_pcr_read(index, priv->pcr_select_min, data, &updates); + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, data, &updates); if (!rc) { printf("PCR #%u content (%d known updates):\n", index, updates); print_byte_string(data, TPM2_DIGEST_LEN); @@ -151,6 +167,12 @@ static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc, u8 *data; size_t count; int i, j; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (argc != 5) return CMD_RET_USAGE; @@ -160,7 +182,7 @@ static int do_tpm_get_capability(cmd_tbl_t *cmdtp, int flag, int argc, data = map_sysmem(simple_strtoul(argv[3], NULL, 0), 0); count = simple_strtoul(argv[4], NULL, 0); - rc = tpm2_get_capability(capability, property, data, count); + rc = tpm2_get_capability(dev, capability, property, data, count); if (rc) goto unmap_data; @@ -186,6 +208,12 @@ static int do_tpm_dam_reset(cmd_tbl_t *cmdtp, int flag, int argc, { const char *pw = (argc < 2) ? NULL : argv[1]; const ssize_t pw_sz = pw ? strlen(pw) : 0; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (argc > 2) return CMD_RET_USAGE; @@ -193,7 +221,7 @@ static int do_tpm_dam_reset(cmd_tbl_t *cmdtp, int flag, int argc, if (pw_sz > TPM2_DIGEST_LEN) return -EINVAL; - return report_return_code(tpm2_dam_reset(pw, pw_sz)); + return report_return_code(tpm2_dam_reset(dev, pw, pw_sz)); } static int do_tpm_dam_parameters(cmd_tbl_t *cmdtp, int flag, int argc, @@ -208,6 +236,12 @@ static int do_tpm_dam_parameters(cmd_tbl_t *cmdtp, int flag, int argc, unsigned long int max_tries; unsigned long int recovery_time; unsigned long int lockout_recovery; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (argc < 4 || argc > 5) return CMD_RET_USAGE; @@ -229,7 +263,7 @@ static int do_tpm_dam_parameters(cmd_tbl_t *cmdtp, int flag, int argc, log(LOGC_NONE, LOGL_INFO, "- recoveryTime: %lu\n", recovery_time); log(LOGC_NONE, LOGL_INFO, "- lockoutRecovery: %lu\n", lockout_recovery); - return report_return_code(tpm2_dam_parameters(pw, pw_sz, max_tries, + return report_return_code(tpm2_dam_parameters(dev, pw, pw_sz, max_tries, recovery_time, lockout_recovery)); } @@ -242,6 +276,12 @@ static int do_tpm_change_auth(cmd_tbl_t *cmdtp, int flag, int argc, const char *oldpw = (argc == 3) ? NULL : argv[3]; const ssize_t newpw_sz = strlen(newpw); const ssize_t oldpw_sz = oldpw ? strlen(oldpw) : 0; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (argc < 3 || argc > 4) return CMD_RET_USAGE; @@ -260,7 +300,7 @@ static int do_tpm_change_auth(cmd_tbl_t *cmdtp, int flag, int argc, else return CMD_RET_USAGE; - return report_return_code(tpm2_change_auth(handle, newpw, newpw_sz, + return report_return_code(tpm2_change_auth(dev, handle, newpw, newpw_sz, oldpw, oldpw_sz)); } @@ -271,6 +311,12 @@ static int do_tpm_pcr_setauthpolicy(cmd_tbl_t *cmdtp, int flag, int argc, char *key = argv[2]; const char *pw = (argc < 4) ? NULL : argv[3]; const ssize_t pw_sz = pw ? strlen(pw) : 0; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (strlen(key) != TPM2_DIGEST_LEN) return -EINVAL; @@ -278,7 +324,7 @@ static int do_tpm_pcr_setauthpolicy(cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 3 || argc > 4) return CMD_RET_USAGE; - return report_return_code(tpm2_pcr_setauthpolicy(pw, pw_sz, index, + return report_return_code(tpm2_pcr_setauthpolicy(dev, pw, pw_sz, index, key)); } @@ -290,6 +336,12 @@ static int do_tpm_pcr_setauthvalue(cmd_tbl_t *cmdtp, int flag, const ssize_t key_sz = strlen(key); const char *pw = (argc < 4) ? NULL : argv[3]; const ssize_t pw_sz = pw ? strlen(pw) : 0; + struct udevice *dev; + int ret; + + ret = get_tpm(&dev); + if (ret) + return ret; if (strlen(key) != TPM2_DIGEST_LEN) return -EINVAL; @@ -297,7 +349,7 @@ static int do_tpm_pcr_setauthvalue(cmd_tbl_t *cmdtp, int flag, if (argc < 3 || argc > 4) return CMD_RET_USAGE; - return report_return_code(tpm2_pcr_setauthvalue(pw, pw_sz, index, + return report_return_code(tpm2_pcr_setauthvalue(dev, pw, pw_sz, index, key, key_sz)); } diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index f21ad5d3cf..56a5aa4aa5 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -7,6 +7,7 @@ #include #include #include +#include "tpm-user-utils.h" /* Prints error and returns on failure */ #define TPM_CHECK(tpm_command) do { \ @@ -28,26 +29,26 @@ #define PHYS_PRESENCE 4 #define PRESENCE 8 -static uint32_t TlclStartupIfNeeded(void) +static uint32_t TlclStartupIfNeeded(struct udevice *dev) { - uint32_t result = tpm_startup(TPM_ST_CLEAR); + uint32_t result = tpm_startup(dev, TPM_ST_CLEAR); return result == TPM_INVALID_POSTINIT ? TPM_SUCCESS : result; } -static int test_timer(void) +static int test_timer(struct udevice *dev) { printf("get_timer(0) = %lu\n", get_timer(0)); return 0; } -static uint32_t tpm_get_flags(uint8_t *disable, uint8_t *deactivated, - uint8_t *nvlocked) +static uint32_t tpm_get_flags(struct udevice *dev, uint8_t *disable, + uint8_t *deactivated, uint8_t *nvlocked) { struct tpm_permanent_flags pflags; uint32_t result; - result = tpm_get_permanent_flags(&pflags); + result = tpm_get_permanent_flags(dev, &pflags); if (result) return result; if (disable) @@ -62,79 +63,79 @@ static uint32_t tpm_get_flags(uint8_t *disable, uint8_t *deactivated, return 0; } -static uint32_t tpm_nv_write_value_lock(uint32_t index) +static uint32_t tpm_nv_write_value_lock(struct udevice *dev, uint32_t index) { debug("TPM: Write lock 0x%x\n", index); - return tpm_nv_write_value(index, NULL, 0); + return tpm_nv_write_value(dev, index, NULL, 0); } -static int tpm_is_owned(void) +static int tpm_is_owned(struct udevice *dev) { uint8_t response[TPM_PUBEK_SIZE]; uint32_t result; - result = tpm_read_pubek(response, sizeof(response)); + result = tpm_read_pubek(dev, response, sizeof(response)); return result != TPM_SUCCESS; } -static int test_early_extend(void) +static int test_early_extend(struct udevice *dev) { uint8_t value_in[20]; uint8_t value_out[20]; printf("Testing earlyextend ..."); - tpm_init(); - TPM_CHECK(tpm_startup(TPM_ST_CLEAR)); - TPM_CHECK(tpm_continue_self_test()); - TPM_CHECK(tpm_extend(1, value_in, value_out)); + tpm_init(dev); + TPM_CHECK(tpm_startup(dev, TPM_ST_CLEAR)); + TPM_CHECK(tpm_continue_self_test(dev)); + TPM_CHECK(tpm_extend(dev, 1, value_in, value_out)); printf("done\n"); return 0; } -static int test_early_nvram(void) +static int test_early_nvram(struct udevice *dev) { uint32_t x; printf("Testing earlynvram ..."); - tpm_init(); - TPM_CHECK(tpm_startup(TPM_ST_CLEAR)); - TPM_CHECK(tpm_continue_self_test()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_nv_read_value(INDEX0, (uint8_t *)&x, sizeof(x))); + tpm_init(dev); + TPM_CHECK(tpm_startup(dev, TPM_ST_CLEAR)); + TPM_CHECK(tpm_continue_self_test(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x))); printf("done\n"); return 0; } -static int test_early_nvram2(void) +static int test_early_nvram2(struct udevice *dev) { uint32_t x; printf("Testing earlynvram2 ..."); - tpm_init(); - TPM_CHECK(tpm_startup(TPM_ST_CLEAR)); - TPM_CHECK(tpm_continue_self_test()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_nv_write_value(INDEX0, (uint8_t *)&x, sizeof(x))); + tpm_init(dev); + TPM_CHECK(tpm_startup(dev, TPM_ST_CLEAR)); + TPM_CHECK(tpm_continue_self_test(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_nv_write_value(dev, INDEX0, (uint8_t *)&x, sizeof(x))); printf("done\n"); return 0; } -static int test_enable(void) +static int test_enable(struct udevice *dev) { uint8_t disable = 0, deactivated = 0; printf("Testing enable ...\n"); - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_self_test_full()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL)); + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_self_test_full(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_get_flags(dev, &disable, &deactivated, NULL)); printf("\tdisable is %d, deactivated is %d\n", disable, deactivated); - TPM_CHECK(tpm_physical_enable()); - TPM_CHECK(tpm_physical_set_deactivated(0)); - TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL)); + TPM_CHECK(tpm_physical_enable(dev)); + TPM_CHECK(tpm_physical_set_deactivated(dev, 0)); + TPM_CHECK(tpm_get_flags(dev, &disable, &deactivated, NULL)); printf("\tdisable is %d, deactivated is %d\n", disable, deactivated); if (disable == 1 || deactivated == 1) printf("\tfailed to enable or activate\n"); @@ -147,27 +148,27 @@ static int test_enable(void) reset_cpu(0); \ } while (0) -static int test_fast_enable(void) +static int test_fast_enable(struct udevice *dev) { uint8_t disable = 0, deactivated = 0; int i; printf("Testing fastenable ...\n"); - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_self_test_full()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL)); + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_self_test_full(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_get_flags(dev, &disable, &deactivated, NULL)); printf("\tdisable is %d, deactivated is %d\n", disable, deactivated); for (i = 0; i < 2; i++) { - TPM_CHECK(tpm_force_clear()); - TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL)); + TPM_CHECK(tpm_force_clear(dev)); + TPM_CHECK(tpm_get_flags(dev, &disable, &deactivated, NULL)); printf("\tdisable is %d, deactivated is %d\n", disable, deactivated); assert(disable == 1 && deactivated == 1); - TPM_CHECK(tpm_physical_enable()); - TPM_CHECK(tpm_physical_set_deactivated(0)); - TPM_CHECK(tpm_get_flags(&disable, &deactivated, NULL)); + TPM_CHECK(tpm_physical_enable(dev)); + TPM_CHECK(tpm_physical_set_deactivated(dev, 0)); + TPM_CHECK(tpm_get_flags(dev, &disable, &deactivated, NULL)); printf("\tdisable is %d, deactivated is %d\n", disable, deactivated); assert(disable == 0 && deactivated == 0); @@ -176,105 +177,109 @@ static int test_fast_enable(void) return 0; } -static int test_global_lock(void) +static int test_global_lock(struct udevice *dev) { uint32_t zero = 0; uint32_t result; uint32_t x; printf("Testing globallock ...\n"); - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_self_test_full()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_nv_read_value(INDEX0, (uint8_t *)&x, sizeof(x))); - TPM_CHECK(tpm_nv_write_value(INDEX0, (uint8_t *)&zero, + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_self_test_full(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_write_value(dev, INDEX0, (uint8_t *)&zero, sizeof(uint32_t))); - TPM_CHECK(tpm_nv_read_value(INDEX1, (uint8_t *)&x, sizeof(x))); - TPM_CHECK(tpm_nv_write_value(INDEX1, (uint8_t *)&zero, + TPM_CHECK(tpm_nv_read_value(dev, INDEX1, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_write_value(dev, INDEX1, (uint8_t *)&zero, sizeof(uint32_t))); - TPM_CHECK(tpm_set_global_lock()); + TPM_CHECK(tpm_set_global_lock(dev)); /* Verifies that write to index0 fails */ x = 1; - result = tpm_nv_write_value(INDEX0, (uint8_t *)&x, sizeof(x)); + result = tpm_nv_write_value(dev, INDEX0, (uint8_t *)&x, sizeof(x)); assert(result == TPM_AREA_LOCKED); - TPM_CHECK(tpm_nv_read_value(INDEX0, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x))); assert(x == 0); /* Verifies that write to index1 is still possible */ x = 2; - TPM_CHECK(tpm_nv_write_value(INDEX1, (uint8_t *)&x, sizeof(x))); - TPM_CHECK(tpm_nv_read_value(INDEX1, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_write_value(dev, INDEX1, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_read_value(dev, INDEX1, (uint8_t *)&x, sizeof(x))); assert(x == 2); /* Turns off PP */ - tpm_tsc_physical_presence(PHYS_PRESENCE); + tpm_tsc_physical_presence(dev, PHYS_PRESENCE); /* Verifies that write to index1 fails */ x = 3; - result = tpm_nv_write_value(INDEX1, (uint8_t *)&x, sizeof(x)); + result = tpm_nv_write_value(dev, INDEX1, (uint8_t *)&x, sizeof(x)); assert(result == TPM_BAD_PRESENCE); - TPM_CHECK(tpm_nv_read_value(INDEX1, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_read_value(dev, INDEX1, (uint8_t *)&x, sizeof(x))); assert(x == 2); printf("\tdone\n"); return 0; } -static int test_lock(void) +static int test_lock(struct udevice *dev) { printf("Testing lock ...\n"); - tpm_init(); - tpm_startup(TPM_ST_CLEAR); - tpm_self_test_full(); - tpm_tsc_physical_presence(PRESENCE); - tpm_nv_write_value_lock(INDEX0); + tpm_init(dev); + tpm_startup(dev, TPM_ST_CLEAR); + tpm_self_test_full(dev); + tpm_tsc_physical_presence(dev, PRESENCE); + tpm_nv_write_value_lock(dev, INDEX0); printf("\tLocked 0x%x\n", INDEX0); printf("\tdone\n"); return 0; } -static void initialise_spaces(void) +static void initialise_spaces(struct udevice *dev) { uint32_t zero = 0; uint32_t perm = TPM_NV_PER_WRITE_STCLEAR | TPM_NV_PER_PPWRITE; printf("\tInitialising spaces\n"); - tpm_nv_set_locked(); /* useful only the first time */ - tpm_nv_define_space(INDEX0, perm, 4); - tpm_nv_write_value(INDEX0, (uint8_t *)&zero, 4); - tpm_nv_define_space(INDEX1, perm, 4); - tpm_nv_write_value(INDEX1, (uint8_t *)&zero, 4); - tpm_nv_define_space(INDEX2, perm, 4); - tpm_nv_write_value(INDEX2, (uint8_t *)&zero, 4); - tpm_nv_define_space(INDEX3, perm, 4); - tpm_nv_write_value(INDEX3, (uint8_t *)&zero, 4); + tpm_nv_set_locked(dev); /* useful only the first time */ + tpm_nv_define_space(dev, INDEX0, perm, 4); + tpm_nv_write_value(dev, INDEX0, (uint8_t *)&zero, 4); + tpm_nv_define_space(dev, INDEX1, perm, 4); + tpm_nv_write_value(dev, INDEX1, (uint8_t *)&zero, 4); + tpm_nv_define_space(dev, INDEX2, perm, 4); + tpm_nv_write_value(dev, INDEX2, (uint8_t *)&zero, 4); + tpm_nv_define_space(dev, INDEX3, perm, 4); + tpm_nv_write_value(dev, INDEX3, (uint8_t *)&zero, 4); perm = TPM_NV_PER_READ_STCLEAR | TPM_NV_PER_WRITE_STCLEAR | TPM_NV_PER_PPWRITE; - tpm_nv_define_space(INDEX_INITIALISED, perm, 1); + tpm_nv_define_space(dev, INDEX_INITIALISED, perm, 1); } -static int test_readonly(void) +static int test_readonly(struct udevice *dev) { uint8_t c; uint32_t index_0, index_1, index_2, index_3; int read0, read1, read2, read3; printf("Testing readonly ...\n"); - tpm_init(); - tpm_startup(TPM_ST_CLEAR); - tpm_self_test_full(); - tpm_tsc_physical_presence(PRESENCE); + tpm_init(dev); + tpm_startup(dev, TPM_ST_CLEAR); + tpm_self_test_full(dev); + tpm_tsc_physical_presence(dev, PRESENCE); /* * Checks if initialisation has completed by trying to read-lock a * space that's created at the end of initialisation */ - if (tpm_nv_read_value(INDEX_INITIALISED, &c, 0) == TPM_BADINDEX) { + if (tpm_nv_read_value(dev, INDEX_INITIALISED, &c, 0) == TPM_BADINDEX) { /* The initialisation did not complete */ - initialise_spaces(); + initialise_spaces(dev); } /* Checks if spaces are OK or messed up */ - read0 = tpm_nv_read_value(INDEX0, (uint8_t *)&index_0, sizeof(index_0)); - read1 = tpm_nv_read_value(INDEX1, (uint8_t *)&index_1, sizeof(index_1)); - read2 = tpm_nv_read_value(INDEX2, (uint8_t *)&index_2, sizeof(index_2)); - read3 = tpm_nv_read_value(INDEX3, (uint8_t *)&index_3, sizeof(index_3)); + read0 = tpm_nv_read_value(dev, INDEX0, (uint8_t *)&index_0, + sizeof(index_0)); + read1 = tpm_nv_read_value(dev, INDEX1, (uint8_t *)&index_1, + sizeof(index_1)); + read2 = tpm_nv_read_value(dev, INDEX2, (uint8_t *)&index_2, + sizeof(index_2)); + read3 = tpm_nv_read_value(dev, INDEX3, (uint8_t *)&index_3, + sizeof(index_3)); if (read0 || read1 || read2 || read3) { printf("Invalid contents\n"); return 0; @@ -285,12 +290,14 @@ static int test_readonly(void) * I really wish I could use the imperative. */ index_0 += 1; - if (tpm_nv_write_value(INDEX0, (uint8_t *)&index_0, sizeof(index_0) != + if (tpm_nv_write_value(dev, INDEX0, (uint8_t *)&index_0, + sizeof(index_0) != TPM_SUCCESS)) { pr_err("\tcould not write index 0\n"); } - tpm_nv_write_value_lock(INDEX0); - if (tpm_nv_write_value(INDEX0, (uint8_t *)&index_0, sizeof(index_0)) == + tpm_nv_write_value_lock(dev, INDEX0); + if (tpm_nv_write_value(dev, INDEX0, (uint8_t *)&index_0, + sizeof(index_0)) == TPM_SUCCESS) pr_err("\tindex 0 is not locked\n"); @@ -298,49 +305,49 @@ static int test_readonly(void) return 0; } -static int test_redefine_unowned(void) +static int test_redefine_unowned(struct udevice *dev) { uint32_t perm; uint32_t result; uint32_t x; printf("Testing redefine_unowned ..."); - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_self_test_full()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - assert(!tpm_is_owned()); + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_self_test_full(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + assert(!tpm_is_owned(dev)); /* Ensures spaces exist. */ - TPM_CHECK(tpm_nv_read_value(INDEX0, (uint8_t *)&x, sizeof(x))); - TPM_CHECK(tpm_nv_read_value(INDEX1, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x))); + TPM_CHECK(tpm_nv_read_value(dev, INDEX1, (uint8_t *)&x, sizeof(x))); /* Redefines spaces a couple of times. */ perm = TPM_NV_PER_PPWRITE | TPM_NV_PER_GLOBALLOCK; - TPM_CHECK(tpm_nv_define_space(INDEX0, perm, 2 * sizeof(uint32_t))); - TPM_CHECK(tpm_nv_define_space(INDEX0, perm, sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX0, perm, 2 * sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX0, perm, sizeof(uint32_t))); perm = TPM_NV_PER_PPWRITE; - TPM_CHECK(tpm_nv_define_space(INDEX1, perm, 2 * sizeof(uint32_t))); - TPM_CHECK(tpm_nv_define_space(INDEX1, perm, sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX1, perm, 2 * sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX1, perm, sizeof(uint32_t))); /* Sets the global lock */ - tpm_set_global_lock(); + tpm_set_global_lock(dev); /* Verifies that index0 cannot be redefined */ - result = tpm_nv_define_space(INDEX0, perm, sizeof(uint32_t)); + result = tpm_nv_define_space(dev, INDEX0, perm, sizeof(uint32_t)); assert(result == TPM_AREA_LOCKED); /* Checks that index1 can */ - TPM_CHECK(tpm_nv_define_space(INDEX1, perm, 2 * sizeof(uint32_t))); - TPM_CHECK(tpm_nv_define_space(INDEX1, perm, sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX1, perm, 2 * sizeof(uint32_t))); + TPM_CHECK(tpm_nv_define_space(dev, INDEX1, perm, sizeof(uint32_t))); /* Turns off PP */ - tpm_tsc_physical_presence(PHYS_PRESENCE); + tpm_tsc_physical_presence(dev, PHYS_PRESENCE); /* Verifies that neither index0 nor index1 can be redefined */ - result = tpm_nv_define_space(INDEX0, perm, sizeof(uint32_t)); + result = tpm_nv_define_space(dev, INDEX0, perm, sizeof(uint32_t)); assert(result == TPM_BAD_PRESENCE); - result = tpm_nv_define_space(INDEX1, perm, sizeof(uint32_t)); + result = tpm_nv_define_space(dev, INDEX1, perm, sizeof(uint32_t)); assert(result == TPM_BAD_PRESENCE); printf("done\n"); @@ -350,38 +357,39 @@ static int test_redefine_unowned(void) #define PERMPPGL (TPM_NV_PER_PPWRITE | TPM_NV_PER_GLOBALLOCK) #define PERMPP TPM_NV_PER_PPWRITE -static int test_space_perm(void) +static int test_space_perm(struct udevice *dev) { uint32_t perm; printf("Testing spaceperm ..."); - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_continue_self_test()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_get_permissions(INDEX0, &perm)); + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_continue_self_test(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_get_permissions(dev, INDEX0, &perm)); assert((perm & PERMPPGL) == PERMPPGL); - TPM_CHECK(tpm_get_permissions(INDEX1, &perm)); + TPM_CHECK(tpm_get_permissions(dev, INDEX1, &perm)); assert((perm & PERMPP) == PERMPP); printf("done\n"); return 0; } -static int test_startup(void) +static int test_startup(struct udevice *dev) { uint32_t result; + printf("Testing startup ...\n"); - tpm_init(); - result = tpm_startup(TPM_ST_CLEAR); + tpm_init(dev); + result = tpm_startup(dev, TPM_ST_CLEAR); if (result != 0 && result != TPM_INVALID_POSTINIT) printf("\ttpm startup failed with 0x%x\n", result); - result = tpm_get_flags(NULL, NULL, NULL); + result = tpm_get_flags(dev, NULL, NULL, NULL); if (result != 0) printf("\ttpm getflags failed with 0x%x\n", result); printf("\texecuting SelfTestFull\n"); - tpm_self_test_full(); - result = tpm_get_flags(NULL, NULL, NULL); + tpm_self_test_full(dev); + result = tpm_get_flags(dev, NULL, NULL, NULL); if (result != 0) printf("\ttpm getflags failed with 0x%x\n", result); printf("\tdone\n"); @@ -410,45 +418,48 @@ static int test_startup(void) } while (0) -static int test_timing(void) +static int test_timing(struct udevice *dev) { - uint32_t x; uint8_t in[20], out[20]; + uint32_t x; printf("Testing timing ..."); - tpm_init(); - TTPM_CHECK(TlclStartupIfNeeded(), 50); - TTPM_CHECK(tpm_continue_self_test(), 100); - TTPM_CHECK(tpm_self_test_full(), 1000); - TTPM_CHECK(tpm_tsc_physical_presence(PRESENCE), 100); - TTPM_CHECK(tpm_nv_write_value(INDEX0, (uint8_t *)&x, sizeof(x)), 100); - TTPM_CHECK(tpm_nv_read_value(INDEX0, (uint8_t *)&x, sizeof(x)), 100); - TTPM_CHECK(tpm_extend(0, in, out), 200); - TTPM_CHECK(tpm_set_global_lock(), 50); - TTPM_CHECK(tpm_tsc_physical_presence(PHYS_PRESENCE), 100); + tpm_init(dev); + TTPM_CHECK(TlclStartupIfNeeded(dev), 50); + TTPM_CHECK(tpm_continue_self_test(dev), 100); + TTPM_CHECK(tpm_self_test_full(dev), 1000); + TTPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE), 100); + TTPM_CHECK(tpm_nv_write_value(dev, INDEX0, (uint8_t *)&x, sizeof(x)), + 100); + TTPM_CHECK(tpm_nv_read_value(dev, INDEX0, (uint8_t *)&x, sizeof(x)), + 100); + TTPM_CHECK(tpm_extend(dev, 0, in, out), 200); + TTPM_CHECK(tpm_set_global_lock(dev), 50); + TTPM_CHECK(tpm_tsc_physical_presence(dev, PHYS_PRESENCE), 100); printf("done\n"); return 0; } #define TPM_MAX_NV_WRITES_NOOWNER 64 -static int test_write_limit(void) +static int test_write_limit(struct udevice *dev) { - printf("Testing writelimit ...\n"); - int i; uint32_t result; + int i; - tpm_init(); - TPM_CHECK(TlclStartupIfNeeded()); - TPM_CHECK(tpm_self_test_full()); - TPM_CHECK(tpm_tsc_physical_presence(PRESENCE)); - TPM_CHECK(tpm_force_clear()); - TPM_CHECK(tpm_physical_enable()); - TPM_CHECK(tpm_physical_set_deactivated(0)); + printf("Testing writelimit ...\n"); + tpm_init(dev); + TPM_CHECK(TlclStartupIfNeeded(dev)); + TPM_CHECK(tpm_self_test_full(dev)); + TPM_CHECK(tpm_tsc_physical_presence(dev, PRESENCE)); + TPM_CHECK(tpm_force_clear(dev)); + TPM_CHECK(tpm_physical_enable(dev)); + TPM_CHECK(tpm_physical_set_deactivated(dev, 0)); for (i = 0; i < TPM_MAX_NV_WRITES_NOOWNER + 2; i++) { printf("\twriting %d\n", i); - result = tpm_nv_write_value(INDEX0, (uint8_t *)&i, sizeof(i)); + result = tpm_nv_write_value(dev, INDEX0, (uint8_t *)&i, + sizeof(i)); switch (result) { case TPM_SUCCESS: break; @@ -461,12 +472,12 @@ static int test_write_limit(void) } /* Reset write count */ - TPM_CHECK(tpm_force_clear()); - TPM_CHECK(tpm_physical_enable()); - TPM_CHECK(tpm_physical_set_deactivated(0)); + TPM_CHECK(tpm_force_clear(dev)); + TPM_CHECK(tpm_physical_enable(dev)); + TPM_CHECK(tpm_physical_set_deactivated(dev, 0)); /* Try writing again. */ - TPM_CHECK(tpm_nv_write_value(INDEX0, (uint8_t *)&i, sizeof(i))); + TPM_CHECK(tpm_nv_write_value(dev, INDEX0, (uint8_t *)&i, sizeof(i))); printf("\tdone\n"); return 0; } @@ -475,7 +486,13 @@ static int test_write_limit(void) int do_test_##XFUNC(cmd_tbl_t *cmd_tbl, int flag, int argc, \ char * const argv[]) \ { \ - return test_##XFUNC(); \ + struct udevice *dev; \ + int ret; \ +\ + ret = get_tpm(&dev); \ + if (ret) \ + return ret; \ + return test_##XFUNC(dev); \ } #define VOIDENT(XNAME) \ diff --git a/cmd/ubi.c b/cmd/ubi.c index 2b74a98144..a12ac703eb 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -101,7 +101,6 @@ static int ubi_check(char *name) return 1; } - static int verify_mkvol_req(const struct ubi_device *ubi, const struct ubi_mkvol_req *req) { @@ -415,7 +414,7 @@ static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset) return 0; } -int ubi_detach(void) +static int ubi_detach(void) { #ifdef CONFIG_CMD_UBIFS /* @@ -473,7 +472,6 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 2) return CMD_RET_USAGE; - if (strcmp(argv[1], "detach") == 0) { if (argc < 2) return CMD_RET_USAGE; @@ -481,7 +479,6 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ubi_detach(); } - if (strcmp(argv[1], "part") == 0) { const char *vid_header_offset = NULL; diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c index ba1f66a5de..808ed974fa 100644 --- a/cmd/usb_gadget_sdp.c +++ b/cmd/usb_gadget_sdp.c @@ -20,7 +20,7 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *usb_controller = argv[1]; int controller_index = simple_strtoul(usb_controller, NULL, 0); - board_usb_init(controller_index, USB_INIT_DEVICE); + usb_gadget_initialize(controller_index); g_dnl_clear_detach(); g_dnl_register("usb_dnl_sdp"); @@ -37,7 +37,7 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) exit: g_dnl_unregister(); - board_usb_cleanup(controller_index, USB_INIT_DEVICE); + usb_gadget_release(controller_index); return ret; } diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index 0d551141e0..753ae4f42a 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -160,7 +160,7 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, controller_index = (unsigned int)(simple_strtoul( usb_controller, NULL, 0)); - if (board_usb_init(controller_index, USB_INIT_DEVICE)) { + if (usb_gadget_initialize(controller_index)) { pr_err("Couldn't init USB controller.\n"); rc = CMD_RET_FAILURE; goto cleanup_ums_init; @@ -231,7 +231,7 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, cleanup_register: g_dnl_unregister(); cleanup_board: - board_usb_cleanup(controller_index, USB_INIT_DEVICE); + usb_gadget_release(controller_index); cleanup_ums_init: ums_fini(); diff --git a/cmd/virtio.c b/cmd/virtio.c new file mode 100644 index 0000000000..b7082bc63a --- /dev/null +++ b/cmd/virtio.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include + +static int virtio_curr_dev; + +static int do_virtio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc == 2 && !strcmp(argv[1], "scan")) { + /* make sure all virtio devices are enumerated */ + virtio_init(); + + return CMD_RET_SUCCESS; + } + + return blk_common_cmd(argc, argv, IF_TYPE_VIRTIO, &virtio_curr_dev); +} + +U_BOOT_CMD( + virtio, 8, 1, do_virtio, + "virtio block devices sub-system", + "scan - initialize virtio bus\n" + "virtio info - show all available virtio block devices\n" + "virtio device [dev] - show or set current virtio block device\n" + "virtio part [dev] - print partition table of one or all virtio block devices\n" + "virtio read addr blk# cnt - read `cnt' blocks starting at block\n" + " `blk#' to memory address `addr'\n" + "virtio write addr blk# cnt - write `cnt' blocks starting at block\n" + " `blk#' from memory address `addr'" +); diff --git a/common/Kconfig b/common/Kconfig index d7300c212f..57bd16d962 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -27,6 +27,15 @@ config SPL_BOOTSTAGE information when SPL finishes and load it when U-Boot proper starts up. +config TPL_BOOTSTAGE + bool "Boot timing and reported in TPL" + depends on BOOTSTAGE + help + Enable recording of boot time in SPL. To make this visible to U-Boot + proper, enable BOOTSTAGE_STASH as well. This will stash the timing + information when TPL finishes and load it when U-Boot proper starts + up. + config BOOTSTAGE_REPORT bool "Display a detailed boot timing report before booting the OS" depends on BOOTSTAGE @@ -290,6 +299,10 @@ config SPL_LOGLEVEL int default LOGLEVEL +config TPL_LOGLEVEL + int + default LOGLEVEL + config SILENT_CONSOLE bool "Support a silent console" help @@ -444,6 +457,16 @@ config LOG config SPL_LOG bool "Enable logging support in SPL" + depends on LOG + help + This enables support for logging of status and debug messages. These + can be displayed on the console, recorded in a memory buffer, or + discarded if not needed. Logging supports various categories and + levels of severity. + +config TPL_LOG + bool "Enable logging support in TPL" + depends on LOG help This enables support for logging of status and debug messages. These can be displayed on the console, recorded in a memory buffer, or @@ -486,6 +509,24 @@ config SPL_LOG_MAX_LEVEL 6 - detail 7 - debug +config TPL_LOG_MAX_LEVEL + int "Maximum log level to record in TPL" + depends on TPL_LOG + default 3 + help + This selects the maximum log level that will be recorded. Any value + higher than this will be ignored. If possible log statements below + this level will be discarded at build time. Levels: + + 0 - panic + 1 - critical + 2 - error + 3 - warning + 4 - note + 5 - info + 6 - detail + 7 - debug + config LOG_CONSOLE bool "Allow log output to the console" depends on LOG @@ -496,9 +537,19 @@ config LOG_CONSOLE log message is shown - other details like level, category, file and line number are omitted. -config LOG_SPL_CONSOLE +config SPL_LOG_CONSOLE bool "Allow log output to the console in SPL" - depends on LOG_SPL + depends on SPL_LOG + default y + help + Enables a log driver which writes log records to the console. + Generally the console is the serial port or LCD display. Only the + log message is shown - other details like level, category, file and + line number are omitted. + +config TPL_LOG_CONSOLE + bool "Allow log output to the console in SPL" + depends on TPL_LOG default y help Enables a log driver which writes log records to the console. @@ -660,6 +711,22 @@ config AVB_VERIFY * Helpers to access MMC, similar to drivers/fastboot/fb_mmc.c. * Helpers to alloc/init/free avb ops. +config SPL_HASH + bool # "Support hashing API (SHA1, SHA256, etc.)" + help + This provides a way to hash data in memory using various supported + algorithms (such as SHA1, MD5, CRC32). The API is defined in hash.h + and the algorithms it supports are defined in common/hash.c. See + also CMD_HASH for command-line access. + +config TPL_HASH + bool # "Support hashing API (SHA1, SHA256, etc.)" + help + This provides a way to hash data in memory using various supported + algorithms (such as SHA1, MD5, CRC32). The API is defined in hash.h + and the algorithms it supports are defined in common/hash.c. See + also CMD_HASH for command-line access. + endmenu menu "Update support" @@ -683,4 +750,52 @@ config UPDATE_TFTP_MSEC_MAX endmenu +menu "Blob list" + +config BLOBLIST + bool "Support for a bloblist" + help + This enables support for a bloblist in U-Boot, which can be passed + from TPL to SPL to U-Boot proper (and potentially to Linux). The + blob list supports multiple binary blobs of data, each with a tag, + so that different U-Boot components can store data which can survive + through to the next stage of the boot. + +config SPL_BLOBLIST + bool "Support for a bloblist in SPL" + depends on BLOBLIST + default y if SPL + help + This enables a bloblist in SPL. If this is the first part of U-Boot + to run, then the bloblist is set up in SPL and passed to U-Boot + proper. If TPL also has a bloblist, then SPL uses the one from there. + +config TPL_BLOBLIST + bool "Support for a bloblist in TPL" + depends on BLOBLIST + default y if TPL + help + This enables a bloblist in TPL. The bloblist is set up in TPL and + passed to SPL and U-Boot proper. + +config BLOBLIST_SIZE + hex "Size of bloblist" + depends on BLOBLIST + default 0x400 + help + Sets the size of the bloblist in bytes. This must include all + overhead (alignment, bloblist header, record header). The bloblist + is set up in the first part of U-Boot to run (TPL, SPL or U-Boot + proper), and this sane bloblist is used for subsequent stages. + +config BLOBLIST_ADDR + hex "Address of bloblist" + depends on BLOBLIST + default 0xe000 if SANDBOX + help + Sets the address of the bloblist, set up by the first part of U-Boot + which runs. Subsequent U-Boot stages typically use the same address. + +endmenu + source "common/spl/Kconfig" diff --git a/common/Makefile b/common/Makefile index a2388364d9..0de60b3ced 100644 --- a/common/Makefile +++ b/common/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_MII) += miiphyutil.o obj-$(CONFIG_CMD_MII) += miiphyutil.o obj-$(CONFIG_PHYLIB) += miiphyutil.o -ifdef CONFIG_CMD_USB +ifdef CONFIG_USB obj-y += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o endif @@ -61,6 +61,7 @@ obj-$(CONFIG_CMDLINE) += cli_readline.o cli_simple.o endif # !CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o +obj-$(CONFIG_$(SPL_TPL_)BLOBLIST) += bloblist.o ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_DFU_SUPPORT @@ -68,15 +69,20 @@ obj-$(CONFIG_DFU_OVER_USB) += dfu.o endif obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o +obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o + ifdef CONFIG_SPL_USB_HOST_SUPPORT obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o obj-$(CONFIG_USB_STORAGE) += usb_storage.o +else +obj-$(CONFIG_USB_MUSB_HOST) += usb.o endif -endif +endif # CONFIG_SPL_BUILD + #others obj-$(CONFIG_DDR_SPD) += ddr_spd.o obj-$(CONFIG_SPD_EEPROM) += ddr_spd.o @@ -90,14 +96,16 @@ obj-$(CONFIG_SPL_SERIAL_SUPPORT) += console.o endif else obj-y += console.o -endif +endif # CONFIG_SPL_BUILD + obj-$(CONFIG_CROS_EC) += cros_ec.o obj-y += dlmalloc.o ifdef CONFIG_SYS_MALLOC_F -ifneq ($(CONFIG_$(SPL_)SYS_MALLOC_F_LEN),0) +ifneq ($(CONFIG_$(SPL_TPL_)SYS_MALLOC_F_LEN),0) obj-y += malloc_simple.o endif endif + obj-y += image.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o @@ -118,8 +126,8 @@ obj-y += cli.o obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o obj-$(CONFIG_DFU_OVER_USB) += dfu.o obj-y += command.o -obj-$(CONFIG_$(SPL_)LOG) += log.o -obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o +obj-$(CONFIG_$(SPL_TPL_)LOG) += log.o +obj-$(CONFIG_$(SPL_TPL_)LOG_CONSOLE) += log_console.o obj-y += s_record.o obj-$(CONFIG_CMD_LOADB) += xyzModem.o obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o diff --git a/common/bloblist.c b/common/bloblist.c new file mode 100644 index 0000000000..b4cf169b05 --- /dev/null +++ b/common/bloblist.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct bloblist_rec *bloblist_first_blob(struct bloblist_hdr *hdr) +{ + if (hdr->alloced <= hdr->hdr_size) + return NULL; + return (struct bloblist_rec *)((void *)hdr + hdr->hdr_size); +} + +struct bloblist_rec *bloblist_next_blob(struct bloblist_hdr *hdr, + struct bloblist_rec *rec) +{ + ulong offset; + + offset = (void *)rec - (void *)hdr; + offset += rec->hdr_size + ALIGN(rec->size, BLOBLIST_ALIGN); + if (offset >= hdr->alloced) + return NULL; + return (struct bloblist_rec *)((void *)hdr + offset); +} + +#define foreach_rec(_rec, _hdr) \ + for (_rec = bloblist_first_blob(_hdr); \ + _rec; \ + _rec = bloblist_next_blob(_hdr, _rec)) + +static struct bloblist_rec *bloblist_findrec(uint tag) +{ + struct bloblist_hdr *hdr = gd->bloblist; + struct bloblist_rec *rec; + + if (!hdr) + return NULL; + + foreach_rec(rec, hdr) { + if (rec->tag == tag) + return rec; + } + + return NULL; +} + +static int bloblist_addrec(uint tag, int size, struct bloblist_rec **recp) +{ + struct bloblist_hdr *hdr = gd->bloblist; + struct bloblist_rec *rec; + int new_alloced; + + new_alloced = hdr->alloced + sizeof(*rec) + + ALIGN(size, BLOBLIST_ALIGN); + if (new_alloced >= hdr->size) { + log(LOGC_BLOBLIST, LOGL_ERR, + "Failed to allocate %x bytes size=%x, need size>=%x\n", + size, hdr->size, new_alloced); + return log_msg_ret("bloblist add", -ENOSPC); + } + rec = (void *)hdr + hdr->alloced; + hdr->alloced = new_alloced; + + rec->tag = tag; + rec->hdr_size = sizeof(*rec); + rec->size = size; + rec->spare = 0; + *recp = rec; + + return 0; +} + +static int bloblist_ensurerec(uint tag, struct bloblist_rec **recp, int size) +{ + struct bloblist_rec *rec; + + rec = bloblist_findrec(tag); + if (rec) { + if (size && size != rec->size) + return -ESPIPE; + } else { + int ret; + + ret = bloblist_addrec(tag, size, &rec); + if (ret) + return ret; + } + *recp = rec; + + return 0; +} + +void *bloblist_find(uint tag, int size) +{ + struct bloblist_rec *rec; + + rec = bloblist_findrec(tag); + if (!rec) + return NULL; + if (size && size != rec->size) + return NULL; + + return (void *)rec + rec->hdr_size; +} + +void *bloblist_add(uint tag, int size) +{ + struct bloblist_rec *rec; + + if (bloblist_addrec(tag, size, &rec)) + return NULL; + + return rec + 1; +} + +int bloblist_ensure_size(uint tag, int size, void **blobp) +{ + struct bloblist_rec *rec; + int ret; + + ret = bloblist_ensurerec(tag, &rec, size); + if (ret) + return ret; + *blobp = (void *)rec + rec->hdr_size; + + return 0; +} + +void *bloblist_ensure(uint tag, int size) +{ + struct bloblist_rec *rec; + + if (bloblist_ensurerec(tag, &rec, size)) + return NULL; + + return (void *)rec + rec->hdr_size; +} + +static u32 bloblist_calc_chksum(struct bloblist_hdr *hdr) +{ + struct bloblist_rec *rec; + u32 chksum; + + chksum = crc32(0, (unsigned char *)hdr, + offsetof(struct bloblist_hdr, chksum)); + foreach_rec(rec, hdr) { + chksum = crc32(chksum, (void *)rec, rec->hdr_size); + chksum = crc32(chksum, (void *)rec + rec->hdr_size, rec->size); + } + + return chksum; +} + +int bloblist_new(ulong addr, uint size, uint flags) +{ + struct bloblist_hdr *hdr; + + if (size < sizeof(*hdr)) + return log_ret(-ENOSPC); + if (addr & (BLOBLIST_ALIGN - 1)) + return log_ret(-EFAULT); + hdr = map_sysmem(addr, size); + memset(hdr, '\0', sizeof(*hdr)); + hdr->version = BLOBLIST_VERSION; + hdr->hdr_size = sizeof(*hdr); + hdr->flags = flags; + hdr->magic = BLOBLIST_MAGIC; + hdr->size = size; + hdr->alloced = hdr->hdr_size; + hdr->chksum = 0; + gd->bloblist = hdr; + + return 0; +} + +int bloblist_check(ulong addr, uint size) +{ + struct bloblist_hdr *hdr; + u32 chksum; + + hdr = map_sysmem(addr, sizeof(*hdr)); + if (hdr->magic != BLOBLIST_MAGIC) + return log_msg_ret("Bad magic", -ENOENT); + if (hdr->version != BLOBLIST_VERSION) + return log_msg_ret("Bad version", -EPROTONOSUPPORT); + if (size && hdr->size != size) + return log_msg_ret("Bad size", -EFBIG); + chksum = bloblist_calc_chksum(hdr); + if (hdr->chksum != chksum) { + log(LOGC_BLOBLIST, LOGL_ERR, "Checksum %x != %x\n", hdr->chksum, + chksum); + return log_msg_ret("Bad checksum", -EIO); + } + gd->bloblist = hdr; + + return 0; +} + +int bloblist_finish(void) +{ + struct bloblist_hdr *hdr = gd->bloblist; + + hdr->chksum = bloblist_calc_chksum(hdr); + + return 0; +} + +int bloblist_init(void) +{ + bool expected; + int ret = -ENOENT; + + /** + * Wed expect to find an existing bloblist in the first phase of U-Boot + * that runs + */ + expected = !u_boot_first_phase(); + if (expected) + ret = bloblist_check(CONFIG_BLOBLIST_ADDR, + CONFIG_BLOBLIST_SIZE); + if (ret) { + log(LOGC_BLOBLIST, expected ? LOGL_WARNING : LOGL_DEBUG, + "Existing bloblist not found: creating new bloblist\n"); + ret = bloblist_new(CONFIG_BLOBLIST_ADDR, CONFIG_BLOBLIST_SIZE, + 0); + } else { + log(LOGC_BLOBLIST, LOGL_DEBUG, "Found existing bloblist\n"); + } + + return ret; +} diff --git a/common/board_f.c b/common/board_f.c index afafec5e4d..149a7229e8 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -10,7 +10,9 @@ */ #include +#include #include +#include #include #include #include @@ -22,7 +24,9 @@ #include #include #include -#include +#ifdef CONFIG_SPL +#include +#endif #include #include #include @@ -90,7 +94,7 @@ static int init_func_watchdog_init(void) { # if defined(CONFIG_HW_WATCHDOG) && \ (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ - defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ + defined(CONFIG_SH) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ defined(CONFIG_IMX_WATCHDOG)) hw_watchdog_init(); @@ -165,6 +169,33 @@ static int print_resetinfo(void) } #endif +#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) +static int print_cpuinfo(void) +{ + struct udevice *dev; + char desc[512]; + int ret; + + ret = uclass_first_device_err(UCLASS_CPU, &dev); + if (ret) { + debug("%s: Could not get CPU device (err = %d)\n", + __func__, ret); + return ret; + } + + ret = cpu_get_desc(dev, desc, sizeof(desc)); + if (ret) { + debug("%s: Could not get CPU description (err = %d)\n", + dev->name, ret); + return ret; + } + + printf("CPU: %s\n", desc); + + return 0; +} +#endif + static int announce_dram_init(void) { puts("DRAM: "); @@ -230,16 +261,6 @@ __weak int init_func_vid(void) } #endif -#if defined(CONFIG_HARD_SPI) -static int init_func_spi(void) -{ - puts("SPI: "); - spi_init(); - puts("ready\n"); - return 0; -} -#endif - static int setup_mon_len(void) { #if defined(__ARM__) || defined(__MICROBLAZE__) @@ -257,6 +278,17 @@ static int setup_mon_len(void) return 0; } +static int setup_spl_handoff(void) +{ +#if CONFIG_IS_ENABLED(HANDOFF) + gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF, + sizeof(struct spl_handoff)); + debug("Found SPL hand-off info %p\n", gd->spl_handoff); +#endif + + return 0; +} + __weak int arch_cpu_init(void) { return 0; @@ -532,6 +564,16 @@ static int reserve_stacks(void) return arch_reserve_stacks(); } +static int reserve_bloblist(void) +{ +#ifdef CONFIG_BLOBLIST + gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE; + gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); +#endif + + return 0; +} + static int display_new_sp(void) { debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); @@ -638,6 +680,24 @@ static int reloc_bootstage(void) return 0; } +static int reloc_bloblist(void) +{ +#ifdef CONFIG_BLOBLIST + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + if (gd->new_bloblist) { + int size = CONFIG_BLOBLIST_SIZE; + + debug("Copying bloblist from %p to %p, size %x\n", + gd->bloblist, gd->new_bloblist, size); + memcpy(gd->new_bloblist, gd->bloblist, size); + gd->bloblist = gd->new_bloblist; + } +#endif + + return 0; +} + static int setup_reloc(void) { if (gd->flags & GD_FLG_SKIP_RELOC) { @@ -785,6 +845,10 @@ static const init_fnc_t init_sequence_f[] = { initf_malloc, log_init, initf_bootstage, /* uses its own timer, so does not need DM */ +#ifdef CONFIG_BLOBLIST + bloblist_init, +#endif + setup_spl_handoff, initf_console_record, #if defined(CONFIG_HAVE_FSP) arch_fsp_init, @@ -837,9 +901,6 @@ static const init_fnc_t init_sequence_f[] = { #endif #if defined(CONFIG_VID) && !defined(CONFIG_SPL) init_func_vid, -#endif -#if defined(CONFIG_HARD_SPI) - init_func_spi, #endif announce_dram_init, dram_init, /* configure available RAM banks */ @@ -885,6 +946,7 @@ static const init_fnc_t init_sequence_f[] = { reserve_global_data, reserve_fdt, reserve_bootstage, + reserve_bloblist, reserve_arch, reserve_stacks, dram_init_banksize, @@ -904,6 +966,7 @@ static const init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET reloc_fdt, reloc_bootstage, + reloc_bloblist, setup_reloc, #if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, diff --git a/common/board_r.c b/common/board_r.c index c55e33eec2..5f3d27aa9f 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -379,20 +378,6 @@ static int initr_flash(void) } #endif -#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI) -static int initr_spi(void) -{ - /* MPC8xx does this here */ -#ifdef CONFIG_MPC8XX_SPI -#if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f(); -#endif - spi_init_r(); -#endif - return 0; -} -#endif - #ifdef CONFIG_CMD_NAND /* go init the NAND */ static int initr_nand(void) @@ -453,7 +438,8 @@ static int initr_env(void) else set_default_env(NULL, 0); #ifdef CONFIG_OF_CONTROL - env_set_addr("fdtcontroladdr", gd->fdt_blob); + env_set_hex("fdtcontroladdr", + (unsigned long)map_to_sysmem(gd->fdt_blob)); #endif /* Initialize from environment */ @@ -743,9 +729,6 @@ static init_fnc_t init_sequence_r[] = { /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif -#ifdef CONFIG_PPC - initr_spi, -#endif #ifdef CONFIG_CMD_NAND initr_nand, #endif diff --git a/common/bootm_os.c b/common/bootm_os.c index f302135868..855c471c28 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -260,7 +260,7 @@ static int do_bootm_plan9(int flag, int argc, char * const argv[], #if defined(CONFIG_BOOTM_VXWORKS) && \ (defined(CONFIG_PPC) || defined(CONFIG_ARM)) -void do_bootvx_fdt(bootm_headers_t *images) +static void do_bootvx_fdt(bootm_headers_t *images) { #if defined(CONFIG_OF_LIBFDT) int ret; @@ -317,8 +317,8 @@ void do_bootvx_fdt(bootm_headers_t *images) puts("## vxWorks terminated\n"); } -static int do_bootm_vxworks(int flag, int argc, char * const argv[], - bootm_headers_t *images) +int do_bootm_vxworks(int flag, int argc, char * const argv[], + bootm_headers_t *images) { if (flag != BOOTM_STATE_OS_GO) return 0; @@ -482,7 +482,7 @@ static boot_os_fn *boot_os[] = { [IH_OS_PLAN9] = do_bootm_plan9, #endif #if defined(CONFIG_BOOTM_VXWORKS) && \ - (defined(CONFIG_PPC) || defined(CONFIG_ARM)) + (defined(CONFIG_PPC) || defined(CONFIG_ARM) || defined(CONFIG_RISCV)) [IH_OS_VXWORKS] = do_bootm_vxworks, #endif #if defined(CONFIG_CMD_ELF) diff --git a/common/console.c b/common/console.c index 9a94f32192..0b0dd76256 100644 --- a/common/console.c +++ b/common/console.c @@ -535,6 +535,13 @@ void putc(const char c) void puts(const char *s) { +#ifdef CONFIG_SANDBOX + /* sandbox can send characters to stdout before it has a console */ + if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) { + os_puts(s); + return; + } +#endif #ifdef CONFIG_DEBUG_UART if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) { while (*s) { diff --git a/common/cros_ec.c b/common/cros_ec.c index 4ca15e19d5..e66471ebd1 100644 --- a/common/cros_ec.c +++ b/common/cros_ec.c @@ -25,15 +25,3 @@ struct udevice *board_get_cros_ec_dev(void) } return dev; } - -int cros_ec_get_error(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_CROS_EC, 0, &dev); - if (ret && ret != -ENODEV) - return ret; - - return 0; -} diff --git a/common/dfu.c b/common/dfu.c index 2620d3238b..44d1484d3d 100644 --- a/common/dfu.c +++ b/common/dfu.c @@ -23,9 +23,9 @@ int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget) bool dfu_reset = false; int ret, i = 0; - ret = board_usb_init(usbctrl_index, USB_INIT_DEVICE); + ret = usb_gadget_initialize(usbctrl_index); if (ret) { - pr_err("board usb init failed\n"); + pr_err("usb_gadget_initialize failed\n"); return CMD_RET_FAILURE; } g_dnl_clear_detach(); @@ -84,7 +84,7 @@ int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget) } exit: g_dnl_unregister(); - board_usb_cleanup(usbctrl_index, USB_INIT_DEVICE); + usb_gadget_release(usbctrl_index); if (dfu_reset) do_reset(NULL, 0, 0, NULL); diff --git a/common/fdt_support.c b/common/fdt_support.c index e6daa67990..3440e42a25 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -633,7 +634,7 @@ int fdt_shrink_to_minimum(void *blob, uint extrasize) fdt_set_totalsize(blob, actualsize); /* Add the new reservation */ - ret = fdt_add_mem_rsv(blob, (uintptr_t)blob, actualsize); + ret = fdt_add_mem_rsv(blob, map_to_sysmem(blob), actualsize); if (ret < 0) return ret; diff --git a/common/hash.c b/common/hash.c index ef146513a0..413a5bfcda 100644 --- a/common/hash.c +++ b/common/hash.c @@ -85,6 +85,33 @@ static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void } #endif +static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) +{ + uint16_t *ctx = malloc(sizeof(uint16_t)); + *ctx = 0; + *ctxp = ctx; + return 0; +} + +static int hash_update_crc16_ccitt(struct hash_algo *algo, void *ctx, + const void *buf, unsigned int size, + int is_last) +{ + *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), buf, size); + return 0; +} + +static int hash_finish_crc16_ccitt(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) +{ + if (size < algo->digest_size) + return -1; + + *((uint16_t *)dest_buf) = *((uint16_t *)ctx); + free(ctx); + return 0; +} + static int hash_init_crc32(struct hash_algo *algo, void **ctxp) { uint32_t *ctx = malloc(sizeof(uint32_t)); @@ -159,6 +186,15 @@ static struct hash_algo hash_algo[] = { #endif }, #endif + { + .name = "crc16-ccitt", + .digest_size = 2, + .chunk_size = CHUNKSZ, + .hash_func_ws = crc16_ccitt_wd_buf, + .hash_init = hash_init_crc16_ccitt, + .hash_update = hash_update_crc16_ccitt, + .hash_finish = hash_finish_crc16_ccitt, + }, { .name = "crc32", .digest_size = 4, diff --git a/common/image-fit.c b/common/image-fit.c index 8d39a243f8..ac901e131c 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -165,6 +165,7 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, uint8_t *value; int value_len; char *algo; + const char *padding; int required; int ret, i; @@ -184,6 +185,10 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, printf(" (required)"); printf("\n"); + padding = fdt_getprop(fit, noffset, "padding", NULL); + if (padding) + printf("%s %s padding: %s\n", p, type, padding); + ret = fit_image_hash_get_value(fit, noffset, &value, &value_len); printf("%s %s value: ", p, type); diff --git a/common/image-sig.c b/common/image-sig.c index 5a269d3289..4f6b4ec412 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -71,6 +71,19 @@ struct crypto_algo crypto_algos[] = { }; +struct padding_algo padding_algos[] = { + { + .name = "pkcs-1.5", + .verify = padding_pkcs_15_verify, + }, +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT + { + .name = "pss", + .verify = padding_pss_verify, + } +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ +}; + struct checksum_algo *image_get_checksum_algo(const char *full_name) { int i; @@ -106,6 +119,21 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name) return NULL; } +struct padding_algo *image_get_padding_algo(const char *name) +{ + int i; + + if (!name) + return NULL; + + for (i = 0; i < ARRAY_SIZE(padding_algos); i++) { + if (!strcmp(padding_algos[i].name, name)) + return &padding_algos[i]; + } + + return NULL; +} + /** * fit_region_make_list() - Make a list of image regions * @@ -155,6 +183,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, char **err_msgp) { char *algo_name; + const char *padding_name; if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) { *err_msgp = "Total size too large"; @@ -165,6 +194,11 @@ static int fit_image_setup_verify(struct image_sign_info *info, *err_msgp = "Can't get hash algo property"; return -1; } + + padding_name = fdt_getprop(fit, noffset, "padding", NULL); + if (!padding_name) + padding_name = RSA_DEFAULT_PADDING_NAME; + memset(info, '\0', sizeof(*info)); info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); info->fit = (void *)fit; @@ -172,6 +206,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, info->name = algo_name; info->checksum = image_get_checksum_algo(algo_name); info->crypto = image_get_crypto_algo(algo_name); + info->padding = image_get_padding_algo(padding_name); info->fdt_blob = gd_fdt_blob(); info->required_keynode = required_keynode; printf("%s:%s", algo_name, info->keyname); @@ -334,6 +369,11 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode, return -1; } + if (prop && prop_len > 0 && prop[prop_len - 1] != '\0') { + *err_msgp = "hashed-nodes property must be null-terminated"; + return -1; + } + /* Add a sanity check here since we are using the stack */ if (count > IMAGE_MAX_HASHED_NODES) { *err_msgp = "Number of hashed nodes exceeds maximum"; diff --git a/common/image.c b/common/image.c index 1c3a7720cb..4d4248f234 100644 --- a/common/image.c +++ b/common/image.c @@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, + { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",}, { IH_TYPE_INVALID, "invalid", "Invalid Image", }, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, @@ -166,6 +167,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" }, { IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",}, { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" }, + { IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" }, { -1, "", "", }, }; diff --git a/common/init/Makefile b/common/init/Makefile index 4902635f53..853b56d1e5 100644 --- a/common/init/Makefile +++ b/common/init/Makefile @@ -5,3 +5,4 @@ # obj-y += board_init.o +obj-$(CONFIG_$(SPL_TPL_)HANDOFF) += handoff.o diff --git a/common/init/handoff.c b/common/init/handoff.c new file mode 100644 index 0000000000..e00b43e6a7 --- /dev/null +++ b/common/init/handoff.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Passing basic information from SPL to U-Boot proper + * + * Copyright 2018 Google, Inc + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void handoff_save_dram(struct spl_handoff *ho) +{ + ho->ram_size = gd->ram_size; +#ifdef CONFIG_NR_DRAM_BANKS + { + struct bd_info *bd = gd->bd; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + ho->ram_bank[i].start = bd->bi_dram[i].start; + ho->ram_bank[i].size = bd->bi_dram[i].size; + } + } +#endif +} + +void handoff_load_dram_size(struct spl_handoff *ho) +{ + gd->ram_size = ho->ram_size; +} + +void handoff_load_dram_banks(struct spl_handoff *ho) +{ +#ifdef CONFIG_NR_DRAM_BANKS + { + struct bd_info *bd = gd->bd; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + bd->bi_dram[i].start = ho->ram_bank[i].start; + bd->bi_dram[i].size = ho->ram_bank[i].size; + } + } +#endif +} diff --git a/common/lcd.c b/common/lcd.c index 2e2bef3848..cd630405d4 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -242,14 +242,6 @@ void lcd_clear(void) lcd_sync(); } -static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - lcd_clear(); - return 0; -} -U_BOOT_CMD(cls, 1, 1, do_lcd_clear, "clear screen", ""); - static int lcd_init(void *lcdbase) { debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); @@ -389,7 +381,6 @@ static inline void lcd_logo_plot(int x, int y) {} #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) #ifdef CONFIG_SPLASH_SCREEN_ALIGN -#define BMP_ALIGN_CENTER 0x7FFF static void splash_align_axis(int *axis, unsigned long panel_size, unsigned long picture_size) diff --git a/common/main.c b/common/main.c index 9802bed229..07b34bf2b0 100644 --- a/common/main.c +++ b/common/main.c @@ -24,15 +24,15 @@ static void run_preboot_environment_command(void) p = env_get("preboot"); if (p != NULL) { -# ifdef CONFIG_AUTOBOOT_KEYED - int prev = disable_ctrlc(1); /* disable Control C checking */ -# endif + int prev = 0; + + if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED)) + prev = disable_ctrlc(1); /* disable Ctrl-C checking */ run_command_list(p, -1, 0); -# ifdef CONFIG_AUTOBOOT_KEYED - disable_ctrlc(prev); /* restore Control C checking */ -# endif + if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED)) + disable_ctrlc(prev); /* restore Ctrl-C checking */ } #endif /* CONFIG_PREBOOT */ } @@ -44,17 +44,15 @@ void main_loop(void) bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); -#ifdef CONFIG_VERSION_VARIABLE - env_set("ver", version_string); /* set version variable */ -#endif /* CONFIG_VERSION_VARIABLE */ + if (IS_ENABLED(CONFIG_VERSION_VARIABLE)) + env_set("ver", version_string); /* set version variable */ cli_init(); run_preboot_environment_command(); -#if defined(CONFIG_UPDATE_TFTP) - update_tftp(0UL, NULL, NULL); -#endif /* CONFIG_UPDATE_TFTP */ + if (IS_ENABLED(CONFIG_UPDATE_TFTP)) + update_tftp(0UL, NULL, NULL); s = bootdelay_process(); if (cli_process_fdt(&s)) diff --git a/common/malloc_simple.c b/common/malloc_simple.c index 871b5444bd..eabbb70128 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -5,6 +5,8 @@ * Copyright (c) 2014 Google, Inc */ +#define LOG_CATEGORY LOGC_ALLOC + #include #include #include @@ -12,40 +14,47 @@ DECLARE_GLOBAL_DATA_PTR; -void *malloc_simple(size_t bytes) -{ - ulong new_ptr; - void *ptr; - - new_ptr = gd->malloc_ptr + bytes; - debug("%s: size=%zx, ptr=%lx, limit=%lx: ", __func__, bytes, new_ptr, - gd->malloc_limit); - if (new_ptr > gd->malloc_limit) { - debug("space exhausted\n"); - return NULL; - } - ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes); - gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); - debug("%lx\n", (ulong)ptr); - - return ptr; -} - -void *memalign_simple(size_t align, size_t bytes) +static void *alloc_simple(size_t bytes, int align) { ulong addr, new_ptr; void *ptr; addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align); new_ptr = addr + bytes - gd->malloc_base; + log_debug("size=%zx, ptr=%lx, limit=%lx: ", bytes, new_ptr, + gd->malloc_limit); if (new_ptr > gd->malloc_limit) { - debug("space exhausted\n"); + log_err("alloc space exhausted\n"); return NULL; } ptr = map_sysmem(addr, bytes); gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); - debug("%lx\n", (ulong)ptr); + + return ptr; +} + +void *malloc_simple(size_t bytes) +{ + void *ptr; + + ptr = alloc_simple(bytes, 1); + if (!ptr) + return ptr; + + log_debug("%lx\n", (ulong)ptr); + + return ptr; +} + +void *memalign_simple(size_t align, size_t bytes) +{ + void *ptr; + + ptr = alloc_simple(bytes, align); + if (!ptr) + return ptr; + log_debug("aligned to %lx\n", (ulong)ptr); return ptr; } @@ -57,9 +66,16 @@ void *calloc(size_t nmemb, size_t elem_size) void *ptr; ptr = malloc(size); - if (ptr) - memset(ptr, '\0', size); + if (!ptr) + return ptr; + memset(ptr, '\0', size); return ptr; } #endif + +void malloc_simple_info(void) +{ + log_info("malloc_simple: %lx bytes used, %lx remain\n", gd->malloc_ptr, + CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr); +} diff --git a/common/spl/Kconfig b/common/spl/Kconfig index d0564621d4..35472f4a92 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -25,8 +25,28 @@ config SPL_FRAMEWORK supports MMC, NAND and YMODEM and other methods loading of U-Boot and the Linux Kernel. If unsure, say Y. +config HANDOFF + bool "Pass hand-off information from SPL to U-Boot proper" + depends on BLOBLIST + help + It is useful to be able to pass information from SPL to U-Boot + proper to preserve state that is known in SPL and is needed in U-Boot. + Enable this to locate the handoff information in U-Boot proper, early + in boot. It is available in gd->handoff. The state state is set up + in SPL (or TPL if that is being used). + if SPL +config SPL_HANDOFF + bool "Pass hand-off information from SPL to U-Boot proper" + depends on HANDOFF + default y + help + This option enables SPL to write handoff information. This can be + used to pass information like the size of SDRAM from SPL to U-Boot + proper. Also SPL can receive information from TPL in the same place + if that is enabled. + config SPL_LDSCRIPT string "Linker script for the SPL stage" default "arch/$(ARCH)/cpu/u-boot-spl.lds" @@ -135,12 +155,21 @@ config SPL_SEPARATE_BSS location is used. Normally we put the device tree at the end of BSS but with this option enabled, it goes at _image_binary_end. -config SPL_DISABLE_BANNER_PRINT - bool "Disable output of the SPL banner 'U-Boot SPL ...'" +config SPL_BANNER_PRINT + bool "Enable output of the SPL banner 'U-Boot SPL ...'" + default y + help + If this option is enabled, SPL will print the banner with version + info. Disabling this option could be useful to reduce TPL boot time + (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). + +config TPL_BANNER_PRINT + bool "Enable output of the TPL banner 'U-Boot TPL ...'" + default y help If this option is enabled, SPL will not print the banner with version - info. Selecting this option could be useful to reduce SPL boot time - (e.g. approx. 6 ms slower, when output on i.MX6 with 115200 baud). + info. Disabling this option could be useful to reduce SPL boot time + (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). config SPL_DISPLAY_PRINT bool "Display a board-specific message in SPL" @@ -257,6 +286,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 + default y if ARCH_IMX8M help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. @@ -295,6 +325,16 @@ config SPL_HASH_SUPPORT this option to build system-specific drivers for hash acceleration as part of an SPL build. +config TPL_HASH_SUPPORT + bool "Support hashing drivers in TPL" + select SHA1 + select SHA256 + help + Enable hashing drivers in SPL. These drivers can be used to + accelerate secure boot processing in secure applications. Enable + this option to build system-specific drivers for hash acceleration + as part of an SPL build. + config SPL_DMA_SUPPORT bool "Support DMA drivers" help @@ -376,7 +416,7 @@ config SPL_FPGA_SUPPORT within SPL. config SPL_GPIO_SUPPORT - bool "Support GPIO" + bool "Support GPIO in SPL" help Enable support for GPIOs (General-purpose Input/Output) in SPL. GPIOs allow U-Boot to read the state of an input line (high or @@ -410,6 +450,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBDISK_SUPPORT bool "Support disk partitions" + select PARTITIONS help Enable support for disk partitions within SPL. 'Disk' is something of a misnomer as it includes non-spinning media such as flash (as @@ -441,6 +482,7 @@ config SPL_DM_MAILBOX config SPL_MMC_SUPPORT bool "Support MMC" depends on MMC + select HAVE_BLOCK_DEVICE help Enable support for MMC (Multimedia Card) within SPL. This enables the MMC protocol implementation and allows any enabled drivers to @@ -571,7 +613,7 @@ config SPL_PAYLOAD TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to use u-boot.img. -config SPL_PCI_SUPPORT +config SPL_PCI bool "Support PCI drivers" help Enable support for PCI in SPL. For platforms that need PCI to boot, @@ -715,6 +757,7 @@ config SPL_THERMAL config SPL_USB_HOST_SUPPORT bool "Support USB host drivers" + select HAVE_BLOCK_DEVICE help Enable access to USB (Universal Serial Bus) host devices so that SPL can load U-Boot from a connected USB peripheral, such as a USB @@ -848,6 +891,16 @@ config TPL if TPL +config TPL_HANDOFF + bool "Pass hand-off information from TPL to SPL and U-Boot proper" + depends on HANDOFF + default y + help + This option enables TPL to write handoff information. This can be + used to pass information like the size of SDRAM from TPL to U-Boot + proper. The information is also available to SPL if it is useful + there. + config TPL_BOARD_INIT bool "Call board-specific initialization in TPL" help @@ -928,6 +981,17 @@ config TPL_ENV_SUPPORT help Enable environment support in TPL. See SPL_ENV_SUPPORT for details. +config TPL_GPIO_SUPPORT + bool "Support GPIO in TPL" + help + Enable support for GPIOs (General-purpose Input/Output) in TPL. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful in TPL to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of an TPL build. + config TPL_I2C_SUPPORT bool "Support I2C" help @@ -963,6 +1027,22 @@ config TPL_NAND_SUPPORT help Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details. +config TPL_PCI + bool "Support PCI drivers" + help + Enable support for PCI in TPL. For platforms that need PCI to boot, + or must perform some init using PCI in SPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of a TPL build. + +config TPL_PCH_SUPPORT + bool "Support PCH drivers" + help + Enable support for PCH (Platform Controller Hub) devices in TPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of a TPL + build. + config TPL_RAM_SUPPORT bool "Support booting from RAM" help @@ -977,6 +1057,15 @@ config TPL_RAM_DEVICE be already in memory when TPL takes over, e.g. loaded by the boot ROM. +config TPL_RTC_SUPPORT + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in TPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of an TPL + build. + config TPL_SERIAL_SUPPORT bool "Support serial" select TPL_PRINTF diff --git a/common/spl/spl.c b/common/spl/spl.c index 12f9359c0a..35120b6efd 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -7,8 +7,10 @@ */ #include +#include #include #include +#include #include #include #include @@ -44,6 +46,14 @@ static bd_t bdata __attribute__ ((section(".data"))); */ __weak void show_boot_progress(int val) {} +#if defined(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) +/* weak, default platform-specific function to initialize dram banks */ +__weak int dram_init_banksize(void) +{ + return 0; +} +#endif + /* * Default function to determine if u-boot or the OS should * be started. This implementation always returns 1. @@ -57,19 +67,12 @@ __weak void show_boot_progress(int val) {} #ifdef CONFIG_SPL_OS_BOOT __weak int spl_start_uboot(void) { - puts("SPL: Please implement spl_start_uboot() for your board\n"); - puts("SPL: Direct Linux boot not active!\n"); + puts(SPL_TPL_PROMPT + "Please implement spl_start_uboot() for your board\n"); + puts(SPL_TPL_PROMPT "Direct Linux boot not active!\n"); return 1; } -/* weak default platform specific function to initialize - * dram banks - */ -__weak int dram_init_banksize(void) -{ - return 0; -} - /* * Weak default function for arch specific zImage check. Return zero * and fill start and end address if image is recognized. @@ -100,13 +103,13 @@ void spl_fixup_fdt(void) /* fixup the memory dt node */ err = fdt_shrink_to_minimum(fdt_blob, 0); if (err == 0) { - printf("spl: fdt_shrink_to_minimum err - %d\n", err); + printf(SPL_TPL_PROMPT "fdt_shrink_to_minimum err - %d\n", err); return; } err = arch_fixup_fdt(fdt_blob); if (err) { - printf("spl: arch_fixup_fdt err - %d\n", err); + printf(SPL_TPL_PROMPT "arch_fixup_fdt err - %d\n", err); return; } #endif @@ -185,7 +188,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image, spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; - debug("spl: payload image: %32s load addr: 0x%lx size: %d\n", + debug(SPL_TPL_PROMPT "payload image: %32s load addr: 0x%lx size: %d\n", spl_image->name, spl_image->load_addr, spl_image->size); #ifdef CONFIG_SPL_FIT_SIGNATURE @@ -255,7 +258,8 @@ int spl_parse_image_header(struct spl_image_info *spl_image, } spl_image->os = image_get_os(header); spl_image->name = image_get_name(header); - debug("spl: payload image: %32s load addr: 0x%lx size: %d\n", + debug(SPL_TPL_PROMPT + "payload image: %32s load addr: 0x%lx size: %d\n", spl_image->name, spl_image->load_addr, spl_image->size); #else /* LEGACY image not supported */ @@ -284,7 +288,8 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->load_addr = CONFIG_SYS_LOAD_ADDR; spl_image->entry_point = CONFIG_SYS_LOAD_ADDR; spl_image->size = end - start; - debug("spl: payload zImage, load addr: 0x%lx size: %d\n", + debug(SPL_TPL_PROMPT + "payload zImage, load addr: 0x%lx size: %d\n", spl_image->load_addr, spl_image->size); return 0; } @@ -316,6 +321,44 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } +#if CONFIG_IS_ENABLED(HANDOFF) +/** + * Set up the SPL hand-off information + * + * This is initially empty (zero) but can be written by + */ +static int setup_spl_handoff(void) +{ + struct spl_handoff *ho; + + ho = bloblist_ensure(BLOBLISTT_SPL_HANDOFF, sizeof(struct spl_handoff)); + if (!ho) + return -ENOENT; + + return 0; +} + +static int write_spl_handoff(void) +{ + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(struct spl_handoff)); + if (!ho) + return -ENOENT; + handoff_save_dram(ho); +#ifdef CONFIG_SANDBOX + ho->arch.magic = TEST_HANDOFF_MAGIC; +#endif + debug(SPL_TPL_PROMPT "Wrote SPL handoff\n"); + + return 0; +} +#else +static inline int setup_spl_handoff(void) { return 0; } +static inline int write_spl_handoff(void) { return 0; } + +#endif /* HANDOFF */ + static int spl_common_init(bool setup_malloc) { int ret; @@ -336,6 +379,30 @@ static int spl_common_init(bool setup_malloc) return ret; } bootstage_mark_name(BOOTSTAGE_ID_START_SPL, "spl"); +#if CONFIG_IS_ENABLED(LOG) + ret = log_init(); + if (ret) { + debug("%s: Failed to set up logging\n", __func__); + return ret; + } +#endif + if (CONFIG_IS_ENABLED(BLOBLIST)) { + ret = bloblist_init(); + if (ret) { + debug("%s: Failed to set up bloblist: ret=%d\n", + __func__, ret); + return ret; + } + } + if (CONFIG_IS_ENABLED(HANDOFF)) { + int ret; + + ret = setup_spl_handoff(); + if (ret) { + puts(SPL_TPL_PROMPT "Cannot set up SPL handoff\n"); + hang(); + } + } if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); if (ret) { @@ -359,6 +426,10 @@ static int spl_common_init(bool setup_malloc) void spl_set_bd(void) { + /* + * NOTE: On some platforms (e.g. x86) bdata may be in flash and not + * writeable. + */ if (!gd->bd) gd->bd = &bdata; } @@ -453,7 +524,7 @@ static int boot_from_devices(struct spl_image_info *spl_image, if (loader) printf("Trying to boot from %s\n", loader->name); else - puts("SPL: Unsupported Boot Device!\n"); + puts(SPL_TPL_PROMPT "Unsupported Boot Device!\n"); #endif if (loader && !spl_load_image(spl_image, loader)) { spl_image->boot_device = spl_boot_list[i]; @@ -474,15 +545,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) BOOT_DEVICE_NONE, }; struct spl_image_info spl_image; + int ret; - debug(">>spl:board_init_r()\n"); + debug(">>" SPL_TPL_PROMPT "board_init_r()\n"); spl_set_bd(); -#ifdef CONFIG_SPL_OS_BOOT - dram_init_banksize(); -#endif - #if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); @@ -504,6 +572,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_board_init(); #endif + if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF)) + dram_init_banksize(); + bootcount_inc(); memset(&spl_image, '\0', sizeof(spl_image)); @@ -515,11 +586,23 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (boot_from_devices(&spl_image, spl_boot_list, ARRAY_SIZE(spl_boot_list))) { - puts("SPL: failed to boot from all boot devices\n"); + puts(SPL_TPL_PROMPT "failed to boot from all boot devices\n"); hang(); } spl_perform_fixups(&spl_image); + if (CONFIG_IS_ENABLED(HANDOFF)) { + ret = write_spl_handoff(); + if (ret) + printf(SPL_TPL_PROMPT + "SPL hand-off write failed (err=%d)\n", ret); + } + if (CONFIG_IS_ENABLED(BLOBLIST)) { + ret = bloblist_finish(); + if (ret) + printf("Warning: Failed to finish bloblist (ret=%d)\n", + ret); + } #ifdef CONFIG_CPU_V7M spl_image.entry_point |= 0x1; @@ -556,8 +639,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2) gd->malloc_ptr / 1024); #endif #ifdef CONFIG_BOOTSTAGE_STASH - int ret; - bootstage_mark_name(BOOTSTAGE_ID_END_SPL, "end_spl"); ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, CONFIG_BOOTSTAGE_STASH_SIZE); @@ -583,9 +664,9 @@ void preloader_console_init(void) gd->have_console = 1; -#ifndef CONFIG_SPL_DISABLE_BANNER_PRINT - puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME " " U_BOOT_TZ ")\n"); +#if CONFIG_IS_ENABLED(BANNER_PRINT) + puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); #endif #ifdef CONFIG_SPL_DISPLAY_PRINT spl_display_print(); diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index faf4ddbd1f..db436268cb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -15,6 +15,15 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif +__weak void board_spl_fit_post_load(ulong load_addr, size_t length) +{ +} + +__weak ulong board_spl_fit_size_align(ulong size) +{ + return size; +} + /** * spl_fit_get_image_name(): By using the matching configuration subnode, * retrieve the name of an image, specified by a property name and an index @@ -350,6 +359,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, */ size = fdt_totalsize(fit); size = (size + 3) & ~3; + size = board_spl_fit_size_align(size); base_offset = (size + 3) & ~3; /* @@ -373,8 +383,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, fit = spl_get_load_buffer(-hsize, hsize); sectors = get_aligned_image_size(info, size, 0); count = info->read(info, sector, sectors, fit); - debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", - sector, sectors, fit, count); + debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n", + sector, sectors, fit, count, size); + if (count == 0) return -EIO; @@ -510,5 +521,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) spl_image->entry_point = spl_image->load_addr; + spl_image->flags |= SPL_FIT_FOUND; + +#ifdef CONFIG_SECURE_BOOT + board_spl_fit_post_load((ulong)fit, size); +#endif + return 0; } diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index b6967ff69e..c91ad2b6dd 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -85,7 +85,9 @@ int spl_net_load_image_usb(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { bootdev->boot_device_name = "usb_ether"; - +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + usb_ether_init(); +#endif return spl_net_load_image(spl_image, bootdev); } SPL_LOAD_IMAGE_METHOD("USB eth", 0, BOOT_DEVICE_USBETH, spl_net_load_image_usb); diff --git a/common/usb.c b/common/usb.c index 78178c54c8..b70f614d24 100644 --- a/common/usb.c +++ b/common/usb.c @@ -42,7 +42,7 @@ static int asynch_allowed; char usb_started; /* flag for the started/stopped USB status */ -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) static struct usb_device usb_dev[USB_MAX_DEVICE]; static int dev_index; @@ -183,7 +183,7 @@ int usb_disable_asynch(int disable) asynch_allowed = !disable; return old_value; } -#endif /* !CONFIG_DM_USB */ +#endif /* !CONFIG_IS_ENABLED(DM_USB) */ /*------------------------------------------------------------------- @@ -849,7 +849,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) * the USB device are static allocated [USB_MAX_DEVICE]. */ -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* returns a pointer to the device with the index [index]. * if the device is not assigned (dev->devnum==-1) returns NULL @@ -906,7 +906,7 @@ __weak int usb_alloc_device(struct usb_device *udev) { return 0; } -#endif /* !CONFIG_DM_USB */ +#endif /* !CONFIG_IS_ENABLED(DM_USB) */ static int usb_hub_port_reset(struct usb_device *dev, struct usb_device *hub) { @@ -1166,7 +1166,7 @@ int usb_setup_device(struct usb_device *dev, bool do_read, return ret; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* * By the time we get here, the device has gotten a new device ID * and is in the default state. We need to identify the thing and @@ -1215,14 +1215,14 @@ int board_usb_cleanup(int index, enum usb_init_type init) bool usb_device_has_child_on_port(struct usb_device *parent, int port) { -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) return false; #else return parent->children[port] != NULL; #endif } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) void usb_find_usb2_hub_address_port(struct usb_device *udev, uint8_t *hub_address, uint8_t *hub_port) { diff --git a/common/usb_hub.c b/common/usb_hub.c index e1d93b8333..33aaeb8e44 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -64,7 +64,7 @@ static inline bool usb_hub_is_superspeed(struct usb_device *hdev) return hdev->descriptor.bDeviceProtocol == 3; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) bool usb_hub_is_root_hub(struct udevice *hub) { if (device_get_uclass_id(hub->parent) != UCLASS_USB_HUB) @@ -125,7 +125,7 @@ int usb_get_port_status(struct usb_device *dev, int port, void *data) USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port, data, sizeof(struct usb_port_status), USB_CNTL_TIMEOUT); -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) if (ret < 0) return ret; @@ -209,7 +209,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub) max(100, (int)pgood_delay) + 1000); } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) static struct usb_hub_device hub_dev[USB_MAX_HUB]; static int usb_hub_index; @@ -273,7 +273,7 @@ static int usb_hub_port_reset(struct usb_device *dev, int port, unsigned short portstatus, portchange; int delay = HUB_SHORT_RESET_TIME; /* start with short reset delay */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) debug("%s: resetting '%s' port %d...\n", __func__, dev->dev->name, port + 1); #else @@ -394,7 +394,7 @@ int usb_hub_port_connect_change(struct usb_device *dev, int port) break; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct udevice *child; ret = usb_scan_device(dev->dev, port + 1, speed, &child); @@ -604,7 +604,7 @@ static struct usb_hub_device *usb_get_hub_device(struct usb_device *dev) { struct usb_hub_device *hub; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* "allocate" Hub device */ hub = usb_hub_allocate(); #else @@ -788,7 +788,7 @@ static int usb_hub_configure(struct usb_device *dev) (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \ "" : "no "); -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /* * Update USB host controller's internal representation of this hub * after the hub descriptor is fetched. @@ -930,7 +930,7 @@ int usb_hub_probe(struct usb_device *dev, int ifnum) return ret; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) int usb_hub_scan(struct udevice *hub) { struct usb_device *udev = dev_get_parent_priv(hub); diff --git a/common/usb_kbd.c b/common/usb_kbd.c index fdeb2aed24..020f0d4117 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -539,7 +539,7 @@ static int probe_usb_keyboard(struct usb_device *dev) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* Search for keyboard and register it if found. */ int drv_usb_kbd_init(void) { @@ -602,7 +602,7 @@ int usb_kbd_deregister(int force) #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int usb_kbd_probe(struct udevice *dev) { diff --git a/common/usb_storage.c b/common/usb_storage.c index d92ebb6eb1..8c889bb1a6 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -66,7 +66,7 @@ static __u32 CBWTag; static int usb_max_devs; /* number of highest available usb device */ -#ifndef CONFIG_BLK +#if !CONFIG_IS_ENABLED(BLK) static struct blk_desc usb_dev_desc[USB_MAX_STOR_DEV]; #endif @@ -99,7 +99,7 @@ struct us_data { unsigned short max_xfer_blk; /* maximum transfer blocks */ }; -#ifndef CONFIG_BLK +#if !CONFIG_IS_ENABLED(BLK) static struct us_data usb_stor[USB_MAX_STOR_DEV]; #endif @@ -111,7 +111,7 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *us, struct blk_desc *dev_desc); int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss); -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) static unsigned long usb_stor_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer); static unsigned long usb_stor_write(struct udevice *dev, lbaint_t blknr, @@ -136,7 +136,7 @@ static void usb_show_progress(void) int usb_stor_info(void) { int count = 0; -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) struct udevice *dev; for (blk_first_device(IF_TYPE_USB, &dev); @@ -186,7 +186,7 @@ static int usb_stor_probe_device(struct usb_device *udev) { int lun, max_lun; -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) struct us_data *data; int ret; #else @@ -197,7 +197,7 @@ static int usb_stor_probe_device(struct usb_device *udev) #endif debug("\n\nProbing for storage\n"); -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) /* * We store the us_data in the mass storage device's platdata. It * is shared by all LUNs (block devices) attached to this mass storage @@ -226,9 +226,7 @@ static int usb_stor_probe_device(struct usb_device *udev) blkdev->lun = lun; ret = usb_stor_get_info(udev, data, blkdev); - if (ret == 1) - ret = blk_prepare_device(dev); - if (!ret) { + if (ret == 1) { usb_max_devs++; debug("%s: Found device %p\n", __func__, udev); } else { @@ -301,7 +299,7 @@ int usb_stor_scan(int mode) if (mode == 1) printf(" scanning usb for storage devices... "); -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) unsigned char i; usb_disable_asynch(1); /* asynch transfer not allowed */ @@ -944,7 +942,7 @@ static void usb_stor_set_max_xfer_blk(struct usb_device *udev, size_t __maybe_unused size; int __maybe_unused ret; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) #ifdef CONFIG_USB_EHCI_HCD /* * The U-Boot EHCI driver can handle any transfer length as long as @@ -1121,7 +1119,7 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, } #endif /* CONFIG_USB_BIN_FIXUP */ -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) static unsigned long usb_stor_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) #else @@ -1136,14 +1134,14 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr, struct us_data *ss; int retry; struct scsi_cmd *srb = &usb_ccb; -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) struct blk_desc *block_dev; #endif if (blkcnt == 0) return 0; /* Setup device */ -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) block_dev = dev_get_uclass_platdata(dev); udev = dev_get_parent_priv(dev_get_parent(dev)); debug("\nusb_read: udev %d\n", block_dev->devnum); @@ -1202,7 +1200,7 @@ retry_it: return blkcnt; } -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) static unsigned long usb_stor_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) #else @@ -1217,7 +1215,7 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, struct us_data *ss; int retry; struct scsi_cmd *srb = &usb_ccb; -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) struct blk_desc *block_dev; #endif @@ -1225,7 +1223,7 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr, return 0; /* Setup device */ -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) block_dev = dev_get_uclass_platdata(dev); udev = dev_get_parent_priv(dev_get_parent(dev)); debug("\nusb_read: udev %d\n", block_dev->devnum); @@ -1497,7 +1495,7 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, return 1; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int usb_mass_storage_probe(struct udevice *dev) { @@ -1521,7 +1519,7 @@ U_BOOT_DRIVER(usb_mass_storage) = { .id = UCLASS_MASS_STORAGE, .of_match = usb_mass_storage_ids, .probe = usb_mass_storage_probe, -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) .platdata_auto_alloc_size = sizeof(struct us_data), #endif }; @@ -1542,7 +1540,7 @@ static const struct usb_device_id mass_storage_id_table[] = { U_BOOT_USB_DEVICE(usb_mass_storage, mass_storage_id_table); #endif -#ifdef CONFIG_BLK +#if CONFIG_IS_ENABLED(BLK) static const struct blk_ops usb_storage_ops = { .read = usb_stor_read, .write = usb_stor_write, diff --git a/common/xyzModem.c b/common/xyzModem.c index 830fca8387..e5c65b480a 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include /* Assumption - run xyzModem protocol over the console port */ diff --git a/config.mk b/config.mk index b4e4618982..caf0dd9b81 100644 --- a/config.mk +++ b/config.mk @@ -15,6 +15,7 @@ PLATFORM_CPPFLAGS := PLATFORM_LDFLAGS := LDFLAGS := LDFLAGS_FINAL := +LDFLAGS_STANDALONE := OBJCOPYFLAGS := # clear VENDOR for tcsh VENDOR := @@ -75,4 +76,5 @@ LDFLAGS_FINAL += -Bstatic export PLATFORM_CPPFLAGS export RELFLAGS export LDFLAGS_FINAL +export LDFLAGS_STANDALONE export CONFIG_STANDALONE_LOAD_ADDR diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 467ca4efab..3e9f57446c 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -27,6 +27,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y +CONFIG_AXP_ALDO3_INRUSH_QUIRK=y CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index fa58a6dac8..e7ca33576a 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -26,6 +26,8 @@ CONFIG_RGMII=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y +CONFIG_AXP_ALDO3_INRUSH_QUIRK=y CONFIG_AXP_ALDO4_VOLT=2800 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 29a60e3a98..3fa68babe7 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -42,6 +42,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="S3K> " @@ -63,13 +64,18 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="mcr3000" CONFIG_ENV_IS_IN_FLASH=y +CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_MPC8XX_FEC=y # CONFIG_PCI is not set +CONFIG_DM_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MPC8xx=y CONFIG_SHA256=y CONFIG_LZMA=y -CONFIG_OF_LIBFDT=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 99526c185e..e0ce1595c5 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set @@ -40,4 +41,5 @@ CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index a0abe23ed3..4a6e05844f 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -32,6 +32,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y # CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set @@ -42,4 +43,5 @@ CONFIG_MV88E61XX_PHY_PORTS=0x003 CONFIG_MV88E61XX_FIXED_PORTS=0x300 CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ax25-ae350_defconfig b/configs/ae350_rv32_defconfig similarity index 93% rename from configs/ax25-ae350_defconfig rename to configs/ae350_rv32_defconfig index d7c4f40e58..5837b48903 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ae350_rv32_defconfig @@ -1,7 +1,6 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_AX25_AE350=y -CONFIG_CPU_RISCV_64=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y @@ -16,7 +15,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_OF_BOARD=y -CONFIG_DEFAULT_DEVICE_TREE="ae350" +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig new file mode 100644 index 0000000000..b250d3fc7e --- /dev/null +++ b/configs/ae350_rv64_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +CONFIG_ATCPIT100_TIMER=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index a61b13b6fc..d2c8825a18 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_AM33XX=y @@ -39,27 +38,35 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_OMAP24_I2C_SPEED=1000 +CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_OMAP_HS_ADMA=y CONFIG_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000 CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_SMSC=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_ETHER=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index 90ccf9adfe..439d0cba05 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -32,15 +32,14 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index d625599461..c62e8322fb 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -13,7 +13,11 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_ETHER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" @@ -31,23 +35,27 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_I2C=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_TI=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index b6cd49a469..0931c1e97f 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -40,20 +40,20 @@ CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 54dc7dff78..e08234e9f8 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -35,15 +35,14 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 5d7ccf0c5a..040384f3c7 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -31,15 +31,14 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 10a935f0c0..1f430ad416 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -30,15 +30,14 @@ CONFIG_MMC_OMAP_HS=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index ec72538ddc..1c315025d1 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -38,15 +38,14 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index aa6e9665d2..1a7c5cfb17 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -# CONFIG_SPL_USE_ARCH_MEMCPY is not set -# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y @@ -8,10 +6,11 @@ CONFIG_AM33XX=y CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -47,9 +46,9 @@ CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_TIMER=y @@ -60,7 +59,6 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 379b9580a2..147da80f0d 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -12,14 +12,17 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" +CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_EXT_SUPPORT is not set CONFIG_SPL_MTD_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set -# CONFIG_SPL_YMODEM_SUPPORT is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set @@ -39,14 +42,15 @@ CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_TIMER=y @@ -57,8 +61,12 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_RSA=y CONFIG_LZO=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 16affb8a05..186c65f0bf 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -44,8 +44,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_MTD_UBI_FASTMAP=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index 065efca633..e93c411766 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_AUTOBOOT_KEYED=y @@ -31,12 +32,13 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" # CONFIG_NET is not set CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_SDHCI=y CONFIG_PINCTRL=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 25e1a4f943..0eaf9c5ab0 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -37,8 +37,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 9ebfe5e7f5..06339a9572 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 064b3c355c..25582f3dfc 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -39,8 +39,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig index dce8334732..5a08c9bcc3 100644 --- a/configs/am335x_shc_prompt_defconfig +++ b/configs/am335x_shc_prompt_defconfig @@ -36,8 +36,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index e4e6adef19..7b74e850fc 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig index e4e6adef19..7b74e850fc 100644 --- a/configs/am335x_shc_sdboot_prompt_defconfig +++ b/configs/am335x_shc_sdboot_prompt_defconfig @@ -38,8 +38,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index a45fd3d1c5..822f73d114 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -41,8 +41,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_MMC_OMAP_HS=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 882163f8c1..0fe3f7ef09 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y @@ -21,7 +20,6 @@ CONFIG_SYS_PROMPT="AM3517_EVM # " CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0xaa0000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set CONFIG_CMD_NAND=y @@ -34,9 +32,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am3517-evm" -CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_DM_PCA953X=y @@ -57,4 +53,3 @@ CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_AM35X=y CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 7601263be4..481aa4fad9 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_AM43XX=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y @@ -12,7 +13,11 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_MISC_INIT_R is not set CONFIG_VERSION_VARIABLE=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_ETHER=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 @@ -27,35 +32,47 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_OMAP_USB2_PHY=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index ea46236bc4..c1b32be190 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -43,8 +43,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y @@ -56,7 +56,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index c38fdc1921..0d7bd72157 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -41,8 +40,8 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TI_QSPI=y @@ -54,7 +53,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 2d54d1aaf0..7d56db43fd 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -38,9 +38,9 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y @@ -54,7 +54,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 2713833544..5131f190a7 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -19,7 +19,6 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 CONFIG_CMD_SPL_WRITE_SIZE=0x40000 CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -51,9 +50,9 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y @@ -67,7 +66,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index aaf8d10fec..5d98e0edee 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -48,9 +48,9 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y @@ -64,7 +64,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 5242ab6f9f..91293daee7 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -50,6 +51,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y @@ -59,8 +61,11 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y @@ -70,14 +75,14 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index be4aa0f316..6924b0bd06 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -53,6 +54,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y @@ -62,8 +64,11 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y @@ -73,14 +78,14 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig new file mode 100644 index 0000000000..237b9e8229 --- /dev/null +++ b/configs/am65x_evm_r5_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SOC_K3_AM6=y +CONFIG_TARGET_AM654_R5_EVM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_GPIO=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_K3_ARASAN=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_K3=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 83721b403b..e0d257564f 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -46,7 +46,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 0e6547b72c..490b93f0de 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -38,7 +38,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 2b6af4b221..24422645cb 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -40,6 +40,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 2a1059a47a..347d941e15 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -84,12 +84,12 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_SPL_GZIP=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig new file mode 100644 index 0000000000..91302eb49c --- /dev/null +++ b/configs/bananapi_m2_zero_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero" diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig new file mode 100644 index 0000000000..56e0a56028 --- /dev/null +++ b/configs/bcm968580_ram_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_BCM6858=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_TARGET_BCM968580XREF=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" +# CONFIG_NET is not set +CONFIG_BLK=y +CONFIG_CLK=y +# CONFIG_MMC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_SEARCH_ALL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_REGEX=y +# CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 28cb04c38b..77d1ad51d8 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -42,7 +42,6 @@ CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 89c777872a..3a25639ab8 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -49,15 +49,14 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index e3dc88b005..fd29396100 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -49,15 +49,14 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index cf1fd0b6c6..9e31b4ac97 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -40,6 +40,7 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPI=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 3296a74a0a..083b5f7e5f 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -76,9 +76,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHY_NATSEMI=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y # CONFIG_NETDEVICES is not set CONFIG_DM_SERIAL=y CONFIG_USB=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index e03eb37dfe..1cfd5fc709 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -80,9 +80,7 @@ CONFIG_MISC=y CONFIG_NAND=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 -CONFIG_PHY_NATSEMI=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y # CONFIG_NETDEVICES is not set CONFIG_DM_SERIAL=y CONFIG_USB=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 2fa5dacd7a..37373967df 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -87,9 +87,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_NATSEMI=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y # CONFIG_NETDEVICES is not set CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 4b00a177f5..74a9121996 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_ARM_SMCCC=y CONFIG_ARCH_OWL=y CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_TARGET_BUBBLEGUM_96=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index c046ef5d8b..be55728e6f 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -36,6 +36,5 @@ CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index c782fef89e..74b17ef938 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -45,7 +45,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index b6cde09d6f..02eb324811 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -29,19 +29,26 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-chiliboard" CONFIG_ENV_IS_IN_MMC=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_DRIVER_TI_CPSW=y +CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_TI=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_LZO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 79ab6acaec..1c20dcd882 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -79,7 +79,6 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d892d65bf0..94a1af01be 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -80,7 +80,6 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 @@ -88,10 +87,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_DM_VIDEO=y +CONFIG_CONSOLE_TRUETYPE=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +# CONFIG_USE_PRIVATE_LIBGCC is not set CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 13b90a13f6..074d333dd4 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -33,7 +33,7 @@ CONFIG_SPL_CPU_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_PCI_SUPPORT=y +CONFIG_SPL_PCI=y CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b042874073..cb7f52f040 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -79,7 +79,6 @@ CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig new file mode 100644 index 0000000000..c1b1c3f7e9 --- /dev/null +++ b/configs/ci20_mmc_defconfig @@ -0,0 +1,48 @@ +CONFIG_MIPS=y +CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds" +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL=y +CONFIG_ARCH_JZ47XX=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000" +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_SPL_BANNER_PRINT is not set +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="ci20" +CONFIG_ENV_IS_IN_MMC=y +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_JZ4780_EFUSE=y +CONFIG_MMC=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +# CONFIG_MMC_VERBOSE is not set +CONFIG_SPL_MMC_TINY=y +CONFIG_JZ47XX_MMC=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_LZO=y diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig index c5337f909e..fec5e60832 100644 --- a/configs/cl-som-am57x_defconfig +++ b/configs/cl-som-am57x_defconfig @@ -46,8 +46,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y CONFIG_SPI=y @@ -56,7 +56,6 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 0eed5264f2..ea7ad5c596 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -43,8 +43,11 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y @@ -56,12 +59,13 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MII=y +CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y -CONFIG_OF_LIBFDT=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 9167a9450d..e1c5a1fa13 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_GPIO_SUPPORT=y @@ -62,4 +63,3 @@ CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig new file mode 100644 index 0000000000..42cdbfab61 --- /dev/null +++ b/configs/clearfog_gt_8k_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MVEBU_ARMADA_8K=y +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MAC_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_REGULATOR_FIXED=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 4ec74b27cd..d6726f6d97 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -72,7 +72,6 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 134b093e54..b948b89daa 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -45,7 +45,7 @@ CONFIG_LED_STATUS_BOOT_ENABLE=y CONFIG_LED_STATUS_BOOT=0 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index eb4a8f5a33..a2530b704d 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -58,8 +58,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y @@ -67,6 +67,5 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index 955a6a57a9..05ac37cc25 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -39,7 +39,6 @@ CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index c26b3b9eb4..90eb309379 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -66,7 +66,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 43528ef383..b1cfd65572 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -49,7 +49,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index c8b82a9b58..fcbb30d82c 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index d9ef52e68d..1b8e4e43c4 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -28,11 +28,14 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5315u" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y @@ -41,6 +44,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_BCM6368_ETH=y CONFIG_PHY=y CONFIG_BCM6318_USBH_PHY=y CONFIG_BCM6328_POWER_DOMAIN=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index f129870ca0..5ba401a441 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -28,11 +28,14 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y @@ -41,6 +44,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_BCM6368_ETH=y CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_POWER_DOMAIN=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 82f2070713..6297e78fd9 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,ct-5361" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6348_USBH_PHY=y CONFIG_DM_RESET=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 1689eecec1..47f53998e1 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -26,15 +26,20 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y +CONFIG_DM_ETH=y +CONFIG_BCM6368_ETH=y CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_POWER_DOMAIN=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index 987e4c3fbc..fd5107bb7d 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="comtrend,wap-5813n" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_BCM6368_ETH=y CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_DM_RESET=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index b1e7c35fa9..a1af2f1342 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 1bb7b9a03e..5100ee7b0e 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y -# CONFIG_CMD_EEPROM is not set CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index b4564f2101..be818dff55 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_BOOTZ is not set CONFIG_CMD_IMLS=y CONFIG_CRC32_VERIFY=y -# CONFIG_CMD_EEPROM is not set CONFIG_CMD_DM=y # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 5c498749d6..1cdde484dd 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y -# CONFIG_CMD_EEPROM is not set CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 9c08aadc0d..c2ee3d890e 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -36,7 +36,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index dd58198a54..9068a58406 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -43,6 +43,9 @@ CONFIG_EFI_PARTITION=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +# CONFIG_SPL_BLK is not set +# CONFIG_BLOCK_CACHE is not set CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 92b23778ef..4a65f7f2a5 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -52,7 +52,6 @@ CONFIG_MII=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 27f6b5d981..fe253a6552 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y @@ -34,11 +34,13 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y @@ -56,6 +58,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -67,11 +70,12 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPL_PHY=y CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y CONFIG_DM_REGULATOR_FIXED=y @@ -87,15 +91,13 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_DRA7XX_INDEX=1 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 651fc4fb42..735be5506a 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_DWC_AHCI=y @@ -56,6 +57,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -66,11 +68,12 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_ETH=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPL_PHY=y CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y CONFIG_DM_REGULATOR_FIXED=y @@ -86,15 +89,13 @@ CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_DRA7XX_INDEX=1 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_OMAP_USB_PHY=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 634721192d..7eac0f282e 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -47,7 +47,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MSM=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 97d828f441..b2b59e122b 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_ARM_SMCCC=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TARGET_DRAGONBOARD820C=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 76c768006d..d3263cf9cd 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -26,6 +26,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_MVSATA_IDE=y # CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y @@ -34,6 +35,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 23f1886a24..352403e573 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -23,6 +23,7 @@ CONFIG_MVSATA_IDE=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y @@ -32,6 +33,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig index 3c1fee4a90..8ea626d013 100644 --- a/configs/duovero_defconfig +++ b/configs/duovero_defconfig @@ -36,6 +36,5 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_UDC=y CONFIG_USB_OMAP3=y -CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 89035a051d..afa08a0289 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -31,7 +31,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/edison_defconfig b/configs/edison_defconfig index eb9f9a089f..234dbac4e8 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -# CONFIG_CMD_PCI is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_TIMER=y CONFIG_CMD_HASH=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig new file mode 100644 index 0000000000..e0bc5776a9 --- /dev/null +++ b/configs/elgin-rv1108_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x60000000 +CONFIG_ROCKCHIP_RV1108=y +CONFIG_TARGET_ELGIN_RV1108=y +CONFIG_DEBUG_UART_BASE=0x10210000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GPIO=y +CONFIG_RANDOM_UUID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x62000000 +CONFIG_FASTBOOT_BUF_SIZE=0x08000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RV1108=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_BAUDRATE=1500000 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x110a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_ERRNO_STR=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 88230f4a12..7fb52d2732 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -12,11 +12,18 @@ CONFIG_PRE_CON_BUF_ADDR=0x1e720000 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb" CONFIG_REGMAP=y CONFIG_CLK=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_FTGMAC100=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_DM_RESET=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 787d6f95c1..439e691386 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" CONFIG_REGMAP=y CONFIG_SYSCON=y +# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 044e60735a..00bf907ff1 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -44,7 +44,6 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 1485844aa6..980f7f7b3d 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -71,7 +71,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5b3bb8eae7..10a5f09b31 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -56,7 +56,7 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f173c10a6b..3ec6b20814 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -67,7 +67,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 2ef041f2c5..0ca6930e43 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -49,7 +49,6 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 8860edfd2f..2795ad82b0 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -70,7 +70,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig new file mode 100644 index 0000000000..a05f832d3c --- /dev/null +++ b/configs/ficus-rk3399_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_TARGET_ROCK960_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index b0db15ddc9..f5a8b614f6 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -74,7 +74,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 7ac4064a8b..e77bc4463d 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -66,7 +66,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index 262dea3115..ae8bf2981f 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -1,56 +1,77 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_MT7620=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y -# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)" CONFIG_CMD_UBI=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_CLK=y -CONFIG_CPU=y -CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_BEB_LIMIT=22 +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y -CONFIG_BAUDRATE=57600 # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_WATCHDOG=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_LZMA=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 6463e891b7..b7024e3dec 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -4,56 +4,77 @@ CONFIG_ARCH_MT7620=y CONFIG_BOOT_ROM=y CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y -# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)" +CONFIG_MTDIDS_DEFAULT="spi-nand0=gd5f,nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);gd5f:-(nand)" CONFIG_CMD_UBI=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c CONFIG_CLK=y -CONFIG_CPU=y -CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_BEB_LIMIT=22 +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y -CONFIG_BAUDRATE=57600 # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_WATCHDOG=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_LZMA=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index c907779636..84947aaae2 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50 +CONFIG_SYS_VPD_EEPROM_I2C_BUS=4 +CONFIG_SYS_VPD_EEPROM_SIZE=1024 CONFIG_TARGET_GE_BX50V3=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 8e99fe7ccb..f0987fc064 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index e30eb3d41c..514b40c356 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_HELIOS4=y CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y -CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 @@ -19,12 +18,12 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 -CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -38,18 +37,21 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SCSI_AHCI=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 +CONFIG_SYS_I2C_MVTWSI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y -CONFIG_PCI=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y @@ -57,4 +59,3 @@ CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 8dc5a2823e..3bc5ceb5d8 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -23,7 +23,6 @@ CONFIG_MMC_DW_K3=y CONFIG_CONS_INDEX=4 CONFIG_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 6bb14ba736..d4e6144319 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -25,11 +25,14 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -40,6 +43,9 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig new file mode 100644 index 0000000000..4588f5bddc --- /dev/null +++ b/configs/imx8mq_evk_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_THERMAL=y +CONFIG_FS_FAT=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 518f7259f2..58b4ca0861 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -6,7 +6,6 @@ CONFIG_TARGET_IMX8QXP_MEK=y CONFIG_NR_DRAM_BANKS=3 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_CMD_CPU=y # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_CLK=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 76f3376e3c..c39c424e7b 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -46,7 +46,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index d744cb1961..a108f88dfd 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -47,12 +48,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 87faf3d207..67f6fb1da5 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -40,12 +41,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index a96029cdd4..ab9e695b02 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -35,7 +35,9 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set +CONFIG_DFU_MMC=y CONFIG_SYS_I2C_DAVINCI=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y @@ -50,6 +52,9 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y @@ -57,6 +62,13 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_SDP=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 9e75500b77..a6757cc0b4 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -28,7 +28,9 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set +CONFIG_DFU_MMC=y CONFIG_SYS_I2C_DAVINCI=y +CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y @@ -43,6 +45,9 @@ CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y @@ -50,6 +55,13 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_SDP=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 8c7d362129..ce139d11d6 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -47,12 +48,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index c8f4bbeb91..db61557f11 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -40,12 +41,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index dd91aa5ef2..368171d134 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -47,12 +48,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index ac400e4369..7bb672f50c 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -29,6 +29,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y +CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_DAVINCI=y @@ -39,12 +40,19 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y +CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 4bbccc2f34..75514d2ca5 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXM=y -CONFIG_TARGET_KHADAS_VIM2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim2" @@ -44,5 +43,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 0c89d9a22c..cf87802653 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_KHADAS_VIM=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" khadas-vim" @@ -49,5 +48,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 5ebbe1dc7c..f0fb52deda 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -39,6 +39,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_IMX_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index eb305e02aa..a577605822 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -30,6 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y +# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 @@ -46,7 +47,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 36d117c4ab..c21b9ad9ca 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_LIBRETECH_CC=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-cc" @@ -49,5 +48,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index 77cd1c1575..2d3ab7e35c 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -1,35 +1,37 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_ARCH_MT7620=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +CONFIG_BOARD_LINKIT_SMART_7688=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y -# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_CLK=y -CONFIG_CPU=y -CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -40,12 +42,17 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y -CONFIG_BAUDRATE=57600 # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 62cdda1e0a..ad34aaf640 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -1,39 +1,41 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9c000000 CONFIG_ARCH_MT7620=y +CONFIG_BOARD_LINKIT_SMART_7688=y CONFIG_BOOT_ROM=y CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y -# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y -# CONFIG_CMD_BOOTD is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="linkit-smart-7688" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_CLK=y -CONFIG_CPU=y -CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y @@ -44,12 +46,17 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_FIXED=y +CONFIG_MT7628_ETH=y CONFIG_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y CONFIG_DM_RESET=y -CONFIG_BAUDRATE=57600 # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y +CONFIG_MT7621_SPI=y CONFIG_SYSRESET_SYSCON=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 42d2e2e7b3..ea64172f3d 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -47,4 +47,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig new file mode 100644 index 0000000000..3d15745411 --- /dev/null +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012A2G5RDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index a63b900a2e..7317f5fc04 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -47,4 +47,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig new file mode 100644 index 0000000000..051d62645e --- /dev/null +++ b/configs/ls1012afrdm_tfa_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRDM=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index d457d9420b..c273dc937e 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -47,6 +47,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 7fe9556d04..85523ba2d3 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -48,4 +48,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..d9020c5281 --- /dev/null +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig new file mode 100644 index 0000000000..08b3692f97 --- /dev/null +++ b/configs/ls1012afrwy_tfa_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 57b5d93870..3a1121c72d 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -60,4 +60,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..7d0d69017b --- /dev/null +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig new file mode 100644 index 0000000000..30f23430ac --- /dev/null +++ b/configs/ls1012aqds_tfa_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 3e5ed6362a..f3c1b569c2 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -53,6 +53,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 2d0cfca9f9..8ca4c8d735 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -54,4 +54,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..5e524e74c1 --- /dev/null +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig new file mode 100644 index 0000000000..aae8df9709 --- /dev/null +++ b/configs/ls1012ardb_tfa_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_FSL_PFE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 97ffa21228..e3cd75563e 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -48,7 +48,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 582f52151f..41688263d1 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -53,7 +53,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index a567c07062..347c664e60 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -51,7 +51,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 1bcf56aa5d..edf74eef48 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -54,7 +54,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 44e59d2acc..42cf38b347 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -62,7 +62,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 4824a83fb4..c69d1dd75a 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -61,7 +61,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 4b01bc42f0..c59e493490 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -64,7 +64,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 7db5d2d43a..8bde83deda 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -53,4 +53,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 65f61f43d1..79448129bd 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -52,4 +52,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 06b266aa7d..ada225c3b6 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -65,4 +65,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 318152a391..e86d4196b5 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -51,4 +51,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index c2024cf7c8..d948981080 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -46,4 +46,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index d547fefcda..afa91e8b3a 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -65,4 +65,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 850b1dc142..310cb2319a 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -59,4 +59,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..ce6f1ef86f --- /dev/null +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig new file mode 100644 index 0000000000..ee30589e1d --- /dev/null +++ b/configs/ls1043aqds_tfa_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 41df0b9fbf..0a51540674 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -45,7 +45,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 7541fad3db..1462a44369 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -46,4 +46,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 2879f45d56..8a45f7c8d0 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -63,6 +63,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 5a23e3cfff..509f2f1e3c 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -63,4 +63,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 3c19694456..33ce8acd08 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -61,6 +61,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 144e48b885..91dac81e8b 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -61,4 +61,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..0af2594205 --- /dev/null +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig new file mode 100644 index 0000000000..da5beeedc2 --- /dev/null +++ b/configs/ls1043ardb_tfa_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 8f61afa5fd..ae05dd150b 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -51,5 +51,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 47a8dcd68b..f7a35dfeb9 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT_VERBOSE=y @@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -44,6 +46,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -52,4 +55,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 7edb0ad384..0a8d51e43d 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -54,4 +54,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index d8a5b0e95e..9e11db7d7f 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -59,4 +59,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index ab1b549a27..a6bbf106e1 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -49,4 +49,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index ff9b0367ae..edf915fdd6 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -68,4 +68,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index ab53eb7689..afb76d6900 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -64,4 +64,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..f57dda591a --- /dev/null +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig new file mode 100644 index 0000000000..48d78b4739 --- /dev/null +++ b/configs/ls1046aqds_tfa_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index f7a35c7e19..181fa61422 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -60,4 +60,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 80f52807e1..d8eb7b7ede 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -45,5 +45,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index e780acc446..fa4a08f024 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -38,6 +40,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -46,4 +49,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index f7cd33d8af..0a45653b98 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -62,5 +62,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_SPL_GZIP=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 24a08b6e01..80c42c5bad 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -59,6 +59,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 61da6ae517..a1bd39b17c 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -59,4 +59,3 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..d570c6de05 --- /dev/null +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SECURE_BOOT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_RSA=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig new file mode 100644 index 0000000000..c5d6935b55 --- /dev/null +++ b/configs/ls1046ardb_tfa_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 177c56889a..dbc0bdf7c9 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -28,6 +29,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y @@ -41,6 +43,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index b184d23295..731408c13e 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -45,12 +45,12 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index c63426d0cd..1a3e74600c 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -45,11 +45,11 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index f83c17b81b..d0319a5b63 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -55,10 +55,10 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index ff72ec5edc..0cee141cf1 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -46,12 +46,12 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 089faa484e..5503a71d3c 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set @@ -30,6 +31,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -42,15 +44,16 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index f7ec11fe05..b53f212125 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -58,11 +58,11 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index b56e11ed3a..5b0f1d6d03 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -56,10 +56,10 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 6a2a522046..d7c0db6343 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -54,7 +54,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index f4a361a64d..51cf327da3 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -31,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -47,6 +49,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -55,5 +58,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 1f93a8378c..30b506fafc 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -61,5 +61,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 32eec9a99d..44a718e855 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -52,5 +52,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index a71913d65c..d6ca28979f 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -59,5 +59,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 8f18d93667..150693b387 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -55,7 +55,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 1c13bbabbc..a1ddc1add6 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x30100000 CONFIG_FSL_LS_PPA=y +CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -31,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y @@ -47,6 +49,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550=y CONFIG_SPI=y @@ -56,5 +59,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 061d5cdc2b..e12c3d5a7e 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -60,5 +60,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 323f63b907..39d431aec1 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -52,5 +52,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index e5712db330..d230e64307 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -50,7 +50,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 5e5d17f6b4..1c9a39d4b0 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -54,5 +54,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 7466b6108d..8563abc135 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -39,4 +39,3 @@ CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index f55a69916e..c3636060a7 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -39,4 +39,3 @@ CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 795f8a3ebc..dd7aed324f 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -49,6 +49,7 @@ CONFIG_NAND=y CONFIG_NAND_MXC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_RTC_M41T62=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 1bc8894cfc..b77ed9ae64 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -29,7 +29,6 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 69fab7c779..61231557bf 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -46,5 +46,4 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 05c6572beb..3047ae6e76 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -47,5 +47,4 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index c2cd298aaa..a55d8d4cfa 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 0b21020cff..02e62e2ee8 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=-1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=romfs" CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index f650a720c7..fcb7163ba1 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -70,7 +70,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig new file mode 100644 index 0000000000..d7476c4863 --- /dev/null +++ b/configs/mscc_luton_defconfig @@ -0,0 +1,64 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x40000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x70100000 +CONFIG_DEBUG_UART_CLOCK=208333333 +CONFIG_ARCH_MSCC=y +CONFIG_TARGET_LUTON_PCB091=y +CONFIG_DDRTYPE_MT47H128M8HQ=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="pcb091 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" +# CONFIG_ISO_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_LZMA=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig new file mode 100644 index 0000000000..5fa74db2ff --- /dev/null +++ b/configs/mscc_ocelot_defconfig @@ -0,0 +1,67 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x40000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x70100000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_ARCH_MSCC=y +CONFIG_TARGET_OCELOT_PCB123=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="pcb123 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_LZMA=y diff --git a/configs/mscc_ocelot_pcb120_defconfig b/configs/mscc_ocelot_pcb120_defconfig new file mode 100644 index 0000000000..c5a9f96977 --- /dev/null +++ b/configs/mscc_ocelot_pcb120_defconfig @@ -0,0 +1,60 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x40000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_MSCC=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="pcb120 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" +CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_LZMA=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig new file mode 100644 index 0000000000..ae4fb280dc --- /dev/null +++ b/configs/mt7623n_bpir2_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x81e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_BLOCK_CACHE is not set +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7623=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TIMER=y +CONFIG_MTK_TIMER=y +CONFIG_WDT_MTK=y +CONFIG_LZMA=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig new file mode 100644 index 0000000000..1729d13c3d --- /dev/null +++ b/configs/mt7629_rfb_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_MT7629=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_DEFAULT_FDT_FILE="mt7629-rfb" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +# CONFIG_PARTITIONS is not set +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_DM_GPIO=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7629=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_MTK_TIMER=y +CONFIG_WDT_MTK=y +CONFIG_LZMA=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 2c7a6a393f..da51868b44 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -68,7 +68,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index cbdc130e98..424d9765dc 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -9,7 +9,7 @@ CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set @@ -62,7 +62,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 6d1649fb88..8701d1f4c2 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -68,7 +68,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 9f72b76a3f..d671f201f6 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -5,11 +5,10 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MVEBU_ARMADA_8K=y CONFIG_DEBUG_UART_BASE=0xf0512000 CONFIG_DEBUG_UART_CLOCK=200000000 -CONFIG_SMBIOS_PRODUCT_NAME="" CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set @@ -35,6 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_DEFAULT_DEVICE_TREE="armada-8040-mcbin" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_AHCI_MVEBU=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y @@ -48,8 +48,9 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y +CONFIG_MVPP2=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y @@ -66,10 +67,8 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SMBIOS_MANUFACTURER="" diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 2eee19dab5..0e552a6ac4 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTEFI is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y @@ -27,7 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=59 +CONFIG_LED_STATUS_BIT=778 CONFIG_LED_STATUS_STATE=2 CONFIG_LED_STATUS_BOOT_ENABLE=y CONFIG_LED_STATUS_BOOT=0 diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 34328fd016..28540719df 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -2,6 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_MX5=y CONFIG_SYS_TEXT_BASE=0x77800000 CONFIG_TARGET_MX53PPD=y +CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50 +CONFIG_SYS_VPD_EEPROM_I2C_BUS=2 +CONFIG_SYS_VPD_EEPROM_SIZE=1024 CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/mx53ppd/imximage.cfg" diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 6e73a9752c..adacd8ca61 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -36,7 +36,6 @@ CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index c73d0d3931..4c84fa5ab7 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -44,7 +44,6 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y CONFIG_USB_GADGET=y diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 5c8c747bf3..8bbf48f41f 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 -CONFIG_MESON_GXBB=y -CONFIG_TARGET_NANOPI_K2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" nanopi-k2" diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index 1abc869856..0f3914fe7e 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -27,17 +27,23 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_BCM6368_ETH=y CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_POWER_DOMAIN=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 7eda3ac49d..c54640df2f 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -47,7 +47,6 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_PCI=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y CONFIG_USB_GADGET=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index ae6d76dfb2..13d8f99cbe 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -63,7 +63,6 @@ CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 19196b3585..33e6e74fa2 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 -CONFIG_MESON_GXBB=y -CONFIG_TARGET_ODROID_C2=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-c2" diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index d5c7cc7129..11796e5bdf 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -47,7 +47,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_PHY_SAMSUNG=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 594800fc50..cdb033ba78 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -47,7 +47,6 @@ CONFIG_DM_REGULATOR_MAX77686=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index a23f6a33d6..d2821b8ceb 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -8,6 +9,7 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -19,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # " CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y @@ -29,14 +30,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit" -CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y @@ -60,14 +57,10 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index f28ca5bcbf..28b35ac80d 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -8,6 +9,7 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -19,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # " CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y @@ -29,14 +30,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit" -CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y @@ -66,14 +63,10 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 4fb8aec57d..9581dd9537 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -66,7 +66,6 @@ CONFIG_USB_OMAP3=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="TI" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 45e5b504f7..9c6f442b64 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -8,6 +9,7 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -19,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # " CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y @@ -29,14 +30,11 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit" -CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y @@ -61,14 +59,10 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index e733584ebe..6602af6abe 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO_SUPPORT is not set CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -8,6 +9,7 @@ CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -19,7 +21,6 @@ CONFIG_SYS_PROMPT="OMAP Logic # " CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 -# CONFIG_CMD_EEPROM is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y @@ -28,14 +29,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit" -CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y @@ -66,14 +63,10 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y -CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TI" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 -CONFIG_USB_ETHER=y CONFIG_BCH=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index 1e7e5f7d83..b2fb146889 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -45,7 +45,6 @@ CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_BCH=y CONFIG_OF_LIBFDT=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 41df480be3..b66659f123 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -36,7 +36,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_UDC=y CONFIG_USB_OMAP3=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 52b76e260a..84d4e2b37c 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -41,7 +41,6 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_PHY_OMAP=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig new file mode 100644 index 0000000000..e5f7d15bf6 --- /dev/null +++ b/configs/orangepi_lite2_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2" diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 9e3b1d6bfb..2ab47e616f 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_MESON_GXL=y -CONFIG_TARGET_P212=y CONFIG_DEBUG_UART_BASE=0xc81004c0 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" p212" @@ -48,5 +47,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 02a7569205..015ac05308 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -32,7 +32,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index d9dcf7e014..81ce9a2d08 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -39,7 +39,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 5cbb1c3201..5482ac2563 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -32,7 +32,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index a11e56d7c2..dc785c8865 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -30,7 +30,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 0be0caa826..274549f6e3 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -43,15 +43,14 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_ETHER=y CONFIG_FAT_WRITE=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 33e8225e53..a41ed1481e 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -43,15 +43,14 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_ETHER=y CONFIG_FAT_WRITE=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 0c8e31a9ec..e207df51a8 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -35,5 +35,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 338eae20b4..96ec8fdb0b 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y @@ -28,7 +29,6 @@ CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y @@ -52,6 +52,7 @@ CONFIG_PWM_EXYNOS=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98090=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_EXYNOS_SPI=y @@ -60,7 +61,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y CONFIG_VIDCONSOLE_AS_LCD=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index 933c823ea8..792f22fa1f 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_TPM=y @@ -27,7 +28,6 @@ CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y @@ -51,6 +51,7 @@ CONFIG_PWM_EXYNOS=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98090=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_EXYNOS_SPI=y @@ -59,7 +60,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y CONFIG_VIDCONSOLE_AS_LCD=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 3c8684ad95..a0206f6fde 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -48,15 +48,14 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index 1dc3944d05..b5738541f2 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -33,8 +33,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index ef7abddbf1..1e33e542ef 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -74,7 +74,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index ce10c64490..de699fc275 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -41,7 +41,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_PIC32=y -CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 362c0a251d..e5713d7924 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -44,7 +44,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index b02cae5237..0afc897ed9 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -51,7 +51,6 @@ CONFIG_MII=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index c8d58cbe71..907ccee77b 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -46,7 +46,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index f355f07be7..19adeb35e1 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -51,7 +51,6 @@ CONFIG_MII=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 680438d265..3adccbb3ea 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -44,7 +44,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 3a182dcb81..1558739e30 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -51,7 +51,6 @@ CONFIG_MII=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 0b6234fbd9..67cfed67f3 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_PICOSAM9G45=y @@ -34,8 +35,12 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y CONFIG_OF_LIBFDT=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig new file mode 100644 index 0000000000..fd3cdeec85 --- /dev/null +++ b/configs/pine64-lts_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC0_CD_PIN="" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_SPL_SPI_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig new file mode 100644 index 0000000000..5294dbd2eb --- /dev/null +++ b/configs/pinebook_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook" +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_SUNXI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +# CONFIG_USB_GADGET is not set +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 73524122de..05b388cce3 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -27,6 +27,5 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index a3ae9a06b2..239783a592 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -16,7 +16,6 @@ CONFIG_MMC_DW_K3=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_FAT_WRITE=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 0e10d1a225..85f4f393e8 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -70,7 +70,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 8e33e09cee..fd492312a1 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -75,9 +75,12 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_PINCTRL_ROCKCHIP_RK3399_FULL=y CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y @@ -95,7 +98,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 4a5c3c6710..527d4a3842 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -68,8 +68,8 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index ff1fb1f30e..6334d8c0fc 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -1,6 +1,9 @@ CONFIG_RISCV=y CONFIG_TARGET_QEMU_VIRT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_OF_BOARD=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig new file mode 100644 index 0000000000..0a84ec1874 --- /dev/null +++ b/configs/qemu-riscv32_smode_defconfig @@ -0,0 +1,10 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d6c1a5d646..2d9ead93a2 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -1,7 +1,10 @@ CONFIG_RISCV=y CONFIG_TARGET_QEMU_VIRT=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_OF_BOARD=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig new file mode 100644 index 0000000000..b012443370 --- /dev/null +++ b/configs/qemu-riscv64_smode_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 32922b84ff..8d43acd480 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_CPU_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_PCI_SUPPORT=y +CONFIG_SPL_PCI=y CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index e9e2819272..f2e759cee9 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -1,7 +1,5 @@ CONFIG_ARM=y -CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_QEMU_ARM_64BIT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -12,10 +10,17 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_FLASH=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_BLK=y # CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_NVME=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 04c9afdb02..27c427dd82 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y -CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y @@ -12,10 +11,17 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_FLASH=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_BLK=y # CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y CONFIG_DM_ETH=y CONFIG_E1000=y CONFIG_NVME=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 40712a44c3..019e72eac1 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot" +CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -40,7 +42,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index f1d150b5a0..b2f1dfe50b 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot" +CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -40,7 +42,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index 72549e2836..3580a44d5e 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot" +CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -41,7 +43,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 7c39268a43..9006b9fc3c 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot" +CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -41,7 +43,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index ef5c9443f9..37b70b993b 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -29,6 +29,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot" +CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y CONFIG_SYSCON=y @@ -41,7 +43,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 7363310d52..8f6a8f503a 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -41,7 +41,7 @@ CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1f00263bb4..32e92a5ca0 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -29,7 +29,6 @@ CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig new file mode 100644 index 0000000000..82134698f9 --- /dev/null +++ b/configs/riotboard_spl_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_EMBESTMX6BOARDS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,MX6S,DDR_MB=1024" +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SST=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_OF_LIBFDT=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 6289506bdd..702e8e91cb 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -71,7 +71,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig new file mode 100644 index 0000000000..caf0fcc8ff --- /dev/null +++ b/configs/rock960-rk3399_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_TARGET_ROCK960_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_PROMPT="rock960 => " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3399=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 28dcd5bccc..0c41ac9f20 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -56,6 +56,5 @@ CONFIG_ROCKCHIP_TIMER=y CONFIG_USB=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index d5bf01b76e..39da54c3e7 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" CONFIG_ENV_FAT_INTERFACE="mmc" @@ -29,7 +30,6 @@ CONFIG_PINCTRL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index a50a815759..5f5b40522d 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" CONFIG_ENV_FAT_INTERFACE="mmc" @@ -29,7 +30,6 @@ CONFIG_PINCTRL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index ec395d29ed..bbf902bb91 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_ENV_FAT_INTERFACE="mmc" @@ -31,7 +32,6 @@ CONFIG_PINCTRL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index ac99f2000a..ea40351dc4 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_ENV_FAT_INTERFACE="mmc" @@ -31,7 +32,6 @@ CONFIG_PINCTRL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_LAN78XX=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index db42ffd135..981d17381a 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" CONFIG_ENV_FAT_INTERFACE="mmc" @@ -29,7 +30,6 @@ CONFIG_PINCTRL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 08eafc235e..958d21b59d 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -69,8 +69,8 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig new file mode 100644 index 0000000000..1bd4b7127b --- /dev/null +++ b/configs/s400_defconfig @@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_MESON_AXG=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" s400" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_AXG=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index 91a966327a..8c36f5dbf8 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -27,11 +27,14 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="sagem,f@st1704" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -40,6 +43,9 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index e6680d9a59..236199d2a1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -1,5 +1,4 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SANDBOX64=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 @@ -181,7 +180,6 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y @@ -198,9 +196,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_UT_OVERLAY=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5a744f4791..90146f64cd 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,10 +1,10 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y @@ -93,8 +93,13 @@ CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y +CONFIG_DMA=y +CONFIG_DMA_CHANNELS=y +CONFIG_SANDBOX_DMA=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SANDBOX=y CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -188,7 +193,6 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y @@ -209,9 +213,7 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_UT_OVERLAY=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 756b839b08..63e3745522 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -1,5 +1,4 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y @@ -163,7 +162,6 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 93b2240185..1a30e53f6f 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -1,5 +1,4 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y @@ -162,7 +161,6 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y @@ -171,6 +169,7 @@ CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_OSD=y CONFIG_SANDBOX_OSD=y +# CONFIG_VIRTIO_BLK is not set CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index f44e80e8c3..012f3342ac 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -1,7 +1,6 @@ CONFIG_SYS_TEXT_BASE=0 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y @@ -22,6 +21,7 @@ CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_CMD_CPU=y @@ -180,7 +180,6 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y CONFIG_CONSOLE_ROTATION=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 69e159b43e..5715665810 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -33,7 +33,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 12adfb01e7..39622875b1 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -26,11 +26,14 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser" -# CONFIG_NET is not set +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -42,6 +45,9 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index cf6f2757ca..7c7220afc8 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -57,5 +57,8 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y +CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 161454b33f..c86fde7399 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y @@ -54,7 +53,6 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 433e9a8447..e92472ecc7 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y @@ -41,6 +40,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_VIDEO_BRIDGE=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 21080091a7..86a668ff33 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y @@ -72,7 +71,6 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_DM_VIDEO=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index e7e1121c5c..0e5e74a621 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -67,7 +67,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="altera" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 8989c4dc96..e8de0f5709 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="altera" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 1a9f2b6038..9a89bb5d68 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -62,7 +62,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="terasic" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index c9490d47a4..db516891ba 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -58,7 +58,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="terasic" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index b6c8e6c84d..5bed755723 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -55,6 +55,5 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 66f7733ee8..abbbcb94d3 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="terasic" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 05f38cbcd2..53f8d3c348 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -68,7 +68,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="ebv" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 6fcf8c66f8..3eba09dcb1 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -84,7 +84,6 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="samtec" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/spring_defconfig b/configs/spring_defconfig index ca1799895e..5c5569acd2 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y @@ -72,7 +71,6 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_DM_VIDEO=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 2df8cc3732..2326bf9481 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -48,7 +48,6 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x483 diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 1bf3a7c11f..121e962808 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_STM32=y CONFIG_SYS_TEXT_BASE=0x08008000 -CONFIG_SYS_MALLOC_F_LEN=0xC00 +CONFIG_SYS_MALLOC_F_LEN=0xE00 CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_ENV_VARS_UBOOT_CONFIG=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 3bf7538089..304688e56f 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_STM32_ADC=y +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y @@ -56,7 +58,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 7c1dbac096..b96f7bb8f0 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -52,7 +52,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index ee5da43ccb..022b0b6da1 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -60,4 +60,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y +CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 65ac1c2e5b..250d7f0250 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -31,6 +31,5 @@ CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 62526a7470..c5bb4955af 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index b78dc7e017..8866d6d0e2 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_DRIVER_TI_CPSW=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 5a69a68384..e0fc1875ee 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -73,7 +73,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" CONFIG_USB_GADGET_VENDOR_NUM=0x2207 diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig new file mode 100644 index 0000000000..fb06076785 --- /dev/null +++ b/configs/tools-only_defconfig @@ -0,0 +1,24 @@ +CONFIG_SYS_TEXT_BASE=0 +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_DATE is not set +CONFIG_OF_CONTROL=y +CONFIG_OF_HOSTFILE=y +CONFIG_DEFAULT_DEVICE_TREE="sandbox" +# CONFIG_UDP_FUNCTION_FASTBOOT is not set +CONFIG_SANDBOX_GPIO=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_SANDBOX=y +CONFIG_DM_RTC=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_SANDBOX is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 7840ab08fd..bbf75c11eb 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -49,7 +49,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index b9dd7f157e..9351cd0315 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -50,7 +50,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 3608ac31e9..969f7aceba 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -50,7 +50,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 6dfb3fbda8..71bfbfc54e 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -37,6 +37,5 @@ CONFIG_TEGRA20_SFLASH=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 749ed31acd..c428bba5c9 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -67,7 +67,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index aad8044782..4a1e23c86c 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -51,6 +51,5 @@ CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_WDT=y CONFIG_WDT_ORION=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 6b9e22ac0e..48f7ac4c87 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y @@ -49,6 +50,5 @@ CONFIG_SMC911X_32_BIT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_PANIC_HANG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 4c06f272b1..f7abf05c52 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y @@ -51,6 +52,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_UNIPHIER=y -CONFIG_USB_STORAGE=y CONFIG_PANIC_HANG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index f8f9bdf05c..1ba1c7d508 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -7,6 +7,7 @@ CONFIG_ARCH_UNIPHIER_V8_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_NR_DRAM_BANKS=3 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" CONFIG_LOGLEVEL=6 CONFIG_CMD_CONFIG=y CONFIG_CMD_IMLS=y @@ -52,6 +53,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_UNIPHIER=y -CONFIG_USB_STORAGE=y CONFIG_PANIC_HANG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 4bac8f1fe6..b1f872405b 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -15,5 +15,4 @@ CONFIG_CMD_USB=y CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_ESDHC=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 12043180c0..856398b377 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -35,7 +35,6 @@ CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index a7c8bcd706..2d63b219cf 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -31,7 +31,6 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig index 9848f96293..0f0f138303 100644 --- a/configs/vexpress_aemv8a_dram_defconfig +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index ef38915955..ed611fea7c 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index a4d1233cd5..0b3bb65ee6 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -23,12 +23,14 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_DM=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index f4d555be48..cabc0c4577 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -18,8 +18,10 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig index bdacc60c2c..dc4411d6f5 100644 --- a/configs/vexpress_ca5x2_defconfig +++ b/configs/vexpress_ca5x2_defconfig @@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 7a90831918..9390cf61d1 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -17,8 +17,10 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_MTD_NOR_FLASH=y +CONFIG_MTD_DEVICE=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index a928cd4fbc..504eebbf5d 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -41,4 +41,4 @@ CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y -# CONFIG_EFI_UNICODE_CAPITALIZATION is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 560776fe56..0a1e28e2ec 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -41,4 +41,4 @@ CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y -# CONFIG_EFI_UNICODE_CAPITALIZATION is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index b23cd6a236..989ede35a1 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -69,7 +69,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_ROCKCHIP_USB2_PHY=y -CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Rockchip" diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 4d8ccff675..adcaf93b29 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -40,7 +40,6 @@ CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_DM_THERMAL=y CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_OF_LIBFDT=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 955c7af42a..4d443295ba 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -8,6 +8,8 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index 33591d73e0..9d881e5d41 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23f00000 CONFIG_TARGET_WB45N=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index c8f5f66232..a96f54c737 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_CONS_INDEX=0 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 09ba34cd1c..9cdc944f0c 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -20,6 +20,8 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 146ee8029f..74ea3a864e 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -20,6 +20,8 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 22b5d71845..9bb54da059 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -43,7 +43,6 @@ CONFIG_CMD_SF=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set -# CONFIG_PARTITIONS is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 1e89838724..674912d890 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -98,7 +98,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 39a68d6ddf..3c378ffa26 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -86,7 +86,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index 344dddb0c2..ed0306199e 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -83,7 +83,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index c81b50d636..c5e1fdae1f 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -84,12 +84,12 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_SPL_GZIP=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 7266fefc9f..b8fa38dccc 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -115,7 +115,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 623498c431..1d6857f754 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -111,10 +111,10 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_FUNCTION_THOR=y +CONFIG_SPL_GZIP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 476a3637cc..08ce4cbd53 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -111,7 +111,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 0b3d993516..c0ee229e8b 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -96,7 +96,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index d4add615ee..1430354ff1 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -97,7 +97,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index d9a75cbc4a..d5be4491a3 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -107,7 +107,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 5d7383a5f2..b9dc5d322a 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -98,7 +98,6 @@ CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 284166f3a2..e0e68f61d8 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -53,7 +53,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index e3dceaead3..317b35938b 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set @@ -40,7 +41,6 @@ CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set -# CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand" # CONFIG_NET is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 331a278381..cf2121630a 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -7,7 +7,6 @@ CONFIG_SPL=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_MALLOC_LEN=0x1000 CONFIG_ZYNQ_M29EW_WB_HACK=y -CONFIG_BOOTDELAY=-1 # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y @@ -15,6 +14,7 @@ CONFIG_SPL_STACK_R=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set @@ -41,7 +41,6 @@ CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set -# CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor" # CONFIG_NET is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 8db4ea95ea..d9708801c2 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_MALLOC_LEN=0x1000 # CONFIG_CMD_ZYNQ is not set CONFIG_DEBUG_UART=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTDELAY=-1 # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_ARCH_EARLY_INIT_R is not set @@ -22,6 +21,7 @@ CONFIG_SPL_SPI_LOAD=y # CONFIG_AUTO_COMPLETE is not set # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " +# CONFIG_AUTOBOOT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set @@ -50,7 +50,6 @@ CONFIG_CMD_SF=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set -# CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single" # CONFIG_NET is not set diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index eb698a05e0..a469bc4d95 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -63,7 +63,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index d6515157e5..f3c27086cb 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -54,7 +54,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig index 6a17503079..d5421df065 100644 --- a/configs/zynq_minized_defconfig +++ b/configs/zynq_minized_defconfig @@ -56,7 +56,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 92bad51b9c..98db04559f 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -41,7 +41,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index 31112f9b51..0cba1274ba 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -55,7 +55,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD diff --git a/configs/zynq_zc702_RSA_defconfig b/configs/zynq_zc702_RSA_defconfig index 4b5192cf17..3bcd24fb63 100644 --- a/configs/zynq_zc702_RSA_defconfig +++ b/configs/zynq_zc702_RSA_defconfig @@ -73,7 +73,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 519ffd84cb..0f10679876 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -72,7 +72,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 18a27108e5..cdfad83b1a 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -73,7 +73,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zc706_eeprom_defconfig b/configs/zynq_zc706_eeprom_defconfig index 78a3226f67..25dd92fad4 100644 --- a/configs/zynq_zc706_eeprom_defconfig +++ b/configs/zynq_zc706_eeprom_defconfig @@ -74,7 +74,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index bfbdfd8248..9fddd44ce7 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -60,7 +60,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 338c0be232..cf718a4db8 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -63,7 +63,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index ddc9a68bed..fcb0df78e2 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -58,7 +58,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03fd diff --git a/disk/part.c b/disk/part.c index 9e457a6e72..f30f9e9187 100644 --- a/disk/part.c +++ b/disk/part.c @@ -150,6 +150,9 @@ void dev_print (struct blk_desc *dev_desc) dev_desc->revision, dev_desc->product); break; + case IF_TYPE_VIRTIO: + printf("%s VirtIO Block Device\n", dev_desc->vendor); + break; case IF_TYPE_DOC: puts("device type DOC\n"); return; @@ -281,6 +284,9 @@ static void print_part_header(const char *type, struct blk_desc *dev_desc) case IF_TYPE_NVME: puts ("NVMe"); break; + case IF_TYPE_VIRTIO: + puts("VirtIO"); + break; default: puts ("UNKNOWN"); break; diff --git a/doc/README.ae350 b/doc/README.ae350 index fe75b80eb7..189a6b7ec3 100644 --- a/doc/README.ae350 +++ b/doc/README.ae350 @@ -25,7 +25,7 @@ Build and boot steps build: 1. Prepare the toolchains and make sure the $PATH to toolchains is correct. -2. Use `make ax25-ae350_defconfig` in u-boot root to build the image. +2. Use `make ae350_rv[32|64]_defconfig` in u-boot root to build the image for 32 or 64 bit. Verification ==================== diff --git a/doc/README.at91 b/doc/README.at91 index 67412136ee..39dd5632ba 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -171,4 +171,4 @@ III. Watchdog support your code (make sure not to disable it in AT91Bootstrap for instance). In the U-Boot configuration, the AT91 watchdog support is enabled using - the CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG options. + the CONFIG_WDT and CONFIG_WDT_AT91 options. diff --git a/doc/README.bloblist b/doc/README.bloblist new file mode 100644 index 0000000000..b0e787b97d --- /dev/null +++ b/doc/README.bloblist @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0+ + +Blob Lists - bloblist +===================== + +Introduction +------------ + +A bloblist provides a way to store collections of binary information (blobs) in +a central structure. Each record of information is assigned a tag so that its +owner can find it and update it. Each record is generally described by a C +structure defined by the code that owns it. + + +Passing state through the boot process +-------------------------------------- + +The bloblist is created when the first U-Boot component runs (often SPL, +sometimes TPL). It is passed through to each successive part of the boot and +can be accessed as needed. This provides a way to transfer state from one part +to the next. For example, TPL may determine that a watchdog reset occurred by +reading an SoC register. Reading the register may reset the value, so that it +cannot be read a second time. So TPL can store that in a bloblist record which +can be passed through to SPL and U-Boot proper, which can print a message +indicating that something went wrong and the watchdog fired. + + +Blobs +----- + +While each blob in the bloblist can be of any length, bloblists are designed to +hold small amounts of data, typically a few KB at most. It is not possible to +change the length of a blob once it has been written. Each blob is normally +created from a C structure which can beused to access its fields. + + +Blob tags +--------- + +Each blob has a tag which is a 32-bit number. This uniquely identifies the +owner of the blob. Blob tags are listed in enum blob_tag_t and are named +with a BLOBT_ prefix. + + +Single structure +---------------- + +There is normally only one bloblist in U-Boot. Since a bloblist can store +multiple blobs it does not seem useful to allow multiple bloblists. Of course +there could be reasons for this, such as needing to spread the blobs around in +different memory areas due to fragmented memory, but it is simpler to just have +a single bloblist. + + +API +--- + +Bloblist provides a fairly simple API which allows blobs to be created and +found. All access is via the blob's tag. + + +Finishing the bloblist +---------------------- + +When a part of U-Boot is about to jump to the next part, it can 'finish' the +bloblist in preparation for the next stage. This involves adding a checksum so +that the next stage can make sure that the data arrived safely. While the +bloblist is in use, changes can be made which will affect the checksum, so it +is easier to calculate the checksum at the end after all changes are made. + + +Future work +----------- + +Bootstage has a mechanism to 'stash' its records for passing to the next part. +This should move to using bloblist, to avoid having its own mechanism for +passing information between U-Boot parts. + + +Simon Glass +sjg@chromium.org +12-Aug-2018 diff --git a/doc/README.commands b/doc/README.commands index 1d29c4d91d..0ccadae0b7 100644 --- a/doc/README.commands +++ b/doc/README.commands @@ -28,6 +28,42 @@ comp: Pointer to the completion function. May be NULL. entering the command arguments to complete the entry. Command completion is only available if CONFIG_AUTO_COMPLETE is defined. +Sub-command definition +---------------------- + +Likewise an array of cmd_tbl_t holding sub-commands can be created using either +of the following macros: + +* U_BOOT_CMD_MKENT(name, maxargs, repeatable, command, "usage", "help") +* U_BOOT_CMD_MKENTCOMPLETE(name, maxargs, repeatable, command, "usage, "help", + comp) + +This table has to be evaluated in the command function of the main command, e.g. + + static cmd_tbl_t cmd_sub[] = { + U_BOOT_CMD_MKENT(foo, CONFIG_SYS_MAXARGS, 1, do_foo, "", ""), + U_BOOT_CMD_MKENT(bar, CONFIG_SYS_MAXARGS, 1, do_bar, "", ""), + }; + + static int do_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + { + cmd_tbl_t *cp; + + if (argc < 2) + return CMD_RET_USAGE; + + /* drop sub-command argument */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_ut_sub, ARRAY_SIZE(cmd_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + return CMD_RET_USAGE; + } + Command function ---------------- diff --git a/doc/README.distro b/doc/README.distro index f8e9752a0f..ab6e6f4e74 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -292,7 +292,7 @@ Each entry in the macro defines a single boot device (e.g. a specific eMMC device or SD card) or type of boot device (e.g. USB disk). The parameters to the func macro (passed in by the internal implementation of the header) are: -- Upper-case disk type (MMC, SATA, SCSI, IDE, USB, DHCP, PXE). +- Upper-case disk type (MMC, SATA, SCSI, IDE, USB, DHCP, PXE, VIRTIO). - Lower-case disk type (same options as above). - ID of the specific disk (MMC only) or ignored for other types. @@ -398,6 +398,7 @@ The list of possible targets consists of: * scsi * ide * usb + * virtio Other *boot* variables than the ones defined above are only for internal use of the boot environment and are not guaranteed to exist or work in the same diff --git a/doc/README.fdt-control b/doc/README.fdt-control index d6ab7bf570..446401c9e9 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -184,6 +184,24 @@ The full device tree is available to U-Boot proper, but normally only a subset 'SPL Support' in doc/driver-model/README.txt for more details. +Using several DTBs in the SPL (CONFIG_SPL_MULTI_DTB) +---------------------------------------------------- +In some rare cases it is desirable to let SPL be able to select one DTB among +many. This usually not very useful as the DTB for the SPL is small and usually +fits several platforms. However the DTB sometimes include information that do +work on several platforms (like IO tuning parameters). +In this case it is possible to use CONFIG_SPL_MULTI_DTB. This option appends to +the SPL a FIT image containing several DTBs listed in SPL_OF_LIST. +board_fit_config_name_match() is called to select the right DTB. + +If board_fit_config_name_match() relies on DM (DM driver to access an EEPROM +containing the board ID for example), it possible to start with a generic DTB +and then switch over to the right DTB after the detection. For this purpose, +the platform code must call fdtdec_resetup(). Based on the returned flag, the +platform may have to re-initiliaze the DM subusystem using dm_uninit() and +dm_init_and_scan(). + + Limitations ----------- diff --git a/doc/README.iscsi b/doc/README.iscsi index faee636264..3a12438f90 100644 --- a/doc/README.iscsi +++ b/doc/README.iscsi @@ -1,8 +1,6 @@ -iSCSI booting with U-Boot and iPXE -================================== +# iSCSI booting with U-Boot and iPXE -Motivation ----------- +## Motivation U-Boot has only a reduced set of supported network protocols. The focus for network booting has been on UDP based protocols. A TCP stack and HTTP support @@ -41,8 +39,7 @@ fine grained control of the boot process and can provide a command shell. iPXE can be built as an EFI application (named snp.efi) which can be loaded and run by U-Boot. -Boot sequence -------------- +## Boot sequence U-Boot loads the EFI application iPXE snp.efi using the bootefi command. This application has network access via the simple network protocol offered by @@ -106,19 +103,16 @@ the EFI stub Linux is called as an EFI application:: | | | ~ ~ ~ ~| -Security --------- +## Security The iSCSI protocol is not encrypted. The traffic could be secured using IPsec but neither U-Boot nor iPXE does support this. So we should at least separate the iSCSI traffic from all other network traffic. This can be achieved using a virtual local area network (VLAN). -Configuration -------------- +## Configuration -iPXE -^^^^ +### iPXE For running iPXE on arm64 the bin-arm64-efi/snp.efi build target is needed:: @@ -157,9 +151,20 @@ following into src/config/local/general.h is sufficient for most use cases:: #define DOWNLOAD_PROTO_NFS /* Network File System Protocol */ #define DOWNLOAD_PROTO_FILE /* Local file system access */ -Links ------ +### Open-iSCSI + +When the root file system is on an iSCSI drive you should disable pings and set +the replacement timer to a high value [3]: + + node.conn[0].timeo.noop_out_interval = 0 + node.conn[0].timeo.noop_out_timeout = 0 + node.session.timeo.replacement_timeout = 86400 + +## Links * [1](https://ipxe.org) https://ipxe.org - iPXE open source boot firmware * [2](https://www.gnu.org/software/grub/) https://www.gnu.org/software/grub/ - - GNU GRUB (Grand Unified Bootloader) + GNU GRUB (Grand Unified Bootloader) +* [3](https://github.com/open-iscsi/open-iscsi/blob/master/README) + https://github.com/open-iscsi/open-iscsi/blob/master/README - + Open-iSCSI README diff --git a/doc/README.mediatek b/doc/README.mediatek new file mode 100644 index 0000000000..246579d4be --- /dev/null +++ b/doc/README.mediatek @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 MediaTek Inc. +# Ryder Lee + + +This document describes how to compile the U-Boot and how to change U-Boot +configuration about the MediaTek SoCs. + + +Build Procedure +=============== + -Set the cross compiler: + + # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- + + -Clean-up old residuals: + + # make mrproper + + -Configure the U-Boot: + + # make + # make + + - For the MT7623n bananapi R2 board use "mt7623n_bpir2_defconfig" + - For the MT7629 reference board use "mt7629_rfb_defconfig" + + +Boot sequence +============= + -Bootrom -> MTK preloader -> U-Boot + + - MT7623n + + This version of U-Boot doesn't implement SPL. So, MTK preloader binary + is needed to boot up: + + https://github.com/BPI-SINOVOIP/BPI-R2-bsp/tree/master/mt-pack/mtk/bpi-r2/bin + + + -Bootrom -> SPL -> U-Boot + + - MT7629 + + +Configuration update +==================== + To update the U-Boot configuration, please refer to doc/README.kconfig + + +MediaTek image header +===================== +Currently there are two image headers used for MediaTek chips: + + - BootROM image header. This header is used by the first stage bootloader. It records + the desired compatible boot device, integrity information and its load address. + + The on-chip BootROM will firstly verify integrity and compatibility of the bootloader. + + If verification passed, the BootROM will then load the bootloader into on-chip SRAM, + and pass control to it. + + Note that this header is actually a combination of three independent headers: + Device header, BRLYT header and GFH header. + + Used by U-Boot SPL of MT7629 and preloader of MT7623. + + + - MediaTek legacy image header. This header was originally used by the legacy image. It + basically records the load address, image size and image name. + + After all low level initializations passed, the preloader will locate the LK image and + load it into DRAM, and pass control to it. + + Now this header is used by U-Boot of MT7623. + + +To generate these two headers with mkimage: + + # mkimage -T mtk_image -a -n -d + + - mtk_image means using MediaTek's header generation method. + + + - load_addr is the load address of this image. + For first stage bootloader like U-Boot SPL or preloader, it usually points to the + on-chip SRAM. + + For second stage bootloader like U-Boot, it usually points to the DRAM. + + + - option_string contains options to generate the header. + + The option string is using the follow format: + key1=value1;key2=value2;... + + The following key names are valid: + lk: If lk=1, LK image header is used. Otherwise BootROM image header is used. + + lkname: The name of the LK image header. The maximum length is 32. + The default value is "U-Boot". + + media: Desired boot device. The valid values are: + nand : Parallel NAND + snand: Serial NAND + nor : Serial NOR + emmc : eMMC + sdmmc: SD + + nandinfo: Desired NAND device type, a combination of page size, oob size and + optional device capacity. Valid types are: + 2k+64 : for Serial NAND, 2KiB page size + 64B oob size + 2k+120 : for Serial NAND, 2KiB page size + 120B oob size + 2k+128 : for Serial NAND, 2KiB page size + 128B oob size + 4k+256 : for Serial NAND, 4KiB page size + 256B oob size + 1g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 1Gbit size + 2g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 2Gbit size + 4g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 4Gbit size + 2g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 2Gbit size + 4g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 4Gbit size + + +MT7629 partitions on Serial NOR +=============================== + + Start End Size Description + 00000000 - 0000ffff: 64KiB U-Boot SPL + 00010000 - 0005ffff: 320KiB U-Boot + 00060000 - 0006ffff: 64KiB U-Boot env / MediaTek NVRAM + 00070000 - 000affff: 256KiB RF calibration data + 000b0000 - xxxxxxxx: all left Firmware image + + +BPi-R2 (MT7623N) partitions on SD +================================= + Please note that the last two partitions can vary from different Linux distributions + depending on the MBR partition table. + + Start End Size Description + 00000000 - 000001ff: 512B Device header (with MBR partition table) + 00000200 - 000007ff: 1536B BRLYT header + 00000800 - 0004ffff: 318KiB Preloader (with GFH header) + 00050000 - 000fffff: 704KiB U-Boot + 00100000 - 063fffff: 99MiB Reserved + 06400000 - 163fffff: 256MiB Partition 1 (FAT32) + 16400000 - xxxxxxxx: all left Partition 2 (ext4) + + +Upgrading notice on Serial NOR +============================== +Example: MT7629 + + The command sf is used to operate the Serial NOR device: + + - To probe current NOR flash: + + # sf probe + + - To erase a region: + + # sf erase + + - To write data to an offset: + + # sf write + + - To boot kernel: + + # bootm 0x300b0000 + + The memory address range 0x30000000 - 0x3fffffff is mapped to the NOR flash. + The DRAM starts at 0x40000000. + + Please note that the output binary u-boot-mtk.bin is a combination of SPL and U-Boot, + and it should be write to beginning of the flash. + + Otherwise you should use standalone files: + + spl/u-boot-spl-mtk.bin for SPL, + u-boot.img for U-Boot. + + +Upgrading notice on SD / eMMC +============================= +Example: MT7623 + + Normally only Preloader and U-Boot can be upgraded within U-Boot, and other partitions + should be written in PC. + + - To probe current SD card / eMMC: + + # mmc dev 0 for eMMC + # mmc dev 1 for SD + + - To erase a region: + + # mmc erase + + - To write data to a block offset: + + # mmc write + + - To load kernel image from partition 1: + + # fatload mmc 0:1 for eMMC + # fatload mmc 1:1 for SD + + - To boot kernel: + + # bootm + + The DRAM starts at 0x80000000. + + Please note that we use block offset and block count for SD card, not the byte offset. + The block size is always 512 bytes for SD card. + + +Documentation +============= + http://wiki.banana-pi.org/Banana_Pi_BPI-R2 diff --git a/doc/README.odroid b/doc/README.odroid index c088ec4cb0..bc77ae3175 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -1,11 +1,11 @@ - U-Boot for Odroid X2/U3/XU3/XU4 + U-Boot for Odroid X2/U3/XU3/XU4/HC1 ======================== 1. Summary ========== This is a quick instruction for setup Odroid boards. Board config: odroid_config for X2/U3 -Board config: odroid-xu3_config for XU3/XU4 +Board config: odroid-xu3_config for XU3/XU4/HC1 2. Supported devices ==================== @@ -15,6 +15,7 @@ This U-BOOT config can be used on three boards: with CPU Exynos 4412 rev 2.0 and 2GB of RAM - Odroid XU3 - Odroid XU4 +- Odroid HC1 with CPU Exynos5422 and 2GB of RAM 3. Boot sequence @@ -121,7 +122,9 @@ Supported fdt files are: - exynos4412-odroidx2.dtb - exynos4412-odroidu3.dtb - exynos5422-odroidxu3.dtb +- exynos5422-odroidxu3-lite.dtb - exynos5422-odroidxu4.dtb +- exynos5422-odroidhc1.dtb Supported kernel files are: - Image.itb diff --git a/doc/README.qemu-arm b/doc/README.qemu-arm index 260165638a..e67bc13f70 100644 --- a/doc/README.qemu-arm +++ b/doc/README.qemu-arm @@ -47,6 +47,12 @@ The minimal QEMU command line to get U-Boot up and running is: Note that for some odd reason qemu-system-aarch64 needs to be explicitly told to use a 64-bit CPU or it will boot in 32-bit mode. +Additional persistent U-boot environment support can be added as follows: +- Create envstore.img using qemu-img: + qemu-img create -f raw envstore.img 64M +- Add a pflash drive parameter to the command line: + -drive if=pflash,format=raw,index=1,file=envstore.img + Additional peripherals that have been tested to work in both U-Boot and Linux can be enabled with the following command line parameters: diff --git a/doc/README.trace b/doc/README.trace index 74ba26a5a4..2e7ca3319a 100644 --- a/doc/README.trace +++ b/doc/README.trace @@ -88,7 +88,7 @@ stdin=serial stdout=serial Environment size: 117/8188 bytes -=>sb save host 0 trace 0 ${profoffset} +=>host save host 0 trace 0 ${profoffset} 11405888 bytes written in 10 ms (1.1 GiB/s) =>reset diff --git a/doc/README.video b/doc/README.video index 09a26b1793..ced35bd2db 100644 --- a/doc/README.video +++ b/doc/README.video @@ -75,3 +75,23 @@ The sunxi U-Boot driver supports the following video-mode options: For example to always use the hdmi connector, even if no cable is inserted, using edid info when available and otherwise initalizing it at 1024x768@60Hz, use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1". + + +TrueType fonts +-------------- + +U-Boot supports the use of antialiased TrueType fonts on some platforms. This +has been tested in x86, ARMv7 and sandbox. + +To enable this, select CONFIG_CONSOLE_TRUETYPE. You can choose between several +fonts, with CONSOLE_TRUETYPE_NIMBUS being the default. + +TrueType support requires floating point at present. On ARMv7 platforms you +need to disable use of the private libgcc. You can do this by disabling +CONFIG_USE_PRIVATE_LIBGCC. See chromebook_jerry for an example. Note that this +increases U-Boot's size by about 70KB at present. + +On ARM you should also make sure your toolchain supports hardfp. This is +normally given in the name of your toolchain, e.g. arm-linux-gnueabihf (hf +means hardware floating point). You can also run gcc with -v to see if it has +this option. diff --git a/doc/README.virtio b/doc/README.virtio new file mode 100644 index 0000000000..d3652f2e2f --- /dev/null +++ b/doc/README.virtio @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +VirtIO Support +============== + +This document describes the information about U-Boot support for VirtIO [1] +devices, including supported boards, build instructions, driver details etc. + +What's VirtIO? +-------------- +VirtIO is a virtualization standard for network and disk device drivers where +just the guest's device driver "knows" it is running in a virtual environment, +and cooperates with the hypervisor. This enables guests to get high performance +network and disk operations, and gives most of the performance benefits of +paravirtualization. In the U-Boot case, the guest is U-Boot itself, while the +virtual environment are normally QEMU [2] targets like ARM, RISC-V and x86. + +Status +------ +VirtIO can use various different buses, aka transports as described in the +spec. While VirtIO devices are commonly implemented as PCI devices on x86, +embedded devices models like ARM/RISC-V, which does not normally come with +PCI support might use simple memory mapped device (MMIO) instead of the PCI +device. The memory mapped virtio device behaviour is based on the PCI device +specification. Therefore most operations including device initialization, +queues configuration and buffer transfers are nearly identical. Both MMIO +and PCI transport options are supported in U-Boot. + +The VirtIO spec defines a lots of VirtIO device types, however at present only +network and block device, the most two commonly used devices, are supported. + +The following QEMU targets are supported. + + - qemu_arm_defconfig + - qemu_arm64_defconfig + - qemu-riscv32_defconfig + - qemu-riscv64_defconfig + - qemu-x86_defconfig + - qemu-x86_64_defconfig + +Note ARM and RISC-V targets are configured with VirtIO MMIO transport driver, +and on x86 it's the PCI transport driver. + +Build Instructions +------------------ +Building U-Boot for pre-configured QEMU targets is no different from others. +For example, we can do the following with the CROSS_COMPILE environment +variable being properly set to a working toolchain for ARM: + + $ make qemu_arm_defconfig + $ make + +You can even create a QEMU ARM target with VirtIO devices showing up on both +MMIO and PCI buses. In this case, you can enable the PCI transport driver +from 'make menuconfig': + +Device Drivers ---> + ... + VirtIO Drivers ---> + ... + [*] PCI driver for virtio devices + +Other drivers are at the same location and can be tuned to suit the needs. + +Requirements +------------ +It is required that QEMU v2.5.0+ should be used to test U-Boot VirtIO support +on QEMU ARM and x86, and v2.12.0+ on QEMU RISC-V. + +Testing +------- +The following QEMU command line is used to get U-Boot up and running with +VirtIO net and block devices on ARM. + + $ qemu-system-arm -nographic -machine virt -bios u-boot.bin \ + -netdev tap,ifname=tap0,id=net0 \ + -device virtio-net-device,netdev=net0 \ + -drive if=none,file=test.img,format=raw,id=hd0 \ + -device virtio-blk-device,drive=hd0 + +On x86, command is slightly different to create PCI VirtIO devices. + + $ qemu-system-i386 -nographic -bios u-boot.rom \ + -netdev tap,ifname=tap0,id=net0 \ + -device virtio-net-pci,netdev=net0 \ + -drive if=none,file=test.img,format=raw,id=hd0 \ + -device virtio-blk-pci,drive=hd0 + +Additional net and block devices can be created by appending more '-device' +parameters. It is also possible to specify both MMIO and PCI VirtIO devices. +For example, the following commnad creates 3 VirtIO devices, with 1 on MMIO +and 2 on PCI bus. + + $ qemu-system-arm -nographic -machine virt -bios u-boot.bin \ + -netdev tap,ifname=tap0,id=net0 \ + -device virtio-net-pci,netdev=net0 \ + -drive if=none,file=test0.img,format=raw,id=hd0 \ + -device virtio-blk-device,drive=hd0 \ + -drive if=none,file=test1.img,format=raw,id=hd1 \ + -device virtio-blk-pci,drive=hd1 + +By default QEMU creates VirtIO legacy devices by default. To create non-legacy +(aka modern) devices, pass additional device property/value pairs like below: + + $ qemu-system-i386 -nographic -bios u-boot.rom \ + -netdev tap,ifname=tap0,id=net0 \ + -device virtio-net-pci,netdev=net0,disable-legacy=true,disable-modern=false \ + -drive if=none,file=test.img,format=raw,id=hd0 \ + -device virtio-blk-pci,drive=hd0,disable-legacy=true,disable-modern=false + +A 'virtio' command is provided in U-Boot shell. + + => virtio + virtio - virtio block devices sub-system + + Usage: + virtio scan - initialize virtio bus + virtio info - show all available virtio block devices + virtio device [dev] - show or set current virtio block device + virtio part [dev] - print partition table of one or all virtio block devices + virtio read addr blk# cnt - read `cnt' blocks starting at block + `blk#' to memory address `addr' + virtio write addr blk# cnt - write `cnt' blocks starting at block + `blk#' from memory address `addr' + +To probe all the VirtIO devices, type: + + => virtio scan + +Then we can show the connected block device details by: + + => virtio info + Device 0: QEMU VirtIO Block Device + Type: Hard Disk + Capacity: 4096.0 MB = 4.0 GB (8388608 x 512) + +And list the directories and files on the disk by: + + => ls virtio 0 / + 4096 . + 4096 .. + 16384 lost+found + 4096 dev + 4096 proc + 4096 sys + 4096 var + 4096 etc + 4096 usr + 7 bin + 8 sbin + 7 lib + 9 lib64 + 4096 run + 4096 boot + 4096 home + 4096 media + 4096 mnt + 4096 opt + 4096 root + 4096 srv + 4096 tmp + 0 .autorelabel + +Driver Internals +---------------- +There are 3 level of drivers in the VirtIO driver family. + + +---------------------------------------+ + | virtio device drivers | + | +-------------+ +------------+ | + | | virtio-net | | virtio-blk | | + | +-------------+ +------------+ | + +---------------------------------------+ + +---------------------------------------+ + | virtio transport drivers | + | +-------------+ +------------+ | + | | virtio-mmio | | virtio-pci | | + | +-------------+ +------------+ | + +---------------------------------------+ + +----------------------+ + | virtio uclass driver | + +----------------------+ + +The root one is the virtio uclass driver (virtio-uclass.c), which does lots of +common stuff for the transport drivers (virtio_mmio.c, virtio_pci.c). The real +virtio device is discovered in the transport driver's probe() method, and its +device ID is saved in the virtio uclass's private data of the transport device. +Then in the virtio uclass's post_probe() method, the real virtio device driver +(virtio_net.c, virtio_blk.c) is bound if there is a match on the device ID. + +The child_post_bind(), child_pre_probe() and child_post_probe() methods of the +virtio uclass driver help bring the virtio device driver online. They do things +like acknowledging device, feature negotiation, etc, which are really common +for all virtio devices. + +The transport drivers provide a set of ops (struct dm_virtio_ops) for the real +virtio device driver to call. These ops APIs's parameter is designed to remind +the caller to pass the correct 'struct udevice' id of the virtio device, eg: + +int virtio_get_status(struct udevice *vdev, u8 *status) + +So the parameter 'vdev' indicates the device should be the real virtio device. +But we also have an API like: + +struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, + unsigned int vring_align, + struct udevice *udev) + +Here the parameter 'udev' indicates the device should be the transport device. +Similar naming is applied in other functions that are even not APIs, eg: + +static int virtio_uclass_post_probe(struct udevice *udev) +static int virtio_uclass_child_pre_probe(struct udevice *vdev) + +So it's easy to tell which device these functions are operating on. + +Development Flow +---------------- +At present only VirtIO network card (device ID 1) and block device (device +ID 2) are supported. If you want to develop new driver for new devices, +please follow the guideline below. + +1. add new device ID in virtio.h +#define VIRTIO_ID_XXX X + +2. update VIRTIO_ID_MAX_NUM to be the largest device ID plus 1 + +3. add new driver name string in virtio.h +#define VIRTIO_XXX_DRV_NAME "virtio-xxx" + +4. create a new driver with name set to the name string above +U_BOOT_DRIVER(virtio_xxx) = { + .name = VIRTIO_XXX_DRV_NAME, + ... + .remove = virtio_reset, + .flags = DM_FLAG_ACTIVE_DMA, +} + +Note the driver needs to provide the remove method and normally this can be +hooked to virtio_reset(). The driver flags should contain DM_FLAG_ACTIVE_DMA +for the remove method to be called before jumping to OS. + +5. provide bind() method in the driver, where virtio_driver_features_init() + should be called for driver to negotiate feature support with the device. + +6. do funny stuff with the driver + +References +---------- +[1] http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf +[2] https://www.qemu.org diff --git a/doc/README.watchdog b/doc/README.watchdog index 7097c8766b..f23c923910 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -14,7 +14,7 @@ CONFIG_WATCHDOG_TIMEOUT_MSECS If not given, will default to maximum timeout. This would be 128000 msec for i.mx31/35/5x/6x. -CONFIG_AT91SAM9_WATCHDOG +CONFIG_WDT_AT91 Available for AT91SAM9 to service the watchdog. CONFIG_FTWDT010_WATCHDOG diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt index 86c533ad6d..395c9501e3 100644 --- a/doc/device-tree-bindings/chosen.txt +++ b/doc/device-tree-bindings/chosen.txt @@ -42,6 +42,36 @@ Example }; }; +u-boot,bootcount-device property +-------------------------------- + +In a DM-based system, the bootcount may be stored in a device known to +the DM framework (e.g. in a battery-backed SRAM area within a RTC +device) managed by a device conforming to UCLASS_BOOTCOUNT. If +multiple such devices are present in a system concurrently, then the +u-boot,bootcount-device property can select the preferred target. + +Example +------- +/ { + chosen { + u-boot,bootcount-device = &bootcount-rv3029; + }; + + bootcount-rv3029: bootcount@0 { + compatible = "u-boot,bootcount-rtc"; + rtc = &rv3029; + offset = <0x38>; + }; + + i2c2 { + rv3029: rtc@56 { + compatible = "mc,rv3029"; + reg = <0x56>; + }; + }; +}; + u-boot,spl-boot-order property ------------------------------ diff --git a/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt new file mode 100644 index 0000000000..ec97504a3f --- /dev/null +++ b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt @@ -0,0 +1,17 @@ +* MediaTek Frame Engine Ethernet controller + +Required properties: +- compatible: should be "mediatek,mt7628-eth" +- reg: address and length of the register set for the frame + engine ethernet controller and the internal switch. +- syscon: phandle to the system controller + +Example: + +eth@10100000 { + compatible = "mediatek,mt7628-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + + syscon = <&sysc>; +}; diff --git a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt new file mode 100644 index 0000000000..4ed731c524 --- /dev/null +++ b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt @@ -0,0 +1,46 @@ +Texas Instruments' K3 AM654 DDRSS +================================= + +K3 based AM654 devices has DDR memory subsystem that comprises +Synopys DDR controller, Synopsis DDR phy and wrapper logic to +integrate these blocks into the device. This DDR subsystem +provides an interface to external SDRAM devices. This DDRSS driver +adds support for the initialization of the external SDRAM devices by +configuring the DDRSS registers and using the buitin PHY +initialization routines. + +DDRSS device node: +================== +Required properties: +-------------------- +- compatible: Shall be: "ti,am654-ddrss" +- reg-names ss - Map the sub system wrapper logic region + ctl - Map the controller region + phy - Map the PHY region +- reg: Contains the register map per reg-names. +- power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the DDRSS device id + value. This property is as per the binding, + doc/device-tree-bindings/power/ti,sci-pm-domain.txt +- clocks: Must contain an entry for enabling DDR clock. Should + be defined as per the appropriate clock bindings consumer + usage in doc/device-tree-bindings/clock/ti,sci-clk.txt + + +Optional Properties: +-------------------- +- clock-frequency: Frequency at which DDR pll should be locked. + If not provided, default frequency will be used. + +Example (AM65x): +================ + memory-controller: memory-controller@298e000 { + compatible = "ti,am654-ddrss"; + reg = <0x0298e000 0x200>, + <0x02980000 0x4000>, + <0x02988000 0x2000>; + reg-names = "ss", "ctl", "phy"; + clocks = <&k3_clks 20 0>; + power-domains = <&k3_pds 20>; + u-boot,dm-spl; + }; diff --git a/doc/device-tree-bindings/regulator/fan53555.txt b/doc/device-tree-bindings/regulator/fan53555.txt new file mode 100644 index 0000000000..b183738d6c --- /dev/null +++ b/doc/device-tree-bindings/regulator/fan53555.txt @@ -0,0 +1,23 @@ +Binding for Fairchild FAN53555 regulators + +Required properties: + - compatible: "fcs,fan53555" + - reg: I2C address + +Optional properties: + - fcs,suspend-voltage-selector: declare which of the two available + voltage selector registers should be used for the suspend + voltage. The other one is used for the runtime voltage setting + Possible values are either <0> or <1> + - vin-supply: regulator supplying the vin pin + +Example: + + regulator@40 { + compatible = "fcs,fan53555"; + regulator-name = "fan53555"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&parent_reg>; + fcs,suspend-voltage-selector = <1>; + }; diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt index 74c82080fc..69e02c1c4b 100644 --- a/doc/device-tree-bindings/spi/spi-cadence.txt +++ b/doc/device-tree-bindings/spi/spi-cadence.txt @@ -2,7 +2,7 @@ Cadence QSPI controller device tree bindings -------------------------------------------- Required properties: -- compatible : should be "cadence,qspi". +- compatible : should be "cdns,qspi-nor" - reg : 1.Physical base address and size of SPI registers map. 2. Physical base address & size of NOR Flash. - clocks : Clock phandles (see clock bindings for details). diff --git a/doc/device-tree-bindings/w1-eeprom/ds2502.txt b/doc/device-tree-bindings/w1-eeprom/ds2502.txt new file mode 100644 index 0000000000..7f05fc432e --- /dev/null +++ b/doc/device-tree-bindings/w1-eeprom/ds2502.txt @@ -0,0 +1,33 @@ +Maxim DS2502 driver device binding - one wire protocol add only memory from Maxim +======================= + +This memory needs to be connected to a onewire bus, as a child node. +The bus will read the device serial number and match this node with a found +device on the bus +Also check doc/device-tree-bindings/w1 for onewire bus drivers + +Driver: +- drivers/w1-eeprom/ds2502.c + +Ds2502 device-tree node properties: +Required: +* compatible = "maxim,ds2502" + +Optional: +* none + +Example: + eeprom1: eeprom@0 { + compatible = "maxim,ds2502"; + }; + +Example with parent bus: + onewire { + compatible = "fsl,imx53-owire"; + reg = <0x63fa4000 0x4000>; + + eeprom1: eeprom@0 { + compatible = "maxim,ds2502"; + }; + }; + diff --git a/doc/device-tree-bindings/w1/mxc-w1.txt b/doc/device-tree-bindings/w1/mxc-w1.txt new file mode 100644 index 0000000000..1fb49cc111 --- /dev/null +++ b/doc/device-tree-bindings/w1/mxc-w1.txt @@ -0,0 +1,37 @@ +NXP i.MX (MXC) One wire bus master controller +======================= + +Child nodes are required in device tree. The driver will detect +the devices serial number and then search in the child nodes in the device tree +for the proper node and try to match it with the device. + +Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers + +Driver: +- drivers/w1/mxc_w1.c + +Required properties: +- compatible : should be one of + "fsl,imx21-owire", "fsl,imx27-owire", "fsl,imx31-owire", "fsl,imx25-owire" + "fsl,imx25-owire", "fsl,imx35-owire", "fsl,imx50-owire", "fsl,imx53-owire" + +- reg : Address and length of the register set for the device + +Optional: +* none + +Example: + onewire { + compatible = "fsl,imx53-owire"; + reg = <0x63fa4000 0x4000>; + }; + +Example with child: + onewire { + compatible = "fsl,imx53-owire"; + reg = <0x63fa4000 0x4000>; + + eeprom1: eeprom@0 { + compatible = "maxim,ds24xxx"; + }; + }; diff --git a/doc/driver-model/MIGRATION.txt b/doc/driver-model/MIGRATION.txt index 5ebefd608b..183d7f5293 100644 --- a/doc/driver-model/MIGRATION.txt +++ b/doc/driver-model/MIGRATION.txt @@ -5,19 +5,48 @@ U-Boot has been migrating to a new driver model since its introduction in 2014. This file describes the schedule for deprecation of pre-driver-model features. +CONFIG_DM_MMC +------------- + +Status: In progress +Deadline: 2019.04 + +The subsystem itself has been converted and maintainers should submit patches +switching over to using CONFIG_DM_MMC and other base driver model options in +time for inclusion in the 2019.04 rerelease. + +CONFIG_DM_USB +------------- + +Status: In progress +Deadline: 2019.07 + +The subsystem itself has been converted along with many of the host controller +and maintainers should submit patches switching over to using CONFIG_DM_USB and +other base driver model options in time for inclusion in the 2019.07 rerelease. + +CONFIG_SATA +----------- + +Status: In progress +Deadline: 2019.07 + +The subsystem itself has been converted along with many of the host controller +and maintainers should submit patches switching over to using CONFIG_AHCI and +other base driver model options in time for inclusion in the 2019.07 rerelease. CONFIG_BLK ---------- Status: In progress -Deadline: 2018.05 +Deadline: 2019.07 -Maintainers should submit patches for enabling CONFIG_BLK on all boards in -time for inclusion in the 2018.05 release. Boards not converted by this -time may be removed in a subsequent release. - -Note that this implies use of driver model for all block devices (e.g. -MMC, USB, SCSI, SATA). +In concert with maintainers migrating their block device usage to the +appropriate DM driver, CONFIG_BLK needs to be set as well. The final deadline +here coincides with the final deadline for migration of the various block +subsystems. At this point we will be able to audit and correct the logic in +Kconfig around using CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE and make +use of CONFIG_BLK / CONFIG_SPL_BLK as needed. CONFIG_DM_SPI CONFIG_DM_SPI_FLASH @@ -26,9 +55,6 @@ CONFIG_DM_SPI_FLASH Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH to move the migration with in the deadline. -Status: In progress -Deadline: 2018.09 - No dm conversion yet: drivers/spi/cf_spi.c drivers/spi/fsl_espi.c @@ -40,6 +66,9 @@ No dm conversion yet: drivers/spi/sh_spi.c drivers/spi/soft_spi_legacy.c + Status: In progress + Deadline: 2019.04 + Partially converted: drivers/spi/atcspi200_spi.c drivers/spi/davinci_spi.c @@ -50,6 +79,10 @@ Partially converted: drivers/spi/omap3_spi.c drivers/spi/ti_qspi.c + Status: In progress + Deadline: 2019.07 + -- Jagan Teki +12/24/2018 03/14/2018 diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index 36541630a2..07b120d512 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -830,10 +830,18 @@ Pre-Relocation Support ---------------------- For pre-relocation we simply call the driver model init function. Only -drivers marked with DM_FLAG_PRE_RELOC or the device tree -'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps -to reduce the driver model overhead. This flag applies to SPL and TPL as -well, if device tree is enabled there. +drivers marked with DM_FLAG_PRE_RELOC or the device tree 'u-boot,dm-pre-reloc' +property are initialised prior to relocation. This helps to reduce the driver +model overhead. This flag applies to SPL and TPL as well, if device tree is +enabled (CONFIG_OF_CONTROL) there. + +Note when device tree is enabled, the device tree 'u-boot,dm-pre-reloc' +property can provide better control granularity on which device is bound +before relocation. While with DM_FLAG_PRE_RELOC flag of the driver all +devices with the same driver are bound, which requires allocation a large +amount of memory. When device tree is not used, DM_FLAG_PRE_RELOC is the +only way for statically declared devices via U_BOOT_DEVICE() to be bound +prior to relocation. It is possible to limit this to specific relocation steps, by using the more specialized 'u-boot,dm-spl' and 'u-boot,dm-tpl' flags diff --git a/doc/driver-model/spi-howto.txt b/doc/driver-model/spi-howto.txt index 1955ffe284..38c26f642b 100644 --- a/doc/driver-model/spi-howto.txt +++ b/doc/driver-model/spi-howto.txt @@ -163,11 +163,6 @@ At this point you should be able to build U-Boot for your board with the empty SPI driver. You still have empty methods in your driver, but we will write these one by one. -If you have spi_init() functions or the like that are called from your -board then the build will fail. Remove these calls and make a note of the -init that needs to be done. - - 7. Set up your platform data structure This will hold the information your driver to operate, like its hardware diff --git a/doc/imx/mkimage/imximage.txt b/doc/imx/mkimage/imximage.txt index 803682f558..f2cf23c5da 100644 --- a/doc/imx/mkimage/imximage.txt +++ b/doc/imx/mkimage/imximage.txt @@ -175,7 +175,7 @@ Warning: setting sector offset for DOS compatiblity We have set 255 heads, 63 sector. We have to set the cylinder. The value to be set can be calculated with: - cilynder = / / / + cylinder = / / / in this example, 1981284352 / 255 / 63 / 512 = 239.x = 239 diff --git a/doc/imx/mkimage/mxsimage.txt b/doc/imx/mkimage/mxsimage.txt index c3975ee5e6..9159f93a97 100644 --- a/doc/imx/mkimage/mxsimage.txt +++ b/doc/imx/mkimage/mxsimage.txt @@ -46,7 +46,7 @@ These semantics and rules will be outlined now. TAG [LAST] - LAST :: Flag denoting the last section in the file - - After a "TAG" unstruction, any of the following instructions may follow + - After a "TAG" instruction, any of the following instructions may follow in any order and any quantity: NOOP @@ -142,7 +142,7 @@ These semantics and rules will be outlined now. - An optional flags lines can be one of the following: DISPLAYPROGRESS - - Enable boot progress output form the BootROM. + - Enable boot progress output from the BootROM. - If the boot progress output from the BootROM is enabled, the BootROM will produce a letter on the Debug UART for each instruction it started processing. diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index a765722679..bfff6fdc73 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -106,6 +106,9 @@ When the image is signed, the following properties are optional: - comment: Additional information about the signer or image +- padding: The padding algorithm, it may be pkcs-1.5 or pss, + if no value is provided we assume pkcs-1.5 + For config bindings (see Signed Configurations below), the following additional properties are optional: diff --git a/drivers/Kconfig b/drivers/Kconfig index 927a2b87f6..e9fbadd13d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -40,6 +40,8 @@ source "drivers/fpga/Kconfig" source "drivers/gpio/Kconfig" +source "drivers/hwspinlock/Kconfig" + source "drivers/i2c/Kconfig" source "drivers/input/Kconfig" @@ -112,6 +114,8 @@ source "drivers/usb/Kconfig" source "drivers/video/Kconfig" +source "drivers/virtio/Kconfig" + source "drivers/w1/Kconfig" source "drivers/w1-eeprom/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index fb38b67541..8c53e05d2f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -2,20 +2,27 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ +obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ +obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/raw/ +obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/ +obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ +obj-$(CONFIG_$(SPL_TPL_)RTC_SUPPORT) += rtc/ obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ +obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ +obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD @@ -23,11 +30,11 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ -obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ @@ -39,19 +46,16 @@ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ -obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ -obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/ -obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ +obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/common/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/ obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ -obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ -obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ +obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ obj-$(CONFIG_SPL_THERMAL) += thermal/ @@ -91,7 +95,6 @@ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ obj-y += sysreset/ -obj-y += tpm/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ @@ -111,4 +114,5 @@ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_W1_EEPROM) += w1-eeprom/ obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/ endif diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c index 738c1eabdc..0a492eba54 100644 --- a/drivers/adc/adc-uclass.c +++ b/drivers/adc/adc-uclass.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -77,6 +78,18 @@ int adc_data_mask(struct udevice *dev, unsigned int *data_mask) return 0; } +int adc_channel_mask(struct udevice *dev, unsigned int *channel_mask) +{ + struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); + + if (!uc_pdata) + return -ENOSYS; + + *channel_mask = uc_pdata->channel_mask; + + return 0; +} + int adc_stop(struct udevice *dev) { const struct adc_ops *ops = dev_get_driver_ops(dev); @@ -329,6 +342,30 @@ int adc_vss_value(struct udevice *dev, int *uV) return 0; } +int adc_raw_to_uV(struct udevice *dev, unsigned int raw, int *uV) +{ + unsigned int data_mask; + int ret, val, vref; + u64 raw64 = raw; + + ret = adc_vdd_value(dev, &vref); + if (ret) + return ret; + + if (!adc_vss_value(dev, &val)) + vref -= val; + + ret = adc_data_mask(dev, &data_mask); + if (ret) + return ret; + + raw64 *= vref; + do_div(raw64, data_mask); + *uV = raw64; + + return 0; +} + static int adc_vdd_platdata_set(struct udevice *dev) { struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 65896d1705..8887be901c 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -82,15 +82,19 @@ #define CEVA_AXICC_CFG 0x3fffffff /* for ls1021a */ -#define LS1021_AHCI_VEND_AXICC 0xC0 +#define LS1021_AHCI_VEND_AXICC 0xC0 #define LS1021_CEVA_PHY2_CFG 0x28183414 #define LS1021_CEVA_PHY3_CFG 0x0e080e06 #define LS1021_CEVA_PHY4_CFG 0x064a080b #define LS1021_CEVA_PHY5_CFG 0x2aa86470 +/* for ls1088a */ +#define LS1088_ECC_DIS_ADDR_CH2 0x100520 +#define LS1088_ECC_DIS_VAL_CH2 0x40000000 + /* ecc addr-val pair */ -#define ECC_DIS_ADDR_CH2 0x80000000 -#define ECC_DIS_VAL_CH2 0x20140520 +#define ECC_DIS_ADDR_CH2 0x20140520 +#define ECC_DIS_VAL_CH2 0x80000000 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 @@ -99,6 +103,9 @@ enum ceva_soc { CEVA_LS1012A, CEVA_LS1021A, CEVA_LS1043A, + CEVA_LS1046A, + CEVA_LS1088A, + CEVA_LS2080A, }; struct ceva_sata_priv { @@ -138,7 +145,18 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) case CEVA_LS1012A: case CEVA_LS1043A: - writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); + case CEVA_LS1046A: + writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); + /* fallthrough */ + case CEVA_LS2080A: + writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); + writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); + if (priv->flag & FLAG_COHERENT) + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); + break; + + case CEVA_LS1088A: + writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); if (priv->flag & FLAG_COHERENT) @@ -170,6 +188,9 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, + { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, + { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, + { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A }, { } }; diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 055d42f7d4..3feb0aa997 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -9,6 +9,8 @@ ifndef CONFIG_$(SPL_)BLK obj-y += blk_legacy.o endif +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_IDE) += ide.o +endif obj-$(CONFIG_SANDBOX) += sandbox.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index facf52711c..baaf431e5e 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -23,6 +23,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = { [IF_TYPE_HOST] = "host", [IF_TYPE_NVME] = "nvme", [IF_TYPE_EFI] = "efi", + [IF_TYPE_VIRTIO] = "virtio", }; static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { @@ -37,6 +38,7 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { [IF_TYPE_HOST] = UCLASS_ROOT, [IF_TYPE_NVME] = UCLASS_NVME, [IF_TYPE_EFI] = UCLASS_EFI, + [IF_TYPE_VIRTIO] = UCLASS_VIRTIO, }; static enum if_type if_typename_to_iftype(const char *if_typename) @@ -471,15 +473,6 @@ unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start, return ops->erase(dev, start, blkcnt); } -int blk_prepare_device(struct udevice *dev) -{ - struct blk_desc *desc = dev_get_uclass_platdata(dev); - - part_init(desc); - - return 0; -} - int blk_get_from_parent(struct udevice *parent, struct udevice **devp) { struct udevice *dev; @@ -526,7 +519,7 @@ int blk_find_max_devnum(enum if_type if_type) return max_devnum; } -static int blk_next_free_devnum(enum if_type if_type) +int blk_next_free_devnum(enum if_type if_type) { int ret; @@ -644,8 +637,20 @@ int blk_unbind_all(int if_type) return 0; } +static int blk_post_probe(struct udevice *dev) +{ +#if defined(CONFIG_PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE) + struct blk_desc *desc = dev_get_uclass_platdata(dev); + + part_init(desc); +#endif + + return 0; +} + UCLASS_DRIVER(blk) = { .id = UCLASS_BLK, .name = "blk", + .post_probe = blk_post_probe, .per_device_platdata_auto_alloc_size = sizeof(struct blk_desc), }; diff --git a/drivers/block/ide.c b/drivers/block/ide.c index 38adb6a241..4b8a4eac17 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -1169,8 +1169,6 @@ static int ide_blk_probe(struct udevice *udev) BLK_REV_SIZE); desc->revision[BLK_REV_SIZE] = '\0'; - part_init(desc); - return 0; } diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 0392437309..d3b1aaaba3 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -33,7 +33,7 @@ static unsigned long host_block_read(struct udevice *dev, unsigned long start, lbaint_t blkcnt, void *buffer) { - struct host_block_dev *host_dev = dev_get_priv(dev); + struct host_block_dev *host_dev = dev_get_platdata(dev); struct blk_desc *block_dev = dev_get_uclass_platdata(dev); #else @@ -64,7 +64,7 @@ static unsigned long host_block_write(struct udevice *dev, unsigned long start, lbaint_t blkcnt, const void *buffer) { - struct host_block_dev *host_dev = dev_get_priv(dev); + struct host_block_dev *host_dev = dev_get_platdata(dev); struct blk_desc *block_dev = dev_get_uclass_platdata(dev); #else static unsigned long host_block_write(struct blk_desc *block_dev, @@ -131,17 +131,18 @@ int host_dev_bind(int devnum, char *filename) os_lseek(fd, 0, OS_SEEK_END) / 512, &dev); if (ret) goto err_file; + + host_dev = dev_get_platdata(dev); + host_dev->fd = fd; + host_dev->filename = fname; + ret = device_probe(dev); if (ret) { device_unbind(dev); goto err_file; } - host_dev = dev_get_priv(dev); - host_dev->fd = fd; - host_dev->filename = fname; - - return blk_prepare_device(dev); + return 0; err_file: os_close(fd); err: @@ -226,7 +227,7 @@ U_BOOT_DRIVER(sandbox_host_blk) = { .name = "sandbox_host_blk", .id = UCLASS_BLK, .ops = &sandbox_host_blk_ops, - .priv_auto_alloc_size = sizeof(struct host_block_dev), + .platdata_auto_alloc_size = sizeof(struct host_block_dev), }; #else U_BOOT_LEGACY_BLK(sandbox_host) = { diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 67033637c0..b7c29f2fd3 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -70,8 +70,36 @@ config BOOTCOUNT_AT91 bool "Boot counter for Atmel AT91SAM9XE" depends on AT91SAM9XE +config DM_BOOTCOUNT + bool "Boot counter in a device-model device" + help + Enables reading/writing the bootcount in a device-model based + backing store. If an entry in /chosen/u-boot,bootcount-device + exists, this will be the preferred bootcount device; otherwise + the first available bootcount device will be used. + endchoice +if DM_BOOTCOUNT + +menu "Backing stores for device-model backed bootcount" +config DM_BOOTCOUNT_RTC + bool "Support RTC devices as a backing store for bootcount" + depends on DM_RTC + help + Enabled reading/writing the bootcount in a DM RTC device. + The wrapper device is to be specified with the compatible string + 'u-boot,bootcount-rtc' and the 'rtc'-property (a phandle pointing + to the underlying RTC device) and an optional 'offset' property + are supported. + + Accesses to the backing store are performed using the write16 + and read16 ops of DM RTC devices. + +endmenu + +endif + config BOOTCOUNT_BOOTLIMIT int "Maximum number of reboot cycles allowed" default 0 diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 68bc006b75..f9841d8615 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -7,3 +7,6 @@ obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o + +obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o +obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o diff --git a/drivers/bootcount/bootcount-uclass.c b/drivers/bootcount/bootcount-uclass.c new file mode 100644 index 0000000000..0689db7a5b --- /dev/null +++ b/drivers/bootcount/bootcount-uclass.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include + +int dm_bootcount_get(struct udevice *dev, u32 *bootcount) +{ + struct bootcount_ops *ops = bootcount_get_ops(dev); + + assert(ops); + if (!ops->get) + return -ENOSYS; + return ops->get(dev, bootcount); +} + +int dm_bootcount_set(struct udevice *dev, const u32 bootcount) +{ + struct bootcount_ops *ops = bootcount_get_ops(dev); + + assert(ops); + if (!ops->set) + return -ENOSYS; + return ops->set(dev, bootcount); +} + +/* Now implement the generic default functions */ +void bootcount_store(ulong val) +{ + struct udevice *dev = NULL; + ofnode node; + const char *propname = "u-boot,bootcount-device"; + int ret = -ENODEV; + + /* + * If there's a preferred bootcount device selected by the user (by + * setting '/chosen/u-boot,bootcount-device' in the DTS), try to use + * it if available. + */ + node = ofnode_get_chosen_node(propname); + if (ofnode_valid(node)) + ret = uclass_get_device_by_ofnode(UCLASS_BOOTCOUNT, node, &dev); + + /* If there was no user-selected device, use the first available one */ + if (ret) + ret = uclass_get_device(UCLASS_BOOTCOUNT, 0, &dev); + + if (dev) + ret = dm_bootcount_set(dev, val); + + if (ret) + pr_debug("%s: failed to store 0x%lx\n", __func__, val); +} + +ulong bootcount_load(void) +{ + struct udevice *dev = NULL; + ofnode node; + const char *propname = "u-boot,bootcount-device"; + int ret = -ENODEV; + u32 val; + + /* + * If there's a preferred bootcount device selected by the user (by + * setting '/chosen/u-boot,bootcount-device' in the DTS), try to use + * it if available. + */ + node = ofnode_get_chosen_node(propname); + if (ofnode_valid(node)) + ret = uclass_get_device_by_ofnode(UCLASS_BOOTCOUNT, node, &dev); + + /* If there was no user-selected device, use the first available one */ + if (ret) + ret = uclass_get_device(UCLASS_BOOTCOUNT, 0, &dev); + + if (dev) + ret = dm_bootcount_get(dev, &val); + + if (ret) + pr_debug("%s: failed to load bootcount\n", __func__); + + /* Return the 0, if the call to dm_bootcount_get failed */ + return ret ? 0 : val; +} + +UCLASS_DRIVER(bootcount) = { + .name = "bootcount", + .id = UCLASS_BOOTCOUNT, +}; diff --git a/drivers/bootcount/rtc.c b/drivers/bootcount/rtc.c new file mode 100644 index 0000000000..db89fa3a35 --- /dev/null +++ b/drivers/bootcount/rtc.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include + +static const u8 bootcount_magic = 0xbc; + +struct bootcount_rtc_priv { + struct udevice *rtc; + u32 offset; +}; + +static int bootcount_rtc_set(struct udevice *dev, const u32 a) +{ + struct bootcount_rtc_priv *priv = dev_get_priv(dev); + const u16 val = bootcount_magic << 8 | (a & 0xff); + + if (rtc_write16(priv->rtc, priv->offset, val) < 0) { + debug("%s: rtc_write16 failed\n", __func__); + return -EIO; + } + + return 0; +} + +static int bootcount_rtc_get(struct udevice *dev, u32 *a) +{ + struct bootcount_rtc_priv *priv = dev_get_priv(dev); + u16 val; + + if (rtc_read16(priv->rtc, priv->offset, &val) < 0) { + debug("%s: rtc_write16 failed\n", __func__); + return -EIO; + } + + if (val >> 8 == bootcount_magic) { + *a = val & 0xff; + return 0; + } + + debug("%s: bootcount magic does not match on %04x\n", __func__, val); + return -EIO; +} + +static int bootcount_rtc_probe(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + struct bootcount_rtc_priv *priv = dev_get_priv(dev); + struct udevice *rtc; + + if (dev_read_phandle_with_args(dev, "rtc", NULL, 0, 0, &phandle_args)) { + debug("%s: rtc backing device not specified\n", dev->name); + return -ENOENT; + } + + if (uclass_get_device_by_ofnode(UCLASS_RTC, phandle_args.node, &rtc)) { + debug("%s: could not get backing device\n", dev->name); + return -ENODEV; + } + + priv->rtc = rtc; + priv->offset = dev_read_u32_default(dev, "offset", 0); + + return 0; +} + +static const struct bootcount_ops bootcount_rtc_ops = { + .get = bootcount_rtc_get, + .set = bootcount_rtc_set, +}; + +static const struct udevice_id bootcount_rtc_ids[] = { + { .compatible = "u-boot,bootcount-rtc" }, + { } +}; + +U_BOOT_DRIVER(bootcount_rtc) = { + .name = "bootcount-rtc", + .id = UCLASS_BOOTCOUNT, + .priv_auto_alloc_size = sizeof(struct bootcount_rtc_priv), + .probe = bootcount_rtc_probe, + .of_match = bootcount_rtc_ids, + .ops = &bootcount_rtc_ops, +}; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 821b5867e8..9acbb1a650 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,7 +9,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ -obj-$(CONFIG_ARCH_MESON) += clk_meson.o +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ +obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index 78102c760d..612a1718dc 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -352,7 +352,6 @@ static const struct udevice_id socfpga_a10_clk_match[] = { U_BOOT_DRIVER(socfpga_a10_clk) = { .name = "clk-a10", .id = UCLASS_CLK, - .flags = DM_FLAG_PRE_RELOC, .of_match = socfpga_a10_clk_match, .ops = &socfpga_a10_clk_ops, .bind = socfpga_a10_clk_bind, diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 526470051c..dbee13a182 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk) return rate; } +struct ast2500_clock_config { + ulong input_rate; + ulong rate; + struct ast2500_div_config cfg; +}; + +static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { + { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, +}; + +static bool ast2500_get_clock_config_default(ulong input_rate, + ulong requested_rate, + struct ast2500_div_config *cfg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { + const struct ast2500_clock_config *default_cfg = + &ast2500_clock_config_defaults[i]; + if (default_cfg->input_rate == input_rate && + default_cfg->rate == requested_rate) { + *cfg = default_cfg->cfg; + return true; + } + } + + return false; +} + /* * @input_rate - the rate of input clock in Hz * @requested_rate - desired output rate in Hz @@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, ulong delta = rate_khz; ulong new_rate_khz = 0; + /* + * Look for a well known frequency first. + */ + if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) + return requested_rate; + for (; it.denum <= max_vals.denum; ++it.denum) { for (it.post_div = 0; it.post_div <= max_vals.post_div; ++it.post_div) { @@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) /* * The values and the meaning of the next three * parameters are undocumented. Taken from Aspeed SDK. + * + * TODO(clg@kaod.org): the SIP and SIC values depend on the + * Numerator value */ const u32 d2_pll_ext_param = 0x2c; const u32 d2_pll_sip = 0x11; @@ -411,6 +449,7 @@ static int ast2500_clk_enable(struct clk *clk) break; case PLL_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); + break; default: return -ENOENT; } diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 2b15978e14..6d7a514006 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -243,8 +243,8 @@ int clk_set_defaults(struct udevice *dev) { int ret; - /* If this is running pre-reloc state, don't take any action. */ - if (!(gd->flags & GD_FLG_RELOC)) + /* If this not in SPL and pre-reloc state, don't take any action. */ + if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) return 0; debug("%s(%s)\n", __func__, dev_read_name(dev)); diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 236d7342b7..2cb53fb92d 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -6,11 +6,13 @@ */ #include -#include +#include #include #include #include #include +#include +#include #include #include "clk_meson.h" @@ -65,7 +67,7 @@ #define XTAL_RATE 24000000 struct meson_clk { - void __iomem *addr; + struct regmap *map; }; static ulong meson_div_get_rate(struct clk *clk, unsigned long id); @@ -79,7 +81,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, static ulong meson_mux_get_parent(struct clk *clk, unsigned long id); static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); -struct meson_gate gates[] = { +static struct meson_gate gates[] = { /* Everything Else (EE) domain gates */ MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0), MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1), @@ -217,8 +219,8 @@ static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on) debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id); - clrsetbits_le32(priv->addr + gate->reg, - BIT(gate->bit), on ? BIT(gate->bit) : 0); + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); /* Propagate to next gate(s) */ switch (id) { @@ -269,7 +271,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) unsigned int rate, parent_rate; struct parm *parm; int parent; - u32 reg; + uint reg; switch (id) { case CLKID_VPU_0_DIV: @@ -292,7 +294,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + parm->reg_off); + regmap_read(priv->map, parm->reg_off, ®); reg = PARM_GET(parm->width, parm->shift, reg); debug("%s: div of %ld is %d\n", __func__, id, reg + 1); @@ -318,7 +320,6 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, unsigned long parent_rate; struct parm *parm; int parent; - u32 reg; int ret; if (current_rate == rate) @@ -383,9 +384,8 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, debug("%s: setting div of %ld to %d\n", __func__, id, new_div); - reg = readl(priv->addr + parm->reg_off); - writel(PARM_SET(parm->width, parm->shift, reg, new_div - 1), - priv->addr + parm->reg_off); + regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), + (new_div - 1) << parm->shift); debug("%s: new rate of %ld is %ld\n", __func__, id, meson_div_get_rate(clk, id)); @@ -446,7 +446,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) struct meson_clk *priv = dev_get_priv(clk->dev); struct parm *parm; int *parents; - u32 reg; + uint reg; switch (id) { case CLKID_VPU: @@ -477,7 +477,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + parm->reg_off); + regmap_read(priv->map, parm->reg_off, ®); reg = PARM_GET(parm->width, parm->shift, reg); debug("%s: parent of %ld is %d (%d)\n", @@ -494,7 +494,6 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, unsigned int new_index = -EINVAL; struct parm *parm; int *parents; - u32 reg; int i; if (IS_ERR_VALUE(cur_parent)) @@ -546,9 +545,8 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, debug("%s: new index of %ld is %d\n", __func__, id, new_index); - reg = readl(priv->addr + parm->reg_off); - writel(PARM_SET(parm->width, parm->shift, reg, new_index), - priv->addr + parm->reg_off); + regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), + new_index << parm->shift); debug("%s: new parent of %ld is %ld\n", __func__, id, meson_mux_get_parent(clk, id)); @@ -570,7 +568,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) { struct meson_clk *priv = dev_get_priv(clk->dev); unsigned long parent_rate; - u32 reg; + uint reg; int parents[] = { -1, -1, @@ -583,7 +581,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) }; /* mux */ - reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); reg = (reg >> 12) & 7; switch (reg) { @@ -597,10 +595,11 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) } /* divider */ - reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); reg = reg & ((1 << 7) - 1); - return parent_rate / reg; + /* clk81 divider is zero based */ + return parent_rate / (reg + 1); } static long mpll_rate_from_params(unsigned long parent_rate, @@ -640,8 +639,9 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); struct parm *psdm, *pn2; - unsigned long reg, sdm, n2; + unsigned long sdm, n2; unsigned long parent_rate; + uint reg; switch (id) { case CLKID_MPLL0: @@ -664,10 +664,10 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) if (IS_ERR_VALUE(parent_rate)) return parent_rate; - reg = readl(priv->addr + psdm->reg_off); + regmap_read(priv->map, psdm->reg_off, ®); sdm = PARM_GET(psdm->width, psdm->shift, reg); - reg = readl(priv->addr + pn2->reg_off); + regmap_read(priv->map, pn2->reg_off, ®); n2 = PARM_GET(pn2->width, pn2->shift, reg); return mpll_rate_from_params(parent_rate, sdm, n2); @@ -691,7 +691,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) struct parm *pm, *pn, *pod; unsigned long parent_rate_mhz = XTAL_RATE / 1000000; u16 n, m, od; - u32 reg; + uint reg; switch (id) { case CLKID_FIXED_PLL: @@ -708,13 +708,13 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + pn->reg_off); + regmap_read(priv->map, pn->reg_off, ®); n = PARM_GET(pn->width, pn->shift, reg); - reg = readl(priv->addr + pm->reg_off); + regmap_read(priv->map, pm->reg_off, ®); m = PARM_GET(pm->width, pm->shift, reg); - reg = readl(priv->addr + pod->reg_off); + regmap_read(priv->map, pod->reg_off, ®); od = PARM_GET(pod->width, pod->shift, reg); return ((parent_rate_mhz * m / n) >> od) * 1000000; @@ -790,7 +790,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) return -ENOENT; } - printf("clock %lu has rate %lu\n", id, rate); + debug("clock %lu has rate %lu\n", id, rate); return rate; } @@ -875,8 +875,8 @@ static ulong meson_clk_set_rate(struct clk *clk, ulong rate) if (IS_ERR_VALUE(ret)) return ret; - printf("clock %lu has new rate %lu\n", clk->id, - meson_clk_get_rate_by_id(clk, clk->id)); + debug("clock %lu has new rate %lu\n", clk->id, + meson_clk_get_rate_by_id(clk, clk->id)); return 0; } @@ -885,9 +885,11 @@ static int meson_clk_probe(struct udevice *dev) { struct meson_clk *priv = dev_get_priv(dev); - priv->addr = dev_read_addr_ptr(dev); + priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); - debug("meson-clk: probed at addr %p\n", priv->addr); + debug("meson-clk: probed\n"); return 0; } diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/clk_meson_axg.c new file mode 100644 index 0000000000..32cbf752ae --- /dev/null +++ b/drivers/clk/clk_meson_axg.c @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 - Beniamino Galvani + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk_meson.h" + +#define XTAL_RATE 24000000 + +struct meson_clk { + struct regmap *map; +}; + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); + +static struct meson_gate gates[] = { + /* Everything Else (EE) domain gates */ + MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8), + MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9), + MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13), + MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15), + MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25), + MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26), + MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3), + MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16), + + /* Always On (AO) domain gates */ + MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4), + + /* PLL Gates */ + /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */ + MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14), + /* CLKID_CLK81 is critical for the system */ + + /* Peripheral Gates */ + MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23), + MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7), +}; + +static int meson_set_gate(struct clk *clk, bool on) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct meson_gate *gate; + + if (clk->id >= ARRAY_SIZE(gates)) + return -ENOENT; + + gate = &gates[clk->id]; + + if (gate->reg == 0) + return 0; + + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); + + return 0; +} + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate(clk, true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate(clk, false); +} + +static unsigned long meson_clk81_get_rate(struct clk *clk) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned long parent_rate; + uint reg; + int parents[] = { + -1, + -1, + CLKID_FCLK_DIV7, + CLKID_MPLL1, + CLKID_MPLL2, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5 + }; + + /* mux */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = (reg >> 12) & 7; + + switch (reg) { + case 0: + parent_rate = XTAL_RATE; + break; + case 1: + return -ENOENT; + default: + parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]); + } + + /* divider */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = reg & ((1 << 7) - 1); + + return parent_rate / reg; +} + +static long mpll_rate_from_params(unsigned long parent_rate, + unsigned long sdm, + unsigned long n2) +{ + unsigned long divisor = (SDM_DEN * n2) + sdm; + + if (n2 < N2_MIN) + return -EINVAL; + + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); +} + +static struct parm meson_mpll0_parm[3] = { + {HHI_MPLL_CNTL7, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */ +}; + +static struct parm meson_mpll1_parm[3] = { + {HHI_MPLL_CNTL8, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */ +}; + +static struct parm meson_mpll2_parm[3] = { + {HHI_MPLL_CNTL9, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */ +}; + +/* + * MultiPhase Locked Loops are outputs from a PLL with additional frequency + * scaling capabilities. MPLL rates are calculated as: + * + * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) + */ +static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *psdm, *pn2; + unsigned long sdm, n2; + unsigned long parent_rate; + uint reg; + + switch (id) { + case CLKID_MPLL0: + psdm = &meson_mpll0_parm[0]; + pn2 = &meson_mpll0_parm[1]; + break; + case CLKID_MPLL1: + psdm = &meson_mpll1_parm[0]; + pn2 = &meson_mpll1_parm[1]; + break; + case CLKID_MPLL2: + psdm = &meson_mpll2_parm[0]; + pn2 = &meson_mpll2_parm[1]; + break; + default: + return -ENOENT; + } + + parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; + + regmap_read(priv->map, psdm->reg_off, ®); + sdm = PARM_GET(psdm->width, psdm->shift, reg); + + regmap_read(priv->map, pn2->reg_off, ®); + n2 = PARM_GET(pn2->width, pn2->shift, reg); + + return mpll_rate_from_params(parent_rate, sdm, n2); +} + +static struct parm meson_fixed_pll_parm[3] = { + {HHI_MPLL_CNTL, 0, 9}, /* pm */ + {HHI_MPLL_CNTL, 9, 5}, /* pn */ + {HHI_MPLL_CNTL, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */ + {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */ + {HHI_SYS_PLL_CNTL, 16, 2}, /* pod */ +}; + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = XTAL_RATE / 1000000; + u16 n, m, od; + uint reg; + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + regmap_read(priv->map, pn->reg_off, ®); + n = PARM_GET(pn->width, pn->shift, reg); + + regmap_read(priv->map, pm->reg_off, ®); + m = PARM_GET(pm->width, pm->shift, reg); + + regmap_read(priv->map, pod->reg_off, ®); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) +{ + ulong rate; + + switch (id) { + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_MPLL0: + case CLKID_MPLL1: + case CLKID_MPLL2: + rate = meson_mpll_get_rate(clk, id); + break; + case CLKID_CLK81: + rate = meson_clk81_get_rate(clk); + break; + default: + if (gates[id].reg != 0) { + /* a clock gate */ + rate = meson_clk81_get_rate(clk); + break; + } + return -ENOENT; + } + + debug("clock %lu has rate %lu\n", id, rate); + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + debug("meson-clk-axg: probed\n"); + + return 0; +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, +}; + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,axg-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk_axg) = { + .name = "meson_clk_axg", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index fdf95a12da..b3ac0d5a92 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -418,7 +418,6 @@ U_BOOT_DRIVER(pic32_clk) = { .name = "pic32_clk", .id = UCLASS_CLK, .of_match = pic32_clk_ids, - .flags = DM_FLAG_PRE_RELOC, .ops = &pic32_pic32_clk_ops, .probe = pic32_clk_probe, .priv_auto_alloc_size = sizeof(struct pic32_clk_priv), diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 6a8c7b754f..b7c5d34fe0 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -104,6 +104,7 @@ #define RCC_MP_APB2ENSETR 0XA08 #define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 +#define RCC_MP_AHB3ENSETR 0xA20 #define RCC_MP_AHB4ENSETR 0xA28 /* used for most of SELR register */ @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 7fef4b2e31..c692a6d0b8 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -29,7 +29,7 @@ static ulong vexpress_osc_clk_get_rate(struct clk *clk) data = CLK_FUNCTION | priv->osc; err = misc_read(vexpress_cfg, 0, &data, sizeof(data)); - if (err) + if (err < 0) return err; return data; @@ -53,7 +53,7 @@ static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) buffer[0] = CLK_FUNCTION | priv->osc; buffer[1] = rate; err = misc_write(vexpress_cfg, 0, buffer, 2 * sizeof(u32)); - if (err) + if (err < 0) return err; return rate; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index d647e0a01e..482f0937cb 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -480,7 +480,6 @@ U_BOOT_DRIVER(zynq_clk) = { .name = "zynq_clk", .id = UCLASS_CLK, .of_match = zynq_clk_ids, - .flags = DM_FLAG_PRE_RELOC, .ops = &zynq_clk_ops, .priv_auto_alloc_size = sizeof(struct zynq_clk_priv), .probe = zynq_clk_probe, diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 763567b17c..aa86c7ca44 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -201,7 +201,6 @@ U_BOOT_DRIVER(exynos7420_clk_topc) = { .probe = exynos7420_clk_topc_probe, .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv), .ops = &exynos7420_clk_topc_ops, - .flags = DM_FLAG_PRE_RELOC, }; static const struct udevice_id exynos7420_clk_top0_compat[] = { @@ -216,7 +215,6 @@ U_BOOT_DRIVER(exynos7420_clk_top0) = { .probe = exynos7420_clk_top0_probe, .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv), .ops = &exynos7420_clk_top0_ops, - .flags = DM_FLAG_PRE_RELOC, }; static const struct udevice_id exynos7420_clk_peric1_compat[] = { @@ -229,5 +227,4 @@ U_BOOT_DRIVER(exynos7420_clk_peric1) = { .id = UCLASS_CLK, .of_match = exynos7420_clk_peric1_compat, .ops = &exynos7420_clk_peric1_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile new file mode 100644 index 0000000000..0632dc87b6 --- /dev/null +++ b/drivers/clk/mediatek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o + +# SoC Drivers +obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o +obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c new file mode 100644 index 0000000000..c6b09d8e18 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7623 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" + +#define MT7623_CLKSQ_STB_CON0 0x18 +#define MT7623_PLL_ISO_CON0 0x24 +#define MT7623_PLL_FMAX (2000UL * MHZ) +#define MT7623_CON0_RST_BAR BIT(27) + +#define MCU_AXI_DIV 0x60 +#define AXI_DIV_MSK GENMASK(4, 0) +#define AXI_DIV_SEL(x) (x) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT7623_CON0_RST_BAR, \ + .fmax = MT7623_PLL_FMAX, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, + 21, 0x204, 24, 0x204, 0), + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, + 21, 0x210, 4, 0x214, 0), + PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, + 7, 0x220, 4, 0x224, 14), + PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0, + 21, 0x230, 4, 0x234, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0, + 21, 0x240, 4, 0x244, 0), + PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0, + 21, 0x250, 4, 0x254, 0), + PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0, + 31, 0x270, 4, 0x274, 0), + PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0, + 31, 0x280, 4, 0x284, 0), + PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0, + 31, 0x290, 4, 0x294, 0), + PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0, + 31, 0x2a0, 4, 0x2a4, 0), + PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0, + 31, 0x2b0, 4, 0x2b4, 0), + PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0, + 31, 0x2c0, 4, 0x2c4, 0), + PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0, + 21, 0x2d0, 4, 0x2d4, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ), + FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ), + FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ), + FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ), + FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ), + FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ), + FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ), + FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ), + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ), + FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ), + FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000), + FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ), + FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0), + FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0), + FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1), + FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), + FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2), + FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4), + FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8), + FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16), + FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2), + FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4), + FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8), + FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2), + FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4), + FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2), + FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4), + + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26), + FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52), + FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108), + FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8), + + FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4), + FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8), + + FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1), + FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2), + + FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2), + FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4), + FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1), + + FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), + FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2), + FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4), + + FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1), + FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1), + FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2), + + FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1), + FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2), + FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4), + + FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1), + FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2), + FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3), + + FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1), + + FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1), + FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4), + FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8), + FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16), + FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24), + + FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3), + FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3), + FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3), + FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1), + FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), + FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793), + FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), + FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), +}; + +static const int axi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_MMPLL_D2, + CLK_TOP_DMPLL_D2 +}; + +static const int mem_parents[] = { + CLK_XTAL, + CLK_TOP_DMPLL +}; + +static const int ddrphycfg_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8 +}; + +static const int mm_parents[] = { + CLK_XTAL, + CLK_TOP_VENCPLL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_DMPLL +}; + +static const int pwm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int vdec_parents[] = { + CLK_XTAL, + CLK_TOP_VDECPLL, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_VENCPLL, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_MMPLL_D2 +}; + +static const int mfg_parents[] = { + CLK_XTAL, + CLK_TOP_MMPLL, + CLK_TOP_DMPLL_X2, + CLK_TOP_MSDCPLL, + CLK_XTAL, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2 +}; + +static const int camtg_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D26, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL3_D2, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_MMPLL_D2 +}; + +static const int uart_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8 +}; + +static const int usb20_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_UNIVPLL3_D4 +}; + +static const int msdc30_parents[] = { + CLK_XTAL, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D4, +}; + +static const int aud_intbus_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL3_D2, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int pmicspi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL_D26, + CLK_TOP_DMPLL_D2, + CLK_TOP_DMPLL_D4 +}; + +static const int scp_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_DMPLL_D2, + CLK_TOP_DMPLL_D4 +}; + +static const int dpi0_tve_parents[] = { + CLK_XTAL, + CLK_TOP_MIPIPLL, + CLK_TOP_MIPIPLL_D2, + CLK_TOP_MIPIPLL_D4, + CLK_XTAL, + CLK_TOP_TVDPLL, + CLK_TOP_TVDPLL_D2, + CLK_TOP_TVDPLL_D4 +}; + +static const int dpi1_parents[] = { + CLK_XTAL, + CLK_TOP_TVDPLL, + CLK_TOP_TVDPLL_D2, + CLK_TOP_TVDPLL_D4 +}; + +static const int hdmi_parents[] = { + CLK_XTAL, + CLK_TOP_HDMIPLL, + CLK_TOP_HDMIPLL_D2, + CLK_TOP_HDMIPLL_D3 +}; + +static const int apll_parents[] = { + CLK_XTAL, + CLK_TOP_AUDPLL, + CLK_TOP_AUDPLL_D4, + CLK_TOP_AUDPLL_D8, + CLK_TOP_AUDPLL_D16, + CLK_TOP_AUDPLL_D24, + CLK_XTAL, + CLK_XTAL +}; + +static const int rtc_parents[] = { + CLK_TOP_32K_INTERNAL, + CLK_TOP_32K_EXTERNAL, + CLK_XTAL, + CLK_TOP_UNIVPLL3_D8 +}; + +static const int nfi2x_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_XTAL +}; + +static const int emmc_hclk_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL2_D2 +}; + +static const int flash_parents[] = { + CLK_TOP_CLK26M_D8, + CLK_XTAL, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int di_parents[] = { + CLK_XTAL, + CLK_TOP_TVD2PLL, + CLK_TOP_TVD2PLL_D2, + CLK_XTAL +}; + +static const int nr_osd_parents[] = { + CLK_XTAL, + CLK_TOP_VENCPLL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_DMPLL +}; + +static const int hdmirx_bist_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL_D3, + CLK_XTAL, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_VENCPLL, + CLK_XTAL +}; + +static const int intdir_parents[] = { + CLK_XTAL, + CLK_TOP_MMPLL, + CLK_TOP_SYSPLL_D2, + CLK_TOP_UNIVPLL_D2 +}; + +static const int asm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int ms_card_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL3_D8, + CLK_TOP_SYSPLL4_D4 +}; + +static const int ethif_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_DMPLL, + CLK_TOP_DMPLL_D2 +}; + +static const int hdmirx_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D52 +}; + +static const int cmsys_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL3_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL1_D8, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL +}; + +static const int clk_8bdac_parents[] = { + CLK_TOP_32K_INTERNAL, + CLK_TOP_8BDAC, + CLK_XTAL, + CLK_XTAL +}; + +static const int aud2dvd_parents[] = { + CLK_TOP_AUD_48K_TIMING, + CLK_TOP_AUD_44K_TIMING +}; + +static const int padmclk_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D26, + CLK_TOP_UNIVPLL_D52, + CLK_TOP_UNIVPLL_D108, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIVPLL2_D32 +}; + +static const int aud_mux_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL_98M, + CLK_TOP_AUD2PLL_90M, + CLK_TOP_HADDS2PLL_98M, + CLK_TOP_AUD_EXTCK1_DIV, + CLK_TOP_AUD_EXTCK2_DIV +}; + +static const int aud_src_parents[] = { + CLK_TOP_AUD_MUX1_SEL, + CLK_TOP_AUD_MUX2_SEL +}; + +static const struct mtk_composite top_muxes[] = { + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, + CLK_DOMAIN_SCPSYS), + + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), + MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, + CLK_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), + + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), + + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), + MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), + + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), + + MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), + MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), + MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), + + MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), + MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), + MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), + + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), + MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), + MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), + + MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), + + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), + MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), + MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, + CLK_DOMAIN_SCPSYS), + + MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), + MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), + MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), + + MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), + MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), + MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), + MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), + + MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), + + MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), + MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), + MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), + + MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), + MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), + MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), + MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), + MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), + MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), +}; + +/* infracfg */ +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +#define GATE_INFRA(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_cgs[] = { + GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0), + GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), + GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), + GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), + GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5), + GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), + GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), + GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13), + GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14), + GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15), + GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16), + GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18), + GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19), + GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22), + GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23), + GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24), +}; + +/* pericfg */ +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x10, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = 0xC, + .clr_ofs = 0x14, + .sta_ofs = 0x1C, +}; + +#define GATE_PERI0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_PERI1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate peri_cgs[] = { + GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0), + GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1), + GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2), + GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3), + GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4), + GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5), + GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6), + GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7), + GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8), + GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9), + GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10), + GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11), + GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12), + GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13), + GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14), + GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15), + GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16), + GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17), + GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18), + GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19), + GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21), + GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22), + GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23), + GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), + GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), + GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), + GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27), + GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), + GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), + + GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), + GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1), + GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2), + GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3), + GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4), + GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5), + GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6), + GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7), + GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8), + GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9), + GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10), + GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11), +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _parent, _shift, _flag) { \ + .id = _id, \ + .parent = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ + } + +#define GATE_ETH0(_id, _parent, _shift) \ + GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) + +#define GATE_ETH1(_id, _parent, _shift) \ + GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5), + GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6), + GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7), + GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8), + GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11), + GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14), + GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17), + GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29), +}; + +static const struct mtk_clk_tree mt7623_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_SYSPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt7623_mcucfg_probe(struct udevice *dev) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENOENT; + + clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, + AXI_DIV_SEL(0x12)); + + return 0; +} + +static int mt7623_apmixedsys_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = mtk_common_clk_init(dev, &mt7623_clk_tree); + if (ret) + return ret; + + /* reduce clock square disable time */ + writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0); + /* extend control timing to 1us */ + writel(0x888, priv->base + MT7623_PLL_ISO_CON0); + + return 0; +} + +static int mt7623_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7623_clk_tree); +} + +static int mt7623_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs); +} + +static int mt7623_pericfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs); +} + +static int mt7623_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs); +} + +static const struct udevice_id mt7623_apmixed_compat[] = { + { .compatible = "mediatek,mt7623-apmixedsys" }, + { } +}; + +static const struct udevice_id mt7623_topckgen_compat[] = { + { .compatible = "mediatek,mt7623-topckgen" }, + { } +}; + +static const struct udevice_id mt7623_infracfg_compat[] = { + { .compatible = "mediatek,mt7623-infracfg", }, + { } +}; + +static const struct udevice_id mt7623_pericfg_compat[] = { + { .compatible = "mediatek,mt7623-pericfg", }, + { } +}; + +static const struct udevice_id mt7623_ethsys_compat[] = { + { .compatible = "mediatek,mt7623-ethsys" }, + { } +}; + +static const struct udevice_id mt7623_mcucfg_compat[] = { + { .compatible = "mediatek,mt7623-mcucfg" }, + { } +}; + +U_BOOT_DRIVER(mtk_mcucfg) = { + .name = "mt7623-mcucfg", + .id = UCLASS_SYSCON, + .of_match = mt7623_mcucfg_compat, + .probe = mt7623_mcucfg_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7623-clock-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt7623_apmixed_compat, + .probe = mt7623_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7623-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7623_topckgen_compat, + .probe = mt7623_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7623-infracfg", + .id = UCLASS_CLK, + .of_match = mt7623_infracfg_compat, + .probe = mt7623_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_pericfg) = { + .name = "mt7623-pericfg", + .id = UCLASS_CLK, + .of_match = mt7623_pericfg_compat, + .probe = mt7623_pericfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7623-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7623_ethsys_compat, + .probe = mt7623_ethsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c new file mode 100644 index 0000000000..2601b6cf30 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" + +#define MT7629_CLKSQ_STB_CON0 0x20 +#define MT7629_PLL_ISO_CON0 0x2c +#define MT7629_PLL_FMAX (2500UL * MHZ) +#define MT7629_CON0_RST_BAR BIT(24) + +#define MCU_AXI_DIV 0x640 +#define AXI_DIV_MSK GENMASK(4, 0) +#define AXI_DIV_SEL(x) (x) + +#define MCU_BUS_MUX 0x7c0 +#define MCU_BUS_MSK GENMASK(10, 9) +#define MCU_BUS_SEL(x) ((x) << 9) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT7629_CON0_RST_BAR, \ + .fmax = MT7629_PLL_FMAX, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, + 21, 0x204, 24, 0x204, 0), + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + 21, 0x214, 24, 0x214, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + 7, 0x224, 24, 0x224, 14), + PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, + 21, 0x300, 1, 0x304, 0), + PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, + 21, 0x314, 1, 0x318, 0), + PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, + 21, 0x358, 1, 0x35c, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), + FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), + FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), + FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), + FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), + FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), + FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), + FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), + FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), + FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), + FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), + FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), + FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), + FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), + FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), + FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), + FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), + FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1), + FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1), + FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1), + FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1), + FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1), + FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1), + FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4), + FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1), + FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1), + FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1), + FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1), + FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), +}; + +static const int axi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL_D7, + CLK_TOP_DMPLL +}; + +static const int mem_parents[] = { + CLK_XTAL, + CLK_TOP_DMPLL +}; + +static const int ddrphycfg_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8 +}; + +static const int eth_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_SGMIIPLL_D2, + CLK_TOP_UNIVPLL_D7, + CLK_TOP_DMPLL +}; + +static const int pwm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int f10m_ref_parents[] = { + CLK_XTAL, + CLK_TOP_SGMIIPLL_D2 +}; + +static const int nfi_infra_parents[] = { + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL_D7 +}; + +static const int flash_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D80_D4, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int uart_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi0_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int spi1_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int msdc30_0_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIV48M +}; + +static const int msdc30_1_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIV48M, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int ap2wbmcu_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIV48M, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int audio_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL1_D16 +}; + +static const int aud_intbus_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_DMPLL_D4 +}; + +static const int pmicspi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_UNIVPLL3_D4, + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_DMPLL_D8 +}; + +static const int scp_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int atb_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int hif_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + -1, + CLK_TOP_UNIVPLL_D7 +}; + +static const int sata_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int usb20_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8 +}; + +static const int aud1_parents[] = { + CLK_XTAL +}; + +static const int irrx_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL4_D16 +}; + +static const int crypto_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_SYSPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D2 +}; + +static const int gpt10m_parents[] = { + CLK_XTAL, + CLK_TOP_CLKXTAL_D4 +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), + + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), + + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, + CLK_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), + + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), + + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), +}; + +/* infracfg */ +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +#define GATE_INFRA(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_cgs[] = { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0), + GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2), + GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4), + GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18), + GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19), +}; + +/* pericfg */ +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x10, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = 0xC, + .clr_ofs = 0x14, + .sta_ofs = 0x1C, +}; + +#define GATE_PERI0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_PERI1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate peri_cgs[] = { + GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2), + GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3), + GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4), + GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5), + GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6), + GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7), + GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8), + GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9), + GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12), + GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14), + GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17), + GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18), + GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19), + GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20), + GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22), + GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23), + GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28), + GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29), + GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30), + GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31), + GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1), +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _parent, _shift, _flag) { \ + .id = _id, \ + .parent = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ + } + +#define GATE_ETH0(_id, _parent, _shift) \ + GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) + +#define GATE_ETH1(_id, _parent, _shift) \ + GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6), + GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), + GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), + GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), + GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16), +}; + +static const struct mtk_gate_regs sgmii_cg_regs = { + .set_ofs = 0xE4, + .clr_ofs = 0xE4, + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate sgmii_cgs[] = { + GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2), + GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), + GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), +}; + +static const struct mtk_clk_tree mt7629_clk_tree = { + .xtal_rate = 40 * MHZ, + .xtal2_rate = 20 * MHZ, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt7629_mcucfg_probe(struct udevice *dev) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENOENT; + + clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, + AXI_DIV_SEL(0x12)); + clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, + MCU_BUS_SEL(0x1)); + + return 0; +} + +static int mt7629_apmixedsys_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = mtk_common_clk_init(dev, &mt7629_clk_tree); + if (ret) + return ret; + + /* reduce clock square disable time */ + writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0); + /* extend pwr/iso control timing to 1us */ + writel(0x80008, priv->base + MT7629_PLL_ISO_CON0); + + return 0; +} + +static int mt7629_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7629_clk_tree); +} + +static int mt7629_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs); +} + +static int mt7629_pericfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs); +} + +static int mt7629_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs); +} + +static int mt7629_sgmiisys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); +} + +static const struct udevice_id mt7629_apmixed_compat[] = { + { .compatible = "mediatek,mt7629-apmixedsys" }, + { } +}; + +static const struct udevice_id mt7629_topckgen_compat[] = { + { .compatible = "mediatek,mt7629-topckgen" }, + { } +}; + +static const struct udevice_id mt7629_infracfg_compat[] = { + { .compatible = "mediatek,mt7629-infracfg", }, + { } +}; + +static const struct udevice_id mt7629_pericfg_compat[] = { + { .compatible = "mediatek,mt7629-pericfg", }, + { } +}; + +static const struct udevice_id mt7629_ethsys_compat[] = { + { .compatible = "mediatek,mt7629-ethsys", }, + { } +}; + +static const struct udevice_id mt7629_sgmiisys_compat[] = { + { .compatible = "mediatek,mt7629-sgmiisys", }, + { } +}; + +static const struct udevice_id mt7629_mcucfg_compat[] = { + { .compatible = "mediatek,mt7629-mcucfg" }, + { } +}; + +U_BOOT_DRIVER(mtk_mcucfg) = { + .name = "mt7629-mcucfg", + .id = UCLASS_SYSCON, + .of_match = mt7629_mcucfg_compat, + .probe = mt7629_mcucfg_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7629-clock-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt7629_apmixed_compat, + .probe = mt7629_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7629-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7629_topckgen_compat, + .probe = mt7629_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7629-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7629_infracfg_compat, + .probe = mt7629_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_pericfg) = { + .name = "mt7629-clock-pericfg", + .id = UCLASS_CLK, + .of_match = mt7629_pericfg_compat, + .probe = mt7629_pericfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7629-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7629_ethsys_compat, + .probe = mt7629_ethsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +U_BOOT_DRIVER(mtk_clk_sgmiisys) = { + .name = "mt7629-clock-sgmiisys", + .id = UCLASS_CLK, + .of_match = mt7629_sgmiisys_compat, + .probe = mt7629_sgmiisys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c new file mode 100644 index 0000000000..870b14ed8b --- /dev/null +++ b/drivers/clk/mediatek/clk-mtk.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek common clock driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include + +#include "clk-mtk.h" + +#define REG_CON0 0 +#define REG_CON1 4 + +#define CON0_BASE_EN BIT(0) +#define CON0_PWR_ON BIT(0) +#define CON0_ISO_EN BIT(1) +#define CON1_PCW_CHG BIT(31) + +#define POSTDIV_MASK 0x7 +#define INTEGER_BITS 7 + +/* scpsys clock off control */ +#define CLK_SCP_CFG0 0x200 +#define CLK_SCP_CFG1 0x204 +#define SCP_ARMCK_OFF_EN GENMASK(9, 0) +#define SCP_AXICK_DCM_DIS_EN BIT(0) +#define SCP_AXICK_26M_SEL_EN BIT(4) + +/* shared functions */ + +/* + * In case the rate change propagation to parent clocks is undesirable, + * this function is recursively called to find the parent to calculate + * the accurate frequency. + */ +static int mtk_clk_find_parent_rate(struct clk *clk, int id, + const struct driver *drv) +{ + struct clk parent = { .id = id, }; + + if (drv) { + struct udevice *dev; + + if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev)) + return -ENODEV; + + parent.dev = dev; + } else { + parent.dev = clk->dev; + } + + return clk_get_rate(&parent); +} + +static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, + const struct mtk_composite *mux) +{ + u32 val, index = 0; + + while (mux->parent[index] != parent) + if (++index == mux->num_parents) + return -EINVAL; + + /* switch mux to a select parent */ + val = readl(base + mux->mux_reg); + val &= ~(mux->mux_mask << mux->mux_shift); + + val |= index << mux->mux_shift; + writel(val, base + mux->mux_reg); + + return 0; +} + +/* apmixedsys functions */ + +static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, + u32 fin, u32 pcw, int postdiv) +{ + int pcwbits = pll->pcwbits; + int pcwfbits; + u64 vco; + u8 c = 0; + + /* The fractional part of the PLL divider. */ + pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + + vco = (u64)fin * pcw; + + if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) + c = 1; + + vco >>= pcwfbits; + + if (c) + vco++; + + return ((unsigned long)vco + postdiv - 1) / postdiv; +} + +/** + * MediaTek PLLs are configured through their pcw value. The pcw value + * describes a divider in the PLL feedback loop which consists of 7 bits + * for the integer part and the remaining bits (if present) for the + * fractional part. Also they have a 3 bit power-of-two post divider. + */ +static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + u32 val; + + /* set postdiv */ + val = readl(priv->base + pll->pd_reg); + val &= ~(POSTDIV_MASK << pll->pd_shift); + val |= (ffs(postdiv) - 1) << pll->pd_shift; + + /* postdiv and pcw need to set at the same time if on same register */ + if (pll->pd_reg != pll->pcw_reg) { + writel(val, priv->base + pll->pd_reg); + val = readl(priv->base + pll->pcw_reg); + } + + /* set pcw */ + val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); + val |= pcw << pll->pcw_shift; + val &= ~CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + + val |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + + udelay(20); +} + +/** + * mtk_pll_calc_values - calculate good values for a given input frequency. + * @clk: The clk + * @pcw: The pcw value (output) + * @postdiv: The post divider (output) + * @freq: The desired target frequency + */ +static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, + u32 freq) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + unsigned long fmin = 1000 * MHZ; + u64 _pcw; + u32 val; + + if (freq > pll->fmax) + freq = pll->fmax; + + for (val = 0; val < 5; val++) { + *postdiv = 1 << val; + if ((u64)freq * *postdiv >= fmin) + break; + } + + /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ + _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS); + do_div(_pcw, priv->tree->xtal2_rate); + + *pcw = (u32)_pcw; +} + +static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) +{ + u32 pcw = 0; + u32 postdiv; + + mtk_pll_calc_values(clk, &pcw, &postdiv, rate); + mtk_pll_set_rate_regs(clk, pcw, postdiv); + + return 0; +} + +static ulong mtk_apmixedsys_get_rate(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + u32 postdiv; + u32 pcw; + + postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & + POSTDIV_MASK; + postdiv = 1 << postdiv; + + pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; + pcw &= GENMASK(pll->pcwbits - 1, 0); + + return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate, + pcw, postdiv); +} + +static int mtk_apmixedsys_enable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + u32 r; + + r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON; + writel(r, priv->base + pll->pwr_reg); + udelay(1); + + r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN; + writel(r, priv->base + pll->pwr_reg); + udelay(1); + + r = readl(priv->base + pll->reg + REG_CON0); + r |= pll->en_mask; + writel(r, priv->base + pll->reg + REG_CON0); + + udelay(20); + + if (pll->flags & HAVE_RST_BAR) { + r = readl(priv->base + pll->reg + REG_CON0); + r |= pll->rst_bar_mask; + writel(r, priv->base + pll->reg + REG_CON0); + } + + return 0; +} + +static int mtk_apmixedsys_disable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; + u32 r; + + if (pll->flags & HAVE_RST_BAR) { + r = readl(priv->base + pll->reg + REG_CON0); + r &= ~pll->rst_bar_mask; + writel(r, priv->base + pll->reg + REG_CON0); + } + + r = readl(priv->base + pll->reg + REG_CON0); + r &= ~CON0_BASE_EN; + writel(r, priv->base + pll->reg + REG_CON0); + + r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN; + writel(r, priv->base + pll->pwr_reg); + + r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON; + writel(r, priv->base + pll->pwr_reg); + + return 0; +} + +/* topckgen functions */ + +static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, + ulong parent_rate) +{ + u64 rate = parent_rate * fdiv->mult; + + do_div(rate, fdiv->div); + + return rate; +} + +static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; + ulong rate; + + switch (fdiv->flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + rate = mtk_clk_find_parent_rate(clk, fdiv->parent, + DM_GET_DRIVER(mtk_clk_apmixedsys)); + break; + case CLK_PARENT_TOPCKGEN: + rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); + break; + + default: + rate = priv->tree->xtal_rate; + } + + return mtk_factor_recalc_rate(fdiv, rate); +} + +static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + u32 index; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + + if (mux->parent[index]) + return mtk_clk_find_parent_rate(clk, mux->parent[index], + NULL); + + return priv->tree->xtal_rate; +} + +static ulong mtk_topckgen_get_rate(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->tree->fdivs_offs) + return priv->tree->fclks[clk->id].rate; + else if (clk->id < priv->tree->muxes_offs) + return mtk_topckgen_get_factor_rate(clk, clk->id - + priv->tree->fdivs_offs); + else + return mtk_topckgen_get_mux_rate(clk, clk->id - + priv->tree->muxes_offs); +} + +static int mtk_topckgen_enable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux; + u32 val; + + if (clk->id < priv->tree->muxes_offs) + return 0; + + mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; + if (mux->gate_shift < 0) + return 0; + + /* enable clock gate */ + val = readl(priv->base + mux->gate_reg); + val &= ~BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + + if (mux->flags & CLK_DOMAIN_SCPSYS) { + /* enable scpsys clock off control */ + writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0); + writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN, + priv->base + CLK_SCP_CFG1); + } + + return 0; +} + +static int mtk_topckgen_disable(struct clk *clk) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux; + u32 val; + + if (clk->id < priv->tree->muxes_offs) + return 0; + + mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; + if (mux->gate_shift < 0) + return 0; + + /* disable clock gate */ + val = readl(priv->base + mux->gate_reg); + val |= BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + + return 0; +} + +static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->tree->muxes_offs) + return 0; + + return mtk_clk_mux_set_parent(priv->base, parent->id, + &priv->tree->muxes[clk->id - priv->tree->muxes_offs]); +} + +/* CG functions */ + +static int mtk_clk_gate_enable(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate = &priv->gates[clk->id]; + u32 bit = BIT(gate->shift); + + switch (gate->flags & CLK_GATE_MASK) { + case CLK_GATE_SETCLR: + writel(bit, priv->base + gate->regs->clr_ofs); + break; + case CLK_GATE_NO_SETCLR_INV: + clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_clk_gate_disable(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate = &priv->gates[clk->id]; + u32 bit = BIT(gate->shift); + + switch (gate->flags & CLK_GATE_MASK) { + case CLK_GATE_SETCLR: + writel(bit, priv->base + gate->regs->set_ofs); + break; + case CLK_GATE_NO_SETCLR_INV: + clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static ulong mtk_clk_gate_get_rate(struct clk *clk) +{ + struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + const struct mtk_gate *gate = &priv->gates[clk->id]; + + switch (gate->flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + return mtk_clk_find_parent_rate(clk, gate->parent, + DM_GET_DRIVER(mtk_clk_apmixedsys)); + break; + case CLK_PARENT_TOPCKGEN: + return mtk_clk_find_parent_rate(clk, gate->parent, + DM_GET_DRIVER(mtk_clk_topckgen)); + break; + + default: + return priv->tree->xtal_rate; + } +} + +const struct clk_ops mtk_clk_apmixedsys_ops = { + .enable = mtk_apmixedsys_enable, + .disable = mtk_apmixedsys_disable, + .set_rate = mtk_apmixedsys_set_rate, + .get_rate = mtk_apmixedsys_get_rate, +}; + +const struct clk_ops mtk_clk_topckgen_ops = { + .enable = mtk_topckgen_enable, + .disable = mtk_topckgen_disable, + .get_rate = mtk_topckgen_get_rate, + .set_parent = mtk_topckgen_set_parent, +}; + +const struct clk_ops mtk_clk_gate_ops = { + .enable = mtk_clk_gate_enable, + .disable = mtk_clk_gate_disable, + .get_rate = mtk_clk_gate_get_rate, +}; + +int mtk_common_clk_init(struct udevice *dev, + const struct mtk_clk_tree *tree) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + priv->tree = tree; + + return 0; +} + +int mtk_common_clk_gate_init(struct udevice *dev, + const struct mtk_clk_tree *tree, + const struct mtk_gate *gates) +{ + struct mtk_cg_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + priv->tree = tree; + priv->gates = gates; + + return 0; +} diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h new file mode 100644 index 0000000000..74152ed9c6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mtk.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#ifndef __DRV_CLK_MTK_H +#define __DRV_CLK_MTK_H + +#define CLK_XTAL 0 +#define MHZ (1000 * 1000) + +#define HAVE_RST_BAR BIT(0) +#define CLK_DOMAIN_SCPSYS BIT(0) + +#define CLK_GATE_SETCLR BIT(0) +#define CLK_GATE_SETCLR_INV BIT(1) +#define CLK_GATE_NO_SETCLR BIT(2) +#define CLK_GATE_NO_SETCLR_INV BIT(3) +#define CLK_GATE_MASK GENMASK(3, 0) + +#define CLK_PARENT_APMIXED BIT(4) +#define CLK_PARENT_TOPCKGEN BIT(5) +#define CLK_PARENT_MASK GENMASK(5, 4) + +/* struct mtk_pll_data - hardware-specific PLLs data */ +struct mtk_pll_data { + const int id; + u32 reg; + u32 pwr_reg; + u32 en_mask; + u32 pd_reg; + int pd_shift; + u32 flags; + u32 rst_bar_mask; + u64 fmax; + int pcwbits; + u32 pcw_reg; + int pcw_shift; +}; + +/** + * struct mtk_fixed_clk - fixed clocks + * + * @id: index of clocks + * @parent: index of parnet clocks + * @rate: fixed rate + */ +struct mtk_fixed_clk { + const int id; + const int parent; + unsigned long rate; +}; + +#define FIXED_CLK(_id, _parent, _rate) { \ + .id = _id, \ + .parent = _parent, \ + .rate = _rate, \ + } + +/** + * struct mtk_fixed_factor - fixed multiplier and divider clocks + * + * @id: index of clocks + * @parent: index of parnet clocks + * @mult: multiplier + * @div: divider + * @flag: hardware-specific flags + */ +struct mtk_fixed_factor { + const int id; + const int parent; + u32 mult; + u32 div; + u32 flags; +}; + +#define FACTOR(_id, _parent, _mult, _div, _flags) { \ + .id = _id, \ + .parent = _parent, \ + .mult = _mult, \ + .div = _div, \ + .flags = _flags, \ + } + +/** + * struct mtk_composite - aggregate clock of mux, divider and gate clocks + * + * @id: index of clocks + * @parent: index of parnet clocks + * @mux_reg: hardware-specific mux register + * @gate_reg: hardware-specific gate register + * @mux_mask: mask to the mux bit field + * @mux_shift: shift to the mux bit field + * @gate_shift: shift to the gate bit field + * @num_parents: number of parent clocks + * @flags: hardware-specific flags + */ +struct mtk_composite { + const int id; + const int *parent; + u32 mux_reg; + u32 gate_reg; + u32 mux_mask; + signed char mux_shift; + signed char gate_shift; + signed char num_parents; + u16 flags; +}; + +#define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ + _flags) { \ + .id = _id, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _reg, \ + .gate_shift = _gate, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = _flags, \ + } + +#define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ + MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) + +#define MUX(_id, _parents, _reg, _shift, _width) { \ + .id = _id, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = 0, \ + } + +struct mtk_gate_regs { + u32 sta_ofs; + u32 clr_ofs; + u32 set_ofs; +}; + +/** + * struct mtk_gate - gate clocks + * + * @id: index of gate clocks + * @parent: index of parnet clocks + * @regs: hardware-specific mux register + * @shift: shift to the gate bit field + * @flags: hardware-specific flags + */ +struct mtk_gate { + const int id; + const int parent; + const struct mtk_gate_regs *regs; + int shift; + u32 flags; +}; + +/* struct mtk_clk_tree - clock tree */ +struct mtk_clk_tree { + unsigned long xtal_rate; + unsigned long xtal2_rate; + const int fdivs_offs; + const int muxes_offs; + const struct mtk_pll_data *plls; + const struct mtk_fixed_clk *fclks; + const struct mtk_fixed_factor *fdivs; + const struct mtk_composite *muxes; +}; + +struct mtk_clk_priv { + void __iomem *base; + const struct mtk_clk_tree *tree; +}; + +struct mtk_cg_priv { + void __iomem *base; + const struct mtk_clk_tree *tree; + const struct mtk_gate *gates; +}; + +extern const struct clk_ops mtk_clk_apmixedsys_ops; +extern const struct clk_ops mtk_clk_topckgen_ops; +extern const struct clk_ops mtk_clk_gate_ops; + +int mtk_common_clk_init(struct udevice *dev, + const struct mtk_clk_tree *tree); +int mtk_common_clk_gate_init(struct udevice *dev, + const struct mtk_clk_tree *tree, + const struct mtk_gate *gates); + +#endif /* __DRV_CLK_MTK_H */ diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c index 2b39bb99af..a7c15d2812 100644 --- a/drivers/clk/owl/clk_s900.c +++ b/drivers/clk/owl/clk_s900.c @@ -134,5 +134,4 @@ U_BOOT_DRIVER(clk_owl) = { .ops = &owl_clk_ops, .priv_auto_alloc_size = sizeof(struct owl_clk_priv), .probe = owl_clk_probe, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 99698b1f46..0529fc8763 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -107,7 +107,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, return renesas_clk_get_parent(clk, info, parent); } -static int gen3_clk_setup_sdif_div(struct clk *clk) +static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct cpg_mssr_info *info = priv->info; @@ -133,7 +133,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); - writel(1, priv->base + core->offset); + writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); return 0; } @@ -141,10 +141,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) static int gen3_clk_enable(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); - int ret = gen3_clk_setup_sdif_div(clk); - - if (ret) - return ret; return renesas_clk_endisable(clk, priv->base, true); } @@ -328,7 +324,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) { /* Force correct SD-IF divider configuration if applicable */ - gen3_clk_setup_sdif_div(clk); + gen3_clk_setup_sdif_div(clk, rate); return gen3_clk_get_rate64(clk); } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 26faf88116..198914b067 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -61,6 +61,11 @@ static const struct pll_div *apll_l_cfgs[] = { [APLL_L_600_MHZ] = &apll_l_600_cfg, }; +static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div *apll_b_cfgs[] = { + [APLL_B_600_MHZ] = &apll_b_600_cfg, +}; + enum { /* PLL_CON0 */ PLL_FBDIV_MASK = 0xfff, @@ -128,6 +133,24 @@ enum { ATCLK_CORE_L_DIV_SHIFT = 0, ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, + /* CLKSEL_CON2 */ + ACLKM_CORE_B_DIV_CON_SHIFT = 8, + ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT, + CLK_CORE_B_PLL_SEL_SHIFT = 6, + CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT, + CLK_CORE_B_PLL_SEL_ALPLL = 0x0, + CLK_CORE_B_PLL_SEL_ABPLL = 0x1, + CLK_CORE_B_PLL_SEL_DPLL = 0x10, + CLK_CORE_B_PLL_SEL_GPLL = 0x11, + CLK_CORE_B_DIV_MASK = 0x1f, + CLK_CORE_B_DIV_SHIFT = 0, + + /* CLKSEL_CON3 */ + PCLK_DBG_B_DIV_SHIFT = 0x8, + PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT, + ATCLK_CORE_B_DIV_SHIFT = 0, + ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT, + /* CLKSEL_CON14 */ PCLK_PERIHP_DIV_CON_SHIFT = 12, PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, @@ -395,25 +418,26 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -void rk3399_configure_cpu(struct rk3399_cru *cru, - enum apll_l_frequencies apll_l_freq) +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; + /* Setup cluster L */ rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); - aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; - assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && + aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ && aclkm_div < 0x1f); - pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; - assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && + pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ && pclk_dbg_div < 0x1f); - atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; - assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && + atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ && atclk_div < 0x1f); rk_clrsetreg(&cru->clksel_con[0], @@ -428,6 +452,42 @@ void rk3399_configure_cpu(struct rk3399_cru *cru, pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | atclk_div << ATCLK_CORE_L_DIV_SHIFT); } + +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq) +{ + u32 aclkm_div; + u32 pclk_dbg_div; + u32 atclk_div; + + /* Setup cluster B */ + rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]); + + aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ && + aclkm_div < 0x1f); + + pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ && + pclk_dbg_div < 0x1f); + + atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ && + atclk_div < 0x1f); + + rk_clrsetreg(&cru->clksel_con[2], + ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK | + CLK_CORE_B_DIV_MASK, + aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT | + CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT | + 0 << CLK_CORE_B_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[3], + PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK, + pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT | + atclk_div << ATCLK_CORE_B_DIV_SHIFT); +} + #define I2C_CLK_REG_MASK(bus) \ (I2C_DIV_CON_MASK << \ CLK_I2C ##bus## _DIV_CON_SHIFT | \ @@ -1026,7 +1086,8 @@ static void rkclk_init(struct rk3399_cru *cru) u32 hclk_div; u32 pclk_div; - rk3399_configure_cpu(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_l(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_b(cru, APLL_B_600_MHZ); /* * some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 1f9f534b28..914e2f4b21 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -17,6 +17,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + enum { VCO_MAX_HZ = 2400U * 1000000, VCO_MIN_HZ = 600 * 1000000, @@ -35,6 +37,9 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + /* use integer mode */ static inline int rv1108_pll_id(enum rk_clk_id clk_id) { @@ -57,6 +62,58 @@ static inline int rv1108_pll_id(enum rk_clk_id clk_id) return id; } +static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rv1108_pll_id(clk_id); + struct rv1108_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* + * When power on or changing PLL setting, + * we must force PLL into slow mode to ensure output stable clock. + */ + rk_clrsetreg(&pll->con3, WORK_MODE_MASK, + WORK_MODE_SLOW << WORK_MODE_SHIFT); + + /* use integer mode */ + rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); + /* Power down */ + rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); + + rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); + rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, + (div->postdiv1 << POSTDIV1_SHIFT | + div->postdiv2 << POSTDIV2_SHIFT | + div->refdiv << REFDIV_SHIFT)); + rk_clrsetreg(&pll->con2, FRACDIV_MASK, + (div->refdiv << REFDIV_SHIFT)); + + /* Power Up */ + rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); + + /* waiting for pll lock */ + while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT)) + udelay(1); + + /* + * set PLL into normal mode. + */ + rk_clrsetreg(&pll->con3, WORK_MODE_MASK, + WORK_MODE_NORMAL << WORK_MODE_SHIFT); + + return 0; +} + static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, enum rk_clk_id clk_id) { @@ -74,7 +131,7 @@ static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; - refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; + refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; } else { freq = OSC_HZ; @@ -154,6 +211,326 @@ static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) return rv1108_saradc_get_clk(cru); } +static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[28]); + div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT, + CLK_VIO_DIV_CON_WIDTH); + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[28], + ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK, + (src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) | + (VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT)); + + return rv1108_aclk_vio1_get_clk(cru); +} + +static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[28]); + div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT, + CLK_VIO_DIV_CON_WIDTH); + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[28], + ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK, + (src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) | + (VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT)); + + /*HCLK_VIO default div = 4*/ + rk_clrsetreg(&cru->clksel_con[29], + HCLK_VIO_CLK_DIV_MASK, + 3 << HCLK_VIO_CLK_DIV_SHIFT); + /*PCLK_VIO default div = 4*/ + rk_clrsetreg(&cru->clksel_con[29], + PCLK_VIO_CLK_DIV_MASK, + 3 << PCLK_VIO_CLK_DIV_SHIFT); + + return rv1108_aclk_vio0_get_clk(cru); +} + +static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[32]); + div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT, + DCLK_VOP_DIV_CON_WIDTH); + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; + assert(src_clk_div < 64); + + rk_clrsetreg(&cru->clksel_con[32], + DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK | + DCLK_VOP_SEL_SHIFT, + (src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) | + (DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) | + (DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT)); + + return rv1108_dclk_vop_get_clk(cru); +} + +static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + val = readl(&cru->clksel_con[2]); + div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT, + ACLK_BUS_DIV_CON_WIDTH); + + return DIV_TO_RATE(parent_rate, div); +} + +static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[2], + ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK, + (src_clk_div << ACLK_BUS_DIV_CON_SHIFT) | + (ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT)); + + return rv1108_aclk_bus_get_clk(cru); +} + +static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + val = readl(&cru->clksel_con[23]); + div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT, + PERI_DIV_CON_WIDTH); + + return DIV_TO_RATE(parent_rate, div); +} + +static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + val = readl(&cru->clksel_con[23]); + div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT, + PERI_DIV_CON_WIDTH); + + return DIV_TO_RATE(parent_rate, div); +} + +static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + val = readl(&cru->clksel_con[23]); + div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT, + PERI_DIV_CON_WIDTH); + + return DIV_TO_RATE(parent_rate, div); +} + +static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[23], + ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK, + (src_clk_div << ACLK_PERI_DIV_CON_SHIFT) | + (ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT)); + + return rv1108_aclk_peri_get_clk(cru); +} + +static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[23], + HCLK_PERI_DIV_CON_MASK, + (src_clk_div << HCLK_PERI_DIV_CON_SHIFT)); + + return rv1108_hclk_peri_get_clk(cru); +} + +static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + + src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; + assert(src_clk_div < 32); + + rk_clrsetreg(&cru->clksel_con[23], + PCLK_PERI_DIV_CON_MASK, + (src_clk_div << PCLK_PERI_DIV_CON_SHIFT)); + + return rv1108_pclk_peri_get_clk(cru); +} + +static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_I2C0_PMU: + con = readl(&cru->clksel_con[19]); + div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT, + I2C_DIV_CON_WIDTH); + break; + case SCLK_I2C1: + con = readl(&cru->clksel_con[19]); + div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT, + I2C_DIV_CON_WIDTH); + break; + case SCLK_I2C2: + con = readl(&cru->clksel_con[20]); + div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT, + I2C_DIV_CON_WIDTH); + break; + case SCLK_I2C3: + con = readl(&cru->clksel_con[20]); + div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT, + I2C_DIV_CON_WIDTH); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case SCLK_I2C0_PMU: + rk_clrsetreg(&cru->clksel_con[19], + CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK, + (src_clk_div << CLK_I2C0_DIV_CON_SHIFT) | + (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT)); + break; + case SCLK_I2C1: + rk_clrsetreg(&cru->clksel_con[19], + CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK, + (src_clk_div << CLK_I2C1_DIV_CON_SHIFT) | + (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT)); + break; + case SCLK_I2C2: + rk_clrsetreg(&cru->clksel_con[20], + CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK, + (src_clk_div << CLK_I2C2_DIV_CON_SHIFT) | + (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT)); + break; + case SCLK_I2C3: + rk_clrsetreg(&cru->clksel_con[20], + CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK, + (src_clk_div << CLK_I2C3_DIV_CON_SHIFT) | + (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT)); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return rv1108_i2c_get_clk(cru, clk_id); +} + +static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru) +{ + u32 div, con; + ulong mmc_clk; + + con = readl(&cru->clksel_con[26]); + div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8); + + con = readl(&cru->clksel_con[25]); + + if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC) + mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2; + else + mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2; + + debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk); + return mmc_clk; +} + +static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate) +{ + int div; + u32 pll_rate; + + div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate); + + if (div < 127) { + debug("%s source gpll\n", __func__); + rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, + (EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT)); + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + } else { + debug("%s source 24m\n", __func__); + rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, + (EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT)); + pll_rate = OSC_HZ; + } + + div = DIV_ROUND_UP(pll_rate / 2, rate); + rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK, + ((div - 1) << EMMC_CLK_DIV_SHIFT)); + + debug("%s set_rate %ld div %d\n", __func__, rate, div); + + return DIV_TO_RATE(pll_rate, div); +} + static ulong rv1108_clk_get_rate(struct clk *clk) { struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); @@ -163,6 +540,29 @@ static ulong rv1108_clk_get_rate(struct clk *clk) return rkclk_pll_get_rate(priv->cru, clk->id); case SCLK_SARADC: return rv1108_saradc_get_clk(priv->cru); + case ACLK_VIO0: + return rv1108_aclk_vio0_get_clk(priv->cru); + case ACLK_VIO1: + return rv1108_aclk_vio1_get_clk(priv->cru); + case DCLK_VOP: + return rv1108_dclk_vop_get_clk(priv->cru); + case ACLK_PRE: + return rv1108_aclk_bus_get_clk(priv->cru); + case ACLK_PERI: + return rv1108_aclk_peri_get_clk(priv->cru); + case HCLK_PERI: + return rv1108_hclk_peri_get_clk(priv->cru); + case PCLK_PERI: + return rv1108_pclk_peri_get_clk(priv->cru); + case SCLK_I2C0_PMU: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + return rv1108_i2c_get_clk(priv->cru, clk->id); + case HCLK_EMMC: + case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: + return rv1108_mmc_get_clk(priv->cru); default: return -ENOENT; } @@ -183,6 +583,37 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: new_rate = rv1108_saradc_set_clk(priv->cru, rate); break; + case ACLK_VIO0: + new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate); + break; + case ACLK_VIO1: + new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate); + break; + case DCLK_VOP: + new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate); + break; + case ACLK_PRE: + new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate); + break; + case ACLK_PERI: + new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate); + break; + case HCLK_PERI: + new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate); + break; + case PCLK_PERI: + new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate); + break; + case SCLK_I2C0_PMU: + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate); + break; + case HCLK_EMMC: + case SCLK_EMMC: + new_rate = rv1108_mmc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } @@ -197,14 +628,34 @@ static const struct clk_ops rv1108_clk_ops = { static void rkclk_init(struct rv1108_cru *cru) { - unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); - unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); - unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); + unsigned int apll, dpll, gpll; + unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri; + + aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2); + aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2); + hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2); + pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2); + rv1108_aclk_vio0_set_clk(cru, 297000000); + rv1108_aclk_vio1_set_clk(cru, 297000000); + + /* configure apll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ); + aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ); + hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ); + pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ); + + apll = rkclk_pll_get_rate(cru, CLK_ARM); + dpll = rkclk_pll_get_rate(cru, CLK_DDR); + gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, 0 << MAC_CLK_DIV_SHIFT); printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); + printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n", + aclk_bus, aclk_peri, hclk_peri, pclk_peri); } static int rv1108_clk_ofdata_to_platdata(struct udevice *dev) @@ -228,8 +679,9 @@ static int rv1108_clk_probe(struct udevice *dev) static int rv1108_clk_bind(struct udevice *dev) { int ret; - struct udevice *sys_child; + struct udevice *sys_child, *sf_child; struct sysreset_reg *priv; + struct softreset_reg *sf_priv; /* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", @@ -251,6 +703,17 @@ static int rv1108_clk_bind(struct udevice *dev) if (ret) debug("Warning: software reset driver bind faile\n"); #endif + ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", + dev_ofnode(dev), &sf_child); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + } else { + sf_priv = malloc(sizeof(struct softreset_reg)); + sf_priv->sf_reset_offset = offsetof(struct rv1108_cru, + softrst_con[0]); + sf_priv->sf_reset_num = 13; + sf_child->priv = sf_priv; + } return 0; } @@ -265,8 +728,8 @@ U_BOOT_DRIVER(clk_rv1108) = { .id = UCLASS_CLK, .of_match = rv1108_clk_ids, .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), - .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata, .ops = &rv1108_clk_ops, .bind = rv1108_clk_bind, + .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata, .probe = rv1108_clk_probe, }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 9e087b6bd2..487b43ebda 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -6,13 +6,12 @@ #include "clk-uniphier.h" -/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */ #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ - UNIPHIER_CLK_RATE(128, 200000000), \ + UNIPHIER_CLK_RATE(128, 50000000), \ UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { @@ -20,6 +19,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ @@ -36,6 +36,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ @@ -48,6 +49,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_RATE(3, 200000000), UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index e8ba20ca82..046b87a333 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -57,13 +57,21 @@ config DM_DEVICE_REMOVE default y help We can save some code space by dropping support for removing a - device. This is not normally required in SPL, so by default this - option is disabled for SPL. + device. Note that this may have undesirable results in the USB subsystem as it causes unplugged devices to linger around in the dm-tree, and it causes USB host controllers to not be stopped when booting the OS. +config SPL_DM_DEVICE_REMOVE + bool "Support device removal in SPL" + depends on SPL_DM + default n + help + We can save some code space by dropping support for removing a + device. This is not normally required in SPL, so by default this + option is disabled for SPL. + config DM_STDIO bool "Support stdio registration" depends on DM diff --git a/drivers/core/device.c b/drivers/core/device.c index 5176aa3f86..0d15e5062b 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -70,7 +70,8 @@ static int device_bind_common(struct udevice *parent, const struct driver *drv, dev->seq = -1; dev->req_seq = -1; - if (CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_SEQ_ALIAS)) { + if (CONFIG_IS_ENABLED(DM_SEQ_ALIAS) && + (uc->uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS)) { /* * Some devices, such as a SPI bus, I2C bus and serial ports * are numbered using aliases. @@ -78,10 +79,11 @@ static int device_bind_common(struct udevice *parent, const struct driver *drv, * This is just a 'requested' sequence, and will be * resolved (and ->seq updated) when the device is probed. */ - if (uc->uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS) { - if (uc->uc_drv->name && ofnode_valid(node)) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (uc->uc_drv->name && ofnode_valid(node)) dev_read_alias_seq(dev, &dev->req_seq); - } + } else { + dev->req_seq = uclass_find_next_free_req_seq(drv->id); } } @@ -699,6 +701,40 @@ int device_find_first_inactive_child(struct udevice *parent, return -ENODEV; } +int device_find_first_child_by_uclass(struct udevice *parent, + enum uclass_id uclass_id, + struct udevice **devp) +{ + struct udevice *dev; + + *devp = NULL; + list_for_each_entry(dev, &parent->child_head, sibling_node) { + if (device_get_uclass_id(dev) == uclass_id) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + +int device_find_child_by_name(struct udevice *parent, const char *name, + struct udevice **devp) +{ + struct udevice *dev; + + *devp = NULL; + + list_for_each_entry(dev, &parent->child_head, sibling_node) { + if (!strcmp(dev->name, name)) { + *devp = dev; + return 0; + } + } + + return -ENODEV; +} + struct udevice *dev_get_parent(const struct udevice *child) { return child->parent; @@ -834,5 +870,5 @@ int dev_enable_by_path(const char *path) if (ret) return ret; - return lists_bind_fdt(parent, node, NULL); + return lists_bind_fdt(parent, node, NULL, false); } diff --git a/drivers/core/dump.c b/drivers/core/dump.c index d7cdb1475d..04217cbde8 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -15,8 +15,8 @@ static void show_devices(struct udevice *dev, int depth, int last_flag) int i, is_last; struct udevice *child; - /* print the first 11 characters to not break the tree-format. */ - printf(" %-10.10s %d [ %c ] %-10.10s ", dev->uclass->uc_drv->name, + /* print the first 20 characters to not break the tree-format. */ + printf(" %-10.10s %d [ %c ] %-20.20s ", dev->uclass->uc_drv->name, dev_get_uclass_index(dev, NULL), dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name); @@ -49,8 +49,8 @@ void dm_dump_all(void) root = dm_root(); if (root) { - printf(" Class index Probed Driver Name\n"); - printf("-----------------------------------------\n"); + printf(" Class index Probed Driver Name\n"); + printf("-----------------------------------------------------------\n"); show_devices(root, -1, 0); } } @@ -89,7 +89,7 @@ void dm_dump_uclass(void) printf("uclass %d: %s\n", id, uc->uc_drv->name); if (list_empty(&uc->dev_head)) continue; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { dm_display_line(dev, i); i++; } diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index bfd9580050..e113f1dd39 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -146,6 +146,16 @@ void *devfdt_remap_addr_index(struct udevice *dev, int index) return map_physmem(addr, 0, MAP_NOCACHE); } +void *devfdt_remap_addr_name(struct udevice *dev, const char *name) +{ + fdt_addr_t addr = devfdt_get_addr_name(dev, name); + + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_physmem(addr, 0, MAP_NOCACHE); +} + void *devfdt_remap_addr(struct udevice *dev) { return devfdt_remap_addr_index(dev, 0); diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a1677269d8..a1f828463e 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -122,7 +122,8 @@ static int driver_check_compatible(const struct udevice_id *of_match, return -ENOENT; } -int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp) +int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, + bool pre_reloc_only) { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); @@ -171,6 +172,12 @@ int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp) if (entry == driver + n_ents) continue; + if (pre_reloc_only) { + if (!dm_ofnode_pre_reloc(node) && + !(entry->flags & DM_FLAG_PRE_RELOC)) + return 0; + } + pr_debug(" - found match at '%s'\n", entry->name); ret = device_bind_with_driver_data(parent, entry, name, id->data, node, &dev); diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index b7b7ad3a62..0e584c12dc 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -253,15 +253,15 @@ int ofnode_read_size(ofnode node, const char *propname) fdt_addr_t ofnode_get_addr_index(ofnode node, int index) { + int na, ns; + fdt_size_t size; + if (ofnode_is_np(node)) { const __be32 *prop_val; uint flags; - u64 size; - int na; - int ns; - prop_val = of_get_address(ofnode_to_np(node), index, &size, - &flags); + prop_val = of_get_address(ofnode_to_np(node), index, + (u64 *)&size, &flags); if (!prop_val) return FDT_ADDR_T_NONE; @@ -274,8 +274,11 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index) return of_read_number(prop_val, na); } } else { - return fdt_get_base_address(gd->fdt_blob, - ofnode_to_offset(node)); + na = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + return fdtdec_get_addr_size_fixed(gd->fdt_blob, + ofnode_to_offset(node), "reg", + index, na, ns, &size, true); } return FDT_ADDR_T_NONE; @@ -831,8 +834,10 @@ int ofnode_write_prop(ofnode node, const char *propname, int len, return -ENOMEM; new->name = strdup(propname); - if (!new->name) + if (!new->name) { + free(new); return -ENOMEM; + } new->value = (void *)value; new->length = len; diff --git a/drivers/core/read.c b/drivers/core/read.c index 96766c7876..3c46b3674e 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -21,6 +21,29 @@ int dev_read_u32_default(struct udevice *dev, const char *propname, int def) return ofnode_read_u32_default(dev_ofnode(dev), propname, def); } +int dev_read_s32(struct udevice *dev, const char *propname, s32 *outp) +{ + return ofnode_read_u32(dev_ofnode(dev), propname, (u32 *)outp); +} + +int dev_read_s32_default(struct udevice *dev, const char *propname, int def) +{ + return ofnode_read_u32_default(dev_ofnode(dev), propname, def); +} + +int dev_read_u32u(struct udevice *dev, const char *propname, uint *outp) +{ + u32 val; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), propname, &val); + if (ret) + return ret; + *outp = val; + + return 0; +} + const char *dev_read_string(struct udevice *dev, const char *propname) { return ofnode_read_string(dev_ofnode(dev), propname); @@ -69,6 +92,26 @@ void *dev_remap_addr_index(struct udevice *dev, int index) return map_physmem(addr, 0, MAP_NOCACHE); } +fdt_addr_t dev_read_addr_name(struct udevice *dev, const char *name) +{ + int index = dev_read_stringlist_search(dev, "reg-names", name); + + if (index < 0) + return FDT_ADDR_T_NONE; + else + return dev_read_addr_index(dev, index); +} + +void *dev_remap_addr_name(struct udevice *dev, const char *name) +{ + fdt_addr_t addr = dev_read_addr_name(dev, name); + + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_physmem(addr, 0, MAP_NOCACHE); +} + fdt_addr_t dev_read_addr(struct udevice *dev) { return dev_read_addr_index(dev, 0); diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 8e5c3bcf61..5ef0f71c8b 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -17,6 +17,12 @@ DECLARE_GLOBAL_DATA_PTR; +/** + * regmap_alloc() - Allocate a regmap with a given number of ranges. + * + * @count: Number of ranges to be allocated for the regmap. + * Return: A pointer to the newly allocated regmap, or NULL on error. + */ static struct regmap *regmap_alloc(int count) { struct regmap *map; @@ -50,6 +56,58 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, return 0; } #else +/** + * init_range() - Initialize a single range of a regmap + * @node: Device node that will use the map in question + * @range: Pointer to a regmap_range structure that will be initialized + * @addr_len: The length of the addr parts of the reg property + * @size_len: The length of the size parts of the reg property + * @index: The index of the range to initialize + * + * This function will read the necessary 'reg' information from the device tree + * (the 'addr' part, and the 'length' part), and initialize the range in + * quesion. + * + * Return: 0 if OK, -ve on error + */ +static int init_range(ofnode node, struct regmap_range *range, int addr_len, + int size_len, int index) +{ + fdt_size_t sz; + struct resource r; + + if (of_live_active()) { + int ret; + + ret = of_address_to_resource(ofnode_to_np(node), + index, &r); + if (ret) { + debug("%s: Could not read resource of range %d (ret = %d)\n", + ofnode_get_name(node), index, ret); + return ret; + } + + range->start = r.start; + range->size = r.end - r.start + 1; + } else { + int offset = ofnode_to_offset(node); + + range->start = fdtdec_get_addr_size_fixed(gd->fdt_blob, offset, + "reg", index, + addr_len, size_len, + &sz, true); + if (range->start == FDT_ADDR_T_NONE) { + debug("%s: Could not read start of range %d\n", + ofnode_get_name(node), index); + return -EINVAL; + } + + range->size = sz; + } + + return 0; +} + int regmap_init_mem(ofnode node, struct regmap **mapp) { struct regmap_range *range; @@ -58,19 +116,41 @@ int regmap_init_mem(ofnode node, struct regmap **mapp) int addr_len, size_len, both_len; int len; int index; - struct resource r; addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + if (addr_len < 0) { + debug("%s: Error while reading the addr length (ret = %d)\n", + ofnode_get_name(node), addr_len); + return addr_len; + } + size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + if (size_len < 0) { + debug("%s: Error while reading the size length: (ret = %d)\n", + ofnode_get_name(node), size_len); + return size_len; + } + both_len = addr_len + size_len; + if (!both_len) { + debug("%s: Both addr and size length are zero\n", + ofnode_get_name(node)); + return -EINVAL; + } len = ofnode_read_size(node, "reg"); - if (len < 0) + if (len < 0) { + debug("%s: Error while reading reg size (ret = %d)\n", + ofnode_get_name(node), len); return len; + } len /= sizeof(fdt32_t); count = len / both_len; - if (!count) + if (!count) { + debug("%s: Not enough data in reg property\n", + ofnode_get_name(node)); return -EINVAL; + } map = regmap_alloc(count); if (!map) @@ -78,19 +158,21 @@ int regmap_init_mem(ofnode node, struct regmap **mapp) for (range = map->ranges, index = 0; count > 0; count--, range++, index++) { - fdt_size_t sz; - if (of_live_active()) { - of_address_to_resource(ofnode_to_np(node), index, &r); - range->start = r.start; - range->size = r.end - r.start + 1; - } else { - range->start = fdtdec_get_addr_size_fixed(gd->fdt_blob, - ofnode_to_offset(node), "reg", index, - addr_len, size_len, &sz, true); - range->size = sz; - } + int ret = init_range(node, range, addr_len, size_len, index); + + if (ret) + return ret; } + if (ofnode_read_bool(node, "little-endian")) + map->endianness = REGMAP_LITTLE_ENDIAN; + else if (ofnode_read_bool(node, "big-endian")) + map->endianness = REGMAP_BIG_ENDIAN; + else if (ofnode_read_bool(node, "native-endian")) + map->endianness = REGMAP_NATIVE_ENDIAN; + else /* Default: native endianness */ + map->endianness = REGMAP_NATIVE_ENDIAN; + *mapp = map; return 0; @@ -115,24 +197,218 @@ int regmap_uninit(struct regmap *map) return 0; } -int regmap_read(struct regmap *map, uint offset, uint *valp) +static inline u8 __read_8(u8 *addr, enum regmap_endianness_t endianness) { - u32 *ptr = map_physmem(map->ranges[0].start + offset, 4, MAP_NOCACHE); + return readb(addr); +} - *valp = le32_to_cpu(readl(ptr)); +static inline u16 __read_16(u16 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le16(addr); + case REGMAP_BIG_ENDIAN: + return in_be16(addr); + case REGMAP_NATIVE_ENDIAN: + return readw(addr); + } + + return readw(addr); +} + +static inline u32 __read_32(u32 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le32(addr); + case REGMAP_BIG_ENDIAN: + return in_be32(addr); + case REGMAP_NATIVE_ENDIAN: + return readl(addr); + } + + return readl(addr); +} + +#if defined(in_le64) && defined(in_be64) && defined(readq) +static inline u64 __read_64(u64 *addr, enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_LITTLE_ENDIAN: + return in_le64(addr); + case REGMAP_BIG_ENDIAN: + return in_be64(addr); + case REGMAP_NATIVE_ENDIAN: + return readq(addr); + } + + return readq(addr); +} +#endif + +int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, + void *valp, size_t val_len) +{ + struct regmap_range *range; + void *ptr; + + if (range_num >= map->range_count) { + debug("%s: range index %d larger than range count\n", + __func__, range_num); + return -ERANGE; + } + range = &map->ranges[range_num]; + + ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE); + + if (offset + val_len > range->size) { + debug("%s: offset/size combination invalid\n", __func__); + return -ERANGE; + } + + switch (val_len) { + case REGMAP_SIZE_8: + *((u8 *)valp) = __read_8(ptr, map->endianness); + break; + case REGMAP_SIZE_16: + *((u16 *)valp) = __read_16(ptr, map->endianness); + break; + case REGMAP_SIZE_32: + *((u32 *)valp) = __read_32(ptr, map->endianness); + break; +#if defined(in_le64) && defined(in_be64) && defined(readq) + case REGMAP_SIZE_64: + *((u64 *)valp) = __read_64(ptr, map->endianness); + break; +#endif + default: + debug("%s: regmap size %zu unknown\n", __func__, val_len); + return -EINVAL; + } return 0; } -int regmap_write(struct regmap *map, uint offset, uint val) +int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len) { - u32 *ptr = map_physmem(map->ranges[0].start + offset, 4, MAP_NOCACHE); + return regmap_raw_read_range(map, 0, offset, valp, val_len); +} - writel(cpu_to_le32(val), ptr); +int regmap_read(struct regmap *map, uint offset, uint *valp) +{ + return regmap_raw_read(map, offset, valp, REGMAP_SIZE_32); +} + +static inline void __write_8(u8 *addr, const u8 *val, + enum regmap_endianness_t endianness) +{ + writeb(*val, addr); +} + +static inline void __write_16(u16 *addr, const u16 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writew(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le16(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be16(addr, *val); + break; + } +} + +static inline void __write_32(u32 *addr, const u32 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writel(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le32(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be32(addr, *val); + break; + } +} + +#if defined(out_le64) && defined(out_be64) && defined(writeq) +static inline void __write_64(u64 *addr, const u64 *val, + enum regmap_endianness_t endianness) +{ + switch (endianness) { + case REGMAP_NATIVE_ENDIAN: + writeq(*val, addr); + break; + case REGMAP_LITTLE_ENDIAN: + out_le64(addr, *val); + break; + case REGMAP_BIG_ENDIAN: + out_be64(addr, *val); + break; + } +} +#endif + +int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, + const void *val, size_t val_len) +{ + struct regmap_range *range; + void *ptr; + + if (range_num >= map->range_count) { + debug("%s: range index %d larger than range count\n", + __func__, range_num); + return -ERANGE; + } + range = &map->ranges[range_num]; + + ptr = map_physmem(range->start + offset, val_len, MAP_NOCACHE); + + if (offset + val_len > range->size) { + debug("%s: offset/size combination invalid\n", __func__); + return -ERANGE; + } + + switch (val_len) { + case REGMAP_SIZE_8: + __write_8(ptr, val, map->endianness); + break; + case REGMAP_SIZE_16: + __write_16(ptr, val, map->endianness); + break; + case REGMAP_SIZE_32: + __write_32(ptr, val, map->endianness); + break; +#if defined(out_le64) && defined(out_be64) && defined(writeq) + case REGMAP_SIZE_64: + __write_64(ptr, val, map->endianness); + break; +#endif + default: + debug("%s: regmap size %zu unknown\n", __func__, val_len); + return -EINVAL; + } return 0; } +int regmap_raw_write(struct regmap *map, uint offset, const void *val, + size_t val_len) +{ + return regmap_raw_write_range(map, 0, offset, val, val_len); +} + +int regmap_write(struct regmap *map, uint offset, uint val) +{ + return regmap_raw_write(map, offset, &val, REGMAP_SIZE_32); +} + int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val) { uint reg; diff --git a/drivers/core/root.c b/drivers/core/root.c index b54bf5bcdc..e6ec7faf37 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -187,6 +187,7 @@ int dm_uninit(void) { device_remove(dm_root(), DM_REMOVE_NORMAL); device_unbind(dm_root()); + gd->dm_root = NULL; return 0; } @@ -222,14 +223,22 @@ static int dm_scan_fdt_live(struct udevice *parent, int ret = 0, err; for (np = node_parent->child; np; np = np->sibling) { - if (pre_reloc_only && - !of_find_property(np, "u-boot,dm-pre-reloc", NULL)) + /* "chosen" node isn't a device itself but may contain some: */ + if (!strcmp(np->name, "chosen")) { + pr_debug("parsing subnodes of \"chosen\"\n"); + + err = dm_scan_fdt_live(parent, np, pre_reloc_only); + if (err && !ret) + ret = err; continue; + } + if (!of_device_is_available(np)) { pr_debug(" - ignoring disabled device\n"); continue; } - err = lists_bind_fdt(parent, np_to_ofnode(np), NULL); + err = lists_bind_fdt(parent, np_to_ofnode(np), NULL, + pre_reloc_only); if (err && !ret) { ret = err; debug("%s: ret=%d\n", np->name, ret); @@ -282,14 +291,12 @@ static int dm_scan_fdt_node(struct udevice *parent, const void *blob, continue; } - if (pre_reloc_only && - !dm_fdt_pre_reloc(blob, offset)) - continue; if (!fdtdec_get_is_enabled(blob, offset)) { pr_debug(" - ignoring disabled device\n"); continue; } - err = lists_bind_fdt(parent, offset_to_ofnode(offset), NULL); + err = lists_bind_fdt(parent, offset_to_ofnode(offset), NULL, + pre_reloc_only); if (err && !ret) { ret = err; debug("%s: ret=%d\n", node_name, ret); diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index 303e166a69..3cf9dd9dbe 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -53,6 +53,29 @@ static int syscon_pre_probe(struct udevice *dev) #endif } +struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev, + const char *name) +{ + struct udevice *syscon; + struct regmap *r; + int err; + + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + name, &syscon); + if (err) { + dev_dbg(dev, "unable to find syscon device\n"); + return ERR_PTR(err); + } + + r = syscon_get_regmap(syscon); + if (!r) { + dev_dbg(dev, "unable to find regmap\n"); + return ERR_PTR(-ENODEV); + } + + return r; +} + int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp) { struct udevice *dev; @@ -123,52 +146,31 @@ U_BOOT_DRIVER(generic_syscon) = { * The syscon node can be bound to another driver, but still works * as a syscon provider. */ -static LIST_HEAD(syscon_list); - -struct syscon { - ofnode node; - struct regmap *regmap; - struct list_head list; -}; - -static struct syscon *of_syscon_register(ofnode node) +struct regmap *syscon_node_to_regmap(ofnode node) { - struct syscon *syscon; + struct udevice *dev, *parent; int ret; + if (!uclass_get_device_by_ofnode(UCLASS_SYSCON, node, &dev)) + return syscon_get_regmap(dev); + if (!ofnode_device_is_compatible(node, "syscon")) return ERR_PTR(-EINVAL); - syscon = malloc(sizeof(*syscon)); - if (!syscon) - return ERR_PTR(-ENOMEM); + /* bound to driver with same ofnode or to root if not found */ + if (device_find_global_by_ofnode(node, &parent)) + parent = dm_root(); - ret = regmap_init_mem(node, &syscon->regmap); - if (ret) { - free(syscon); + /* force bound to syscon class */ + ret = device_bind_driver_to_node(parent, "syscon", + ofnode_get_name(node), + node, &dev); + if (ret) return ERR_PTR(ret); - } - list_add_tail(&syscon->list, &syscon_list); + ret = device_probe(dev); + if (ret) + return ERR_PTR(ret); - return syscon; -} - -struct regmap *syscon_node_to_regmap(ofnode node) -{ - struct syscon *entry, *syscon = NULL; - - list_for_each_entry(entry, &syscon_list, list) - if (ofnode_equal(entry->node, node)) { - syscon = entry; - break; - } - - if (!syscon) - syscon = of_syscon_register(node); - - if (IS_ERR(syscon)) - return ERR_CAST(syscon); - - return syscon->regmap; + return syscon_get_regmap(dev); } diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 3113d6a56b..a622f07941 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -180,7 +180,7 @@ int dev_get_uclass_index(struct udevice *dev, struct uclass **ucp) if (list_empty(&uc->dev_head)) return -ENODEV; - list_for_each_entry(iter, &uc->dev_head, uclass_node) { + uclass_foreach_dev(iter, uc) { if (iter == dev) { if (ucp) *ucp = uc; @@ -205,7 +205,7 @@ int uclass_find_device(enum uclass_id id, int index, struct udevice **devp) if (list_empty(&uc->dev_head)) return -ENODEV; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { if (!index--) { *devp = dev; return 0; @@ -259,7 +259,7 @@ int uclass_find_device_by_name(enum uclass_id id, const char *name, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { if (!strncmp(dev->name, name, strlen(name))) { *devp = dev; return 0; @@ -269,6 +269,30 @@ int uclass_find_device_by_name(enum uclass_id id, const char *name, return -ENODEV; } +#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA) +int uclass_find_next_free_req_seq(enum uclass_id id) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + int max = -1; + + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if ((dev->req_seq != -1) && (dev->req_seq > max)) + max = dev->req_seq; + } + + if (max == -1) + return 0; + + return max + 1; +} +#endif + int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, bool find_req_seq, struct udevice **devp) { @@ -284,7 +308,7 @@ int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { debug(" - %d %d '%s'\n", dev->req_seq, dev->seq, dev->name); if ((find_req_seq ? dev->req_seq : dev->seq) == seq_or_req_seq) { @@ -312,7 +336,7 @@ int uclass_find_device_by_of_offset(enum uclass_id id, int node, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { if (dev_of_offset(dev) == node) { *devp = dev; return 0; @@ -337,7 +361,7 @@ int uclass_find_device_by_ofnode(enum uclass_id id, ofnode node, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { log(LOGC_DM, LOGL_DEBUG_CONTENT, " - checking %s\n", dev->name); if (ofnode_equal(dev_ofnode(dev), node)) { @@ -354,10 +378,8 @@ done: } #if CONFIG_IS_ENABLED(OF_CONTROL) -static int uclass_find_device_by_phandle(enum uclass_id id, - struct udevice *parent, - const char *name, - struct udevice **devp) +int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -372,7 +394,7 @@ static int uclass_find_device_by_phandle(enum uclass_id id, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { uint phandle; phandle = dev_read_phandle(dev); @@ -399,7 +421,7 @@ int uclass_get_device_by_driver(enum uclass_id id, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { if (dev->driver == find_drv) return uclass_get_device_tail(dev, 0, devp); } @@ -499,7 +521,7 @@ int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id, if (ret) return ret; - list_for_each_entry(dev, &uc->dev_head, uclass_node) { + uclass_foreach_dev(dev, uc) { uint phandle; phandle = dev_read_phandle(dev); @@ -562,6 +584,19 @@ int uclass_next_device(struct udevice **devp) return uclass_get_device_tail(dev, ret, devp); } +int uclass_next_device_err(struct udevice **devp) +{ + int ret; + + ret = uclass_next_device(devp); + if (ret) + return ret; + else if (!*devp) + return -ENODEV; + + return 0; +} + int uclass_first_device_check(enum uclass_id id, struct udevice **devp) { int ret; @@ -687,8 +722,19 @@ int uclass_pre_probe_device(struct udevice *dev) int uclass_post_probe_device(struct udevice *dev) { - struct uclass_driver *uc_drv = dev->uclass->uc_drv; + struct uclass_driver *uc_drv; + int ret; + if (dev->parent) { + uc_drv = dev->parent->uclass->uc_drv; + if (uc_drv->child_post_probe) { + ret = uc_drv->child_post_probe(dev); + if (ret) + return ret; + } + } + + uc_drv = dev->uclass->uc_drv; if (uc_drv->post_probe) return uc_drv->post_probe(dev); diff --git a/drivers/core/util.c b/drivers/core/util.c index 451d4766d0..27a6848703 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -53,3 +54,27 @@ bool dm_fdt_pre_reloc(const void *blob, int offset) return false; } + +bool dm_ofnode_pre_reloc(ofnode node) +{ + if (ofnode_read_bool(node, "u-boot,dm-pre-reloc")) + return true; + +#ifdef CONFIG_TPL_BUILD + if (ofnode_read_bool(node, "u-boot,dm-tpl")) + return true; +#elif defined(CONFIG_SPL_BUILD) + if (ofnode_read_bool(node, "u-boot,dm-spl")) + return true; +#else + /* + * In regular builds individual spl and tpl handling both + * count as handled pre-relocation for later second init. + */ + if (ofnode_read_bool(node, "u-boot,dm-spl") || + ofnode_read_bool(node, "u-boot,dm-tpl")) + return true; +#endif + + return false; +} diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index d4052005e2..3d5729f6dc 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -13,3 +13,9 @@ config CPU_MPC83XX select CLK_MPC83XX help Support CPU cores for SoCs of the MPC83xx series. + +config CPU_RISCV + bool "Enable RISC-V CPU driver" + depends on CPU && RISCV + help + Support CPU cores for RISC-V architecture. diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 858b03755f..be0300cd4a 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o +obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o obj-$(CONFIG_SANDBOX) += cpu_sandbox.o diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c index 31717afaec..7bc86bf9b2 100644 --- a/drivers/cpu/mpc83xx_cpu.c +++ b/drivers/cpu/mpc83xx_cpu.c @@ -262,7 +262,7 @@ static int mpc83xx_cpu_get_desc(struct udevice *dev, char *buf, int size) determine_cpu_data(dev); snprintf(buf, size, - "CPU: %s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz\n", + "%s, MPC%s%s%s, Rev: %d.%d at %s MHz, CSB: %s MHz", e300_names[priv->e300_type], cpu_type_names[priv->type], priv->is_e_processor ? "E" : "", diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c new file mode 100644 index 0000000000..5e15df590e --- /dev/null +++ b/drivers/cpu/riscv_cpu.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) +{ + const char *isa; + + isa = dev_read_string(dev, "riscv,isa"); + if (size < (strlen(isa) + 1)) + return -ENOSPC; + + strcpy(buf, isa); + + return 0; +} + +static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) +{ + const char *mmu; + + dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + + mmu = dev_read_string(dev, "mmu-type"); + if (!mmu) + info->features |= BIT(CPU_FEAT_MMU); + + return 0; +} + +static int riscv_cpu_get_count(struct udevice *dev) +{ + ofnode node; + int num = 0; + + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + if (strcmp(device_type, "cpu") == 0) + num++; + } + + return num; +} + +static int riscv_cpu_bind(struct udevice *dev) +{ + struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct driver *drv; + int ret; + + /* save the hart id */ + plat->cpu_id = dev_read_addr(dev); + + /* first examine the property in current cpu node */ + ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); + /* if not found, then look at the parent /cpus node */ + if (ret) + dev_read_u32(dev->parent, "timebase-frequency", + &plat->timebase_freq); + + /* + * Bind riscv-timer driver on hart 0 + * + * We only instantiate one timer device which is enough for U-Boot. + * Pass the "timebase-frequency" value as the driver data for the + * timer device. + * + * Return value is not checked since it's possible that the timer + * driver is not included. + */ + if (!plat->cpu_id && plat->timebase_freq) { + drv = lists_driver_lookup_name("riscv_timer"); + if (!drv) { + debug("Cannot find the timer driver, not included?\n"); + return 0; + } + + device_bind_with_driver_data(dev, drv, "riscv_timer", + plat->timebase_freq, ofnode_null(), + NULL); + } + + return 0; +} + +static const struct cpu_ops riscv_cpu_ops = { + .get_desc = riscv_cpu_get_desc, + .get_info = riscv_cpu_get_info, + .get_count = riscv_cpu_get_count, +}; + +static const struct udevice_id riscv_cpu_ids[] = { + { .compatible = "riscv" }, + { } +}; + +U_BOOT_DRIVER(riscv_cpu) = { + .name = "riscv_cpu", + .id = UCLASS_CPU, + .of_match = riscv_cpu_ids, + .bind = riscv_cpu_bind, + .ops = &riscv_cpu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index b764add060..d4b393d25e 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1 +1,2 @@ source "drivers/ddr/altera/Kconfig" +source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index a3d2bd5fe6..c5bd8a8876 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ + ARCH_LX2160A || \ ARCH_T4160 default 1 diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig new file mode 100644 index 0000000000..7e06fb2f7d --- /dev/null +++ b/drivers/ddr/imx/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/imx/imx8m/Kconfig" diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig new file mode 100644 index 0000000000..71f466f5ec --- /dev/null +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -0,0 +1,22 @@ +config IMX8M_DRAM + bool "imx8m dram" + +config IMX8M_LPDDR4 + bool "imx8m lpddr4" + select IMX8M_DRAM + help + Select the i.MX8M LPDDR4 driver support on i.MX8M SOC. + +config IMX8M_DDR4 + bool "imx8m ddr4" + select IMX8M_DRAM + help + Select the i.MX8M DDR4 driver support on i.MX8M SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. OCRAM_S is used for this + purpose on i.MX8MM. + default 0x180000 diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile new file mode 100644 index 0000000000..64f9ab20e6 --- /dev/null +++ b/drivers/ddr/imx/imx8m/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +endif diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c new file mode 100644 index 0000000000..031cdc57e1 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddr4_init.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + volatile unsigned int tmp_t; + /* + * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, + * [4]src_system_rst_b! + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); + /* deassert [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + + /* + * change the clock source of dram_apb_clk_root + * to source 4 --800MHz/4 + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + /* config the uMCTL2's registers */ + ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000001); + /* RESET: DEASSERTED */ + /* RESET: +#include + +/* ddr phy trained csr */ +struct dram_cfg_param ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c new file mode 100644 index 0000000000..18f7ed7fea --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_train.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +void ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddr_load_train_firmware(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + wait_ddrphy_training_complete(); + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c new file mode 100644 index 0000000000..4732539764 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include +#include +#include +#include +#include +#include +#include + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_receive(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + debug("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} + +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, + unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c new file mode 100644 index 0000000000..61cd4f6db1 --- /dev/null +++ b/drivers/ddr/imx/imx8m/helper.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 /* byte */ +#define DMEM_LEN 16384 /* byte */ +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_firmware(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + debug("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) + printf("check ddr4_pmu_train_imem code fail=%d\n", error); + else + debug("check ddr4_pmu_train_imem code pass\n"); + + debug("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) + printf("check ddr4_pmu_train_dmem code fail=%d", error); + else + debug("check ddr4_pmu_train_dmem code pass\n"); +} + +void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, + unsigned int num) +{ + int i = 0; + + /* enable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + for (i = 0; i < num; i++) { + ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr++; + } + /* disable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xc0080, 0x2); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void dram_config_save(struct dram_timing_info *timing_info, + unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; + saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; + saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + + sizeof(*timing_info)); + + /* save ddrc config */ + saved_timing->ddrc_cfg = cfg; + for (i = 0; i < timing_info->ddrc_cfg_num; i++) { + cfg->reg = timing_info->ddrc_cfg[i].reg; + cfg->val = timing_info->ddrc_cfg[i].val; + cfg++; + } + + /* save ddrphy config */ + saved_timing->ddrphy_cfg = cfg; + for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { + cfg->reg = timing_info->ddrphy_cfg[i].reg; + cfg->val = timing_info->ddrphy_cfg[i].val; + cfg++; + } + + /* save the ddrphy csr */ + saved_timing->ddrphy_trained_csr = cfg; + for (i = 0; i < ddrphy_trained_csr_num; i++) { + cfg->reg = ddrphy_trained_csr[i].reg; + cfg->val = ddrphy_trained_csr[i].val; + cfg++; + } + + /* save the ddrphy pie */ + saved_timing->ddrphy_pie = cfg; + for (i = 0; i < timing_info->ddrphy_pie_num; i++) { + cfg->reg = timing_info->ddrphy_pie[i].reg; + cfg->val = timing_info->ddrphy_pie[i].val; + cfg++; + } +} diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c new file mode 100644 index 0000000000..a4bc1de8eb --- /dev/null +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +* +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp; + + debug("DDRINFO: start lpddr4 ddr init\n"); + /* step 1: reset */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + mdelay(100); + + debug("DDRINFO: reset done\n"); + /* + * change the clock source of dram_apb_clk_root: + * source 4 800MHz /4 = 200MHz + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + debug("DDRINFO: cfg clk\n"); + dram_pll_init(MHZ(750)); + + /* + * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /*step2 Configure uMCTL2's registers */ + debug("DDRINFO: ddrc config start\n"); + lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* + * step3 de-assert all reset + * RESET: DEASSERTED + * RESET: for Port 0 DEASSERT(0)ED + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + /* step4 */ + /* [0]dis_auto_refresh=1 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x33f) != 0x223); + + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* step5 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step6 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000210); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000110); + else + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* step7 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step8 Configure LPDDR4 PHY's registers */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + debug("DDRINFO:ddrphy calibration done\n"); + + /* step15 [0]--0: to enable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step16 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000230); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000130); + else + reg32_write(DDRC_DFIMISC(0), 0x00000030); + + /* step17 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* step18 wait DFISTAT.dfi_init_complete to 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* step19 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step20~22 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000211); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000111); + } else { + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + } + + /* step23 [5]selfref_sw=0; */ + reg32_write(DDRC_PWRCTL(0), 0x00000008); + /* step24 sw_done=1 */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step25 wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + +#ifdef DFI_BUG_WR + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); +#endif + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* step26 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + debug("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c index 1eac0bcd2b..f5fc964d6f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_debug.c +++ b/drivers/ddr/marvell/a38x/ddr3_debug.c @@ -4,6 +4,8 @@ */ #include "ddr3_init.h" +#include "mv_ddr_training_db.h" +#include "mv_ddr_regs.h" u8 is_reg_dump = 0; u8 debug_pbs = DEBUG_LEVEL_ERROR; @@ -83,7 +85,7 @@ void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level) #endif /* SILENT_LIB */ #if defined(DDR_VIEWER_TOOL) -static char *convert_freq(enum hws_ddr_freq freq); +static char *convert_freq(enum mv_ddr_freq freq); #if defined(EXCLUDE_SWITCH_DEBUG) u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM]; u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM]; @@ -176,23 +178,6 @@ int ddr3_tip_init_config_func(u32 dev_num, return MV_OK; } -/* - * Read training result table - */ -int hws_ddr3_tip_read_training_result( - u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) -{ - if (result == NULL) - return MV_BAD_PARAM; - - memcpy(result, training_result, - sizeof(enum hws_result) * - MAX_STAGE_LIMIT * - MAX_INTERFACE_NUM); - - return MV_OK; -} - /* * Get training result info pointer */ @@ -218,50 +203,50 @@ int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr) /* * Convert freq to character string */ -static char *convert_freq(enum hws_ddr_freq freq) +static char *convert_freq(enum mv_ddr_freq freq) { switch (freq) { - case DDR_FREQ_LOW_FREQ: - return "DDR_FREQ_LOW_FREQ"; + case MV_DDR_FREQ_LOW_FREQ: + return "MV_DDR_FREQ_LOW_FREQ"; - case DDR_FREQ_400: + case MV_DDR_FREQ_400: return "400"; - case DDR_FREQ_533: + case MV_DDR_FREQ_533: return "533"; - case DDR_FREQ_667: + case MV_DDR_FREQ_667: return "667"; - case DDR_FREQ_800: + case MV_DDR_FREQ_800: return "800"; - case DDR_FREQ_933: + case MV_DDR_FREQ_933: return "933"; - case DDR_FREQ_1066: + case MV_DDR_FREQ_1066: return "1066"; - case DDR_FREQ_311: + case MV_DDR_FREQ_311: return "311"; - case DDR_FREQ_333: + case MV_DDR_FREQ_333: return "333"; - case DDR_FREQ_467: + case MV_DDR_FREQ_467: return "467"; - case DDR_FREQ_850: + case MV_DDR_FREQ_850: return "850"; - case DDR_FREQ_900: + case MV_DDR_FREQ_900: return "900"; - case DDR_FREQ_360: - return "DDR_FREQ_360"; + case MV_DDR_FREQ_360: + return "MV_DDR_FREQ_360"; - case DDR_FREQ_1000: - return "DDR_FREQ_1000"; + case MV_DDR_FREQ_1000: + return "MV_DDR_FREQ_1000"; default: return "Unknown Frequency"; @@ -364,7 +349,7 @@ int ddr3_tip_print_log(u32 dev_num, u32 mem_addr) if ((is_validate_window_per_if != 0) || (is_validate_window_per_pup != 0)) { u32 is_pup_log = 0; - enum hws_ddr_freq freq; + enum mv_ddr_freq freq; freq = tm->interface_params[first_active_if].memory_freq; @@ -528,7 +513,7 @@ int ddr3_tip_print_stability_log(u32 dev_num) u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0; u32 reg_data; u32 read_data[MAX_INTERFACE_NUM]; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); /* Title print */ @@ -844,8 +829,6 @@ u32 xsb_test_table[][8] = { 0xffffffff, 0xffffffff} }; -static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr); - int ddr3_tip_print_adll(void) { u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; @@ -877,353 +860,6 @@ int ddr3_tip_print_adll(void) return MV_OK; } -/* - * Set attribute value - */ -int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value) -{ - int ret; - u32 *ptr_flag = NULL; - - ret = ddr3_tip_access_atr(dev_num, flag_id, value, &ptr_flag); - if (ptr_flag != NULL) { - printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x (was 0x%x)\n", - flag_id, value, *ptr_flag); - *ptr_flag = value; - } else { - printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x\n", - flag_id, value); - } - - return ret; -} - -/* - * Access attribute - */ -static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr) -{ - u32 tmp_val = 0, if_id = 0, pup_id = 0; - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - *ptr = NULL; - - switch (flag_id) { - case 0: - *ptr = (u32 *)&(tm->if_act_mask); - break; - - case 0x1: - *ptr = (u32 *)&mask_tune_func; - break; - - case 0x2: - low_freq = (enum hws_ddr_freq)value; - break; - - case 0x3: - medium_freq = (enum hws_ddr_freq)value; - break; - - case 0x4: - *ptr = (u32 *)&generic_init_controller; - break; - - case 0x8: - *ptr = (u32 *)&start_xsb_offset; - break; - - case 0x20: - *ptr = (u32 *)&is_rl_old; - break; - - case 0x21: - *ptr = (u32 *)&is_freq_old; - break; - - case 0x23: - *ptr = (u32 *)&is_dfs_disabled; - break; - - case 0x24: - *ptr = (u32 *)&is_pll_before_init; - break; - - case 0x25: - *ptr = (u32 *)&is_adll_calib_before_init; - break; - case 0x28: - *ptr = (u32 *)&is_tune_result; - break; - - case 0x29: - *ptr = (u32 *)&is_validate_window_per_if; - break; - - case 0x2a: - *ptr = (u32 *)&is_validate_window_per_pup; - break; - - case 0x30: - *ptr = (u32 *)&sweep_cnt; - break; - - case 0x31: - *ptr = (u32 *)&is_bist_reset_bit; - break; - - case 0x32: - *ptr = (u32 *)&is_dfs_in_init; - break; - - case 0x33: - *ptr = (u32 *)&g_zpodt_data; - break; - - case 0x34: - *ptr = (u32 *)&g_znodt_data; - break; - - case 0x35: - break; - - case 0x36: - *ptr = (u32 *)&(freq_val[DDR_FREQ_LOW_FREQ]); - break; - - case 0x37: - *ptr = (u32 *)&start_pattern; - break; - - case 0x38: - *ptr = (u32 *)&end_pattern; - break; - - case 0x39: - *ptr = (u32 *)&phy_reg0_val; - break; - - case 0x4a: - *ptr = (u32 *)&phy_reg1_val; - break; - - case 0x4b: - *ptr = (u32 *)&phy_reg2_val; - break; - - case 0x4c: - *ptr = (u32 *)&phy_reg3_val; - break; - - case 0x4e: - sweep_pattern = (enum hws_pattern)value; - break; - - case 0x51: - *ptr = (u32 *)&g_znri_data; - break; - - case 0x52: - *ptr = (u32 *)&g_zpri_data; - break; - - case 0x53: - *ptr = (u32 *)&finger_test; - break; - - case 0x54: - *ptr = (u32 *)&n_finger_start; - break; - - case 0x55: - *ptr = (u32 *)&n_finger_end; - break; - - case 0x56: - *ptr = (u32 *)&p_finger_start; - break; - - case 0x57: - *ptr = (u32 *)&p_finger_end; - break; - - case 0x58: - *ptr = (u32 *)&p_finger_step; - break; - - case 0x59: - *ptr = (u32 *)&n_finger_step; - break; - - case 0x5a: - *ptr = (u32 *)&g_znri_ctrl; - break; - - case 0x5b: - *ptr = (u32 *)&g_zpri_ctrl; - break; - - case 0x5c: - *ptr = (u32 *)&is_reg_dump; - break; - - case 0x5d: - *ptr = (u32 *)&vref_init_val; - break; - - case 0x5e: - *ptr = (u32 *)&mode_2t; - break; - - case 0x5f: - *ptr = (u32 *)&xsb_validate_type; - break; - - case 0x60: - *ptr = (u32 *)&xsb_validation_base_address; - break; - - case 0x67: - *ptr = (u32 *)&activate_select_before_run_alg; - break; - - case 0x68: - *ptr = (u32 *)&activate_deselect_after_run_alg; - break; - - case 0x69: - *ptr = (u32 *)&odt_additional; - break; - - case 0x70: - *ptr = (u32 *)&debug_mode; - break; - - case 0x71: - pbs_pattern = (enum hws_pattern)value; - break; - - case 0x72: - *ptr = (u32 *)&delay_enable; - break; - - case 0x73: - *ptr = (u32 *)&ck_delay; - break; - - case 0x75: - *ptr = (u32 *)&ca_delay; - break; - - case 0x100: - *ptr = (u32 *)&debug_dunit; - break; - - case 0x101: - debug_acc = (int)value; - break; - - case 0x102: - debug_training = (u8)value; - break; - - case 0x103: - debug_training_bist = (u8)value; - break; - - case 0x104: - debug_centralization = (u8)value; - break; - - case 0x105: - debug_training_ip = (u8)value; - break; - - case 0x106: - debug_leveling = (u8)value; - break; - - case 0x107: - debug_pbs = (u8)value; - break; - - case 0x108: - debug_training_static = (u8)value; - break; - - case 0x109: - debug_training_access = (u8)value; - break; - - - case 0x112: - *ptr = &start_pattern; - break; - - case 0x113: - *ptr = &end_pattern; - break; - - default: - if ((flag_id >= 0x200) && (flag_id < 0x210)) { - if_id = flag_id - 0x200; - *ptr = (u32 *)&(tm->interface_params - [if_id].memory_freq); - } else if ((flag_id >= 0x210) && (flag_id < 0x220)) { - if_id = flag_id - 0x210; - *ptr = (u32 *)&(tm->interface_params - [if_id].speed_bin_index); - } else if ((flag_id >= 0x220) && (flag_id < 0x230)) { - if_id = flag_id - 0x220; - *ptr = (u32 *)&(tm->interface_params - [if_id].bus_width); - } else if ((flag_id >= 0x230) && (flag_id < 0x240)) { - if_id = flag_id - 0x230; - *ptr = (u32 *)&(tm->interface_params - [if_id].memory_size); - } else if ((flag_id >= 0x240) && (flag_id < 0x250)) { - if_id = flag_id - 0x240; - *ptr = (u32 *)&(tm->interface_params - [if_id].cas_l); - } else if ((flag_id >= 0x250) && (flag_id < 0x260)) { - if_id = flag_id - 0x250; - *ptr = (u32 *)&(tm->interface_params - [if_id].cas_wl); - } else if ((flag_id >= 0x270) && (flag_id < 0x2cf)) { - if_id = (flag_id - 0x270) / MAX_BUS_NUM; - pup_id = (flag_id - 0x270) % MAX_BUS_NUM; - *ptr = (u32 *)&(tm->interface_params[if_id]. - as_bus_params[pup_id].is_ck_swap); - } else if ((flag_id >= 0x2d0) && (flag_id < 0x32f)) { - if_id = (flag_id - 0x2d0) / MAX_BUS_NUM; - pup_id = (flag_id - 0x2d0) % MAX_BUS_NUM; - *ptr = (u32 *)&(tm->interface_params[if_id]. - as_bus_params[pup_id].is_dqs_swap); - } else if ((flag_id >= 0x330) && (flag_id < 0x38f)) { - if_id = (flag_id - 0x330) / MAX_BUS_NUM; - pup_id = (flag_id - 0x330) % MAX_BUS_NUM; - *ptr = (u32 *)&(tm->interface_params[if_id]. - as_bus_params[pup_id].cs_bitmask); - } else if ((flag_id >= 0x390) && (flag_id < 0x3ef)) { - if_id = (flag_id - 0x390) / MAX_BUS_NUM; - pup_id = (flag_id - 0x390) % MAX_BUS_NUM; - *ptr = (u32 *)&(tm->interface_params - [if_id].as_bus_params - [pup_id].mirror_enable_bitmask); - } else if ((flag_id >= 0x500) && (flag_id <= 0x50f)) { - tmp_val = flag_id - 0x320; - *ptr = (u32 *)&(clamp_tbl[tmp_val]); - } else { - DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, - ("flag_id out of boundary %d\n", - flag_id)); - return MV_BAD_PARAM; - } - } - - return MV_OK; -} - #endif /* EXCLUDE_SWITCH_DEBUG */ #if defined(DDR_VIEWER_TOOL) @@ -1315,7 +951,7 @@ int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, u32 reg; enum hws_access_type pup_access; u32 cs; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); @@ -1462,7 +1098,7 @@ int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, u32 reg; enum hws_access_type pup_access; u32 cs; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 27dbf4f44b..22c8f9ca54 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -6,18 +6,6 @@ #include "ddr3_init.h" #include "mv_ddr_common.h" -/* - * Translates topology map definitions to real memory size in bits - * (per values in ddr3_training_ip_def.h) - */ -u32 mem_size[] = { - ADDR_SIZE_512MB, - ADDR_SIZE_1GB, - ADDR_SIZE_2GB, - ADDR_SIZE_4GB, - ADDR_SIZE_8GB -}; - static char *ddr_type = "DDR3"; /* @@ -37,8 +25,6 @@ static int mv_ddr_training_params_set(u8 dev_num); */ int ddr3_init(void) { - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - u32 octets_per_if_num; int status; int is_manual_cal_done; @@ -55,7 +41,7 @@ int ddr3_init(void) mv_ddr_early_init(); - if (mv_ddr_topology_map_update() == NULL) { + if (mv_ddr_topology_map_update()) { printf("mv_ddr: failed to update topology\n"); return MV_FAIL; } @@ -68,7 +54,6 @@ int ddr3_init(void) if (MV_OK != status) return status; - mv_ddr_mc_config(); is_manual_cal_done = mv_ddr_manual_cal_do(); @@ -101,76 +86,14 @@ int ddr3_init(void) mv_ddr_post_training_fixup(); - octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); - if (ddr3_if_ecc_enabled()) { - if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) || - MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(tm->bus_act_mask, octets_per_if_num)) - mv_ddr_mem_scrubbing(); - else - ddr3_new_tip_ecc_scrub(); - } + if (mv_ddr_is_ecc_ena()) + mv_ddr_mem_scrubbing(); printf("mv_ddr: completed successfully\n"); return MV_OK; } -uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void) -{ - uint64_t memory_size_per_cs; - - u32 bus_cnt, num_of_active_bus = 0; - u32 num_of_sub_phys_per_ddr_unit = 0; - - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - u32 octets_per_if_num = ddr3_tip_dev_attr_get(DEV_NUM_0, MV_ATTR_OCTET_PER_INTERFACE); - - /* count the number of active bus */ - for (bus_cnt = 0; bus_cnt < octets_per_if_num - 1/* ignore ecc octet */; bus_cnt++) { - VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); - num_of_active_bus++; - } - - /* calculate number of sub-phys per ddr unit */ - if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_16BIT) - num_of_sub_phys_per_ddr_unit = TWO_SUB_PHYS; - if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_8BIT) - num_of_sub_phys_per_ddr_unit = SINGLE_SUB_PHY; - - /* calculate dram size per cs */ - memory_size_per_cs = (uint64_t)mem_size[tm->interface_params[0].memory_size] * (uint64_t)num_of_active_bus - / (uint64_t)num_of_sub_phys_per_ddr_unit * (uint64_t)MV_DDR_NUM_BITS_IN_BYTE; - - return memory_size_per_cs; -} - -uint64_t mv_ddr_get_total_memory_size_in_bits(void) -{ - uint64_t total_memory_size = 0; - uint64_t memory_size_per_cs = 0; - - /* get the number of cs */ - u32 max_cs = ddr3_tip_max_cs_get(DEV_NUM_0); - - memory_size_per_cs = mv_ddr_get_memory_size_per_cs_in_bits(); - total_memory_size = (uint64_t)max_cs * memory_size_per_cs; - - return total_memory_size; -} - -int ddr3_if_ecc_enabled(void) -{ - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) || - DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) || - DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask)) - return 1; - else - return 0; -} - /* * Name: mv_ddr_training_params_set * Desc: @@ -182,15 +105,9 @@ static int mv_ddr_training_params_set(u8 dev_num) { struct tune_train_params params; int status; - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - u32 if_id; u32 cs_num; - CHECK_STATUS(ddr3_tip_get_first_active_if - (dev_num, tm->if_act_mask, - &if_id)); - - CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); + cs_num = mv_ddr_cs_num_get(); /* NOTE: do not remove any field initilization */ params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h index 382bd922f2..055516b67e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.h +++ b/drivers/ddr/marvell/a38x/ddr3_init.h @@ -7,9 +7,7 @@ #define _DDR3_INIT_H #include "ddr_ml_wrapper.h" -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) #include "mv_ddr_plat.h" -#endif #include "seq_exec.h" #include "ddr3_logging_def.h" @@ -32,14 +30,8 @@ return status; \ } -#define GET_MAX_VALUE(x, y) \ - ((x) > (y)) ? (x) : (y) - #define SUB_VERSION 0 -/* max number of devices supported by driver */ -#define MAX_DEVICE_NUM 1 - enum log_level { MV_LOG_LEVEL_0, MV_LOG_LEVEL_1, @@ -47,24 +39,26 @@ enum log_level { MV_LOG_LEVEL_3 }; +/* TODO: consider to move to misl phy driver */ +#define MISL_PHY_DRV_P_OFFS 0x7 +#define MISL_PHY_DRV_N_OFFS 0x0 +#define MISL_PHY_ODT_P_OFFS 0x6 +#define MISL_PHY_ODT_N_OFFS 0x0 + /* Globals */ extern u8 debug_training, debug_calibration, debug_ddr4_centralization, debug_tap_tuning, debug_dm_tuning; extern u8 is_reg_dump; extern u8 generic_init_controller; -/* list of allowed frequency listed in order of enum hws_ddr_freq */ -extern u32 freq_val[DDR_FREQ_LAST]; +/* list of allowed frequency listed in order of enum mv_ddr_freq */ extern u32 is_pll_old; -extern struct cl_val_per_freq cas_latency_table[]; extern struct pattern_info pattern_table[]; -extern struct cl_val_per_freq cas_write_latency_table[]; extern u8 debug_centralization, debug_training_ip, debug_training_bist, debug_pbs, debug_training_static, debug_leveling; extern struct hws_tip_config_func_db config_func_info[]; extern u8 twr_mask_table[]; extern u8 cl_mask_table[]; extern u8 cwl_mask_table[]; -extern u16 rfc_table[]; extern u32 speed_bin_table_t_rc[]; extern u32 speed_bin_table_t_rcd_t_rp[]; @@ -90,10 +84,10 @@ extern u32 mask_tune_func; extern u32 rl_version; extern int rl_mid_freq_wa; extern u8 calibration_update_control; /* 2 external only, 1 is internal only */ -extern enum hws_ddr_freq medium_freq; +extern enum mv_ddr_freq medium_freq; extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]; -extern enum hws_ddr_freq low_freq; +extern enum mv_ddr_freq low_freq; extern enum auto_tune_stage training_stage; extern u32 is_pll_before_init; extern u32 is_adll_calib_before_init; @@ -120,7 +114,7 @@ extern u32 odt_additional; extern u32 debug_mode; extern u32 debug_dunit; extern u32 clamp_tbl[]; -extern u32 freq_mask[MAX_DEVICE_NUM][DDR_FREQ_LAST]; +extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST]; extern u32 maxt_poll_tries; extern u32 is_bist_reset_bit; @@ -139,7 +133,6 @@ extern u16 mask_results_dq_reg_map[]; extern u32 target_freq; extern u32 dfs_low_freq; -extern u32 mem_size[]; extern u32 nominal_avs; extern u32 extension_avs; @@ -154,13 +147,8 @@ int mv_ddr_early_init(void); int mv_ddr_early_init2(void); int ddr3_silicon_post_init(void); int ddr3_post_run_alg(void); -int ddr3_if_ecc_enabled(void); void ddr3_new_tip_ecc_scrub(void); -void mv_ddr_ver_print(void); -struct mv_ddr_topology_map *mv_ddr_topology_map_get(void); - -int ddr3_if_ecc_enabled(void); int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data); int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask); int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq); @@ -185,15 +173,20 @@ void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); void ddr3_fast_path_static_cs_size_config(u32 cs_ena); u32 mv_board_id_index_get(u32 board_id); void ddr3_set_log_level(u32 n_log_level); -int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num); int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr); int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode); int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode); - -u32 mv_ddr_init_freq_get(void); void mv_ddr_mc_config(void); int mv_ddr_mc_init(void); void mv_ddr_set_calib_controller(void); +/* TODO: consider to move to misl phy driver */ +unsigned int mv_ddr_misl_phy_drv_data_p_get(void); +unsigned int mv_ddr_misl_phy_drv_data_n_get(void); +unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void); +unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void); +unsigned int mv_ddr_misl_phy_odt_p_get(void); +unsigned int mv_ddr_misl_phy_odt_n_get(void); + #endif /* _DDR3_INIT_H */ diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h deleted file mode 100644 index 1963bae3e6..0000000000 --- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - */ - -#ifndef _DDR3_TOPOLOGY_DEF_H -#define _DDR3_TOPOLOGY_DEF_H - -#define DEV_NUM_0 0 - -/* TOPOLOGY */ -enum hws_speed_bin { - SPEED_BIN_DDR_800D, - SPEED_BIN_DDR_800E, - SPEED_BIN_DDR_1066E, - SPEED_BIN_DDR_1066F, - SPEED_BIN_DDR_1066G, - SPEED_BIN_DDR_1333F, - SPEED_BIN_DDR_1333G, - SPEED_BIN_DDR_1333H, - SPEED_BIN_DDR_1333J, - SPEED_BIN_DDR_1600G, - SPEED_BIN_DDR_1600H, - SPEED_BIN_DDR_1600J, - SPEED_BIN_DDR_1600K, - SPEED_BIN_DDR_1866J, - SPEED_BIN_DDR_1866K, - SPEED_BIN_DDR_1866L, - SPEED_BIN_DDR_1866M, - SPEED_BIN_DDR_2133K, - SPEED_BIN_DDR_2133L, - SPEED_BIN_DDR_2133M, - SPEED_BIN_DDR_2133N, - - SPEED_BIN_DDR_1333H_EXT, - SPEED_BIN_DDR_1600K_EXT, - SPEED_BIN_DDR_1866M_EXT -}; - -enum hws_ddr_freq { - DDR_FREQ_LOW_FREQ, - DDR_FREQ_400, - DDR_FREQ_533, - DDR_FREQ_667, - DDR_FREQ_800, - DDR_FREQ_933, - DDR_FREQ_1066, - DDR_FREQ_311, - DDR_FREQ_333, - DDR_FREQ_467, - DDR_FREQ_850, - DDR_FREQ_600, - DDR_FREQ_300, - DDR_FREQ_900, - DDR_FREQ_360, - DDR_FREQ_1000, - DDR_FREQ_LAST, - DDR_FREQ_SAR -}; - -enum speed_bin_table_elements { - SPEED_BIN_TRCD, - SPEED_BIN_TRP, - SPEED_BIN_TRAS, - SPEED_BIN_TRC, - SPEED_BIN_TRRD1K, - SPEED_BIN_TRRD2K, - SPEED_BIN_TPD, - SPEED_BIN_TFAW1K, - SPEED_BIN_TFAW2K, - SPEED_BIN_TWTR, - SPEED_BIN_TRTP, - SPEED_BIN_TWR, - SPEED_BIN_TMOD, - SPEED_BIN_TXPDLL -}; - -#endif /* _DDR3_TOPOLOGY_DEF_H */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 799c5ba089..c7be700d64 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -5,6 +5,8 @@ #include "ddr3_init.h" #include "mv_ddr_common.h" +#include "mv_ddr_training_db.h" +#include "mv_ddr_regs.h" #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) @@ -14,8 +16,8 @@ u32 phy_reg0_val = 0; u32 phy_reg1_val = 8; u32 phy_reg2_val = 0; u32 phy_reg3_val = PARAM_UNDEFINED; -enum hws_ddr_freq low_freq = DDR_FREQ_LOW_FREQ; -enum hws_ddr_freq medium_freq; +enum mv_ddr_freq low_freq = MV_DDR_FREQ_LOW_FREQ; +enum mv_ddr_freq medium_freq; u32 debug_dunit = 0; u32 odt_additional = 1; u32 *dq_map_table = NULL; @@ -97,36 +99,9 @@ static int odt_test(u32 dev_num, enum hws_algo_type algo_type); #endif int adll_calibration(u32 dev_num, enum hws_access_type access_type, - u32 if_id, enum hws_ddr_freq frequency); + u32 if_id, enum mv_ddr_freq frequency); static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, - u32 if_id, enum hws_ddr_freq frequency); - -static struct page_element page_tbl[] = { - /* - * 8bits 16 bits - * page-size(K) page-size(K) mask - */ - { 1, 2, 2}, - /* 512M */ - { 1, 2, 3}, - /* 1G */ - { 1, 2, 0}, - /* 2G */ - { 1, 2, 4}, - /* 4G */ - { 2, 2, 5}, - /* 8G */ - {0, 0, 0}, /* TODO: placeholder for 16-Mbit die capacity */ - {0, 0, 0}, /* TODO: placeholder for 32-Mbit die capacity */ - {0, 0, 0}, /* TODO: placeholder for 12-Mbit die capacity */ - {0, 0, 0} /* TODO: placeholder for 24-Mbit die capacity */ - -}; - -struct page_element *mv_ddr_page_tbl_get(void) -{ - return &page_tbl[0]; -} + u32 if_id, enum mv_ddr_freq frequency); static u8 mem_size_config[MV_DDR_DIE_CAP_LAST] = { 0x2, /* 512Mbit */ @@ -204,7 +179,52 @@ struct mv_ddr_mr_data mr_data[] = { {MRS3_CMD, MR3_REG} }; -static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id); +/* inverse pads */ +static int ddr3_tip_pad_inv(void) +{ + u32 sphy, data; + u32 sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); + u32 ck_swap_ctrl_sphy; + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + + for (sphy = 0; sphy < sphy_max; sphy++) { + VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); + if (tm->interface_params[0]. + as_bus_params[sphy].is_dqs_swap == 1) { + data = (INVERT_PAD << INV_PAD4_OFFS | + INVERT_PAD << INV_PAD5_OFFS); + /* dqs swap */ + ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST, + 0, sphy, + DDR_PHY_DATA, + PHY_CTRL_PHY_REG, + data, data); + } + + if (tm->interface_params[0].as_bus_params[sphy]. + is_ck_swap == 1 && sphy == 0) { +/* TODO: move this code to per platform one */ +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) + /* clock swap for both cs0 and cs1 */ + data = (INVERT_PAD << INV_PAD2_OFFS | + INVERT_PAD << INV_PAD6_OFFS | + INVERT_PAD << INV_PAD4_OFFS | + INVERT_PAD << INV_PAD5_OFFS); + ck_swap_ctrl_sphy = CK_SWAP_CTRL_PHY_NUM; + ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST, + 0, ck_swap_ctrl_sphy, + DDR_PHY_CONTROL, + PHY_CTRL_PHY_REG, + data, data); +#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */ +#pragma message "unknown platform to configure ddr clock swap" +#endif + } + } + + return MV_OK; +} + static int ddr3_tip_rank_control(u32 dev_num, u32 if_id); /* @@ -244,6 +264,7 @@ int ddr3_tip_tune_training_params(u32 dev_num, if (params->g_rtt_park != PARAM_UNDEFINED) g_rtt_park = params->g_rtt_park; + DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data, @@ -308,44 +329,6 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) return MV_OK; } -/* - * Calculate number of CS - */ -int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num) -{ - u32 cs; - u32 bus_cnt; - u32 cs_count; - u32 cs_bitmask; - u32 curr_cs_num = 0; - u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { - VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); - cs_count = 0; - cs_bitmask = tm->interface_params[if_id]. - as_bus_params[bus_cnt].cs_bitmask; - for (cs = 0; cs < MAX_CS_NUM; cs++) { - if ((cs_bitmask >> cs) & 1) - cs_count++; - } - - if (curr_cs_num == 0) { - curr_cs_num = cs_count; - } else if (cs_count != curr_cs_num) { - DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, - ("CS number is different per bus (IF %d BUS %d cs_num %d curr_cs_num %d)\n", - if_id, bus_cnt, cs_count, - curr_cs_num)); - return MV_NOT_SUPPORTED; - } - } - *cs_num = curr_cs_num; - - return MV_OK; -} - /* * Init Controller Flow */ @@ -356,7 +339,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ u32 t_ckclk = 0, t_wr = 0, t2t = 0; u32 data_value = 0, cs_cnt = 0, mem_mask = 0, bus_index = 0; - enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N; + enum mv_ddr_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N; u32 cs_mask = 0; u32 cl_value = 0, cwl_val = 0; u32 bus_cnt = 0, adll_tap = 0; @@ -364,8 +347,8 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ u32 data_read[MAX_INTERFACE_NUM]; u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - enum hws_ddr_freq freq = tm->interface_params[0].memory_freq; enum mv_ddr_timing timing; + enum mv_ddr_freq freq = tm->interface_params[0].memory_freq; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n", @@ -403,7 +386,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ speed_bin_index; /* t_ckclk is external clock */ - t_ckclk = (MEGA / freq_val[freq]); + t_ckclk = (MEGA / mv_ddr_freq_get(freq)); if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num)) data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26); @@ -508,7 +491,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ * configure them both: The Bust_width it\92s the * Memory Bus width \96 x8 or x16 */ - for (cs_cnt = 0; cs_cnt < NUM_OF_CS; cs_cnt++) { + for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) { ddr3_tip_configure_cs(dev_num, if_id, cs_cnt, ((cs_mask & (1 << cs_cnt)) ? 1 : 0)); @@ -534,7 +517,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ ("cl_value 0x%x cwl_val 0x%x\n", cl_value, cwl_val)); - t_wr = time_to_nclk(speed_bin_table + t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get (speed_bin_index, SPEED_BIN_TWR), t_ckclk); @@ -612,8 +595,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* calculate number of CS (per interface) */ - CHECK_STATUS(calc_cs_num - (dev_num, if_id, &cs_num)); + cs_num = mv_ddr_cs_num_get(); t2t = (cs_num == 1) ? 0 : 1; } @@ -666,9 +648,8 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id)); - if (init_cntr_prm->do_mrs_phy) { - CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id)); - } + if (init_cntr_prm->do_mrs_phy) + ddr3_tip_pad_inv(); /* Pad calibration control - disable */ CHECK_STATUS(ddr3_tip_if_write @@ -682,7 +663,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ if (delay_enable != 0) { - adll_tap = MEGA / (freq_val[freq] * 64); + adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64); ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); } @@ -787,48 +768,6 @@ static int ddr3_tip_rank_control(u32 dev_num, u32 if_id) return ddr3_tip_rev3_rank_control(dev_num, if_id); } -/* - * PAD Inverse Flow - */ -static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id) -{ - u32 bus_cnt, data_value, ck_swap_pup_ctrl; - u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { - VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); - if (tm->interface_params[if_id]. - as_bus_params[bus_cnt].is_dqs_swap == 1) { - /* dqs swap */ - ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST, - if_id, bus_cnt, - DDR_PHY_DATA, - PHY_CTRL_PHY_REG, 0xc0, - 0xc0); - } - - if (tm->interface_params[if_id]. - as_bus_params[bus_cnt].is_ck_swap == 1) { - if (bus_cnt <= 1) - data_value = 0x5 << 2; - else - data_value = 0xa << 2; - - /* mask equals data */ - /* ck swap pup is only control pup #0 ! */ - ck_swap_pup_ctrl = 0; - ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST, - if_id, ck_swap_pup_ctrl, - DDR_PHY_CONTROL, - PHY_CTRL_PHY_REG, - data_value, data_value); - } - } - - return MV_OK; -} - /* * Algorithm Parameters Validation */ @@ -1182,7 +1121,7 @@ int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type * ADLL Calibration */ int adll_calibration(u32 dev_num, enum hws_access_type access_type, - u32 if_id, enum hws_ddr_freq frequency) + u32 if_id, enum mv_ddr_freq frequency) { struct hws_tip_freq_config_info freq_config_info; u32 bus_cnt = 0; @@ -1229,7 +1168,7 @@ int adll_calibration(u32 dev_num, enum hws_access_type access_type, CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, 0, (0x80000000 | 0x40000000))); - mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); + mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)); CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000), (0x80000000 | 0x40000000))); @@ -1255,7 +1194,7 @@ int adll_calibration(u32 dev_num, enum hws_access_type access_type, } int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, - u32 if_id, enum hws_ddr_freq frequency) + u32 if_id, enum mv_ddr_freq frequency) { u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, bus_cnt = 0, t_wr = 0, t_ckclk = 0, @@ -1263,7 +1202,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 end_if, start_if; u32 bus_index = 0; int is_dll_off = 0; - enum hws_speed_bin speed_bin_index = 0; + enum mv_ddr_speed_bin speed_bin_index = 0; struct hws_tip_freq_config_info freq_config_info; enum hws_result *flow_result = training_result[training_stage]; u32 adll_tap = 0; @@ -1274,12 +1213,13 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); unsigned int tclk; enum mv_ddr_timing timing = tm->interface_params[if_id].timing; + u32 freq = mv_ddr_freq_get(frequency); DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("dev %d access %d IF %d freq %d\n", dev_num, access_type, if_id, frequency)); - if (frequency == DDR_FREQ_LOW_FREQ) + if (frequency == MV_DDR_FREQ_LOW_FREQ) is_dll_off = 1; if (access_type == ACCESS_TYPE_MULTICAST) { start_if = 0; @@ -1318,7 +1258,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, cwl_value = tm->interface_params[if_id].cas_wl; } else if (tm->cfg_src == MV_DDR_CFG_SPD) { - tclk = 1000000 / freq_val[frequency]; + tclk = 1000000 / freq; cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); if (cl_value == 0) { printf("mv_ddr: unsupported cas latency value found\n"); @@ -1330,11 +1270,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, return MV_FAIL; } } else { - cl_value = - cas_latency_table[speed_bin_index].cl_val[frequency]; - cwl_value = - cas_write_latency_table[speed_bin_index]. - cl_val[frequency]; + cl_value = mv_ddr_cl_val_get(speed_bin_index, frequency); + cwl_value = mv_ddr_cwl_val_get(speed_bin_index, frequency); } DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, @@ -1342,11 +1279,9 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, dev_num, access_type, if_id, frequency, speed_bin_index)); - for (cnt_id = 0; cnt_id < DDR_FREQ_LAST; cnt_id++) { + for (cnt_id = 0; cnt_id < MV_DDR_FREQ_LAST; cnt_id++) { DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, - ("%d ", - cas_latency_table[speed_bin_index]. - cl_val[cnt_id])); + ("%d ", mv_ddr_cl_val_get(speed_bin_index, cnt_id))); } DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n")); @@ -1420,7 +1355,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* Calculate number of CS per interface */ - CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); + cs_num = mv_ddr_cs_num_get(); t2t = (cs_num == 1) ? 0 : 1; } @@ -1455,8 +1390,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, (dev_num, access_type, if_id, DFS_REG, (cwl_mask_table[cwl_value] << 12), 0x7000)); - t_ckclk = (MEGA / freq_val[frequency]); - t_wr = time_to_nclk(speed_bin_table + t_ckclk = (MEGA / freq); + t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get (speed_bin_index, SPEED_BIN_TWR), t_ckclk); @@ -1517,7 +1452,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, 0, (0x80000000 | 0x40000000))); - mdelay(100 / (freq_val[frequency] / freq_val[DDR_FREQ_LOW_FREQ])); + mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ))); CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000), @@ -1544,7 +1479,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, /* Set proper timing params before existing Self-Refresh */ ddr3_tip_set_timing(dev_num, access_type, if_id, frequency); if (delay_enable != 0) { - adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq_val[frequency] * 64)); + adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64)); ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); } @@ -1682,7 +1617,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, * Set Timing values for training */ static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, - u32 if_id, enum hws_ddr_freq frequency) + u32 if_id, enum mv_ddr_freq frequency) { u32 t_ckclk = 0, t_ras = 0; u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0, @@ -1690,66 +1625,63 @@ static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, t_r2w_w2r = 0x3, t_r2w_w2r_high = 0x1, t_w2w = 0x3; u32 refresh_interval_cnt, t_hclk, t_refi, t_faw, t_pd, t_xpdll; u32 val = 0, page_size = 0, mask = 0; - enum hws_speed_bin speed_bin_index; + enum mv_ddr_speed_bin speed_bin_index; enum mv_ddr_die_capacity memory_size = MV_DDR_DIE_CAP_2GBIT; struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - struct page_element *page_param = mv_ddr_page_tbl_get(); + u32 freq = mv_ddr_freq_get(frequency); speed_bin_index = tm->interface_params[if_id].speed_bin_index; memory_size = tm->interface_params[if_id].memory_size; - page_size = - (tm->interface_params[if_id].bus_width == - MV_DDR_DEV_WIDTH_8BIT) ? page_param[memory_size]. - page_size_8bit : page_param[memory_size].page_size_16bit; - t_ckclk = (MEGA / freq_val[frequency]); + page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size); + t_ckclk = (MEGA / freq); /* HCLK in[ps] */ - t_hclk = MEGA / (freq_val[frequency] / config_func_info[dev_num].tip_get_clock_ratio(frequency)); + t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency)); t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW; t_refi *= 1000; /* psec */ refresh_interval_cnt = t_refi / t_hclk; /* no units */ if (page_size == 1) { - t_faw = speed_bin_table(speed_bin_index, SPEED_BIN_TFAW1K); + t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW1K); t_faw = time_to_nclk(t_faw, t_ckclk); t_faw = GET_MAX_VALUE(20, t_faw); } else { /* page size =2, we do not support page size 0.5k */ - t_faw = speed_bin_table(speed_bin_index, SPEED_BIN_TFAW2K); + t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW2K); t_faw = time_to_nclk(t_faw, t_ckclk); t_faw = GET_MAX_VALUE(28, t_faw); } - t_pd = GET_MAX_VALUE(t_ckclk * 3, speed_bin_table(speed_bin_index, SPEED_BIN_TPD)); + t_pd = GET_MAX_VALUE(t_ckclk * 3, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TPD)); t_pd = time_to_nclk(t_pd, t_ckclk); - t_xpdll = GET_MAX_VALUE(t_ckclk * 10, speed_bin_table(speed_bin_index, SPEED_BIN_TXPDLL)); + t_xpdll = GET_MAX_VALUE(t_ckclk * 10, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TXPDLL)); t_xpdll = time_to_nclk(t_xpdll, t_ckclk); - t_rrd = (page_size == 1) ? speed_bin_table(speed_bin_index, + t_rrd = (page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD1K) : - speed_bin_table(speed_bin_index, SPEED_BIN_TRRD2K); + mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD2K); t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd); - t_rtp = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index, + t_rtp = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRTP)); t_mod = GET_MAX_VALUE(t_ckclk * 12, 15000); - t_wtr = GET_MAX_VALUE(t_ckclk * 4, speed_bin_table(speed_bin_index, + t_wtr = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TWTR)); - t_ras = time_to_nclk(speed_bin_table(speed_bin_index, + t_ras = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRAS), t_ckclk); - t_rcd = time_to_nclk(speed_bin_table(speed_bin_index, + t_rcd = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRCD), t_ckclk); - t_rp = time_to_nclk(speed_bin_table(speed_bin_index, + t_rp = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRP), t_ckclk); - t_wr = time_to_nclk(speed_bin_table(speed_bin_index, + t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TWR), t_ckclk); t_wtr = time_to_nclk(t_wtr, t_ckclk); t_rrd = time_to_nclk(t_rrd, t_ckclk); t_rtp = time_to_nclk(t_rtp, t_ckclk); - t_rfc = time_to_nclk(rfc_table[memory_size] * 1000, t_ckclk); + t_rfc = time_to_nclk(mv_ddr_rfc_get(memory_size) * 1000, t_ckclk); t_mod = time_to_nclk(t_mod, t_ckclk); /* SDRAM Timing Low */ @@ -1826,68 +1758,6 @@ static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, } -/* - * Mode Read - */ -int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info) -{ - u32 ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - MR0_REG, mode_info->reg_mr0, MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - MR1_REG, mode_info->reg_mr1, MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - MR2_REG, mode_info->reg_mr2, MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - MR3_REG, mode_info->reg_mr2, MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - RD_DATA_SMPL_DLYS_REG, mode_info->read_data_sample, - MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, - RD_DATA_RDY_DLYS_REG, mode_info->read_data_ready, - MASK_ALL_BITS); - if (ret != MV_OK) - return ret; - - return MV_OK; -} - -/* - * Get first active IF - */ -int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, - u32 *interface_id) -{ - u32 if_id; - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - - for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { - VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); - if (interface_mask & (1 << if_id)) { - *interface_id = if_id; - break; - } - } - - return MV_OK; -} - /* * Write CS Result */ @@ -2139,9 +2009,10 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) int ret = MV_OK; int adll_bypass_flag = 0; u32 if_id; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - enum hws_ddr_freq freq = tm->interface_params[0].memory_freq; + enum mv_ddr_freq freq = tm->interface_params[0].memory_freq; + unsigned int *freq_tbl = mv_ddr_freq_tbl_get(); #ifdef DDR_VIEWER_TOOL if (debug_training == DEBUG_LEVEL_TRACE) { @@ -2157,7 +2028,7 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) /* Set to 0 after each loop to avoid illegal value may be used */ effective_cs = 0; - freq_val[DDR_FREQ_LOW_FREQ] = dfs_low_freq; + freq_tbl[MV_DDR_FREQ_LOW_FREQ] = dfs_low_freq; if (is_pll_before_init != 0) { for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { @@ -2220,7 +2091,7 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("SET_LOW_FREQ_MASK_BIT %d\n", - freq_val[low_freq])); + freq_tbl[low_freq])); ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, low_freq); if (is_reg_dump != 0) @@ -2281,7 +2152,7 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) training_stage = SET_MEDIUM_FREQ; DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("SET_MEDIUM_FREQ_MASK_BIT %d\n", - freq_val[medium_freq])); + freq_tbl[medium_freq])); ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, medium_freq); @@ -2299,7 +2170,7 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) training_stage = WRITE_LEVELING; DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("WRITE_LEVELING_MASK_BIT\n")); - if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) { + if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) { ret = ddr3_tip_dynamic_write_leveling(dev_num, 0); } else { /* Use old WL */ @@ -2341,7 +2212,7 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) training_stage = READ_LEVELING; DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("READ_LEVELING_MASK_BIT\n")); - if ((rl_mid_freq_wa == 0) || (freq_val[medium_freq] == 533)) { + if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) { ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq); } else { /* Use old RL */ @@ -2417,19 +2288,13 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) training_stage = SET_TARGET_FREQ; DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("SET_TARGET_FREQ_MASK_BIT %d\n", - freq_val[tm-> + freq_tbl[tm-> interface_params[first_active_if]. memory_freq])); ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, tm->interface_params[first_active_if]. memory_freq); -#if defined(A70X0) || defined(A80X0) - if (apn806_rev_id_get() == APN806_REV_ID_A0) { - reg_write(0x6f812c, extension_avs); - reg_write(0x6f8130, nominal_avs); - } -#endif /* #if defined(A70X0) || defined(A80X0) */ if (is_reg_dump != 0) ddr3_tip_reg_dump(dev_num); if (ret != MV_OK) { @@ -2892,3 +2757,140 @@ int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr) return MV_OK; } + +/* TODO: consider to move to misl phy driver */ +enum { + MISL_PHY_DRV_OHM_30 = 0xf, + MISL_PHY_DRV_OHM_48 = 0xa, + MISL_PHY_DRV_OHM_80 = 0x6, + MISL_PHY_DRV_OHM_120 = 0x4 +}; + +enum { + MISL_PHY_ODT_OHM_60 = 0x8, + MISL_PHY_ODT_OHM_80 = 0x6, + MISL_PHY_ODT_OHM_120 = 0x4, + MISL_PHY_ODT_OHM_240 = 0x2 +}; + +static unsigned int mv_ddr_misl_phy_drv_calc(unsigned int cfg) +{ + unsigned int val; + + switch (cfg) { + case MV_DDR_OHM_30: + val = MISL_PHY_DRV_OHM_30; + break; + case MV_DDR_OHM_48: + val = MISL_PHY_DRV_OHM_48; + break; + case MV_DDR_OHM_80: + val = MISL_PHY_DRV_OHM_80; + break; + case MV_DDR_OHM_120: + val = MISL_PHY_DRV_OHM_120; + break; + default: + val = PARAM_UNDEFINED; + } + + return val; +} + +static unsigned int mv_ddr_misl_phy_odt_calc(unsigned int cfg) +{ + unsigned int val; + + switch (cfg) { + case MV_DDR_OHM_60: + val = MISL_PHY_ODT_OHM_60; + break; + case MV_DDR_OHM_80: + val = MISL_PHY_ODT_OHM_80; + break; + case MV_DDR_OHM_120: + val = MISL_PHY_ODT_OHM_120; + break; + case MV_DDR_OHM_240: + val = MISL_PHY_ODT_OHM_240; + break; + default: + val = PARAM_UNDEFINED; + } + + return val; +} + +unsigned int mv_ddr_misl_phy_drv_data_p_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int drv_data_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_p); + + if (drv_data_p == PARAM_UNDEFINED) + printf("error: %s: unsupported drv_data_p parameter found\n", __func__); + + return drv_data_p; +} + +unsigned int mv_ddr_misl_phy_drv_data_n_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int drv_data_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_n); + + if (drv_data_n == PARAM_UNDEFINED) + printf("error: %s: unsupported drv_data_n parameter found\n", __func__); + + return drv_data_n; +} + +unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int drv_ctrl_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_p); + + if (drv_ctrl_p == PARAM_UNDEFINED) + printf("error: %s: unsupported drv_ctrl_p parameter found\n", __func__); + + return drv_ctrl_p; +} + +unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int drv_ctrl_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_n); + + if (drv_ctrl_n == PARAM_UNDEFINED) + printf("error: %s: unsupported drv_ctrl_n parameter found\n", __func__); + + return drv_ctrl_n; +} + +unsigned int mv_ddr_misl_phy_odt_p_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int cs_num = mv_ddr_cs_num_get(); + unsigned int odt_p = PARAM_UNDEFINED; + + if (cs_num > 0 && cs_num <= MAX_CS_NUM) + odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]); + + if (odt_p == PARAM_UNDEFINED) + printf("error: %s: unsupported odt_p parameter found\n", __func__); + + return odt_p; +} + +unsigned int mv_ddr_misl_phy_odt_n_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int cs_num = mv_ddr_cs_num_get(); + unsigned int odt_n = PARAM_UNDEFINED; + + if (cs_num > 0 && cs_num <= MAX_CS_NUM) + odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]); + + if (odt_n == PARAM_UNDEFINED) + printf("error: %s: unsupported odt_n parameter found\n", __func__); + + return odt_n; +} diff --git a/drivers/ddr/marvell/a38x/ddr3_training_bist.c b/drivers/ddr/marvell/a38x/ddr3_training_bist.c index e29b1713f9..d388a17291 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_bist.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_bist.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_regs.h" static u32 bist_offset = 32; enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0; diff --git a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c index 03e5c9fdce..648b37ef6f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_regs.h" #define VALIDATE_WIN_LENGTH(e1, e2, maxsize) \ (((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) && \ @@ -698,6 +699,8 @@ int ddr3_tip_print_centralization_result(u32 dev_num) u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + dev_num = dev_num; + printf("Centralization Results\n"); printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n"); for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index c0089f67f2..111a8586c6 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -3,11 +3,16 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include "ddr3_init.h" +#include "ddr_ml_wrapper.h" + +#include "ddr3_training_ip_flow.h" +#include "mv_ddr_topology.h" +#include "mv_ddr_training_db.h" +#include "ddr3_training_ip_db.h" /* Device attributes structures */ -enum mv_ddr_dev_attribute ddr_dev_attributes[MAX_DEVICE_NUM][MV_ATTR_LAST]; -int ddr_dev_attr_init_done[MAX_DEVICE_NUM] = { 0 }; +enum mv_ddr_dev_attribute ddr_dev_attributes[MV_ATTR_LAST]; +int ddr_dev_attr_init_done = 0; static inline u32 pattern_table_get_killer_word16(u8 dqs, u8 index); static inline u32 pattern_table_get_sso_word(u8 sso, u8 index); @@ -20,28 +25,38 @@ static inline u32 pattern_table_get_sso_xtalk_free_word16(u8 bit, u8 index); static inline u32 pattern_table_get_isi_word(u8 index); static inline u32 pattern_table_get_isi_word16(u8 index); -/* List of allowed frequency listed in order of enum hws_ddr_freq */ -u32 freq_val[DDR_FREQ_LAST] = { - 0, /*DDR_FREQ_LOW_FREQ */ - 400, /*DDR_FREQ_400, */ - 533, /*DDR_FREQ_533, */ - 666, /*DDR_FREQ_667, */ - 800, /*DDR_FREQ_800, */ - 933, /*DDR_FREQ_933, */ - 1066, /*DDR_FREQ_1066, */ - 311, /*DDR_FREQ_311, */ - 333, /*DDR_FREQ_333, */ - 467, /*DDR_FREQ_467, */ - 850, /*DDR_FREQ_850, */ - 600, /*DDR_FREQ_600 */ - 300, /*DDR_FREQ_300 */ - 900, /*DDR_FREQ_900 */ - 360, /*DDR_FREQ_360 */ - 1000 /*DDR_FREQ_1000 */ +/* List of allowed frequency listed in order of enum mv_ddr_freq */ +static unsigned int freq_val[MV_DDR_FREQ_LAST] = { + 0, /*MV_DDR_FREQ_LOW_FREQ */ + 400, /*MV_DDR_FREQ_400, */ + 533, /*MV_DDR_FREQ_533, */ + 666, /*MV_DDR_FREQ_667, */ + 800, /*MV_DDR_FREQ_800, */ + 933, /*MV_DDR_FREQ_933, */ + 1066, /*MV_DDR_FREQ_1066, */ + 311, /*MV_DDR_FREQ_311, */ + 333, /*MV_DDR_FREQ_333, */ + 467, /*MV_DDR_FREQ_467, */ + 850, /*MV_DDR_FREQ_850, */ + 600, /*MV_DDR_FREQ_600 */ + 300, /*MV_DDR_FREQ_300 */ + 900, /*MV_DDR_FREQ_900 */ + 360, /*MV_DDR_FREQ_360 */ + 1000 /*MV_DDR_FREQ_1000 */ }; -/* Table for CL values per frequency for each speed bin index */ -struct cl_val_per_freq cas_latency_table[] = { +unsigned int *mv_ddr_freq_tbl_get(void) +{ + return &freq_val[0]; +} + +u32 mv_ddr_freq_get(enum mv_ddr_freq freq) +{ + return freq_val[freq]; +} + +/* cas latency values per frequency for each speed bin index */ +static struct mv_ddr_cl_val_per_freq cl_table[] = { /* * 400M 667M 933M 311M 467M 600M 360 * 100M 533M 800M 1066M 333M 850M 900 @@ -97,8 +112,13 @@ struct cl_val_per_freq cas_latency_table[] = { { {6, 6, 7, 9, 11, 13, 0, 6, 6, 7, 13, 9, 6, 13, 6, 13} }, }; -/* Table for CWL values per speedbin index */ -struct cl_val_per_freq cas_write_latency_table[] = { +u32 mv_ddr_cl_val_get(u32 index, u32 freq) +{ + return cl_table[index].cl_val[freq]; +} + +/* cas write latency values per frequency for each speed bin index */ +static struct mv_ddr_cl_val_per_freq cwl_table[] = { /* * 400M 667M 933M 311M 467M 600M 360 * 100M 533M 800M 1066M 333M 850M 900 @@ -154,6 +174,11 @@ struct cl_val_per_freq cas_write_latency_table[] = { { {5, 5, 6, 7, 8, 9, 0, 5, 5, 6, 9, 7, 5, 9, 5, 9} }, }; +u32 mv_ddr_cwl_val_get(u32 index, u32 freq) +{ + return cwl_table[index].cl_val[freq]; +} + u8 twr_mask_table[] = { 10, 10, @@ -213,18 +238,23 @@ u8 cwl_mask_table[] = { }; /* RFC values (in ns) */ -u16 rfc_table[] = { - 90, /* 512M */ - 110, /* 1G */ - 160, /* 2G */ - 260, /* 4G */ - 350, /* 8G */ - 0, /* TODO: placeholder for 16-Mbit dev width */ - 0, /* TODO: placeholder for 32-Mbit dev width */ - 0, /* TODO: placeholder for 12-Mbit dev width */ - 0 /* TODO: placeholder for 24-Mbit dev width */ +static unsigned int rfc_table[] = { + 90, /* 512M */ + 110, /* 1G */ + 160, /* 2G */ + 260, /* 4G */ + 350, /* 8G */ + 0, /* TODO: placeholder for 16-Mbit dev width */ + 0, /* TODO: placeholder for 32-Mbit dev width */ + 0, /* TODO: placeholder for 12-Mbit dev width */ + 0 /* TODO: placeholder for 24-Mbit dev width */ }; +u32 mv_ddr_rfc_get(u32 mem) +{ + return rfc_table[mem]; +} + u32 speed_bin_table_t_rc[] = { 50000, 52500, @@ -358,8 +388,29 @@ static u8 pattern_vref_pattern_table_map[] = { 0xfe }; +static struct mv_ddr_page_element page_tbl[] = { + /* 8-bit, 16-bit page size */ + {MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 512M */ + {MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 1G */ + {MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 2G */ + {MV_DDR_PAGE_SIZE_1K, MV_DDR_PAGE_SIZE_2K}, /* 4G */ + {MV_DDR_PAGE_SIZE_2K, MV_DDR_PAGE_SIZE_2K}, /* 8G */ + {0, 0}, /* TODO: placeholder for 16-Mbit die capacity */ + {0, 0}, /* TODO: placeholder for 32-Mbit die capacity */ + {0, 0}, /* TODO: placeholder for 12-Mbit die capacity */ + {0, 0} /* TODO: placeholder for 24-Mbit die capacity */ +}; + +u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size) +{ + if (bus_width == MV_DDR_DEV_WIDTH_8BIT) + return page_tbl[mem_size].page_size_8bit; + else + return page_tbl[mem_size].page_size_16bit; +} + /* Return speed Bin value for selected index and t* element */ -u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) +unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element) { u32 result = 0; @@ -384,19 +435,19 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) result = speed_bin_table_t_rc[index]; break; case SPEED_BIN_TRRD1K: - if (index < SPEED_BIN_DDR_800E) + if (index <= SPEED_BIN_DDR_800E) result = 10000; - else if (index < SPEED_BIN_DDR_1066G) + else if (index <= SPEED_BIN_DDR_1066G) result = 7500; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 6000; else result = 5000; break; case SPEED_BIN_TRRD2K: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 10000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 7500; else result = 6000; @@ -410,23 +461,23 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) result = 5000; break; case SPEED_BIN_TFAW1K: - if (index < SPEED_BIN_DDR_800E) + if (index <= SPEED_BIN_DDR_800E) result = 40000; - else if (index < SPEED_BIN_DDR_1066G) + else if (index <= SPEED_BIN_DDR_1066G) result = 37500; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 30000; - else if (index < SPEED_BIN_DDR_1866M) + else if (index <= SPEED_BIN_DDR_1866M) result = 27000; else result = 25000; break; case SPEED_BIN_TFAW2K: - if (index < SPEED_BIN_DDR_1066G) + if (index <= SPEED_BIN_DDR_1066G) result = 50000; - else if (index < SPEED_BIN_DDR_1333J) + else if (index <= SPEED_BIN_DDR_1333J) result = 45000; - else if (index < SPEED_BIN_DDR_1600K) + else if (index <= SPEED_BIN_DDR_1600K) result = 40000; else result = 35000; @@ -446,6 +497,9 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) case SPEED_BIN_TXPDLL: result = 24000; break; + case SPEED_BIN_TXSDLL: + result = 512; + break; default: break; } @@ -608,7 +662,7 @@ static inline u32 pattern_table_get_static_pbs_word(u8 index) u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) { - u32 pattern; + u32 pattern = 0; struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) == 0) { @@ -696,8 +750,8 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) pattern = pattern_table_get_isi_word(index); break; default: - DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Error: %s: pattern type [%d] not supported\n", - __func__, (int)type)); + printf("error: %s: unsupported pattern type [%d] found\n", + __func__, (int)type); pattern = 0; break; } @@ -779,8 +833,8 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) pattern = pattern_table_get_isi_word16(index); break; default: - DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("Error: %s: pattern type [%d] not supported\n", - __func__, (int)type)); + printf("error: %s: unsupported pattern type [%d] found\n", + __func__, (int)type); pattern = 0; break; } @@ -795,23 +849,23 @@ void ddr3_tip_dev_attr_init(u32 dev_num) u32 attr_id; for (attr_id = 0; attr_id < MV_ATTR_LAST; attr_id++) - ddr_dev_attributes[dev_num][attr_id] = 0xFF; + ddr_dev_attributes[attr_id] = 0xFF; - ddr_dev_attr_init_done[dev_num] = 1; + ddr_dev_attr_init_done = 1; } u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id) { - if (ddr_dev_attr_init_done[dev_num] == 0) + if (ddr_dev_attr_init_done == 0) ddr3_tip_dev_attr_init(dev_num); - return ddr_dev_attributes[dev_num][attr_id]; + return ddr_dev_attributes[attr_id]; } void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value) { - if (ddr_dev_attr_init_done[dev_num] == 0) + if (ddr_dev_attr_init_done == 0) ddr3_tip_dev_attr_init(dev_num); - ddr_dev_attributes[dev_num][attr_id] = value; + ddr_dev_attributes[attr_id] = value; } diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index 6b8aae83d7..db0f8ad7fb 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_regs.h" #define VREF_INITIAL_STEP 3 #define VREF_SECOND_STEP 1 diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h index 531103c1ab..056c21497c 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h @@ -6,12 +6,8 @@ #ifndef _DDR3_TRAINING_IP_H_ #define _DDR3_TRAINING_IP_H_ -#include "ddr3_training_ip_def.h" #include "ddr_topology_def.h" -#include "ddr_training_ip_db.h" -#define MAX_CS_NUM 4 -#define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM) #define TIP_ENG_LOCK 0x02000000 #define TIP_TX_DLL_RANGE_MAX 64 @@ -112,40 +108,11 @@ struct pattern_info { u8 pattern_len; }; -/* CL value for each frequency */ -struct cl_val_per_freq { - u8 cl_val[DDR_FREQ_LAST]; -}; - struct cs_element { u8 cs_num; u8 num_of_cs; }; -struct mode_info { - /* 32 bits representing MRS bits */ - u32 reg_mr0[MAX_INTERFACE_NUM]; - u32 reg_mr1[MAX_INTERFACE_NUM]; - u32 reg_mr2[MAX_INTERFACE_NUM]; - u32 reg_m_r3[MAX_INTERFACE_NUM]; - /* - * Each element in array represent read_data_sample register delay for - * a specific interface. - * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR - * cycles from read command until data is ready to be fetched from - * the PHY, when accessing CS. - */ - u32 read_data_sample[MAX_INTERFACE_NUM]; - /* - * Each element in array represent read_data_sample register delay for - * a specific interface. - * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay - * from read command until opening the read mask, when accessing CS. - * This field defines the delay in DDR cycles granularity. - */ - u32 read_data_ready[MAX_INTERFACE_NUM]; -}; - struct hws_tip_freq_config_info { u8 is_supported; u8 bw_per_freq; @@ -173,12 +140,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, int hws_ddr3_tip_load_topology_map(u32 dev_num, struct mv_ddr_topology_map *topology); int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); -int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info); -int hws_ddr3_tip_read_training_result(u32 dev_num, - enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]); int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); u8 ddr3_tip_get_buf_min(u8 *buf_ptr); u8 ddr3_tip_get_buf_max(u8 *buf_ptr); -uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void); -uint64_t mv_ddr_get_total_memory_size_in_bits(void); #endif /* _DDR3_TRAINING_IP_H_ */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h index 2318ceba29..2a68669f36 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h @@ -75,32 +75,6 @@ #define GET_RESULT_STATE(res) (res) #define SET_RESULT_STATE(res, state) (res = state) -#define _1K 0x00000400 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _4M 0x00400000 -#define _8M 0x00800000 -#define _16M 0x01000000 -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 -#define _4G 0x100000000 -#define _8G 0x200000000 - #define ADDR_SIZE_512MB 0x04000000 #define ADDR_SIZE_1GB 0x08000000 #define ADDR_SIZE_2GB 0x10000000 @@ -126,11 +100,6 @@ enum hws_search_dir { HWS_SEARCH_DIR_LIMIT }; -enum hws_page_size { - PAGE_SIZE_1K, - PAGE_SIZE_2K -}; - enum hws_operation { OPERATION_READ = 0, OPERATION_WRITE = 1 diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 334c2906fd..74417d61b4 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -4,6 +4,8 @@ */ #include "ddr3_init.h" +#include "mv_ddr_regs.h" +#include "ddr_training_ip_db.h" #define PATTERN_1 0x55555555 #define PATTERN_2 0xaaaaaaaa diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h index 8fbcff50bb..2d40e68db8 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h @@ -8,6 +8,7 @@ #include "ddr3_training_ip_def.h" #include "ddr3_training_ip_flow.h" +#include "ddr3_training_ip_pbs.h" #define EDGE_1 0 #define EDGE_2 1 diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h index 6a9ef35f64..ab152cb455 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h @@ -7,71 +7,17 @@ #define _DDR3_TRAINING_IP_FLOW_H_ #include "ddr3_training_ip.h" -#include "ddr3_training_ip_pbs.h" -#include "mv_ddr_regs.h" +#include "ddr3_training_ip_db.h" #define KILLER_PATTERN_LENGTH 32 #define EXT_ACCESS_BURST_LENGTH 8 -#define IS_ACTIVE(mask, id) \ - ((mask) & (1 << (id))) - -#define VALIDATE_ACTIVE(mask, id) \ - { \ - if (IS_ACTIVE(mask, id) == 0) \ - continue; \ - } - -#define IS_IF_ACTIVE(if_mask, if_id) \ - ((if_mask) & (1 << (if_id))) - -#define VALIDATE_IF_ACTIVE(mask, id) \ - { \ - if (IS_IF_ACTIVE(mask, id) == 0) \ - continue; \ - } - -#define IS_BUS_ACTIVE(if_mask , if_id) \ - (((if_mask) >> (if_id)) & 1) - -#define VALIDATE_BUS_ACTIVE(mask, id) \ - { \ - if (IS_BUS_ACTIVE(mask, id) == 0) \ - continue; \ - } - -#define DDR3_IS_ECC_PUP3_MODE(if_mask) \ - (((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) - -#define DDR3_IS_ECC_PUP4_MODE(if_mask) \ - ((if_mask == BUS_MASK_32BIT_ECC || if_mask == BUS_MASK_16BIT_ECC) ? 1 : 0) - -#define DDR3_IS_16BIT_DRAM_MODE(mask) \ - ((mask == BUS_MASK_16BIT || mask == BUS_MASK_16BIT_ECC || mask == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) - -#define DDR3_IS_ECC_PUP8_MODE(if_mask) \ - ((if_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || if_mask == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) - -#define MV_DDR_IS_64BIT_DRAM_MODE(mask) \ - ((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \ - (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) - -#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \ - ((octets_per_if_num == 9/* FIXME: get from ATF */) && \ - ((mask == BUS_MASK_32BIT) || \ - (mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0) - -#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \ - (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num) || DDR3_IS_16BIT_DRAM_MODE(mask)) - #define ECC_READ_BUS_0 0 #define ECC_PHY_ACCESS_3 3 #define ECC_PHY_ACCESS_4 4 #define ECC_PHY_ACCESS_8 8 -#define MEGA 1000000 #define BUS_WIDTH_IN_BITS 8 #define MAX_POLLING_ITERATIONS 1000000 -#define NUM_OF_CS 4 #define ADLL_LENGTH 32 #define GP_RSVD0_REG 0x182e0 @@ -92,8 +38,6 @@ */ /* nsec */ -#define TREFI_LOW 7800 -#define TREFI_HIGH 3900 #define AUTO_ZQC_TIMING 15384 enum mr_number { @@ -114,20 +58,11 @@ struct write_supp_result { int is_pup_fail; }; -struct page_element { - enum hws_page_size page_size_8bit; - /* page size in 8 bits bus width */ - enum hws_page_size page_size_16bit; - /* page size in 16 bits bus width */ - u32 ui_page_mask; - /* Mask used in register */ -}; - int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, - enum hws_ddr_freq frequency, + enum mv_ddr_freq frequency, u32 *round_trip_delay_arr); int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, - enum hws_ddr_freq frequency, + enum mv_ddr_freq frequency, u32 *total_round_trip_delay_arr); int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, u32 if_id, u32 reg_addr, u32 data_value, u32 mask); @@ -149,7 +84,7 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, enum hws_ddr_phy e_phy_type, u32 reg_addr, u32 data_value); int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, - enum hws_ddr_freq memory_freq); + enum mv_ddr_freq memory_freq); int ddr3_tip_adjust_dqs(u32 dev_num); int ddr3_tip_init_controller(u32 dev_num); int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, @@ -174,22 +109,12 @@ int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, u32 tx_burst_size, u32 rx_phases, u32 delay_between_burst, u32 rd_mode, u32 cs_num, u32 addr_stress_jump, u32 single_pattern); -int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value); int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask); int ddr3_tip_write_cs_result(u32 dev_num, u32 offset); -int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id); int ddr3_tip_reset_fifo_ptr(u32 dev_num); -int ddr3_tip_read_pup_value(u32 dev_num, - u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], - int reg_addr, u32 mask); -int ddr3_tip_read_adll_value(u32 dev_num, - u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], - u32 reg_addr, u32 mask); -int ddr3_tip_write_adll_value(u32 dev_num, - u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], - u32 reg_addr); -int ddr3_tip_tune_training_params(u32 dev_num, - struct tune_train_params *params); -struct page_element *mv_ddr_page_tbl_get(void); +int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask); +int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask); +int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr); +int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params); #endif /* _DDR3_TRAINING_IP_FLOW_H_ */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h index f614d688c9..2df592e1b0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h @@ -28,15 +28,15 @@ typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)( u8 dev_num, enum hws_access_type interface_access, u32 if_id, u32 offset, u32 data, u32 mask); typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)( - u8 dev_num, enum hws_ddr_freq freq, + u8 dev_num, enum mv_ddr_freq freq, struct hws_tip_freq_config_info *freq_config_info); typedef int (*HWS_TIP_GET_DEVICE_INFO)( u8 dev_num, struct ddr3_device_info *info_ptr); typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)( u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)( - u8 dev_num, u32 if_id, enum hws_ddr_freq freq); -typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq); + u8 dev_num, u32 if_id, enum mv_ddr_freq freq); +typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq); typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)( u32 dev_num, enum hws_access_type access_type, u32 dunit_id, u32 reg_addr, u32 data, u32 mask); @@ -54,7 +54,7 @@ typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)( u32 dev_num, enum hws_algo_type algo_type); typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)( u32 dev_num, enum hws_access_type access_type, u32 if_id, - enum hws_ddr_freq frequency); + enum mv_ddr_freq frequency); typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)( u32 dev_num, struct init_cntr_param *init_cntr_prm); typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num); @@ -64,7 +64,7 @@ typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)( typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)( u32 dev_num, struct mv_ddr_topology_map *tm); typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)( - u32 dev_num, enum hws_ddr_freq frequency, + u32 dev_num, enum mv_ddr_freq frequency, enum hws_static_config_type static_config_type, u32 if_id); typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)( u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c index 6248ffc3fb..7f7df6794a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c @@ -4,6 +4,9 @@ */ #include "ddr3_init.h" +#include "mv_ddr_training_db.h" +#include "ddr_training_ip_db.h" +#include "mv_ddr_regs.h" #define WL_ITERATION_NUM 10 @@ -24,33 +27,6 @@ static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, u32 edge_offset); -u32 ddr3_tip_max_cs_get(u32 dev_num) -{ - u32 c_cs, if_id, bus_id; - static u32 max_cs; - struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); - - if (!max_cs) { - CHECK_STATUS(ddr3_tip_get_first_active_if((u8)dev_num, - tm->if_act_mask, - &if_id)); - for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) { - VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); - break; - } - - for (c_cs = 0; c_cs < NUM_OF_CS; c_cs++) { - VALIDATE_ACTIVE(tm-> - interface_params[if_id].as_bus_params[bus_id]. - cs_bitmask, c_cs); - max_cs++; - } - } - - return max_cs; -} - enum { PASS, FAIL @@ -61,20 +37,20 @@ Dynamic read leveling int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) { u32 data, mask; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); u32 bus_num, if_id, cl_val; - enum hws_speed_bin speed_bin_index; + enum mv_ddr_speed_bin speed_bin_index; /* save current CS value */ u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; int is_any_pup_fail = 0; u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 }; - u8 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; + u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map(); u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++) + for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) for (bus_num = 0; bus_num < MAX_BUS_NUM; bus_num++) for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) rl_values[effective_cs][bus_num][if_id] = 0; @@ -143,8 +119,7 @@ int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); speed_bin_index = tm->interface_params[if_id].speed_bin_index; - cl_val = - cas_latency_table[speed_bin_index].cl_val[freq]; + cl_val = mv_ddr_cl_val_get(speed_bin_index, freq); data = (cl_val << 17) | (0x3 << 25); mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25); CHECK_STATUS(ddr3_tip_if_write @@ -340,7 +315,7 @@ int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num) { u32 c_cs, if_id, cs_mask = 0; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); /* @@ -381,7 +356,7 @@ int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num) int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num) { u32 c_cs, if_id, cs_mask = 0; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); /* @@ -426,7 +401,7 @@ int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 freq) u32 curr_numb, curr_min_delay; int adll_array[3] = { 0, -0xa, 0x14 }; u32 phyreg3_arr[MAX_INTERFACE_NUM][MAX_BUS_NUM]; - enum hws_speed_bin speed_bin_index; + enum mv_ddr_speed_bin speed_bin_index; int is_any_pup_fail = 0; int break_loop = 0; u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */ @@ -516,8 +491,7 @@ int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 freq) VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); speed_bin_index = tm->interface_params[if_id].speed_bin_index; - cl_val = - cas_latency_table[speed_bin_index].cl_val[freq]; + cl_val = mv_ddr_cl_val_get(speed_bin_index, freq); data = (cl_val << 17) | (0x3 << 25); mask = (0xff << 9) | (0x1f << 17) | (0x3 << 25); CHECK_STATUS(ddr3_tip_if_write @@ -839,10 +813,10 @@ int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove) u32 res_values[MAX_INTERFACE_NUM * MAX_BUS_NUM] = { 0 }; u32 test_res = 0; /* 0 - success for all pup */ u32 data_read[MAX_INTERFACE_NUM]; - u8 wl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM]; + u8 wl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; u16 *mask_results_pup_reg_map = ddr3_tip_get_mask_results_pup_reg_map(); u32 cs_mask0[MAX_INTERFACE_NUM] = { 0 }; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); @@ -1694,9 +1668,11 @@ enum rl_dqs_burst_state { RL_INSIDE, RL_BEHIND }; + + int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) { - enum rl_dqs_burst_state rl_state[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; + enum rl_dqs_burst_state rl_state[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; enum hws_ddr_phy subphy_type = DDR_PHY_DATA; struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); int cl_val = tm->interface_params[0].cas_l; @@ -1707,17 +1683,18 @@ int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) int init_pass_lock_num; int phase_delta; int min_phase, max_phase; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); - u32 rl_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; - u32 rl_min_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; - u32 rl_max_values[NUM_OF_CS][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; - u32 rl_val, rl_min_val[NUM_OF_CS], rl_max_val[NUM_OF_CS]; + unsigned int max_cs = mv_ddr_cs_num_get(); + u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; + u32 rl_min_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; + u32 rl_max_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; + u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; u32 reg_val_low, reg_val_high; - u32 reg_val, reg_mask; + u32 reg_val, reg_mask; uintptr_t test_addr = TEST_ADDR; + /* initialization */ - if (ddr3_if_ecc_enabled()) { + if (mv_ddr_is_ecc_ena()) { ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_SW_2_REG, ®_val, MASK_ALL_BITS); reg_mask = (TRAINING_ECC_MUX_MASK << TRAINING_ECC_MUX_OFFS) | @@ -1753,6 +1730,7 @@ int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) /* search for dqs edges per subphy */ if_id = 0; for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { + pass_lock_num = init_pass_lock_num; ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, ODPG_DATA_CTRL_REG, effective_cs << ODPG_DATA_CS_OFFS, @@ -1972,6 +1950,7 @@ int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) CHECK_STATUS(ddr3_tip_write_additional_odt_setting(dev_num, if_id)); } + /* reset read fifo assertion */ ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, if_id, SDRAM_CFG_REG, DATA_PUP_RD_RESET_ENA << DATA_PUP_RD_RESET_OFFS, diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.h b/drivers/ddr/marvell/a38x/ddr3_training_leveling.h index 96d945a33d..6719fb83f5 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.h @@ -11,6 +11,5 @@ int ddr3_tip_print_wl_supp_result(u32 dev_num); int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, u32 *cs_mask); -u32 ddr3_tip_max_cs_get(u32 dev_num); #endif /* _DDR3_TRAINING_LEVELING_H_ */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c index 0511026afb..b7dfebd93c 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_pbs.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_pbs.c @@ -4,6 +4,9 @@ */ #include "ddr3_init.h" +#include "mv_ddr_training_db.h" +#include "mv_ddr_common.h" +#include "mv_ddr_regs.h" #define TYPICAL_PBS_VALUE 12 @@ -33,7 +36,7 @@ static u8 pup_state[MAX_INTERFACE_NUM][MAX_BUS_NUM]; int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode) { u32 res0[MAX_INTERFACE_NUM]; - int adll_tap = MEGA / freq_val[medium_freq] / 64; + int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64; int pad_num = 0; enum hws_search_dir search_dir = (pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH; @@ -921,7 +924,7 @@ int ddr3_tip_pbs_tx(u32 uidev_num) int ddr3_tip_print_all_pbs_result(u32 dev_num) { u32 curr_cs; - u32 max_cs = ddr3_tip_max_cs_get(dev_num); + unsigned int max_cs = mv_ddr_cs_num_get(); for (curr_cs = 0; curr_cs < max_cs; curr_cs++) { ddr3_tip_print_pbs_result(dev_num, curr_cs, PBS_RX_MODE); diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 812224909a..e6fe8a0428 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -7,16 +7,13 @@ #define _DDR_TOPOLOGY_DEF_H #include "ddr3_training_ip_def.h" -#include "ddr3_topology_def.h" - -#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) -#include "mv_ddr_plat.h" -#endif - #include "mv_ddr_topology.h" #include "mv_ddr_spd.h" #include "ddr3_logging_def.h" +#define MV_DDR_MAX_BUS_NUM 9 +#define MV_DDR_MAX_IFACE_NUM 1 + struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -36,10 +33,10 @@ struct bus_params { struct if_params { /* bus configuration */ - struct bus_params as_bus_params[MAX_BUS_NUM]; + struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM]; /* Speed Bin Table */ - enum hws_speed_bin speed_bin_index; + enum mv_ddr_speed_bin speed_bin_index; /* sdram device width */ enum mv_ddr_dev_width bus_width; @@ -48,7 +45,7 @@ struct if_params { enum mv_ddr_die_capacity memory_size; /* The DDR frequency for each interfaces */ - enum hws_ddr_freq memory_freq; + enum mv_ddr_freq memory_freq; /* * delay CAS Write Latency @@ -69,6 +66,37 @@ struct if_params { enum mv_ddr_timing timing; }; +/* memory electrical configuration */ +struct mv_ddr_mem_edata { + enum mv_ddr_rtt_nom_park_evalue rtt_nom; + enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM]; + enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM]; + enum mv_ddr_dic_evalue dic; +}; + +/* phy electrical configuration */ +struct mv_ddr_phy_edata { + enum mv_ddr_ohm_evalue drv_data_p; + enum mv_ddr_ohm_evalue drv_data_n; + enum mv_ddr_ohm_evalue drv_ctrl_p; + enum mv_ddr_ohm_evalue drv_ctrl_n; + enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM]; + enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM]; +}; + +/* mac electrical configuration */ +struct mv_ddr_mac_edata { + enum mv_ddr_odt_cfg_evalue odt_cfg_pat; + enum mv_ddr_odt_cfg_evalue odt_cfg_wr; + enum mv_ddr_odt_cfg_evalue odt_cfg_rd; +}; + +struct mv_ddr_edata { + struct mv_ddr_mem_edata mem_edata; + struct mv_ddr_phy_edata phy_edata; + struct mv_ddr_mac_edata mac_edata; +}; + struct mv_ddr_topology_map { /* debug level configuration */ enum mv_ddr_debug_level debug_level; @@ -77,7 +105,7 @@ struct mv_ddr_topology_map { u8 if_act_mask; /* Controller configuration per interface */ - struct if_params interface_params[MAX_INTERFACE_NUM]; + struct if_params interface_params[MV_DDR_MAX_IFACE_NUM]; /* Bit mask for active buses */ u16 bus_act_mask; @@ -90,8 +118,67 @@ struct mv_ddr_topology_map { /* timing parameters */ unsigned int timing_data[MV_DDR_TDATA_LAST]; + + /* electrical configuration */ + struct mv_ddr_edata edata; + + /* electrical parameters */ + unsigned int electrical_data[MV_DDR_EDATA_LAST]; }; +enum mv_ddr_iface_mode { + MV_DDR_RAR_ENA, + MV_DDR_RAR_DIS, +}; + +enum mv_ddr_iface_state { + MV_DDR_IFACE_NRDY, /* not ready */ + MV_DDR_IFACE_INIT, /* init'd */ + MV_DDR_IFACE_RDY, /* ready */ + MV_DDR_IFACE_DNE /* does not exist */ +}; + +enum mv_ddr_validation { + MV_DDR_VAL_DIS, + MV_DDR_VAL_RX, + MV_DDR_VAL_TX, + MV_DDR_VAL_RX_TX +}; + +struct mv_ddr_iface { + /* base addr of ap ddr interface belongs to */ + unsigned int ap_base; + + /* ddr interface id */ + unsigned int id; + + /* ddr interface state */ + enum mv_ddr_iface_state state; + + /* ddr interface mode (rar enabled/disabled) */ + enum mv_ddr_iface_mode iface_mode; + + /* ddr interface base address */ + unsigned long long iface_base_addr; + + /* ddr interface size - ddr flow will update this parameter */ + unsigned long long iface_byte_size; + + /* ddr i2c spd data address */ + unsigned int spd_data_addr; + + /* ddr i2c spd page 0 select address */ + unsigned int spd_page_sel_addr; + + /* ddr interface validation mode */ + enum mv_ddr_validation validation; + + /* ddr interface topology map */ + struct mv_ddr_topology_map tm; +}; + +struct mv_ddr_iface *mv_ddr_iface_get(void); + /* DDR3 training global configuration parameters */ struct tune_train_params { u32 ck_delay; diff --git a/drivers/ddr/marvell/a38x/ddr_training_ip_db.h b/drivers/ddr/marvell/a38x/ddr_training_ip_db.h index e7de5aef0c..f1b4d8efc0 100644 --- a/drivers/ddr/marvell/a38x/ddr_training_ip_db.h +++ b/drivers/ddr/marvell/a38x/ddr_training_ip_db.h @@ -6,10 +6,8 @@ #ifndef _DDR_TRAINING_IP_DB_H_ #define _DDR_TRAINING_IP_DB_H_ -#include "ddr_topology_def.h" #include "ddr3_training_ip_db.h" -u32 speed_bin_table(u8 index, enum speed_bin_table_elements element); u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index); #endif /* _DDR3_TRAINING_IP_DB_H_ */ diff --git a/drivers/ddr/marvell/a38x/dram_if.h b/drivers/ddr/marvell/a38x/dram_if.h new file mode 100644 index 0000000000..4d0846489b --- /dev/null +++ b/drivers/ddr/marvell/a38x/dram_if.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Marvell International Ltd. + */ + +#ifndef _DRAM_IF_H_ +#define _DRAM_IF_H_ + +/* TODO: update atf to this new prototype */ +int dram_init(void); +void dram_mmap_config(void); +unsigned long long dram_iface_mem_sz_get(void); +#endif /* _DRAM_IF_H_ */ diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c index 2b49b77f73..cc6234fd40 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c @@ -1,3 +1,3 @@ // SPDX-License-Identifier: GPL-2.0 const char mv_ddr_build_message[] = ""; -const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4"; +const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2"; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_common.h b/drivers/ddr/marvell/a38x/mv_ddr_common.h index c71ff442ed..321a390c0d 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_common.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_common.h @@ -9,10 +9,44 @@ extern const char mv_ddr_build_message[]; extern const char mv_ddr_version_string[]; -#define MV_DDR_NUM_BITS_IN_BYTE 8 -#define MV_DDR_MEGA_BITS (1024 * 1024) +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 +#define _4G 0x100000000 +#define _8G 0x200000000 +#define _16G 0x400000000 +#define _32G 0x800000000 +#define _64G 0x1000000000 +#define _128G 0x2000000000 + +#define MEGA 1000000 +#define MV_DDR_MEGABYTE (1024 * 1024) #define MV_DDR_32_BITS_MASK 0xffffffff +#define GET_MAX_VALUE(x, y) \ + (((x) > (y)) ? (x) : (y)) + +void mv_ddr_ver_print(void); unsigned int ceil_div(unsigned int x, unsigned int y); unsigned int time_to_nclk(unsigned int t, unsigned int tclk); int round_div(unsigned int dividend, unsigned int divisor, unsigned int *quotient); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 2f318cb9ea..cc7942d0ba 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -4,7 +4,8 @@ */ #include "ddr3_init.h" - +#include "mv_ddr_training_db.h" +#include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" #define DDR_INTERFACES_NUM 1 @@ -58,42 +59,42 @@ static struct dlb_config *sys_env_dlb_config_ptr_get(void) return &ddr3_dlb_config_table[0]; } -static u8 a38x_bw_per_freq[DDR_FREQ_LAST] = { - 0x3, /* DDR_FREQ_100 */ - 0x4, /* DDR_FREQ_400 */ - 0x4, /* DDR_FREQ_533 */ - 0x5, /* DDR_FREQ_667 */ - 0x5, /* DDR_FREQ_800 */ - 0x5, /* DDR_FREQ_933 */ - 0x5, /* DDR_FREQ_1066 */ - 0x3, /* DDR_FREQ_311 */ - 0x3, /* DDR_FREQ_333 */ - 0x4, /* DDR_FREQ_467 */ - 0x5, /* DDR_FREQ_850 */ - 0x5, /* DDR_FREQ_600 */ - 0x3, /* DDR_FREQ_300 */ - 0x5, /* DDR_FREQ_900 */ - 0x3, /* DDR_FREQ_360 */ - 0x5 /* DDR_FREQ_1000 */ +static u8 a38x_bw_per_freq[MV_DDR_FREQ_LAST] = { + 0x3, /* MV_DDR_FREQ_100 */ + 0x4, /* MV_DDR_FREQ_400 */ + 0x4, /* MV_DDR_FREQ_533 */ + 0x5, /* MV_DDR_FREQ_667 */ + 0x5, /* MV_DDR_FREQ_800 */ + 0x5, /* MV_DDR_FREQ_933 */ + 0x5, /* MV_DDR_FREQ_1066 */ + 0x3, /* MV_DDR_FREQ_311 */ + 0x3, /* MV_DDR_FREQ_333 */ + 0x4, /* MV_DDR_FREQ_467 */ + 0x5, /* MV_DDR_FREQ_850 */ + 0x5, /* MV_DDR_FREQ_600 */ + 0x3, /* MV_DDR_FREQ_300 */ + 0x5, /* MV_DDR_FREQ_900 */ + 0x3, /* MV_DDR_FREQ_360 */ + 0x5 /* MV_DDR_FREQ_1000 */ }; -static u8 a38x_rate_per_freq[DDR_FREQ_LAST] = { - 0x1, /* DDR_FREQ_100 */ - 0x2, /* DDR_FREQ_400 */ - 0x2, /* DDR_FREQ_533 */ - 0x2, /* DDR_FREQ_667 */ - 0x2, /* DDR_FREQ_800 */ - 0x3, /* DDR_FREQ_933 */ - 0x3, /* DDR_FREQ_1066 */ - 0x1, /* DDR_FREQ_311 */ - 0x1, /* DDR_FREQ_333 */ - 0x2, /* DDR_FREQ_467 */ - 0x2, /* DDR_FREQ_850 */ - 0x2, /* DDR_FREQ_600 */ - 0x1, /* DDR_FREQ_300 */ - 0x2, /* DDR_FREQ_900 */ - 0x1, /* DDR_FREQ_360 */ - 0x2 /* DDR_FREQ_1000 */ +static u8 a38x_rate_per_freq[MV_DDR_FREQ_LAST] = { + 0x1, /* MV_DDR_FREQ_100 */ + 0x2, /* MV_DDR_FREQ_400 */ + 0x2, /* MV_DDR_FREQ_533 */ + 0x2, /* MV_DDR_FREQ_667 */ + 0x2, /* MV_DDR_FREQ_800 */ + 0x3, /* MV_DDR_FREQ_933 */ + 0x3, /* MV_DDR_FREQ_1066 */ + 0x1, /* MV_DDR_FREQ_311 */ + 0x1, /* MV_DDR_FREQ_333 */ + 0x2, /* MV_DDR_FREQ_467 */ + 0x2, /* MV_DDR_FREQ_850 */ + 0x2, /* MV_DDR_FREQ_600 */ + 0x1, /* MV_DDR_FREQ_300 */ + 0x2, /* MV_DDR_FREQ_900 */ + 0x1, /* MV_DDR_FREQ_360 */ + 0x2 /* MV_DDR_FREQ_1000 */ }; static u16 a38x_vco_freq_per_sar_ref_clk_25_mhz[] = { @@ -177,10 +178,11 @@ static u32 dq_bit_map_2_phy_pin[] = { void mv_ddr_mem_scrubbing(void) { + ddr3_new_tip_ecc_scrub(); } static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, - enum hws_ddr_freq freq); + enum mv_ddr_freq freq); /* * Read temperature TJ value @@ -219,7 +221,7 @@ static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) * Notes: * Returns: MV_OK if success, other error code if fail. */ -static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq, +static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq, struct hws_tip_freq_config_info *freq_config_info) { @@ -377,13 +379,13 @@ static int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) static u8 ddr3_tip_clock_mode(u32 frequency) { - if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) + if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400)) return 1; return 2; } -static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) +static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq) { u32 reg, ref_clk_satr; @@ -402,7 +404,7 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) reg)); /* fallthrough */ case 0x0: - *freq = DDR_FREQ_333; + *freq = MV_DDR_FREQ_333; break; case 0x3: DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, @@ -410,7 +412,7 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) reg)); /* fallthrough */ case 0x2: - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0xd: DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, @@ -418,10 +420,10 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) reg)); /* fallthrough */ case 0x4: - *freq = DDR_FREQ_533; + *freq = MV_DDR_FREQ_533; break; case 0x6: - *freq = DDR_FREQ_600; + *freq = MV_DDR_FREQ_600; break; case 0x11: case 0x14: @@ -430,7 +432,7 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) reg)); /* fallthrough */ case 0x8: - *freq = DDR_FREQ_667; + *freq = MV_DDR_FREQ_667; break; case 0x15: case 0x1b: @@ -439,16 +441,16 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) reg)); /* fallthrough */ case 0xc: - *freq = DDR_FREQ_800; + *freq = MV_DDR_FREQ_800; break; case 0x10: - *freq = DDR_FREQ_933; + *freq = MV_DDR_FREQ_933; break; case 0x12: - *freq = DDR_FREQ_900; + *freq = MV_DDR_FREQ_900; break; case 0x13: - *freq = DDR_FREQ_933; + *freq = MV_DDR_FREQ_933; break; default: *freq = 0; @@ -457,16 +459,16 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) } else { /* REFCLK 40MHz case */ switch (reg) { case 0x3: - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0x5: - *freq = DDR_FREQ_533; + *freq = MV_DDR_FREQ_533; break; case 0xb: - *freq = DDR_FREQ_800; + *freq = MV_DDR_FREQ_800; break; case 0x1e: - *freq = DDR_FREQ_900; + *freq = MV_DDR_FREQ_900; break; default: *freq = 0; @@ -477,7 +479,7 @@ static int mv_ddr_sar_freq_get(int dev_num, enum hws_ddr_freq *freq) return MV_OK; } -static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq) +static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) { u32 reg, ref_clk_satr; @@ -493,37 +495,37 @@ static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq) case 0x0: case 0x1: /* Medium is same as TF to run PBS in this freq */ - *freq = DDR_FREQ_333; + *freq = MV_DDR_FREQ_333; break; case 0x2: case 0x3: /* Medium is same as TF to run PBS in this freq */ - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0x4: case 0xd: /* Medium is same as TF to run PBS in this freq */ - *freq = DDR_FREQ_533; + *freq = MV_DDR_FREQ_533; break; case 0x8: case 0x10: case 0x11: case 0x14: - *freq = DDR_FREQ_333; + *freq = MV_DDR_FREQ_333; break; case 0xc: case 0x15: case 0x1b: - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0x6: - *freq = DDR_FREQ_300; + *freq = MV_DDR_FREQ_300; break; case 0x12: - *freq = DDR_FREQ_360; + *freq = MV_DDR_FREQ_360; break; case 0x13: - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; default: *freq = 0; @@ -533,17 +535,17 @@ static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq) switch (reg) { case 0x3: /* Medium is same as TF to run PBS in this freq */ - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0x5: /* Medium is same as TF to run PBS in this freq */ - *freq = DDR_FREQ_533; + *freq = MV_DDR_FREQ_533; break; case 0xb: - *freq = DDR_FREQ_400; + *freq = MV_DDR_FREQ_400; break; case 0x1e: - *freq = DDR_FREQ_360; + *freq = MV_DDR_FREQ_360; break; default: *freq = 0; @@ -682,7 +684,7 @@ static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) static int mv_ddr_training_mask_set(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); - enum hws_ddr_freq ddr_freq = tm->interface_params[0].memory_freq; + enum mv_ddr_freq ddr_freq = tm->interface_params[0].memory_freq; mask_tune_func = (SET_LOW_FREQ_MASK_BIT | LOAD_PATTERN_MASK_BIT | @@ -699,7 +701,7 @@ static int mv_ddr_training_mask_set(void) CENTRALIZATION_TX_MASK_BIT); rl_mid_freq_wa = 1; - if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) { + if ((ddr_freq == MV_DDR_FREQ_333) || (ddr_freq == MV_DDR_FREQ_400)) { mask_tune_func = (WRITE_LEVELING_MASK_BIT | LOAD_PATTERN_2_MASK_BIT | WRITE_LEVELING_SUPP_MASK_BIT | @@ -712,7 +714,7 @@ static int mv_ddr_training_mask_set(void) } /* Supplementary not supported for ECC modes */ - if (1 == ddr3_if_ecc_enabled()) { + if (mv_ddr_is_ecc_ena()) { mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT; mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT; mask_tune_func &= ~PBS_TX_MASK_BIT; @@ -734,11 +736,12 @@ void mv_ddr_set_calib_controller(void) } static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, - enum hws_ddr_freq frequency) + enum mv_ddr_freq frequency) { u32 divider = 0; u32 sar_val, ref_clk_satr; u32 async_val; + u32 freq = mv_ddr_freq_get(frequency); if (if_id != 0) { DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR, @@ -755,11 +758,11 @@ static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ) - divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq_val[frequency]; + divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq; else - divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq_val[frequency]; + divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq; - if ((async_mode_at_tf == 1) && (freq_val[frequency] > 400)) { + if ((async_mode_at_tf == 1) && (freq > 400)) { /* Set async mode */ dunit_write(0x20220, 0x1000, 0x1000); dunit_write(0xe42f4, 0x200, 0x200); @@ -769,42 +772,38 @@ static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, /* Set KNL values */ switch (frequency) { -#ifdef CONFIG_DDR3 - case DDR_FREQ_467: + case MV_DDR_FREQ_467: async_val = 0x806f012; break; - case DDR_FREQ_533: + case MV_DDR_FREQ_533: async_val = 0x807f012; break; - case DDR_FREQ_600: + case MV_DDR_FREQ_600: async_val = 0x805f00a; break; -#endif - case DDR_FREQ_667: + case MV_DDR_FREQ_667: async_val = 0x809f012; break; - case DDR_FREQ_800: + case MV_DDR_FREQ_800: async_val = 0x807f00a; break; -#ifdef CONFIG_DDR3 - case DDR_FREQ_850: + case MV_DDR_FREQ_850: async_val = 0x80cb012; break; -#endif - case DDR_FREQ_900: + case MV_DDR_FREQ_900: async_val = 0x80d7012; break; - case DDR_FREQ_933: + case MV_DDR_FREQ_933: async_val = 0x80df012; break; - case DDR_FREQ_1000: + case MV_DDR_FREQ_1000: async_val = 0x80ef012; break; - case DDR_FREQ_1066: + case MV_DDR_FREQ_1066: async_val = 0x80ff012; break; default: - /* set DDR_FREQ_667 as default */ + /* set MV_DDR_FREQ_667 as default */ async_val = 0x809f012; } dunit_write(0xe42f0, 0xffffffff, async_val); @@ -890,7 +889,7 @@ int mv_ddr_early_init(void) mv_ddr_sw_db_init(0, 0); - if (tm->interface_params[0].memory_freq != DDR_FREQ_SAR) + if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR) async_mode_at_tf = 1; return MV_OK; @@ -934,7 +933,7 @@ int ddr3_silicon_post_init(void) u32 mv_ddr_init_freq_get(void) { - enum hws_ddr_freq freq; + enum mv_ddr_freq freq; mv_ddr_sar_freq_get(0, &freq); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 9c5fdecd93..281d4c2301 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -6,6 +6,7 @@ #ifndef _MV_DDR_PLAT_H #define _MV_DDR_PLAT_H +#define MAX_DEVICE_NUM 1 #define MAX_INTERFACE_NUM 1 #define MAX_BUS_NUM 5 #define DDR_IF_CTRL_SUBPHYS_NUM 3 @@ -121,6 +122,9 @@ #define DLB_QUEUE_MAP_REG 0x1784 #define DLB_SPLIT_REG 0x1788 +/* ck swap control subphy number */ +#define CK_SWAP_CTRL_PHY_NUM 2 + /* Subphy result control per byte registers */ #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 @@ -221,7 +225,7 @@ extern u16 odt_intercept[]; int mv_ddr_pre_training_soc_config(const char *ddr_type); int mv_ddr_post_training_soc_config(const char *ddr_type); void mv_ddr_mem_scrubbing(void); - +u32 mv_ddr_init_freq_get(void); void mv_ddr_odpg_enable(void); void mv_ddr_odpg_disable(void); void mv_ddr_odpg_done_clr(void); @@ -233,4 +237,5 @@ int mv_ddr_pre_training_fixup(void); int mv_ddr_post_training_fixup(void); int mv_ddr_manual_cal_do(void); int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); + #endif /* _MV_DDR_PLAT_H */ diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h index ceda204a49..cf2a6c92e8 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h @@ -134,6 +134,7 @@ #define SDRAM_OP_CMD_CS_BASE 8 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) #define SDRAM_OP_CMD_CS_MASK 0x1 +#define SDRAM_OP_CMD_ALL_CS_MASK 0xf enum { CMD_NORMAL, CMD_PRECHARGE, @@ -270,6 +271,10 @@ enum { #define ZQC_CFG_REG 0x15e4 #define DRAM_PHY_CFG_REG 0x15ec #define ODPG_CTRL_CTRL_REG 0x1600 +#define ODPG_CTRL_AUTO_REFRESH_OFFS 21 +#define ODPG_CTRL_AUTO_REFRESH_MASK 0x1 +#define ODPG_CTRL_AUTO_REFRESH_DIS 1 +#define ODPG_CTRL_AUTO_REFRESH_ENA 0 #define ODPG_DATA_CTRL_REG 0x1630 #define ODPG_WRBUF_WR_CTRL_OFFS 0 @@ -406,6 +411,20 @@ enum { #define CRX_PHY_REG(cs) (CRX_PHY_BASE + (cs) * 0x4) #define PHY_CTRL_PHY_REG 0x90 +#define INV_PAD0_OFFS 2 +#define INV_PAD1_OFFS 3 +#define INV_PAD2_OFFS 4 +#define INV_PAD3_OFFS 5 +#define INV_PAD4_OFFS 6 +#define INV_PAD5_OFFS 7 +#define INV_PAD6_OFFS 8 +#define INV_PAD7_OFFS 9 +#define INV_PAD8_OFFS 10 +#define INV_PAD9_OFFS 11 +#define INV_PAD10_OFFS 12 +#define INV_PAD_MASK 0x1 +#define INVERT_PAD 1 + #define ADLL_CFG0_PHY_REG 0x92 #define ADLL_CFG1_PHY_REG 0x93 #define ADLL_CFG2_PHY_REG 0x94 diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index e9e7f18098..04dbfe94d6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -81,9 +81,6 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 + (spd_data->byte_fields.byte_41.bit_fields.t_wr_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twr to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWR_MIN] == 0) - timing_data[MV_DDR_TWR_MIN] = 15000; /* t rcd min, ps */ calc_val = spd_data->byte_fields.byte_25 * MV_DDR_SPD_DATA_MTB + @@ -127,6 +124,13 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ return 1; timing_data[MV_DDR_TRRD_L_MIN] = calc_val; + /* t ccd l min, ps */ + calc_val = spd_data->byte_fields.byte_40 * MV_DDR_SPD_DATA_MTB + + (signed char)spd_data->byte_fields.byte_117 * MV_DDR_SPD_DATA_FTB; + if (calc_val < 0) + return 1; + timing_data[MV_DDR_TCCD_L_MIN] = calc_val; + /* t faw min, ps */ timing_data[MV_DDR_TFAW_MIN] = (spd_data->byte_fields.byte_37 + (spd_data->byte_fields.byte_36.bit_fields.t_faw_min_msn << MV_DDR_SPD_MSB_OFFS)) * @@ -136,17 +140,11 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ timing_data[MV_DDR_TWTR_S_MIN] = (spd_data->byte_fields.byte_44 + (spd_data->byte_fields.byte_43.bit_fields.t_wtr_s_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twtr_s to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWTR_S_MIN] == 0) - timing_data[MV_DDR_TWTR_S_MIN] = 2500; /* t wtr l min, ps */ timing_data[MV_DDR_TWTR_L_MIN] = (spd_data->byte_fields.byte_45 + (spd_data->byte_fields.byte_43.bit_fields.t_wtr_l_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twtr_l to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWTR_L_MIN] == 0) - timing_data[MV_DDR_TWTR_L_MIN] = 7500; return 0; } diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index f56ce06770..ef3b658a78 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -2,15 +2,16 @@ /* * Copyright (C) Marvell International Ltd. and its affiliates */ +#include "ddr_ml_wrapper.h" +#include "mv_ddr_plat.h" #include "mv_ddr_topology.h" #include "mv_ddr_common.h" #include "mv_ddr_spd.h" -#include "ddr3_init.h" #include "ddr_topology_def.h" #include "ddr3_training_ip_db.h" #include "ddr3_training_ip.h" - +#include "mv_ddr_training_db.h" unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk) { @@ -32,54 +33,57 @@ unsigned int mv_ddr_cwl_calc(unsigned int tclk) cwl = 11; else if (tclk >= 833) cwl = 12; + else if (tclk >= 750) + cwl = 14; + else if (tclk >= 625) + cwl = 16; else cwl = 0; return cwl; } -struct mv_ddr_topology_map *mv_ddr_topology_map_update(void) +int mv_ddr_topology_map_update(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + struct if_params *iface_params = &(tm->interface_params[0]); unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); - enum hws_speed_bin speed_bin_index; - enum hws_ddr_freq freq = DDR_FREQ_LAST; + enum mv_ddr_speed_bin speed_bin_index; + enum mv_ddr_freq freq = MV_DDR_FREQ_LAST; unsigned int tclk; unsigned char val = 0; int i; - - if (tm->interface_params[0].memory_freq == DDR_FREQ_SAR) - tm->interface_params[0].memory_freq = mv_ddr_init_freq_get(); + if (iface_params->memory_freq == MV_DDR_FREQ_SAR) + iface_params->memory_freq = mv_ddr_init_freq_get(); if (tm->cfg_src == MV_DDR_CFG_SPD) { /* check dram device type */ val = mv_ddr_spd_dev_type_get(&tm->spd_data); if (val != MV_DDR_SPD_DEV_TYPE_DDR4) { printf("mv_ddr: unsupported dram device type found\n"); - return NULL; + return -1; } /* update topology map with timing data */ if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) { printf("mv_ddr: negative timing data found\n"); - return NULL; + return -1; } /* update device width in topology map */ - tm->interface_params[0].bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); + iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); /* update die capacity in topology map */ - tm->interface_params[0].memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); + iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); /* update bus bit mask in topology map */ tm->bus_act_mask = mv_ddr_bus_bit_mask_get(); /* update cs bit mask in topology map */ val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data); - for (i = 0; i < octets_per_if_num; i++) { - tm->interface_params[0].as_bus_params[i].cs_bitmask = val; - } + for (i = 0; i < octets_per_if_num; i++) + iface_params->as_bus_params[i].cs_bitmask = val; /* check dram module type */ val = mv_ddr_spd_module_type_get(&tm->spd_data); @@ -93,48 +97,44 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_update(void) break; default: printf("mv_ddr: unsupported dram module type found\n"); - return NULL; + return -1; } /* update mirror bit mask in topology map */ val = mv_ddr_spd_mem_mirror_get(&tm->spd_data); - for (i = 0; i < octets_per_if_num; i++) { - tm->interface_params[0].as_bus_params[i].mirror_enable_bitmask = val << 1; - } + for (i = 0; i < octets_per_if_num; i++) + iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1; - tclk = 1000000 / freq_val[tm->interface_params[0].memory_freq]; + tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq); /* update cas write latency (cwl) */ val = mv_ddr_cwl_calc(tclk); if (val == 0) { printf("mv_ddr: unsupported cas write latency value found\n"); - return NULL; + return -1; } - tm->interface_params[0].cas_wl = val; + iface_params->cas_wl = val; /* update cas latency (cl) */ mv_ddr_spd_supported_cls_calc(&tm->spd_data); val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); if (val == 0) { printf("mv_ddr: unsupported cas latency value found\n"); - return NULL; + return -1; } - tm->interface_params[0].cas_l = val; + iface_params->cas_l = val; } else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) { /* set cas and cas-write latencies per speed bin, if they unset */ - speed_bin_index = tm->interface_params[0].speed_bin_index; - freq = tm->interface_params[0].memory_freq; + speed_bin_index = iface_params->speed_bin_index; + freq = iface_params->memory_freq; - if (tm->interface_params[0].cas_l == 0) - tm->interface_params[0].cas_l = - cas_latency_table[speed_bin_index].cl_val[freq]; + if (iface_params->cas_l == 0) + iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq); - if (tm->interface_params[0].cas_wl == 0) - tm->interface_params[0].cas_wl = - cas_write_latency_table[speed_bin_index].cl_val[freq]; + if (iface_params->cas_wl == 0) + iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq); } - - return tm; + return 0; } unsigned short mv_ddr_bus_bit_mask_get(void) @@ -195,3 +195,150 @@ unsigned int mv_ddr_if_bus_width_get(void) return bus_width; } + +unsigned int mv_ddr_cs_num_get(void) +{ + unsigned int cs_num = 0; + unsigned int cs, sphy; + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + struct if_params *iface_params = &(tm->interface_params[0]); + unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); + + for (sphy = 0; sphy < sphy_max; sphy++) { + VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); + break; + } + + for (cs = 0; cs < MAX_CS_NUM; cs++) { + VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs); + cs_num++; + } + + return cs_num; +} + +int mv_ddr_is_ecc_ena(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + + if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) || + DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) || + DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask)) + return 1; + else + return 0; +} + +/* translate topology map definition to real memory size in bits */ +static unsigned int mem_size[] = { + ADDR_SIZE_512MB, + ADDR_SIZE_1GB, + ADDR_SIZE_2GB, + ADDR_SIZE_4GB, + ADDR_SIZE_8GB + /* TODO: add capacity up to 256GB */ +}; + +unsigned long long mv_ddr_mem_sz_per_cs_get(void) +{ + unsigned long long mem_sz_per_cs; + unsigned int i, sphys, sphys_per_dunit; + unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE); + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + struct if_params *iface_params = &(tm->interface_params[0]); + + /* calc number of active subphys excl. ecc one */ + for (i = 0, sphys = 0; i < sphy_max - 1; i++) { + VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); + sphys++; + } + + /* calc number of subphys per ddr unit */ + if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT) + sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT; + else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT) + sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT; + else { + printf("mv_ddr: unsupported bus width type found\n"); + return 0; + } + + /* calc dram size per cs */ + mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] * + (unsigned long long)sphys / + (unsigned long long)sphys_per_dunit; + + return mem_sz_per_cs; +} + +unsigned long long mv_ddr_mem_sz_get(void) +{ + unsigned long long tot_mem_sz = 0; + unsigned long long mem_sz_per_cs = 0; + unsigned long long max_cs = mv_ddr_cs_num_get(); + + mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get(); + tot_mem_sz = max_cs * mem_sz_per_cs; + + return tot_mem_sz; +} + +unsigned int mv_ddr_rtt_nom_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom; + + if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) { + printf("error: %s: unsupported rtt_nom parameter found\n", __func__); + rtt_nom = PARAM_UNDEFINED; + } + + return rtt_nom; +} + +unsigned int mv_ddr_rtt_park_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int cs_num = mv_ddr_cs_num_get(); + unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST; + + if (cs_num > 0 && cs_num <= MAX_CS_NUM) + rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1]; + + if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) { + printf("error: %s: unsupported rtt_park parameter found\n", __func__); + rtt_park = PARAM_UNDEFINED; + } + + return rtt_park; +} + +unsigned int mv_ddr_rtt_wr_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int cs_num = mv_ddr_cs_num_get(); + unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST; + + if (cs_num > 0 && cs_num <= MAX_CS_NUM) + rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1]; + + if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) { + printf("error: %s: unsupported rtt_wr parameter found\n", __func__); + rtt_wr = PARAM_UNDEFINED; + } + + return rtt_wr; +} + +unsigned int mv_ddr_dic_get(void) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + unsigned int dic = tm->edata.mem_edata.dic; + + if (dic >= MV_DDR_DIC_RZQ_LAST) { + printf("error: %s: unsupported dic parameter found\n", __func__); + dic = PARAM_UNDEFINED; + } + + return dic; +} diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h index 7bef2d1e0e..766f25db57 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h @@ -6,6 +6,75 @@ #ifndef _MV_DDR_TOPOLOGY_H #define _MV_DDR_TOPOLOGY_H +#define MAX_CS_NUM 4 + +enum mv_ddr_speed_bin { + SPEED_BIN_DDR_800D, + SPEED_BIN_DDR_800E, + SPEED_BIN_DDR_1066E, + SPEED_BIN_DDR_1066F, + SPEED_BIN_DDR_1066G, + SPEED_BIN_DDR_1333F, + SPEED_BIN_DDR_1333G, + SPEED_BIN_DDR_1333H, + SPEED_BIN_DDR_1333J, + SPEED_BIN_DDR_1600G, + SPEED_BIN_DDR_1600H, + SPEED_BIN_DDR_1600J, + SPEED_BIN_DDR_1600K, + SPEED_BIN_DDR_1866J, + SPEED_BIN_DDR_1866K, + SPEED_BIN_DDR_1866L, + SPEED_BIN_DDR_1866M, + SPEED_BIN_DDR_2133K, + SPEED_BIN_DDR_2133L, + SPEED_BIN_DDR_2133M, + SPEED_BIN_DDR_2133N, + + SPEED_BIN_DDR_1333H_EXT, + SPEED_BIN_DDR_1600K_EXT, + SPEED_BIN_DDR_1866M_EXT +}; + +enum mv_ddr_freq { + MV_DDR_FREQ_LOW_FREQ, + MV_DDR_FREQ_400, + MV_DDR_FREQ_533, + MV_DDR_FREQ_667, + MV_DDR_FREQ_800, + MV_DDR_FREQ_933, + MV_DDR_FREQ_1066, + MV_DDR_FREQ_311, + MV_DDR_FREQ_333, + MV_DDR_FREQ_467, + MV_DDR_FREQ_850, + MV_DDR_FREQ_600, + MV_DDR_FREQ_300, + MV_DDR_FREQ_900, + MV_DDR_FREQ_360, + MV_DDR_FREQ_1000, + MV_DDR_FREQ_LAST, + MV_DDR_FREQ_SAR +}; + +enum mv_ddr_speed_bin_timing { + SPEED_BIN_TRCD, + SPEED_BIN_TRP, + SPEED_BIN_TRAS, + SPEED_BIN_TRC, + SPEED_BIN_TRRD1K, + SPEED_BIN_TRRD2K, + SPEED_BIN_TPD, + SPEED_BIN_TFAW1K, + SPEED_BIN_TFAW2K, + SPEED_BIN_TWTR, + SPEED_BIN_TRTP, + SPEED_BIN_TWR, + SPEED_BIN_TMOD, + SPEED_BIN_TXPDLL, + SPEED_BIN_TXSDLL +}; + /* ddr bus masks */ #define BUS_MASK_32BIT 0xf #define BUS_MASK_32BIT_ECC 0x1f @@ -16,6 +85,12 @@ #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f +#define MV_DDR_CS_BITMASK_1CS 0x1 +#define MV_DDR_CS_BITMASK_2CS 0x3 + +#define MV_DDR_ONE_SPHY_PER_DUNIT 1 +#define MV_DDR_TWO_SPHY_PER_DUNIT 2 + /* source of ddr configuration data */ enum mv_ddr_cfg_src { MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */ @@ -25,11 +100,6 @@ enum mv_ddr_cfg_src { MV_DDR_CFG_LAST }; -enum mv_ddr_num_of_sub_phys_per_ddr_unit { - SINGLE_SUB_PHY = 1, - TWO_SUB_PHYS = 2 -}; - enum mv_ddr_temperature { MV_DDR_TEMP_LOW, MV_DDR_TEMP_NORMAL, @@ -53,12 +123,78 @@ enum mv_ddr_timing_data { MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */ MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */ MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */ + MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */ MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */ MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */ MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */ MV_DDR_TDATA_LAST }; +enum mv_ddr_electrical_data { + MV_DDR_CK_DLY, + MV_DDR_PHY_REG3, + MV_DDR_ZPRI_DATA, + MV_DDR_ZNRI_DATA, + MV_DDR_ZPRI_CTRL, + MV_DDR_ZNRI_CTRL, + MV_DDR_ZPODT_DATA, + MV_DDR_ZNODT_DATA, + MV_DDR_ZPODT_CTRL, + MV_DDR_ZNODT_CTRL, + MV_DDR_DIC, + MV_DDR_ODT_CFG, + MV_DDR_RTT_NOM, + MV_DDR_RTT_WR, + MV_DDR_RTT_PARK, + MV_DDR_EDATA_LAST +}; + +/* memory electrical configuration values */ +enum mv_ddr_rtt_nom_park_evalue { + MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_NOM_PARK_RZQ_LAST +}; + +enum mv_ddr_rtt_wr_evalue { + MV_DDR_RTT_WR_DYN_ODT_OFF, + MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_WR_HIZ, + MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */ + MV_DDR_RTT_WR_RZQ_LAST +}; + +enum mv_ddr_dic_evalue { + MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */ + MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */ + MV_DDR_DIC_RZQ_LAST +}; + +/* phy electrical configuration values */ +enum mv_ddr_ohm_evalue { + MV_DDR_OHM_30 = 30, + MV_DDR_OHM_48 = 48, + MV_DDR_OHM_60 = 60, + MV_DDR_OHM_80 = 80, + MV_DDR_OHM_120 = 120, + MV_DDR_OHM_240 = 240, + MV_DDR_OHM_LAST +}; + +/* mac electrical configuration values */ +enum mv_ddr_odt_cfg_evalue { + MV_DDR_ODT_CFG_NORMAL, + MV_DDR_ODT_CFG_ALWAYS_ON, + MV_DDR_ODT_CFG_LAST +}; + enum mv_ddr_dev_width { /* sdram device width */ MV_DDR_DEV_WIDTH_4BIT, MV_DDR_DEV_WIDTH_8BIT, @@ -119,11 +255,75 @@ enum mv_ddr_die_count { MV_DDR_DIE_CNT_LAST }; +#define IS_ACTIVE(mask, id) \ + ((mask) & (1 << (id))) + +#define VALIDATE_ACTIVE(mask, id) \ + { \ + if (IS_ACTIVE(mask, id) == 0) \ + continue; \ + } + +#define IS_IF_ACTIVE(if_mask, if_id) \ + ((if_mask) & (1 << (if_id))) + +#define VALIDATE_IF_ACTIVE(mask, id) \ + { \ + if (IS_IF_ACTIVE(mask, id) == 0) \ + continue; \ + } + +#define IS_BUS_ACTIVE(if_mask , if_id) \ + (((if_mask) >> (if_id)) & 1) + +#define VALIDATE_BUS_ACTIVE(mask, id) \ + { \ + if (IS_BUS_ACTIVE(mask, id) == 0) \ + continue; \ + } + +#define DDR3_IS_ECC_PUP3_MODE(if_mask) \ + (((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) + +#define DDR3_IS_ECC_PUP4_MODE(if_mask) \ + (((if_mask) == BUS_MASK_32BIT_ECC || \ + (if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0) + +#define DDR3_IS_16BIT_DRAM_MODE(mask) \ + (((mask) == BUS_MASK_16BIT || \ + (mask) == BUS_MASK_16BIT_ECC || \ + (mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0) + +#define DDR3_IS_ECC_PUP8_MODE(if_mask) \ + (((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || \ + (if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) + +#define MV_DDR_IS_64BIT_DRAM_MODE(mask) \ + ((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \ + (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0) + +#define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) \ + (((sphys) == 9) && \ + (((mask) == BUS_MASK_32BIT) || \ + ((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0) + +#define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys) \ + (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) || \ + DDR3_IS_16BIT_DRAM_MODE(mask)) + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void); unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk); unsigned int mv_ddr_cwl_calc(unsigned int tclk); -struct mv_ddr_topology_map *mv_ddr_topology_map_update(void); -struct dram_config *mv_ddr_dram_config_update(void); +int mv_ddr_topology_map_update(void); unsigned short mv_ddr_bus_bit_mask_get(void); unsigned int mv_ddr_if_bus_width_get(void); +unsigned int mv_ddr_cs_num_get(void); +int mv_ddr_is_ecc_ena(void); +unsigned long long mv_ddr_mem_sz_per_cs_get(void); +unsigned long long mv_ddr_mem_sz_get(void); +unsigned int mv_ddr_rtt_nom_get(void); +unsigned int mv_ddr_rtt_park_get(void); +unsigned int mv_ddr_rtt_wr_get(void); +unsigned int mv_ddr_dic_get(void); #endif /* _MV_DDR_TOPOLOGY_H */ diff --git a/drivers/ddr/marvell/a38x/mv_ddr_training_db.h b/drivers/ddr/marvell/a38x/mv_ddr_training_db.h new file mode 100644 index 0000000000..838be4574d --- /dev/null +++ b/drivers/ddr/marvell/a38x/mv_ddr_training_db.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Marvell International Ltd. + */ + +#ifndef _MV_DDR_TRAINING_DB_H +#define _MV_DDR_TRAINING_DB_H + +#include "mv_ddr_topology.h" + +/* in ns */ +#define TREFI_LOW 7800 +#define TREFI_HIGH 3900 + +enum mv_ddr_page_size { + MV_DDR_PAGE_SIZE_1K = 1, + MV_DDR_PAGE_SIZE_2K +}; + +struct mv_ddr_page_element { + /* 8-bit bus width page size */ + enum mv_ddr_page_size page_size_8bit; + /* 16-bit bus width page size */ + enum mv_ddr_page_size page_size_16bit; +}; + +/* cas latency value per frequency */ +struct mv_ddr_cl_val_per_freq { + unsigned int cl_val[MV_DDR_FREQ_LAST]; +}; + +u32 mv_ddr_rfc_get(u32 mem); +unsigned int *mv_ddr_freq_tbl_get(void); +u32 mv_ddr_freq_get(enum mv_ddr_freq freq); +u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size); +unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element); +u32 mv_ddr_cl_val_get(u32 index, u32 freq); +u32 mv_ddr_cwl_val_get(u32 index, u32 freq); + +#endif /* _MV_DDR_TRAINING_DB_H */ diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index f859596d89..5fb9e216d3 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -4,6 +4,7 @@ */ #include "ddr3_init.h" +#include "mv_ddr_common.h" #include "xor_regs.h" /* defines */ @@ -339,16 +340,17 @@ void ddr3_new_tip_ecc_scrub(void) { u32 cs_c, max_cs; u32 cs_ena = 0; - u32 dev_num = 0; uint64_t total_mem_size, cs_mem_size = 0; printf("DDR Training Sequence - Start scrubbing\n"); - max_cs = ddr3_tip_max_cs_get(dev_num); + max_cs = mv_ddr_cs_num_get(); for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; - /* assume that all CS have same size */ +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) + /* all chip-selects are of same size */ ddr3_calc_mem_cs_size(0, &cs_mem_size); +#endif mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 4ee6afad35..1820676d7a 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -12,6 +12,29 @@ config DMA buses that is used to transfer data to and from memory. The uclass interface is defined in include/dma.h. +config DMA_CHANNELS + bool "Enable DMA channels support" + depends on DMA + help + Enable channels support for DMA. Some DMA controllers have multiple + channels which can either transfer data to/from different devices. + +config SANDBOX_DMA + bool "Enable the sandbox DMA test driver" + depends on DMA && DMA_CHANNELS && SANDBOX + help + Enable support for a test DMA uclass implementation. It stimulates + DMA transfer by simple copying data between channels. + +config BCM6348_IUDMA + bool "BCM6348 IUDMA driver" + depends on ARCH_BMIPS + select DMA_CHANNELS + help + Enable the BCM6348 IUDMA driver. + This driver support data transfer from devices to + memory and from memory to devices. + config TI_EDMA3 bool "TI EDMA3 driver" help diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 4eaef8ac65..b5f9147e0a 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -7,7 +7,9 @@ obj-$(CONFIG_DMA) += dma-uclass.o obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o +obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o +obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c new file mode 100644 index 0000000000..1d3c192cfe --- /dev/null +++ b/drivers/dma/bcm6348-iudma.c @@ -0,0 +1,642 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/dma/bcm63xx-iudma.c: + * Copyright (C) 2015 Simon Arlott + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon + * + * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h: + * Copyright (C) 2000-2010 Broadcom Corporation + * + * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c: + * Copyright (C) 2010 Broadcom Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DMA_RX_DESC 6 +#define DMA_TX_DESC 1 + +/* DMA Channels */ +#define DMA_CHAN_FLOWC(x) ((x) >> 1) +#define DMA_CHAN_MAX 16 +#define DMA_CHAN_SIZE 0x10 +#define DMA_CHAN_TOUT 500 + +/* DMA Global Configuration register */ +#define DMA_CFG_REG 0x00 +#define DMA_CFG_ENABLE_SHIFT 0 +#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT) +#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1) +#define DMA_CFG_NCHANS_SHIFT 24 +#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT) + +/* DMA Global Flow Control registers */ +#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31 +#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT) + +/* DMA Global Reset register */ +#define DMA_RST_REG 0x34 +#define DMA_RST_CHAN_SHIFT 0 +#define DMA_RST_CHAN_MASK(x) (1 << x) + +/* DMA Channel Configuration register */ +#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) +#define DMAC_CFG_ENABLE_SHIFT 0 +#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT) +#define DMAC_CFG_PKT_HALT_SHIFT 1 +#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT) +#define DMAC_CFG_BRST_HALT_SHIFT 2 +#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT) + +/* DMA Channel Max Burst Length register */ +#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) + +/* DMA SRAM Descriptor Ring Start register */ +#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) + +/* DMA SRAM State/Bytes done/ring offset register */ +#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) + +/* DMA Descriptor Status */ +#define DMAD_ST_CRC_SHIFT 8 +#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT) +#define DMAD_ST_WRAP_SHIFT 12 +#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT) +#define DMAD_ST_SOP_SHIFT 13 +#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT) +#define DMAD_ST_EOP_SHIFT 14 +#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT) +#define DMAD_ST_OWN_SHIFT 15 +#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT) + +#define DMAD6348_ST_OV_ERR_SHIFT 0 +#define DMAD6348_ST_OV_ERR_MASK (1 << DMAD6348_ST_OV_ERR_SHIFT) +#define DMAD6348_ST_CRC_ERR_SHIFT 1 +#define DMAD6348_ST_CRC_ERR_MASK (1 << DMAD6348_ST_CRC_ERR_SHIFT) +#define DMAD6348_ST_RX_ERR_SHIFT 2 +#define DMAD6348_ST_RX_ERR_MASK (1 << DMAD6348_ST_RX_ERR_SHIFT) +#define DMAD6348_ST_OS_ERR_SHIFT 4 +#define DMAD6348_ST_OS_ERR_MASK (1 << DMAD6348_ST_OS_ERR_SHIFT) +#define DMAD6348_ST_UN_ERR_SHIFT 9 +#define DMAD6348_ST_UN_ERR_MASK (1 << DMAD6348_ST_UN_ERR_SHIFT) + +struct bcm6348_dma_desc { + uint16_t length; + uint16_t status; + uint32_t address; +}; + +struct bcm6348_chan_priv { + void __iomem *dma_ring; + uint8_t dma_ring_size; + uint8_t desc_id; + uint8_t desc_cnt; + bool *busy_desc; + bool running; +}; + +struct bcm6348_iudma_hw { + uint16_t err_mask; +}; + +struct bcm6348_iudma_priv { + const struct bcm6348_iudma_hw *hw; + void __iomem *base; + void __iomem *chan; + void __iomem *sram; + struct bcm6348_chan_priv **ch_priv; + uint8_t n_channels; +}; + +static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch) +{ + return !(ch & 1); +} + +static inline void bcm6348_iudma_fdc(void *ptr, ulong size) +{ + ulong start = (ulong) ptr; + + flush_dcache_range(start, start + size); +} + +static inline void bcm6348_iudma_idc(void *ptr, ulong size) +{ + ulong start = (ulong) ptr; + + invalidate_dcache_range(start, start + size); +} + +static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv, + uint8_t ch) +{ + unsigned int timeout = DMA_CHAN_TOUT; + + do { + uint32_t cfg, halt; + + if (timeout > DMA_CHAN_TOUT / 2) + halt = DMAC_CFG_PKT_HALT_MASK; + else + halt = DMAC_CFG_BRST_HALT_MASK; + + /* try to stop dma channel */ + writel_be(halt, priv->chan + DMAC_CFG_REG(ch)); + mb(); + + /* check if channel was stopped */ + cfg = readl_be(priv->chan + DMAC_CFG_REG(ch)); + if (!(cfg & DMAC_CFG_ENABLE_MASK)) + break; + + udelay(1); + } while (--timeout); + + if (!timeout) + pr_err("unable to stop channel %u\n", ch); + + /* reset dma channel */ + setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); + mb(); + clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); +} + +static int bcm6348_iudma_disable(struct dma *dma) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + + /* stop dma channel */ + bcm6348_iudma_chan_stop(priv, dma->id); + + /* dma flow control */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + writel_be(DMA_FLOWC_ALLOC_FORCE_MASK, + DMA_FLOWC_ALLOC_REG(dma->id)); + + /* init channel config */ + ch_priv->running = false; + ch_priv->desc_id = 0; + if (bcm6348_iudma_chan_is_rx(dma->id)) + ch_priv->desc_cnt = 0; + else + ch_priv->desc_cnt = ch_priv->dma_ring_size; + + return 0; +} + +static int bcm6348_iudma_enable(struct dma *dma) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + uint8_t i; + + /* dma ring init */ + for (i = 0; i < ch_priv->desc_cnt; i++) { + if (bcm6348_iudma_chan_is_rx(dma->id)) { + ch_priv->busy_desc[i] = false; + dma_desc->status |= DMAD_ST_OWN_MASK; + } else { + dma_desc->status = 0; + dma_desc->length = 0; + dma_desc->address = 0; + } + + if (i == ch_priv->desc_cnt - 1) + dma_desc->status |= DMAD_ST_WRAP_MASK; + + dma_desc++; + } + + /* init to first descriptor */ + ch_priv->desc_id = 0; + + /* force cache writeback */ + bcm6348_iudma_fdc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* clear sram */ + writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id)); + + /* set dma ring start */ + writel_be(virt_to_phys(ch_priv->dma_ring), + priv->sram + DMAS_RSTART_REG(dma->id)); + + /* set flow control */ + if (bcm6348_iudma_chan_is_rx(dma->id)) { + u32 val; + + setbits_be32(priv->base + DMA_CFG_REG, + DMA_CFG_FLOWC_ENABLE(dma->id)); + + val = ch_priv->desc_cnt / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id)); + + val = (ch_priv->desc_cnt * 2) / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id)); + + writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id)); + } + + /* set dma max burst */ + writel_be(ch_priv->desc_cnt, + priv->chan + DMAC_BURST_REG(dma->id)); + + /* kick rx dma channel */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), + DMAC_CFG_ENABLE_MASK); + + /* channel is now enabled */ + ch_priv->running = true; + + return 0; +} + +static int bcm6348_iudma_request(struct dma *dma) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv; + + /* check if channel is valid */ + if (dma->id >= priv->n_channels) + return -ENODEV; + + /* alloc channel private data */ + priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv)); + if (!priv->ch_priv[dma->id]) + return -ENOMEM; + ch_priv = priv->ch_priv[dma->id]; + + /* alloc dma ring */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + ch_priv->dma_ring_size = DMA_RX_DESC; + else + ch_priv->dma_ring_size = DMA_TX_DESC; + + ch_priv->dma_ring = + malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) * + ch_priv->dma_ring_size); + if (!ch_priv->dma_ring) + return -ENOMEM; + + /* init channel config */ + ch_priv->running = false; + ch_priv->desc_id = 0; + if (bcm6348_iudma_chan_is_rx(dma->id)) { + ch_priv->desc_cnt = 0; + ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool)); + } else { + ch_priv->desc_cnt = ch_priv->dma_ring_size; + ch_priv->busy_desc = NULL; + } + + return 0; +} + +static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + const struct bcm6348_iudma_hw *hw = priv->hw; + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring; + int ret; + + /* get dma ring descriptor address */ + dma_desc += ch_priv->desc_id; + + /* invalidate cache data */ + bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc)); + + /* check dma own */ + if (dma_desc->status & DMAD_ST_OWN_MASK) + return -EAGAIN; + + /* check pkt */ + if (!(dma_desc->status & DMAD_ST_EOP_MASK) || + !(dma_desc->status & DMAD_ST_SOP_MASK) || + (dma_desc->status & hw->err_mask)) { + pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n", + dma->id, ch_priv->desc_id, dma_desc->status); + ret = -EAGAIN; + } else { + /* set dma buffer address */ + *dst = phys_to_virt(dma_desc->address); + + /* invalidate cache data */ + bcm6348_iudma_idc(*dst, dma_desc->length); + + /* return packet length */ + ret = dma_desc->length; + } + + /* busy dma descriptor */ + ch_priv->busy_desc[ch_priv->desc_id] = true; + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt; + + return ret; +} + +static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len, + void *metadata) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc; + uint16_t status; + + /* flush cache */ + bcm6348_iudma_fdc(src, len); + + /* get dma ring descriptor address */ + dma_desc = ch_priv->dma_ring; + dma_desc += ch_priv->desc_id; + + /* config dma descriptor */ + status = (DMAD_ST_OWN_MASK | + DMAD_ST_EOP_MASK | + DMAD_ST_CRC_MASK | + DMAD_ST_SOP_MASK); + if (ch_priv->desc_id == ch_priv->desc_cnt - 1) + status |= DMAD_ST_WRAP_MASK; + + /* set dma descriptor */ + dma_desc->address = virt_to_phys(src); + dma_desc->length = len; + dma_desc->status = status; + + /* flush cache */ + bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc)); + + /* kick tx dma channel */ + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK); + + /* poll dma status */ + do { + /* invalidate cache */ + bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc)); + + if (!(dma_desc->status & DMAD_ST_OWN_MASK)) + break; + } while(1); + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt; + + return 0; +} + +static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + uint16_t status; + uint8_t i; + u32 cfg; + + /* get dirty dma descriptor */ + for (i = 0; i < ch_priv->desc_cnt; i++) { + if (phys_to_virt(dma_desc->address) == dst) + break; + + dma_desc++; + } + + /* dma descriptor not found */ + if (i == ch_priv->desc_cnt) { + pr_err("dirty dma descriptor not found\n"); + return -ENOENT; + } + + /* invalidate cache */ + bcm6348_iudma_idc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* free dma descriptor */ + ch_priv->busy_desc[i] = false; + + status = DMAD_ST_OWN_MASK; + if (i == ch_priv->desc_cnt - 1) + status |= DMAD_ST_WRAP_MASK; + + dma_desc->status |= status; + dma_desc->length = PKTSIZE_ALIGN; + + /* tell dma we allocated one buffer */ + writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id)); + + /* flush cache */ + bcm6348_iudma_fdc(ch_priv->dma_ring, + sizeof(*dma_desc) * ch_priv->desc_cnt); + + /* kick rx dma channel if disabled */ + cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id)); + if (!(cfg & DMAC_CFG_ENABLE_MASK)) + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), + DMAC_CFG_ENABLE_MASK); + + return 0; +} + +static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring; + + /* no more dma descriptors available */ + if (ch_priv->desc_cnt == ch_priv->dma_ring_size) { + pr_err("max number of buffers reached\n"); + return -EINVAL; + } + + /* get next dma descriptor */ + dma_desc += ch_priv->desc_cnt; + + /* init dma descriptor */ + dma_desc->address = virt_to_phys(dst); + dma_desc->length = size; + dma_desc->status = 0; + + /* flush cache */ + bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc)); + + /* increment dma descriptors */ + ch_priv->desc_cnt++; + + return 0; +} + +static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst, + size_t size) +{ + const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + + /* only add new rx buffers if channel isn't running */ + if (ch_priv->running) + return bcm6348_iudma_free_rcv_buf(dma, dst, size); + else + return bcm6348_iudma_add_rcv_buf(dma, dst, size); +} + +static const struct dma_ops bcm6348_iudma_ops = { + .disable = bcm6348_iudma_disable, + .enable = bcm6348_iudma_enable, + .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf, + .request = bcm6348_iudma_request, + .receive = bcm6348_iudma_receive, + .send = bcm6348_iudma_send, +}; + +static const struct bcm6348_iudma_hw bcm6348_hw = { + .err_mask = (DMAD6348_ST_OV_ERR_MASK | + DMAD6348_ST_CRC_ERR_MASK | + DMAD6348_ST_RX_ERR_MASK | + DMAD6348_ST_OS_ERR_MASK | + DMAD6348_ST_UN_ERR_MASK), +}; + +static const struct bcm6348_iudma_hw bcm6368_hw = { + .err_mask = 0, +}; + +static const struct udevice_id bcm6348_iudma_ids[] = { + { + .compatible = "brcm,bcm6348-iudma", + .data = (ulong)&bcm6348_hw, + }, { + .compatible = "brcm,bcm6368-iudma", + .data = (ulong)&bcm6368_hw, + }, { /* sentinel */ } +}; + +static int bcm6348_iudma_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct bcm6348_iudma_priv *priv = dev_get_priv(dev); + const struct bcm6348_iudma_hw *hw = + (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev); + uint8_t ch; + int i; + + uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM | + DMA_SUPPORTS_MEM_TO_DEV); + priv->hw = hw; + + /* dma global base address */ + priv->base = dev_remap_addr_name(dev, "dma"); + if (!priv->base) + return -EINVAL; + + /* dma channels base address */ + priv->chan = dev_remap_addr_name(dev, "dma-channels"); + if (!priv->chan) + return -EINVAL; + + /* dma sram base address */ + priv->sram = dev_remap_addr_name(dev, "dma-sram"); + if (!priv->sram) + return -EINVAL; + + /* get number of channels */ + priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8); + if (priv->n_channels > DMA_CHAN_MAX) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("error enabling clock %d\n", i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("error freeing clock %d\n", i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("error deasserting reset %d\n", i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("error freeing reset %d\n", i); + return ret; + } + } + + /* disable dma controller */ + clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + /* alloc channel private data pointers */ + priv->ch_priv = calloc(priv->n_channels, + sizeof(struct bcm6348_chan_priv*)); + if (!priv->ch_priv) + return -ENOMEM; + + /* stop dma channels */ + for (ch = 0; ch < priv->n_channels; ch++) + bcm6348_iudma_chan_stop(priv, ch); + + /* enable dma controller */ + setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + return 0; +} + +U_BOOT_DRIVER(bcm6348_iudma) = { + .name = "bcm6348_iudma", + .id = UCLASS_DMA, + .of_match = bcm6348_iudma_ids, + .ops = &bcm6348_iudma_ops, + .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv), + .probe = bcm6348_iudma_probe, +}; diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index a33f7d52da..9c961cf1e2 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -2,19 +2,192 @@ /* * Direct Memory Access U-Class driver * - * (C) Copyright 2015 - * Texas Instruments Incorporated, + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 - 2018 Texas Instruments Incorporated + * Written by Mugunthan V N * * Author: Mugunthan V N */ #include -#include #include -#include -#include +#include +#include +#include #include +#ifdef CONFIG_DMA_CHANNELS +static inline struct dma_ops *dma_dev_ops(struct udevice *dev) +{ + return (struct dma_ops *)dev->driver->ops; +} + +# if CONFIG_IS_ENABLED(OF_CONTROL) +static int dma_of_xlate_default(struct dma *dma, + struct ofnode_phandle_args *args) +{ + debug("%s(dma=%p)\n", __func__, dma); + + if (args->args_count > 1) { + pr_err("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + dma->id = args->args[0]; + else + dma->id = 0; + + return 0; +} + +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *dev_dma; + const struct dma_ops *ops; + + debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma); + + assert(dma); + dma->dev = NULL; + + ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index, + &args); + if (ret) { + pr_err("%s: dev_read_phandle_with_args failed: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, &dev_dma); + if (ret) { + pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n", + __func__, ret); + return ret; + } + + dma->dev = dev_dma; + + ops = dma_dev_ops(dev_dma); + + if (ops->of_xlate) + ret = ops->of_xlate(dma, &args); + else + ret = dma_of_xlate_default(dma, &args); + if (ret) { + pr_err("of_xlate() failed: %d\n", ret); + return ret; + } + + return dma_request(dev_dma, dma); +} + +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma) +{ + int index; + + debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma); + dma->dev = NULL; + + index = dev_read_stringlist_search(dev, "dma-names", name); + if (index < 0) { + pr_err("dev_read_stringlist_search() failed: %d\n", index); + return index; + } + + return dma_get_by_index(dev, index, dma); +} +# endif /* OF_CONTROL */ + +int dma_request(struct udevice *dev, struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dev); + + debug("%s(dev=%p, dma=%p)\n", __func__, dev, dma); + + dma->dev = dev; + + if (!ops->request) + return 0; + + return ops->request(dma); +} + +int dma_free(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->free) + return 0; + + return ops->free(dma); +} + +int dma_enable(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->enable) + return -ENOSYS; + + return ops->enable(dma); +} + +int dma_disable(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->disable) + return -ENOSYS; + + return ops->disable(dma); +} + +int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->prepare_rcv_buf) + return -1; + + return ops->prepare_rcv_buf(dma, dst, size); +} + +int dma_receive(struct dma *dma, void **dst, void *metadata) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->receive) + return -ENOSYS; + + return ops->receive(dma, dst, metadata); +} + +int dma_send(struct dma *dma, void *src, size_t len, void *metadata) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->send) + return -ENOSYS; + + return ops->send(dma, src, len, metadata); +} +#endif /* CONFIG_DMA_CHANNELS */ + int dma_get_device(u32 transfer_type, struct udevice **devp) { struct udevice *dev; diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c new file mode 100644 index 0000000000..8fcef1863e --- /dev/null +++ b/drivers/dma/sandbox-dma-test.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Direct Memory Access U-Class Simulation driver + * + * Copyright (C) 2018 Texas Instruments Incorporated + * + * Author: Grygorii Strashko + */ + +#include +#include +#include +#include +#include +#include + +#define SANDBOX_DMA_CH_CNT 3 +#define SANDBOX_DMA_BUF_SIZE 1024 + +struct sandbox_dma_chan { + struct sandbox_dma_dev *ud; + char name[20]; + u32 id; + enum dma_direction dir; + bool in_use; + bool enabled; +}; + +struct sandbox_dma_dev { + struct device *dev; + u32 ch_count; + struct sandbox_dma_chan channels[SANDBOX_DMA_CH_CNT]; + uchar buf[SANDBOX_DMA_BUF_SIZE]; + uchar *buf_rx; + size_t data_len; + u32 meta; +}; + +static int sandbox_dma_transfer(struct udevice *dev, int direction, + void *dst, void *src, size_t len) +{ + memcpy(dst, src, len); + + return 0; +} + +static int sandbox_dma_of_xlate(struct dma *dma, + struct ofnode_phandle_args *args) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + debug("%s(dma id=%u)\n", __func__, args->args[0]); + + if (args->args[0] >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + + dma->id = args->args[0]; + + uc = &ud->channels[dma->id]; + + if (dma->id == 1) + uc->dir = DMA_MEM_TO_DEV; + else if (dma->id == 2) + uc->dir = DMA_DEV_TO_MEM; + else + uc->dir = DMA_MEM_TO_MEM; + debug("%s(dma id=%lu dir=%d)\n", __func__, dma->id, uc->dir); + + return 0; +} + +static int sandbox_dma_request(struct dma *dma) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + + uc = &ud->channels[dma->id]; + if (uc->in_use) + return -EBUSY; + + uc->in_use = true; + debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use); + + return 0; +} + +static int sandbox_dma_free(struct dma *dma) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + + uc = &ud->channels[dma->id]; + if (!uc->in_use) + return -EINVAL; + + uc->in_use = false; + ud->buf_rx = NULL; + ud->data_len = 0; + debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use); + + return 0; +} + +static int sandbox_dma_enable(struct dma *dma) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + + uc = &ud->channels[dma->id]; + if (!uc->in_use) + return -EINVAL; + if (uc->enabled) + return -EINVAL; + + uc->enabled = true; + debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled); + + return 0; +} + +static int sandbox_dma_disable(struct dma *dma) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + + uc = &ud->channels[dma->id]; + if (!uc->in_use) + return -EINVAL; + if (!uc->enabled) + return -EINVAL; + + uc->enabled = false; + debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled); + + return 0; +} + +static int sandbox_dma_send(struct dma *dma, + void *src, size_t len, void *metadata) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + if (!src || !metadata) + return -EINVAL; + + debug("%s(dma id=%lu)\n", __func__, dma->id); + + uc = &ud->channels[dma->id]; + if (uc->dir != DMA_MEM_TO_DEV) + return -EINVAL; + if (!uc->in_use) + return -EINVAL; + if (!uc->enabled) + return -EINVAL; + if (len >= SANDBOX_DMA_BUF_SIZE) + return -EINVAL; + + memcpy(ud->buf, src, len); + ud->data_len = len; + ud->meta = *((u32 *)metadata); + + debug("%s(dma id=%lu len=%zu meta=%08x)\n", + __func__, dma->id, len, ud->meta); + + return 0; +} + +static int sandbox_dma_receive(struct dma *dma, void **dst, void *metadata) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + struct sandbox_dma_chan *uc; + + if (dma->id >= SANDBOX_DMA_CH_CNT) + return -EINVAL; + if (!dst || !metadata) + return -EINVAL; + + uc = &ud->channels[dma->id]; + if (uc->dir != DMA_DEV_TO_MEM) + return -EINVAL; + if (!uc->in_use) + return -EINVAL; + if (!uc->enabled) + return -EINVAL; + if (!ud->data_len) + return 0; + + if (ud->buf_rx) { + memcpy(ud->buf_rx, ud->buf, ud->data_len); + *dst = ud->buf_rx; + } else { + memcpy(*dst, ud->buf, ud->data_len); + } + + *((u32 *)metadata) = ud->meta; + + debug("%s(dma id=%lu len=%zu meta=%08x %p)\n", + __func__, dma->id, ud->data_len, ud->meta, *dst); + + return ud->data_len; +} + +static int sandbox_dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) +{ + struct sandbox_dma_dev *ud = dev_get_priv(dma->dev); + + ud->buf_rx = dst; + + return 0; +} + +static const struct dma_ops sandbox_dma_ops = { + .transfer = sandbox_dma_transfer, + .of_xlate = sandbox_dma_of_xlate, + .request = sandbox_dma_request, + .free = sandbox_dma_free, + .enable = sandbox_dma_enable, + .disable = sandbox_dma_disable, + .send = sandbox_dma_send, + .receive = sandbox_dma_receive, + .prepare_rcv_buf = sandbox_dma_prepare_rcv_buf, +}; + +static int sandbox_dma_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct sandbox_dma_dev *ud = dev_get_priv(dev); + int i, ret = 0; + + uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | + DMA_SUPPORTS_MEM_TO_DEV | + DMA_SUPPORTS_DEV_TO_MEM; + + ud->ch_count = SANDBOX_DMA_CH_CNT; + ud->buf_rx = NULL; + ud->meta = 0; + ud->data_len = 0; + + pr_err("Number of channels: %u\n", ud->ch_count); + + for (i = 0; i < ud->ch_count; i++) { + struct sandbox_dma_chan *uc = &ud->channels[i]; + + uc->ud = ud; + uc->id = i; + sprintf(uc->name, "DMA chan%d\n", i); + uc->in_use = false; + uc->enabled = false; + } + + return ret; +} + +static const struct udevice_id sandbox_dma_ids[] = { + { .compatible = "sandbox,dma" }, + { } +}; + +U_BOOT_DRIVER(sandbox_dma) = { + .name = "sandbox-dma", + .id = UCLASS_DMA, + .of_match = sandbox_dma_ids, + .ops = &sandbox_dma_ops, + .probe = sandbox_dma_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_dma_dev), +}; diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index 2131e10a40..7e11b13e45 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index feaea8130f..7d8f161b26 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,6 +1,10 @@ config FIRMWARE bool "Enable Firmware driver support" +config SPL_ARM_PSCI_FW + bool + select FIRMWARE + config ARM_PSCI_FW bool select FIRMWARE diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 6cb83582b9..6c3e129685 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -1,4 +1,4 @@ obj-$(CONFIG_FIRMWARE) += firmware-uclass.o -obj-$(CONFIG_ARM_PSCI_FW) += psci.o +obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_SANDBOX) += firmware-sandbox.o diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 2cb35f356f..c8c47acfd3 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -9,31 +9,38 @@ #include #include #include +#include #include #include #include #include #include -psci_fn *invoke_psci_fn; +#define DRIVER_NAME "psci" -static unsigned long __invoke_psci_fn_hvc(unsigned long function_id, - unsigned long arg0, unsigned long arg1, - unsigned long arg2) +#define PSCI_METHOD_HVC 1 +#define PSCI_METHOD_SMC 2 + +int __efi_runtime_data psci_method; + +unsigned long __efi_runtime invoke_psci_fn + (unsigned long function_id, unsigned long arg0, + unsigned long arg1, unsigned long arg2) { struct arm_smccc_res res; - arm_smccc_hvc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); - return res.a0; -} - -static unsigned long __invoke_psci_fn_smc(unsigned long function_id, - unsigned long arg0, unsigned long arg1, - unsigned long arg2) -{ - struct arm_smccc_res res; - - arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + /* + * In the __efi_runtime we need to avoid the switch statement. In some + * cases the compiler creates lookup tables to implement switch. These + * tables are not correctly relocated when SetVirtualAddressMap is + * called. + */ + if (psci_method == PSCI_METHOD_SMC) + arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + else if (psci_method == PSCI_METHOD_HVC) + arm_smccc_hvc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + else + res.a0 = PSCI_RET_DISABLED; return res.a0; } @@ -67,9 +74,9 @@ static int psci_probe(struct udevice *dev) } if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; + psci_method = PSCI_METHOD_HVC; } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; + psci_method = PSCI_METHOD_SMC; } else { pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; @@ -78,6 +85,67 @@ static int psci_probe(struct udevice *dev) return 0; } +/** + * void do_psci_probe() - probe PSCI firmware driver + * + * Ensure that psci_method is initialized. + */ +static void __maybe_unused do_psci_probe(void) +{ + struct udevice *dev; + + uclass_get_device_by_name(UCLASS_FIRMWARE, DRIVER_NAME, &dev); +} + +#if IS_ENABLED(CONFIG_EFI_LOADER) && IS_ENABLED(CONFIG_PSCI_RESET) +efi_status_t efi_reset_system_init(void) +{ + do_psci_probe(); + return EFI_SUCCESS; +} + +void __efi_runtime EFIAPI efi_reset_system(enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, + void *reset_data) +{ + if (reset_type == EFI_RESET_COLD || + reset_type == EFI_RESET_WARM || + reset_type == EFI_RESET_PLATFORM_SPECIFIC) { + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); + } else if (reset_type == EFI_RESET_SHUTDOWN) { + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0); + } + while (1) + ; +} +#endif /* IS_ENABLED(CONFIG_EFI_LOADER) && IS_ENABLED(CONFIG_PSCI_RESET) */ + +#ifdef CONFIG_PSCI_RESET +void reset_misc(void) +{ + do_psci_probe(); + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); +} +#endif /* CONFIG_PSCI_RESET */ + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + do_psci_probe(); + + puts("poweroff ...\n"); + udelay(50000); /* wait 50 ms */ + + disable_interrupts(); + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0); + enable_interrupts(); + + log_err("Power off not supported on this platform\n"); + return CMD_RET_FAILURE; +} +#endif + static const struct udevice_id psci_of_match[] = { { .compatible = "arm,psci" }, { .compatible = "arm,psci-0.2" }, @@ -86,7 +154,7 @@ static const struct udevice_id psci_of_match[] = { }; U_BOOT_DRIVER(psci) = { - .name = "psci", + .name = DRIVER_NAME, .id = UCLASS_FIRMWARE, .of_match = psci_of_match, .bind = psci_bind, diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 50e901973d..8f59193e3c 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -31,6 +31,17 @@ config FPGA_CYCLON2 Enable FPGA driver for loading bitstream in BIT and BIN format on Altera Cyclone II device. +config FPGA_STRATIX10 + bool "Enable Altera FPGA driver for Stratix 10" + depends on TARGET_SOCFPGA_STRATIX10 + select FPGA_ALTERA + help + Say Y here to enable the Altera Stratix 10 FPGA specific driver + + This provides common functionality for Altera Stratix 10 devices. + Enable FPGA driver for writing bitstream into Altera Stratix10 + device. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 97d7d5d9be..5a778c10e8 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o +obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 9605554c6a..7c8f518509 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -39,6 +39,9 @@ static const struct altera_fpga { #if defined(CONFIG_FPGA_STRATIX_V) { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, #endif +#if defined(CONFIG_FPGA_STRATIX10) + { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL }, +#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif @@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc) case fast_passive_parallel_security: printf("Fast Passive Parallel with Security (FPPS)\n"); break; + case secure_device_manager_mailbox: + puts("Secure Device Manager (SDM) Mailbox\n"); + break; /* Add new interface types here */ default: printf("Unsupported interface type, %d\n", desc->iface); diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c new file mode 100644 index 0000000000..aae052130e --- /dev/null +++ b/drivers/fpga/stratix10.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation + */ + +#include +#include +#include + +#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 +#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 + +static const struct mbox_cfgstat_state { + int err_no; + const char *error_name; +} mbox_cfgstat_state[] = { + {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."}, + {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."}, + {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"}, + {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"}, + {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"}, + {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"}, + {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"}, + {MBOX_RESP_ERROR, "Mailbox general error!"}, + {-ETIMEDOUT, "I/O timeout error"}, + {-1, "Unknown error!"} +}; + +#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state) + +static const char *mbox_cfgstat_to_str(int err) +{ + int i; + + for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) { + if (mbox_cfgstat_state[i].err_no == err) + return mbox_cfgstat_state[i].error_name; + } + + return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name; +} + +/* + * Add the ongoing transaction's command ID into pending list and return + * the command ID for next transfer. + */ +static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (xfer_pending_list[i]) + continue; + xfer_pending_list[i] = id; + debug("ID(%d) added to transaction pending list\n", id); + /* + * Increment command ID for next transaction. + * Valid command ID (4 bits) is from 1 to 15. + */ + id = (id % 15) + 1; + break; + } + + return id; +} + +/* + * Check whether response ID match the command ID in the transfer + * pending list. If a match is found in the transfer pending list, + * it clears the transfer pending list and return the matched + * command ID. + */ +static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size, + u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (id != xfer_pending_list[i]) + continue; + xfer_pending_list[i] = 0; + return id; + } + + return 0; +} + +/* + * Polling the FPGA configuration status. + * Return 0 for success, non-zero for error. + */ +static int reconfig_status_polling_resp(void) +{ + int ret; + unsigned long start = get_timer(0); + + while (1) { + ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); + if (!ret) + return 0; /* configuration success */ + + if (ret != MBOX_CFGSTAT_STATE_CONFIG) + return ret; + + if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) + break; /* time out */ + + puts("."); + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + } + + return -ETIMEDOUT; +} + +static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count, + u32 *resp_buf, u32 buf_size, u32 client_id) +{ + u32 buf[MBOX_RESP_BUFFER_SIZE]; + u32 mbox_hdr; + u32 resp_len; + u32 hdr_len; + u32 i; + + if (*resp_count < buf_size) { + u32 rcv_len_max = buf_size - *resp_count; + + if (rcv_len_max > MBOX_RESP_BUFFER_SIZE) + rcv_len_max = MBOX_RESP_BUFFER_SIZE; + resp_len = mbox_rcv_resp(buf, rcv_len_max); + + for (i = 0; i < resp_len; i++) { + resp_buf[(*w_index)++] = buf[i]; + *w_index %= buf_size; + (*resp_count)++; + } + } + + /* No response in buffer */ + if (*resp_count == 0) + return 0; + + mbox_hdr = resp_buf[*r_index]; + + hdr_len = MBOX_RESP_LEN_GET(mbox_hdr); + + /* Insufficient header length to return a mailbox header */ + if ((*resp_count - 1) < hdr_len) + return 0; + + *r_index += (hdr_len + 1); + *r_index %= buf_size; + *resp_count -= (hdr_len + 1); + + /* Make sure response belongs to us */ + if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id) + return 0; + + return mbox_hdr; +} + +/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */ +static int send_reconfig_data(const void *rbf_data, size_t rbf_size, + u32 xfer_max, u32 buf_size_max) +{ + u32 response_buffer[MBOX_RESP_BUFFER_SIZE]; + u32 xfer_pending[MBOX_RESP_BUFFER_SIZE]; + u32 resp_rindex = 0; + u32 resp_windex = 0; + u32 resp_count = 0; + u32 xfer_count = 0; + u8 resp_err = 0; + u8 cmd_id = 1; + u32 args[3]; + int ret; + + debug("SDM xfer_max = %d\n", xfer_max); + debug("SDM buf_size_max = %x\n\n", buf_size_max); + + memset(xfer_pending, 0, sizeof(xfer_pending)); + + while (rbf_size || xfer_count) { + if (!resp_err && rbf_size && xfer_count < xfer_max) { + args[0] = MBOX_ARG_DESC_COUNT(1); + args[1] = (u64)rbf_data; + if (rbf_size >= buf_size_max) { + args[2] = buf_size_max; + rbf_size -= buf_size_max; + rbf_data += buf_size_max; + } else { + args[2] = (u64)rbf_size; + rbf_size = 0; + } + + ret = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, + MBOX_CMD_INDIRECT, 3, args); + if (ret) { + resp_err = 1; + } else { + xfer_count++; + cmd_id = add_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + cmd_id); + } + puts("."); + } else { + u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex, + &resp_count, + response_buffer, + MBOX_RESP_BUFFER_SIZE, + MBOX_CLIENT_ID_UBOOT); + + /* + * If no valid response header found or + * non-zero length from RECONFIG_DATA + */ + if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr)) + continue; + + /* Check for response's status */ + if (!resp_err) { + ret = MBOX_RESP_ERR_GET(resp_hdr); + debug("Response error code: %08x\n", ret); + /* Error in response */ + if (ret) + resp_err = 1; + } + + ret = get_and_clr_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + MBOX_RESP_ID_GET(resp_hdr)); + if (ret) { + /* Claim and reuse the ID */ + cmd_id = (u8)ret; + xfer_count--; + } + + if (resp_err && !xfer_count) + return ret; + } + } + + return 0; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for success, non-zero for error. + */ +int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + int ret; + u32 resp_len = 2; + u32 resp_buf[2]; + + debug("Sending MBOX_RECONFIG...\n"); + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, resp_buf); + if (ret) { + puts("Failure in RECONFIG mailbox command!\n"); + return ret; + } + + ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]); + if (ret) { + printf("RECONFIG_DATA error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + + debug("Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(); + if (ret) { + printf("RECONFIG_STATUS Error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + puts("FPGA reconfiguration OK!\n"); + + return ret; +} diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5cd8b34400..c8c6c60623 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -99,6 +99,13 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config MSCC_BITBANG_SPI_GPIO + bool "Microsemi bitbang spi GPIO driver" + depends on DM_GPIO && SOC_VCOREIII + help + Support controlling the GPIO used for SPI bitbang by software. Can + be used by the VCoreIII SoCs, but it was mainly useful for Luton. + config MSM_GPIO bool "Qualcomm GPIO driver" depends on DM_GPIO @@ -314,4 +321,12 @@ config MPC8XXX_GPIO Aside from the standard functions of input/output mode, and output value setting, the open-drain feature, which can configure individual GPIOs to work as open-drain outputs, is supported. + +config MT7621_GPIO + bool "MediaTek MT7621 GPIO driver" + depends on DM_GPIO && ARCH_MT7620 + default y + help + Say yes here to support MediaTek MT7621 compatible GPIOs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index f186120684..61feda1537 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -58,3 +58,5 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o +obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o +obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 68836a7902..e55fb4ac73 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -180,6 +180,13 @@ static int gpio_dwapb_bind(struct udevice *dev) plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0); plat->name = fdt_stringlist_get(blob, node, "bank-name", 0, NULL); + if (!plat->name) { + /* + * Fall back to node name. This means accessing pins + * via bank name won't work. + */ + plat->name = fdt_get_name(blob, node, NULL); + } ret = device_bind(dev, dev->driver, plat->name, plat, -1, &subdev); diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c b/drivers/gpio/gpio-mscc-bitbang-spi.c new file mode 100644 index 0000000000..b675f9052c --- /dev/null +++ b/drivers/gpio/gpio-mscc-bitbang-spi.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: + * License: Dual MIT/GPL + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include + +enum { + SDI, + CS0, + CS1, + CS2, + CS3, + SDO, + SCK +}; + +static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 }; + +#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */ +#define SW_SPI_CS0_OE BIT(1) +#define SW_SPI_SDO_OE BIT(9) +#define SW_SPI_SCK_OE BIT(11) +#define SW_PIN_CTRL_MODE BIT(13) + +struct mscc_bb_spi_gpio { + void __iomem *regs; + u32 cache_val; +}; + +static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + + if (val) + gpio->cache_val |= BIT(pinmap[oft]); + else + gpio->cache_val &= ~BIT(pinmap[oft]); + + writel(gpio->cache_val, gpio->regs); + + return 0; +} + +static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft, + int val) +{ + if (oft == 0) { + pr_err("SW_SPI_DSI can't be used as output\n"); + return -ENOTSUPP; + } + + mscc_bb_spi_gpio_set(dev, oft, val); + + return 0; +} + +static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft) +{ + return 0; +} + +static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + u32 val = readl(gpio->regs); + + return !!(val & BIT(pinmap[oft])); +} + +static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = { + .direction_output = mscc_bb_spi_gpio_direction_output, + .direction_input = mscc_bb_spi_gpio_direction_input, + .set_value = mscc_bb_spi_gpio_set, + .get_value = mscc_bb_spi_gpio_get, +}; + +static int mscc_bb_spi_gpio_probe(struct udevice *dev) +{ + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + gpio->regs = dev_remap_addr(dev); + if (!gpio->regs) + return -EINVAL; + + uc_priv->bank_name = dev->name; + uc_priv->gpio_count = ARRAY_SIZE(pinmap); + /* + * Enable software mode to control the SPI pin, enables the + * output mode for most of the pin and initialize the cache + * value in the same time + */ + + gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE | + SW_SPI_CS0_OE; + writel(gpio->cache_val, gpio->regs); + + return 0; +} + +static const struct udevice_id mscc_bb_spi_gpio_ids[] = { + {.compatible = "mscc,spi-bitbang-gpio"}, + {} +}; + +U_BOOT_DRIVER(gpio_mscc_bb_spi) = { + .name = "gpio-mscc-spi-bitbang", + .id = UCLASS_GPIO, + .ops = &mscc_bb_spi_gpio_ops, + .probe = mscc_bb_spi_gpio_probe, + .of_match = of_match_ptr(mscc_bb_spi_gpio_ids), + .priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio), +}; diff --git a/drivers/gpio/mt7621_gpio.c b/drivers/gpio/mt7621_gpio.c new file mode 100644 index 0000000000..54d313d6f1 --- /dev/null +++ b/drivers/gpio/mt7621_gpio.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese + * + * Based on the Linux driver version which is: + * Copyright (C) 2009-2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MTK_MAX_BANK 3 +#define MTK_BANK_WIDTH 32 + +enum mediatek_gpio_reg { + GPIO_REG_CTRL = 0, + GPIO_REG_POL, + GPIO_REG_DATA, + GPIO_REG_DSET, + GPIO_REG_DCLR, + GPIO_REG_REDGE, + GPIO_REG_FEDGE, + GPIO_REG_HLVL, + GPIO_REG_LLVL, + GPIO_REG_STAT, + GPIO_REG_EDGE, +}; + +static void __iomem *mediatek_gpio_membase; + +struct mediatek_gpio_platdata { + char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */ + int gpio_count; + int bank; +}; + +static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg) +{ + return (reg * 0x10) + (plat->bank * 0x4); +} + +static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + + return !!(ioread32(mediatek_gpio_membase + + reg_offs(plat, GPIO_REG_DATA)) & BIT(offset)); +} + +static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + + iowrite32(BIT(offset), mediatek_gpio_membase + + reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR)); + + return 0; +} + +static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + + clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), + BIT(offset)); + + return 0; +} + +static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + + setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), + BIT(offset)); + mediatek_gpio_set_value(dev, offset, value); + + return 0; +} + +static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + u32 t; + + t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL)); + if (t & BIT(offset)) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops gpio_mediatek_ops = { + .direction_input = mediatek_gpio_direction_input, + .direction_output = mediatek_gpio_direction_output, + .get_value = mediatek_gpio_get_value, + .set_value = mediatek_gpio_set_value, + .get_function = mediatek_gpio_get_function, +}; + +static int gpio_mediatek_probe(struct udevice *dev) +{ + struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* Tell the uclass how many GPIOs we have */ + if (plat) { + uc_priv->gpio_count = plat->gpio_count; + uc_priv->bank_name = plat->bank_name; + } + + return 0; +} + +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child + * device for each Mediatek bank. + */ +static int gpio_mediatek_bind(struct udevice *parent) +{ + struct mediatek_gpio_platdata *plat = parent->platdata; + ofnode node; + int bank = 0; + int ret; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + mediatek_gpio_membase = dev_remap_addr(parent); + if (!mediatek_gpio_membase) + return -EINVAL; + + for (node = dev_read_first_subnode(parent); ofnode_valid(node); + node = dev_read_next_subnode(node)) { + struct mediatek_gpio_platdata *plat; + struct udevice *dev; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->bank_name[0] = 'P'; + plat->bank_name[1] = 'A' + bank; + plat->bank_name[2] = '\0'; + plat->gpio_count = MTK_BANK_WIDTH; + plat->bank = bank; + + ret = device_bind(parent, parent->driver, + plat->bank_name, plat, -1, &dev); + if (ret) + return ret; + + dev->node = node; + bank++; + } + + return 0; +} + +static const struct udevice_id mediatek_gpio_ids[] = { + { .compatible = "mtk,mt7621-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_mediatek) = { + .name = "gpio_mediatek", + .id = UCLASS_GPIO, + .ops = &gpio_mediatek_ops, + .of_match = mediatek_gpio_ids, + .bind = gpio_mediatek_bind, + .probe = gpio_mediatek_probe, +}; diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index b820160ae7..8bd30c75b2 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif @@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif @@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 555eba2662..0031415d03 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -372,7 +372,9 @@ U_BOOT_DRIVER(gpio_omap) = { .ops = &gpio_omap_ops, .probe = omap_gpio_probe, .priv_auto_alloc_size = sizeof(struct gpio_bank), +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif /* CONFIG_DM_GPIO */ diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 0bb484498a..341527acc5 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -130,6 +130,25 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val) return ret; } +static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val) +{ + struct pca953x_info *info = dev_get_platdata(dev); + int ret = 0; + + if (info->gpio_count <= 8) { + ret = dm_i2c_write(dev, reg, val, 1); + } else if (info->gpio_count <= 16) { + ret = dm_i2c_write(dev, reg << 1, val, info->bank_count); + } else if (info->gpio_count == 40) { + /* Auto increment */ + ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count); + } else { + return -EINVAL; + } + + return ret; +} + static int pca953x_is_output(struct udevice *dev, int offset) { struct pca953x_info *info = dev_get_platdata(dev); @@ -251,6 +270,7 @@ static int pca953x_probe(struct udevice *dev) int ret; int size; const u8 *tmp; + u8 val[MAX_BANK]; addr = dev_read_addr(dev); if (addr == 0) @@ -296,6 +316,14 @@ static int pca953x_probe(struct udevice *dev) snprintf(name, sizeof(name), "gpio@%x_", info->addr); } + /* Clear the polarity registers to no invert */ + memset(val, 0, MAX_BANK); + ret = pca953x_write_regs(dev, PCA953X_INVERT, val); + if (ret < 0) { + dev_err(dev, "Error writing invert register\n"); + return ret; + } + str = strdup(name); if (!str) return -ENOMEM; diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c index 4c0786fff8..f160b4e689 100644 --- a/drivers/gpio/stm32f7_gpio.c +++ b/drivers/gpio/stm32f7_gpio.c @@ -15,17 +15,45 @@ #include #include -#define STM32_GPIOS_PER_BANK 16 #define MODE_BITS(gpio_pin) (gpio_pin * 2) #define MODE_BITS_MASK 3 #define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16)) +/* + * convert gpio offset to gpio index taking into account gpio holes + * into gpio bank + */ +int stm32_offset_to_index(struct udevice *dev, unsigned int offset) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + int idx = 0; + int i; + + for (i = 0; i < STM32_GPIOS_PER_BANK; i++) { + if (priv->gpio_range & BIT(i)) { + if (idx == offset) + return idx; + idx++; + } + } + /* shouldn't happen */ + return -EINVAL; +} + static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int bits_index = MODE_BITS(offset); - int mask = MODE_BITS_MASK << bits_index; + int bits_index; + int mask; + int idx; + + idx = stm32_offset_to_index(dev, offset); + if (idx < 0) + return idx; + + bits_index = MODE_BITS(idx); + mask = MODE_BITS_MASK << bits_index; clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index); @@ -37,12 +65,20 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset, { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; - int bits_index = MODE_BITS(offset); - int mask = MODE_BITS_MASK << bits_index; + int bits_index; + int mask; + int idx; + + idx = stm32_offset_to_index(dev, offset); + if (idx < 0) + return idx; + + bits_index = MODE_BITS(idx); + mask = MODE_BITS_MASK << bits_index; clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index); - writel(BSRR_BIT(offset, value), ®s->bsrr); + writel(BSRR_BIT(idx, value), ®s->bsrr); return 0; } @@ -51,33 +87,75 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; + int idx; - return readl(®s->idr) & BIT(offset) ? 1 : 0; + idx = stm32_offset_to_index(dev, offset); + if (idx < 0) + return idx; + + return readl(®s->idr) & BIT(idx) ? 1 : 0; } static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct stm32_gpio_priv *priv = dev_get_priv(dev); struct stm32_gpio_regs *regs = priv->regs; + int idx; - writel(BSRR_BIT(offset, value), ®s->bsrr); + idx = stm32_offset_to_index(dev, offset); + if (idx < 0) + return idx; + + writel(BSRR_BIT(idx, value), ®s->bsrr); return 0; } +static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + int bits_index; + int mask; + int idx; + u32 mode; + + idx = stm32_offset_to_index(dev, offset); + if (idx < 0) + return idx; + + bits_index = MODE_BITS(idx); + mask = MODE_BITS_MASK << bits_index; + + mode = (readl(®s->moder) & mask) >> bits_index; + if (mode == STM32_GPIO_MODE_OUT) + return GPIOF_OUTPUT; + if (mode == STM32_GPIO_MODE_IN) + return GPIOF_INPUT; + if (mode == STM32_GPIO_MODE_AN) + return GPIOF_UNUSED; + + return GPIOF_FUNC; +} + static const struct dm_gpio_ops gpio_stm32_ops = { .direction_input = stm32_gpio_direction_input, .direction_output = stm32_gpio_direction_output, .get_value = stm32_gpio_get_value, .set_value = stm32_gpio_set_value, + .get_function = stm32_gpio_get_function, }; static int gpio_stm32_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + struct clk clk; fdt_addr_t addr; const char *name; + int ret; + int i; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -88,14 +166,25 @@ static int gpio_stm32_probe(struct udevice *dev) if (!name) return -EINVAL; uc_priv->bank_name = name; - uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", - STM32_GPIOS_PER_BANK); - debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs, - uc_priv->bank_name); -#ifdef CONFIG_CLK - struct clk clk; - int ret; + i = 0; + ret = dev_read_phandle_with_args(dev, "gpio-ranges", + NULL, 3, i, &args); + + while (ret != -ENOENT) { + priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1, + args.args[0]); + + uc_priv->gpio_count += args.args[2]; + + ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, + ++i, &args); + } + + dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n", + (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count, + priv->gpio_range); + ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; @@ -107,7 +196,6 @@ static int gpio_stm32_probe(struct udevice *dev) return ret; } debug("clock enabled for device %s\n", dev->name); -#endif return 0; } @@ -123,6 +211,6 @@ U_BOOT_DRIVER(gpio_stm32) = { .of_match = stm32_gpio_ids, .probe = gpio_stm32_probe, .ops = &gpio_stm32_ops, - .flags = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS, + .flags = DM_UC_FLAG_SEQ_ALIAS, .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv), }; diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c index 1f0e8d51da..6626b5415a 100644 --- a/drivers/gpio/tegra186_gpio.c +++ b/drivers/gpio/tegra186_gpio.c @@ -281,5 +281,4 @@ U_BOOT_DRIVER(tegra186_gpio) = { .bind = tegra186_gpio_bind, .probe = tegra186_gpio_probe, .ops = &tegra186_gpio_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 302efddc27..a730f5c4fe 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -378,5 +378,4 @@ U_BOOT_DRIVER(gpio_tegra) = { .probe = gpio_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_port_info), .ops = &gpio_tegra_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig new file mode 100644 index 0000000000..96d4f5d6ca --- /dev/null +++ b/drivers/hwspinlock/Kconfig @@ -0,0 +1,24 @@ +menu "Hardware Spinlock Support" + +config DM_HWSPINLOCK + bool "Enable U-Boot hardware spinlock support" + help + This option enables U-Boot hardware spinlock support + +config HWSPINLOCK_SANDBOX + bool "Enable Hardware Spinlock support for Sandbox" + depends on SANDBOX && DM_HWSPINLOCK + help + Enable hardware spinlock support in Sandbox. This is a dummy device that + can be probed and support all the methods of HWSPINLOCK, but does not + really do anything. + +config HWSPINLOCK_STM32 + bool "Enable Hardware Spinlock support for STM32" + depends on ARCH_STM32MP && DM_HWSPINLOCK + help + Enable hardware spinlock support in STM32MP. Hardware spinlocks are + hardware mutex which provide a synchronisation mechanism for the + various processors on the SoC. + +endmenu diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile new file mode 100644 index 0000000000..289b12a256 --- /dev/null +++ b/drivers/hwspinlock/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved + +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o +obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c new file mode 100644 index 0000000000..195f079707 --- /dev/null +++ b/drivers/hwspinlock/hwspinlock-uclass.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +static inline const struct hwspinlock_ops * +hwspinlock_dev_ops(struct udevice *dev) +{ + return (const struct hwspinlock_ops *)dev->driver->ops; +} + +static int hwspinlock_of_xlate_default(struct hwspinlock *hws, + struct ofnode_phandle_args *args) +{ + if (args->args_count > 1) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + hws->id = args->args[0]; + else + hws->id = 0; + + return 0; +} + +int hwspinlock_get_by_index(struct udevice *dev, int index, + struct hwspinlock *hws) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *dev_hws; + const struct hwspinlock_ops *ops; + + assert(hws); + hws->dev = NULL; + + ret = dev_read_phandle_with_args(dev, "hwlocks", "#hwlock-cells", 1, + index, &args); + if (ret) { + dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_HWSPINLOCK, + args.node, &dev_hws); + if (ret) { + dev_dbg(dev, + "%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + hws->dev = dev_hws; + + ops = hwspinlock_dev_ops(dev_hws); + + if (ops->of_xlate) + ret = ops->of_xlate(hws, &args); + else + ret = hwspinlock_of_xlate_default(hws, &args); + if (ret) + dev_dbg(dev, "of_xlate() failed: %d\n", ret); + + return ret; +} + +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout) +{ + const struct hwspinlock_ops *ops; + ulong start; + int ret; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->lock) + return -ENOSYS; + + start = get_timer(0); + do { + ret = ops->lock(hws->dev, hws->id); + if (!ret) + return ret; + + if (ops->relax) + ops->relax(hws->dev); + } while (get_timer(start) < timeout); + + return -ETIMEDOUT; +} + +int hwspinlock_unlock(struct hwspinlock *hws) +{ + const struct hwspinlock_ops *ops; + + assert(hws); + + if (!hws->dev) + return -EINVAL; + + ops = hwspinlock_dev_ops(hws->dev); + if (!ops->unlock) + return -ENOSYS; + + return ops->unlock(hws->dev, hws->id); +} + +static int hwspinlock_post_bind(struct udevice *dev) +{ +#if defined(CONFIG_NEEDS_MANUAL_RELOC) + struct hwspinlock_ops *ops = device_get_ops(dev); + static int reloc_done; + + if (!reloc_done) { + if (ops->lock) + ops->lock += gd->reloc_off; + if (ops->unlock) + ops->unlock += gd->reloc_off; + if (ops->relax) + ops->relax += gd->reloc_off; + + reloc_done++; + } +#endif + return 0; +} + +UCLASS_DRIVER(hwspinlock) = { + .id = UCLASS_HWSPINLOCK, + .name = "hwspinlock", + .post_bind = hwspinlock_post_bind, +}; diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c new file mode 100644 index 0000000000..be920f5f99 --- /dev/null +++ b/drivers/hwspinlock/sandbox_hwspinlock.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include + +static int sandbox_lock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (state->hwspinlock) + return -1; + + state->hwspinlock = true; + + return 0; +} + +static int sandbox_unlock(struct udevice *dev, int index) +{ + struct sandbox_state *state = state_get_current(); + + if (index != 0) + return -1; + + if (!state->hwspinlock) + return -1; + + state->hwspinlock = false; + + return 0; +} + +static const struct hwspinlock_ops sandbox_hwspinlock_ops = { + .lock = sandbox_lock, + .unlock = sandbox_unlock, +}; + +static const struct udevice_id sandbox_hwspinlock_ids[] = { + { .compatible = "sandbox,hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_sandbox) = { + .name = "hwspinlock_sandbox", + .id = UCLASS_HWSPINLOCK, + .of_match = sandbox_hwspinlock_ids, + .ops = &sandbox_hwspinlock_ops, +}; diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 0000000000..a32bde4906 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32mp1_hws_priv { + fdt_addr_t base; +}; + +static int stm32mp1_lock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + u32 status; + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + status = readl(priv->base + index * sizeof(u32)); + if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EBUSY; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, + priv->base + index * sizeof(u32)); + + status = readl(priv->base + index * sizeof(u32)); + if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID)) + return -EINVAL; + + return 0; +} + +static int stm32mp1_unlock(struct udevice *dev, int index) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + + if (index >= STM32_MUTEX_NUM_LOCKS) + return -EINVAL; + + writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32)); + + return 0; +} + +static int stm32mp1_hwspinlock_probe(struct udevice *dev) +{ + struct stm32mp1_hws_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + clk_free(&clk); + + return ret; +} + +static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = { + .lock = stm32mp1_lock, + .unlock = stm32mp1_unlock, +}; + +static const struct udevice_id stm32mp1_hwspinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock" }, + {} +}; + +U_BOOT_DRIVER(hwspinlock_stm32mp1) = { + .name = "hwspinlock_stm32mp1", + .id = UCLASS_HWSPINLOCK, + .of_match = stm32mp1_hwspinlock_ids, + .ops = &stm32mp1_hwspinlock_ops, + .probe = stm32mp1_hwspinlock_probe, + .priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv), +}; diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index a2bdd5aa84..ae5aae03e7 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -6,8 +6,85 @@ #include #include #include +#include +#include + +/* + * i2c emulation works using an 'emul' node at the bus level. Each device in + * that node is in the UCLASS_I2C_EMUL uclass, and emulates one i2c device. A + * pointer to the device it emulates is in the 'dev' property of the emul device + * uclass platdata (struct i2c_emul_platdata), put there by i2c_emul_find(). + * When sandbox wants an emulator for a device, it calls i2c_emul_find() which + * searches for the emulator with the correct address. To find the device for an + * emulator, call i2c_emul_get_device(). + * + * The 'emul' node is in the UCLASS_I2C_EMUL_PARENT uclass. We use a separate + * uclass so avoid having strange devices on the I2C bus. + */ + +/** + * struct i2c_emul_uc_platdata - information about the emulator for this device + * + * This is used by devices in UCLASS_I2C_EMUL to record information about the + * device being emulated. It is accessible with dev_get_uclass_platdata() + * + * @dev: Device being emulated + */ +struct i2c_emul_uc_platdata { + struct udevice *dev; +}; + +struct udevice *i2c_emul_get_device(struct udevice *emul) +{ + struct i2c_emul_uc_platdata *uc_plat = dev_get_uclass_platdata(emul); + + return uc_plat->dev; +} + +int i2c_emul_find(struct udevice *dev, struct udevice **emulp) +{ + struct i2c_emul_uc_platdata *uc_plat; + struct udevice *emul; + int ret; + + ret = uclass_find_device_by_phandle(UCLASS_I2C_EMUL, dev, + "sandbox,emul", &emul); + if (ret) { + log_err("No emulators for device '%s'\n", dev->name); + return ret; + } + uc_plat = dev_get_uclass_platdata(emul); + uc_plat->dev = dev; + *emulp = emul; + + return device_probe(emul); +} UCLASS_DRIVER(i2c_emul) = { .id = UCLASS_I2C_EMUL, .name = "i2c_emul", + .per_device_platdata_auto_alloc_size = + sizeof(struct i2c_emul_uc_platdata), +}; + +/* + * This uclass is a child of the i2c bus. Its platdata is not defined here so + * is defined by its parent, UCLASS_I2C, which uses struct dm_i2c_chip. See + * per_child_platdata_auto_alloc_size in UCLASS_DRIVER(i2c). + */ +UCLASS_DRIVER(i2c_emul_parent) = { + .id = UCLASS_I2C_EMUL_PARENT, + .name = "i2c_emul_parent", + .post_bind = dm_scan_fdt_dev, +}; + +static const struct udevice_id i2c_emul_parent_ids[] = { + { .compatible = "sandbox,i2c-emul-parent" }, + { } +}; + +U_BOOT_DRIVER(i2c_emul_parent_drv) = { + .name = "i2c_emul_parent_drv", + .id = UCLASS_I2C_EMUL_PARENT, + .of_match = i2c_emul_parent_ids, }; diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index c5a3c4e201..975318e5f2 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -347,6 +347,17 @@ int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, debug("Cannot find I2C bus %d\n", busnum); return ret; } + + /* detect the presence of the chip on the bus */ + ret = i2c_probe_chip(bus, chip_addr, 0); + debug("%s: bus='%s', address %02x, ret=%d\n", __func__, bus->name, + chip_addr, ret); + if (ret) { + debug("Cannot detect I2C chip %02x on bus %d\n", chip_addr, + busnum); + return ret; + } + ret = i2c_get_chip(bus, chip_addr, offset_len, devp); if (ret) { debug("Cannot find I2C chip %02x on bus %d\n", chip_addr, diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 54bf35e552..4b93e02bbe 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -42,8 +42,18 @@ #include #include -#include #include +#include + +/* + * Provide access to architecture-specific I2C header files for platforms + * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and + * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C + * access is desired. + */ +#ifndef CONFIG_ARCH_K3 +#include +#endif #include "omap24xx_i2c.h" @@ -52,14 +62,107 @@ /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 +enum { + OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */ + OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */ + OMAP_I2C_STAT_REG, + OMAP_I2C_WE_REG, + OMAP_I2C_SYSS_REG, + OMAP_I2C_BUF_REG, + OMAP_I2C_CNT_REG, + OMAP_I2C_DATA_REG, + OMAP_I2C_SYSC_REG, + OMAP_I2C_CON_REG, + OMAP_I2C_OA_REG, + OMAP_I2C_SA_REG, + OMAP_I2C_PSC_REG, + OMAP_I2C_SCLL_REG, + OMAP_I2C_SCLH_REG, + OMAP_I2C_SYSTEST_REG, + OMAP_I2C_BUFSTAT_REG, + /* Only on IP V2 (OMAP4430, etc.) */ + OMAP_I2C_IP_V2_REVNB_LO, + OMAP_I2C_IP_V2_REVNB_HI, + OMAP_I2C_IP_V2_IRQSTATUS_RAW, + OMAP_I2C_IP_V2_IRQENABLE_SET, + OMAP_I2C_IP_V2_IRQENABLE_CLR, +}; + +static const u8 __maybe_unused reg_map_ip_v1[] = { + [OMAP_I2C_REV_REG] = 0x00, + [OMAP_I2C_IE_REG] = 0x04, + [OMAP_I2C_STAT_REG] = 0x08, + [OMAP_I2C_WE_REG] = 0x0c, + [OMAP_I2C_SYSS_REG] = 0x10, + [OMAP_I2C_BUF_REG] = 0x14, + [OMAP_I2C_CNT_REG] = 0x18, + [OMAP_I2C_DATA_REG] = 0x1c, + [OMAP_I2C_SYSC_REG] = 0x20, + [OMAP_I2C_CON_REG] = 0x24, + [OMAP_I2C_OA_REG] = 0x28, + [OMAP_I2C_SA_REG] = 0x2c, + [OMAP_I2C_PSC_REG] = 0x30, + [OMAP_I2C_SCLL_REG] = 0x34, + [OMAP_I2C_SCLH_REG] = 0x38, + [OMAP_I2C_SYSTEST_REG] = 0x3c, + [OMAP_I2C_BUFSTAT_REG] = 0x40, +}; + +static const u8 __maybe_unused reg_map_ip_v2[] = { + [OMAP_I2C_STAT_REG] = 0x28, + [OMAP_I2C_WE_REG] = 0x34, + [OMAP_I2C_SYSS_REG] = 0x90, + [OMAP_I2C_BUF_REG] = 0x94, + [OMAP_I2C_CNT_REG] = 0x98, + [OMAP_I2C_DATA_REG] = 0x9c, + [OMAP_I2C_SYSC_REG] = 0x10, + [OMAP_I2C_CON_REG] = 0xa4, + [OMAP_I2C_OA_REG] = 0xa8, + [OMAP_I2C_SA_REG] = 0xac, + [OMAP_I2C_PSC_REG] = 0xb0, + [OMAP_I2C_SCLL_REG] = 0xb4, + [OMAP_I2C_SCLH_REG] = 0xb8, + [OMAP_I2C_SYSTEST_REG] = 0xbc, + [OMAP_I2C_BUFSTAT_REG] = 0xc0, + [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, + [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, + [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, + [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, + [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, +}; + struct omap_i2c { struct udevice *clk; + int ip_rev; struct i2c *regs; unsigned int speed; int waitdelay; int clk_id; }; +static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev) +{ + switch (ip_rev) { + case OMAP_I2C_REV_V1: + return reg_map_ip_v1; + case OMAP_I2C_REV_V2: + /* Fall through... */ + default: + return reg_map_ip_v2; + } +} + +static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev, + u16 val, int reg) +{ + writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); +} + +static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg) +{ + return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); +} + static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) { unsigned long internal_clk = 0, fclk; @@ -114,29 +217,31 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) * Wait for the bus to be free by checking the Bus Busy (BB) * bit to become clear */ -static int wait_for_bb(struct i2c *i2c_base, int waitdelay) +static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay) { int timeout = I2C_TIMEOUT; + int irq_stat_reg; u16 stat; - writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ -#if defined(CONFIG_OMAP34XX) - while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { -#else - /* Read RAW status */ - while ((stat = readw(&i2c_base->irqstatus_raw) & + irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? + OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; + + /* clear current interrupts */ + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); + + while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) & I2C_STAT_BB) && timeout--) { -#endif - writew(stat, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG); udelay(waitdelay); } if (timeout <= 0) { - printf("Timed out in wait_for_bb: status=%04x\n", - stat); + printf("Timed out in %s: status=%04x\n", __func__, stat); return 1; } - writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ + + /* clear delayed stuff */ + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); return 0; } @@ -144,40 +249,37 @@ static int wait_for_bb(struct i2c *i2c_base, int waitdelay) * Wait for the I2C controller to complete current action * and update status */ -static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) +static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay) { u16 status; int timeout = I2C_TIMEOUT; + int irq_stat_reg; + irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? + OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; do { udelay(waitdelay); -#if defined(CONFIG_OMAP34XX) - status = readw(&i2c_base->stat); -#else - /* Read RAW status */ - status = readw(&i2c_base->irqstatus_raw); -#endif + status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg); } while (!(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | I2C_STAT_AL)) && timeout--); if (timeout <= 0) { - printf("Timed out in wait_for_event: status=%04x\n", - status); + printf("Timed out in %s: status=%04x\n", __func__, status); /* * If status is still 0 here, probably the bus pads have * not been configured for I2C, and/or pull-ups are missing. */ printf("Check if pads/pull-ups of bus are properly configured\n"); - writew(0xFFFF, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); status = 0; } return status; } -static void flush_fifo(struct i2c *i2c_base) +static void flush_fifo(void __iomem *i2c_base, int ip_rev) { u16 stat; @@ -186,17 +288,18 @@ static void flush_fifo(struct i2c *i2c_base) * you get a bus error */ while (1) { - stat = readw(&i2c_base->stat); + stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG); if (stat == I2C_STAT_RRDY) { - readb(&i2c_base->data); - writew(I2C_STAT_RRDY, &i2c_base->stat); + omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_RRDY, OMAP_I2C_STAT_REG); udelay(1000); } else break; } } -static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, +static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed, int *waitdelay) { int psc, fsscll = 0, fssclh = 0; @@ -248,79 +351,89 @@ static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, } } - *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ - writew(0, &i2c_base->con); - writew(psc, &i2c_base->psc); - writew(scll, &i2c_base->scll); - writew(sclh, &i2c_base->sclh); - writew(I2C_CON_EN, &i2c_base->con); - writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ + /* wait for 20 clkperiods */ + *waitdelay = (10000000 / speed) * 2; + + omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); + omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG); + omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG); + omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG); + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); + + /* clear all pending status */ + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); return 0; } -static void omap24_i2c_deblock(struct i2c *i2c_base) +static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev) { int i; u16 systest; u16 orgsystest; /* set test mode ST_EN = 1 */ - orgsystest = readw(&i2c_base->systest); + orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG); systest = orgsystest; + /* enable testmode */ systest |= I2C_SYSTEST_ST_EN; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); systest &= ~I2C_SYSTEST_TMODE_MASK; systest |= 3 << I2C_SYSTEST_TMODE_SHIFT; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); /* set SCL, SDA = 1 */ systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); udelay(10); /* toggle scl 9 clocks */ for (i = 0; i < 9; i++) { /* SCL = 0 */ systest &= ~I2C_SYSTEST_SCL_O; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, + systest, OMAP_I2C_SYSTEST_REG); udelay(10); /* SCL = 1 */ systest |= I2C_SYSTEST_SCL_O; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, + systest, OMAP_I2C_SYSTEST_REG); udelay(10); } /* send stop */ systest &= ~I2C_SYSTEST_SDA_O; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); udelay(10); systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; - writew(systest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); udelay(10); /* restore original mode */ - writew(orgsystest, &i2c_base->systest); + omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG); } -static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, - int *waitdelay) +static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed, + int slaveadd, int *waitdelay) { int timeout = I2C_TIMEOUT; int deblock = 1; retry: - if (readw(&i2c_base->con) & I2C_CON_EN) { - writew(0, &i2c_base->con); + if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) & + I2C_CON_EN) { + omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); udelay(50000); } - writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ + /* for ES2 after soft reset */ + omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG); udelay(1000); - writew(I2C_CON_EN, &i2c_base->con); - while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); + while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) & + I2C_SYSS_RDONE) && timeout--) { if (timeout <= 0) { puts("ERROR: Timeout in soft-reset\n"); return; @@ -328,30 +441,33 @@ retry: udelay(1000); } - if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { + if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } /* own address */ - writew(slaveadd, &i2c_base->oa); + omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG); + + if (ip_rev == OMAP_I2C_REV_V1) { + /* + * Have to enable interrupts for OMAP2/3, these IPs don't have + * an 'irqstatus_raw' register and we shall have to poll 'stat' + */ + omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE | + I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, + OMAP_I2C_IE_REG); + } -#if defined(CONFIG_OMAP34XX) - /* - * Have to enable interrupts for OMAP2/3, these IPs don't have - * an 'irqstatus_raw' register and we shall have to poll 'stat' - */ - writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); -#endif udelay(1000); - flush_fifo(i2c_base); - writew(0xFFFF, &i2c_base->stat); + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); /* Handle possible failed I2C state */ - if (wait_for_bb(i2c_base, *waitdelay)) + if (wait_for_bb(i2c_base, ip_rev, *waitdelay)) if (deblock == 1) { - omap24_i2c_deblock(i2c_base); + omap24_i2c_deblock(i2c_base, ip_rev); deblock = 0; goto retry; } @@ -361,25 +477,28 @@ retry: * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip) +static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay, + uchar chip) { u16 status; int res = 1; /* default = fail */ - if (chip == readw(&i2c_base->oa)) + if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG)) return res; /* Wait until bus is free */ - if (wait_for_bb(i2c_base, waitdelay)) + if (wait_for_bb(i2c_base, ip_rev, waitdelay)) return res; /* No data transfer, slave addr only */ - writew(chip, &i2c_base->sa); - /* Stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); - status = wait_for_event(i2c_base, waitdelay); + /* Stop bit needed here */ + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, + OMAP_I2C_CON_REG); + + status = wait_for_event(i2c_base, ip_rev, waitdelay); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -400,14 +519,17 @@ static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip) res = 0; /* Device found */ udelay(waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ - writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX, + OMAP_I2C_CON_REG); /* Reset */ udelay(1000); - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); /* STP */ + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_TRX | I2C_CON_STP, + OMAP_I2C_CON_REG); /* STP */ } + pr_exit: - flush_fifo(i2c_base); - writew(0xFFFF, &i2c_base->stat); + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); return res; } @@ -424,8 +546,9 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, - uint addr, int alen, uchar *buffer, int len) +static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, + uchar chip, uint addr, int alen, uchar *buffer, + int len) { int i2c_error = 0; u16 status; @@ -434,10 +557,12 @@ static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, puts("I2C read: addr len < 0\n"); return 1; } + if (len < 0) { puts("I2C read: data len < 0\n"); return 1; } + if (buffer == NULL) { puts("I2C read: NULL pointer passed\n"); return 1; @@ -471,28 +596,29 @@ static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, #endif /* Wait until bus not busy */ - if (wait_for_bb(i2c_base, waitdelay)) + if (wait_for_bb(i2c_base, ip_rev, waitdelay)) return 1; /* Zero, one or two bytes reg address (offset) */ - writew(alen, &i2c_base->cnt); + omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG); /* Set slave address */ - writew(chip, &i2c_base->sa); + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); if (alen) { /* Must write reg offset first */ #ifdef CONFIG_I2C_REPEATED_START /* No stop bit, use Repeated Start (Sr) */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | - I2C_CON_TRX, &i2c_base->con); + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG); #else /* Stop - Start (P-S) */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | - I2C_CON_TRX, &i2c_base->con); + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, + OMAP_I2C_CON_REG); #endif /* Send register offset */ while (1) { - status = wait_for_event(i2c_base, waitdelay); + status = wait_for_event(i2c_base, ip_rev, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; @@ -508,31 +634,37 @@ static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, } if (alen) { if (status & I2C_STAT_XRDY) { + u8 addr_byte; alen--; - /* Do we have to use byte access? */ - writeb((addr >> (8 * alen)) & 0xff, - &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); + addr_byte = (addr >> (8 * alen)) & 0xff; + omap_i2c_write_reg(i2c_base, ip_rev, + addr_byte, + OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_XRDY, + OMAP_I2C_STAT_REG); } } if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_ARDY, + OMAP_I2C_STAT_REG); break; } } } + /* Set slave address */ - writew(chip, &i2c_base->sa); + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); /* Read len bytes from slave */ - writew(len, &i2c_base->cnt); + omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG); /* Need stop bit here */ - writew(I2C_CON_EN | I2C_CON_MST | - I2C_CON_STT | I2C_CON_STP, - &i2c_base->con); + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG); /* Receive data */ while (1) { - status = wait_for_event(i2c_base, waitdelay); + status = wait_for_event(i2c_base, ip_rev, waitdelay); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -549,24 +681,28 @@ static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, goto rd_exit; } if (status & I2C_STAT_RRDY) { - *buffer++ = readb(&i2c_base->data); - writew(I2C_STAT_RRDY, &i2c_base->stat); + *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev, + OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_RRDY, OMAP_I2C_STAT_REG); } if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_ARDY, OMAP_I2C_STAT_REG); break; } } rd_exit: - flush_fifo(i2c_base); - writew(0xFFFF, &i2c_base->stat); + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, - uint addr, int alen, uchar *buffer, int len) +static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay, + uchar chip, uint addr, int alen, uchar *buffer, + int len) { int i; u16 status; @@ -617,20 +753,21 @@ static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, #endif /* Wait until bus not busy */ - if (wait_for_bb(i2c_base, waitdelay)) + if (wait_for_bb(i2c_base, ip_rev, waitdelay)) return 1; /* Start address phase - will write regoffset + len bytes data */ - writew(alen + len, &i2c_base->cnt); + omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG); /* Set slave address */ - writew(chip, &i2c_base->sa); + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); /* Stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); + omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, + OMAP_I2C_CON_REG); while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(i2c_base, waitdelay); + status = wait_for_event(i2c_base, ip_rev, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; @@ -646,8 +783,11 @@ static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, } if (status & I2C_STAT_XRDY) { alen--; - writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, + (addr >> (8 * alen)) & 0xff, + OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_XRDY, OMAP_I2C_STAT_REG); } else { i2c_error = 1; printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", @@ -655,9 +795,10 @@ static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, goto wr_exit; } } + /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(i2c_base, waitdelay); + status = wait_for_event(i2c_base, ip_rev, waitdelay); if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", @@ -665,8 +806,10 @@ static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, goto wr_exit; } if (status & I2C_STAT_XRDY) { - writeb(buffer[i], &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); + omap_i2c_write_reg(i2c_base, ip_rev, + buffer[i], OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_XRDY, OMAP_I2C_STAT_REG); } else { i2c_error = 1; printf("i2c_write: bus not ready for data Tx (i=%d)\n", @@ -674,19 +817,20 @@ static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, goto wr_exit; } } + /* * poll ARDY bit for making sure that last byte really has been * transferred on the bus. */ do { - status = wait_for_event(i2c_base, waitdelay); + status = wait_for_event(i2c_base, ip_rev, waitdelay); } while (!(status & I2C_STAT_ARDY) && timeout--); if (timeout <= 0) printf("i2c_write: timed out writig last byte!\n"); wr_exit: - flush_fifo(i2c_base); - writew(0xFFFF, &i2c_base->stat); + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); return i2c_error; } @@ -695,26 +839,26 @@ wr_exit: * The legacy I2C functions. These need to get removed once * all users of this driver are converted to DM. */ -static struct i2c *omap24_get_base(struct i2c_adapter *adap) +static void __iomem *omap24_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { case 0: - return (struct i2c *)I2C_BASE1; + return (void __iomem *)I2C_BASE1; break; case 1: - return (struct i2c *)I2C_BASE2; + return (void __iomem *)I2C_BASE2; break; #if (CONFIG_SYS_I2C_BUS_MAX > 2) case 2: - return (struct i2c *)I2C_BASE3; + return (void __iomem *)I2C_BASE3; break; #if (CONFIG_SYS_I2C_BUS_MAX > 3) case 3: - return (struct i2c *)I2C_BASE4; + return (void __iomem *)I2C_BASE4; break; #if (CONFIG_SYS_I2C_BUS_MAX > 4) case 4: - return (struct i2c *)I2C_BASE5; + return (void __iomem *)I2C_BASE5; break; #endif #endif @@ -723,35 +867,46 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) printf("wrong hwadapnr: %d\n", adap->hwadapnr); break; } + return NULL; } +static int omap24_get_ip_rev(void) +{ +#ifdef CONFIG_OMAP34XX + return OMAP_I2C_REV_V1; +#else + return OMAP_I2C_REV_V2; +#endif +} static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); + void __iomem *i2c_base = omap24_get_base(adap); + int ip_rev = omap24_get_ip_rev(); - return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr, + return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr, alen, buffer, len); } - static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); + void __iomem *i2c_base = omap24_get_base(adap); + int ip_rev = omap24_get_ip_rev(); - return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr, + return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr, alen, buffer, len); } static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) { - struct i2c *i2c_base = omap24_get_base(adap); + void __iomem *i2c_base = omap24_get_base(adap); + int ip_rev = omap24_get_ip_rev(); int ret; - ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay); + ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay); if (ret) { pr_err("%s: set i2c speed failed\n", __func__); return ret; @@ -764,16 +919,19 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { - struct i2c *i2c_base = omap24_get_base(adap); + void __iomem *i2c_base = omap24_get_base(adap); + int ip_rev = omap24_get_ip_rev(); - return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay); + return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd, + &adap->waitdelay); } static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { - struct i2c *i2c_base = omap24_get_base(adap); + void __iomem *i2c_base = omap24_get_base(adap); + int ip_rev = omap24_get_ip_rev(); - return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip); + return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); } #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) @@ -793,6 +951,7 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, CONFIG_SYS_OMAP24_I2C_SPEED1, CONFIG_SYS_OMAP24_I2C_SLAVE1, 1) + #if (CONFIG_SYS_I2C_BUS_MAX > 2) #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED @@ -847,11 +1006,13 @@ static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) for (; nmsgs > 0; nmsgs--, msg++) { debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); if (msg->flags & I2C_M_RD) { - ret = __omap24_i2c_read(priv->regs, priv->waitdelay, + ret = __omap24_i2c_read(priv->regs, priv->ip_rev, + priv->waitdelay, msg->addr, 0, 0, msg->buf, msg->len); } else { - ret = __omap24_i2c_write(priv->regs, priv->waitdelay, + ret = __omap24_i2c_write(priv->regs, priv->ip_rev, + priv->waitdelay, msg->addr, 0, 0, msg->buf, msg->len); } @@ -870,7 +1031,8 @@ static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) priv->speed = speed; - return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay); + return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed, + &priv->waitdelay); } static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, @@ -878,14 +1040,22 @@ static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, { struct omap_i2c *priv = dev_get_priv(bus); - return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr); + return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay, + chip_addr); } static int omap_i2c_probe(struct udevice *bus) { struct omap_i2c *priv = dev_get_priv(bus); + struct omap_i2c_platdata *plat = dev_get_platdata(bus); - __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay); + priv->speed = plat->speed; + priv->regs = map_physmem(plat->base, sizeof(void *), + MAP_NOCACHE); + priv->ip_rev = plat->ip_rev; + + __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0, + &priv->waitdelay); return 0; } @@ -893,18 +1063,18 @@ static int omap_i2c_probe(struct udevice *bus) #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int omap_i2c_ofdata_to_platdata(struct udevice *bus) { - struct omap_i2c *priv = dev_get_priv(bus); + struct omap_i2c_platdata *plat = dev_get_platdata(bus); - priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *), - MAP_NOCACHE); - priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED; + plat->base = devfdt_get_addr(bus); + plat->speed = dev_read_u32_default(bus, "clock-frequency", 100000); + plat->ip_rev = dev_get_driver_data(bus); return 0; } static const struct udevice_id omap_i2c_ids[] = { - { .compatible = "ti,omap3-i2c" }, - { .compatible = "ti,omap4-i2c" }, + { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 }, + { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 }, { } }; #endif @@ -921,11 +1091,14 @@ U_BOOT_DRIVER(i2c_omap) = { #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = omap_i2c_ids, .ofdata_to_platdata = omap_i2c_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct omap_i2c_platdata), #endif .probe = omap_i2c_probe, .priv_auto_alloc_size = sizeof(struct omap_i2c), .ops = &omap_i2c_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 6657851084..0dbbaa0c44 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -21,33 +21,15 @@ static int get_emul(struct udevice *dev, struct udevice **devp, struct dm_i2c_ops **opsp) { struct dm_i2c_chip *plat; - struct udevice *child; int ret; *devp = NULL; *opsp = NULL; plat = dev_get_parent_platdata(dev); if (!plat->emul) { - ret = dm_scan_fdt_dev(dev); + ret = i2c_emul_find(dev, &plat->emul); if (ret) return ret; - - for (device_find_first_child(dev, &child); child; - device_find_next_child(&child)) { - if (device_get_uclass_id(child) != UCLASS_I2C_EMUL) - continue; - - ret = device_probe(child); - if (ret) - return ret; - - break; - } - - if (child) - plat->emul = child; - else - return -ENODEV; } *devp = plat->emul; *opsp = i2c_get_ops(plat->emul); diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 36ec610c8e..3872364d6b 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -58,7 +58,7 @@ struct stm32_i2c_regs { #define STM32_I2C_CR2_ADD10 BIT(11) #define STM32_I2C_CR2_RD_WRN BIT(10) #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) -#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK)) +#define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK) #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ @@ -197,7 +197,7 @@ struct stm32_i2c_priv { int speed; }; -static struct stm32_i2c_spec i2c_specs[] = { +static const struct stm32_i2c_spec i2c_specs[] = { [STM32_I2C_SPEED_STANDARD] = { .rate = STANDARD_RATE, .rate_min = 8000, @@ -236,7 +236,7 @@ static struct stm32_i2c_spec i2c_specs[] = { }, }; -static struct stm32_i2c_setup stm32f7_setup = { +static const struct stm32_i2c_setup stm32f7_setup = { .rise_time = STM32_I2C_RISE_TIME_DEFAULT, .fall_time = STM32_I2C_FALL_TIME_DEFAULT, .dnf = STM32_I2C_DNF_DEFAULT, @@ -255,7 +255,7 @@ static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) } static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, - struct i2c_msg *msg, bool stop) + struct i2c_msg *msg, bool stop) { struct stm32_i2c_regs *regs = i2c_priv->regs; u32 cr2 = readl(®s->cr2); @@ -299,7 +299,7 @@ static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, */ static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, - struct i2c_msg *msg, bool stop) + struct i2c_msg *msg, bool stop) { struct stm32_i2c_regs *regs = i2c_priv->regs; u32 cr2 = readl(®s->cr2); @@ -317,7 +317,7 @@ static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, } static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, - u32 flags, u32 *status) + u32 flags, u32 *status) { struct stm32_i2c_regs *regs = i2c_priv->regs; u32 time_start = get_timer(0); @@ -392,7 +392,7 @@ static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) } static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, - struct i2c_msg *msg, bool stop) + struct i2c_msg *msg, bool stop) { struct stm32_i2c_regs *regs = i2c_priv->regs; u32 status; @@ -465,7 +465,7 @@ static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, } static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, - int nmsgs) + int nmsgs) { struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); int ret; @@ -594,6 +594,7 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, for (l = 0; l < STM32_SCLL_MAX; l++) { u32 tscl_l = (l + 1) * prescaler + tsync; + if ((tscl_l < i2c_specs[setup->speed].l_min) || (i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4))) { @@ -634,8 +635,8 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, } static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, - struct stm32_i2c_setup *setup, - struct stm32_i2c_timings *output) + struct stm32_i2c_setup *setup, + struct stm32_i2c_timings *output) { struct stm32_i2c_timings *v, *_v; struct list_head solutions; @@ -643,28 +644,28 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, if (setup->speed >= STM32_I2C_SPEED_END) { pr_err("%s: speed out of bound {%d/%d}\n", __func__, - setup->speed, STM32_I2C_SPEED_END - 1); + setup->speed, STM32_I2C_SPEED_END - 1); return -EINVAL; } if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || (setup->fall_time > i2c_specs[setup->speed].fall_max)) { pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", - __func__, - setup->rise_time, i2c_specs[setup->speed].rise_max, - setup->fall_time, i2c_specs[setup->speed].fall_max); + __func__, + setup->rise_time, i2c_specs[setup->speed].rise_max, + setup->fall_time, i2c_specs[setup->speed].fall_max); return -EINVAL; } if (setup->dnf > STM32_I2C_DNF_MAX) { pr_err("%s: DNF out of bound %d/%d\n", __func__, - setup->dnf, STM32_I2C_DNF_MAX); + setup->dnf, STM32_I2C_DNF_MAX); return -EINVAL; } if (setup->speed_freq > i2c_specs[setup->speed].rate) { pr_err("%s: Freq {%d/%d}\n", __func__, - setup->speed_freq, i2c_specs[setup->speed].rate); + setup->speed_freq, i2c_specs[setup->speed].rate); return -EINVAL; } @@ -693,7 +694,7 @@ exit: } static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, - struct stm32_i2c_timings *timing) + struct stm32_i2c_timings *timing) { struct stm32_i2c_setup *setup = i2c_priv->setup; int ret = 0; diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c index b4fff43269..793f3f59b5 100644 --- a/drivers/i2c/tegra186_bpmp_i2c.c +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -85,6 +85,12 @@ static int tegra186_bpmp_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, return 0; } +static int tegra186_bpmp_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + return 0; +} + static int tegra186_bpmp_i2c_probe(struct udevice *dev) { struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); @@ -101,6 +107,7 @@ static int tegra186_bpmp_i2c_probe(struct udevice *dev) static const struct dm_i2c_ops tegra186_bpmp_i2c_ops = { .xfer = tegra186_bpmp_i2c_xfer, + .probe_chip = tegra186_bpmp_probe_chip, }; static const struct udevice_id tegra186_bpmp_i2c_ids[] = { diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 5678f8e3cf..9a5dc46207 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -167,19 +167,8 @@ static int kbd_controller_present(void) return in8(I8042_STS_REG) != 0xff; } -/* - * Implement a weak default function for boards that optionally - * need to skip the i8042 initialization. - * - * TODO(sjg@chromium.org): Use device tree for this? - */ -int __weak board_i8042_skip(void) -{ - /* As default, don't skip */ - return 0; -} - -void i8042_flush(void) +/** Flush all buffer from keyboard controller to host*/ +static void i8042_flush(void) { int timeout; @@ -202,7 +191,13 @@ void i8042_flush(void) } } -int i8042_disable(void) +/** + * Disables the keyboard so that key strokes no longer generate scancodes to + * the host. + * + * @return 0 if ok, -1 if keyboard input was found while disabling + */ +static int i8042_disable(void) { if (kbd_input_empty() == 0) return -1; @@ -266,7 +261,7 @@ static int i8042_start(struct udevice *dev) char *penv; int ret; - if (!kbd_controller_present() || board_i8042_skip()) { + if (!kbd_controller_present()) { debug("i8042 keyboard controller is not present\n"); return -ENOENT; } @@ -294,6 +289,15 @@ static int i8042_start(struct udevice *dev) return 0; } +static int i8042_kbd_remove(struct udevice *dev) +{ + if (i8042_disable()) + log_debug("i8042_disable() failed. fine, continue.\n"); + i8042_flush(); + + return 0; +} + /** * Set up the i8042 keyboard. This is called by the stdio device handler * @@ -348,6 +352,7 @@ U_BOOT_DRIVER(i8042_kbd) = { .id = UCLASS_KEYBOARD, .of_match = i8042_kbd_ids, .probe = i8042_kbd_probe, + .remove = i8042_kbd_remove, .ops = &i8042_kbd_ops, .priv_auto_alloc_size = sizeof(struct i8042_kbd_priv), }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c5697011f2..704c8dd195 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -120,6 +120,12 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. +config JZ4780_EFUSE + bool "Ingenic JZ4780 eFUSE support" + depends on ARCH_JZ47XX + help + This selects support for the eFUSE on Ingenic JZ4780 SoCs. + config MXC_OCOTP bool "Enable MXC OCOTP Driver" help @@ -312,4 +318,21 @@ config FS_LOADER The consumer driver would then use this loader to program whatever, ie. the FPGA device. +config GDSYS_SOC + bool "Enable gdsys SOC driver" + depends on MISC + help + Support for gdsys IHS SOC, a simple bus associated with each gdsys + IHS (Integrated Hardware Systems) FPGA, which holds all devices whose + register maps are contained within the FPGA's register map. + +config IHS_FPGA + bool "Enable IHS FPGA driver" + depends on MISC + help + Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on + gdsys devices, which supply the majority of the functionality offered + by the devices. This driver supports both CON and CPU variants of the + devices, depending on the device tree entry. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 759d2c791b..6bdf5054f4 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -4,11 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_MISC) += misc-uclass.o -obj-$(CONFIG_ALI152X) += ali512x.o -obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o -obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o -obj-$(CONFIG_DS4510) += ds4510.o -obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o @@ -16,46 +11,55 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o endif -obj-$(CONFIG_FSL_IIM) += fsl_iim.o -obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o -obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o -obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o -obj-$(CONFIG_IMX8) += imx8/ -obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o -obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o -obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o -obj-$(CONFIG_NS87308) += ns87308.o -obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o + ifdef CONFIG_DM_I2C ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif endif -obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o -obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o -obj-$(CONFIG_LED_STATUS) += status_led.o -obj-$(CONFIG_SANDBOX) += swap_case.o ifdef CONFIG_SPL_OF_PLATDATA ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif -obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o -obj-$(CONFIG_TEGRA_CAR) += tegra_car.o -obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o -obj-$(CONFIG_TWL4030_LED) += twl4030_led.o -obj-$(CONFIG_FSL_IFC) += fsl_ifc.o -obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o -obj-$(CONFIG_PCA9551_LED) += pca9551_led.o +obj-$(CONFIG_ALI152X) += ali512x.o +obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o +obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o +obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o +obj-$(CONFIG_DS4510) += ds4510.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o -obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o -obj-$(CONFIG_QFW) += qfw.o -obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o -obj-$(CONFIG_STM32_RCC) += stm32_rcc.o -obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o -obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o +obj-$(CONFIG_FSL_IFC) += fsl_ifc.o +obj-$(CONFIG_FSL_IIM) += fsl_iim.o +obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o +obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o +obj-$(CONFIG_FS_LOADER) += fs_loader.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o -obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o +obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o +obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o +obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o +obj-$(CONFIG_IMX8) += imx8/ +obj-$(CONFIG_LED_STATUS) += status_led.o +obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o -obj-$(CONFIG_FS_LOADER) += fs_loader.o +obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NS87308) += ns87308.o +obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o +obj-$(CONFIG_PCA9551_LED) += pca9551_led.o +obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o +obj-$(CONFIG_QFW) += qfw.o +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o +obj-$(CONFIG_SANDBOX) += swap_case.o +obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o +obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o +obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o +obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o +obj-$(CONFIG_STM32_RCC) += stm32_rcc.o +obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o +obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o +obj-$(CONFIG_TEGRA_CAR) += tegra_car.o +obj-$(CONFIG_TWL4030_LED) += twl4030_led.o +obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o +obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o +obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c index 883b2a35e0..eff33f7343 100644 --- a/drivers/misc/altera_sysid.c +++ b/drivers/misc/altera_sysid.c @@ -35,7 +35,7 @@ void display_sysid(void) if (ret) return; ret = misc_read(dev, 0, &sysid, sizeof(sysid)); - if (ret) + if (ret < 0) return; stamp = sysid[1]; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 190505c11c..565de040fe 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -13,6 +13,8 @@ * is not reset. */ +#define LOG_CATEGORY UCLASS_CROS_EC + #include #include #include @@ -41,6 +43,54 @@ enum { CROS_EC_CMD_HASH_TIMEOUT_MS = 2000, }; +#define INVALID_HCMD 0xFF + +/* + * Map UHEPI masks to non UHEPI commands in order to support old EC FW + * which does not support UHEPI command. + */ +static const struct { + u8 set_cmd; + u8 clear_cmd; + u8 get_cmd; +} event_map[] = { + [EC_HOST_EVENT_MAIN] = { + INVALID_HCMD, EC_CMD_HOST_EVENT_CLEAR, + INVALID_HCMD, + }, + [EC_HOST_EVENT_B] = { + INVALID_HCMD, EC_CMD_HOST_EVENT_CLEAR_B, + EC_CMD_HOST_EVENT_GET_B, + }, + [EC_HOST_EVENT_SCI_MASK] = { + EC_CMD_HOST_EVENT_SET_SCI_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_SCI_MASK, + }, + [EC_HOST_EVENT_SMI_MASK] = { + EC_CMD_HOST_EVENT_SET_SMI_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_SMI_MASK, + }, + [EC_HOST_EVENT_ALWAYS_REPORT_MASK] = { + INVALID_HCMD, INVALID_HCMD, INVALID_HCMD, + }, + [EC_HOST_EVENT_ACTIVE_WAKE_MASK] = { + EC_CMD_HOST_EVENT_SET_WAKE_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_WAKE_MASK, + }, + [EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX] = { + EC_CMD_HOST_EVENT_SET_WAKE_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_WAKE_MASK, + }, + [EC_HOST_EVENT_LAZY_WAKE_MASK_S3] = { + EC_CMD_HOST_EVENT_SET_WAKE_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_WAKE_MASK, + }, + [EC_HOST_EVENT_LAZY_WAKE_MASK_S5] = { + EC_CMD_HOST_EVENT_SET_WAKE_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_WAKE_MASK, + }, +}; + void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len) { #ifdef DEBUG @@ -227,7 +277,7 @@ static int send_command_proto3(struct cros_ec_dev *cdev, return handle_proto3_response(cdev, dinp, din_len); } -static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, +static int send_command(struct cros_ec_dev *dev, uint cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { @@ -330,7 +380,7 @@ static int ec_command_inptr(struct udevice *dev, uint8_t cmd, * @param din_len Maximum size of response in bytes * @return number of bytes in response, or -ve on error */ -static int ec_command(struct udevice *dev, uint8_t cmd, int cmd_version, +static int ec_command(struct udevice *dev, uint cmd, int cmd_version, const void *dout, int dout_len, void *din, int din_len) { @@ -365,10 +415,14 @@ int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan) int cros_ec_read_id(struct udevice *dev, char *id, int maxlen) { struct ec_response_get_version *r; + int ret; - if (ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, - (uint8_t **)&r, sizeof(*r)) != sizeof(*r)) + ret = ec_command_inptr(dev, EC_CMD_GET_VERSION, 0, NULL, 0, + (uint8_t **)&r, sizeof(*r)); + if (ret != sizeof(*r)) { + log_err("Got rc %d, expected %u\n", ret, (uint)sizeof(*r)); return -1; + } if (maxlen > (int)sizeof(r->version_string_ro)) maxlen = sizeof(r->version_string_ro); @@ -381,6 +435,7 @@ int cros_ec_read_id(struct udevice *dev, char *id, int maxlen) memcpy(id, r->version_string_rw, maxlen); break; default: + log_err("Invalid EC image %d\n", r->current_image); return -1; } @@ -563,6 +618,36 @@ int cros_ec_info(struct udevice *dev, struct ec_response_mkbp_info *info) return 0; } +int cros_ec_get_event_mask(struct udevice *dev, uint type, uint32_t *mask) +{ + struct ec_response_host_event_mask rsp; + int ret; + + ret = ec_command(dev, type, 0, NULL, 0, &rsp, sizeof(rsp)); + if (ret < 0) + return ret; + else if (ret != sizeof(rsp)) + return -EINVAL; + + *mask = rsp.mask; + + return 0; +} + +int cros_ec_set_event_mask(struct udevice *dev, uint type, uint32_t mask) +{ + struct ec_params_host_event_mask req; + int ret; + + req.mask = mask; + + ret = ec_command(dev, type, 0, &req, sizeof(req), NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + int cros_ec_get_host_events(struct udevice *dev, uint32_t *events_ptr) { struct ec_response_host_event_mask *resp; @@ -616,6 +701,17 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, return 0; } +int cros_ec_entering_mode(struct udevice *dev, int mode) +{ + int rc; + + rc = ec_command(dev, EC_CMD_ENTERING_MODE, 0, &mode, sizeof(mode), + NULL, 0); + if (rc) + return -1; + return 0; +} + static int cros_ec_check_version(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); @@ -650,16 +746,14 @@ static int cros_ec_check_version(struct udevice *dev) cdev->protocol_version = 3; req.in_data = 0; if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), - (uint8_t **)&resp, sizeof(*resp)) > 0) { + (uint8_t **)&resp, sizeof(*resp)) > 0) return 0; - } /* Try sending a version 2 packet */ cdev->protocol_version = 2; if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req), - (uint8_t **)&resp, sizeof(*resp)) > 0) { + (uint8_t **)&resp, sizeof(*resp)) > 0) return 0; - } /* * Fail if we're still here, since the EC doesn't understand any @@ -822,6 +916,9 @@ int cros_ec_flash_write(struct udevice *dev, const uint8_t *data, uint32_t end, off; int ret; + if (!burst) + return -EINVAL; + /* * TODO: round up to the nearest multiple of write size. Can get away * without that on link right now because its write size is 4 bytes. @@ -844,6 +941,35 @@ int cros_ec_flash_write(struct udevice *dev, const uint8_t *data, return 0; } +/** + * Run verification on a slot + * + * @param me CrosEc instance + * @param region Region to run verification on + * @return 0 if success or not applicable. Non-zero if verification failed. + */ +int cros_ec_efs_verify(struct udevice *dev, enum ec_flash_region region) +{ + struct ec_params_efs_verify p; + int rv; + + log_info("EFS: EC is verifying updated image...\n"); + p.region = region; + + rv = ec_command(dev, EC_CMD_EFS_VERIFY, 0, &p, sizeof(p), NULL, 0); + if (rv >= 0) { + log_info("EFS: Verification success\n"); + return 0; + } + if (rv == -EC_RES_INVALID_COMMAND) { + log_info("EFS: EC doesn't support EFS_VERIFY command\n"); + return 0; + } + log_info("EFS: Verification failed\n"); + + return rv; +} + /** * Read a single block from the flash * @@ -934,15 +1060,17 @@ int cros_ec_read_nvdata(struct udevice *dev, uint8_t *block, int size) struct ec_params_vbnvcontext p; int len; - if (size != EC_VBNV_BLOCK_SIZE) + if (size != EC_VBNV_BLOCK_SIZE && size != EC_VBNV_BLOCK_SIZE_V2) return -EINVAL; p.op = EC_VBNV_CONTEXT_OP_READ; len = ec_command(dev, EC_CMD_VBNV_CONTEXT, EC_VER_VBNV_CONTEXT, - &p, sizeof(p), block, EC_VBNV_BLOCK_SIZE); - if (len < EC_VBNV_BLOCK_SIZE) + &p, sizeof(uint32_t) + size, block, size); + if (len != size) { + log_err("Expected %d bytes, got %d\n", size, len); return -EIO; + } return 0; } @@ -952,19 +1080,33 @@ int cros_ec_write_nvdata(struct udevice *dev, const uint8_t *block, int size) struct ec_params_vbnvcontext p; int len; - if (size != EC_VBNV_BLOCK_SIZE) + if (size != EC_VBNV_BLOCK_SIZE && size != EC_VBNV_BLOCK_SIZE_V2) return -EINVAL; p.op = EC_VBNV_CONTEXT_OP_WRITE; - memcpy(p.block, block, sizeof(p.block)); + memcpy(p.block, block, size); len = ec_command_inptr(dev, EC_CMD_VBNV_CONTEXT, EC_VER_VBNV_CONTEXT, - &p, sizeof(p), NULL, 0); + &p, sizeof(uint32_t) + size, NULL, 0); if (len < 0) return -1; return 0; } +int cros_ec_battery_cutoff(struct udevice *dev, uint8_t flags) +{ + struct ec_params_battery_cutoff p; + int len; + + p.flags = flags; + len = ec_command(dev, EC_CMD_BATTERY_CUT_OFF, 1, &p, sizeof(p), + NULL, 0); + + if (len < 0) + return -1; + return 0; +} + int cros_ec_set_ldo(struct udevice *dev, uint8_t index, uint8_t state) { struct ec_params_ldo_set params; @@ -1139,9 +1281,209 @@ int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *in, return 0; } +int cros_ec_check_feature(struct udevice *dev, int feature) +{ + struct ec_response_get_features r; + int rv; + + rv = ec_command(dev, EC_CMD_GET_FEATURES, 0, &r, sizeof(r), NULL, 0); + if (rv) + return rv; + + if (feature >= 8 * sizeof(r.flags)) + return -1; + + return r.flags[feature / 32] & EC_FEATURE_MASK_0(feature); +} + +/* + * Query the EC for specified mask indicating enabled events. + * The EC maintains separate event masks for SMI, SCI and WAKE. + */ +static int cros_ec_uhepi_cmd(struct udevice *dev, uint mask, uint action, + uint64_t *value) +{ + int ret; + struct ec_params_host_event req; + struct ec_response_host_event rsp; + + req.action = action; + req.mask_type = mask; + if (action != EC_HOST_EVENT_GET) + req.value = *value; + else + *value = 0; + ret = ec_command(dev, EC_CMD_HOST_EVENT, 0, &req, sizeof(req), &rsp, + sizeof(rsp)); + + if (action != EC_HOST_EVENT_GET) + return ret; + if (ret == 0) + *value = rsp.value; + + return ret; +} + +static int cros_ec_handle_non_uhepi_cmd(struct udevice *dev, uint hcmd, + uint action, uint64_t *value) +{ + int ret = -1; + struct ec_params_host_event_mask req; + struct ec_response_host_event_mask rsp; + + if (hcmd == INVALID_HCMD) + return ret; + + if (action != EC_HOST_EVENT_GET) + req.mask = (uint32_t)*value; + else + *value = 0; + + ret = ec_command(dev, hcmd, 0, &req, sizeof(req), &rsp, sizeof(rsp)); + if (action != EC_HOST_EVENT_GET) + return ret; + if (ret == 0) + *value = rsp.mask; + + return ret; +} + +bool cros_ec_is_uhepi_supported(struct udevice *dev) +{ +#define UHEPI_SUPPORTED 1 +#define UHEPI_NOT_SUPPORTED 2 + static int uhepi_support; + + if (!uhepi_support) { + uhepi_support = cros_ec_check_feature(dev, + EC_FEATURE_UNIFIED_WAKE_MASKS) > 0 ? UHEPI_SUPPORTED : + UHEPI_NOT_SUPPORTED; + log_debug("Chrome EC: UHEPI %s\n", + uhepi_support == UHEPI_SUPPORTED ? "supported" : + "not supported"); + } + return uhepi_support == UHEPI_SUPPORTED; +} + +static int cros_ec_get_mask(struct udevice *dev, uint type) +{ + u64 value = 0; + + if (cros_ec_is_uhepi_supported(dev)) { + cros_ec_uhepi_cmd(dev, type, EC_HOST_EVENT_GET, &value); + } else { + assert(type < ARRAY_SIZE(event_map)); + cros_ec_handle_non_uhepi_cmd(dev, event_map[type].get_cmd, + EC_HOST_EVENT_GET, &value); + } + return value; +} + +static int cros_ec_clear_mask(struct udevice *dev, uint type, u64 mask) +{ + if (cros_ec_is_uhepi_supported(dev)) + return cros_ec_uhepi_cmd(dev, type, EC_HOST_EVENT_CLEAR, &mask); + + assert(type < ARRAY_SIZE(event_map)); + + return cros_ec_handle_non_uhepi_cmd(dev, event_map[type].clear_cmd, + EC_HOST_EVENT_CLEAR, &mask); +} + +uint64_t cros_ec_get_events_b(struct udevice *dev) +{ + return cros_ec_get_mask(dev, EC_HOST_EVENT_B); +} + +int cros_ec_clear_events_b(struct udevice *dev, uint64_t mask) +{ + log_debug("Chrome EC: clear events_b mask to 0x%016llx\n", mask); + + return cros_ec_clear_mask(dev, EC_HOST_EVENT_B, mask); +} + +int cros_ec_read_limit_power(struct udevice *dev, int *limit_powerp) +{ + struct ec_params_charge_state p; + struct ec_response_charge_state r; + int ret; + + p.cmd = CHARGE_STATE_CMD_GET_PARAM; + p.get_param.param = CS_PARAM_LIMIT_POWER; + ret = ec_command(dev, EC_CMD_CHARGE_STATE, 0, &p, sizeof(p), + &r, sizeof(r)); + + /* + * If our EC doesn't support the LIMIT_POWER parameter, assume that + * LIMIT_POWER is not requested. + */ + if (ret == -EC_RES_INVALID_PARAM || ret == -EC_RES_INVALID_COMMAND) { + log_warning("PARAM_LIMIT_POWER not supported by EC\n"); + return -ENOSYS; + } + + if (ret != sizeof(r.get_param)) + return -EINVAL; + + *limit_powerp = r.get_param.value; + return 0; +} + +int cros_ec_config_powerbtn(struct udevice *dev, uint32_t flags) +{ + struct ec_params_config_power_button params; + int ret; + + params.flags = flags; + ret = ec_command(dev, EC_CMD_CONFIG_POWER_BUTTON, 0, + ¶ms, sizeof(params), NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + +int cros_ec_get_lid_shutdown_mask(struct udevice *dev) +{ + u32 mask; + int ret; + + ret = cros_ec_get_event_mask(dev, EC_CMD_HOST_EVENT_GET_SMI_MASK, + &mask); + if (ret < 0) + return ret; + + return !!(mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)); +} + +int cros_ec_set_lid_shutdown_mask(struct udevice *dev, int enable) +{ + u32 mask; + int ret; + + ret = cros_ec_get_event_mask(dev, EC_CMD_HOST_EVENT_GET_SMI_MASK, + &mask); + if (ret < 0) + return ret; + + /* Set lid close event state in the EC SMI event mask */ + if (enable) + mask |= EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED); + else + mask &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED); + + ret = cros_ec_set_event_mask(dev, EC_CMD_HOST_EVENT_SET_SMI_MASK, mask); + if (ret < 0) + return ret; + + printf("EC: %sabled lid close event\n", enable ? "en" : "dis"); + return 0; +} + UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros_ec", .per_device_auto_alloc_size = sizeof(struct cros_ec_dev), .post_bind = dm_scan_fdt_dev, + .flags = DM_UC_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index d741554d8a..4fcb2d96f5 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -74,7 +74,7 @@ struct ec_keymatrix_entry { * @recovery_req: Keyboard recovery requested */ struct ec_state { - uint8_t vbnv_context[EC_VBNV_BLOCK_SIZE]; + u8 vbnv_context[EC_VBNV_BLOCK_SIZE_V2]; struct fdt_cros_ec ec_config; uint8_t *flash_data; int flash_data_len; @@ -313,13 +313,15 @@ static int process_cmd(struct ec_state *ec, switch (req->op) { case EC_VBNV_CONTEXT_OP_READ: + /* TODO(sjg@chromium.org): Support full-size context */ memcpy(resp->block, ec->vbnv_context, - sizeof(resp->block)); - len = sizeof(*resp); + EC_VBNV_BLOCK_SIZE); + len = 16; break; case EC_VBNV_CONTEXT_OP_WRITE: - memcpy(ec->vbnv_context, resp->block, - sizeof(resp->block)); + /* TODO(sjg@chromium.org): Support full-size context */ + memcpy(ec->vbnv_context, req->block, + EC_VBNV_BLOCK_SIZE); len = 0; break; default: diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index b7bb96a458..baa5f8302a 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -55,11 +55,9 @@ static int select_fs_dev(struct device_platdata *plat) node = ofnode_get_by_phandle(plat->phandlepart.phandle); - int of_offset = ofnode_to_offset(node); - struct udevice *dev; - ret = device_get_global_by_of_offset(of_offset, &dev); + ret = device_get_global_by_ofnode(node, &dev); if (!ret) { struct blk_desc *desc = blk_get_by_device(dev); if (desc) { @@ -190,8 +188,9 @@ static int fw_get_filesystem_firmware(struct device_platdata *plat, ret = fs_read(fw_priv->name, (ulong)map_to_sysmem(firmware->data), fw_priv->offset, firmware->size, &actread); + if (ret) { - debug("Error: %d Failed to read %s from flash %lld != %d.\n", + debug("Error: %d Failed to read %s from flash %lld != %zu.\n", ret, fw_priv->name, actread, firmware->size); } else { ret = actread; diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 7d66c3cf76..0c3394f2a8 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -7,6 +7,340 @@ #include #include +struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "cs0", +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + CONFIG_SYS_CSPR0, +#ifdef CONFIG_SYS_CSPR0_EXT + CONFIG_SYS_CSPR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK0 + CONFIG_SYS_AMASK0, +#else + 0, +#endif + CONFIG_SYS_CSOR0, + { + CONFIG_SYS_CS0_FTIM0, + CONFIG_SYS_CS0_FTIM1, + CONFIG_SYS_CS0_FTIM2, + CONFIG_SYS_CS0_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR0_EXT + CONFIG_SYS_CSOR0_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR0_FINAL + CONFIG_SYS_CSPR0_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK0_FINAL + CONFIG_SYS_AMASK0_FINAL, +#else + 0, +#endif +#endif + }, + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 + { + "cs1", +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + CONFIG_SYS_CSPR1, +#ifdef CONFIG_SYS_CSPR1_EXT + CONFIG_SYS_CSPR1_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1 + CONFIG_SYS_AMASK1, +#else + 0, +#endif + CONFIG_SYS_CSOR1, + { + CONFIG_SYS_CS1_FTIM0, + CONFIG_SYS_CS1_FTIM1, + CONFIG_SYS_CS1_FTIM2, + CONFIG_SYS_CS1_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR1_EXT + CONFIG_SYS_CSOR1_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR1_FINAL + CONFIG_SYS_CSPR1_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK1_FINAL + CONFIG_SYS_AMASK1_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 + { + "cs2", +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + CONFIG_SYS_CSPR2, +#ifdef CONFIG_SYS_CSPR2_EXT + CONFIG_SYS_CSPR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2 + CONFIG_SYS_AMASK2, +#else + 0, +#endif + CONFIG_SYS_CSOR2, + { + CONFIG_SYS_CS2_FTIM0, + CONFIG_SYS_CS2_FTIM1, + CONFIG_SYS_CS2_FTIM2, + CONFIG_SYS_CS2_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR2_EXT + CONFIG_SYS_CSOR2_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR2_FINAL + CONFIG_SYS_CSPR2_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK2_FINAL + CONFIG_SYS_AMASK2_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 + { + "cs3", +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + CONFIG_SYS_CSPR3, +#ifdef CONFIG_SYS_CSPR3_EXT + CONFIG_SYS_CSPR3_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3 + CONFIG_SYS_AMASK3, +#else + 0, +#endif + CONFIG_SYS_CSOR3, + { + CONFIG_SYS_CS3_FTIM0, + CONFIG_SYS_CS3_FTIM1, + CONFIG_SYS_CS3_FTIM2, + CONFIG_SYS_CS3_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR3_EXT + CONFIG_SYS_CSOR3_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR3_FINAL + CONFIG_SYS_CSPR3_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK3_FINAL + CONFIG_SYS_AMASK3_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 + { + "cs4", +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) + CONFIG_SYS_CSPR4, +#ifdef CONFIG_SYS_CSPR4_EXT + CONFIG_SYS_CSPR4_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4 + CONFIG_SYS_AMASK4, +#else + 0, +#endif + CONFIG_SYS_CSOR4, + { + CONFIG_SYS_CS4_FTIM0, + CONFIG_SYS_CS4_FTIM1, + CONFIG_SYS_CS4_FTIM2, + CONFIG_SYS_CS4_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR4_EXT + CONFIG_SYS_CSOR4_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR4_FINAL + CONFIG_SYS_CSPR4_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK4_FINAL + CONFIG_SYS_AMASK4_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6 + { + "cs5", +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) + CONFIG_SYS_CSPR5, +#ifdef CONFIG_SYS_CSPR5_EXT + CONFIG_SYS_CSPR5_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5 + CONFIG_SYS_AMASK5, +#else + 0, +#endif + CONFIG_SYS_CSOR5, + { + CONFIG_SYS_CS5_FTIM0, + CONFIG_SYS_CS5_FTIM1, + CONFIG_SYS_CS5_FTIM2, + CONFIG_SYS_CS5_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR5_EXT + CONFIG_SYS_CSOR5_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR5_FINAL + CONFIG_SYS_CSPR5_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK5_FINAL + CONFIG_SYS_AMASK5_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 + { + "cs6", +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) + CONFIG_SYS_CSPR6, +#ifdef CONFIG_SYS_CSPR6_EXT + CONFIG_SYS_CSPR6_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6 + CONFIG_SYS_AMASK6, +#else + 0, +#endif + CONFIG_SYS_CSOR6, + { + CONFIG_SYS_CS6_FTIM0, + CONFIG_SYS_CS6_FTIM1, + CONFIG_SYS_CS6_FTIM2, + CONFIG_SYS_CS6_FTIM3, + }, +#ifdef CONFIG_SYS_CSOR6_EXT + CONFIG_SYS_CSOR6_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_CSPR6_FINAL + CONFIG_SYS_CSPR6_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK6_FINAL + CONFIG_SYS_AMASK6_FINAL, +#else + 0, +#endif +#endif + }, +#endif + +#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 + { + "cs7", +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) + CONFIG_SYS_CSPR7, +#ifdef CONFIG_SYS_CSPR7_EXT + CONFIG_SYS_CSPR7_EXT, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK7 + CONFIG_SYS_AMASK7, +#else + 0, +#endif + CONFIG_SYS_CSOR7, +#ifdef CONFIG_SYS_CSOR7_EXT + CONFIG_SYS_CSOR7_EXT, +#else + 0, +#endif + { + CONFIG_SYS_CS7_FTIM0, + CONFIG_SYS_CS7_FTIM1, + CONFIG_SYS_CS7_FTIM2, + CONFIG_SYS_CS7_FTIM3, + }, +#ifdef CONFIG_SYS_CSPR7_FINAL + CONFIG_SYS_CSPR7_FINAL, +#else + 0, +#endif +#ifdef CONFIG_SYS_AMASK7_FINAL + CONFIG_SYS_AMASK7_FINAL, +#else + 0, +#endif +#endif + }, +#endif +}; + +__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + regs_info->regs = ifc_cfg_default_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + void print_ifc_regs(void) { int i, j; @@ -14,8 +348,8 @@ void print_ifc_regs(void) printf("IFC Controller Registers\n"); for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", - i, get_ifc_cspr(i), i, get_ifc_amask(i), - i, get_ifc_csor(i)); + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); for (j = 0; j < 4; j++) printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); } @@ -23,169 +357,51 @@ void print_ifc_regs(void) void init_early_memctl_regs(void) { -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); + int i, j; + struct ifc_regs *regs; + struct ifc_regs_info regs_info = {0}; -#ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); -#endif -#ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); -#endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; -#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); -#endif -#ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); -#endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); + for (i = 0 ; i < regs_info.cs_size; i++) { + if (regs[i].pr && (regs[i].pr & CSPR_V)) { + /* skip setting cspr/csor_ext in below condition */ + if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) && + i == 0 && + ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) { + if (regs[i].pr_ext) + set_ifc_cspr_ext(i, regs[i].pr_ext); + if (regs[i].or_ext) + set_ifc_csor_ext(i, regs[i].or_ext); + } - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); -#endif + for (j = 0; j < ARRAY_SIZE(regs->ftim); j++) + set_ifc_ftim(i, j, regs[i].ftim[j]); -#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); -#endif -#ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); -#endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); - - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); -#endif - -#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); -#endif -#ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); -#endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); - - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); -#endif - -#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); -#endif -#ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); -#endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); - - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); -#endif - -#ifdef CONFIG_SYS_CSPR5_EXT - set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); -#endif -#ifdef CONFIG_SYS_CSOR5_EXT - set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); -#endif -#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) - set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); - set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); - set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); - set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); - - set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); - set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); - set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); -#endif - -#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); -#endif -#ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); -#endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); - - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); -#endif - -#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); -#endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); -#endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); - - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); -#endif + set_ifc_csor(i, regs[i].or); + set_ifc_amask(i, regs[i].amask); + set_ifc_cspr(i, regs[i].pr); + } + } } void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); -#endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); -#endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); -#endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); -#endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); -#endif + int i; + struct ifc_regs *regs; + struct ifc_regs_info regs_info; + + ifc_cfg_boot_info(®s_info); + regs = regs_info.regs; + + for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) { + if (!(regs[i].pr_final & CSPR_V)) + continue; + if (regs[i].pr_final) + set_ifc_cspr(i, regs[i].pr_final); + if (regs[i].amask_final) + set_ifc_amask(i, (i == 1) ? regs[i].amask_final : + regs[i].amask); + } } diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c new file mode 100644 index 0000000000..94a21e08af --- /dev/null +++ b/drivers/misc/gdsys_soc.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include +#include +#include + +#include "gdsys_soc.h" + +/** + * struct gdsys_soc_priv - Private data for gdsys soc bus + * @fpga: The gdsys IHS FPGA this bus is associated with + */ +struct gdsys_soc_priv { + struct udevice *fpga; +}; + +static const struct udevice_id gdsys_soc_ids[] = { + { .compatible = "gdsys,soc" }, + { /* sentinel */ } +}; + +int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga) +{ + struct gdsys_soc_priv *bus_priv; + + if (!child->parent) { + debug("%s: Invalid parent\n", child->name); + return -EINVAL; + } + + if (!device_is_compatible(child->parent, "gdsys,soc")) { + debug("%s: Not child of a gdsys soc\n", child->name); + return -EINVAL; + } + + bus_priv = dev_get_priv(child->parent); + + *fpga = bus_priv->fpga; + + return 0; +} + +static int gdsys_soc_probe(struct udevice *dev) +{ + struct gdsys_soc_priv *priv = dev_get_priv(dev); + struct udevice *fpga; + int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga", + &fpga); + if (res == -ENOENT) { + debug("%s: Could not find 'fpga' phandle\n", dev->name); + return -EINVAL; + } + + if (res == -ENODEV) { + debug("%s: Could not get FPGA device\n", dev->name); + return -EINVAL; + } + + priv->fpga = fpga; + + return 0; +} + +U_BOOT_DRIVER(gdsys_soc_bus) = { + .name = "gdsys_soc_bus", + .id = UCLASS_SIMPLE_BUS, + .of_match = gdsys_soc_ids, + .probe = gdsys_soc_probe, + .priv_auto_alloc_size = sizeof(struct gdsys_soc_priv), +}; diff --git a/drivers/misc/gdsys_soc.h b/drivers/misc/gdsys_soc.h new file mode 100644 index 0000000000..088d3b6523 --- /dev/null +++ b/drivers/misc/gdsys_soc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef _GDSYS_SOC_H_ +#define _GDSYS_SOC_H_ + +/** + * gdsys_soc_get_fpga() - Retrieve pointer to parent bus' FPGA device + * @child: The child device on the FPGA bus needing access to the FPGA. + * @fpga: Pointer to the retrieved FPGA device. + * + * To access their register maps, devices on gdsys soc buses usually have + * facilitate the accessor function of the IHS FPGA their parent bus is + * attached to. To access the FPGA device from within the bus' children, this + * function returns a pointer to it. + * + * Return: 0 on success, -ve on failure + */ +int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga); +#endif /* _GDSYS_SOC_H_ */ diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c new file mode 100644 index 0000000000..f9e4b27a27 --- /dev/null +++ b/drivers/misc/ihs_fpga.c @@ -0,0 +1,867 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * based on the ioep-fpga driver, which is + * + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + */ + +#include +#include +#include +#include + +#include "ihs_fpga.h" + +/** + * struct ihs_fpga_priv - Private data structure for IHS FPGA driver + * @map: Register map for the FPGA's own register space + * @reset_gpio: GPIO to start FPGA reconfiguration + * @done_gpio: GPOI to read the 'ready' status of the FPGA + */ +struct ihs_fpga_priv { + struct regmap *map; + struct gpio_desc reset_gpio; + struct gpio_desc done_gpio; +}; + +/* Test pattern for reflection test */ +const u16 REFLECTION_TESTPATTERN = 0xdead; +/* Delay (in ms) for each round in the reflection test */ +const uint REFLECTION_TEST_DELAY = 100; +/* Maximum number of rounds in the reflection test */ +const uint REFLECTION_TEST_ROUNDS = 5; +/* Delay (in ms) for each round waiting for the FPGA's done GPIO */ +const uint FPGA_DONE_WAIT_DELAY = 100; +/* Maximum number of rounds for waiting for the FPGA's done GPIO */ +const uint FPGA_DONE_WAIT_ROUND = 5; + +/** + * enum pcb_video_type - Video type of the PCB + * @PCB_DVI_SL: Video type is DVI single-link + * @PCB_DP_165MPIX: Video type is DisplayPort (165Mpix) + * @PCB_DP_300MPIX: Video type is DisplayPort (300Mpix) + * @PCB_HDMI: Video type is HDMI + * @PCB_DP_1_2: Video type is DisplayPort 1.2 + * @PCB_HDMI_2_0: Video type is HDMI 2.0 + */ +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, +}; + +/** + * enum pcb_transmission_type - Transmission type of the PCB + * @PCB_CAT_1G: Transmission type is 1G Ethernet + * @PCB_FIBER_3G: Transmission type is 3G Fiber + * @PCB_CAT_10G: Transmission type is 10G Ethernet + * @PCB_FIBER_10G: Transmission type is 10G Fiber + */ +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, +}; + +/** + * enum carrier_speed - Speed of the FPGA's carrier + * @CARRIER_SPEED_1G: The carrier speed is 1G + * @CARRIER_SPEED_2_5G: The carrier speed is 2.5G + * @CARRIER_SPEED_3G: The carrier speed is 3G + * @CARRIER_SPEED_10G: The carrier speed is 10G + */ +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, +}; + +/** + * enum ram_config - FPGA's RAM configuration + * @RAM_DDR2_32BIT_295MBPS: DDR2 32 bit at 295Mb/s + * @RAM_DDR3_32BIT_590MBPS: DDR3 32 bit at 590Mb/s + * @RAM_DDR3_48BIT_590MBPS: DDR3 48 bit at 590Mb/s + * @RAM_DDR3_64BIT_1800MBPS: DDR3 64 bit at 1800Mb/s + * @RAM_DDR3_48BIT_1800MBPS: DDR3 48 bit at 1800Mb/s + */ +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, +}; + +/** + * enum sysclock - Speed of the FPGA's system clock + * @SYSCLK_147456: System clock is 147.456 MHz + */ +enum sysclock { + SYSCLK_147456, +}; + +/** + * struct fpga_versions - Data read from the versions register + * @video_channel: Is the FPGA for a video channel (true) or main + * channel (false) device? + * @con_side: Is the FPGA for a CON (true) or a CPU (false) device? + * @pcb_video_type: Defines for whch video type the FPGA is configured + * @pcb_transmission_type: Defines for which transmission type the FPGA is + * configured + * @hw_version: Hardware version of the FPGA + */ +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; +}; + +/** + * struct fpga_features - Data read from the features register + * @video_channels: Number of video channels supported + * @carriers: Number of carrier channels supported + * @carrier_speed: Speed of carriers + * @ram_config: RAM configuration of FPGA + * @sysclock: System clock speed of FPGA + * @pcm_tx: Support for PCM transmission + * @pcm_rx: Support for PCM reception + * @spdif_tx: Support for SPDIF audio transmission + * @spdif_rx: Support for SPDIF audio reception + * @usb2: Support for transparent USB2.0 + * @rs232: Support for bidirectional RS232 + * @compression_type1: Support for compression type 1 + * @compression_type2: Support for compression type 2 + * @compression_type3: Support for compression type 3 + * @interlace: Support for interlace image formats + * @osd: Support for a OSD + * @compression_pipes: Number of compression pipes supported + */ +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; +}; + +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +/** + * get_versions() - Fill structure with info from version register. + * @dev: FPGA device to be queried for information + * @versions: Pointer to the structure to fill with information from the + * versions register + * Return: 0 + */ +static int get_versions(struct udevice *dev, struct fpga_versions *versions) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + ihs_fpga_get(priv->map, versions, &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + return 0; +} + +/** + * get_features() - Fill structure with info from features register. + * @dev: FPGA device to be queried for information + * @features: Pointer to the structure to fill with information from the + * features register + * Return: 0 + */ +static int get_features(struct udevice *dev, struct fpga_features *features) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + ihs_fpga_get(priv->map, features, &raw_features); + ihs_fpga_get(priv->map, extended_features, &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; + break; + + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; + break; + + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; + break; + }; + + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; + break; + + case FEATURE_CARRIERS_1: + features->carriers = 1; + break; + + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; + break; + } + + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + } + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & + EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +/** + * get_versions() - Fill structure with info from version register. + * @fpga: Identifier of the FPGA device to be queried for information + * @versions: Pointer to the structure to fill with information from the + * versions register + * + * This is the legacy version and should be considered deprecated for new + * devices. + * + * Return: 0 + */ +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break; + + case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break; + + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; + break; + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; + break; + + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; + break; + + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; + break; + + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; + break; + } + + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK; + + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +/** + * get_features() - Fill structure with info from features register. + * @fpga: Identifier of the FPGA device to be queried for information + * @features: Pointer to the structure to fill with information from the + * features register + * + * This is the legacy version and should be considered deprecated for new + * devices. + * + * Return: 0 + */ +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; + break; + + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; + break; + } + + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; + features->spdif_tx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & + EXTENDED_FEATURE_SPDIF_AUDIO_RX; + + features->usb2 = raw_features & FEATURE_USB20; + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + /* fall-through */ + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + /* fall-through */ + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; + break; + } + + features->interlace = raw_extended_features & + EXTENDED_FEATURE_INTERLACE; + features->osd = raw_features & FEATURE_OSD; + features->compression_pipes = raw_extended_features & + EXTENDED_FEATURE_COMPRESSION_PIPES; + + return 0; +} + +#endif + +/** + * fpga_print_info() - Print information about FPGA device + * @dev: FPGA device to print information about + */ +static void fpga_print_info(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + u16 fpga_version; + struct fpga_versions versions; + struct fpga_features features; + + ihs_fpga_get(priv->map, fpga_version, &fpga_version); + get_versions(dev, &versions); + get_features(dev, &features); + + if (versions.video_channel) + printf("Videochannel"); + else + printf("Mainchannel"); + + if (versions.con_side) + printf(" User"); + else + printf(" Server"); + + switch (versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: + printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; + + switch (versions.pcb_video_type) { + case PCB_DVI_SL: + printf(" DVI,"); + break; + case PCB_DP_165MPIX: + printf(" DP 165MPix/s,"); + break; + case PCB_DP_300MPIX: + printf(" DP 300MPix/s,"); + break; + case PCB_HDMI: + printf(" HDMI,"); + break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); + break; + } + + printf(" FPGA V %d.%02d\n features: ", + fpga_version / 100, fpga_version % 100); + + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); + + if (features.compression_type1) + printf("type1, "); + + if (features.compression_type2) + printf("type2, "); + + if (features.compression_type3) + printf("type3, "); + + printf("%sosd", features.osd ? "" : "no "); + + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if (features.pcm_rx) + printf(", pcm rx"); + else if (features.pcm_tx) + printf(", pcm tx"); + + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if (features.spdif_rx) + printf(", spdif rx"); + else if (features.spdif_tx) + printf(", spdif tx"); + + puts(",\n "); + + switch (features.sysclock) { + case SYSCLK_147456: + printf("clock 147.456 MHz"); + break; + } + + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: + printf(", RAM 32 bit DDR2"); + break; + case RAM_DDR3_32BIT_590MBPS: + printf(", RAM 32 bit DDR3"); + break; + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: + printf(", RAM 48 bit DDR3"); + break; + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); + break; + } + + printf(", %d carrier(s)", features.carriers); + + switch (features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + } + + printf(", %d video channel(s)\n", features.video_channels); +} + +/** + * do_reflection_test() - Run reflection test on a FPGA device + * @dev: FPGA device to run reflection test on + * + * Return: 0 if reflection test succeeded, -ve on error + */ +static int do_reflection_test(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ctr = 0; + + while (1) { + u16 val; + + ihs_fpga_set(priv->map, reflection_low, REFLECTION_TESTPATTERN); + + ihs_fpga_get(priv->map, reflection_low, &val); + if (val == (~REFLECTION_TESTPATTERN & 0xffff)) + return -EIO; + + mdelay(REFLECTION_TEST_DELAY); + if (ctr++ > REFLECTION_TEST_ROUNDS) + return 0; + } +} + +/** + * wait_for_fpga_done() - Wait until 'done'-flag is set for FPGA device + * @dev: FPGA device whose done flag to wait for + * + * This function waits until it detects that the done-GPIO's value was changed + * to 1 by the FPGA, which indicates that the device is configured and ready to + * use. + * + * Return: 0 if done flag was detected, -ve on error + */ +static int wait_for_fpga_done(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ctr = 0; + int done_val; + + while (1) { + done_val = dm_gpio_get_value(&priv->done_gpio); + if (done_val < 0) { + debug("%s: Error while reading done-GPIO (err = %d)\n", + dev->name, done_val); + return done_val; + } + + if (done_val) + return 0; + + mdelay(FPGA_DONE_WAIT_DELAY); + if (ctr++ > FPGA_DONE_WAIT_ROUND) { + debug("%s: FPGA init failed (done not detected)\n", + dev->name); + return -EIO; + } + } +} + +static int ihs_fpga_probe(struct udevice *dev) +{ + struct ihs_fpga_priv *priv = dev_get_priv(dev); + int ret; + + /* TODO(mario.six@gdsys.cc): Case of FPGA attached to MCLink bus */ + + ret = regmap_init_mem(dev_ofnode(dev), &priv->map); + if (ret) { + debug("%s: Could not initialize regmap (err = %d)", + dev->name, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (ret) { + debug("%s: Could not get reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!priv->reset_gpio.dev) { + debug("%s: Could not get reset-GPIO\n", dev->name); + return -ENOENT; + } + + ret = gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio, + GPIOD_IS_IN); + if (ret) { + debug("%s: Could not get done-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!priv->done_gpio.dev) { + debug("%s: Could not get done-GPIO\n", dev->name); + return -ENOENT; + } + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + /* If FPGA already runs, don't initialize again */ + if (do_reflection_test(dev)) + goto reflection_ok; + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + ret = wait_for_fpga_done(dev); + if (ret) { + debug("%s: Error while waiting for FPGA done (err = %d)\n", + dev->name, ret); + return ret; + } + + udelay(10); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + debug("%s: Error while setting reset-GPIO (err = %d)\n", + dev->name, ret); + return ret; + } + + if (!do_reflection_test(dev)) { + debug("%s: Reflection test FAILED\n", dev->name); + return -EIO; + } + +reflection_ok: + printf("%s: Reflection test passed.\n", dev->name); + + fpga_print_info(dev); + + return 0; +} + +static const struct udevice_id ihs_fpga_ids[] = { + { .compatible = "gdsys,iocon_fpga" }, + { .compatible = "gdsys,iocpu_fpga" }, + { } +}; + +U_BOOT_DRIVER(ihs_fpga_bus) = { + .name = "ihs_fpga_bus", + .id = UCLASS_MISC, + .of_match = ihs_fpga_ids, + .probe = ihs_fpga_probe, + .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv), +}; diff --git a/drivers/misc/ihs_fpga.h b/drivers/misc/ihs_fpga.h new file mode 100644 index 0000000000..efb5dabb9c --- /dev/null +++ b/drivers/misc/ihs_fpga.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +/** + * struct ihs_fpga_regs - IHS FPGA register map structure + * @reflection_low: Lower reflection register + * @versions: PCB versions register + * @fpga_version: FPGA versions register + * @features: FPGA features register + * @extended_features: FPGA extended features register + * @top_interrupt: Top interrupt register + * @top_interrupt_enable: Top interrupt enable register + * @status: FPGA status register + * @control: FPGA control register + * @extended_control: FPGA extended control register + */ +struct ihs_fpga_regs { + u16 reflection_low; + u16 versions; + u16 fpga_version; + u16 features; + u16 extended_features; + u16 top_interrupt; + u16 top_interrupt_enable; + u16 status; + u16 control; + u16 extended_control; +}; + +/** + * ihs_fpga_set() - Convenience macro to set values in FPGA register map + * @map: Register map to set a value in + * @member: Name of member (described by ihs_fpga_regs) to set + * @val: Value to set the member to + */ +#define ihs_fpga_set(map, member, val) \ + regmap_set(map, struct ihs_fpga_regs, member, val) + +/** + * ihs_fpga_get() - Convenience macro to get values from FPGA register map + * @map: Register map to read value from + * @member: Name of member (described by ihs_fpga_regs) to get + * @valp: Pointe to variable to receive the value read + */ +#define ihs_fpga_get(map, member, valp) \ + regmap_get(map, struct ihs_fpga_regs, member, valp) diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 0647ddf103..b824ac79e6 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -223,7 +223,7 @@ static int imx8_scu_bind(struct udevice *dev) if (node < 0) panic("No clk node found\n"); - ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child); + ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child, true); if (ret) return ret; @@ -234,7 +234,7 @@ static int imx8_scu_bind(struct udevice *dev) if (node < 0) panic("No iomuxc node found\n"); - ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child); + ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child, true); if (ret) return ret; diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c new file mode 100644 index 0000000000..bc3dc93af2 --- /dev/null +++ b/drivers/misc/jz4780_efuse.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * JZ4780 EFUSE driver + * + * Copyright (c) 2014 Imagination Technologies + * Author: Alex Smith + */ + +#include +#include +#include +#include +#include +#include + +#define EFUSE_EFUCTRL 0xd0 +#define EFUSE_EFUCFG 0xd4 +#define EFUSE_EFUSTATE 0xd8 +#define EFUSE_EFUDATA(n) (0xdc + ((n) * 4)) + +#define EFUSE_EFUCTRL_RD_EN BIT(0) +#define EFUSE_EFUCTRL_LEN_BIT 16 +#define EFUSE_EFUCTRL_LEN_MASK 0x1f +#define EFUSE_EFUCTRL_ADDR_BIT 21 +#define EFUSE_EFUCTRL_ADDR_MASK 0x1ff +#define EFUSE_EFUCTRL_CS BIT(30) + +#define EFUSE_EFUCFG_RD_STROBE_BIT 16 +#define EFUSE_EFUCFG_RD_STROBE_MASK 0xf +#define EFUSE_EFUCFG_RD_ADJ_BIT 20 +#define EFUSE_EFUCFG_RD_ADJ_MASK 0xf + +#define EFUSE_EFUSTATE_RD_DONE BIT(0) + +static void jz4780_efuse_read_chunk(size_t addr, size_t count, u8 *buf) +{ + void __iomem *regs = (void __iomem *)NEMC_BASE; + size_t i; + u32 val; + int ret; + + val = EFUSE_EFUCTRL_RD_EN | + ((count - 1) << EFUSE_EFUCTRL_LEN_BIT) | + (addr << EFUSE_EFUCTRL_ADDR_BIT) | + ((addr > 0x200) ? EFUSE_EFUCTRL_CS : 0); + writel(val, regs + EFUSE_EFUCTRL); + + ret = wait_for_bit_le32(regs + EFUSE_EFUSTATE, + EFUSE_EFUSTATE_RD_DONE, true, 10000, false); + if (ret) + return; + + if ((count % 4) == 0) { + for (i = 0; i < count / 4; i++) { + val = readl(regs + EFUSE_EFUDATA(i)); + put_unaligned(val, (u32 *)(buf + (i * 4))); + } + } else { + val = readl(regs + EFUSE_EFUDATA(0)); + if (count > 2) + buf[2] = (val >> 16) & 0xff; + if (count > 1) + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; + } +} + +static inline int jz4780_efuse_chunk_size(size_t count) +{ + if (count >= 32) + return 32; + else if ((count / 4) > 0) + return (count / 4) * 4; + else + return count % 4; +} + +void jz4780_efuse_read(size_t addr, size_t count, u8 *buf) +{ + size_t chunk; + + while (count > 0) { + chunk = jz4780_efuse_chunk_size(count); + jz4780_efuse_read_chunk(addr, chunk, buf); + addr += chunk; + buf += chunk; + count -= chunk; + } +} + +void jz4780_efuse_init(u32 ahb2_rate) +{ + void __iomem *regs = (void __iomem *)NEMC_BASE; + u32 rd_adj, rd_strobe, tmp; + + rd_adj = (((6500 * (ahb2_rate / 1000000)) / 1000000) + 0xf) / 2; + tmp = (((35000 * (ahb2_rate / 1000000)) / 1000000) - 4) - rd_adj; + rd_strobe = ((tmp + 0xf) / 2 < 7) ? 7 : (tmp + 0xf) / 2; + + tmp = (rd_adj << EFUSE_EFUCFG_RD_ADJ_BIT) | + (rd_strobe << EFUSE_EFUCFG_RD_STROBE_BIT); + writel(tmp, regs + EFUSE_EFUCFG); +} diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c index e4164f76fb..f7c5b2e25f 100644 --- a/drivers/misc/misc_sandbox.c +++ b/drivers/misc/misc_sandbox.c @@ -20,7 +20,7 @@ int misc_sandbox_read(struct udevice *dev, int offset, void *buf, int size) memcpy(buf, priv->mem + offset, size); - return 0; + return size; } int misc_sandbox_write(struct udevice *dev, int offset, const void *buf, @@ -30,7 +30,7 @@ int misc_sandbox_write(struct udevice *dev, int offset, const void *buf, memcpy(priv->mem + offset, buf, size); - return 0; + return size; } int misc_sandbox_ioctl(struct udevice *dev, unsigned long request, void *buf) diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 9ff475d925..f84fe88db1 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -34,7 +34,7 @@ #define BM_OUT_STATUS_DED 0x00000400 #define BM_OUT_STATUS_LOCKED 0x00000800 #define BM_OUT_STATUS_PROGFAIL 0x00001000 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define BM_CTRL_ADDR 0x000000ff #else #define BM_CTRL_ADDR 0x0000007f @@ -80,7 +80,7 @@ #elif defined(CONFIG_MX7ULP) #define FUSE_BANK_SIZE 0x80 #define FUSE_BANKS 31 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define FUSE_BANK_SIZE 0x40 #define FUSE_BANKS 64 #else @@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef CONFIG_MX7 u32 addr = bank; -#elif defined CONFIG_MX8M +#elif defined CONFIG_IMX8M u32 addr = bank << 2 | word; #else u32 addr; diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c index 8a213c9e27..2520c6a38e 100644 --- a/drivers/misc/rockchip-efuse.c +++ b/drivers/misc/rockchip-efuse.c @@ -65,7 +65,7 @@ static int dump_efuses(cmd_tbl_t *cmdtp, int flag, } ret = misc_read(dev, 0, &fuses, sizeof(fuses)); - if (ret) { + if (ret < 0) { printf("%s: misc_read failed\n", __func__); return 0; } diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 2d661351a1..33943a231b 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -29,6 +29,9 @@ int fuse_read(u32 bank, u32 word, u32 *val) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, val, 4); + if (ret < 0) + return ret; + ret = 0; break; default: @@ -54,6 +57,9 @@ int fuse_prog(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET, &val, 4); + if (ret < 0) + return ret; + ret = 0; break; default: @@ -78,6 +84,9 @@ int fuse_sense(u32 bank, u32 word, u32 *val) if (ret) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4); + if (ret < 0) + return ret; + ret = 0; break; default: @@ -103,6 +112,9 @@ int fuse_override(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, &val, 4); + if (ret < 0) + return ret; + ret = 0; break; default: diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index bffb809f14..fa608cec1b 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -124,12 +124,21 @@ static int sandbox_swap_case_read_config(struct udevice *emul, uint offset, case PCI_CAP_ID_PM_OFFSET: *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM; break; + case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT: + *valuep = PCI_CAP_ID_EXP_OFFSET; + break; case PCI_CAP_ID_EXP_OFFSET: *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP; break; + case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT: + *valuep = PCI_CAP_ID_MSIX_OFFSET; + break; case PCI_CAP_ID_MSIX_OFFSET: *valuep = PCI_CAP_ID_MSIX; break; + case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT: + *valuep = 0; + break; case PCI_EXT_CAP_ID_ERR_OFFSET: *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR; break; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 27246ee465..496b2cba64 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,6 +332,12 @@ config MMC_BCM2835 If unsure, say N. +config JZ47XX_MMC + bool "Ingenic JZ47xx SD/MMC Host Controller support" + depends on ARCH_JZ47XX + help + This selects support for the SD Card Controller on Ingenic JZ47xx SoCs. + config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX @@ -569,6 +575,10 @@ config MMC_SUNXI_HAS_NEW_MODE bool depends on MMC_SUNXI +config MMC_SUNXI_HAS_MODE_SWITCH + bool + depends on MMC_SUNXI + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && ARCH_AT91 @@ -598,6 +608,17 @@ config FTSDC010_SDIO help This can enable ftsdc010 sdio function. +config MMC_MTK + bool "MediaTek SD/MMC Card Interface support" + depends on ARCH_MEDIATEK + depends on BLK && DM_MMC + depends on OF_CONTROL + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 23c5b0daef..7892c468f0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o +obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o @@ -65,3 +66,4 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3cdfa7f5a6..74007e2ad4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; #endif uint wml_value; @@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c new file mode 100644 index 0000000000..3132c3e191 --- /dev/null +++ b/drivers/mmc/jz_mmc.c @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ingenic JZ MMC driver + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ +#define MSC_STRPCL 0x000 +#define MSC_STAT 0x004 +#define MSC_CLKRT 0x008 +#define MSC_CMDAT 0x00c +#define MSC_RESTO 0x010 +#define MSC_RDTO 0x014 +#define MSC_BLKLEN 0x018 +#define MSC_NOB 0x01c +#define MSC_SNOB 0x020 +#define MSC_IMASK 0x024 +#define MSC_IREG 0x028 +#define MSC_CMD 0x02c +#define MSC_ARG 0x030 +#define MSC_RES 0x034 +#define MSC_RXFIFO 0x038 +#define MSC_TXFIFO 0x03c +#define MSC_LPM 0x040 +#define MSC_DMAC 0x044 +#define MSC_DMANDA 0x048 +#define MSC_DMADA 0x04c +#define MSC_DMALEN 0x050 +#define MSC_DMACMD 0x054 +#define MSC_CTRL2 0x058 +#define MSC_RTCNT 0x05c +#define MSC_DBG 0x0fc + +/* MSC Clock and Control Register (MSC_STRPCL) */ +#define MSC_STRPCL_EXIT_MULTIPLE BIT(7) +#define MSC_STRPCL_EXIT_TRANSFER BIT(6) +#define MSC_STRPCL_START_READWAIT BIT(5) +#define MSC_STRPCL_STOP_READWAIT BIT(4) +#define MSC_STRPCL_RESET BIT(3) +#define MSC_STRPCL_START_OP BIT(2) +#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0) +#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1) + +/* MSC Status Register (MSC_STAT) */ +#define MSC_STAT_AUTO_CMD_DONE BIT(31) +#define MSC_STAT_IS_RESETTING BIT(15) +#define MSC_STAT_SDIO_INT_ACTIVE BIT(14) +#define MSC_STAT_PRG_DONE BIT(13) +#define MSC_STAT_DATA_TRAN_DONE BIT(12) +#define MSC_STAT_END_CMD_RES BIT(11) +#define MSC_STAT_DATA_FIFO_AFULL BIT(10) +#define MSC_STAT_IS_READWAIT BIT(9) +#define MSC_STAT_CLK_EN BIT(8) +#define MSC_STAT_DATA_FIFO_FULL BIT(7) +#define MSC_STAT_DATA_FIFO_EMPTY BIT(6) +#define MSC_STAT_CRC_RES_ERR BIT(5) +#define MSC_STAT_CRC_READ_ERROR BIT(4) +#define MSC_STAT_CRC_WRITE_ERROR BIT(2) +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4) +#define MSC_STAT_TIME_OUT_RES BIT(1) +#define MSC_STAT_TIME_OUT_READ BIT(0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ +#define MSC_CLKRT_CLK_RATE_MASK 0x7 + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ +#define MSC_CMDAT_IO_ABORT BIT(11) +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9) +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9) +#define MSC_CMDAT_DMA_EN BIT(8) +#define MSC_CMDAT_INIT BIT(7) +#define MSC_CMDAT_BUSY BIT(6) +#define MSC_CMDAT_STREAM_BLOCK BIT(5) +#define MSC_CMDAT_WRITE BIT(4) +#define MSC_CMDAT_DATA_EN BIT(3) +#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0) +#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */ +#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */ +#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */ +#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */ +#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */ +#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */ +#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */ + +/* MSC Interrupts Mask Register (MSC_IMASK) */ +#define MSC_IMASK_TIME_OUT_RES BIT(9) +#define MSC_IMASK_TIME_OUT_READ BIT(8) +#define MSC_IMASK_SDIO BIT(7) +#define MSC_IMASK_TXFIFO_WR_REQ BIT(6) +#define MSC_IMASK_RXFIFO_RD_REQ BIT(5) +#define MSC_IMASK_END_CMD_RES BIT(2) +#define MSC_IMASK_PRG_DONE BIT(1) +#define MSC_IMASK_DATA_TRAN_DONE BIT(0) + +/* MSC Interrupts Status Register (MSC_IREG) */ +#define MSC_IREG_TIME_OUT_RES BIT(9) +#define MSC_IREG_TIME_OUT_READ BIT(8) +#define MSC_IREG_SDIO BIT(7) +#define MSC_IREG_TXFIFO_WR_REQ BIT(6) +#define MSC_IREG_RXFIFO_RD_REQ BIT(5) +#define MSC_IREG_END_CMD_RES BIT(2) +#define MSC_IREG_PRG_DONE BIT(1) +#define MSC_IREG_DATA_TRAN_DONE BIT(0) + +struct jz_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct jz_mmc_priv { + void __iomem *regs; + u32 flags; +/* priv flags */ +#define JZ_MMC_BUS_WIDTH_MASK 0x3 +#define JZ_MMC_BUS_WIDTH_1 0x0 +#define JZ_MMC_BUS_WIDTH_4 0x2 +#define JZ_MMC_BUS_WIDTH_8 0x3 +#define JZ_MMC_SENT_INIT BIT(2) +}; + +static int jz_mmc_clock_rate(void) +{ + return 24000000; +} + +static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv, + struct mmc_cmd *cmd, struct mmc_data *data) +{ + u32 stat, mask, cmdat = 0; + int i, ret; + + /* stop the clock */ + writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL); + ret = wait_for_bit_le32(priv->regs + MSC_STAT, + MSC_STAT_CLK_EN, false, 10000, false); + if (ret) + return ret; + + writel(0, priv->regs + MSC_DMAC); + + /* setup command */ + writel(cmd->cmdidx, priv->regs + MSC_CMD); + writel(cmd->cmdarg, priv->regs + MSC_ARG); + + if (data) { + /* setup data */ + cmdat |= MSC_CMDAT_DATA_EN; + if (data->flags & MMC_DATA_WRITE) + cmdat |= MSC_CMDAT_WRITE; + + writel(data->blocks, priv->regs + MSC_NOB); + writel(data->blocksize, priv->regs + MSC_BLKLEN); + } else { + writel(0, priv->regs + MSC_NOB); + writel(0, priv->regs + MSC_BLKLEN); + } + + /* setup response */ + switch (cmd->resp_type) { + case MMC_RSP_NONE: + break; + case MMC_RSP_R1: + case MMC_RSP_R1b: + cmdat |= MSC_CMDAT_RESPONSE_R1; + break; + case MMC_RSP_R2: + cmdat |= MSC_CMDAT_RESPONSE_R2; + break; + case MMC_RSP_R3: + cmdat |= MSC_CMDAT_RESPONSE_R3; + break; + default: + break; + } + + if (cmd->resp_type & MMC_RSP_BUSY) + cmdat |= MSC_CMDAT_BUSY; + + /* set init for the first command only */ + if (!(priv->flags & JZ_MMC_SENT_INIT)) { + cmdat |= MSC_CMDAT_INIT; + priv->flags |= JZ_MMC_SENT_INIT; + } + + cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9; + + /* write the data setup */ + writel(cmdat, priv->regs + MSC_CMDAT); + + /* unmask interrupts */ + mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES); + if (data) { + mask &= ~MSC_IMASK_DATA_TRAN_DONE; + if (data->flags & MMC_DATA_WRITE) { + mask &= ~MSC_IMASK_TXFIFO_WR_REQ; + } else { + mask &= ~(MSC_IMASK_RXFIFO_RD_REQ | + MSC_IMASK_TIME_OUT_READ); + } + } + writel(mask, priv->regs + MSC_IMASK); + + /* clear interrupts */ + writel(0xffffffff, priv->regs + MSC_IREG); + + /* start the command (& the clock) */ + writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START, + priv->regs + MSC_STRPCL); + + /* wait for completion */ + for (i = 0; i < 100; i++) { + stat = readl(priv->regs + MSC_IREG); + stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES; + if (stat) + break; + mdelay(1); + } + writel(stat, priv->regs + MSC_IREG); + if (stat & MSC_IREG_TIME_OUT_RES) + return -ETIMEDOUT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + /* read the response */ + if (cmd->resp_type & MMC_RSP_136) { + u16 a, b, c, i; + + a = readw(priv->regs + MSC_RES); + for (i = 0; i < 4; i++) { + b = readw(priv->regs + MSC_RES); + c = readw(priv->regs + MSC_RES); + cmd->response[i] = + (a << 24) | (b << 8) | (c >> 8); + a = c; + } + } else { + cmd->response[0] = readw(priv->regs + MSC_RES) << 24; + cmd->response[0] |= readw(priv->regs + MSC_RES) << 8; + cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff; + } + } + + if (data && (data->flags & MMC_DATA_WRITE)) { + /* write the data */ + int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4); + const void *buf = data->src; + + while (sz--) { + u32 val = get_unaligned_le32(buf); + + wait_for_bit_le32(priv->regs + MSC_IREG, + MSC_IREG_TXFIFO_WR_REQ, + true, 10000, false); + writel(val, priv->regs + MSC_TXFIFO); + buf += 4; + } + } else if (data && (data->flags & MMC_DATA_READ)) { + /* read the data */ + int sz = data->blocks * data->blocksize; + void *buf = data->dest; + + do { + stat = readl(priv->regs + MSC_STAT); + + if (stat & MSC_STAT_TIME_OUT_READ) + return -ETIMEDOUT; + if (stat & MSC_STAT_CRC_READ_ERROR) + return -EINVAL; + if (stat & MSC_STAT_DATA_FIFO_EMPTY) { + udelay(10); + continue; + } + do { + u32 val = readl(priv->regs + MSC_RXFIFO); + + if (sz == 1) + *(u8 *)buf = (u8)val; + else if (sz == 2) + put_unaligned_le16(val, buf); + else if (sz >= 4) + put_unaligned_le32(val, buf); + buf += 4; + sz -= 4; + stat = readl(priv->regs + MSC_STAT); + } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY)); + } while (!(stat & MSC_STAT_DATA_TRAN_DONE)); + } + + return 0; +} + +static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv) +{ + u32 real_rate = jz_mmc_clock_rate(); + u8 clk_div = 0; + + /* calculate clock divide */ + while ((real_rate > mmc->clock) && (clk_div < 7)) { + real_rate >>= 1; + clk_div++; + } + writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT); + + /* set the bus width for the next command */ + priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK; + if (mmc->bus_width == 8) + priv->flags |= JZ_MMC_BUS_WIDTH_8; + else if (mmc->bus_width == 4) + priv->flags |= JZ_MMC_BUS_WIDTH_4; + else + priv->flags |= JZ_MMC_BUS_WIDTH_1; + + return 0; +} + +static int jz_mmc_core_init(struct mmc *mmc) +{ + struct jz_mmc_priv *priv = mmc->priv; + int ret; + + /* Reset */ + writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL); + ret = wait_for_bit_le32(priv->regs + MSC_STAT, + MSC_STAT_IS_RESETTING, false, 10000, false); + if (ret) + return ret; + + /* Maximum timeouts */ + writel(0xffff, priv->regs + MSC_RESTO); + writel(0xffffffff, priv->regs + MSC_RDTO); + + /* Enable low power mode */ + writel(0x1, priv->regs + MSC_LPM); + + return 0; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) + +static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct jz_mmc_priv *priv = mmc->priv; + + return jz_mmc_send_cmd(mmc, priv, cmd, data); +} + +static int jz_mmc_legacy_set_ios(struct mmc *mmc) +{ + struct jz_mmc_priv *priv = mmc->priv; + + return jz_mmc_set_ios(mmc, priv); +}; + +static const struct mmc_ops jz_msc_ops = { + .send_cmd = jz_mmc_legacy_send_cmd, + .set_ios = jz_mmc_legacy_set_ios, + .init = jz_mmc_core_init, +}; + +static struct jz_mmc_priv jz_mmc_priv_static; +static struct jz_mmc_plat jz_mmc_plat_static = { + .cfg = { + .name = "MSC", + .ops = &jz_msc_ops, + + .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | + MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36, + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS, + + .f_min = 375000, + .f_max = 48000000, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, + }, +}; + +int jz_mmc_init(void __iomem *base) +{ + struct mmc *mmc; + + jz_mmc_priv_static.regs = base; + + mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static); + + return mmc ? 0 : -ENODEV; +} + +#else /* CONFIG_DM_MMC */ + +#include +DECLARE_GLOBAL_DATA_PTR; + +static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return jz_mmc_send_cmd(mmc, priv, cmd, data); +} + +static int jz_mmc_dm_set_ios(struct udevice *dev) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return jz_mmc_set_ios(mmc, priv); +}; + +static const struct dm_mmc_ops jz_msc_ops = { + .send_cmd = jz_mmc_dm_send_cmd, + .set_ios = jz_mmc_dm_set_ios, +}; + +static int jz_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct jz_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg; + int ret; + + priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE); + cfg = &plat->cfg; + + cfg->name = "MSC"; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + ret = mmc_of_parse(dev, cfg); + if (ret < 0) { + dev_err(dev, "failed to parse host caps\n"); + return ret; + } + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + return 0; +} + +static int jz_mmc_bind(struct udevice *dev) +{ + struct jz_mmc_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int jz_mmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct jz_mmc_priv *priv = dev_get_priv(dev); + struct jz_mmc_plat *plat = dev_get_platdata(dev); + + plat->mmc.priv = priv; + upriv->mmc = &plat->mmc; + return jz_mmc_core_init(&plat->mmc); +} + +static const struct udevice_id jz_mmc_ids[] = { + { .compatible = "ingenic,jz4780-mmc" }, + { } +}; + +U_BOOT_DRIVER(jz_mmc_drv) = { + .name = "jz_mmc", + .id = UCLASS_MMC, + .of_match = jz_mmc_ids, + .ofdata_to_platdata = jz_mmc_ofdata_to_platdata, + .bind = jz_mmc_bind, + .probe = jz_mmc_probe, + .priv_auto_alloc_size = sizeof(struct jz_mmc_priv), + .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat), + .ops = &jz_msc_ops, +}; +#endif /* CONFIG_DM_MMC */ diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 332f1e12a5..767dfff805 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -278,6 +278,7 @@ int meson_mmc_bind(struct udevice *dev) static const struct udevice_id meson_mmc_match[] = { { .compatible = "amlogic,meson-gx-mmc" }, + { .compatible = "amlogic,meson-axg-mmc" }, { /* sentinel */ } }; diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index f73f07254b..76225b7939 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -166,6 +166,10 @@ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg) cfg->host_caps |= MMC_CAP(MMC_HS_200); if (dev_read_bool(dev, "mmc-hs200-1_2v")) cfg->host_caps |= MMC_CAP(MMC_HS_200); + if (dev_read_bool(dev, "mmc-hs400-1_8v")) + cfg->host_caps |= MMC_CAP(MMC_HS_400); + if (dev_read_bool(dev, "mmc-hs400-1_2v")) + cfg->host_caps |= MMC_CAP(MMC_HS_400); return 0; } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 585951cd78..f5c821e308 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1289,6 +1289,10 @@ static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); int speed; + /* SD version 1.00 and 1.01 does not support CMD 6 */ + if (mmc->version == SD_VERSION_1_0) + return 0; + switch (mode) { case SD_LEGACY: speed = UHS_SDR12_BUS_SPEED; @@ -2444,9 +2448,6 @@ static int mmc_startup(struct mmc *mmc) bdesc->product[0] = 0; bdesc->revision[0] = 0; #endif -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) - part_init(bdesc); -#endif return 0; } diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index a9d95fbd74..4f57990d9c 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c new file mode 100644 index 0000000000..0741a525c0 --- /dev/null +++ b/drivers/mmc/mtk-sd.c @@ -0,0 +1,1394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek SD/MMC Card Interface driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MSDC_CFG */ +#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) +#define MSDC_CFG_CKMOD_EXT_M 0x300000 +#define MSDC_CFG_CKMOD_EXT_S 20 +#define MSDC_CFG_CKDIV_EXT_M 0xfff00 +#define MSDC_CFG_CKDIV_EXT_S 8 +#define MSDC_CFG_HS400_CK_MODE BIT(18) +#define MSDC_CFG_CKMOD_M 0x30000 +#define MSDC_CFG_CKMOD_S 16 +#define MSDC_CFG_CKDIV_M 0xff00 +#define MSDC_CFG_CKDIV_S 8 +#define MSDC_CFG_CKSTB BIT(7) +#define MSDC_CFG_PIO BIT(3) +#define MSDC_CFG_RST BIT(2) +#define MSDC_CFG_CKPDN BIT(1) +#define MSDC_CFG_MODE BIT(0) + +/* MSDC_IOCON */ +#define MSDC_IOCON_W_DSPL BIT(8) +#define MSDC_IOCON_DSPL BIT(2) +#define MSDC_IOCON_RSPL BIT(1) + +/* MSDC_PS */ +#define MSDC_PS_DAT0 BIT(16) +#define MSDC_PS_CDDBCE_M 0xf000 +#define MSDC_PS_CDDBCE_S 12 +#define MSDC_PS_CDSTS BIT(1) +#define MSDC_PS_CDEN BIT(0) + +/* #define MSDC_INT(EN) */ +#define MSDC_INT_ACMDRDY BIT(3) +#define MSDC_INT_ACMDTMO BIT(4) +#define MSDC_INT_ACMDCRCERR BIT(5) +#define MSDC_INT_CMDRDY BIT(8) +#define MSDC_INT_CMDTMO BIT(9) +#define MSDC_INT_RSPCRCERR BIT(10) +#define MSDC_INT_XFER_COMPL BIT(12) +#define MSDC_INT_DATTMO BIT(14) +#define MSDC_INT_DATCRCERR BIT(15) + +/* MSDC_FIFOCS */ +#define MSDC_FIFOCS_CLR BIT(31) +#define MSDC_FIFOCS_TXCNT_M 0xff0000 +#define MSDC_FIFOCS_TXCNT_S 16 +#define MSDC_FIFOCS_RXCNT_M 0xff +#define MSDC_FIFOCS_RXCNT_S 0 + +/* #define SDC_CFG */ +#define SDC_CFG_DTOC_M 0xff000000 +#define SDC_CFG_DTOC_S 24 +#define SDC_CFG_SDIOIDE BIT(20) +#define SDC_CFG_SDIO BIT(19) +#define SDC_CFG_BUSWIDTH_M 0x30000 +#define SDC_CFG_BUSWIDTH_S 16 + +/* SDC_CMD */ +#define SDC_CMD_BLK_LEN_M 0xfff0000 +#define SDC_CMD_BLK_LEN_S 16 +#define SDC_CMD_STOP BIT(14) +#define SDC_CMD_WR BIT(13) +#define SDC_CMD_DTYPE_M 0x1800 +#define SDC_CMD_DTYPE_S 11 +#define SDC_CMD_RSPTYP_M 0x380 +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_CMD_M 0x3f +#define SDC_CMD_CMD_S 0 + +/* SDC_STS */ +#define SDC_STS_CMDBUSY BIT(1) +#define SDC_STS_SDCBUSY BIT(0) + +/* SDC_ADV_CFG0 */ +#define SDC_RX_ENHANCE_EN BIT(20) + +/* PATCH_BIT0 */ +#define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380 +#define MSDC_INT_DAT_LATCH_CK_SEL_S 7 + +/* PATCH_BIT1 */ +#define MSDC_PB1_STOP_DLY_M 0xf00 +#define MSDC_PB1_STOP_DLY_S 8 + +/* PATCH_BIT2 */ +#define MSDC_PB2_CRCSTSENSEL_M 0xe0000000 +#define MSDC_PB2_CRCSTSENSEL_S 29 +#define MSDC_PB2_CFGCRCSTS BIT(28) +#define MSDC_PB2_RESPSTSENSEL_M 0x70000 +#define MSDC_PB2_RESPSTSENSEL_S 16 +#define MSDC_PB2_CFGRESP BIT(15) +#define MSDC_PB2_RESPWAIT_M 0x0c +#define MSDC_PB2_RESPWAIT_S 2 + +/* PAD_TUNE */ +#define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000 +#define MSDC_PAD_TUNE_CMDRRDLY_S 22 +#define MSDC_PAD_TUNE_CMD_SEL BIT(21) +#define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000 +#define MSDC_PAD_TUNE_CMDRDLY_S 16 +#define MSDC_PAD_TUNE_RXDLYSEL BIT(15) +#define MSDC_PAD_TUNE_RD_SEL BIT(13) +#define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00 +#define MSDC_PAD_TUNE_DATRRDLY_S 8 +#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f +#define MSDC_PAD_TUNE_DATWRDLY_S 0 + +/* EMMC50_CFG0 */ +#define EMMC50_CFG_CFCSTS_SEL BIT(4) + +/* SDC_FIFO_CFG */ +#define SDC_FIFO_CFG_WRVALIDSEL BIT(24) +#define SDC_FIFO_CFG_RDVALIDSEL BIT(25) + +/* SDC_CFG_BUSWIDTH */ +#define MSDC_BUS_1BITS 0x0 +#define MSDC_BUS_4BITS 0x1 +#define MSDC_BUS_8BITS 0x2 + +#define MSDC_FIFO_SIZE 128 + +#define PAD_DELAY_MAX 32 + +#define DEFAULT_CD_DEBOUNCE 8 + +#define CMD_INTS_MASK \ + (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) + +#define DATA_INTS_MASK \ + (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR) + +/* Register offset */ +struct mtk_sd_regs { + u32 msdc_cfg; + u32 msdc_iocon; + u32 msdc_ps; + u32 msdc_int; + u32 msdc_inten; + u32 msdc_fifocs; + u32 msdc_txdata; + u32 msdc_rxdata; + u32 reserved0[4]; + u32 sdc_cfg; + u32 sdc_cmd; + u32 sdc_arg; + u32 sdc_sts; + u32 sdc_resp[4]; + u32 sdc_blk_num; + u32 sdc_vol_chg; + u32 sdc_csts; + u32 sdc_csts_en; + u32 sdc_datcrc_sts; + u32 sdc_adv_cfg0; + u32 reserved1[2]; + u32 emmc_cfg0; + u32 emmc_cfg1; + u32 emmc_sts; + u32 emmc_iocon; + u32 sd_acmd_resp; + u32 sd_acmd19_trg; + u32 sd_acmd19_sts; + u32 dma_sa_high4bit; + u32 dma_sa; + u32 dma_ca; + u32 dma_ctrl; + u32 dma_cfg; + u32 sw_dbg_sel; + u32 sw_dbg_out; + u32 dma_length; + u32 reserved2; + u32 patch_bit0; + u32 patch_bit1; + u32 patch_bit2; + u32 reserved3; + u32 dat0_tune_crc; + u32 dat1_tune_crc; + u32 dat2_tune_crc; + u32 dat3_tune_crc; + u32 cmd_tune_crc; + u32 sdio_tune_wind; + u32 reserved4[5]; + u32 pad_tune; + u32 pad_tune0; + u32 pad_tune1; + u32 dat_rd_dly[4]; + u32 reserved5[2]; + u32 hw_dbg_sel; + u32 main_ver; + u32 eco_ver; + u32 reserved6[27]; + u32 pad_ds_tune; + u32 reserved7[31]; + u32 emmc50_cfg0; + u32 reserved8[7]; + u32 sdc_fifo_cfg; +}; + +struct msdc_compatible { + u8 clk_div_bits; + bool pad_tune0; + bool async_fifo; + bool data_tune; + bool busy_check; + bool stop_clk_fix; + bool enhance_rx; +}; + +struct msdc_delay_phase { + u8 maxlen; + u8 start; + u8 final_phase; +}; + +struct msdc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct msdc_tune_para { + u32 iocon; + u32 pad_tune; +}; + +struct msdc_host { + struct mtk_sd_regs *base; + struct mmc *mmc; + + struct msdc_compatible *dev_comp; + + struct clk src_clk; /* for SD/MMC bus clock */ + struct clk h_clk; /* MSDC core clock */ + + u32 src_clk_freq; /* source clock */ + u32 mclk; /* mmc framework required bus clock */ + u32 sclk; /* actual calculated bus clock */ + + /* operation timeout clocks */ + u32 timeout_ns; + u32 timeout_clks; + + /* tuning options */ + u32 hs400_ds_delay; + u32 hs200_cmd_int_delay; + u32 hs200_write_int_delay; + u32 latch_ck; + u32 r_smpl; /* sample edge */ + bool hs400_mode; + + /* whether to use gpio detection or built-in hw detection */ + bool builtin_cd; + + /* card detection / write protection GPIOs */ +#ifdef CONFIG_DM_GPIO + struct gpio_desc gpio_wp; + struct gpio_desc gpio_cd; +#endif + + uint last_resp_type; + uint last_data_write; + + enum bus_mode timing; + + struct msdc_tune_para def_tune_para; + struct msdc_tune_para saved_tune_para; +}; + +static void msdc_reset_hw(struct msdc_host *host) +{ + u32 reg; + + setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); + + readl_poll_timeout(&host->base->msdc_cfg, reg, + !(reg & MSDC_CFG_RST), 1000000); +} + +static void msdc_fifo_clr(struct msdc_host *host) +{ + u32 reg; + + setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); + + readl_poll_timeout(&host->base->msdc_fifocs, reg, + !(reg & MSDC_FIFOCS_CLR), 1000000); +} + +static u32 msdc_fifo_rx_bytes(struct msdc_host *host) +{ + return (readl(&host->base->msdc_fifocs) & + MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S; +} + +static u32 msdc_fifo_tx_bytes(struct msdc_host *host) +{ + return (readl(&host->base->msdc_fifocs) & + MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S; +} + +static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd) +{ + u32 resp; + + switch (cmd->resp_type) { + /* Actually, R1, R5, R6, R7 are the same */ + case MMC_RSP_R1: + resp = 0x1; + break; + case MMC_RSP_R1b: + resp = 0x7; + break; + case MMC_RSP_R2: + resp = 0x2; + break; + case MMC_RSP_R3: + resp = 0x3; + break; + case MMC_RSP_NONE: + default: + resp = 0x0; + break; + } + + return resp; +} + +static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, + struct mmc_cmd *cmd, + struct mmc_data *data) +{ + u32 opcode = cmd->cmdidx; + u32 resp_type = msdc_cmd_find_resp(host, cmd); + uint blocksize = 0; + u32 dtype = 0; + u32 rawcmd = 0; + + switch (opcode) { + case MMC_CMD_WRITE_MULTIPLE_BLOCK: + case MMC_CMD_READ_MULTIPLE_BLOCK: + dtype = 2; + break; + case MMC_CMD_WRITE_SINGLE_BLOCK: + case MMC_CMD_READ_SINGLE_BLOCK: + case SD_CMD_APP_SEND_SCR: + dtype = 1; + break; + case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */ + case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */ + case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */ + if (data) + dtype = 1; + } + + if (data) { + if (data->flags == MMC_DATA_WRITE) + rawcmd |= SDC_CMD_WR; + + if (data->blocks > 1) + dtype = 2; + + blocksize = data->blocksize; + } + + rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) | + ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) | + ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) | + ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M); + + if (opcode == MMC_CMD_STOP_TRANSMISSION) + rawcmd |= SDC_CMD_STOP; + + return rawcmd; +} + +static int msdc_cmd_done(struct msdc_host *host, int events, + struct mmc_cmd *cmd) +{ + u32 *rsp = cmd->response; + int ret = 0; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + rsp[0] = readl(&host->base->sdc_resp[3]); + rsp[1] = readl(&host->base->sdc_resp[2]); + rsp[2] = readl(&host->base->sdc_resp[1]); + rsp[3] = readl(&host->base->sdc_resp[0]); + } else { + rsp[0] = readl(&host->base->sdc_resp[0]); + } + } + + if (!(events & MSDC_INT_CMDRDY)) { + if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && + cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) + /* + * should not clear fifo/interrupt as the tune data + * may have alreay come. + */ + msdc_reset_hw(host); + + if (events & MSDC_INT_CMDTMO) + ret = -ETIMEDOUT; + else + ret = -EIO; + } + + return ret; +} + +static bool msdc_cmd_is_ready(struct msdc_host *host) +{ + int ret; + u32 reg; + + /* The max busy time we can endure is 20ms */ + ret = readl_poll_timeout(&host->base->sdc_sts, reg, + !(reg & SDC_STS_CMDBUSY), 20000); + + if (ret) { + pr_err("CMD bus busy detected\n"); + msdc_reset_hw(host); + return false; + } + + if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) { + ret = readl_poll_timeout(&host->base->msdc_ps, reg, + reg & MSDC_PS_DAT0, 1000000); + + if (ret) { + pr_err("Card stuck in programming state!\n"); + msdc_reset_hw(host); + return false; + } + } + + return true; +} + +static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + u32 rawcmd; + u32 status; + u32 blocks = 0; + int ret; + + if (!msdc_cmd_is_ready(host)) + return -EIO; + + msdc_fifo_clr(host); + + host->last_resp_type = cmd->resp_type; + host->last_data_write = 0; + + rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data); + + if (data) + blocks = data->blocks; + + writel(CMD_INTS_MASK, &host->base->msdc_int); + writel(blocks, &host->base->sdc_blk_num); + writel(cmd->cmdarg, &host->base->sdc_arg); + writel(rawcmd, &host->base->sdc_cmd); + + ret = readl_poll_timeout(&host->base->msdc_int, status, + status & CMD_INTS_MASK, 1000000); + + if (ret) + status = MSDC_INT_CMDTMO; + + return msdc_cmd_done(host, status, cmd); +} + +static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size) +{ + u32 *wbuf; + + while ((size_t)buf % 4) { + *buf++ = readb(&host->base->msdc_rxdata); + size--; + } + + wbuf = (u32 *)buf; + while (size >= 4) { + *wbuf++ = readl(&host->base->msdc_rxdata); + size -= 4; + } + + buf = (u8 *)wbuf; + while (size) { + *buf++ = readb(&host->base->msdc_rxdata); + size--; + } +} + +static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size) +{ + const u32 *wbuf; + + while ((size_t)buf % 4) { + writeb(*buf++, &host->base->msdc_txdata); + size--; + } + + wbuf = (const u32 *)buf; + while (size >= 4) { + writel(*wbuf++, &host->base->msdc_txdata); + size -= 4; + } + + buf = (const u8 *)wbuf; + while (size) { + writeb(*buf++, &host->base->msdc_txdata); + size--; + } +} + +static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size) +{ + u32 status; + u32 chksz; + int ret = 0; + + while (1) { + status = readl(&host->base->msdc_int); + writel(status, &host->base->msdc_int); + status &= DATA_INTS_MASK; + + if (status & MSDC_INT_DATCRCERR) { + ret = -EIO; + break; + } + + if (status & MSDC_INT_DATTMO) { + ret = -ETIMEDOUT; + break; + } + + if (status & MSDC_INT_XFER_COMPL) { + if (size) { + pr_err("data not fully read\n"); + ret = -EIO; + } + + break; + } + + chksz = min(size, (u32)MSDC_FIFO_SIZE); + + if (msdc_fifo_rx_bytes(host) >= chksz) { + msdc_fifo_read(host, ptr, chksz); + ptr += chksz; + size -= chksz; + } + } + + return ret; +} + +static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size) +{ + u32 status; + u32 chksz; + int ret = 0; + + while (1) { + status = readl(&host->base->msdc_int); + writel(status, &host->base->msdc_int); + status &= DATA_INTS_MASK; + + if (status & MSDC_INT_DATCRCERR) { + ret = -EIO; + break; + } + + if (status & MSDC_INT_DATTMO) { + ret = -ETIMEDOUT; + break; + } + + if (status & MSDC_INT_XFER_COMPL) { + if (size) { + pr_err("data not fully written\n"); + ret = -EIO; + } + + break; + } + + chksz = min(size, (u32)MSDC_FIFO_SIZE); + + if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) { + msdc_fifo_write(host, ptr, chksz); + ptr += chksz; + size -= chksz; + } + } + + return ret; +} + +static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) +{ + u32 size; + int ret; + + if (data->flags == MMC_DATA_WRITE) + host->last_data_write = 1; + + writel(DATA_INTS_MASK, &host->base->msdc_int); + + size = data->blocks * data->blocksize; + + if (data->flags == MMC_DATA_WRITE) + ret = msdc_pio_write(host, (const u8 *)data->src, size); + else + ret = msdc_pio_read(host, (u8 *)data->dest, size); + + if (ret) { + msdc_reset_hw(host); + msdc_fifo_clr(host); + } + + return ret; +} + +static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct msdc_host *host = dev_get_priv(dev); + int ret; + + ret = msdc_start_command(host, cmd, data); + if (ret) + return ret; + + if (data) + return msdc_start_data(host, data); + + return 0; +} + +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +{ + u32 timeout, clk_ns; + u32 mode = 0; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + if (host->sclk == 0) { + timeout = 0; + } else { + clk_ns = 1000000000UL / host->sclk; + timeout = (ns + clk_ns - 1) / clk_ns + clks; + /* unit is 1048576 sclk cycles */ + timeout = (timeout + (0x1 << 20) - 1) >> 20; + if (host->dev_comp->clk_div_bits == 8) + mode = (readl(&host->base->msdc_cfg) & + MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S; + else + mode = (readl(&host->base->msdc_cfg) & + MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S; + /* DDR mode will double the clk cycles for data timeout */ + timeout = mode >= 2 ? timeout * 2 : timeout; + timeout = timeout > 1 ? timeout - 1 : 0; + timeout = timeout > 255 ? 255 : timeout; + } + + clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, + timeout << SDC_CFG_DTOC_S); +} + +static void msdc_set_buswidth(struct msdc_host *host, u32 width) +{ + u32 val = readl(&host->base->sdc_cfg); + + val &= ~SDC_CFG_BUSWIDTH_M; + + switch (width) { + default: + case 1: + val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S); + break; + case 4: + val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S); + break; + case 8: + val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S); + break; + } + + writel(val, &host->base->sdc_cfg); +} + +static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz) +{ + u32 mode; + u32 div; + u32 sclk; + u32 reg; + + if (!hz) { + host->mclk = 0; + clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); + return; + } + + if (host->dev_comp->clk_div_bits == 8) + clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE); + else + clrbits_le32(&host->base->msdc_cfg, + MSDC_CFG_HS400_CK_MODE_EXT); + + if (timing == UHS_DDR50 || timing == MMC_DDR_52 || + timing == MMC_HS_400) { + if (timing == MMC_HS_400) + mode = 0x3; + else + mode = 0x2; /* ddr mode and use divisor */ + + if (hz >= (host->src_clk_freq >> 2)) { + div = 0; /* mean div = 1/4 */ + sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ + } else { + div = (host->src_clk_freq + ((hz << 2) - 1)) / + (hz << 2); + sclk = (host->src_clk_freq >> 2) / div; + div = (div >> 1); + } + + if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) { + if (host->dev_comp->clk_div_bits == 8) + setbits_le32(&host->base->msdc_cfg, + MSDC_CFG_HS400_CK_MODE); + else + setbits_le32(&host->base->msdc_cfg, + MSDC_CFG_HS400_CK_MODE_EXT); + + sclk = host->src_clk_freq >> 1; + div = 0; /* div is ignore when bit18 is set */ + } + } else if (hz >= host->src_clk_freq) { + mode = 0x1; /* no divisor */ + div = 0; + sclk = host->src_clk_freq; + } else { + mode = 0x0; /* use divisor */ + if (hz >= (host->src_clk_freq >> 1)) { + div = 0; /* mean div = 1/2 */ + sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ + } else { + div = (host->src_clk_freq + ((hz << 2) - 1)) / + (hz << 2); + sclk = (host->src_clk_freq >> 2) / div; + } + } + + clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); + + if (host->dev_comp->clk_div_bits == 8) { + div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S)); + clrsetbits_le32(&host->base->msdc_cfg, + MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M, + (mode << MSDC_CFG_CKMOD_S) | + (div << MSDC_CFG_CKDIV_S)); + } else { + div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >> + MSDC_CFG_CKDIV_EXT_S)); + clrsetbits_le32(&host->base->msdc_cfg, + MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M, + (mode << MSDC_CFG_CKMOD_EXT_S) | + (div << MSDC_CFG_CKDIV_EXT_S)); + } + + readl_poll_timeout(&host->base->msdc_cfg, reg, + reg & MSDC_CFG_CKSTB, 1000000); + + setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); + host->sclk = sclk; + host->mclk = hz; + host->timing = timing; + + /* needed because clk changed. */ + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); + + /* + * mmc_select_hs400() will drop to 50Mhz and High speed mode, + * tune result of hs200/200Mhz is not suitable for 50Mhz + */ + if (host->sclk <= 52000000) { + writel(host->def_tune_para.iocon, &host->base->msdc_iocon); + writel(host->def_tune_para.pad_tune, + &host->base->pad_tune); + } else { + writel(host->saved_tune_para.iocon, &host->base->msdc_iocon); + writel(host->saved_tune_para.pad_tune, + &host->base->pad_tune); + } + + dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing); +} + +static int msdc_ops_set_ios(struct udevice *dev) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc *mmc = &plat->mmc; + uint clock = mmc->clock; + + msdc_set_buswidth(host, mmc->bus_width); + + if (mmc->clk_disable) + clock = 0; + else if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; + + if (host->mclk != clock || host->timing != mmc->selected_mode) + msdc_set_mclk(host, mmc->selected_mode, clock); + + return 0; +} + +static int msdc_ops_get_cd(struct udevice *dev) +{ + struct msdc_host *host = dev_get_priv(dev); + u32 val; + + if (host->builtin_cd) { + val = readl(&host->base->msdc_ps); + return !(val & MSDC_PS_CDSTS); + } + +#ifdef CONFIG_DM_GPIO + if (!host->gpio_cd.dev) + return 1; + + return dm_gpio_get_value(&host->gpio_cd); +#else + return 1; +#endif +} + +static int msdc_ops_get_wp(struct udevice *dev) +{ + struct msdc_host *host = dev_get_priv(dev); + +#ifdef CONFIG_DM_GPIO + if (!host->gpio_wp.dev) + return 0; + + return !dm_gpio_get_value(&host->gpio_wp); +#else + return 0; +#endif +} + +#ifdef MMC_SUPPORTS_TUNING +static u32 test_delay_bit(u32 delay, u32 bit) +{ + bit %= PAD_DELAY_MAX; + return delay & (1 << bit); +} + +static int get_delay_len(u32 delay, u32 start_bit) +{ + int i; + + for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { + if (test_delay_bit(delay, start_bit + i) == 0) + return i; + } + + return PAD_DELAY_MAX - start_bit; +} + +static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) +{ + int start = 0, len = 0; + int start_final = 0, len_final = 0; + u8 final_phase = 0xff; + struct msdc_delay_phase delay_phase = { 0, }; + + if (delay == 0) { + dev_err(dev, "phase error: [map:%x]\n", delay); + delay_phase.final_phase = final_phase; + return delay_phase; + } + + while (start < PAD_DELAY_MAX) { + len = get_delay_len(delay, start); + if (len_final < len) { + start_final = start; + len_final = len; + } + + start += len ? len : 1; + if (len >= 12 && start_final < 4) + break; + } + + /* The rule is to find the smallest delay cell */ + if (start_final == 0) + final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; + else + final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; + + dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", + delay, len_final, final_phase); + + delay_phase.maxlen = len_final; + delay_phase.start = start_final; + delay_phase.final_phase = final_phase; + return delay_phase; +} + +static int msdc_tune_response(struct udevice *dev, u32 opcode) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc *mmc = &plat->mmc; + u32 rise_delay = 0, fall_delay = 0; + struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; + struct msdc_delay_phase internal_delay_phase; + u8 final_delay, final_maxlen; + u32 internal_delay = 0; + void __iomem *tune_reg = &host->base->pad_tune; + int cmd_err; + int i, j; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + if (mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == UHS_SDR104) + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, + host->hs200_cmd_int_delay << + MSDC_PAD_TUNE_CMDRRDLY_S); + + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + + for (i = 0; i < PAD_DELAY_MAX; i++) { + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + i << MSDC_PAD_TUNE_CMDRDLY_S); + + for (j = 0; j < 3; j++) { + mmc_send_tuning(mmc, opcode, &cmd_err); + if (!cmd_err) { + rise_delay |= (1 << i); + } else { + rise_delay &= ~(1 << i); + break; + } + } + } + + final_rise_delay = get_best_delay(host, rise_delay); + /* if rising edge has enough margin, do not scan falling edge */ + if (final_rise_delay.maxlen >= 12 || + (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) + goto skip_fall; + + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + for (i = 0; i < PAD_DELAY_MAX; i++) { + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + i << MSDC_PAD_TUNE_CMDRDLY_S); + + for (j = 0; j < 3; j++) { + mmc_send_tuning(mmc, opcode, &cmd_err); + if (!cmd_err) { + fall_delay |= (1 << i); + } else { + fall_delay &= ~(1 << i); + break; + } + } + } + + final_fall_delay = get_best_delay(host, fall_delay); + +skip_fall: + final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); + if (final_maxlen == final_rise_delay.maxlen) { + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + final_rise_delay.final_phase << + MSDC_PAD_TUNE_CMDRDLY_S); + final_delay = final_rise_delay.final_phase; + } else { + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + final_fall_delay.final_phase << + MSDC_PAD_TUNE_CMDRDLY_S); + final_delay = final_fall_delay.final_phase; + } + + if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) + goto skip_internal; + + for (i = 0; i < PAD_DELAY_MAX; i++) { + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, + i << MSDC_PAD_TUNE_CMDRRDLY_S); + + mmc_send_tuning(mmc, opcode, &cmd_err); + if (!cmd_err) + internal_delay |= (1 << i); + } + + dev_err(dev, "Final internal delay: 0x%x\n", internal_delay); + + internal_delay_phase = get_best_delay(host, internal_delay); + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, + internal_delay_phase.final_phase << + MSDC_PAD_TUNE_CMDRRDLY_S); + +skip_internal: + dev_err(dev, "Final cmd pad delay: %x\n", final_delay); + return final_delay == 0xff ? -EIO : 0; +} + +static int msdc_tune_data(struct udevice *dev, u32 opcode) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc *mmc = &plat->mmc; + u32 rise_delay = 0, fall_delay = 0; + struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; + u8 final_delay, final_maxlen; + void __iomem *tune_reg = &host->base->pad_tune; + int cmd_err; + int i, ret; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); + + for (i = 0; i < PAD_DELAY_MAX; i++) { + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + i << MSDC_PAD_TUNE_DATRRDLY_S); + + ret = mmc_send_tuning(mmc, opcode, &cmd_err); + if (!ret) { + rise_delay |= (1 << i); + } else if (cmd_err) { + /* in this case, retune response is needed */ + ret = msdc_tune_response(dev, opcode); + if (ret) + break; + } + } + + final_rise_delay = get_best_delay(host, rise_delay); + if (final_rise_delay.maxlen >= 12 || + (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) + goto skip_fall; + + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); + + for (i = 0; i < PAD_DELAY_MAX; i++) { + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + i << MSDC_PAD_TUNE_DATRRDLY_S); + + ret = mmc_send_tuning(mmc, opcode, &cmd_err); + if (!ret) { + fall_delay |= (1 << i); + } else if (cmd_err) { + /* in this case, retune response is needed */ + ret = msdc_tune_response(dev, opcode); + if (ret) + break; + } + } + + final_fall_delay = get_best_delay(host, fall_delay); + +skip_fall: + final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); + if (final_maxlen == final_rise_delay.maxlen) { + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + final_rise_delay.final_phase << + MSDC_PAD_TUNE_DATRRDLY_S); + final_delay = final_rise_delay.final_phase; + } else { + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + final_fall_delay.final_phase << + MSDC_PAD_TUNE_DATRRDLY_S); + final_delay = final_fall_delay.final_phase; + } + + if (mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == UHS_SDR104) + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M, + host->hs200_write_int_delay << + MSDC_PAD_TUNE_DATWRDLY_S); + + dev_err(dev, "Final data pad delay: %x\n", final_delay); + + return final_delay == 0xff ? -EIO : 0; +} + +static int msdc_execute_tuning(struct udevice *dev, uint opcode) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc *mmc = &plat->mmc; + int ret; + + if (mmc->selected_mode == MMC_HS_400) { + writel(host->hs400_ds_delay, &host->base->pad_ds_tune); + /* for hs400 mode it must be set to 0 */ + clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS); + host->hs400_mode = true; + } + + ret = msdc_tune_response(dev, opcode); + if (ret == -EIO) { + dev_err(dev, "Tune response fail!\n"); + return ret; + } + + if (!host->hs400_mode) { + ret = msdc_tune_data(dev, opcode); + if (ret == -EIO) + dev_err(dev, "Tune data fail!\n"); + } + + host->saved_tune_para.iocon = readl(&host->base->msdc_iocon); + host->saved_tune_para.pad_tune = readl(&host->base->pad_tune); + + return ret; +} +#endif + +static void msdc_init_hw(struct msdc_host *host) +{ + u32 val; + void __iomem *tune_reg = &host->base->pad_tune; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + /* Configure to MMC/SD mode, clock free running */ + setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE); + + /* Use PIO mode */ + setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); + + /* Reset */ + msdc_reset_hw(host); + + /* Enable/disable hw card detection according to fdt option */ + if (host->builtin_cd) + clrsetbits_le32(&host->base->msdc_ps, + MSDC_PS_CDDBCE_M, + (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) | + MSDC_PS_CDEN); + else + clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN); + + /* Clear all interrupts */ + val = readl(&host->base->msdc_int); + writel(val, &host->base->msdc_int); + + /* Enable data & cmd interrupts */ + writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); + + writel(0, tune_reg); + writel(0, &host->base->msdc_iocon); + + if (host->r_smpl) + setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + else + clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); + + writel(0x403c0046, &host->base->patch_bit0); + writel(0xffff4089, &host->base->patch_bit1); + + if (host->dev_comp->stop_clk_fix) + clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, + 3 << MSDC_PB1_STOP_DLY_S); + + if (host->dev_comp->busy_check) + clrbits_le32(&host->base->patch_bit1, (1 << 7)); + + setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL); + + if (host->dev_comp->async_fifo) { + clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M, + 3 << MSDC_PB2_RESPWAIT_S); + + if (host->dev_comp->enhance_rx) { + setbits_le32(&host->base->sdc_adv_cfg0, + SDC_RX_ENHANCE_EN); + } else { + clrsetbits_le32(&host->base->patch_bit2, + MSDC_PB2_RESPSTSENSEL_M, + 2 << MSDC_PB2_RESPSTSENSEL_S); + clrsetbits_le32(&host->base->patch_bit2, + MSDC_PB2_CRCSTSENSEL_M, + 2 << MSDC_PB2_CRCSTSENSEL_S); + } + + /* use async fifo to avoid tune internal delay */ + clrbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGRESP); + clrbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); + } + + if (host->dev_comp->data_tune) { + setbits_le32(tune_reg, + MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); + clrsetbits_le32(&host->base->patch_bit0, + MSDC_INT_DAT_LATCH_CK_SEL_M, + host->latch_ck << + MSDC_INT_DAT_LATCH_CK_SEL_S); + } else { + /* choose clock tune */ + setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); + } + + /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */ + setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO); + + /* disable detecting SDIO device interrupt function */ + clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE); + + /* Configure to default data timeout */ + clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, + 3 << SDC_CFG_DTOC_S); + + if (host->dev_comp->stop_clk_fix) { + clrbits_le32(&host->base->sdc_fifo_cfg, + SDC_FIFO_CFG_WRVALIDSEL); + clrbits_le32(&host->base->sdc_fifo_cfg, + SDC_FIFO_CFG_RDVALIDSEL); + } + + host->def_tune_para.iocon = readl(&host->base->msdc_iocon); + host->def_tune_para.pad_tune = readl(&host->base->pad_tune); +} + +static void msdc_ungate_clock(struct msdc_host *host) +{ + clk_enable(&host->src_clk); + clk_enable(&host->h_clk); +} + +static int msdc_drv_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + + host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev); + + host->src_clk_freq = clk_get_rate(&host->src_clk); + + if (host->dev_comp->clk_div_bits == 8) + cfg->f_min = host->src_clk_freq / (4 * 255); + else + cfg->f_min = host->src_clk_freq / (4 * 4095); + cfg->f_max = host->src_clk_freq / 2; + + cfg->b_max = 1024; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + + host->mmc = &plat->mmc; + host->timeout_ns = 100000000; + host->timeout_clks = 3 * 1048576; + +#ifdef CONFIG_PINCTRL + pinctrl_select_state(dev, "default"); +#endif + + msdc_ungate_clock(host); + msdc_init_hw(host); + + upriv->mmc = &plat->mmc; + + return 0; +} + +static int msdc_ofdata_to_platdata(struct udevice *dev) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + struct msdc_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; + int ret; + + host->base = (void *)dev_read_addr(dev); + if (!host->base) + return -EINVAL; + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret; + + ret = clk_get_by_name(dev, "source", &host->src_clk); + if (ret < 0) + return ret; + + ret = clk_get_by_name(dev, "hclk", &host->h_clk); + if (ret < 0) + return ret; + +#ifdef CONFIG_DM_GPIO + gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); + gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); +#endif + + host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0); + host->hs200_cmd_int_delay = + dev_read_u32_default(dev, "cmd_int_delay", 0); + host->hs200_write_int_delay = + dev_read_u32_default(dev, "write_int_delay", 0); + host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); + host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); + host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); + + return 0; +} + +static int msdc_drv_bind(struct udevice *dev) +{ + struct msdc_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct dm_mmc_ops msdc_ops = { + .send_cmd = msdc_ops_send_cmd, + .set_ios = msdc_ops_set_ios, + .get_cd = msdc_ops_get_cd, + .get_wp = msdc_ops_get_wp, +#ifdef MMC_SUPPORTS_TUNING + .execute_tuning = msdc_execute_tuning, +#endif +}; + +static const struct msdc_compatible mt7623_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = false, + .stop_clk_fix = false, + .enhance_rx = false +}; + +static const struct udevice_id msdc_ids[] = { + { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, + {} +}; + +U_BOOT_DRIVER(mtk_sd_drv) = { + .name = "mtk_sd", + .id = UCLASS_MMC, + .of_match = msdc_ids, + .ofdata_to_platdata = msdc_ofdata_to_platdata, + .bind = msdc_drv_bind, + .probe = msdc_drv_probe, + .ops = &msdc_ops, + .platdata_auto_alloc_size = sizeof(struct msdc_plat), + .priv_auto_alloc_size = sizeof(struct msdc_host), +}; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index ec853d063f..5cb97eb02a 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1953,6 +1953,8 @@ U_BOOT_DRIVER(omap_hsmmc) = { .ops = &omap_hsmmc_ops, .probe = omap_hsmmc_probe, .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index e7f96f8bf2..733b6d62f5 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -17,7 +17,9 @@ #include "tmio-common.h" -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) /* SCC registers */ #define RENESAS_SDHI_SCC_DTCNTL 0x800 @@ -107,6 +109,56 @@ static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv) tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); } +static int renesas_sdhi_hs400(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + bool hs400 = (mmc->selected_mode == MMC_HS_400); + int ret, taps = hs400 ? priv->nrtaps : 8; + u32 reg; + + if (taps == 4) /* HS400 on 4tap SoC needs different clock */ + ret = clk_set_rate(&priv->clk, 400000000); + else + ret = clk_set_rate(&priv->clk, 200000000); + if (ret < 0) + return ret; + + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); + if (hs400) { + reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN | + RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL; + } else { + reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN | + RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL); + } + + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2); + + tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) | + RENESAS_SDHI_SCC_DTCNTL_TAPEN, + RENESAS_SDHI_SCC_DTCNTL); + + if (taps == 4) { + tmio_sd_writel(priv, priv->tap_set >> 1, + RENESAS_SDHI_SCC_TAPSET); + } else { + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + } + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); + reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); + + return 0; +} + static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv, unsigned long tap) { @@ -125,7 +177,6 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, unsigned int smpcmp) { unsigned long tap_cnt; /* counter of tuning success */ - unsigned long tap_set; /* tap position */ unsigned long tap_start;/* start position of tuning success */ unsigned long tap_end; /* end position of tuning success */ unsigned long ntap; /* temporary counter of tuning success */ @@ -209,12 +260,12 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; else return -EIO; /* Set SCC */ - tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); /* Enable auto re-tuning */ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); @@ -240,6 +291,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* clock tuning is not needed for upto 52MHz */ if (!((mmc->selected_mode == MMC_HS_200) || + (mmc->selected_mode == MMC_HS_400) || (mmc->selected_mode == UHS_SDR104) || (mmc->selected_mode == UHS_SDR50))) return 0; @@ -287,19 +339,42 @@ out: return ret; } +#else +static int renesas_sdhi_hs400(struct udevice *dev) +{ + return 0; +} #endif static int renesas_sdhi_set_ios(struct udevice *dev) { - int ret = tmio_sd_set_ios(dev); + struct tmio_sd_priv *priv = dev_get_priv(dev); + u32 tmp; + int ret; + + /* Stop the clock before changing its rate to avoid a glitch signal */ + tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + + ret = renesas_sdhi_hs400(dev); + if (ret) + return ret; + + ret = tmio_sd_set_ios(dev); mdelay(10); -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) - struct tmio_sd_priv *priv = dev_get_priv(dev); - - if (priv->caps & TMIO_SD_CAP_RCAR_UHS) +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + struct mmc *mmc = mmc_get_mmc_dev(dev); + if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && + (mmc->selected_mode != UHS_SDR104) && + (mmc->selected_mode != MMC_HS_200) && + (mmc->selected_mode != MMC_HS_400)) { renesas_sdhi_reset_tuning(priv); + } #endif return ret; @@ -331,7 +406,9 @@ static const struct dm_mmc_ops renesas_sdhi_ops = { .send_cmd = tmio_sd_send_cmd, .set_ios = renesas_sdhi_set_ios, .get_cd = tmio_sd_get_cd, -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) .execute_tuning = renesas_sdhi_execute_tuning, #endif #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) @@ -358,15 +435,45 @@ static const struct udevice_id renesas_sdhi_match[] = { { /* sentinel */ } }; +static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) +{ + return clk_get_rate(&priv->clk); +} + +static void renesas_sdhi_filter_caps(struct udevice *dev) +{ + struct tmio_sd_plat *plat = dev_get_platdata(dev); + struct tmio_sd_priv *priv = dev_get_priv(dev); + + if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) + return; + + /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 1)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() <= 1))) + plat->cfg.host_caps &= ~MMC_MODE_HS400; + + /* H3 ES2.0 uses 4 tuning taps */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() == 2)) + priv->nrtaps = 4; + else + priv->nrtaps = 8; +} + static int renesas_sdhi_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; - struct clk clk; DECLARE_GLOBAL_DATA_PTR; int ret; + priv->clk_get_rate = renesas_sdhi_clk_get_rate; + if (quirks == RENESAS_GEN2_QUIRKS) { ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", 0, ®_res); @@ -380,29 +487,33 @@ static int renesas_sdhi_probe(struct udevice *dev) quirks |= TMIO_SD_CAP_16BIT; } - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, 200000000); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; } ret = tmio_sd_probe(dev, quirks); -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + + renesas_sdhi_filter_caps(dev); + +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS)) renesas_sdhi_reset_tuning(priv); #endif diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 39f15eb423..9bf040cb40 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -98,18 +98,20 @@ static int mmc_resource_init(int sdc_no) static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) { unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; - bool new_mode = false; + bool new_mode = true; + bool calibrate = false; u32 val = 0; - if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) - new_mode = true; + if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE)) + new_mode = false; - /* - * The MMC clock has an extra /2 post-divider when operating in the new - * mode. - */ - if (new_mode) - hz = hz * 2; + /* A83T support new mode only on eMMC */ + if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2) + new_mode = false; + +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6) + calibrate = true; +#endif if (hz <= 24000000) { pll = CCM_MMC_CTRL_OSCM24; @@ -171,10 +173,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE +#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH val = CCM_MMC_CTRL_MODE_SEL_NEW; +#endif setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif - } else { + } else if (!calibrate) { + /* + * Use hardcoded delay values if controller doesn't support + * calibration + */ val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly); } @@ -228,6 +236,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr); +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6) + /* A64 supports calibration of delays on MMC controller and we + * have to set delay of zero before starting calibration. + * Allwinner BSP driver sets a delay only in the case of + * using HS400 which is not supported by mainline U-Boot or + * Linux at the moment + */ + writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl); +#endif + /* Re-enable Clock */ rval |= SUNXI_MMC_CLK_ENABLE; writel(rval, &priv->reg->clkcr); diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0eca83a0f4..201492001f 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -555,55 +555,76 @@ static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); } -static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, - struct mmc *mmc) +static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv) +{ + return priv->clk_get_rate(priv); +} + +static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc) { unsigned int divisor; - u32 val, tmp; + u32 tmp, val = 0; + ulong mclk; - if (!mmc->clock) - return; + if (mmc->clock) { + mclk = tmio_sd_clk_get_rate(priv); - divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); + divisor = DIV_ROUND_UP(mclk, mmc->clock); - if (divisor <= 1) - val = (priv->caps & TMIO_SD_CAP_RCAR) ? - TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; - else if (divisor <= 2) - val = TMIO_SD_CLKCTL_DIV2; - else if (divisor <= 4) - val = TMIO_SD_CLKCTL_DIV4; - else if (divisor <= 8) - val = TMIO_SD_CLKCTL_DIV8; - else if (divisor <= 16) - val = TMIO_SD_CLKCTL_DIV16; - else if (divisor <= 32) - val = TMIO_SD_CLKCTL_DIV32; - else if (divisor <= 64) - val = TMIO_SD_CLKCTL_DIV64; - else if (divisor <= 128) - val = TMIO_SD_CLKCTL_DIV128; - else if (divisor <= 256) - val = TMIO_SD_CLKCTL_DIV256; - else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) - val = TMIO_SD_CLKCTL_DIV512; - else - val = TMIO_SD_CLKCTL_DIV1024; + /* Do not set divider to 0xff in DDR mode */ + if (mmc->ddr_mode && (divisor == 1)) + divisor = 2; + + if (divisor <= 1) + val = (priv->caps & TMIO_SD_CAP_RCAR) ? + TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; + else if (divisor <= 2) + val = TMIO_SD_CLKCTL_DIV2; + else if (divisor <= 4) + val = TMIO_SD_CLKCTL_DIV4; + else if (divisor <= 8) + val = TMIO_SD_CLKCTL_DIV8; + else if (divisor <= 16) + val = TMIO_SD_CLKCTL_DIV16; + else if (divisor <= 32) + val = TMIO_SD_CLKCTL_DIV32; + else if (divisor <= 64) + val = TMIO_SD_CLKCTL_DIV64; + else if (divisor <= 128) + val = TMIO_SD_CLKCTL_DIV128; + else if (divisor <= 256) + val = TMIO_SD_CLKCTL_DIV256; + else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) + val = TMIO_SD_CLKCTL_DIV512; + else + val = TMIO_SD_CLKCTL_DIV1024; + } tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); - if (tmp & TMIO_SD_CLKCTL_SCLKEN && - (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) - return; + if (mmc->clock && + !((tmp & TMIO_SD_CLKCTL_SCLKEN) && + ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) { + /* + * Stop the clock before changing its rate + * to avoid a glitch signal + */ + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); - /* stop the clock before changing its rate to avoid a glitch signal */ - tmp &= ~TMIO_SD_CLKCTL_SCLKEN; - tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + /* Change the clock rate. */ + tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; + tmp |= val; + } - tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; - tmp |= val | TMIO_SD_CLKCTL_OFFEN; - tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + /* Enable or Disable the clock */ + if (mmc->clk_disable) { + tmp |= TMIO_SD_CLKCTL_OFFEN; + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + } else { + tmp &= ~TMIO_SD_CLKCTL_OFFEN; + tmp |= TMIO_SD_CLKCTL_SCLKEN; + } - tmp |= TMIO_SD_CLKCTL_SCLKEN; tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); udelay(1000); @@ -708,6 +729,7 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) struct tmio_sd_priv *priv = dev_get_priv(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); fdt_addr_t base; + ulong mclk; int ret; base = devfdt_get_addr(dev); @@ -750,10 +772,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) tmio_sd_host_init(priv); + mclk = tmio_sd_clk_get_rate(priv); + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; - plat->cfg.f_min = priv->mclk / + plat->cfg.f_min = mclk / (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); - plat->cfg.f_max = priv->mclk; + plat->cfg.f_max = mclk; plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ upriv->mmc = &plat->mmc; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 792b1ba5ae..192026ce3e 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -117,7 +117,6 @@ struct tmio_sd_plat { struct tmio_sd_priv { void __iomem *regbase; - unsigned long mclk; unsigned int version; u32 caps; #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ @@ -133,6 +132,14 @@ struct tmio_sd_priv { #ifdef CONFIG_DM_REGULATOR struct udevice *vqmmc_dev; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +#if CONFIG_IS_ENABLED(RENESAS_SDHI) + u8 tap_set; + u8 nrtaps; +#endif + ulong (*clk_get_rate)(struct tmio_sd_priv *); }; int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 813c28494c..6539880ab5 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -31,35 +31,45 @@ static const struct udevice_id uniphier_sd_match[] = { { /* sentinel */ } }; +static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv) +{ +#if CONFIG_IS_ENABLED(CLK) + return clk_get_rate(&priv->clk); +#elif CONFIG_SPL_BUILD + return 100000000; +#else + return 0; +#endif +} + static int uniphier_sd_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); + + priv->clk_get_rate = uniphier_sd_clk_get_rate; + #ifndef CONFIG_SPL_BUILD - struct clk clk; int ret; - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, ULONG_MAX); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; } -#else - priv->mclk = 100000000; #endif return tmio_sd_probe(dev, 0); diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 5ca560c968..d638f700d0 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -13,6 +13,29 @@ #define MTD_NAME_MAX_LEN 20 +void board_mtdparts_default(const char **mtdids, const char **mtdparts); + +static const char *get_mtdids(void) +{ + __maybe_unused const char *mtdparts = NULL; + const char *mtdids = env_get("mtdids"); + + if (mtdids) + return mtdids; + +#if defined(CONFIG_SYS_MTDPARTS_RUNTIME) + board_mtdparts_default(&mtdids, &mtdparts); +#elif defined(MTDIDS_DEFAULT) + mtdids = MTDIDS_DEFAULT; +#elif defined(CONFIG_MTDIDS_DEFAULT) + mtdids = CONFIG_MTDIDS_DEFAULT; +#endif + + if (mtdids) + env_set("mtdids", mtdids); + + return mtdids; +} /** * mtd_search_alternate_name - Search an alternate name for @mtdname thanks to @@ -34,7 +57,7 @@ int mtd_search_alternate_name(const char *mtdname, char *altname, const char *mtdids, *equal, *comma, *dev_id, *mtd_id; int dev_id_len, mtd_id_len; - mtdids = env_get("mtdids"); + mtdids = get_mtdids(); if (!mtdids) return -EINVAL; @@ -92,30 +115,6 @@ static void mtd_probe_uclass_mtd_devs(void) { } #endif #if defined(CONFIG_MTD_PARTITIONS) -extern void board_mtdparts_default(const char **mtdids, - const char **mtdparts); - -static const char *get_mtdids(void) -{ - __maybe_unused const char *mtdparts = NULL; - const char *mtdids = env_get("mtdids"); - - if (mtdids) - return mtdids; - -#if defined(CONFIG_SYS_MTDPARTS_RUNTIME) - board_mtdparts_default(&mtdids, &mtdparts); -#elif defined(MTDIDS_DEFAULT) - mtdids = MTDIDS_DEFAULT; -#elif defined(CONFIG_MTDIDS_DEFAULT) - mtdids = CONFIG_MTDIDS_DEFAULT; -#endif - - if (mtdids) - env_set("mtdids", mtdids); - - return mtdids; -} #define MTDPARTS_MAXLEN 512 @@ -150,20 +149,74 @@ static const char *get_mtdparts(void) return mtdparts; } +static int mtd_del_parts(struct mtd_info *mtd, bool quiet) +{ + int ret; + + if (!mtd_has_partitions(mtd)) + return 0; + + /* do not delete partitions if they are in use. */ + if (mtd_partitions_used(mtd)) { + if (!quiet) + printf("\"%s\" partitions still in use, can't delete them\n", + mtd->name); + return -EACCES; + } + + ret = del_mtd_partitions(mtd); + if (ret) + return ret; + + return 1; +} + +static bool mtd_del_all_parts_failed; + +static void mtd_del_all_parts(void) +{ + struct mtd_info *mtd; + int ret = 0; + + mtd_del_all_parts_failed = false; + + /* + * It is not safe to remove entries from the mtd_for_each_device loop + * as it uses idr indexes and the partitions removal is done in bulk + * (all partitions of one device at the same time), so break and + * iterate from start each time a new partition is found and deleted. + */ + do { + mtd_for_each_device(mtd) { + ret = mtd_del_parts(mtd, false); + if (ret > 0) + break; + else if (ret < 0) + mtd_del_all_parts_failed = true; + } + } while (ret > 0); +} + int mtd_probe_devices(void) { static char *old_mtdparts; static char *old_mtdids; const char *mtdparts = get_mtdparts(); const char *mtdids = get_mtdids(); - bool remaining_partitions = true; + const char *mtdparts_next = mtdparts; struct mtd_info *mtd; mtd_probe_uclass_mtd_devs(); - /* Check if mtdparts/mtdids changed since last call, otherwise: exit */ + /* + * Check if mtdparts/mtdids changed, if the MTD dev list was updated + * or if our previous attempt to delete existing partititions failed. + * In any of these cases we want to update the partitions, otherwise, + * everything is up-to-date and we can return 0 directly. + */ if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) || (mtdparts && old_mtdparts && mtdids && old_mtdids && + !mtd_dev_list_updated() && !mtd_del_all_parts_failed && !strcmp(mtdparts, old_mtdparts) && !strcmp(mtdids, old_mtdids))) return 0; @@ -174,55 +227,55 @@ int mtd_probe_devices(void) old_mtdparts = strdup(mtdparts); old_mtdids = strdup(mtdids); - /* If at least one partition is still in use, do not delete anything */ - mtd_for_each_device(mtd) { - if (mtd->usecount) { - printf("Partition \"%s\" already in use, aborting\n", - mtd->name); - return -EACCES; - } - } + /* + * Remove all old parts. Note that partition removal can fail in case + * one of the partition is still being used by an MTD user, so this + * does not guarantee that all old partitions are gone. + */ + mtd_del_all_parts(); /* - * Everything looks clear, remove all partitions. It is not safe to - * remove entries from the mtd_for_each_device loop as it uses idr - * indexes and the partitions removal is done in bulk (all partitions of - * one device at the same time), so break and iterate from start each - * time a new partition is found and deleted. + * Call mtd_dev_list_updated() to clear updates generated by our own + * parts removal loop. */ - while (remaining_partitions) { - remaining_partitions = false; - mtd_for_each_device(mtd) { - if (!mtd_is_partition(mtd) && mtd_has_partitions(mtd)) { - del_mtd_partitions(mtd); - remaining_partitions = true; - break; - } - } - } + mtd_dev_list_updated(); /* If either mtdparts or mtdids is empty, then exit */ if (!mtdparts || !mtdids) return 0; /* Start the parsing by ignoring the extra 'mtdparts=' prefix, if any */ - if (strstr(mtdparts, "mtdparts=")) + if (!strncmp(mtdparts, "mtdparts=", sizeof("mtdparts=") - 1)) mtdparts += 9; /* For each MTD device in mtdparts */ - while (mtdparts[0] != '\0') { + for (; mtdparts[0] != '\0'; mtdparts = mtdparts_next) { char mtd_name[MTD_NAME_MAX_LEN], *colon; struct mtd_partition *parts; - int mtd_name_len, nparts; - int ret; + unsigned int mtd_name_len; + int nparts, ret; + + mtdparts_next = strchr(mtdparts, ';'); + if (!mtdparts_next) + mtdparts_next = mtdparts + strlen(mtdparts); + else + mtdparts_next++; colon = strchr(mtdparts, ':'); + if (colon > mtdparts_next) + colon = NULL; + if (!colon) { printf("Wrong mtdparts: %s\n", mtdparts); return -EINVAL; } - mtd_name_len = colon - mtdparts; + mtd_name_len = (unsigned int)(colon - mtdparts); + if (mtd_name_len + 1 > sizeof(mtd_name)) { + printf("MTD name too long: %s\n", mtdparts); + return -EINVAL; + } + strncpy(mtd_name, mtdparts, mtd_name_len); mtd_name[mtd_name_len] = '\0'; /* Move the pointer forward (including the ':') */ @@ -249,14 +302,22 @@ int mtd_probe_devices(void) if (ret || IS_ERR_OR_NULL(mtd)) { printf("Could not find a valid device for %s\n", mtd_name); - mtdparts = strchr(mtdparts, ';'); - if (mtdparts) - mtdparts++; - + mtdparts = mtdparts_next; continue; } } + /* + * Call mtd_del_parts() again, even if it's already been called + * in mtd_del_all_parts(). We need to know if old partitions are + * still around (because they are still being used by someone), + * and if they are, we shouldn't create new partitions, so just + * skip this MTD device and try the next one. + */ + ret = mtd_del_parts(mtd, true); + if (ret < 0) + continue; + /* * Parse the MTD device partitions. It will update the mtdparts * pointer, create an array of parts (that must be freed), and @@ -281,6 +342,12 @@ int mtd_probe_devices(void) put_mtd_device(mtd); } + /* + * Call mtd_dev_list_updated() to clear updates generated by our own + * parts registration loop. + */ + mtd_dev_list_updated(); + return 0; } #else diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index fb6c779abb..cb7ca38d07 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -87,14 +87,17 @@ struct idr_layer { struct idr { struct idr_layer id[MAX_IDR_ID]; + bool updated; }; #define DEFINE_IDR(name) struct idr name; void idr_remove(struct idr *idp, int id) { - if (idp->id[id].used) + if (idp->id[id].used) { idp->id[id].used = 0; + idp->updated = true; + } return; } @@ -134,6 +137,7 @@ int idr_alloc(struct idr *idp, void *ptr, int start, int end, gfp_t gfp_mask) if (idl->used == 0) { idl->used = 1; idl->ptr = ptr; + idp->updated = true; return i; } i++; @@ -155,6 +159,16 @@ struct mtd_info *__mtd_next_device(int i) } EXPORT_SYMBOL_GPL(__mtd_next_device); +bool mtd_dev_list_updated(void) +{ + if (mtd_idr.updated) { + mtd_idr.updated = false; + return true; + } + + return false; +} + #ifndef __UBOOT__ static LIST_HEAD(mtd_notifiers); @@ -514,6 +528,13 @@ int del_mtd_device(struct mtd_info *mtd) struct mtd_notifier *not; #endif + ret = del_mtd_partitions(mtd); + if (ret) { + debug("Failed to delete MTD partitions attached to %s (err %d)\n", + mtd->name, ret); + return ret; + } + mutex_lock(&mtd_table_mutex); if (idr_find(&mtd_idr, mtd->index) != mtd) { diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 4d2ac8107f..fd8d8e5ea7 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -63,6 +63,18 @@ char *kstrdup(const char *s, gfp_t gfp) #define MTD_SIZE_REMAINING (~0LLU) #define MTD_OFFSET_NOT_SPECIFIED (~0LLU) +bool mtd_partitions_used(struct mtd_info *master) +{ + struct mtd_info *slave; + + list_for_each_entry(slave, &master->partitions, node) { + if (slave->usecount) + return true; + } + + return false; +} + /** * mtd_parse_partition - Parse @mtdparts partition definition, fill @partition * with it and update the @mtdparts string pointer. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 86e8b5e55d..0350760c4b 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -88,6 +88,15 @@ config NAND_VF610_NFC The driver supports a maximum 2k page size. The driver currently does not support hardware ECC. +if NAND_VF610_NFC + +config NAND_VF610_NFC_DT + bool "Support Vybrid's vf610 NAND controller as a DT device" + depends on OF_CONTROL && MTD + help + Enable the driver for Vybrid's vf610 NAND flash on platforms + using device tree. + choice prompt "Hardware ECC strength" depends on NAND_VF610_NFC @@ -103,6 +112,8 @@ config SYS_NAND_VF610_NFC_60_ECC_BYTES endchoice +endif + config NAND_PXA3XX bool "Support for NAND on PXA3xx and Armada 370/XP/38x" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index d1cac063f4..e0eb1339ec 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -69,14 +69,6 @@ static int dma_mapping_error(void *dev, dma_addr_t addr) #define DENALI_INVALID_BANK -1 #define DENALI_NR_BANKS 4 -/* - * The bus interface clock, clk_x, is phase aligned with the core clock. The - * clk_x is an integral multiple N of the core clk. The value N is configured - * at IP delivery time, and its available value is 4, 5, or 6. We need to align - * to the largest value to make it work with any possible configuration. - */ -#define DENALI_CLK_X_MULT 6 - static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) { return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); @@ -595,6 +587,12 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, } iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); + /* + * The ->setup_dma() hook kicks DMA by using the data/command + * interface, which belongs to a different AXI port from the + * register interface. Read back the register to avoid a race. + */ + ioread32(denali->reg + DMA_ENABLE); denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); @@ -946,7 +944,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, { struct denali_nand_info *denali = mtd_to_denali(mtd); const struct nand_sdr_timings *timings; - unsigned long t_clk; + unsigned long t_x, mult_x; int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; int addr_2_data_mask; @@ -957,15 +955,24 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, return PTR_ERR(timings); /* clk_x period in picoseconds */ - t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); - if (!t_clk) + t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); + if (!t_x) + return -EINVAL; + + /* + * The bus interface clock, clk_x, is phase aligned with the core clock. + * The clk_x is an integral multiple N of the core clk. The value N is + * configured at IP delivery time, and its available value is 4, 5, 6. + */ + mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); + if (mult_x < 4 || mult_x > 6) return -EINVAL; if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; /* tREA -> ACC_CLKS */ - acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); + acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); tmp = ioread32(denali->reg + ACC_CLKS); @@ -974,7 +981,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ - re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); + re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); tmp = ioread32(denali->reg + RE_2_WE); @@ -983,7 +990,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ - re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); + re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); tmp = ioread32(denali->reg + RE_2_RE); @@ -997,8 +1004,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, * With WE_2_RE properly set, the Denali controller automatically takes * care of the delay; the driver need not set NAND_WAIT_TCCS. */ - we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), - t_clk); + we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); @@ -1013,7 +1019,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, if (denali->revision < 0x0501) addr_2_data_mask >>= 1; - addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); + addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); @@ -1023,7 +1029,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, /* tREH, tWH -> RDWR_EN_HI_CNT */ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), - t_clk); + t_x); rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); @@ -1032,11 +1038,10 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ - rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), - t_clk); + rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), - t_clk); - rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); + t_x); + rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); @@ -1046,8 +1051,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ - cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, - (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, + cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, + (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 0); cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 9b797beffa..019deda094 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -292,6 +292,7 @@ struct udevice; struct denali_nand_info { struct nand_chip nand; + unsigned long clk_rate; /* core clock rate */ unsigned long clk_x_rate; /* bus interface clock rate */ int active_bank; /* currently selected bank */ struct udevice *dev; diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 65a7797f0f..d384b974df 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk; + struct clk clk, clk_x, clk_ecc; struct resource res; int ret; @@ -87,15 +87,49 @@ static int denali_dt_probe(struct udevice *dev) denali->host = devm_ioremap(dev, res.start, resource_size(&res)); - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_name(dev, "nand", &clk); + if (ret) + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; + ret = clk_get_by_name(dev, "nand_x", &clk_x); + if (ret) + clk_x.dev = NULL; + + ret = clk_get_by_name(dev, "ecc", &clk_ecc); + if (ret) + clk_ecc.dev = NULL; + ret = clk_enable(&clk); if (ret) return ret; - denali->clk_x_rate = clk_get_rate(&clk); + if (clk_x.dev) { + ret = clk_enable(&clk_x); + if (ret) + return ret; + } + + if (clk_ecc.dev) { + ret = clk_enable(&clk_ecc); + if (ret) + return ret; + } + + if (clk_x.dev) { + denali->clk_rate = clk_get_rate(&clk); + denali->clk_x_rate = clk_get_rate(&clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_rate = 50000000; + denali->clk_x_rate = 200000000; + } return denali_init(denali); } diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 5d4ffea608..79d1489dc7 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -82,6 +82,10 @@ struct lpc32xx_nand_mlc_registers { static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE; +#if !defined(CONFIG_SYS_MAX_NAND_CHIPS) +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#endif + #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) /** diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 99f6e15f4e..8615b112a2 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -2,13 +2,12 @@ /* * LPC32xx SLC NAND flash controller driver * - * (C) Copyright 2015 Vladimir Zapolskiy + * (C) Copyright 2015-2018 Vladimir Zapolskiy + * Copyright (c) 2015 Tyco Fire Protection Products. * * Hardware ECC support original source code * Copyright (C) 2008 by NXP Semiconductors * Author: Kevin Wells - * - * Copyright (c) 2015 Tyco Fire Protection Products. */ #include @@ -22,10 +21,6 @@ #include #include -#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD) -#warning "DMA support in SPL image is not tested" -#endif - struct lpc32xx_nand_slc_regs { u32 data; u32 addr; @@ -78,16 +73,14 @@ struct lpc32xx_nand_slc_regs { * Note: For large page devices, the default layouts are used. */ static struct nand_ecclayout lpc32xx_nand_oob_16 = { .eccbytes = 6, - .eccpos = {10, 11, 12, 13, 14, 15}, + .eccpos = { 10, 11, 12, 13, 14, 15, }, .oobfree = { - {.offset = 0, - . length = 4}, - {.offset = 6, - . length = 4} - } + { .offset = 0, .length = 4, }, + { .offset = 6, .length = 4, }, + } }; -#if defined(CONFIG_DMA_LPC32XX) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) /* @@ -165,7 +158,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } -#if defined(CONFIG_DMA_LPC32XX) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) /* * Prepares DMA descriptors for NAND RD/WR operations * If the size is < 256 Bytes then it is assumed to be @@ -324,7 +317,6 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, if (unlikely(ret < 0)) BUG(); - /* Wait for NAND to be ready */ while (!lpc32xx_nand_dev_ready(mtd)) ; @@ -404,46 +396,18 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, return ret2; } -#endif -#if defined(CONFIG_DMA_LPC32XX) static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { lpc32xx_nand_xfer(mtd, buf, len, 1); } -#else -static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - while (len-- > 0) - *buf++ = readl(&lpc32xx_nand_slc_regs->data); -} -#endif -static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) -{ - return readl(&lpc32xx_nand_slc_regs->data); -} - -#if defined(CONFIG_DMA_LPC32XX) static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { lpc32xx_nand_xfer(mtd, buf, len, 0); } -#else -static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - while (len-- > 0) - writel(*buf++, &lpc32xx_nand_slc_regs->data); -} -#endif -static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) -{ - writel(byte, &lpc32xx_nand_slc_regs->data); -} - -#if defined(CONFIG_DMA_LPC32XX) /* Reuse the logic from "nand_read_page_hwecc()" */ static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) @@ -511,8 +475,30 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, return 0; } +#else +static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + while (len-- > 0) + *buf++ = readl(&lpc32xx_nand_slc_regs->data); +} + +static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + while (len-- > 0) + writel(*buf++, &lpc32xx_nand_slc_regs->data); +} #endif +static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) +{ + return readl(&lpc32xx_nand_slc_regs->data); +} + +static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) +{ + writel(byte, &lpc32xx_nand_slc_regs->data); +} + /* * LPC32xx has only one SLC NAND controller, don't utilize * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function @@ -520,7 +506,7 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, */ int board_nand_init(struct nand_chip *lpc32xx_chip) { -#if defined(CONFIG_DMA_LPC32XX) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) int ret; /* Acquire a channel for our use */ @@ -543,7 +529,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->read_byte = lpc32xx_read_byte; lpc32xx_chip->write_byte = lpc32xx_write_byte; -#if defined(CONFIG_DMA_LPC32XX) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) /* Hardware ECC calculation is supported when DMA driver is selected */ lpc32xx_chip->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 4009d64123..3104f879f6 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -61,6 +61,10 @@ struct nand_flash_dev nand_flash_ids[] = { {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, + {"H27UBG8T2BTR-BC 32G 3.3V 8-bit", + { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} }, + SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, + NAND_ECC_INFO(40, SZ_1K), 0 }, {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 4c783f1e1e..4d2712df4c 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -195,6 +195,7 @@ struct pxa3xx_nand_info { int cs; int use_ecc; /* use HW ECC ? */ + int force_raw; /* prevent use_ecc to be set */ int ecc_bch; /* using BCH ECC? */ int use_spare; /* use spare ? */ int need_wait; @@ -326,14 +327,14 @@ static struct nand_ecclayout ecc_layout_2KB_bch4bit = { static struct nand_ecclayout ecc_layout_2KB_bch8bit = { .eccbytes = 64, .eccpos = { - 64, 65, 66, 67, 68, 69, 70, 71, - 72, 73, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89, 90, 91, 92, 93, 94, 95, - 96, 97, 98, 99, 100, 101, 102, 103, - 104, 105, 106, 107, 108, 109, 110, 111, - 112, 113, 114, 115, 116, 117, 118, 119, - 120, 121, 122, 123, 124, 125, 126, 127}, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95}, .oobfree = { {1, 4}, {6, 26} } }; @@ -579,7 +580,7 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) { - if (info->ecc_bch) { + if (info->ecc_bch && !info->force_raw) { u32 ts; /* @@ -612,12 +613,22 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) static void handle_data_pio(struct pxa3xx_nand_info *info) { + int data_len = info->step_chunk_size; + + /* + * In raw mode, include the spare area and the ECC bytes that are not + * consumed by the controller in the data section. Do not reorganize + * here, do it in the ->read_page_raw() handler instead. + */ + if (info->force_raw) + data_len += info->step_spare_size + info->ecc_size; + switch (info->state) { case STATE_PIO_WRITING: if (info->step_chunk_size) writesl(info->mmio_base + NDDB, info->data_buff + info->data_buff_pos, - DIV_ROUND_UP(info->step_chunk_size, 4)); + DIV_ROUND_UP(data_len, 4)); if (info->step_spare_size) writesl(info->mmio_base + NDDB, @@ -628,7 +639,10 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) if (info->step_chunk_size) drain_fifo(info, info->data_buff + info->data_buff_pos, - DIV_ROUND_UP(info->step_chunk_size, 4)); + DIV_ROUND_UP(data_len, 4)); + + if (info->force_raw) + break; if (info->step_spare_size) drain_fifo(info, @@ -642,7 +656,7 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) } /* Update buffer pointers for multi-page read/write */ - info->data_buff_pos += info->step_chunk_size; + info->data_buff_pos += data_len; info->oob_buff_pos += info->step_spare_size; } @@ -796,7 +810,8 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) case NAND_CMD_READ0: case NAND_CMD_READOOB: case NAND_CMD_PAGEPROG: - info->use_ecc = 1; + if (!info->force_raw) + info->use_ecc = 1; break; case NAND_CMD_PARAM: info->use_spare = 0; @@ -866,7 +881,13 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, * which is either naked-read or last-read according to the * state. */ - if (mtd->writesize == info->chunk_size) { + if (info->force_raw) { + info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) | + NDCB0_LEN_OVRD | + NDCB0_EXT_CMD_TYPE(ext_cmd_type); + info->ndcb3 = info->step_chunk_size + + info->step_spare_size + info->ecc_size; + } else if (mtd->writesize == info->chunk_size) { info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); } else if (mtd->writesize > info->chunk_size) { info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) @@ -1216,6 +1237,7 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, { struct pxa3xx_nand_host *host = nand_get_controller_data(chip); struct pxa3xx_nand_info *info = host->info_data; + int bf; chip->read_buf(mtd, buf, mtd->writesize); chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); @@ -1223,12 +1245,30 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, if (info->retcode == ERR_CORERR && info->use_ecc) { mtd->ecc_stats.corrected += info->ecc_err_cnt; - } else if (info->retcode == ERR_UNCORERR) { + } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) { /* - * for blank page (all 0xff), HW will calculate its ECC as - * 0, which is different from the ECC information within - * OOB, ignore such uncorrectable errors + * Empty pages will trigger uncorrectable errors. Re-read the + * entire page in raw mode and check for bits not being "1". + * If there are more than the supported strength, then it means + * this is an actual uncorrectable error. */ + chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page); + bf = nand_check_erased_ecc_chunk(buf, mtd->writesize, + chip->oob_poi, mtd->oobsize, + NULL, 0, chip->ecc.strength); + if (bf < 0) { + mtd->ecc_stats.failed++; + } else if (bf) { + mtd->ecc_stats.corrected += bf; + info->max_bitflips = max_t(unsigned int, + info->max_bitflips, bf); + info->retcode = ERR_CORERR; + } else { + info->retcode = ERR_NONE; + } + + } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) { + /* Raw read is not supported with Hamming ECC engine */ if (is_buf_blank(buf, mtd->writesize)) info->retcode = ERR_NONE; else @@ -1238,6 +1278,69 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, return info->max_bitflips; } +static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + struct pxa3xx_nand_host *host = chip->priv; + struct pxa3xx_nand_info *info = host->info_data; + int chunk, ecc_off_buf; + + if (!info->ecc_bch) + return -ENOTSUPP; + + /* + * Set the force_raw boolean, then re-call ->cmdfunc() that will run + * pxa3xx_nand_start(), which will actually disable the ECC engine. + */ + info->force_raw = true; + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + + ecc_off_buf = (info->nfullchunks * info->spare_size) + + info->last_spare_size; + for (chunk = 0; chunk < info->nfullchunks; chunk++) { + chip->read_buf(mtd, + buf + (chunk * info->chunk_size), + info->chunk_size); + chip->read_buf(mtd, + chip->oob_poi + + (chunk * (info->spare_size)), + info->spare_size); + chip->read_buf(mtd, + chip->oob_poi + ecc_off_buf + + (chunk * (info->ecc_size)), + info->ecc_size - 2); + } + + if (info->ntotalchunks > info->nfullchunks) { + chip->read_buf(mtd, + buf + (info->nfullchunks * info->chunk_size), + info->last_chunk_size); + chip->read_buf(mtd, + chip->oob_poi + + (info->nfullchunks * (info->spare_size)), + info->last_spare_size); + chip->read_buf(mtd, + chip->oob_poi + ecc_off_buf + + (info->nfullchunks * (info->ecc_size)), + info->ecc_size - 2); + } + + info->force_raw = false; + + return 0; +} + +static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + /* Invalidate page cache */ + chip->pagebuf = -1; + + return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true, + page); +} + static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -1488,7 +1591,7 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info, info->chunk_size = 1024; info->spare_size = 0; info->last_chunk_size = 1024; - info->last_spare_size = 64; + info->last_spare_size = 32; info->ecc_size = 32; ecc->mode = NAND_ECC_HW; ecc->size = info->chunk_size; @@ -1669,6 +1772,8 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) nand_set_controller_data(chip, host); chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; + chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw; + chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw; chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; chip->controller = &info->controller; chip->waitfunc = pxa3xx_nand_waitfunc; diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 619d0403e9..3326c2b096 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -31,6 +31,11 @@ #include #include #include +#if CONFIG_NAND_VF610_NFC_DT +#include +#include +#include +#endif /* Register Offsets */ #define NFC_FLASH_CMD1 0x3F00 @@ -641,7 +646,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) .flash_bbt = 1, }; - nfc = malloc(sizeof(*nfc)); + nfc = calloc(1, sizeof(*nfc)); if (!nfc) { printf(KERN_ERR "%s: Memory exhausted!\n", __func__); return -ENOMEM; @@ -760,9 +765,51 @@ error: return err; } +#if CONFIG_NAND_VF610_NFC_DT +static const struct udevice_id vf610_nfc_dt_ids[] = { + { + .compatible = "fsl,vf610-nfc", + }, + { /* sentinel */ } +}; + +static int vf610_nfc_dt_probe(struct udevice *dev) +{ + struct resource res; + int ret; + + ret = dev_read_resource(dev, 0, &res); + if (ret) + return ret; + + return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start, + resource_size(&res))); +} + +U_BOOT_DRIVER(vf610_nfc_dt) = { + .name = "vf610-nfc-dt", + .id = UCLASS_MTD, + .of_match = vf610_nfc_dt_ids, + .probe = vf610_nfc_dt_probe, +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(vf610_nfc_dt), + &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize NAND controller. (error %d)\n", + ret); +} +#else void board_nand_init(void) { int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); if (err) printf("VF610 NAND init failed (err %d)\n", err); } +#endif /* CONFIG_NAND_VF610_NFC_DT */ diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 7fef754c63..7b9891cb98 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -57,6 +57,8 @@ static const char *sandbox_sf_state_name(enum sandbox_sf_state state) /* Bits for the status register */ #define STAT_WIP (1 << 0) #define STAT_WEL (1 << 1) +#define STAT_BP_SHIFT 2 +#define STAT_BP_MASK (7 << STAT_BP_SHIFT) /* Assume all SPI flashes have 3 byte addresses since they do atm */ #define SF_ADDR_LEN 3 @@ -102,6 +104,14 @@ struct sandbox_spi_flash_plat_data { int cs; }; +void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask) +{ + struct sandbox_spi_flash *sbsf = dev_get_priv(dev); + + sbsf->status &= ~STAT_BP_MASK; + sbsf->status |= bp_mask << STAT_BP_SHIFT; +} + /** * This is a very strange probe function. If it has platform data (which may * have come from the device tree) then this function gets the filename and diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 662525f016..719a2fd23a 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -28,6 +28,15 @@ int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len) return log_ret(sf_get_ops(dev)->erase(dev, offset, len)); } +int spl_flash_get_sw_write_prot(struct udevice *dev) +{ + struct dm_spi_flash_ops *ops = sf_get_ops(dev); + + if (!ops->get_sw_write_prot) + return -ENOSYS; + return log_ret(ops->get_sw_write_prot(dev)); +} + /* * TODO(sjg@chromium.org): This is an old-style function. We should remove * it when all SPI flash drivers use dm diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index b47ecf1b82..98fdf6f5b9 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -176,6 +176,9 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, /* Flash erase(sectors) operation, support all possible erase commands */ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); +/* Get software write-protect value (BP bits) */ +int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash); + /* Lock stmicro spi flash region */ int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 58d7e44399..68c36002be 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -10,6 +10,7 @@ #include static struct mtd_info sf_mtd_info; +static bool sf_mtd_registered; static char sf_mtd_name[8]; static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) @@ -17,6 +18,9 @@ static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) struct spi_flash *flash = mtd->priv; int err; + if (!flash) + return -ENODEV; + instr->state = MTD_ERASING; err = spi_flash_erase(flash, instr->addr, instr->len); @@ -38,6 +42,9 @@ static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, struct spi_flash *flash = mtd->priv; int err; + if (!flash) + return -ENODEV; + err = spi_flash_read(flash, from, len, buf); if (!err) *retlen = len; @@ -51,6 +58,9 @@ static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, struct spi_flash *flash = mtd->priv; int err; + if (!flash) + return -ENODEV; + err = spi_flash_write(flash, to, len, buf); if (!err) *retlen = len; @@ -73,6 +83,17 @@ static int spi_flash_mtd_number(void) int spi_flash_mtd_register(struct spi_flash *flash) { + int ret; + + if (sf_mtd_registered) { + ret = del_mtd_device(&sf_mtd_info); + if (ret) + return ret; + + sf_mtd_registered = false; + } + + sf_mtd_registered = false; memset(&sf_mtd_info, 0, sizeof(sf_mtd_info)); sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number()); @@ -94,10 +115,33 @@ int spi_flash_mtd_register(struct spi_flash *flash) sf_mtd_info.numeraseregions = 0; sf_mtd_info.erasesize = flash->sector_size; - return add_mtd_device(&sf_mtd_info); + ret = add_mtd_device(&sf_mtd_info); + if (!ret) + sf_mtd_registered = true; + + return ret; } void spi_flash_mtd_unregister(void) { - del_mtd_device(&sf_mtd_info); + int ret; + + if (!sf_mtd_registered) + return; + + ret = del_mtd_device(&sf_mtd_info); + if (!ret) { + sf_mtd_registered = false; + return; + } + + /* + * Setting mtd->priv to NULL is the best we can do. Thanks to that, + * the MTD layer can still call mtd hooks without risking a + * use-after-free bug. Still, things should be fixed to prevent the + * spi_flash object from being destroyed when del_mtd_device() fails. + */ + sf_mtd_info.priv = NULL; + printf("Failed to unregister MTD %s and the spi_flash object is going away: you're in deep trouble!", + sf_mtd_info.name); } diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 6eda9d69f5..faaab26d68 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -159,6 +159,13 @@ static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len) return spi_flash_cmd_erase_ops(flash, offset, len); } +static int spi_flash_std_get_sw_write_prot(struct udevice *dev) +{ + struct spi_flash *flash = dev_get_uclass_priv(dev); + + return spi_flash_cmd_get_sw_write_prot(flash); +} + static int spi_flash_std_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -172,10 +179,19 @@ static int spi_flash_std_probe(struct udevice *dev) return spi_flash_probe_slave(flash); } +static int spi_flash_std_remove(struct udevice *dev) +{ +#ifdef CONFIG_SPI_FLASH_MTD + spi_flash_mtd_unregister(); +#endif + return 0; +} + static const struct dm_spi_flash_ops spi_flash_std_ops = { .read = spi_flash_std_read, .write = spi_flash_std_write, .erase = spi_flash_std_erase, + .get_sw_write_prot = spi_flash_std_get_sw_write_prot, }; static const struct udevice_id spi_flash_std_ids[] = { @@ -188,6 +204,7 @@ U_BOOT_DRIVER(spi_flash_std) = { .id = UCLASS_SPI_FLASH, .of_match = spi_flash_std_ids, .probe = spi_flash_std_probe, + .remove = spi_flash_std_remove, .priv_auto_alloc_size = sizeof(struct spi_flash), .ops = &spi_flash_std_ops, }; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 9070ff3f73..87771d1691 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -150,6 +150,18 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash) +{ + u8 status; + int ret; + + ret = read_sr(flash, &status); + if (ret) + return ret; + + return (status >> 2) & 7; +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 39687431fb..7044c6adf3 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -11,13 +11,6 @@ config DM_ETH This is currently implemented in net/eth-uclass.c Look in include/net.h for details. -config DRIVER_TI_CPSW - bool "TI Common Platform Ethernet Switch" - select PHYLIB - help - This driver supports the TI three port switch gigabit ethernet - subsystem found in the TI SoCs. - menuconfig NETDEVICES bool "Network device support" depends on NET @@ -79,6 +72,24 @@ config BCM_SF2_ETH_GMAC by the BCM_SF2_ETH driver. Say Y to any bcmcygnus based platforms. +config BCM6348_ETH + bool "BCM6348 EMAC support" + depends on DM_ETH && ARCH_BMIPS + select DMA + select DMA_CHANNELS + select MII + select PHYLIB + help + This driver supports the BCM6348 Ethernet MAC. + +config BCM6368_ETH + bool "BCM6368 EMAC support" + depends on DM_ETH && ARCH_BMIPS + select DMA + select MII + help + This driver supports the BCM6368 Ethernet MAC. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH @@ -186,6 +197,32 @@ config FTMAC100 help This MAC is present in Andestech SoCs. +config FTGMAC100 + bool "Ftgmac100 Ethernet Support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Faraday's FTGMAC100 Gigabit SoC + Ethernet controller that can be found on Aspeed SoCs (which + include NCSI). + + It is fully compliant with IEEE 802.3 specification for + 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 + Mbps Ethernet and includes Reduced Media Independent + Interface (RMII) and Reduced Gigabit Media Independent + Interface (RGMII) interfaces. It adopts an AHB bus interface + and integrates a link list DMA engine with direct M-Bus + accesses for transmitting and receiving packets. It has + independent TX/RX fifos, supports half and full duplex (1000 + Mbps mode only supports full duplex), flow control for full + duplex and backpressure for half duplex. + + The FTGMAC100 also implements IP, TCP, UDP checksum offloads + and supports IEEE 802.1Q VLAN tag insertion and removal. It + offers high-priority transmit queue for QoS and CoS + applications. + + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on KIRKWOOD || ORION5X @@ -227,6 +264,13 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT7628_ETH + bool "MediaTek MT7628 Ethernet Interface" + depends on ARCH_MT7620 + help + The MediaTek MT7628 ethernet interface is used on MT7628 and + MT7688 based boards. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI @@ -322,10 +366,7 @@ config SH_ETHER help This driver supports the Ethernet for Renesas SH and ARM SoCs. -config DRIVER_TI_EMAC - bool "TI Davinci EMAC" - help - Support for davinci emac +source "drivers/net/ti/Kconfig" config XILINX_AXIEMAC depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878071..0dbfa03306 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -6,6 +6,8 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o +obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o +obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o @@ -30,13 +32,13 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o -obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o @@ -56,9 +58,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o obj-$(CONFIG_RENESAS_RAVB) += ravb.o obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o -obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o -obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_ULI526X) += uli526x.o obj-$(CONFIG_VSC7385_ENET) += vsc7385.o @@ -73,3 +73,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-y += ti/ diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c new file mode 100644 index 0000000000..7100e68bd2 --- /dev/null +++ b/drivers/net/bcm6348-eth.c @@ -0,0 +1,537 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ETH_RX_DESC PKTBUFSRX +#define ETH_MAX_MTU_SIZE 1518 +#define ETH_TIMEOUT 100 +#define ETH_TX_WATERMARK 32 + +/* ETH Receiver Configuration register */ +#define ETH_RXCFG_REG 0x00 +#define ETH_RXCFG_ENFLOW_SHIFT 5 +#define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT) + +/* ETH Receive Maximum Length register */ +#define ETH_RXMAXLEN_REG 0x04 +#define ETH_RXMAXLEN_SHIFT 0 +#define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT) + +/* ETH Transmit Maximum Length register */ +#define ETH_TXMAXLEN_REG 0x08 +#define ETH_TXMAXLEN_SHIFT 0 +#define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT) + +/* MII Status/Control register */ +#define MII_SC_REG 0x10 +#define MII_SC_MDCFREQDIV_SHIFT 0 +#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT) +#define MII_SC_PREAMBLE_EN_SHIFT 7 +#define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT) + +/* MII Data register */ +#define MII_DAT_REG 0x14 +#define MII_DAT_DATA_SHIFT 0 +#define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT) +#define MII_DAT_TA_SHIFT 16 +#define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT) +#define MII_DAT_REG_SHIFT 18 +#define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT) +#define MII_DAT_PHY_SHIFT 23 +#define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT) +#define MII_DAT_OP_SHIFT 28 +#define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT) +#define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT) + +/* ETH Interrupts Mask register */ +#define ETH_IRMASK_REG 0x18 + +/* ETH Interrupts register */ +#define ETH_IR_REG 0x1c +#define ETH_IR_MII_SHIFT 0 +#define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT) + +/* ETH Control register */ +#define ETH_CTL_REG 0x2c +#define ETH_CTL_ENABLE_SHIFT 0 +#define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT) +#define ETH_CTL_DISABLE_SHIFT 1 +#define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT) +#define ETH_CTL_RESET_SHIFT 2 +#define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT) +#define ETH_CTL_EPHY_SHIFT 3 +#define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT) + +/* ETH Transmit Control register */ +#define ETH_TXCTL_REG 0x30 +#define ETH_TXCTL_FD_SHIFT 0 +#define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT) + +/* ETH Transmit Watermask register */ +#define ETH_TXWMARK_REG 0x34 +#define ETH_TXWMARK_WM_SHIFT 0 +#define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT) + +/* MIB Control register */ +#define MIB_CTL_REG 0x38 +#define MIB_CTL_RDCLEAR_SHIFT 0 +#define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT) + +/* ETH Perfect Match registers */ +#define ETH_PM_CNT 4 +#define ETH_PML_REG(x) (0x58 + (x) * 0x8) +#define ETH_PMH_REG(x) (0x5c + (x) * 0x8) +#define ETH_PMH_VALID_SHIFT 16 +#define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT) + +/* MIB Counters registers */ +#define MIB_REG_CNT 55 +#define MIB_REG(x) (0x200 + (x) * 4) + +/* ETH data */ +struct bcm6348_eth_priv { + void __iomem *base; + /* DMA */ + struct dma rx_dma; + struct dma tx_dma; + /* PHY */ + int phy_id; + struct phy_device *phy_dev; +}; + +static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv) +{ + /* disable emac */ + clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK, + ETH_CTL_DISABLE_MASK); + + /* wait until emac is disabled */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_DISABLE_MASK, false, + ETH_TIMEOUT, false)) + pr_err("%s: error disabling emac\n", __func__); +} + +static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv) +{ + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK); +} + +static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv) +{ + /* reset emac */ + writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG); + wmb(); + + /* wait until emac is reset */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_RESET_MASK, false, + ETH_TIMEOUT, false)) + pr_err("%s: error resetting emac\n", __func__); +} + +static int bcm6348_eth_free_pkt(struct udevice *dev, uchar *packet, int len) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_prepare_rcv_buf(&priv->rx_dma, packet, len); +} + +static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_receive(&priv->rx_dma, (void**)packetp, NULL); +} + +static int bcm6348_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + return dma_send(&priv->tx_dma, packet, length, NULL); +} + +static int bcm6348_eth_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* mac duplex parameters */ + if (phydev->duplex) + setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + else + clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + + /* rx flow control (pause frame handling) */ + if (phydev->pause) + setbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + else + clrbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + + return 0; +} + +static int bcm6348_eth_start(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + int ret, i; + + /* prepare rx dma buffers */ + for (i = 0; i < ETH_RX_DESC; i++) { + ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i], + PKTSIZE_ALIGN); + if (ret < 0) + break; + } + + /* enable dma rx channel */ + dma_enable(&priv->rx_dma); + + /* enable dma tx channel */ + dma_enable(&priv->tx_dma); + + ret = phy_startup(priv->phy_dev); + if (ret) { + pr_err("%s: could not initialize phy\n", __func__); + return ret; + } + + if (!priv->phy_dev->link) { + pr_err("%s: no phy link\n", __func__); + return -EIO; + } + + bcm6348_eth_adjust_link(dev, priv->phy_dev); + + /* zero mib counters */ + for (i = 0; i < MIB_REG_CNT; i++) + writel_be(0, MIB_REG(i)); + + /* enable rx flow control */ + setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK); + + /* set max rx/tx length */ + writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) & + ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG); + writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) & + ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG); + + /* set correct transmit fifo watermark */ + writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) & + ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG); + + /* enable emac */ + bcm6348_eth_mac_enable(priv); + + /* clear interrupts */ + writel_be(0, priv->base + ETH_IRMASK_REG); + + return 0; +} + +static void bcm6348_eth_stop(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* disable dma rx channel */ + dma_disable(&priv->rx_dma); + + /* disable dma tx channel */ + dma_disable(&priv->tx_dma); + + /* disable emac */ + bcm6348_eth_mac_disable(priv); +} + +static int bcm6348_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + bool running = false; + + /* check if emac is running */ + if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK) + running = true; + + /* disable emac */ + if (running) + bcm6348_eth_mac_disable(priv); + + /* set mac address */ + writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 | + (pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]), + priv->base + ETH_PML_REG(0)); + writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) | + ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0)); + + /* enable emac */ + if (running) + bcm6348_eth_mac_enable(priv); + + return 0; +} + +static const struct eth_ops bcm6348_eth_ops = { + .free_pkt = bcm6348_eth_free_pkt, + .recv = bcm6348_eth_recv, + .send = bcm6348_eth_send, + .start = bcm6348_eth_start, + .stop = bcm6348_eth_stop, + .write_hwaddr = bcm6348_eth_write_hwaddr, +}; + +static const struct udevice_id bcm6348_eth_ids[] = { + { .compatible = "brcm,bcm6348-enet", }, + { /* sentinel */ } +}; + +static int bcm6348_mdio_op(void __iomem *base, uint32_t data) +{ + /* make sure mii interrupt status is cleared */ + writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG); + + /* issue mii op */ + writel_be(data, base + MII_DAT_REG); + + /* wait until emac is disabled */ + return wait_for_bit_be32(base + ETH_IR_REG, + ETH_IR_MII_MASK, true, + ETH_TIMEOUT, false); +} + +static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr, + int reg) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_READ; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK; + val >>= MII_DAT_DATA_SHIFT; + + return val; +} + +static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr, + int reg, u16 value) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_WRITE; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int bcm6348_mdio_init(const char *name, void __iomem *base) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + pr_err("%s: failed to allocate MDIO bus\n", __func__); + return -ENOMEM; + } + + bus->read = bcm6348_mdio_read; + bus->write = bcm6348_mdio_write; + bus->priv = base; + snprintf(bus->name, sizeof(bus->name), "%s", name); + + return mdio_register(bus); +} + +static int bcm6348_phy_init(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *bus; + + /* get mii bus */ + bus = miiphy_get_dev_by_name(dev->name); + + /* phy connect */ + priv->phy_dev = phy_connect(bus, priv->phy_id, dev, + pdata->phy_interface); + if (!priv->phy_dev) { + pr_err("%s: no phy device\n", __func__); + return -ENODEV; + } + + priv->phy_dev->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_Pause | + SUPPORTED_MII); + priv->phy_dev->advertising = priv->phy_dev->supported; + + /* phy config */ + phy_config(priv->phy_dev); + + return 0; +} + +static int bcm6348_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phy; + const char *phy_mode; + int ret, i; + + /* get base address */ + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + pdata->iobase = (phys_addr_t) priv->base; + + /* get phy mode */ + pdata->phy_interface = PHY_INTERFACE_MODE_NONE; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) + return -ENODEV; + + /* get phy */ + if (dev_read_phandle_with_args(dev, "phy", NULL, 0, 0, &phy)) + return -ENOENT; + priv->phy_id = ofnode_read_u32_default(phy.node, "reg", -1); + + /* get dma channels */ + ret = dma_get_by_name(dev, "tx", &priv->tx_dma); + if (ret) + return -EINVAL; + + ret = dma_get_by_name(dev, "rx", &priv->rx_dma); + if (ret) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("%s: error enabling clock %d\n", __func__, i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("%s: error freeing clock %d\n", __func__, i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("%s: error deasserting reset %d\n", __func__, i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("%s: error freeing reset %d\n", __func__, i); + return ret; + } + } + + /* disable emac */ + bcm6348_eth_mac_disable(priv); + + /* reset emac */ + bcm6348_eth_mac_reset(priv); + + /* select correct mii interface */ + if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL) + clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + else + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + + /* turn on mdc clock */ + writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) | + MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG); + + /* set mib counters to not clear when read */ + clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK); + + /* initialize perfect match registers */ + for (i = 0; i < ETH_PM_CNT; i++) { + writel_be(0, priv->base + ETH_PML_REG(i)); + writel_be(0, priv->base + ETH_PMH_REG(i)); + } + + /* init mii bus */ + ret = bcm6348_mdio_init(dev->name, priv->base); + if (ret) + return ret; + + /* init phy */ + ret = bcm6348_phy_init(dev); + if (ret) + return ret; + + return 0; +} + +U_BOOT_DRIVER(bcm6348_eth) = { + .name = "bcm6348_eth", + .id = UCLASS_ETH, + .of_match = bcm6348_eth_ids, + .ops = &bcm6348_eth_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv), + .probe = bcm6348_eth_probe, +}; diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c new file mode 100644 index 0000000000..a31efba9d1 --- /dev/null +++ b/drivers/net/bcm6368-eth.c @@ -0,0 +1,625 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ETH_PORT_STR "brcm,enetsw-port" + +#define ETH_RX_DESC PKTBUFSRX +#define ETH_ZLEN 60 +#define ETH_TIMEOUT 100 + +#define ETH_MAX_PORT 8 +#define ETH_RGMII_PORT0 4 + +/* Port traffic control */ +#define ETH_PTCTRL_REG(x) (0x0 + (x)) +#define ETH_PTCTRL_RXDIS_SHIFT 0 +#define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT) +#define ETH_PTCTRL_TXDIS_SHIFT 1 +#define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT) + +/* Switch mode register */ +#define ETH_SWMODE_REG 0xb +#define ETH_SWMODE_FWD_EN_SHIFT 1 +#define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT) + +/* IMP override Register */ +#define ETH_IMPOV_REG 0xe +#define ETH_IMPOV_LINKUP_SHIFT 0 +#define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT) +#define ETH_IMPOV_FDX_SHIFT 1 +#define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT) +#define ETH_IMPOV_100_SHIFT 2 +#define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT) +#define ETH_IMPOV_1000_SHIFT 3 +#define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT) +#define ETH_IMPOV_RXFLOW_SHIFT 4 +#define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT) +#define ETH_IMPOV_TXFLOW_SHIFT 5 +#define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT) +#define ETH_IMPOV_FORCE_SHIFT 7 +#define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT) + +/* Port override Register */ +#define ETH_PORTOV_REG(x) (0x58 + (x)) +#define ETH_PORTOV_LINKUP_SHIFT 0 +#define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT) +#define ETH_PORTOV_FDX_SHIFT 1 +#define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT) +#define ETH_PORTOV_100_SHIFT 2 +#define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT) +#define ETH_PORTOV_1000_SHIFT 3 +#define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT) +#define ETH_PORTOV_RXFLOW_SHIFT 4 +#define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT) +#define ETH_PORTOV_TXFLOW_SHIFT 5 +#define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT) +#define ETH_PORTOV_ENABLE_SHIFT 6 +#define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT) + +/* Port RGMII control register */ +#define ETH_RGMII_CTRL_REG(x) (0x60 + (x)) +#define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7) +#define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) +#define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4) +#define ETH_RGMII_CTRL_RGMII_MODE (0 << 4) +#define ETH_RGMII_CTRL_MII_MODE (1 << 4) +#define ETH_RGMII_CTRL_RVMII_MODE (2 << 4) +#define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0) + +/* Port RGMII timing register */ +#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) + +/* MDIO control register */ +#define MII_SC_REG 0xb0 +#define MII_SC_EXT_SHIFT 16 +#define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT) +#define MII_SC_REG_SHIFT 20 +#define MII_SC_PHYID_SHIFT 25 +#define MII_SC_RD_SHIFT 30 +#define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT) +#define MII_SC_WR_SHIFT 31 +#define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT) + +/* MDIO data register */ +#define MII_DAT_REG 0xb4 + +/* Global Management Configuration Register */ +#define ETH_GMCR_REG 0x200 +#define ETH_GMCR_RST_MIB_SHIFT 0 +#define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT) + +/* Jumbo control register port mask register */ +#define ETH_JMBCTL_PORT_REG 0x4004 + +/* Jumbo control mib good frame register */ +#define ETH_JMBCTL_MAXSIZE_REG 0x4008 + +/* ETH port data */ +struct bcm_enetsw_port { + bool used; + const char *name; + /* Config */ + bool bypass_link; + int force_speed; + bool force_duplex_full; + /* PHY */ + int phy_id; +}; + +/* ETH data */ +struct bcm6368_eth_priv { + void __iomem *base; + /* DMA */ + struct dma rx_dma; + struct dma tx_dma; + /* Ports */ + uint8_t num_ports; + struct bcm_enetsw_port used_ports[ETH_MAX_PORT]; + int sw_port_link[ETH_MAX_PORT]; + bool rgmii_override; + bool rgmii_timing; + /* PHY */ + int phy_id; +}; + +static inline bool bcm_enet_port_is_rgmii(int portid) +{ + return portid >= ETH_RGMII_PORT0; +} + +static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext, + int phy_id, int reg) +{ + uint32_t val; + + writel_be(0, priv->base + MII_SC_REG); + + val = MII_SC_RD_MASK | + (phy_id << MII_SC_PHYID_SHIFT) | + (reg << MII_SC_REG_SHIFT); + + if (ext) + val |= MII_SC_EXT_MASK; + + writel_be(val, priv->base + MII_SC_REG); + udelay(50); + + return readw_be(priv->base + MII_DAT_REG); +} + +static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext, + int phy_id, int reg, u16 data) +{ + uint32_t val; + + writel_be(0, priv->base + MII_SC_REG); + + val = MII_SC_WR_MASK | + (phy_id << MII_SC_PHYID_SHIFT) | + (reg << MII_SC_REG_SHIFT); + + if (ext) + val |= MII_SC_EXT_MASK; + + val |= data; + + writel_be(val, priv->base + MII_SC_REG); + udelay(50); + + return 0; +} + +static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + return dma_prepare_rcv_buf(&priv->rx_dma, packet, len); +} + +static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + return dma_receive(&priv->rx_dma, (void**)packetp, NULL); +} + +static int bcm6368_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + /* pad packets smaller than ETH_ZLEN */ + if (length < ETH_ZLEN) { + memset(packet + length, 0, ETH_ZLEN - length); + length = ETH_ZLEN; + } + + return dma_send(&priv->tx_dma, packet, length, NULL); +} + +static int bcm6368_eth_adjust_link(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + unsigned int i; + + for (i = 0; i < priv->num_ports; i++) { + struct bcm_enetsw_port *port; + int val, j, up, adv, lpa, speed, duplex, media; + int external_phy = bcm_enet_port_is_rgmii(i); + u8 override; + + port = &priv->used_ports[i]; + if (!port->used) + continue; + + if (port->bypass_link) + continue; + + /* dummy read to clear */ + for (j = 0; j < 2; j++) + val = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_BMSR); + + if (val == 0xffff) + continue; + + up = (val & BMSR_LSTATUS) ? 1 : 0; + if (!(up ^ priv->sw_port_link[i])) + continue; + + priv->sw_port_link[i] = up; + + /* link changed */ + if (!up) { + dev_info(&priv->pdev->dev, "link DOWN on %s\n", + port->name); + writeb_be(ETH_PORTOV_ENABLE_MASK, + priv->base + ETH_PORTOV_REG(i)); + writeb_be(ETH_PTCTRL_RXDIS_MASK | + ETH_PTCTRL_TXDIS_MASK, + priv->base + ETH_PTCTRL_REG(i)); + continue; + } + + adv = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_ADVERTISE); + + lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id, + MII_LPA); + + /* figure out media and duplex from advertise and LPA values */ + media = mii_nway_result(lpa & adv); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) + speed = 100; + else + speed = 10; + + if (val & BMSR_ESTATEN) { + adv = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_CTRL1000); + + lpa = bcm6368_mdio_read(priv, external_phy, + port->phy_id, MII_STAT1000); + + if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && + (lpa & (LPA_1000FULL | LPA_1000HALF))) { + speed = 1000; + duplex = (lpa & LPA_1000FULL); + } + } + + pr_alert("link UP on %s, %dMbps, %s-duplex\n", + port->name, speed, duplex ? "full" : "half"); + + override = ETH_PORTOV_ENABLE_MASK | + ETH_PORTOV_LINKUP_MASK; + + if (speed == 1000) + override |= ETH_PORTOV_1000_MASK; + else if (speed == 100) + override |= ETH_PORTOV_100_MASK; + if (duplex) + override |= ETH_PORTOV_FDX_MASK; + + writeb_be(override, priv->base + ETH_PORTOV_REG(i)); + writeb_be(0, priv->base + ETH_PTCTRL_REG(i)); + } + + return 0; +} + +static int bcm6368_eth_start(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + uint8_t i; + + /* prepare rx dma buffers */ + for (i = 0; i < ETH_RX_DESC; i++) { + int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i], + PKTSIZE_ALIGN); + if (ret < 0) + break; + } + + /* enable dma rx channel */ + dma_enable(&priv->rx_dma); + + /* enable dma tx channel */ + dma_enable(&priv->tx_dma); + + /* apply override config for bypass_link ports here. */ + for (i = 0; i < priv->num_ports; i++) { + struct bcm_enetsw_port *port; + u8 override; + + port = &priv->used_ports[i]; + if (!port->used) + continue; + + if (!port->bypass_link) + continue; + + override = ETH_PORTOV_ENABLE_MASK | + ETH_PORTOV_LINKUP_MASK; + + switch (port->force_speed) { + case 1000: + override |= ETH_PORTOV_1000_MASK; + break; + case 100: + override |= ETH_PORTOV_100_MASK; + break; + case 10: + break; + default: + pr_warn("%s: invalid forced speed on port %s\n", + __func__, port->name); + break; + } + + if (port->force_duplex_full) + override |= ETH_PORTOV_FDX_MASK; + + writeb_be(override, priv->base + ETH_PORTOV_REG(i)); + writeb_be(0, priv->base + ETH_PTCTRL_REG(i)); + } + + bcm6368_eth_adjust_link(dev); + + return 0; +} + +static void bcm6368_eth_stop(struct udevice *dev) +{ + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + + /* disable dma rx channel */ + dma_disable(&priv->rx_dma); + + /* disable dma tx channel */ + dma_disable(&priv->tx_dma); +} + +static const struct eth_ops bcm6368_eth_ops = { + .free_pkt = bcm6368_eth_free_pkt, + .recv = bcm6368_eth_recv, + .send = bcm6368_eth_send, + .start = bcm6368_eth_start, + .stop = bcm6368_eth_stop, +}; + +static const struct udevice_id bcm6368_eth_ids[] = { + { .compatible = "brcm,bcm6368-enet", }, + { /* sentinel */ } +}; + +static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id) +{ + uint8_t i; + + for (i = 0; i < priv->num_ports; ++i) { + if (!priv->used_ports[i].used) + continue; + if (priv->used_ports[i].phy_id == phy_id) + return bcm_enet_port_is_rgmii(i); + } + + return true; +} + +static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr, + int reg) +{ + struct bcm6368_eth_priv *priv = bus->priv; + bool ext = bcm6368_phy_is_external(priv, addr); + + return bcm6368_mdio_read(priv, ext, addr, reg); +} + +static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr, + int reg, u16 data) +{ + struct bcm6368_eth_priv *priv = bus->priv; + bool ext = bcm6368_phy_is_external(priv, addr); + + return bcm6368_mdio_write(priv, ext, addr, reg, data); +} + +static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + pr_err("%s: failed to allocate MDIO bus\n", __func__); + return -ENOMEM; + } + + bus->read = bcm6368_mii_mdio_read; + bus->write = bcm6368_mii_mdio_write; + bus->priv = priv; + snprintf(bus->name, sizeof(bus->name), "%s", name); + + return mdio_register(bus); +} + +static int bcm6368_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6368_eth_priv *priv = dev_get_priv(dev); + int num_ports, ret, i; + uint32_t val; + ofnode node; + + /* get base address */ + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + pdata->iobase = (phys_addr_t) priv->base; + + /* get number of ports */ + num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT); + if (!num_ports || num_ports > ETH_MAX_PORT) + return -EINVAL; + + /* get dma channels */ + ret = dma_get_by_name(dev, "tx", &priv->tx_dma); + if (ret) + return -EINVAL; + + ret = dma_get_by_name(dev, "rx", &priv->rx_dma); + if (ret) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + + ret = clk_enable(&clk); + if (ret < 0) { + pr_err("%s: error enabling clock %d\n", __func__, i); + return ret; + } + + ret = clk_free(&clk); + if (ret < 0) { + pr_err("%s: error freeing clock %d\n", __func__, i); + return ret; + } + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + + ret = reset_deassert(&reset); + if (ret < 0) { + pr_err("%s: error deasserting reset %d\n", __func__, i); + return ret; + } + + ret = reset_free(&reset); + if (ret < 0) { + pr_err("%s: error freeing reset %d\n", __func__, i); + return ret; + } + } + + /* set priv data */ + priv->num_ports = num_ports; + if (dev_read_bool(dev, "brcm,rgmii-override")) + priv->rgmii_override = true; + if (dev_read_bool(dev, "brcm,rgmii-timing")) + priv->rgmii_timing = true; + + /* get ports */ + dev_for_each_subnode(node, dev) { + const char *comp; + const char *label; + unsigned int p; + int phy_id; + int speed; + + comp = ofnode_read_string(node, "compatible"); + if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR))) + continue; + + p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT); + if (p >= num_ports) + return -EINVAL; + + label = ofnode_read_string(node, "label"); + if (!label) { + debug("%s: node %s has no label\n", __func__, + ofnode_get_name(node)); + return -EINVAL; + } + + phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1); + + priv->used_ports[p].used = true; + priv->used_ports[p].name = label; + priv->used_ports[p].phy_id = phy_id; + + if (ofnode_read_bool(node, "full-duplex")) + priv->used_ports[p].force_duplex_full = true; + if (ofnode_read_bool(node, "bypass-link")) + priv->used_ports[p].bypass_link = true; + speed = ofnode_read_u32_default(node, "speed", 0); + if (speed) + priv->used_ports[p].force_speed = speed; + } + + /* init mii bus */ + ret = bcm6368_mdio_init(dev->name, priv); + if (ret) + return ret; + + /* disable all ports */ + for (i = 0; i < priv->num_ports; i++) { + writeb_be(ETH_PORTOV_ENABLE_MASK, + priv->base + ETH_PORTOV_REG(i)); + writeb_be(ETH_PTCTRL_RXDIS_MASK | + ETH_PTCTRL_TXDIS_MASK, + priv->base + ETH_PTCTRL_REG(i)); + + priv->sw_port_link[i] = 0; + } + + /* enable external ports */ + for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) { + u8 rgmii_ctrl; + + if (!priv->used_ports[i].used) + continue; + + rgmii_ctrl = readb_be(priv->base + ETH_RGMII_CTRL_REG(i)); + rgmii_ctrl |= ETH_RGMII_CTRL_GMII_CLK_EN; + if (priv->rgmii_override) + rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN; + if (priv->rgmii_timing) + rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN; + writeb_be(rgmii_ctrl, priv->base + ETH_RGMII_CTRL_REG(i)); + } + + /* reset mib */ + val = readb_be(priv->base + ETH_GMCR_REG); + val |= ETH_GMCR_RST_MIB_MASK; + writeb_be(val, priv->base + ETH_GMCR_REG); + mdelay(1); + val &= ~ETH_GMCR_RST_MIB_MASK; + writeb_be(val, priv->base + ETH_GMCR_REG); + mdelay(1); + + /* force CPU port state */ + val = readb_be(priv->base + ETH_IMPOV_REG); + val |= ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK; + writeb_be(val, priv->base + ETH_IMPOV_REG); + + /* enable switch forward engine */ + val = readb_be(priv->base + ETH_SWMODE_REG); + val |= ETH_SWMODE_FWD_EN_MASK; + writeb_be(val, priv->base + ETH_SWMODE_REG); + + /* enable jumbo on all ports */ + writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG); + writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG); + + return 0; +} + +U_BOOT_DRIVER(bcm6368_eth) = { + .name = "bcm6368_eth", + .id = UCLASS_ETH, + .of_match = bcm6368_eth_ids, + .ops = &bcm6368_eth_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct bcm6368_eth_priv), + .probe = bcm6368_eth_probe, +}; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 19db0a8114..4fa26abc1b 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -838,6 +838,8 @@ static const struct udevice_id designware_eth_ids[] = { { .compatible = "altr,socfpga-stmmac" }, { .compatible = "amlogic,meson6-dwmac" }, { .compatible = "amlogic,meson-gx-dwmac" }, + { .compatible = "amlogic,meson-gxbb-dwmac" }, + { .compatible = "amlogic,meson-axg-dwmac" }, { .compatible = "st,stm32-dwmac" }, { } }; diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index b38f4df9f3..aecd290d72 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -77,9 +77,6 @@ static inline struct e1000_hw *e1000_hw_from_spi(struct spi_slave *spi) return container_of(spi, struct e1000_hw, spi); } -/* Not sure why all of these are necessary */ -void spi_init(void) { /* Nothing to do */ } - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 99c5c649a0..32fb34b793 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index c5cf188f05..e19d7777dc 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -11,12 +11,14 @@ #include "fm.h" #include /* For struct qe_firmware */ -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include -#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH) #include -#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) #include +#include + +#ifdef CONFIG_ARM64 +#include +#include #endif struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; @@ -347,6 +349,100 @@ static void fm_init_qmi(struct fm_qmi_common *qmi) } /* Init common part of FM, index is fm num# like fm as above */ +#ifdef CONFIG_TFABOOT +int fm_init_common(int index, struct ccsr_fman *reg) +{ + int rc; + void *addr = NULL; + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NOR) { + addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE); + } else if (src == BOOT_SOURCE_IFC_NAND) { + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + + rc = nand_read(get_nand_dev_by_index(0), + (loff_t)CONFIG_SYS_FMAN_FW_ADDR, + &fw_length, (u_char *)addr); + if (rc == -EUCLEAN) { + printf("NAND read of FMAN firmware at offset 0x%x failed %d\n", + CONFIG_SYS_FMAN_FW_ADDR, rc); + } + } else if (src == BOOT_SOURCE_QSPI_NOR) { + struct spi_flash *ucode_flash; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + int ret = 0; + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + ucode_flash = dev_get_uclass_priv(new); +#else + ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!ucode_flash) { + printf("SF: probe for ucode failed\n"); + } else { + ret = spi_flash_read(ucode_flash, + CONFIG_SYS_FMAN_FW_ADDR + + CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for ucode failed\n"); + spi_flash_free(ucode_flash); + } + } else if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, + addr); + } + } else { + addr = NULL; + } + + /* Upload the Fman microcode if it's present */ + rc = fman_upload_firmware(index, ®->fm_imem, addr); + if (rc) + return rc; + env_set_addr("fman_ucode", addr); + + fm_init_muram(index, ®->muram); + fm_init_qmi(®->fm_qmi_common); + fm_init_fpm(®->fm_fpm); + + /* clear DMA status */ + setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL); + + /* set DMA mode */ + setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER); + + return fm_init_bmi(index, ®->fm_bmi_common); +} +#else int fm_init_common(int index, struct ccsr_fman *reg) { int rc; @@ -429,3 +525,4 @@ int fm_init_common(int index, struct ccsr_fman *reg) return fm_init_bmi(index, ®->fm_bmi_common); } +#endif diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index c996f5f4a1..92c38a81bd 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -7,321 +7,239 @@ * * (C) Copyright 2010 Andes Technology * Macpaul Lin + * + * Copyright (C) 2018, IBM Corporation. */ -#include -#include -#include +#include +#include +#include #include -#include -#include -#include +#include +#include +#include #include "ftgmac100.h" -#define ETH_ZLEN 60 -#define CFG_XBUF_SIZE 1536 +/* Min frame ethernet frame size without FCS */ +#define ETH_ZLEN 60 -/* RBSR - hw default init value is also 0x640 */ -#define RBSR_DEFAULT_VALUE 0x640 +/* Receive Buffer Size Register - HW default is 0x640 */ +#define FTGMAC100_RBSR_DEFAULT 0x640 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ #define PKTBUFSTX 4 /* must be power of 2 */ +/* Timeout for transmit */ +#define FTGMAC100_TX_TIMEOUT_MS 1000 + +/* Timeout for a mdio read/write operation */ +#define FTGMAC100_MDIO_TIMEOUT_USEC 10000 + +/* + * MDC clock cycle threshold + * + * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 + */ +#define MDC_CYCTHR 0x34 + +/* + * ftgmac100 model variants + */ +enum ftgmac100_model { + FTGMAC100_MODEL_FARADAY, + FTGMAC100_MODEL_ASPEED, +}; + +/** + * struct ftgmac100_data - private data for the FTGMAC100 driver + * + * @iobase: The base address of the hardware registers + * @txdes: The array of transmit descriptors + * @rxdes: The array of receive descriptors + * @tx_index: Transmit descriptor index in @txdes + * @rx_index: Receive descriptor index in @rxdes + * @phy_addr: The PHY interface address to use + * @phydev: The PHY device backing the MAC + * @bus: The mdio bus + * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) + * @max_speed: Maximum speed of Ethernet connection supported by MAC + * @clks: The bulk of clocks assigned to the device in the DT + * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer + * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer + */ struct ftgmac100_data { - ulong txdes_dma; - struct ftgmac100_txdes *txdes; - ulong rxdes_dma; - struct ftgmac100_rxdes *rxdes; + struct ftgmac100 *iobase; + + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; int tx_index; int rx_index; - int phy_addr; + + u32 phy_addr; + struct phy_device *phydev; + struct mii_dev *bus; + u32 phy_mode; + u32 max_speed; + + struct clk_bulk clks; + + /* End of RX/TX ring buffer bits. Depend on model */ + u32 rxdes0_edorr_mask; + u32 txdes0_edotr_mask; }; /* * struct mii_bus functions */ -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, - int regnum) +static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - int phycr; - int i; - - phycr = readl(&ftgmac100->phycr); - - /* preserve MDC cycle threshold */ - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; - - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) - | FTGMAC100_PHYCR_REGAD(regnum) - | FTGMAC100_PHYCR_MIIRD; - - writel(phycr, &ftgmac100->phycr); - - for (i = 0; i < 10; i++) { - phycr = readl(&ftgmac100->phycr); - - if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { - int data; - - data = readl(&ftgmac100->phydata); - return FTGMAC100_PHYDATA_MIIRDATA(data); - } - - mdelay(10); - } - - debug("mdio read timed out\n"); - return -1; -} - -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, - int regnum, u16 value) -{ - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = bus->priv; + struct ftgmac100 *ftgmac100 = priv->iobase; int phycr; int data; - int i; + int ret; - phycr = readl(&ftgmac100->phycr); + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | + FTGMAC100_PHYCR_PHYAD(phy_addr) | + FTGMAC100_PHYCR_REGAD(reg_addr) | + FTGMAC100_PHYCR_MIIRD; + writel(phycr, &ftgmac100->phycr); - /* preserve MDC cycle threshold */ - phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + ret = readl_poll_timeout(&ftgmac100->phycr, phycr, + !(phycr & FTGMAC100_PHYCR_MIIRD), + FTGMAC100_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: mdio read failed (phy:%d reg:%x)\n", + priv->phydev->dev->name, phy_addr, reg_addr); + return ret; + } - phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) - | FTGMAC100_PHYCR_REGAD(regnum) - | FTGMAC100_PHYCR_MIIWR; + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); +} + +static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 value) +{ + struct ftgmac100_data *priv = bus->priv; + struct ftgmac100 *ftgmac100 = priv->iobase; + int phycr; + int data; + int ret; + + phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | + FTGMAC100_PHYCR_PHYAD(phy_addr) | + FTGMAC100_PHYCR_REGAD(reg_addr) | + FTGMAC100_PHYCR_MIIWR; data = FTGMAC100_PHYDATA_MIIWDATA(value); writel(data, &ftgmac100->phydata); writel(phycr, &ftgmac100->phycr); - for (i = 0; i < 10; i++) { - phycr = readl(&ftgmac100->phycr); - - if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { - debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ - "phy_addr: %x\n", phy_addr); - return 0; - } - - mdelay(1); + ret = readl_poll_timeout(&ftgmac100->phycr, phycr, + !(phycr & FTGMAC100_PHYCR_MIIWR), + FTGMAC100_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: mdio write failed (phy:%d reg:%x)\n", + priv->phydev->dev->name, phy_addr, reg_addr); } - debug("mdio write timed out\n"); - return -1; + return ret; } -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +static int ftgmac100_mdio_init(struct udevice *dev) { - *value = ftgmac100_mdiobus_read(dev , addr, reg); + struct ftgmac100_data *priv = dev_get_priv(dev); + struct mii_dev *bus; + int ret; - if (*value == -1) - return -1; + bus = mdio_alloc(); + if (!bus) + return -ENOMEM; + + bus->read = ftgmac100_mdio_read; + bus->write = ftgmac100_mdio_write; + bus->priv = priv; + + ret = mdio_register_seq(bus, dev->seq); + if (ret) { + free(bus); + return ret; + } + + priv->bus = bus; return 0; } -int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv) { - if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) - return -1; + struct ftgmac100 *ftgmac100 = priv->iobase; + struct phy_device *phydev = priv->phydev; + u32 maccr; - return 0; -} - -static int ftgmac100_phy_reset(struct eth_device *dev) -{ - struct ftgmac100_data *priv = dev->priv; - int i; - u16 status, adv; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - - ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); - - printf("%s: Starting autonegotiation...\n", dev->name); - - ftgmac100_phy_write(dev, priv->phy_addr, - MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - - for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); - - if (status & BMSR_ANEGCOMPLETE) - break; - mdelay(1); + if (!phydev->link) { + dev_err(phydev->dev, "No link\n"); + return -EREMOTEIO; } - if (status & BMSR_ANEGCOMPLETE) { - printf("%s: Autonegotiation complete\n", dev->name); - } else { - printf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->name, status); - return 0; - } - - return 1; -} - -static int ftgmac100_phy_init(struct eth_device *dev) -{ - struct ftgmac100_data *priv = dev->priv; - - int phy_addr; - u16 phy_id, status, adv, lpa, stat_ge; - int media, speed, duplex; - int i; - - /* Check if the PHY is up to snuff... */ - for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { - - ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); - - /* - * When it is unable to found PHY, - * the interface usually return 0xffff or 0x0000 - */ - if (phy_id != 0xffff && phy_id != 0x0) { - printf("%s: found PHY at 0x%02x\n", - dev->name, phy_addr); - priv->phy_addr = phy_addr; - break; - } - } - - if (phy_id == 0xffff || phy_id == 0x0) { - printf("%s: no PHY present\n", dev->name); - return 0; - } - - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); - - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - ftgmac100_phy_reset(dev); - - for (i = 0; i < 100000 / 100; i++) { - ftgmac100_phy_read(dev, priv->phy_addr, - MII_BMSR, &status); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - - if (!(status & BMSR_LSTATUS)) { - printf("%s: link down\n", dev->name); - return 0; - } - -#ifdef CONFIG_FTGMAC100_EGIGA - /* 1000 Base-T Status Register */ - ftgmac100_phy_read(dev, priv->phy_addr, - MII_STAT1000, &stat_ge); - - speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) - ? 1 : 0); - - duplex = ((stat_ge & LPA_1000FULL) - ? 1 : 0); - - if (speed) { /* Speed is 1000 */ - printf("%s: link up, 1000bps %s-duplex\n", - dev->name, duplex ? "full" : "half"); - return 0; - } -#endif - - ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); - ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); - - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - - printf("%s: link up, %sMbps %s-duplex\n", - dev->name, speed ? "100" : "10", duplex ? "full" : "half"); - - return 1; -} - -static int ftgmac100_update_link_speed(struct eth_device *dev) -{ - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; - - unsigned short stat_fe; - unsigned short stat_ge; - unsigned int maccr; - -#ifdef CONFIG_FTGMAC100_EGIGA - /* 1000 Base-T Status Register */ - ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); -#endif - - ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); - - if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ - return 0; - /* read MAC control register and clear related bits */ maccr = readl(&ftgmac100->maccr) & ~(FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP); -#ifdef CONFIG_FTGMAC100_EGIGA - if (stat_ge & LPA_1000FULL) { - /* set gmac for 1000BaseTX and Full Duplex */ - maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; - } - - if (stat_ge & LPA_1000HALF) { - /* set gmac for 1000BaseTX and Half Duplex */ + if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000) maccr |= FTGMAC100_MACCR_GIGA_MODE; - } -#endif - if (stat_fe & BMSR_100FULL) { - /* set MII for 100BaseTX and Full Duplex */ - maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; - } - - if (stat_fe & BMSR_10FULL) { - /* set MII for 10BaseT and Full Duplex */ - maccr |= FTGMAC100_MACCR_FULLDUP; - } - - if (stat_fe & BMSR_100HALF) { - /* set MII for 100BaseTX and Half Duplex */ + if (phydev->speed == 100) maccr |= FTGMAC100_MACCR_FAST_MODE; - } - if (stat_fe & BMSR_10HALF) { - /* set MII for 10BaseT and Half Duplex */ - /* we have already clear these bits, do nothing */ - ; - } + if (phydev->duplex) + maccr |= FTGMAC100_MACCR_FULLDUP; /* update MII config into maccr */ writel(maccr, &ftgmac100->maccr); - return 1; + return 0; +} + +static int ftgmac100_phy_init(struct udevice *dev) +{ + struct ftgmac100_data *priv = dev_get_priv(dev); + struct phy_device *phydev; + int ret; + + phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); + if (!phydev) + return -ENODEV; + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + priv->phydev = phydev; + phy_config(phydev); + + return 0; } /* * Reset MAC */ -static void ftgmac100_reset(struct eth_device *dev) +static void ftgmac100_reset(struct ftgmac100_data *priv) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; debug("%s()\n", __func__); - writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST); while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) ; @@ -330,10 +248,10 @@ static void ftgmac100_reset(struct eth_device *dev) /* * Set MAC address */ -static void ftgmac100_set_mac(struct eth_device *dev, - const unsigned char *mac) +static int ftgmac100_set_mac(struct ftgmac100_data *priv, + const unsigned char *mac) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100 *ftgmac100 = priv->iobase; unsigned int maddr = mac[0] << 8 | mac[1]; unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; @@ -341,61 +259,42 @@ static void ftgmac100_set_mac(struct eth_device *dev, writel(maddr, &ftgmac100->mac_madr); writel(laddr, &ftgmac100->mac_ladr); -} -static void ftgmac100_set_mac_from_env(struct eth_device *dev) -{ - eth_env_get_enetaddr("ethaddr", dev->enetaddr); - - ftgmac100_set_mac(dev, dev->enetaddr); + return 0; } /* * disable transmitter, receiver */ -static void ftgmac100_halt(struct eth_device *dev) +static void ftgmac100_stop(struct udevice *dev) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; debug("%s()\n", __func__); writel(0, &ftgmac100->maccr); + + phy_shutdown(priv->phydev); } -static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +static int ftgmac100_start(struct udevice *dev) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; - struct ftgmac100_txdes *txdes; - struct ftgmac100_rxdes *rxdes; + struct eth_pdata *plat = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; + struct phy_device *phydev = priv->phydev; unsigned int maccr; - void *buf; + ulong start, end; + int ret; int i; debug("%s()\n", __func__); - if (!priv->txdes) { - txdes = dma_alloc_coherent( - sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma); - if (!txdes) - panic("ftgmac100: out of memory\n"); - memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX); - priv->txdes = txdes; - } - txdes = priv->txdes; - - if (!priv->rxdes) { - rxdes = dma_alloc_coherent( - sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma); - if (!rxdes) - panic("ftgmac100: out of memory\n"); - memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX); - priv->rxdes = rxdes; - } - rxdes = priv->rxdes; + ftgmac100_reset(priv); /* set the ethernet address */ - ftgmac100_set_mac_from_env(dev); + ftgmac100_set_mac(priv, plat->enetaddr); /* disable all interrupts */ writel(0, &ftgmac100->ier); @@ -404,42 +303,37 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd) priv->tx_index = 0; priv->rx_index = 0; - txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; - rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; - for (i = 0; i < PKTBUFSTX; i++) { - /* TXBUF_BADR */ - if (!txdes[i].txdes2) { - buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); - if (!buf) - panic("ftgmac100: out of memory\n"); - txdes[i].txdes3 = virt_to_phys(buf); - txdes[i].txdes2 = (uint)buf; - } - txdes[i].txdes1 = 0; + priv->txdes[i].txdes3 = 0; + priv->txdes[i].txdes0 = 0; } + priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask; + + start = (ulong)&priv->txdes[0]; + end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); for (i = 0; i < PKTBUFSRX; i++) { - /* RXBUF_BADR */ - if (!rxdes[i].rxdes2) { - buf = net_rx_packets[i]; - rxdes[i].rxdes3 = virt_to_phys(buf); - rxdes[i].rxdes2 = (uint)buf; - } - rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; + priv->rxdes[i].rxdes0 = 0; } + priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; + + start = (ulong)&priv->rxdes[0]; + end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); /* transmit ring */ - writel(priv->txdes_dma, &ftgmac100->txr_badr); + writel((u32)priv->txdes, &ftgmac100->txr_badr); /* receive ring */ - writel(priv->rxdes_dma, &ftgmac100->rxr_badr); + writel((u32)priv->rxdes, &ftgmac100->rxr_badr); /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); /* config receive buffer size register */ - writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr); /* enable transmitter, receiver */ maccr = FTGMAC100_MACCR_TXMAC_EN | @@ -453,34 +347,67 @@ static int ftgmac100_init(struct eth_device *dev, bd_t *bd) writel(maccr, &ftgmac100->maccr); - if (!ftgmac100_phy_init(dev)) { - if (!ftgmac100_update_link_speed(dev)) - return -1; + ret = phy_startup(phydev); + if (ret) { + dev_err(phydev->dev, "Could not start PHY\n"); + return ret; } + ret = ftgmac100_phy_adjust_link(priv); + if (ret) { + dev_err(phydev->dev, "Could not adjust link\n"); + return ret; + } + + printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name, + phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr); + + return 0; +} + +static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + + /* Release buffer to DMA and flush descriptor */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + flush_dcache_range(des_start, des_end); + + /* Move to next descriptor */ + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + return 0; } /* * Get a data block via Ethernet */ -static int ftgmac100_recv(struct eth_device *dev) +static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) { - struct ftgmac100_data *priv = dev->priv; - struct ftgmac100_rxdes *curr_des; + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; unsigned short rxlen; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + ulong data_start = curr_des->rxdes3; + ulong data_end; - curr_des = &priv->rxdes[priv->rx_index]; + invalidate_dcache_range(des_start, des_end); if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) - return -1; + return -EAGAIN; if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | FTGMAC100_RXDES0_CRC_ERR | FTGMAC100_RXDES0_FTL | FTGMAC100_RXDES0_RUNT | FTGMAC100_RXDES0_RX_ODD_NB)) { - return -1; + return -EAGAIN; } rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); @@ -488,95 +415,194 @@ static int ftgmac100_recv(struct eth_device *dev) debug("%s(): RX buffer %d, %x received\n", __func__, priv->rx_index, rxlen); - /* invalidate d-cache */ - dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE); + /* Invalidate received data */ + data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + *packetp = (uchar *)data_start; - /* pass the packet up to the protocol layers. */ - net_process_received_packet((void *)curr_des->rxdes2, rxlen); - - /* release buffer to DMA */ - curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; - - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; - - return 0; + return rxlen; } +static u32 ftgmac100_read_txdesc(const void *desc) +{ + const struct ftgmac100_txdes *txdes = desc; + ulong des_start = (ulong)txdes; + ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(des_start, des_end); + + return txdes->txdes0; +} + +BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc) + /* * Send a data block via Ethernet */ -static int ftgmac100_send(struct eth_device *dev, void *packet, int length) +static int ftgmac100_send(struct udevice *dev, void *packet, int length) { - struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; - struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_data *priv = dev_get_priv(dev); + struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + ulong des_start = (ulong)curr_des; + ulong des_end = des_start + + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + ulong data_start; + ulong data_end; + int rc; + + invalidate_dcache_range(des_start, des_end); if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { - debug("%s(): no TX descriptor available\n", __func__); - return -1; + dev_err(dev, "no TX descriptor available\n"); + return -EPERM; } debug("%s(%x, %x)\n", __func__, (int)packet, length); length = (length < ETH_ZLEN) ? ETH_ZLEN : length; - memcpy((void *)curr_des->txdes2, (void *)packet, length); - dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE); + curr_des->txdes3 = (unsigned int)packet; - /* only one descriptor on TXBUF */ - curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + /* Flush data to be sent */ + data_start = curr_des->txdes3; + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + flush_dcache_range(data_start, data_end); + + /* Only one segment on TXBUF */ + curr_des->txdes0 &= priv->txdes0_edotr_mask; curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | FTGMAC100_TXDES0_LTS | FTGMAC100_TXDES0_TXBUF_SIZE(length) | FTGMAC100_TXDES0_TXDMA_OWN ; - /* start transmit */ + /* Flush modified buffer descriptor */ + flush_dcache_range(des_start, des_end); + + /* Start transmit */ writel(1, &ftgmac100->txpd); + rc = wait_for_bit_ftgmac100_txdone(curr_des, + FTGMAC100_TXDES0_TXDMA_OWN, false, + FTGMAC100_TX_TIMEOUT_MS, true); + if (rc) + return rc; + debug("%s(): packet sent\n", __func__); + /* Move to next descriptor */ priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; return 0; } -int ftgmac100_initialize(bd_t *bd) +static int ftgmac100_write_hwaddr(struct udevice *dev) { - struct eth_device *dev; - struct ftgmac100_data *priv; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); - dev = malloc(sizeof *dev); - if (!dev) { - printf("%s(): failed to allocate dev\n", __func__); + return ftgmac100_set_mac(priv, pdata->enetaddr); +} + +static int ftgmac100_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = devfdt_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = dev_read_string(dev, "phy-mode"); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); + return -EINVAL; + } + + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { + priv->rxdes0_edorr_mask = BIT(30); + priv->txdes0_edotr_mask = BIT(30); + } else { + priv->rxdes0_edorr_mask = BIT(15); + priv->txdes0_edotr_mask = BIT(15); + } + + return clk_get_bulk(dev, &priv->clks); +} + +static int ftgmac100_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ftgmac100_data *priv = dev_get_priv(dev); + int ret; + + priv->iobase = (struct ftgmac100 *)pdata->iobase; + priv->phy_mode = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + priv->phy_addr = 0; + + ret = clk_enable_bulk(&priv->clks); + if (ret) + goto out; + + ret = ftgmac100_mdio_init(dev); + if (ret) { + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); goto out; } - /* Transmit and receive descriptors should align to 16 bytes */ - priv = memalign(16, sizeof(struct ftgmac100_data)); - if (!priv) { - printf("%s(): failed to allocate priv\n", __func__); - goto free_dev; + ret = ftgmac100_phy_init(dev); + if (ret) { + dev_err(dev, "Failed to initialize PHY: %d\n", ret); + goto out; } - memset(dev, 0, sizeof(*dev)); - memset(priv, 0, sizeof(*priv)); - - strcpy(dev->name, "FTGMAC100"); - dev->iobase = CONFIG_FTGMAC100_BASE; - dev->init = ftgmac100_init; - dev->halt = ftgmac100_halt; - dev->send = ftgmac100_send; - dev->recv = ftgmac100_recv; - dev->priv = priv; - - eth_register(dev); - - ftgmac100_reset(dev); - - return 1; - -free_dev: - free(dev); out: + if (ret) + clk_release_bulk(&priv->clks); + + return ret; +} + +static int ftgmac100_remove(struct udevice *dev) +{ + struct ftgmac100_data *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + clk_release_bulk(&priv->clks); + return 0; } + +static const struct eth_ops ftgmac100_ops = { + .start = ftgmac100_start, + .send = ftgmac100_send, + .recv = ftgmac100_recv, + .stop = ftgmac100_stop, + .free_pkt = ftgmac100_free_pkt, + .write_hwaddr = ftgmac100_write_hwaddr, +}; + +static const struct udevice_id ftgmac100_ids[] = { + { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, + { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, + { } +}; + +U_BOOT_DRIVER(ftgmac100) = { + .name = "ftgmac100", + .id = UCLASS_ETH, + .of_match = ftgmac100_ids, + .ofdata_to_platdata = ftgmac100_ofdata_to_platdata, + .probe = ftgmac100_probe, + .remove = ftgmac100_remove, + .ops = &ftgmac100_ops, + .priv_auto_alloc_size = sizeof(struct ftgmac100_data), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index ffbe1f3e3f..9a789e4d5b 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -70,48 +70,48 @@ struct ftgmac100 { /* * Interrupt status register & interrupt enable register */ -#define FTGMAC100_INT_RPKT_BUF (1 << 0) -#define FTGMAC100_INT_RPKT_FIFO (1 << 1) -#define FTGMAC100_INT_NO_RXBUF (1 << 2) -#define FTGMAC100_INT_RPKT_LOST (1 << 3) -#define FTGMAC100_INT_XPKT_ETH (1 << 4) -#define FTGMAC100_INT_XPKT_FIFO (1 << 5) -#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) -#define FTGMAC100_INT_XPKT_LOST (1 << 7) -#define FTGMAC100_INT_AHB_ERR (1 << 8) -#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) -#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) +#define FTGMAC100_INT_RPKT_BUF BIT(0) +#define FTGMAC100_INT_RPKT_FIFO BIT(1) +#define FTGMAC100_INT_NO_RXBUF BIT(2) +#define FTGMAC100_INT_RPKT_LOST BIT(3) +#define FTGMAC100_INT_XPKT_ETH BIT(4) +#define FTGMAC100_INT_XPKT_FIFO BIT(5) +#define FTGMAC100_INT_NO_NPTXBUF BIT(6) +#define FTGMAC100_INT_XPKT_LOST BIT(7) +#define FTGMAC100_INT_AHB_ERR BIT(8) +#define FTGMAC100_INT_PHYSTS_CHG BIT(9) +#define FTGMAC100_INT_NO_HPTXBUF BIT(10) /* * Interrupt timer control register */ #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) -#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) -#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) +#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) /* * Automatic polling timer control register */ #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) -#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) -#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) /* * DMA burst length and arbitration control register */ #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) -#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RX_THR_EN BIT(6) #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) -#define FTGMAC100_DBLAC_IFG_INC (1 << 23) +#define FTGMAC100_DBLAC_IFG_INC BIT(23) /* * DMA FIFO status register @@ -122,12 +122,12 @@ struct ftgmac100 { #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) -#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) -#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) -#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) -#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) -#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) -#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) /* * Receive buffer size register @@ -137,26 +137,26 @@ struct ftgmac100 { /* * MAC control register */ -#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) -#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) -#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) -#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) -#define FTGMAC100_MACCR_RM_VLAN (1 << 4) -#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) -#define FTGMAC100_MACCR_LOOP_EN (1 << 6) -#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) -#define FTGMAC100_MACCR_FULLDUP (1 << 8) -#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) -#define FTGMAC100_MACCR_CRC_APD (1 << 10) -#define FTGMAC100_MACCR_RX_RUNT (1 << 12) -#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) -#define FTGMAC100_MACCR_RX_ALL (1 << 14) -#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) -#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) -#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) -#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) -#define FTGMAC100_MACCR_FAST_MODE (1 << 19) -#define FTGMAC100_MACCR_SW_RST (1 << 31) +#define FTGMAC100_MACCR_TXDMA_EN BIT(0) +#define FTGMAC100_MACCR_RXDMA_EN BIT(1) +#define FTGMAC100_MACCR_TXMAC_EN BIT(2) +#define FTGMAC100_MACCR_RXMAC_EN BIT(3) +#define FTGMAC100_MACCR_RM_VLAN BIT(4) +#define FTGMAC100_MACCR_HPTXR_EN BIT(5) +#define FTGMAC100_MACCR_LOOP_EN BIT(6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) +#define FTGMAC100_MACCR_FULLDUP BIT(8) +#define FTGMAC100_MACCR_GIGA_MODE BIT(9) +#define FTGMAC100_MACCR_CRC_APD BIT(10) +#define FTGMAC100_MACCR_RX_RUNT BIT(12) +#define FTGMAC100_MACCR_JUMBO_LF BIT(13) +#define FTGMAC100_MACCR_RX_ALL BIT(14) +#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) +#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) +#define FTGMAC100_MACCR_RX_BROADPKT BIT(17) +#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) +#define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_SW_RST BIT(31) /* * PHY control register @@ -165,8 +165,8 @@ struct ftgmac100 { #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) -#define FTGMAC100_PHYCR_MIIRD (1 << 26) -#define FTGMAC100_PHYCR_MIIWR (1 << 27) +#define FTGMAC100_PHYCR_MIIRD BIT(26) +#define FTGMAC100_PHYCR_MIIWR BIT(27) /* * PHY data register @@ -182,23 +182,23 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __attribute__ ((aligned(16))); +} __aligned(16); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) -#define FTGMAC100_TXDES0_EDOTR (1 << 15) -#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_TXDES0_LTS (1 << 28) -#define FTGMAC100_TXDES0_FTS (1 << 29) -#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) +#define FTGMAC100_TXDES0_EDOTR BIT(15) +#define FTGMAC100_TXDES0_CRC_ERR BIT(19) +#define FTGMAC100_TXDES0_LTS BIT(28) +#define FTGMAC100_TXDES0_FTS BIT(29) +#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) -#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) -#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) -#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) -#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) -#define FTGMAC100_TXDES1_LLC (1 << 22) -#define FTGMAC100_TXDES1_TX2FIC (1 << 30) -#define FTGMAC100_TXDES1_TXIC (1 << 31) +#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) +#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) +#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) +#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) +#define FTGMAC100_TXDES1_LLC BIT(22) +#define FTGMAC100_TXDES1_TX2FIC BIT(30) +#define FTGMAC100_TXDES1_TXIC BIT(31) /* * Receive descriptor, aligned to 16 bytes @@ -208,23 +208,23 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __attribute__ ((aligned(16))); +} __aligned(16); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) -#define FTGMAC100_RXDES0_EDORR (1 << 15) -#define FTGMAC100_RXDES0_MULTICAST (1 << 16) -#define FTGMAC100_RXDES0_BROADCAST (1 << 17) -#define FTGMAC100_RXDES0_RX_ERR (1 << 18) -#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) -#define FTGMAC100_RXDES0_FTL (1 << 20) -#define FTGMAC100_RXDES0_RUNT (1 << 21) -#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) -#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) -#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) -#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) -#define FTGMAC100_RXDES0_LRS (1 << 28) -#define FTGMAC100_RXDES0_FRS (1 << 29) -#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) +#define FTGMAC100_RXDES0_EDORR BIT(15) +#define FTGMAC100_RXDES0_MULTICAST BIT(16) +#define FTGMAC100_RXDES0_BROADCAST BIT(17) +#define FTGMAC100_RXDES0_RX_ERR BIT(18) +#define FTGMAC100_RXDES0_CRC_ERR BIT(19) +#define FTGMAC100_RXDES0_FTL BIT(20) +#define FTGMAC100_RXDES0_RUNT BIT(21) +#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) +#define FTGMAC100_RXDES0_FIFO_FULL BIT(23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) +#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) +#define FTGMAC100_RXDES0_LRS BIT(28) +#define FTGMAC100_RXDES0_FRS BIT(29) +#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) @@ -232,11 +232,11 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) -#define FTGMAC100_RXDES1_LLC (1 << 22) -#define FTGMAC100_RXDES1_DF (1 << 23) -#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) -#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) -#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) -#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +#define FTGMAC100_RXDES1_LLC BIT(22) +#define FTGMAC100_RXDES1_DF BIT(23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) #endif /* __FTGMAC100_H */ diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4faed..1d85b2cfa8 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2015-2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000000..7dd46c04f6 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include +#include +#include +#include +#include +#include + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c new file mode 100644 index 0000000000..7833b2f47a --- /dev/null +++ b/drivers/net/mt7628-eth.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MediaTek ethernet IP driver for U-Boot + * + * Copyright (C) 2018 Stefan Roese + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System controller register */ +#define MT7628_RSTCTRL_REG 0x34 +#define RSTCTRL_EPHY_RST BIT(24) + +#define MT7628_AGPIO_CFG_REG 0x3c +#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) +#define MT7628_EPHY_P0_DIS BIT(16) + +#define MT7628_GPIO2_MODE_REG 0x64 + +/* Ethernet frame engine register */ +#define PDMA_RELATED 0x0800 + +#define TX_BASE_PTR0 (PDMA_RELATED + 0x000) +#define TX_MAX_CNT0 (PDMA_RELATED + 0x004) +#define TX_CTX_IDX0 (PDMA_RELATED + 0x008) +#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c) + +#define RX_BASE_PTR0 (PDMA_RELATED + 0x100) +#define RX_MAX_CNT0 (PDMA_RELATED + 0x104) +#define RX_CALC_IDX0 (PDMA_RELATED + 0x108) + +#define PDMA_GLO_CFG (PDMA_RELATED + 0x204) +#define PDMA_RST_IDX (PDMA_RELATED + 0x208) +#define DLY_INT_CFG (PDMA_RELATED + 0x20c) + +#define SDM_RELATED 0x0c00 + +#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */ +#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */ + +#define RST_DTX_IDX0 BIT(0) +#define RST_DRX_IDX0 BIT(16) + +#define TX_DMA_EN BIT(0) +#define TX_DMA_BUSY BIT(1) +#define RX_DMA_EN BIT(2) +#define RX_DMA_BUSY BIT(3) +#define TX_WB_DDONE BIT(6) + +/* Ethernet switch register */ +#define MT7628_SWITCH_FCT0 0x0008 +#define MT7628_SWITCH_PFC1 0x0014 +#define MT7628_SWITCH_FPA 0x0084 +#define MT7628_SWITCH_SOCPC 0x008c +#define MT7628_SWITCH_POC0 0x0090 +#define MT7628_SWITCH_POC2 0x0098 +#define MT7628_SWITCH_SGC 0x009c +#define MT7628_SWITCH_PCR0 0x00c0 +#define PCR0_PHY_ADDR GENMASK(4, 0) +#define PCR0_PHY_REG GENMASK(12, 8) +#define PCR0_WT_PHY_CMD BIT(13) +#define PCR0_RD_PHY_CMD BIT(14) +#define PCR0_WT_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_PCR1 0x00c4 +#define PCR1_WT_DONE BIT(0) +#define PCR1_RD_RDY BIT(1) +#define PCR1_RD_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_FPA1 0x00c8 +#define MT7628_SWITCH_FCT2 0x00cc +#define MT7628_SWITCH_SGC2 0x00e4 +#define MT7628_SWITCH_BMU_CTRL 0x0110 + +/* rxd2 */ +#define RX_DMA_DONE BIT(31) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_PLEN0 GENMASK(29, 16) +#define RX_DMA_TAG BIT(15) + +struct fe_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_PLEN0 GENMASK(29, 16) +#define TX_DMA_LS1 BIT(14) +#define TX_DMA_LS0 BIT(30) +#define TX_DMA_DONE BIT(31) + +#define TX_DMA_INS_VLAN_MT7621 BIT(16) +#define TX_DMA_INS_VLAN BIT(7) +#define TX_DMA_INS_PPPOE BIT(12) +#define TX_DMA_PN GENMASK(26, 24) + +struct fe_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 4 + +#define PADDING_LENGTH 60 + +#define MTK_QDMA_PAGE_SIZE 2048 + +#define CONFIG_MDIO_TIMEOUT 100 +#define CONFIG_DMA_STOP_TIMEOUT 100 +#define CONFIG_TX_DMA_TIMEOUT 100 + +#define LINK_DELAY_TIME 500 /* 500 ms */ +#define LINK_TIMEOUT 10000 /* 10 seconds */ + +struct mt7628_eth_dev { + void __iomem *base; /* frame engine base address */ + void __iomem *eth_sw_base; /* switch base address */ + struct regmap *sysctrl_regmap; /* system-controller reg-map */ + + struct mii_dev *bus; + + struct fe_tx_dma *tx_ring; + struct fe_rx_dma *rx_ring; + + u8 *rx_buf[NUM_RX_DESC]; + + /* Point to the next RXD DMA wants to use in RXD Ring0 */ + int rx_dma_idx; + /* Point to the next TXD in TXD Ring0 CPU wants to use */ + int tx_dma_idx; +}; + +static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) +{ + void __iomem *base = priv->eth_sw_base; + int ret; + + ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set, + CONFIG_MDIO_TIMEOUT, false); + if (ret) { + printf("MDIO operation timeout!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mii_mgr_read(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 *read_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 status = 0; + u32 ret; + + *read_data = 0xffff; + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, false); + if (ret) + return ret; + + writel(PCR0_RD_PHY_CMD | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr), + base + MT7628_SWITCH_PCR0); + + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, true); + if (ret) + return ret; + + status = readl(base + MT7628_SWITCH_PCR1); + *read_data = FIELD_GET(PCR1_RD_DATA, status); + + return 0; +} + +static int mii_mgr_write(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 write_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 data; + int ret; + + /* Make sure previous write operation is complete */ + ret = mdio_wait_read(priv, PCR1_WT_DONE, false); + if (ret) + return ret; + + data = FIELD_PREP(PCR0_WT_DATA, write_data) | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr) | + PCR0_WT_PHY_CMD; + writel(data, base + MT7628_SWITCH_PCR0); + + return mdio_wait_read(priv, PCR1_WT_DONE, true); +} + +static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + u32 val; + int ret; + + ret = mii_mgr_read(bus->priv, addr, reg, &val); + if (ret) + return ret; + + return val; +} + +static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + return mii_mgr_write(bus->priv, addr, reg, value); +} + +static void mt7628_ephy_init(struct mt7628_eth_dev *priv) +{ + int i; + + mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */ + mii_mgr_write(priv, 0, 26, 0x0000); + + for (i = 0; i < 5; i++) { + mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */ + mii_mgr_write(priv, i, 0, 0x3100); + + /* EEE disable */ + mii_mgr_write(priv, i, 30, 0xa000); + mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */ + mii_mgr_write(priv, i, 16, 0x0606); + mii_mgr_write(priv, i, 23, 0x0f0e); + mii_mgr_write(priv, i, 24, 0x1610); + mii_mgr_write(priv, i, 30, 0x1f15); + mii_mgr_write(priv, i, 28, 0x6111); + } + + /* 100Base AOI setting */ + mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */ + mii_mgr_write(priv, 0, 19, 0x004a); + mii_mgr_write(priv, 0, 20, 0x015a); + mii_mgr_write(priv, 0, 21, 0x00ee); + mii_mgr_write(priv, 0, 22, 0x0033); + mii_mgr_write(priv, 0, 23, 0x020a); + mii_mgr_write(priv, 0, 24, 0x0000); + mii_mgr_write(priv, 0, 25, 0x024a); + mii_mgr_write(priv, 0, 26, 0x035a); + mii_mgr_write(priv, 0, 27, 0x02ee); + mii_mgr_write(priv, 0, 28, 0x0233); + mii_mgr_write(priv, 0, 29, 0x000a); + mii_mgr_write(priv, 0, 30, 0x0000); + + /* Fix EPHY idle state abnormal behavior */ + mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */ + mii_mgr_write(priv, 0, 29, 0x000d); + mii_mgr_write(priv, 0, 30, 0x0500); +} + +static void rt305x_esw_init(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->eth_sw_base; + + /* + * FC_RLS_TH=200, FC_SET_TH=160 + * DROP_RLS=120, DROP_SET_TH=80 + */ + writel(0xc8a07850, base + MT7628_SWITCH_FCT0); + writel(0x00000000, base + MT7628_SWITCH_SGC2); + writel(0x00405555, base + MT7628_SWITCH_PFC1); + writel(0x00007f7f, base + MT7628_SWITCH_POC0); + writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */ + writel(0x0002500c, base + MT7628_SWITCH_FCT2); + /* hashing algorithm=XOR48, aging interval=300sec */ + writel(0x0008a301, base + MT7628_SWITCH_SGC); + writel(0x02404040, base + MT7628_SWITCH_SOCPC); + + /* Ext PHY Addr=0x1f */ + writel(0x3f502b28, base + MT7628_SWITCH_FPA1); + writel(0x00000000, base + MT7628_SWITCH_FPA); + /* 1us cycle number=125 (FE's clock=125Mhz) */ + writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL); + + /* Configure analog GPIO setup */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG, + MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + + /* Reset PHY */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + 0, RSTCTRL_EPHY_RST); + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + RSTCTRL_EPHY_RST, 0); + mdelay(10); + + /* Set P0 EPHY LED mode */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG, + 0x0ffc0ffc, 0x05540554); + mdelay(10); + + mt7628_ephy_init(priv); +} + +static void eth_dma_start(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + + setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +} + +static void eth_dma_stop(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + int ret; + + clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); + + /* Wait for DMA to stop */ + ret = wait_for_bit_le32(base + PDMA_GLO_CFG, + RX_DMA_BUSY | TX_DMA_BUSY, false, + CONFIG_DMA_STOP_TIMEOUT, false); + if (ret) + printf("DMA stop timeout error!\n"); +} + +static int mt7628_eth_write_hwaddr(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr; + u32 val; + + /* Set MAC address. */ + val = addr[0]; + val = (val << 8) | addr[1]; + writel(val, base + SDM_MAC_ADRH); + + val = addr[2]; + val = (val << 8) | addr[3]; + val = (val << 8) | addr[4]; + val = (val << 8) | addr[5]; + writel(val, base + SDM_MAC_ADRL); + + return 0; +} + +static int mt7628_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int ret; + int idx; + int i; + + idx = priv->tx_dma_idx; + + /* Pad message to a minimum length */ + if (length < PADDING_LENGTH) { + char *p = (char *)packet; + + for (i = 0; i < PADDING_LENGTH - length; i++) + p[length + i] = 0; + length = PADDING_LENGTH; + } + + /* Check if buffer is ready for next TX DMA */ + ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, + CONFIG_TX_DMA_TIMEOUT, false); + if (ret) { + printf("TX: DMA still busy on buffer %d\n", idx); + return ret; + } + + flush_dcache_range((u32)packet, (u32)packet + length); + + priv->tx_ring[idx].txd1 = CPHYSADDR(packet); + priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0; + priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length); + priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; + + idx = (idx + 1) % NUM_TX_DESC; + + /* Make sure the writes executed at this place */ + wmb(); + writel(idx, base + TX_CTX_IDX0); + + priv->tx_dma_idx = idx; + + return 0; +} + +static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + u32 rxd_info; + int length; + int idx; + + idx = priv->rx_dma_idx; + + rxd_info = priv->rx_ring[idx].rxd2; + if ((rxd_info & RX_DMA_DONE) == 0) + return -EAGAIN; + + length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2); + if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { + printf("%s: invalid length (%d bytes)\n", __func__, length); + return -EIO; + } + + *packetp = priv->rx_buf[idx]; + invalidate_dcache_range((u32)*packetp, (u32)*packetp + length); + + priv->rx_ring[idx].rxd4 = 0; + priv->rx_ring[idx].rxd2 = RX_DMA_LSO; + + /* Make sure the writes executed at this place */ + wmb(); + + return length; +} + +static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int idx; + + idx = priv->rx_dma_idx; + + /* Move point to next RXD which wants to alloc */ + writel(idx, base + RX_CALC_IDX0); + + /* Update to Next packet point that was received */ + idx = (idx + 1) % NUM_RX_DESC; + + priv->rx_dma_idx = idx; + + return 0; +} + +static int phy_link_up(struct mt7628_eth_dev *priv) +{ + u32 val; + + mii_mgr_read(priv, 0x00, MII_BMSR, &val); + return !!(val & BMSR_LSTATUS); +} + +static int mt7628_eth_start(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + uchar packet[MTK_QDMA_PAGE_SIZE]; + uchar *packetp; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0])); + priv->rx_ring[i].rxd2 |= RX_DMA_LSO; + priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); + priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; + priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1); + } + + priv->rx_dma_idx = 0; + priv->tx_dma_idx = 0; + + /* Make sure the writes executed at this place */ + wmb(); + + /* disable delay interrupt */ + writel(0, base + DLY_INT_CFG); + + clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000); + + /* Tell the adapter where the TX/RX rings are located. */ + writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0); + writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); + + writel(NUM_RX_DESC, base + RX_MAX_CNT0); + writel(NUM_TX_DESC, base + TX_MAX_CNT0); + + writel(priv->tx_dma_idx, base + TX_CTX_IDX0); + writel(RST_DTX_IDX0, base + PDMA_RST_IDX); + + writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0); + writel(RST_DRX_IDX0, base + PDMA_RST_IDX); + + /* Make sure the writes executed at this place */ + wmb(); + eth_dma_start(priv); + + /* Check if link is not up yet */ + if (!phy_link_up(priv)) { + /* Wait for link to come up */ + + printf("Waiting for link to come up ."); + for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { + mdelay(LINK_DELAY_TIME); + if (phy_link_up(priv)) { + mdelay(100); /* Ensure all is ready */ + break; + } + + printf("."); + } + + if (phy_link_up(priv)) + printf(" done\n"); + else + printf(" timeout! Trying anyways\n"); + } + + /* + * The integrated switch seems to queue some received ethernet + * packets in some FIFO. Lets read the already queued packets + * out by using the receive routine, so that these old messages + * are dropped before the new xfer starts. + */ + packetp = &packet[0]; + while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN) + mt7628_eth_free_pkt(dev, packetp, 0); + + return 0; +} + +static void mt7628_eth_stop(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + + eth_dma_stop(priv); +} + +static int mt7628_eth_probe(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + struct udevice *syscon; + struct mii_dev *bus; + int ret; + int i; + + /* Save frame-engine base address for later use */ + priv->base = dev_remap_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Save switch base address for later use */ + priv->eth_sw_base = dev_remap_addr_index(dev, 1); + if (IS_ERR(priv->eth_sw_base)) + return PTR_ERR(priv->eth_sw_base); + + /* Get system controller regmap */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "syscon", &syscon); + if (ret) { + pr_err("unable to find syscon device\n"); + return ret; + } + + priv->sysctrl_regmap = syscon_get_regmap(syscon); + if (!priv->sysctrl_regmap) { + pr_err("unable to find regmap\n"); + return -ENODEV; + } + + /* Put rx and tx rings into KSEG1 area (uncached) */ + priv->tx_ring = (struct fe_tx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->tx_ring) * NUM_TX_DESC)); + priv->rx_ring = (struct fe_rx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->rx_ring) * NUM_RX_DESC)); + + for (i = 0; i < NUM_RX_DESC; i++) + priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mt7628_mdio_read; + bus->write = mt7628_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + + ret = mdio_register(bus); + if (ret) + return ret; + + /* Switch configuration */ + rt305x_esw_init(priv); + + return 0; +} + +static const struct eth_ops mt7628_eth_ops = { + .start = mt7628_eth_start, + .send = mt7628_eth_send, + .recv = mt7628_eth_recv, + .free_pkt = mt7628_eth_free_pkt, + .stop = mt7628_eth_stop, + .write_hwaddr = mt7628_eth_write_hwaddr, +}; + +static const struct udevice_id mt7628_eth_ids[] = { + { .compatible = "mediatek,mt7628-eth" }, + { } +}; + +U_BOOT_DRIVER(mt7628_eth) = { + .name = "mt7628_eth", + .id = UCLASS_ETH, + .of_match = mt7628_eth_ids, + .probe = mt7628_eth_probe, + .ops = &mt7628_eth_ops, + .priv_auto_alloc_size = sizeof(struct mt7628_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 37749e0185..a0abb23299 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c index 6f102f134e..72bbda5469 100644 --- a/drivers/net/phy/mscc.c +++ b/drivers/net/phy/mscc.c @@ -11,12 +11,16 @@ #include #include +#include +#include /* Microsemi PHY ID's */ #define PHY_ID_VSC8530 0x00070560 #define PHY_ID_VSC8531 0x00070570 #define PHY_ID_VSC8540 0x00070760 #define PHY_ID_VSC8541 0x00070770 +#define PHY_ID_VSC8574 0x000704a0 +#define PHY_ID_VSC8584 0x000707c0 /* Microsemi VSC85xx PHY Register Pages */ #define MSCC_EXT_PAGE_ACCESS 31 /* Page Access Register */ @@ -29,6 +33,17 @@ #define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */ #define MSCC_PHY_PAGE_TR 0x52B5 /* Token Ring Page registers */ +/* Std Page Register 18 */ +#define MSCC_PHY_BYPASS_CONTROL 18 +#define PARALLEL_DET_IGNORE_ADVERTISED BIT(3) + +/* Std Page Register 22 */ +#define MSCC_PHY_EXT_CNTL_STATUS 22 +#define SMI_BROADCAST_WR_EN BIT(0) + +/* Std Page Register 24 */ +#define MSCC_PHY_EXT_PHY_CNTL_2 24 + /* Std Page Register 28 - PHY AUX Control/Status */ #define MIIM_AUX_CNTRL_STAT_REG 28 #define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004) @@ -47,6 +62,37 @@ #define MAC_IF_SELECTION_RGMII (2) #define MAC_IF_SELECTION_POS (11) #define MAC_IF_SELECTION_WIDTH (2) +#define VSC8584_MAC_IF_SELECTION_MASK BIT(12) +#define VSC8584_MAC_IF_SELECTION_SGMII 0 +#define VSC8584_MAC_IF_SELECTION_1000BASEX 1 +#define VSC8584_MAC_IF_SELECTION_POS 12 +#define MEDIA_OP_MODE_MASK GENMASK(10, 8) +#define MEDIA_OP_MODE_COPPER 0 +#define MEDIA_OP_MODE_SERDES 1 +#define MEDIA_OP_MODE_1000BASEX 2 +#define MEDIA_OP_MODE_100BASEFX 3 +#define MEDIA_OP_MODE_AMS_COPPER_SERDES 5 +#define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6 +#define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7 +#define MEDIA_OP_MODE_POS 8 + +/* Extended Page 1 Register 20E1 */ +#define MSCC_PHY_ACTIPHY_CNTL 20 +#define PHY_ADDR_REVERSED BIT(9) + +/* Extended Page 1 Register 23E1 */ + +#define MSCC_PHY_EXT_PHY_CNTL_4 23 +#define PHY_CNTL_4_ADDR_POS 11 + +/* Extended Page 1 Register 25E1 */ +#define MSCC_PHY_VERIPHY_CNTL_2 25 + +/* Extended Page 1 Register 26E1 */ +#define MSCC_PHY_VERIPHY_CNTL_3 26 + +/* Extended Page 2 Register 16E2 */ +#define MSCC_PHY_CU_PMD_TX_CNTL 16 /* Extended Page 2 Register 20E2 */ #define MSCC_PHY_RGMII_CNTL_REG 20 @@ -72,6 +118,85 @@ #define RMII_CLK_OUT_ENABLE_WIDTH (1) #define RMII_CLK_OUT_ENABLE_MASK (0x10) +/* Extended Page 3 Register 22E3 */ +#define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22 + +/* Extended page GPIO register 00G */ +#define MSCC_DW8051_CNTL_STATUS 0 +#define MICRO_NSOFT_RESET BIT(15) +#define RUN_FROM_INT_ROM BIT(14) +#define AUTOINC_ADDR BIT(13) +#define PATCH_RAM_CLK BIT(12) +#define MICRO_PATCH_EN BIT(7) +#define DW8051_CLK_EN BIT(4) +#define MICRO_CLK_EN BIT(3) +#define MICRO_CLK_DIVIDE(x) ((x) >> 1) +#define MSCC_DW8051_VLD_MASK 0xf1ff + +/* Extended page GPIO register 09G */ +#define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1) +#define MSCC_TRAP_ROM_ADDR_SERDES_INIT 0x3eb7 + +/* Extended page GPIO register 10G */ +#define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2) +#define MSCC_PATCH_RAM_ADDR_SERDES_INIT 0x4012 + +/* Extended page GPIO register 11G */ +#define MSCC_INT_MEM_ADDR 11 + +/* Extended page GPIO register 12G */ +#define MSCC_INT_MEM_CNTL 12 +#define READ_SFR (BIT(14) | BIT(13)) +#define READ_PRAM BIT(14) +#define READ_ROM BIT(13) +#define READ_RAM (0x00 << 13) +#define INT_MEM_WRITE_EN BIT(12) +#define EN_PATCH_RAM_TRAP_ADDR(x) BIT((x) + 7) +#define INT_MEM_DATA_M GENMASK(7, 0) +#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x)) + +/* Extended page GPIO register 18G */ +#define MSCC_PHY_PROC_CMD 18 +#define PROC_CMD_NCOMPLETED BIT(15) +#define PROC_CMD_FAILED BIT(14) +#define PROC_CMD_SGMII_PORT(x) ((x) << 8) +#define PROC_CMD_FIBER_PORT(x) BIT(8 + (x) % 4) +#define PROC_CMD_QSGMII_PORT (BIT(11) | BIT(10)) +#define PROC_CMD_RST_CONF_PORT BIT(7) +#define PROC_CMD_RECONF_PORT (0 << 7) +#define PROC_CMD_READ_MOD_WRITE_PORT BIT(6) +#define PROC_CMD_WRITE BIT(6) +#define PROC_CMD_READ (0 << 6) +#define PROC_CMD_FIBER_DISABLE BIT(5) +#define PROC_CMD_FIBER_100BASE_FX BIT(4) +#define PROC_CMD_FIBER_1000BASE_X (0 << 4) +#define PROC_CMD_SGMII_MAC (BIT(5) | BIT(4)) +#define PROC_CMD_QSGMII_MAC BIT(5) +#define PROC_CMD_NO_MAC_CONF (0x00 << 4) +#define PROC_CMD_1588_DEFAULT_INIT BIT(4) +#define PROC_CMD_NOP GENMASK(3, 0) +#define PROC_CMD_PHY_INIT (BIT(3) | BIT(1)) +#define PROC_CMD_CRC16 BIT(3) +#define PROC_CMD_FIBER_MEDIA_CONF BIT(0) +#define PROC_CMD_MCB_ACCESS_MAC_CONF (0x0000 << 0) +#define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500 + +/* Extended page GPIO register 19G */ +#define MSCC_PHY_MAC_CFG_FASTLINK 19 +#define MAC_CFG_MASK GENMASK(15, 14) +#define MAC_CFG_SGMII (0x00 << 14) +#define MAC_CFG_QSGMII BIT(14) + +/* Test Registers */ +#define MSCC_PHY_TEST_PAGE_5 5 + +#define MSCC_PHY_TEST_PAGE_8 8 +#define TR_CLK_DISABLE BIT(15) + +#define MSCC_PHY_TEST_PAGE_9 9 +#define MSCC_PHY_TEST_PAGE_20 20 +#define MSCC_PHY_TEST_PAGE_24 24 + /* Token Ring Page 0x52B5 Registers */ #define MSCC_PHY_REG_TR_ADDR_16 16 #define MSCC_PHY_REG_TR_DATA_17 17 @@ -110,6 +235,15 @@ #define MSCC_PHY_RESET_TIMEOUT (100) #define MSCC_PHY_MICRO_TIMEOUT (500) +#define VSC8584_REVB 0x0001 +#define MSCC_DEV_REV_MASK GENMASK(3, 0) + +#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000 +#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8 + +#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800 +#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48 + /* RGMII/GMII Clock Delay (Skew) Options */ enum vsc_phy_rgmii_skew { VSC_PHY_RGMII_DELAY_200_PS, VSC_PHY_RGMII_DELAY_800_PS, @@ -133,6 +267,743 @@ vsc_phy_clk_slew { VSC_PHY_CLK_SLEW_RATE_7, }; +struct vsc85xx_priv { + int (*config_pre)(struct phy_device *phydev); +}; + +static void vsc8584_csr_write(struct mii_dev *bus, int phy0, u16 addr, u32 val) +{ + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, + val >> 16); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, + val & GENMASK(15, 0)); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, + MSCC_PHY_TR_16_WRITE | addr); +} + +static int vsc8584_cmd(struct mii_dev *bus, int phy, u16 val) +{ + unsigned long deadline; + u16 reg_val; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, + PROC_CMD_NCOMPLETED | val); + + deadline = timer_get_us() + PROC_CMD_NCOMPLETED_TIMEOUT_MS * 1000; + do { + reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, + MSCC_PHY_PROC_CMD); + } while (timer_get_us() <= deadline && + (reg_val & PROC_CMD_NCOMPLETED) && + !(reg_val & PROC_CMD_FAILED)); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + if (reg_val & PROC_CMD_FAILED) + return -EIO; + if (reg_val & PROC_CMD_NCOMPLETED) + return -ETIMEDOUT; + + return 0; +} + +static int vsc8584_micro_deassert_reset(struct mii_dev *bus, int phy, + bool patch_en) +{ + u32 enable, release; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; + release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | + MICRO_CLK_EN; + + if (patch_en) { + enable |= MICRO_PATCH_EN; + release |= MICRO_PATCH_EN; + + /* Clear all patches */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, + READ_RAM); + } + + /* + * Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock + * override and addr. auto-incr; operate at 125 MHz + */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); + /* Release 8051 Micro SW reset */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return 0; +} + +static int vsc8584_micro_assert_reset(struct mii_dev *bus, int phy) +{ + int ret; + u16 reg; + + ret = vsc8584_cmd(bus, phy, PROC_CMD_NOP); + if (ret) + return ret; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); + reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(4), 0x005b); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(4), 0x005b); + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); + reg |= EN_PATCH_RAM_TRAP_ADDR(4); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); + reg &= ~MICRO_NSOFT_RESET; + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, + PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_SGMII_PORT(0) | + PROC_CMD_NO_MAC_CONF | PROC_CMD_READ); + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); + reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return 0; +} + +static const u8 fw_patch_vsc8574[] = { + 0x46, 0x4a, 0x02, 0x43, 0x37, 0x02, 0x46, 0x26, 0x02, 0x46, 0x77, 0x02, + 0x45, 0x60, 0x02, 0x45, 0xaf, 0xed, 0xff, 0xe5, 0xfc, 0x54, 0x38, 0x64, + 0x20, 0x70, 0x08, 0x65, 0xff, 0x70, 0x04, 0xed, 0x44, 0x80, 0xff, 0x22, + 0x8f, 0x19, 0x7b, 0xbb, 0x7d, 0x0e, 0x7f, 0x04, 0x12, 0x3d, 0xd7, 0xef, + 0x4e, 0x60, 0x03, 0x02, 0x41, 0xf9, 0xe4, 0xf5, 0x1a, 0x74, 0x01, 0x7e, + 0x00, 0xa8, 0x1a, 0x08, 0x80, 0x05, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, + 0xf9, 0xff, 0xef, 0x55, 0x19, 0x70, 0x03, 0x02, 0x41, 0xed, 0x85, 0x1a, + 0xfb, 0x7b, 0xbb, 0xe4, 0xfd, 0xff, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60, + 0x03, 0x02, 0x41, 0xed, 0xe5, 0x1a, 0x54, 0x02, 0x75, 0x1d, 0x00, 0x25, + 0xe0, 0x25, 0xe0, 0xf5, 0x1c, 0xe4, 0x78, 0xc5, 0xf6, 0xd2, 0x0a, 0x12, + 0x41, 0xfa, 0x7b, 0xff, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef, + 0x4e, 0x60, 0x03, 0x02, 0x41, 0xe7, 0xc2, 0x0a, 0x74, 0xc7, 0x25, 0x1a, + 0xf9, 0x74, 0xe7, 0x25, 0x1a, 0xf8, 0xe6, 0x27, 0xf5, 0x1b, 0xe5, 0x1d, + 0x24, 0x5b, 0x12, 0x45, 0xea, 0x12, 0x3e, 0xda, 0x7b, 0xfc, 0x7d, 0x11, + 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0x78, 0xcc, 0xef, 0xf6, 0x78, 0xc1, 0xe6, + 0xfe, 0xef, 0xd3, 0x9e, 0x40, 0x06, 0x78, 0xcc, 0xe6, 0x78, 0xc1, 0xf6, + 0x12, 0x41, 0xfa, 0x7b, 0xec, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7, + 0x78, 0xcb, 0xef, 0xf6, 0xbf, 0x07, 0x06, 0x78, 0xc3, 0x76, 0x1a, 0x80, + 0x1f, 0x78, 0xc5, 0xe6, 0xff, 0x60, 0x0f, 0xc3, 0xe5, 0x1b, 0x9f, 0xff, + 0x78, 0xcb, 0xe6, 0x85, 0x1b, 0xf0, 0xa4, 0x2f, 0x80, 0x07, 0x78, 0xcb, + 0xe6, 0x85, 0x1b, 0xf0, 0xa4, 0x78, 0xc3, 0xf6, 0xe4, 0x78, 0xc2, 0xf6, + 0x78, 0xc2, 0xe6, 0xff, 0xc3, 0x08, 0x96, 0x40, 0x03, 0x02, 0x41, 0xd1, + 0xef, 0x54, 0x03, 0x60, 0x33, 0x14, 0x60, 0x46, 0x24, 0xfe, 0x60, 0x42, + 0x04, 0x70, 0x4b, 0xef, 0x24, 0x02, 0xff, 0xe4, 0x33, 0xfe, 0xef, 0x78, + 0x02, 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0xd8, 0xf8, 0xff, 0xe5, 0x1d, + 0x24, 0x5c, 0xcd, 0xe5, 0x1c, 0x34, 0xf0, 0xcd, 0x2f, 0xff, 0xed, 0x3e, + 0xfe, 0x12, 0x46, 0x0d, 0x7d, 0x11, 0x80, 0x0b, 0x78, 0xc2, 0xe6, 0x70, + 0x04, 0x7d, 0x11, 0x80, 0x02, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3e, 0x9a, + 0x8e, 0x1e, 0x8f, 0x1f, 0x80, 0x03, 0xe5, 0x1e, 0xff, 0x78, 0xc5, 0xe6, + 0x06, 0x24, 0xcd, 0xf8, 0xa6, 0x07, 0x78, 0xc2, 0x06, 0xe6, 0xb4, 0x1a, + 0x0a, 0xe5, 0x1d, 0x24, 0x5c, 0x12, 0x45, 0xea, 0x12, 0x3e, 0xda, 0x78, + 0xc5, 0xe6, 0x65, 0x1b, 0x70, 0x82, 0x75, 0xdb, 0x20, 0x75, 0xdb, 0x28, + 0x12, 0x46, 0x02, 0x12, 0x46, 0x02, 0xe5, 0x1a, 0x12, 0x45, 0xf5, 0xe5, + 0x1a, 0xc3, 0x13, 0x12, 0x45, 0xf5, 0x78, 0xc5, 0x16, 0xe6, 0x24, 0xcd, + 0xf8, 0xe6, 0xff, 0x7e, 0x08, 0x1e, 0xef, 0xa8, 0x06, 0x08, 0x80, 0x02, + 0xc3, 0x13, 0xd8, 0xfc, 0xfd, 0xc4, 0x33, 0x54, 0xe0, 0xf5, 0xdb, 0xef, + 0xa8, 0x06, 0x08, 0x80, 0x02, 0xc3, 0x13, 0xd8, 0xfc, 0xfd, 0xc4, 0x33, + 0x54, 0xe0, 0x44, 0x08, 0xf5, 0xdb, 0xee, 0x70, 0xd8, 0x78, 0xc5, 0xe6, + 0x70, 0xc8, 0x75, 0xdb, 0x10, 0x02, 0x40, 0xfd, 0x78, 0xc2, 0xe6, 0xc3, + 0x94, 0x17, 0x50, 0x0e, 0xe5, 0x1d, 0x24, 0x62, 0x12, 0x42, 0x08, 0xe5, + 0x1d, 0x24, 0x5c, 0x12, 0x42, 0x08, 0x20, 0x0a, 0x03, 0x02, 0x40, 0x76, + 0x05, 0x1a, 0xe5, 0x1a, 0xc3, 0x94, 0x04, 0x50, 0x03, 0x02, 0x40, 0x3a, + 0x22, 0xe5, 0x1d, 0x24, 0x5c, 0xff, 0xe5, 0x1c, 0x34, 0xf0, 0xfe, 0x12, + 0x46, 0x0d, 0x22, 0xff, 0xe5, 0x1c, 0x34, 0xf0, 0xfe, 0x12, 0x46, 0x0d, + 0x22, 0xe4, 0xf5, 0x19, 0x12, 0x46, 0x43, 0x20, 0xe7, 0x1e, 0x7b, 0xfe, + 0x12, 0x42, 0xf9, 0xef, 0xc4, 0x33, 0x33, 0x54, 0xc0, 0xff, 0xc0, 0x07, + 0x7b, 0x54, 0x12, 0x42, 0xf9, 0xd0, 0xe0, 0x4f, 0xff, 0x74, 0x2a, 0x25, + 0x19, 0xf8, 0xa6, 0x07, 0x12, 0x46, 0x43, 0x20, 0xe7, 0x03, 0x02, 0x42, + 0xdf, 0x54, 0x03, 0x64, 0x03, 0x70, 0x03, 0x02, 0x42, 0xcf, 0x7b, 0xcb, + 0x12, 0x43, 0x2c, 0x8f, 0xfb, 0x7b, 0x30, 0x7d, 0x03, 0xe4, 0xff, 0x12, + 0x3d, 0xd7, 0xc3, 0xef, 0x94, 0x02, 0xee, 0x94, 0x00, 0x50, 0x2a, 0x12, + 0x42, 0xec, 0xef, 0x4e, 0x70, 0x23, 0x12, 0x43, 0x04, 0x60, 0x0a, 0x12, + 0x43, 0x12, 0x70, 0x0c, 0x12, 0x43, 0x1f, 0x70, 0x07, 0x12, 0x46, 0x39, + 0x7b, 0x03, 0x80, 0x07, 0x12, 0x46, 0x39, 0x12, 0x46, 0x43, 0xfb, 0x7a, + 0x00, 0x7d, 0x54, 0x80, 0x3e, 0x12, 0x42, 0xec, 0xef, 0x4e, 0x70, 0x24, + 0x12, 0x43, 0x04, 0x60, 0x0a, 0x12, 0x43, 0x12, 0x70, 0x0f, 0x12, 0x43, + 0x1f, 0x70, 0x0a, 0x12, 0x46, 0x39, 0xe4, 0xfb, 0xfa, 0x7d, 0xee, 0x80, + 0x1e, 0x12, 0x46, 0x39, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x80, 0x13, + 0x12, 0x46, 0x39, 0x12, 0x46, 0x43, 0x54, 0x40, 0xfe, 0xc4, 0x13, 0x13, + 0x54, 0x03, 0xfb, 0x7a, 0x00, 0x7d, 0xee, 0x12, 0x38, 0xbd, 0x7b, 0xff, + 0x12, 0x43, 0x2c, 0xef, 0x4e, 0x70, 0x07, 0x74, 0x2a, 0x25, 0x19, 0xf8, + 0xe4, 0xf6, 0x05, 0x19, 0xe5, 0x19, 0xc3, 0x94, 0x02, 0x50, 0x03, 0x02, + 0x42, 0x15, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd, 0x7b, 0x20, 0x7f, 0x04, + 0x12, 0x3d, 0xd7, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd, 0x7f, 0x04, 0x12, + 0x3d, 0xd7, 0x22, 0x7b, 0x22, 0x7d, 0x18, 0x7f, 0x06, 0x12, 0x3d, 0xd7, + 0xef, 0x64, 0x01, 0x4e, 0x22, 0x7d, 0x1c, 0xe4, 0xff, 0x12, 0x3e, 0x9a, + 0xef, 0x54, 0x1b, 0x64, 0x0a, 0x22, 0x7b, 0xcc, 0x7d, 0x10, 0xff, 0x12, + 0x3d, 0xd7, 0xef, 0x64, 0x01, 0x4e, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd, + 0x7f, 0x04, 0x12, 0x3d, 0xd7, 0x22, 0xd2, 0x08, 0x75, 0xfb, 0x03, 0xab, + 0x7e, 0xaa, 0x7d, 0x7d, 0x19, 0x7f, 0x03, 0x12, 0x3e, 0xda, 0xe5, 0x7e, + 0x54, 0x0f, 0x24, 0xf3, 0x60, 0x03, 0x02, 0x43, 0xe9, 0x12, 0x46, 0x5a, + 0x12, 0x46, 0x61, 0xd8, 0xfb, 0xff, 0x20, 0xe2, 0x35, 0x13, 0x92, 0x0c, + 0xef, 0xa2, 0xe1, 0x92, 0x0b, 0x30, 0x0c, 0x2a, 0xe4, 0xf5, 0x10, 0x7b, + 0xfe, 0x12, 0x43, 0xff, 0xef, 0xc4, 0x33, 0x33, 0x54, 0xc0, 0xff, 0xc0, + 0x07, 0x7b, 0x54, 0x12, 0x43, 0xff, 0xd0, 0xe0, 0x4f, 0xff, 0x74, 0x2a, + 0x25, 0x10, 0xf8, 0xa6, 0x07, 0x05, 0x10, 0xe5, 0x10, 0xc3, 0x94, 0x02, + 0x40, 0xd9, 0x12, 0x46, 0x5a, 0x12, 0x46, 0x61, 0xd8, 0xfb, 0x54, 0x05, + 0x64, 0x04, 0x70, 0x27, 0x78, 0xc4, 0xe6, 0x78, 0xc6, 0xf6, 0xe5, 0x7d, + 0xff, 0x33, 0x95, 0xe0, 0xef, 0x54, 0x0f, 0x78, 0xc4, 0xf6, 0x12, 0x44, + 0x0a, 0x20, 0x0c, 0x0c, 0x12, 0x46, 0x5a, 0x12, 0x46, 0x61, 0xd8, 0xfb, + 0x13, 0x92, 0x0d, 0x22, 0xc2, 0x0d, 0x22, 0x12, 0x46, 0x5a, 0x12, 0x46, + 0x61, 0xd8, 0xfb, 0x54, 0x05, 0x64, 0x05, 0x70, 0x1e, 0x78, 0xc4, 0x7d, + 0xb8, 0x12, 0x43, 0xf5, 0x78, 0xc1, 0x7d, 0x74, 0x12, 0x43, 0xf5, 0xe4, + 0x78, 0xc1, 0xf6, 0x22, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x7f, 0x92, + 0x12, 0x38, 0xbd, 0x22, 0xe6, 0xfb, 0x7a, 0x00, 0x7f, 0x92, 0x12, 0x38, + 0xbd, 0x22, 0xe5, 0x10, 0x24, 0x17, 0xfd, 0x7f, 0x04, 0x12, 0x3d, 0xd7, + 0x22, 0x78, 0xc1, 0xe6, 0xfb, 0x7a, 0x00, 0x7d, 0x74, 0x7f, 0x92, 0x12, + 0x38, 0xbd, 0xe4, 0x78, 0xc1, 0xf6, 0xf5, 0x11, 0x74, 0x01, 0x7e, 0x00, + 0xa8, 0x11, 0x08, 0x80, 0x05, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9, + 0xff, 0x78, 0xc4, 0xe6, 0xfd, 0xef, 0x5d, 0x60, 0x44, 0x85, 0x11, 0xfb, + 0xe5, 0x11, 0x54, 0x02, 0x25, 0xe0, 0x25, 0xe0, 0xfe, 0xe4, 0x24, 0x5b, + 0xfb, 0xee, 0x12, 0x45, 0xed, 0x12, 0x3e, 0xda, 0x7b, 0x40, 0x7d, 0x11, + 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0x74, 0xc7, 0x25, 0x11, 0xf8, 0xa6, 0x07, + 0x7b, 0x11, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60, + 0x09, 0x74, 0xe7, 0x25, 0x11, 0xf8, 0x76, 0x04, 0x80, 0x07, 0x74, 0xe7, + 0x25, 0x11, 0xf8, 0x76, 0x0a, 0x05, 0x11, 0xe5, 0x11, 0xc3, 0x94, 0x04, + 0x40, 0x9a, 0x78, 0xc6, 0xe6, 0x70, 0x15, 0x78, 0xc4, 0xe6, 0x60, 0x10, + 0x75, 0xd9, 0x38, 0x75, 0xdb, 0x10, 0x7d, 0xfe, 0x12, 0x44, 0xb8, 0x7d, + 0x76, 0x12, 0x44, 0xb8, 0x79, 0xc6, 0xe7, 0x78, 0xc4, 0x66, 0xff, 0x60, + 0x03, 0x12, 0x40, 0x25, 0x78, 0xc4, 0xe6, 0x70, 0x09, 0xfb, 0xfa, 0x7d, + 0xfe, 0x7f, 0x8e, 0x12, 0x38, 0xbd, 0x22, 0x7b, 0x01, 0x7a, 0x00, 0x7f, + 0x8e, 0x12, 0x38, 0xbd, 0x22, 0xe4, 0xf5, 0xfb, 0x7d, 0x1c, 0xe4, 0xff, + 0x12, 0x3e, 0x9a, 0xad, 0x07, 0xac, 0x06, 0xec, 0x54, 0xc0, 0xff, 0xed, + 0x54, 0x3f, 0x4f, 0xf5, 0x20, 0x30, 0x06, 0x2c, 0x30, 0x01, 0x08, 0xa2, + 0x04, 0x72, 0x03, 0x92, 0x07, 0x80, 0x21, 0x30, 0x04, 0x06, 0x7b, 0xcc, + 0x7d, 0x11, 0x80, 0x0d, 0x30, 0x03, 0x06, 0x7b, 0xcc, 0x7d, 0x10, 0x80, + 0x04, 0x7b, 0x66, 0x7d, 0x16, 0xe4, 0xff, 0x12, 0x3d, 0xd7, 0xee, 0x4f, + 0x24, 0xff, 0x92, 0x07, 0xaf, 0xfb, 0x74, 0x26, 0x2f, 0xf8, 0xe6, 0xff, + 0xa6, 0x20, 0x20, 0x07, 0x39, 0x8f, 0x20, 0x30, 0x07, 0x34, 0x30, 0x00, + 0x31, 0x20, 0x04, 0x2e, 0x20, 0x03, 0x2b, 0xe4, 0xf5, 0xff, 0x75, 0xfc, + 0xc2, 0xe5, 0xfc, 0x30, 0xe0, 0xfb, 0xaf, 0xfe, 0xef, 0x20, 0xe3, 0x1a, + 0xae, 0xfd, 0x44, 0x08, 0xf5, 0xfe, 0x75, 0xfc, 0x80, 0xe5, 0xfc, 0x30, + 0xe0, 0xfb, 0x8f, 0xfe, 0x8e, 0xfd, 0x75, 0xfc, 0x80, 0xe5, 0xfc, 0x30, + 0xe0, 0xfb, 0x05, 0xfb, 0xaf, 0xfb, 0xef, 0xc3, 0x94, 0x04, 0x50, 0x03, + 0x02, 0x44, 0xc5, 0xe4, 0xf5, 0xfb, 0x22, 0xe5, 0x7e, 0x54, 0x0f, 0x64, + 0x01, 0x70, 0x23, 0xe5, 0x7e, 0x30, 0xe4, 0x1e, 0x90, 0x47, 0xd0, 0xe0, + 0x44, 0x02, 0xf0, 0x54, 0xfb, 0xf0, 0x90, 0x47, 0xd4, 0xe0, 0x44, 0x04, + 0xf0, 0x7b, 0x03, 0x7d, 0x5b, 0x7f, 0x5d, 0x12, 0x36, 0x29, 0x7b, 0x0e, + 0x80, 0x1c, 0x90, 0x47, 0xd0, 0xe0, 0x54, 0xfd, 0xf0, 0x44, 0x04, 0xf0, + 0x90, 0x47, 0xd4, 0xe0, 0x54, 0xfb, 0xf0, 0x7b, 0x02, 0x7d, 0x5b, 0x7f, + 0x5d, 0x12, 0x36, 0x29, 0x7b, 0x06, 0x7d, 0x60, 0x7f, 0x63, 0x12, 0x36, + 0x29, 0x22, 0xe5, 0x7e, 0x30, 0xe5, 0x35, 0x30, 0xe4, 0x0b, 0x7b, 0x02, + 0x7d, 0x33, 0x7f, 0x35, 0x12, 0x36, 0x29, 0x80, 0x10, 0x7b, 0x01, 0x7d, + 0x33, 0x7f, 0x35, 0x12, 0x36, 0x29, 0x90, 0x47, 0xd2, 0xe0, 0x44, 0x04, + 0xf0, 0x90, 0x47, 0xd2, 0xe0, 0x54, 0xf7, 0xf0, 0x90, 0x47, 0xd1, 0xe0, + 0x44, 0x10, 0xf0, 0x7b, 0x05, 0x7d, 0x84, 0x7f, 0x86, 0x12, 0x36, 0x29, + 0x22, 0xfb, 0xe5, 0x1c, 0x34, 0xf0, 0xfa, 0x7d, 0x10, 0x7f, 0x07, 0x22, + 0x54, 0x01, 0xc4, 0x33, 0x54, 0xe0, 0xf5, 0xdb, 0x44, 0x08, 0xf5, 0xdb, + 0x22, 0xf5, 0xdb, 0x75, 0xdb, 0x08, 0xf5, 0xdb, 0x75, 0xdb, 0x08, 0x22, + 0xab, 0x07, 0xaa, 0x06, 0x7d, 0x10, 0x7f, 0x07, 0x12, 0x3e, 0xda, 0x7b, + 0xff, 0x7d, 0x10, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60, 0xf3, + 0x22, 0x12, 0x44, 0xc2, 0x30, 0x0c, 0x03, 0x12, 0x42, 0x12, 0x78, 0xc4, + 0xe6, 0xff, 0x60, 0x03, 0x12, 0x40, 0x25, 0x22, 0xe5, 0x19, 0x24, 0x17, + 0x54, 0x1f, 0x44, 0x80, 0xff, 0x22, 0x74, 0x2a, 0x25, 0x19, 0xf8, 0xe6, + 0x22, 0x12, 0x46, 0x72, 0x12, 0x46, 0x68, 0x90, 0x47, 0xfa, 0xe0, 0x54, + 0xf8, 0x44, 0x02, 0xf0, 0x22, 0xe5, 0x7e, 0xae, 0x7d, 0x78, 0x04, 0x22, + 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0x22, 0xe4, 0x78, 0xc4, 0xf6, 0xc2, + 0x0d, 0x78, 0xc1, 0xf6, 0x22, 0xc2, 0x0c, 0xc2, 0x0b, 0x22, 0x22, +}; + +static const u8 fw_patch_vsc8584[] = { + 0xe8, 0x59, 0x02, 0xe8, 0x12, 0x02, 0xe8, 0x42, 0x02, 0xe8, 0x5a, 0x02, + 0xe8, 0x5b, 0x02, 0xe8, 0x5c, 0xe5, 0x69, 0x54, 0x0f, 0x24, 0xf7, 0x60, + 0x27, 0x24, 0xfc, 0x60, 0x23, 0x24, 0x08, 0x70, 0x14, 0xe5, 0x69, 0xae, + 0x68, 0x78, 0x04, 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0xd8, 0xf8, 0x7e, + 0x00, 0x54, 0x0f, 0x80, 0x00, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x7f, + 0x92, 0x12, 0x50, 0xee, 0x22, 0xe4, 0xf5, 0x10, 0x85, 0x10, 0xfb, 0x7d, + 0x1c, 0xe4, 0xff, 0x12, 0x59, 0xea, 0x05, 0x10, 0xe5, 0x10, 0xc3, 0x94, + 0x04, 0x40, 0xed, 0x22, 0x22, 0x22, 0x22, 0x22, +}; + +static int vsc8584_get_fw_crc(struct mii_dev *bus, int phy, u16 start, + u16 *crc, const u8 *fw_patch, int fw_size) +{ + int ret; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT1); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2, start); + /* Add one byte to size for the one added by the patch_fw function */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_3, + fw_size + 1); + + ret = vsc8584_cmd(bus, phy, PROC_CMD_CRC16); + if (ret) + goto out; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT1); + + *crc = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2); + +out: + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return ret; +} + +static int vsc8584_patch_fw(struct mii_dev *bus, int phy, const u8 *fw_patch, + int fw_size) +{ + int i, ret; + + ret = vsc8584_micro_assert_reset(bus, phy); + if (ret) { + pr_err("%s: failed to assert reset of micro\n", __func__); + return ret; + } + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + /* + * Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock + * Disable the 8051 Micro clock + */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, + RUN_FROM_INT_ROM | AUTOINC_ADDR | PATCH_RAM_CLK | + MICRO_CLK_EN | MICRO_CLK_DIVIDE(2)); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_PRAM | + INT_MEM_WRITE_EN | INT_MEM_DATA(2)); + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_ADDR, 0x0000); + + for (i = 0; i < fw_size; i++) + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, + READ_PRAM | INT_MEM_WRITE_EN | fw_patch[i]); + + /* Clear internal memory access */ + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_RAM); + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return 0; +} + +static bool vsc8574_is_serdes_init(struct mii_dev *bus, int phy) +{ + u16 reg; + bool ret; + + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1)); + if (reg != MSCC_TRAP_ROM_ADDR_SERDES_INIT) { + ret = false; + goto out; + } + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1)); + if (reg != MSCC_PATCH_RAM_ADDR_SERDES_INIT) { + ret = false; + goto out; + } + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); + if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { + ret = false; + goto out; + } + + reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); + if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | + MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { + ret = false; + goto out; + } + + ret = true; + +out: + bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + return ret; +} + +static int vsc8574_config_pre_init(struct phy_device *phydev) +{ + struct mii_dev *bus = phydev->bus; + u16 crc, reg, phy0, addr; + bool serdes_init; + int ret; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT1); + addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); + addr >>= PHY_CNTL_4_ADDR_POS; + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL); + if (reg & PHY_ADDR_REVERSED) + phy0 = phydev->addr + addr; + else + phy0 = phydev->addr - addr; + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + /* all writes below are broadcasted to all PHYs in the same package */ + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); + reg |= SMI_BROADCAST_WR_EN; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); + + /* + * The below register writes are tweaking analog and electrical + * configuration that were determined through characterization by PHY + * engineers. These don't mean anything more than "these are the best + * values". + */ + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TEST); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_20, 0x4320); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_24, 0x0c00); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_9, 0x18ca); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1b20); + + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); + reg |= TR_CLK_DISABLE; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TR); + + vsc8584_csr_write(bus, phy0, 0x0fae, 0x000401bd); + vsc8584_csr_write(bus, phy0, 0x0fac, 0x000f000f); + vsc8584_csr_write(bus, phy0, 0x17a0, 0x00a0f147); + vsc8584_csr_write(bus, phy0, 0x0fe4, 0x00052f54); + vsc8584_csr_write(bus, phy0, 0x1792, 0x0027303d); + vsc8584_csr_write(bus, phy0, 0x07fe, 0x00000704); + vsc8584_csr_write(bus, phy0, 0x0fe0, 0x00060150); + vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b00a); + vsc8584_csr_write(bus, phy0, 0x0f80, 0x00000d74); + vsc8584_csr_write(bus, phy0, 0x02e0, 0x00000012); + vsc8584_csr_write(bus, phy0, 0x03a2, 0x00050208); + vsc8584_csr_write(bus, phy0, 0x03b2, 0x00009186); + vsc8584_csr_write(bus, phy0, 0x0fb0, 0x000e3700); + vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81); + vsc8584_csr_write(bus, phy0, 0x0fd2, 0x0000ffff); + vsc8584_csr_write(bus, phy0, 0x168a, 0x00039fa2); + vsc8584_csr_write(bus, phy0, 0x1690, 0x0020640b); + vsc8584_csr_write(bus, phy0, 0x0258, 0x00002220); + vsc8584_csr_write(bus, phy0, 0x025a, 0x00002a20); + vsc8584_csr_write(bus, phy0, 0x025c, 0x00003060); + vsc8584_csr_write(bus, phy0, 0x025e, 0x00003fa0); + vsc8584_csr_write(bus, phy0, 0x03a6, 0x0000e0f0); + vsc8584_csr_write(bus, phy0, 0x0f92, 0x00001489); + vsc8584_csr_write(bus, phy0, 0x16a2, 0x00007000); + vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448); + vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd); + vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c); + vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600); + vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00); + vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000); + vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814); + vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980); + vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0); + vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400); + vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f); + vsc8584_csr_write(bus, phy0, 0x0796, 0x00000003); + vsc8584_csr_write(bus, phy0, 0x07f8, 0x00c3ff98); + vsc8584_csr_write(bus, phy0, 0x0fa4, 0x0018292a); + vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f); + vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620); + vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f); + vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028); + vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901c09); + vsc8584_csr_write(bus, phy0, 0x0fee, 0x0004a6a1); + vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01807); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT2); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TR); + + vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518); + vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696); + vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912); + vsc8584_csr_write(bus, phy0, 0x048e, 0x00000db6); + vsc8584_csr_write(bus, phy0, 0x049c, 0x00596596); + vsc8584_csr_write(bus, phy0, 0x049e, 0x00000514); + vsc8584_csr_write(bus, phy0, 0x04a2, 0x00410280); + vsc8584_csr_write(bus, phy0, 0x04a4, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x04a6, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x04a8, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x04aa, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x04ae, 0x007df7dd); + vsc8584_csr_write(bus, phy0, 0x04b0, 0x006d95d4); + vsc8584_csr_write(bus, phy0, 0x04b2, 0x00492410); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TEST); + + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); + reg &= ~TR_CLK_DISABLE; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + /* end of write broadcasting */ + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); + reg &= ~SMI_BROADCAST_WR_EN; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); + + ret = vsc8584_get_fw_crc(bus, phy0, + MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, &crc, + fw_patch_vsc8574, + ARRAY_SIZE(fw_patch_vsc8574)); + if (ret) + goto out; + + if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { + serdes_init = vsc8574_is_serdes_init(bus, phy0); + + if (!serdes_init) { + ret = vsc8584_micro_assert_reset(bus, phy0); + if (ret) { + pr_err("failed to assert reset of micro\n"); + return ret; + } + } + } else { + pr_debug("FW CRC is not the expected one, patching FW\n"); + + serdes_init = false; + + if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8574, + ARRAY_SIZE(fw_patch_vsc8574))) + pr_warn("failed to patch FW, expect non-optimal device\n"); + } + + if (!serdes_init) { + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1), + MSCC_TRAP_ROM_ADDR_SERDES_INIT); + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1), + MSCC_PATCH_RAM_ADDR_SERDES_INIT); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, + EN_PATCH_RAM_TRAP_ADDR(1)); + + vsc8584_micro_deassert_reset(bus, phy0, false); + + ret = vsc8584_get_fw_crc(bus, phy0, + MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, + &crc, fw_patch_vsc8574, + ARRAY_SIZE(fw_patch_vsc8574)); + if (ret) + goto out; + + if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) + pr_warn("FW CRC after patching is not the expected one, expect non-optimal device\n"); + } + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + ret = vsc8584_cmd(bus, phy0, PROC_CMD_1588_DEFAULT_INIT | + PROC_CMD_PHY_INIT); + +out: + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return ret; +} + +static int vsc8584_config_pre_init(struct phy_device *phydev) +{ + struct mii_dev *bus = phydev->bus; + u16 reg, crc, phy0, addr; + int ret; + + if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { + pr_warn("VSC8584 revA not officially supported, skipping firmware patching. Use at your own risk.\n"); + return 0; + } + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT1); + addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); + addr >>= PHY_CNTL_4_ADDR_POS; + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL); + if (reg & PHY_ADDR_REVERSED) + phy0 = phydev->addr + addr; + else + phy0 = phydev->addr - addr; + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + /* all writes below are broadcasted to all PHYs in the same package */ + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); + reg |= SMI_BROADCAST_WR_EN; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); + + /* + * The below register writes are tweaking analog and electrical + * configuration that were determined through characterization by PHY + * engineers. These don't mean anything more than "these are the best + * values". + */ + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL); + reg |= PARALLEL_DET_IGNORE_ADVERTISED; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT3); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, + 0x2000); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TEST); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1f20); + + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); + reg |= TR_CLK_DISABLE; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TR); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0xafa4); + + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); + reg &= ~0x007f; + reg |= 0x0019; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0x8fa4); + + vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f); + vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81); + vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980); + vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0); + vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400); + vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b002); + vsc8584_csr_write(bus, phy0, 0x1686, 0x00000004); + vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f); + vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620); + vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd); + vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448); + vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f); + vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000); + vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028); + vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c); + vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600); + vsc8584_csr_write(bus, phy0, 0x0f80, 0x00fffaff); + vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901809); + vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01007); + vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00); + vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000); + vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT2); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TR); + + vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518); + vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696); + vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_TEST); + + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); + reg &= ~TR_CLK_DISABLE; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); + + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + /* end of write broadcasting */ + reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); + reg &= ~SMI_BROADCAST_WR_EN; + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); + + ret = vsc8584_get_fw_crc(bus, phy0, + MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, &crc, + fw_patch_vsc8584, + ARRAY_SIZE(fw_patch_vsc8584)); + if (ret) + goto out; + + if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { + debug("FW CRC is not the expected one, patching FW...\n"); + if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8584, + ARRAY_SIZE(fw_patch_vsc8584))) + pr_warn("failed to patch FW, expect non-optimal device\n"); + } + + vsc8584_micro_deassert_reset(bus, phy0, false); + + ret = vsc8584_get_fw_crc(bus, phy0, + MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, &crc, + fw_patch_vsc8584, + ARRAY_SIZE(fw_patch_vsc8584)); + if (ret) + goto out; + + if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) + pr_warn("FW CRC after patching is not the expected one, expect non-optimal device\n"); + + ret = vsc8584_micro_assert_reset(bus, phy0); + if (ret) + goto out; + + vsc8584_micro_deassert_reset(bus, phy0, true); + +out: + bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + + return ret; +} static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev) { @@ -457,6 +1328,108 @@ static int vsc8541_config(struct phy_device *phydev) return genphy_config_aneg(phydev); } +static int vsc8584_config_init(struct phy_device *phydev) +{ + struct vsc85xx_priv *priv = phydev->priv; + int ret; + u16 addr; + u16 reg_val; + u16 val; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_EXT1); + addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); + addr >>= PHY_CNTL_4_ADDR_POS; + + ret = priv->config_pre(phydev); + if (ret) + return ret; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_GPIO); + + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) + val = MAC_CFG_QSGMII; + else + val = MAC_CFG_SGMII; + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_MAC_CFG_FASTLINK); + reg_val &= ~MAC_CFG_MASK; + reg_val |= val; + ret = phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_MAC_CFG_FASTLINK, + reg_val); + if (ret) + return ret; + + reg_val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | + PROC_CMD_READ_MOD_WRITE_PORT; + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) + reg_val |= PROC_CMD_QSGMII_MAC; + else + reg_val |= PROC_CMD_SGMII_MAC; + + ret = vsc8584_cmd(phydev->bus, phydev->addr, reg_val); + if (ret) + return ret; + + mdelay(10); + + /* Disable SerDes for 100Base-FX */ + ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF | + PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | + PROC_CMD_READ_MOD_WRITE_PORT | + PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); + if (ret) + return ret; + + /* Disable SerDes for 1000Base-X */ + ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF | + PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | + PROC_CMD_READ_MOD_WRITE_PORT | + PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); + if (ret) + return ret; + + phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, + MSCC_PHY_PAGE_STD); + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, + MSCC_PHY_EXT_PHY_CNTL_1_REG); + reg_val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); + reg_val |= MEDIA_OP_MODE_COPPER | + (VSC8584_MAC_IF_SELECTION_SGMII << + VSC8584_MAC_IF_SELECTION_POS); + ret = phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG, + reg_val); + + ret = mscc_phy_soft_reset(phydev); + if (ret != 0) + return ret; + + return genphy_config(phydev); +} + +static struct vsc85xx_priv vsc8574_priv = { + .config_pre = vsc8574_config_pre_init, +}; + +static int vsc8574_config(struct phy_device *phydev) +{ + phydev->priv = &vsc8574_priv; + + return vsc8584_config_init(phydev); +} + +static struct vsc85xx_priv vsc8584_priv = { + .config_pre = vsc8584_config_pre_init, +}; + +static int vsc8584_config(struct phy_device *phydev) +{ + phydev->priv = &vsc8584_priv; + + return vsc8584_config_init(phydev); +} + static struct phy_driver VSC8530_driver = { .name = "Microsemi VSC8530", .uid = PHY_ID_VSC8530, @@ -497,12 +1470,34 @@ static struct phy_driver VSC8541_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8574_driver = { + .name = "Microsemi VSC8574", + .uid = PHY_ID_VSC8574, + .mask = 0x000ffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8574_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + +static struct phy_driver VSC8584_driver = { + .name = "Microsemi VSC8584", + .uid = PHY_ID_VSC8584, + .mask = 0x000ffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8584_config, + .startup = &mscc_startup, + .shutdown = &genphy_shutdown, +}; + int phy_mscc_init(void) { phy_register(&VSC8530_driver); phy_register(&VSC8531_driver); phy_register(&VSC8540_driver); phy_register(&VSC8541_driver); + phy_register(&VSC8574_driver); + phy_register(&VSC8584_driver); return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index baa6dd9f9c..25656ca08c 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -659,7 +659,8 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, phy_probe(dev); - bus->phymap[addr] = dev; + if (addr >= 0 && addr < PHY_MAX_ADDR) + bus->phymap[addr] = dev; return dev; } diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index 76d65afe6c..0086f25fc1 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -42,7 +42,7 @@ static int eth_raw_bus_post_bind(struct udevice *dev) device_probe(child); priv = dev_get_priv(child); if (priv) { - memcpy(priv->host_ifname, i->if_name, IFNAMSIZ); + strcpy(priv->host_ifname, i->if_name); priv->host_ifindex = i->if_index; priv->local = local; } diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 3ba3a1ff8b..c9798445c7 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -60,6 +60,10 @@ #define SC_ETCS_MASK GENMASK(1, 0) #define SC_ETCS_EXT_GMII 0x1 #define SC_ETCS_INT_GMII 0x2 +#define SC_ETXDC_MASK GENMASK(12, 10) +#define SC_ETXDC_OFFSET 10 +#define SC_ERXDC_MASK GENMASK(9, 5) +#define SC_ERXDC_OFFSET 5 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) @@ -140,6 +144,8 @@ struct emac_eth_dev { struct sun8i_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + int tx_delay_ps; + int rx_delay_ps; }; @@ -273,7 +279,8 @@ static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) return 0; } -static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) +static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + struct emac_eth_dev *priv) { int ret; u32 reg; @@ -312,6 +319,14 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) return -EINVAL; } + if (pdata->tx_delay_ps) + reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET) + & SC_ETXDC_MASK; + + if (pdata->rx_delay_ps) + reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) + & SC_ERXDC_MASK; + writel(reg, priv->sysctl_reg + 0x30); return 0; @@ -784,13 +799,14 @@ static void sun8i_emac_eth_stop(struct udevice *dev) static int sun8i_emac_eth_probe(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); priv->mac_reg = (void *)pdata->iobase; sun8i_emac_board_setup(priv); - sun8i_emac_set_syscon(priv); + sun8i_emac_set_syscon(sun8i_pdata, priv); sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); @@ -891,6 +907,18 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (!priv->use_internal_phy) parse_phy_pins(dev); + sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,tx-delay-ps", 0); + if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700) + printf("%s: Invalid TX delay value %d\n", __func__, + sun8i_pdata->tx_delay_ps); + + sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,rx-delay-ps", 0); + if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100) + printf("%s: Invalid RX delay value %d\n", __func__, + sun8i_pdata->rx_delay_ps); + #ifdef CONFIG_DM_GPIO if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "snps,reset-active-low")) diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig new file mode 100644 index 0000000000..82bc9f5d03 --- /dev/null +++ b/drivers/net/ti/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + +config DRIVER_TI_CPSW + bool "TI Common Platform Ethernet Switch" + select PHYLIB + help + This driver supports the TI three port switch gigabit ethernet + subsystem found in the TI SoCs. + +config DRIVER_TI_EMAC + bool "TI Davinci EMAC" + help + Support for davinci emac + +config DRIVER_TI_KEYSTONE_NET + bool "TI Keystone 2 Ethernet" + help + This driver supports the TI Keystone 2 Ethernet subsystem diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile new file mode 100644 index 0000000000..ee3e4eb5d6 --- /dev/null +++ b/drivers/net/ti/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o +obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o diff --git a/drivers/net/cpsw-common.c b/drivers/net/ti/cpsw-common.c similarity index 100% rename from drivers/net/cpsw-common.c rename to drivers/net/ti/cpsw-common.c diff --git a/drivers/net/cpsw.c b/drivers/net/ti/cpsw.c similarity index 90% rename from drivers/net/cpsw.c rename to drivers/net/ti/cpsw.c index 8e2a48cfd6..f5fd02efe1 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * CPSW Ethernet Switch Driver * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ */ #include @@ -29,11 +21,11 @@ #include #include +#include "cpsw_mdio.h" + DECLARE_GLOBAL_DATA_PTR; #define BITMASK(bits) (BIT(bits) - 1) -#define PHY_REG_MASK 0x1f -#define PHY_ID_MASK 0x1f #define NUM_DESCS (PKTBUFSRX * 2) #define PKT_MIN 60 #define PKT_MAX (1500 + 14 + 4 + 4) @@ -84,37 +76,8 @@ DECLARE_GLOBAL_DATA_PTR; * unexpected controller lock ups. Ideally, we should never ever hit this * scenario in practice. */ -#define MDIO_TIMEOUT 100 /* msecs */ #define CPDMA_TIMEOUT 100 /* msecs */ -struct cpsw_mdio_regs { - u32 version; - u32 control; -#define CONTROL_IDLE BIT(31) -#define CONTROL_ENABLE BIT(30) - - u32 alive; - u32 link; - u32 linkintraw; - u32 linkintmasked; - u32 __reserved_0[2]; - u32 userintraw; - u32 userintmasked; - u32 userintmaskset; - u32 userintmaskclr; - u32 __reserved_1[20]; - - struct { - u32 access; - u32 physel; -#define USERACCESS_GO BIT(31) -#define USERACCESS_WRITE BIT(30) -#define USERACCESS_ACK BIT(29) -#define USERACCESS_READ (0) -#define USERACCESS_DATA (0xffff) - } user[0]; -}; - struct cpsw_regs { u32 id_ver; u32 control; @@ -492,100 +455,6 @@ static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, __raw_writel(tmp, priv->ale_regs + offset); } -static struct cpsw_mdio_regs *mdio_regs; - -/* wait until hardware is ready for another user access */ -static inline u32 wait_for_user_access(void) -{ - u32 reg = 0; - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) - udelay(10); - - if (timeout == -1) { - printf("wait_for_user_access Timeout\n"); - return -ETIMEDOUT; - } - return reg; -} - -/* wait until hardware state machine is idle */ -static inline void wait_for_idle(void) -{ - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) - udelay(10); - - if (timeout == -1) - printf("wait_for_idle Timeout\n"); -} - -static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, - int dev_addr, int phy_reg) -{ - int data; - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | - (phy_id << 16)); - __raw_writel(reg, &mdio_regs->user[0].access); - reg = wait_for_user_access(); - - data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; - return data; -} - -static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, - int phy_reg, u16 data) -{ - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | - (phy_id << 16) | (data & USERACCESS_DATA)); - __raw_writel(reg, &mdio_regs->user[0].access); - wait_for_user_access(); - - return 0; -} - -static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) -{ - struct mii_dev *bus = mdio_alloc(); - - mdio_regs = (struct cpsw_mdio_regs *)mdio_base; - - /* set enable and clock divider */ - __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); - - /* - * wait for scan logic to settle: - * the scan time consists of (a) a large fixed component, and (b) a - * small component that varies with the mii bus frequency. These - * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x - * silicon. Since the effect of (b) was found to be largely - * negligible, we keep things simple here. - */ - udelay(1000); - - bus->read = cpsw_mdio_read; - bus->write = cpsw_mdio_write; - strcpy(bus->name, name); - - mdio_register(bus); -} - /* Set a self-clearing bit in a register, and wait for it to clear */ static inline void setbit_and_wait_for_clear32(void *addr) { @@ -1011,7 +880,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) static void cpsw_phy_addr_update(struct cpsw_priv *priv) { struct cpsw_platform_data *data = &priv->data; - u16 alive = mdio_regs->alive & GENMASK(15, 0); + u16 alive = cpsw_mdio_get_alive(priv->bus); int active = data->active_slave; int new_addr = ffs(alive) - 1; @@ -1052,11 +921,12 @@ int _cpsw_register(struct cpsw_priv *priv) idx = idx + 1; } - cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); + priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0); + if (!priv->bus) + return -EFAULT; cpsw_phy_addr_update(priv); - priv->bus = miiphy_get_dev_by_name(priv->dev->name); for_active_slave(slave, priv) cpsw_phy_init(priv, slave); diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c new file mode 100644 index 0000000000..70f547e6d7 --- /dev/null +++ b/drivers/net/ti/cpsw_mdio.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include +#include + +struct cpsw_mdio_regs { + u32 version; + u32 control; +#define CONTROL_IDLE BIT(31) +#define CONTROL_ENABLE BIT(30) +#define CONTROL_FAULT BIT(19) +#define CONTROL_FAULT_ENABLE BIT(18) +#define CONTROL_DIV_MASK GENMASK(15, 0) + + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 __reserved_0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclr; + u32 __reserved_1[20]; + + struct { + u32 access; + u32 physel; +#define USERACCESS_GO BIT(31) +#define USERACCESS_WRITE BIT(30) +#define USERACCESS_ACK BIT(29) +#define USERACCESS_READ (0) +#define USERACCESS_PHY_REG_SHIFT (21) +#define USERACCESS_PHY_ADDR_SHIFT (16) +#define USERACCESS_DATA GENMASK(15, 0) + } user[0]; +}; + +#define CPSW_MDIO_DIV_DEF 0xff +#define PHY_REG_MASK 0x1f +#define PHY_ID_MASK 0x1f + +/* + * This timeout definition is a worst-case ultra defensive measure against + * unexpected controller lock ups. Ideally, we should never ever hit this + * scenario in practice. + */ +#define CPSW_MDIO_TIMEOUT 100 /* msecs */ + +struct cpsw_mdio { + struct cpsw_mdio_regs *regs; + struct mii_dev *bus; + int div; +}; + +/* wait until hardware is ready for another user access */ +static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio) +{ + return wait_for_bit_le32(&mdio->regs->user[0].access, + USERACCESS_GO, false, + CPSW_MDIO_TIMEOUT, false); +} + +static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, + int dev_addr, int phy_reg) +{ + struct cpsw_mdio *mdio = bus->priv; + int data, ret; + u32 reg; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + reg = (USERACCESS_GO | USERACCESS_READ | + (phy_reg << USERACCESS_PHY_REG_SHIFT) | + (phy_id << USERACCESS_PHY_ADDR_SHIFT)); + writel(reg, &mdio->regs->user[0].access); + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + + reg = readl(&mdio->regs->user[0].access); + data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; + return data; +} + +static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, + int phy_reg, u16 data) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 reg; + int ret; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + reg = (USERACCESS_GO | USERACCESS_WRITE | + (phy_reg << USERACCESS_PHY_REG_SHIFT) | + (phy_id << USERACCESS_PHY_ADDR_SHIFT) | + (data & USERACCESS_DATA)); + writel(reg, &mdio->regs->user[0].access); + + return cpsw_mdio_wait_for_user_access(mdio); +} + +u32 cpsw_mdio_get_alive(struct mii_dev *bus) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 val; + + val = readl(&mdio->regs->control); + return val & GENMASK(15, 0); +} + +struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base, + u32 bus_freq, int fck_freq) +{ + struct cpsw_mdio *cpsw_mdio; + int ret; + + cpsw_mdio = calloc(1, sizeof(*cpsw_mdio)); + if (!cpsw_mdio) { + debug("failed to alloc cpsw_mdio\n"); + return NULL; + } + + cpsw_mdio->bus = mdio_alloc(); + if (!cpsw_mdio->bus) { + debug("failed to alloc mii bus\n"); + free(cpsw_mdio); + return NULL; + } + + cpsw_mdio->regs = (struct cpsw_mdio_regs *)mdio_base; + + if (!bus_freq || !fck_freq) + cpsw_mdio->div = CPSW_MDIO_DIV_DEF; + else + cpsw_mdio->div = (fck_freq / bus_freq) - 1; + cpsw_mdio->div &= CONTROL_DIV_MASK; + + /* set enable and clock divider */ + writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT | + CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control); + wait_for_bit_le32(&cpsw_mdio->regs->control, + CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true); + + /* + * wait for scan logic to settle: + * the scan time consists of (a) a large fixed component, and (b) a + * small component that varies with the mii bus frequency. These + * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x + * silicon. Since the effect of (b) was found to be largely + * negligible, we keep things simple here. + */ + mdelay(1); + + cpsw_mdio->bus->read = cpsw_mdio_read; + cpsw_mdio->bus->write = cpsw_mdio_write; + cpsw_mdio->bus->priv = cpsw_mdio; + snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name); + + ret = mdio_register(cpsw_mdio->bus); + if (ret < 0) { + debug("failed to register mii bus\n"); + goto free_bus; + } + + return cpsw_mdio->bus; + +free_bus: + mdio_free(cpsw_mdio->bus); + free(cpsw_mdio); + return NULL; +} + +void cpsw_mdio_free(struct mii_dev *bus) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 reg; + + /* disable mdio */ + reg = readl(&mdio->regs->control); + reg &= ~CONTROL_ENABLE; + writel(reg, &mdio->regs->control); + + mdio_unregister(bus); + mdio_free(bus); + free(mdio); +} diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h new file mode 100644 index 0000000000..4a76d4e5c5 --- /dev/null +++ b/drivers/net/ti/cpsw_mdio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef CPSW_MDIO_H_ +#define CPSW_MDIO_H_ + +struct cpsw_mdio; + +struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base, + u32 bus_freq, int fck_freq); +void cpsw_mdio_free(struct mii_dev *bus); +u32 cpsw_mdio_get_alive(struct mii_dev *bus); + +#endif /* CPSW_MDIO_H_ */ diff --git a/drivers/net/davinci_emac.c b/drivers/net/ti/davinci_emac.c similarity index 100% rename from drivers/net/davinci_emac.c rename to drivers/net/ti/davinci_emac.c diff --git a/drivers/net/davinci_emac.h b/drivers/net/ti/davinci_emac.h similarity index 100% rename from drivers/net/davinci_emac.h rename to drivers/net/ti/davinci_emac.h diff --git a/drivers/net/keystone_net.c b/drivers/net/ti/keystone_net.c similarity index 68% rename from drivers/net/keystone_net.c rename to drivers/net/ti/keystone_net.c index d4d909b983..a3ba91cc3f 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -22,13 +22,9 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; +#include "cpsw_mdio.h" -#ifndef CONFIG_DM_ETH -unsigned int emac_open; -static struct mii_dev *mdio_bus; -static unsigned int sys_has_mdio = 1; -#endif +DECLARE_GLOBAL_DATA_PTR; #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) @@ -43,17 +39,6 @@ static unsigned int sys_has_mdio = 1; static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); -#ifndef CONFIG_DM_ETH -struct rx_buff_desc net_rx_buffs = { - .buff_ptr = rx_buffs, - .num_buffs = RX_BUFF_NUMS, - .buff_len = RX_BUFF_LEN, - .rx_flow = 22, -}; -#endif - -#ifdef CONFIG_DM_ETH - enum link_type { LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0, LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1, @@ -83,7 +68,7 @@ enum link_type { #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ (x) * 0x30) -#elif defined CONFIG_KSNET_NETCP_V1_5 +#elif defined(CONFIG_KSNET_NETCP_V1_5) #define EMAC_EMACSW_PORT_BASE_OFS 0x222000 @@ -113,126 +98,26 @@ struct ks2_eth_priv { bool emac_open; bool has_mdio; }; -#endif -/* MDIO */ - -static int keystone2_mdio_reset(struct mii_dev *bus) -{ - u_int32_t clkdiv; - struct mdio_regs *adap_mdio = bus->priv; - - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - - writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | - MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, - &adap_mdio->control); - - while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) - ; - - return 0; -} - -/** - * keystone2_mdio_read - read a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_read(struct mii_dev *bus, - int addr, int devad, int reg) -{ - int tmp; - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), - &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) - ; - - if (tmp & MDIO_USERACCESS0_ACK) - return tmp & 0xffff; - - return -1; -} - -/** - * keystone2_mdio_write - write to a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_write(struct mii_dev *bus, - int addr, int devad, int reg, u16 val) -{ - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | - (val & 0xffff), &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - return 0; -} - -#ifndef CONFIG_DM_ETH -static void __attribute__((unused)) - keystone2_eth_gigabit_enable(struct eth_device *dev) -{ - u_int16_t data; - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - - if (sys_has_mdio) { - data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, - MDIO_DEVAD_NONE, 0); - /* speed selection MSB */ - if (!(data & (1 << 6))) - return; - } - - /* - * Check if link detected is giga-bit - * If Gigabit mode detected, enable gigbit in MAC - */ - writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + - CPGMACSL_REG_CTL) | - EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, - DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); -} -#else static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - u_int16_t data; - - if (priv->has_mdio) { - data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, - MDIO_DEVAD_NONE, 0); - /* speed selection MSB */ - if (!(data & (1 << 6))) - return; - } /* * Check if link detected is giga-bit * If Gigabit mode detected, enable gigbit in MAC */ + if (priv->has_mdio) { + if (priv->phydev->speed != 1000) + return; + } + writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL) | EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); } -#endif #ifdef CONFIG_SOC_K2G int keystone_rgmii_config(struct phy_device *phy_dev) @@ -497,246 +382,6 @@ static void keystone2_net_serdes_setup(void) } #endif -#ifndef CONFIG_DM_ETH - -int keystone2_eth_read_mac_addr(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv; - u32 maca = 0; - u32 macb = 0; - - eth_priv = (struct eth_priv_t *)dev->priv; - - /* Read the e-fuse mac address */ - if (eth_priv->slave_port == 1) { - maca = __raw_readl(MAC_ID_BASE_ADDR); - macb = __raw_readl(MAC_ID_BASE_ADDR + 4); - } - - dev->enetaddr[0] = (macb >> 8) & 0xff; - dev->enetaddr[1] = (macb >> 0) & 0xff; - dev->enetaddr[2] = (maca >> 24) & 0xff; - dev->enetaddr[3] = (maca >> 16) & 0xff; - dev->enetaddr[4] = (maca >> 8) & 0xff; - dev->enetaddr[5] = (maca >> 0) & 0xff; - - return 0; -} - -int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) -{ - if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) - num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; - - return ksnav_send(&netcp_pktdma, buffer, - num_bytes, (slave_port_num) << 16); -} - -/* Eth device open */ -static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) -{ - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - debug("+ emac_open\n"); - - net_rx_buffs.rx_flow = eth_priv->rx_flow; - - sys_has_mdio = - (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; - - if (sys_has_mdio) - keystone2_mdio_reset(mdio_bus); - -#ifdef CONFIG_SOC_K2G - keystone_rgmii_config(phy_dev); -#else - keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, - eth_priv->sgmii_link_type); -#endif - - udelay(10000); - - /* On chip switch configuration */ - ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); - - /* TODO: add error handling code */ - if (qm_init()) { - printf("ERROR: qm_init()\n"); - return -1; - } - if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { - qm_close(); - printf("ERROR: netcp_init()\n"); - return -1; - } - - /* - * Streaming switch configuration. If not present this - * statement is defined to void in target.h. - * If present this is usually defined to a series of register writes - */ - hw_config_streaming_switch(); - - if (sys_has_mdio) { - keystone2_mdio_reset(mdio_bus); - - phy_startup(phy_dev); - if (phy_dev->link == 0) { - ksnav_close(&netcp_pktdma); - qm_close(); - return -1; - } - } - - emac_gigabit_enable(dev); - - ethss_start(); - - debug("- emac_open\n"); - - emac_open = 1; - - return 0; -} - -/* Eth device close */ -void keystone2_eth_close(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - debug("+ emac_close\n"); - - if (!emac_open) - return; - - ethss_stop(); - - ksnav_close(&netcp_pktdma); - qm_close(); - phy_shutdown(phy_dev); - - emac_open = 0; - - debug("- emac_close\n"); -} - -/* - * This function sends a single packet on the network and returns - * positive number (number of bytes transmitted) or negative for error - */ -static int keystone2_eth_send_packet(struct eth_device *dev, - void *packet, int length) -{ - int ret_status = -1; - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - genphy_update_link(phy_dev); - if (phy_dev->link == 0) - return -1; - - if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) - return ret_status; - - return length; -} - -/* - * This function handles receipt of a packet from the network - */ -static int keystone2_eth_rcv_packet(struct eth_device *dev) -{ - void *hd; - int pkt_size; - u32 *pkt; - - hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); - if (hd == NULL) - return 0; - - net_process_received_packet((uchar *)pkt, pkt_size); - - ksnav_release_rxhd(&netcp_pktdma, hd); - - return pkt_size; -} - -#ifdef CONFIG_MCAST_TFTP -static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set) -{ - return 0; -} -#endif - -/* - * This function initializes the EMAC hardware. - */ -int keystone2_emac_initialize(struct eth_priv_t *eth_priv) -{ - int res; - struct eth_device *dev; - struct phy_device *phy_dev; - struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; - - dev = malloc(sizeof(struct eth_device)); - if (dev == NULL) - return -1; - - memset(dev, 0, sizeof(struct eth_device)); - - strcpy(dev->name, eth_priv->int_name); - dev->priv = eth_priv; - - keystone2_eth_read_mac_addr(dev); - - dev->iobase = 0; - dev->init = keystone2_eth_open; - dev->halt = keystone2_eth_close; - dev->send = keystone2_eth_send_packet; - dev->recv = keystone2_eth_rcv_packet; -#ifdef CONFIG_MCAST_TFTP - dev->mcast = keystone2_eth_bcast_addr; -#endif - - eth_register(dev); - - /* Register MDIO bus if it's not registered yet */ - if (!mdio_bus) { - mdio_bus = mdio_alloc(); - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; - strcpy(mdio_bus->name, "ethernet-mdio"); - - res = mdio_register(mdio_bus); - if (res) - return res; - } - -#ifndef CONFIG_SOC_K2G - keystone2_net_serdes_setup(); -#endif - - /* Create phy device and bind it with driver */ -#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE - phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, - dev, eth_priv->phy_if); - phy_config(phy_dev); -#else - phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, - eth_priv->phy_if); - phy_dev->dev = dev; -#endif - eth_priv->phy_dev = phy_dev; - - return 0; -} - -#else - static int ks2_eth_start(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); @@ -768,8 +413,6 @@ static int ks2_eth_start(struct udevice *dev) hw_config_streaming_switch(); if (priv->has_mdio) { - keystone2_mdio_reset(priv->mdio_bus); - phy_startup(priv->phydev); if (priv->phydev->link == 0) { pr_err("phy startup failed\n"); @@ -889,9 +532,9 @@ static int ks2_eth_probe(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); struct mii_dev *mdio_bus; - int ret; priv->dev = dev; + priv->emac_open = false; /* These clock enables has to be moved to common location */ if (cpu_is_k2g()) @@ -910,45 +553,36 @@ static int ks2_eth_probe(struct udevice *dev) if (cpu_is_k2e() || cpu_is_k2l()) pll_pa_clk_sel(); - priv->net_rx_buffs.buff_ptr = rx_buffs; priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; priv->net_rx_buffs.buff_len = RX_BUFF_LEN; if (priv->slave_port == 1) { +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif /* * Register MDIO bus for slave 0 only, other slave have * to re-use the same */ - mdio_bus = mdio_alloc(); + mdio_bus = cpsw_mdio_init("ethernet-mdio", + (u32)priv->mdio_base, + EMAC_MDIO_CLOCK_FREQ, + EMAC_MDIO_BUS_FREQ); if (!mdio_bus) { pr_err("MDIO alloc failed\n"); return -ENOMEM; } priv->mdio_bus = mdio_bus; - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = priv->mdio_base; - sprintf(mdio_bus->name, "ethernet-mdio"); - - ret = mdio_register(mdio_bus); - if (ret) { - pr_err("MDIO bus register failed\n"); - return ret; - } } else { /* Get the MDIO bus from slave 0 device */ struct ks2_eth_priv *parent_priv; parent_priv = dev_get_priv(dev->parent); priv->mdio_bus = parent_priv->mdio_bus; + priv->mdio_base = parent_priv->mdio_base; } -#ifndef CONFIG_SOC_K2G - keystone2_net_serdes_setup(); -#endif - priv->netcp_pktdma = &netcp_pktdma; if (priv->has_mdio) { @@ -964,9 +598,7 @@ int ks2_eth_remove(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - free(priv->phydev); - mdio_unregister(priv->mdio_bus); - mdio_free(priv->mdio_bus); + cpsw_mdio_free(priv->mdio_bus); return 0; } @@ -1167,4 +799,3 @@ U_BOOT_DRIVER(eth_ks2) = { .platdata_auto_alloc_size = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index eb6fdeda50..1ee0a0aefb 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -664,7 +664,6 @@ static int nvme_blk_probe(struct udevice *udev) sprintf(desc->vendor, "0x%.4x", pplat->vendor); memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); - part_init(desc); return 0; } diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index da49c96ed5..2cf55cb743 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -774,16 +774,19 @@ int pci_bind_bus_devices(struct udevice *bus) found_multi = false; if (PCI_FUNC(bdf) && !found_multi) continue; + /* Check only the first access, we don't expect problems */ - ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, - &header_type, PCI_SIZE_8); + ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, + PCI_SIZE_16); if (ret) goto error; - pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, - PCI_SIZE_16); + if (vendor == 0xffff || vendor == 0x0000) continue; + pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, + &header_type, PCI_SIZE_8); + if (!PCI_FUNC(bdf)) found_multi = header_type & 0x80; @@ -1344,26 +1347,14 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); } -int dm_pci_find_capability(struct udevice *dev, int cap) +static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) { - u16 status; - u8 header_type; int ttl = PCI_FIND_CAP_TTL; u8 id; u16 ent; - u8 pos; - - dm_pci_read_config16(dev, PCI_STATUS, &status); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); - if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS) - pos = PCI_CB_CAPABILITY_LIST; - else - pos = PCI_CAPABILITY_LIST; dm_pci_read_config8(dev, pos, &pos); + while (ttl--) { if (pos < PCI_STD_HEADER_SIZEOF) break; @@ -1381,7 +1372,32 @@ int dm_pci_find_capability(struct udevice *dev, int cap) return 0; } -int dm_pci_find_ext_capability(struct udevice *dev, int cap) +int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap) +{ + return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT, + cap); +} + +int dm_pci_find_capability(struct udevice *dev, int cap) +{ + u16 status; + u8 header_type; + u8 pos; + + dm_pci_read_config16(dev, PCI_STATUS, &status); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS) + pos = PCI_CB_CAPABILITY_LIST; + else + pos = PCI_CAPABILITY_LIST; + + return _dm_pci_find_next_capability(dev, pos, cap); +} + +int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap) { u32 header; int ttl; @@ -1390,6 +1406,9 @@ int dm_pci_find_ext_capability(struct udevice *dev, int cap) /* minimum 8 bytes per capability */ ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + if (start) + pos = start; + dm_pci_read_config32(dev, pos, &header); /* * If we have no capabilities, this is indicated by cap ID, @@ -1412,6 +1431,11 @@ int dm_pci_find_ext_capability(struct udevice *dev, int cap) return 0; } +int dm_pci_find_ext_capability(struct udevice *dev, int cap) +{ + return dm_pci_find_next_ext_capability(dev, 0, cap); +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index eaacd4066e..7d9b75c2c4 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -331,6 +331,7 @@ int vbe_setup_video_priv(struct vesa_mode_info *vesa, return log_msg_ret("No x resolution", -ENXIO); uc_priv->xsize = vesa->x_resolution; uc_priv->ysize = vesa->y_resolution; + uc_priv->line_length = vesa->bytes_per_scanline; switch (vesa->bits_per_pixel) { case 32: case 24: diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 14d82b93ed..825ee7c3be 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -155,4 +155,23 @@ config MSM8916_USB_PHY This PHY is found on qualcomm dragonboard410c development board. +config OMAP_USB2_PHY + bool "Support OMAP's USB2 PHY" + depends on PHY + depends on SYSCON + help + Support for the OMAP's USB2 PHY. + + This PHY is found on OMAP devices supporting USB2. + + +config KEYSTONE_USB_PHY + bool "Support TI Keystone USB PHY" + depends on PHY + depends on ARCH_KEYSTONE + help + Support for the USB PHY found on some Keystone (k2) processors + + This PHY is found on some Keystone (K2) devices supporting USB. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 8030d599e7..099551d693 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -17,3 +17,5 @@ obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o +obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c new file mode 100644 index 0000000000..e8146cabfa --- /dev/null +++ b/drivers/phy/keystone-usb-phy.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Written by Jean-Jacques Hiblot + */ + +#include +#include +#include +#include +#include + +/* USB PHY control register offsets */ +#define USB_PHY_CTL_UTMI 0x0000 +#define USB_PHY_CTL_PIPE 0x0004 +#define USB_PHY_CTL_PARAM_1 0x0008 +#define USB_PHY_CTL_PARAM_2 0x000c +#define USB_PHY_CTL_CLOCK 0x0010 +#define USB_PHY_CTL_PLL 0x0014 + +#define PHY_OTG_VBUSVLDECTSEL BIT(16) +#define PHY_REF_SSP_EN BIT(29) + +struct keystone_usb_phy { + void __iomem *reg; +}; + +static int keystone_usb_init(struct phy *phy) +{ + u32 val; + struct udevice *dev = phy->dev; + struct keystone_usb_phy *keystone = dev_get_priv(dev); + + /* + * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. + * It should always be cleared because our USB PHY has an onchip VBUS + * analog comparator. + */ + val = readl(keystone->reg + USB_PHY_CTL_CLOCK); + /* quit selecting the vbusvldextsel by default! */ + val &= ~PHY_OTG_VBUSVLDECTSEL; + writel(val, keystone->reg + USB_PHY_CTL_CLOCK); + + return 0; +} + +static int keystone_usb_power_on(struct phy *phy) +{ + u32 val; + struct udevice *dev = phy->dev; + struct keystone_usb_phy *keystone = dev_get_priv(dev); + + val = readl(keystone->reg + USB_PHY_CTL_CLOCK); + val |= PHY_REF_SSP_EN; + writel(val, keystone->reg + USB_PHY_CTL_CLOCK); + + return 0; +} + +static int keystone_usb_power_off(struct phy *phy) +{ + u32 val; + struct udevice *dev = phy->dev; + struct keystone_usb_phy *keystone = dev_get_priv(dev); + + val = readl(keystone->reg + USB_PHY_CTL_CLOCK); + val &= ~PHY_REF_SSP_EN; + writel(val, keystone->reg + USB_PHY_CTL_CLOCK); + + return 0; +} + +static int keystone_usb_exit(struct phy *phy) +{ + return 0; +} + +static int keystone_usb_phy_probe(struct udevice *dev) +{ + struct keystone_usb_phy *keystone = dev_get_priv(dev); + + keystone->reg = dev_remap_addr_index(dev, 0); + if (!keystone->reg) { + pr_err("unable to remap usb phy\n"); + return -EINVAL; + } + return 0; +} + +static const struct udevice_id keystone_usb_phy_ids[] = { + { .compatible = "ti,keystone-usbphy" }, + { } +}; + +static struct phy_ops keystone_usb_phy_ops = { + .init = keystone_usb_init, + .power_on = keystone_usb_power_on, + .power_off = keystone_usb_power_off, + .exit = keystone_usb_exit, +}; + +U_BOOT_DRIVER(keystone_usb_phy) = { + .name = "keystone_usb_phy", + .id = UCLASS_PHY, + .of_match = keystone_usb_phy_ids, + .ops = &keystone_usb_phy_ops, + .probe = keystone_usb_phy_probe, + .priv_auto_alloc_size = sizeof(struct keystone_usb_phy), +}; diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c new file mode 100644 index 0000000000..be3bb0d367 --- /dev/null +++ b/drivers/phy/omap-usb2-phy.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP USB2 PHY LAYER + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Written by Jean-Jacques Hiblot + */ + +#include +#include +#include +#include +#include +#include +#include + +#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(0) + +#define OMAP_DEV_PHY_PD BIT(0) +#define OMAP_USB2_PHY_PD BIT(28) + +#define AM437X_USB2_PHY_PD BIT(0) +#define AM437X_USB2_OTG_PD BIT(1) +#define AM437X_USB2_OTGVDET_EN BIT(19) +#define AM437X_USB2_OTGSESSEND_EN BIT(20) + +#define USB2PHY_DISCON_BYP_LATCH BIT(31) +#define USB2PHY_ANA_CONFIG1 (0x4c) + +DECLARE_GLOBAL_DATA_PTR; + +struct omap_usb2_phy { + struct regmap *pwr_regmap; + ulong flags; + void *phy_base; + u32 pwr_reg_offset; +}; + +struct usb_phy_data { + const char *label; + u8 flags; + u32 mask; + u32 power_on; + u32 power_off; +}; + +static const struct usb_phy_data omap5_usb2_data = { + .label = "omap5_usb2", + .flags = 0, + .mask = OMAP_DEV_PHY_PD, + .power_off = OMAP_DEV_PHY_PD, +}; + +static const struct usb_phy_data dra7x_usb2_data = { + .label = "dra7x_usb2", + .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT, + .mask = OMAP_DEV_PHY_PD, + .power_off = OMAP_DEV_PHY_PD, +}; + +static const struct usb_phy_data dra7x_usb2_phy2_data = { + .label = "dra7x_usb2_phy2", + .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT, + .mask = OMAP_USB2_PHY_PD, + .power_off = OMAP_USB2_PHY_PD, +}; + +static const struct usb_phy_data am437x_usb2_data = { + .label = "am437x_usb2", + .flags = 0, + .mask = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD | + AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN, + .power_on = AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN, + .power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD, +}; + +static const struct udevice_id omap_usb2_id_table[] = { + { + .compatible = "ti,omap5-usb2", + .data = (ulong)&omap5_usb2_data, + }, + { + .compatible = "ti,dra7x-usb2", + .data = (ulong)&dra7x_usb2_data, + }, + { + .compatible = "ti,dra7x-usb2-phy2", + .data = (ulong)&dra7x_usb2_phy2_data, + }, + { + .compatible = "ti,am437x-usb2", + .data = (ulong)&am437x_usb2_data, + }, + {}, +}; + +static int omap_usb_phy_power(struct phy *usb_phy, bool on) +{ + struct udevice *dev = usb_phy->dev; + const struct usb_phy_data *data; + const struct omap_usb2_phy *phy = dev_get_priv(dev); + u32 val; + int rc; + + data = (const struct usb_phy_data *)dev_get_driver_data(dev); + if (!data) + return -EINVAL; + + rc = regmap_read(phy->pwr_regmap, phy->pwr_reg_offset, &val); + if (rc) + return rc; + val &= ~data->mask; + if (on) + val |= data->power_on; + else + val |= data->power_off; + rc = regmap_write(phy->pwr_regmap, phy->pwr_reg_offset, val); + if (rc) + return rc; + + return 0; +} + +static int omap_usb2_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct omap_usb2_phy *priv = dev_get_priv(dev); + u32 val; + + if (priv->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) { + /* + * + * Reduce the sensitivity of internal PHY by enabling the + * DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This + * resolves issues with certain devices which can otherwise + * be prone to false disconnects. + * + */ + val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); + val |= USB2PHY_DISCON_BYP_LATCH; + writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); + } + + return 0; +} + +static int omap_usb2_phy_power_on(struct phy *usb_phy) +{ + return omap_usb_phy_power(usb_phy, true); +} + +static int omap_usb2_phy_power_off(struct phy *usb_phy) +{ + return omap_usb_phy_power(usb_phy, false); +} + +static int omap_usb2_phy_exit(struct phy *usb_phy) +{ + return omap_usb_phy_power(usb_phy, false); +} + +struct phy_ops omap_usb2_phy_ops = { + .init = omap_usb2_phy_init, + .power_on = omap_usb2_phy_power_on, + .power_off = omap_usb2_phy_power_off, + .exit = omap_usb2_phy_exit, +}; + +int omap_usb2_phy_probe(struct udevice *dev) +{ + int rc; + struct regmap *regmap; + struct omap_usb2_phy *priv = dev_get_priv(dev); + const struct usb_phy_data *data; + u32 tmp[2]; + + data = (const struct usb_phy_data *)dev_get_driver_data(dev); + if (!data) + return -EINVAL; + + if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) { + u32 base = dev_read_addr(dev); + + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + priv->phy_base = (void *)base; + priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT; + } + + regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power"); + if (!IS_ERR(regmap)) { + priv->pwr_regmap = regmap; + rc = dev_read_u32_array(dev, "syscon-phy-power", tmp, 2); + if (rc) { + printf("couldn't get power reg. offset (err %d)\n", rc); + return rc; + } + priv->pwr_reg_offset = tmp[1]; + return 0; + } + regmap = syscon_regmap_lookup_by_phandle(dev, "ctrl-module"); + if (!IS_ERR(regmap)) { + priv->pwr_regmap = regmap; + priv->pwr_reg_offset = 0; + return 0; + } + + printf("can't get regmap (err %ld)\n", PTR_ERR(regmap)); + return PTR_ERR(regmap); +} + +U_BOOT_DRIVER(omap_usb2_phy) = { + .name = "omap_usb2_phy", + .id = UCLASS_PHY, + .of_match = omap_usb2_id_table, + .probe = omap_usb2_phy_probe, + .ops = &omap_usb2_phy_ops, + .priv_auto_alloc_size = sizeof(struct omap_usb2_phy), +}; diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index b22bbaf985..e7e78e3c56 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -141,7 +141,7 @@ static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3) omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val); val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; + val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE); val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val); @@ -265,10 +265,13 @@ static int pipe3_exit(struct phy *phy) return -EBUSY; } - val = readl(pipe3->pll_reset_reg); - writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); - mdelay(1); - writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); + if (pipe3->pll_reset_reg) { + val = readl(pipe3->pll_reset_reg); + writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); + mdelay(1); + writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg); + } + return 0; } @@ -331,9 +334,11 @@ static int pipe3_phy_probe(struct udevice *dev) if (!pipe3->power_reg) return -EINVAL; - pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset"); - if (!pipe3->pll_reset_reg) - return -EINVAL; + if (device_is_compatible(dev, "ti,phy-pipe3-sata")) { + pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset"); + if (!pipe3->pll_reset_reg) + return -EINVAL; + } pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev); @@ -350,8 +355,19 @@ static struct pipe3_dpll_map dpll_map_sata[] = { { }, /* Terminator */ }; +static struct pipe3_dpll_map dpll_map_usb[] = { + {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ + {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ + {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ + {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ + {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ + {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + static const struct udevice_id pipe3_phy_ids[] = { { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata }, + { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb}, { } }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ad0b8daba6..30a6aa6ee8 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -238,6 +238,16 @@ config PINCTRL_ROCKCHIP_RK3399 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK3399_FULL + bool "Rockchip rk3399 pin control driver (full)" + depends on PINCTRL_FULL && PINCTRL_ROCKCHIP_RK3399 + help + Support full pin multiplexing control on Rockchip rk3399 SoCs. + + This enables the full pinctrl driver for the RK3399. + Contrary to the non-full pinctrl driver, this will evaluate + the board DTB to get the pinctrl settings. + config PINCTRL_ROCKCHIP_RV1108 bool "Rockchip rv1108 pin control driver" depends on DM @@ -301,10 +311,12 @@ config ASPEED_AST2500_PINCTRL endif source "drivers/pinctrl/meson/Kconfig" +source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/exynos/Kconfig" +source "drivers/pinctrl/mscc/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index a3a6c6d163..66d36b99d1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ obj-$(CONFIG_PINCTRL_MESON) += meson/ +obj-$(CONFIG_PINCTRL_MTK) += mediatek/ +obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index 891b4c25fd..3be080d29e 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -148,5 +148,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = { .priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv), .ops = &bcm283x_pinctrl_ops, .probe = bcm283x_pinctl_probe, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c index cb5975b252..ff6d6c4143 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos7420.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c @@ -113,5 +113,4 @@ U_BOOT_DRIVER(pinctrl_exynos7420) = { .priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv), .ops = &exynos7420_pinctrl_ops, .probe = exynos_pinctrl_probe, - .flags = DM_FLAG_PRE_RELOC }; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig new file mode 100644 index 0000000000..1bd9a925a5 --- /dev/null +++ b/drivers/pinctrl/mediatek/Kconfig @@ -0,0 +1,15 @@ +if ARCH_MEDIATEK + +config PINCTRL_MTK + depends on PINCTRL_GENERIC + bool + +config PINCTRL_MT7623 + bool "MT7623 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT7629 + bool "MT7629 SoC pinctrl driver" + select PINCTRL_MTK + +endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile new file mode 100644 index 0000000000..f6ef3627e8 --- /dev/null +++ b/drivers/pinctrl/mediatek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# Core +obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c new file mode 100644 index 0000000000..fd37dfa442 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -0,0 +1,1284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include + +#include "pinctrl-mtk-common.h" + +#define PIN_BOND_REG0 0xb10 +#define PIN_BOND_REG1 0xf20 +#define PIN_BOND_REG2 0xef0 +#define BOND_PCIE_CLR (0x77 << 3) +#define BOND_I2S_CLR 0x3 +#define BOND_MSDC0E_CLR 0x1 + +#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 15, false) + +#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, false) + +#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 16, true) + +static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = { + PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = { + PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1), + PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_di_range[] = { + PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_do_range[] = { + PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = { + PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1), + PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1), + PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1), + PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1), + PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1), + PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1), + PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1), + PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1), + PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1), + PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1), + PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1), + PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1), + PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1), + PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1), + PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1), + PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1), + PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1), + PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1), + PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1), + PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1), + PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1), + PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1), + PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1), + PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1), + PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1), + PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1), + PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1), + PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1), + PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1), + PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1), + PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1), + PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1), + PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1), + PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1), + PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1), + PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1), + PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1), + PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1), + PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1), + PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1), + PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1), + PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1), + PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1), + PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1), + PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1), + PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1), + PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1), + PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1), + PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1), + PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1), + PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1), + PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1), + PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1), + PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1), + PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1), + PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1), + PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = { + PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1), + PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1), + PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1), + PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1), + PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1), + PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1), + PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1), + PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1), + PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1), + PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1), + PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1), + PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1), + PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1), + PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1), + PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1), + PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1), + PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1), + PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1), + PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1), + PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1), + PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1), + PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1), + PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1), + PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1), + PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1), + PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1), + PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1), + PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1), + PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1), + PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1), + PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1), + PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1), + PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1), + PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1), + PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1), + PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1), + PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1), + PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1), + PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1), + PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1), + PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1), + PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1), + PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1), + PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1), + PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1), + PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1), + PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1), + PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1), + PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1), + PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1), + PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1), + PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1), + PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1), + PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1), + PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1), + PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1), + PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1), + PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1), + PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1), + PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1), + PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1), + PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1), + PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1), + PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1), + PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1), + PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1), + PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1), + PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10), + PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1), + PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1), + PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1), + PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1), + PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1), + PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1), + PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1), + PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1), + PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1), + PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1), + PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1), + PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1), + PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = { + PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = { + PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = { + PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4), + PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4), + PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4), + PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4), + PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4), + PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4), + PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4), + PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4), + PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4), + PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4), + PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4), + PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4), + PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4), + PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4), + PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4), + PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4), + PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4), + PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4), + PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4), + PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4), + PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4), + PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4), + PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4), + PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4), + PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4), + PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4), + PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4), + PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4), + PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4), + PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4), + PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4), + PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4), + PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4), + PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4), + PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4), + PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4), + PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4), + PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4), + PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4), + PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4), + PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4), + PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4), + PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4), + PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4), + PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4), + PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4), + PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4), + PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4), + PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4), + PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4), + PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4), + PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4), +}; + +static const struct mtk_pin_reg_calc mt7623_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range), +}; + +static const struct mtk_pin_desc mt7623_pins[] = { + MTK_PIN(0, "PWRAP_SPI0_MI", DRV_GRP3), + MTK_PIN(1, "PWRAP_SPI0_MO", DRV_GRP3), + MTK_PIN(2, "PWRAP_INT", DRV_GRP3), + MTK_PIN(3, "PWRAP_SPI0_CK", DRV_GRP3), + MTK_PIN(4, "PWRAP_SPI0_CSN", DRV_GRP3), + MTK_PIN(5, "PWRAP_SPI0_CK2", DRV_GRP3), + MTK_PIN(6, "PWRAP_SPI0_CSN2", DRV_GRP3), + MTK_PIN(7, "SPI1_CSN", DRV_GRP3), + MTK_PIN(8, "SPI1_MI", DRV_GRP3), + MTK_PIN(9, "SPI1_MO", DRV_GRP3), + MTK_PIN(10, "RTC32K_CK", DRV_GRP3), + MTK_PIN(11, "WATCHDOG", DRV_GRP3), + MTK_PIN(12, "SRCLKENA", DRV_GRP3), + MTK_PIN(13, "SRCLKENAI", DRV_GRP3), + MTK_PIN(14, "URXD2", DRV_GRP1), + MTK_PIN(15, "UTXD2", DRV_GRP1), + MTK_PIN(16, "I2S5_DATA_IN", DRV_GRP1), + MTK_PIN(17, "I2S5_BCK", DRV_GRP1), + MTK_PIN(18, "PCM_CLK", DRV_GRP1), + MTK_PIN(19, "PCM_SYNC", DRV_GRP1), + MTK_PIN(20, "PCM_RX", DRV_GRP1), + MTK_PIN(21, "PCM_TX", DRV_GRP1), + MTK_PIN(22, "EINT0", DRV_GRP1), + MTK_PIN(23, "EINT1", DRV_GRP1), + MTK_PIN(24, "EINT2", DRV_GRP1), + MTK_PIN(25, "EINT3", DRV_GRP1), + MTK_PIN(26, "EINT4", DRV_GRP1), + MTK_PIN(27, "EINT5", DRV_GRP1), + MTK_PIN(28, "EINT6", DRV_GRP1), + MTK_PIN(29, "EINT7", DRV_GRP1), + MTK_PIN(30, "I2S5_LRCK", DRV_GRP1), + MTK_PIN(31, "I2S5_MCLK", DRV_GRP1), + MTK_PIN(32, "I2S5_DATA", DRV_GRP1), + MTK_PIN(33, "I2S1_DATA", DRV_GRP1), + MTK_PIN(34, "I2S1_DATA_IN", DRV_GRP1), + MTK_PIN(35, "I2S1_BCK", DRV_GRP1), + MTK_PIN(36, "I2S1_LRCK", DRV_GRP1), + MTK_PIN(37, "I2S1_MCLK", DRV_GRP1), + MTK_PIN(38, "I2S2_DATA", DRV_GRP1), + MTK_PIN(39, "JTMS", DRV_GRP3), + MTK_PIN(40, "JTCK", DRV_GRP3), + MTK_PIN(41, "JTDI", DRV_GRP3), + MTK_PIN(42, "JTDO", DRV_GRP3), + MTK_PIN(43, "NCLE", DRV_GRP1), + MTK_PIN(44, "NCEB1", DRV_GRP1), + MTK_PIN(45, "NCEB0", DRV_GRP1), + MTK_PIN(46, "IR", DRV_FIXED), + MTK_PIN(47, "NREB", DRV_GRP1), + MTK_PIN(48, "NRNB", DRV_GRP1), + MTK_PIN(49, "I2S0_DATA", DRV_GRP1), + MTK_PIN(50, "I2S2_BCK", DRV_GRP1), + MTK_PIN(51, "I2S2_DATA_IN", DRV_GRP1), + MTK_PIN(52, "I2S2_LRCK", DRV_GRP1), + MTK_PIN(53, "SPI0_CSN", DRV_GRP1), + MTK_PIN(54, "SPI0_CK", DRV_GRP1), + MTK_PIN(55, "SPI0_MI", DRV_GRP1), + MTK_PIN(56, "SPI0_MO", DRV_GRP1), + MTK_PIN(57, "SDA1", DRV_FIXED), + MTK_PIN(58, "SCL1", DRV_FIXED), + MTK_PIN(59, "RAMBUF_I_CLK", DRV_FIXED), + MTK_PIN(60, "WB_RSTB", DRV_GRP3), + MTK_PIN(61, "F2W_DATA", DRV_GRP3), + MTK_PIN(62, "F2W_CLK", DRV_GRP3), + MTK_PIN(63, "WB_SCLK", DRV_GRP3), + MTK_PIN(64, "WB_SDATA", DRV_GRP3), + MTK_PIN(65, "WB_SEN", DRV_GRP3), + MTK_PIN(66, "WB_CRTL0", DRV_GRP3), + MTK_PIN(67, "WB_CRTL1", DRV_GRP3), + MTK_PIN(68, "WB_CRTL2", DRV_GRP3), + MTK_PIN(69, "WB_CRTL3", DRV_GRP3), + MTK_PIN(70, "WB_CRTL4", DRV_GRP3), + MTK_PIN(71, "WB_CRTL5", DRV_GRP3), + MTK_PIN(72, "I2S0_DATA_IN", DRV_GRP1), + MTK_PIN(73, "I2S0_LRCK", DRV_GRP1), + MTK_PIN(74, "I2S0_BCK", DRV_GRP1), + MTK_PIN(75, "SDA0", DRV_FIXED), + MTK_PIN(76, "SCL0", DRV_FIXED), + MTK_PIN(77, "SDA2", DRV_FIXED), + MTK_PIN(78, "SCL2", DRV_FIXED), + MTK_PIN(79, "URXD0", DRV_FIXED), + MTK_PIN(80, "UTXD0", DRV_FIXED), + MTK_PIN(81, "URXD1", DRV_FIXED), + MTK_PIN(82, "UTXD1", DRV_FIXED), + MTK_PIN(83, "LCM_RST", DRV_FIXED), + MTK_PIN(84, "DSI_TE", DRV_FIXED), + MTK_PIN(85, "MSDC2_CMD", DRV_GRP4), + MTK_PIN(86, "MSDC2_CLK", DRV_GRP4), + MTK_PIN(87, "MSDC2_DAT0", DRV_GRP4), + MTK_PIN(88, "MSDC2_DAT1", DRV_GRP4), + MTK_PIN(89, "MSDC2_DAT2", DRV_GRP4), + MTK_PIN(90, "MSDC2_DAT3", DRV_GRP4), + MTK_PIN(91, "TDN3", DRV_FIXED), + MTK_PIN(92, "TDP3", DRV_FIXED), + MTK_PIN(93, "TDN2", DRV_FIXED), + MTK_PIN(94, "TDP2", DRV_FIXED), + MTK_PIN(95, "TCN", DRV_FIXED), + MTK_PIN(96, "TCP", DRV_FIXED), + MTK_PIN(97, "TDN1", DRV_FIXED), + MTK_PIN(98, "TDP1", DRV_FIXED), + MTK_PIN(99, "TDN0", DRV_FIXED), + MTK_PIN(100, "TDP0", DRV_FIXED), + MTK_PIN(101, "SPI2_CSN", DRV_FIXED), + MTK_PIN(102, "SPI2_MI", DRV_FIXED), + MTK_PIN(103, "SPI2_MO", DRV_FIXED), + MTK_PIN(104, "SPI2_CLK", DRV_FIXED), + MTK_PIN(105, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(106, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(107, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(108, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(109, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(110, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(111, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(112, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(113, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(114, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(115, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(116, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(117, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(118, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(119, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(120, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(121, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(122, "CEC", DRV_FIXED), + MTK_PIN(123, "HTPLG", DRV_FIXED), + MTK_PIN(124, "HDMISCK", DRV_FIXED), + MTK_PIN(125, "HDMISD", DRV_FIXED), + MTK_PIN(126, "I2S0_MCLK", DRV_GRP1), + MTK_PIN(127, "RAMBUF_IDATA0", DRV_FIXED), + MTK_PIN(128, "RAMBUF_IDATA1", DRV_FIXED), + MTK_PIN(129, "RAMBUF_IDATA2", DRV_FIXED), + MTK_PIN(130, "RAMBUF_IDATA3", DRV_FIXED), + MTK_PIN(131, "RAMBUF_IDATA4", DRV_FIXED), + MTK_PIN(132, "RAMBUF_IDATA5", DRV_FIXED), + MTK_PIN(133, "RAMBUF_IDATA6", DRV_FIXED), + MTK_PIN(134, "RAMBUF_IDATA7", DRV_FIXED), + MTK_PIN(135, "RAMBUF_IDATA8", DRV_FIXED), + MTK_PIN(136, "RAMBUF_IDATA9", DRV_FIXED), + MTK_PIN(137, "RAMBUF_IDATA10", DRV_FIXED), + MTK_PIN(138, "RAMBUF_IDATA11", DRV_FIXED), + MTK_PIN(139, "RAMBUF_IDATA12", DRV_FIXED), + MTK_PIN(140, "RAMBUF_IDATA13", DRV_FIXED), + MTK_PIN(141, "RAMBUF_IDATA14", DRV_FIXED), + MTK_PIN(142, "RAMBUF_IDATA15", DRV_FIXED), + MTK_PIN(143, "RAMBUF_ODATA0", DRV_FIXED), + MTK_PIN(144, "RAMBUF_ODATA1", DRV_FIXED), + MTK_PIN(145, "RAMBUF_ODATA2", DRV_FIXED), + MTK_PIN(146, "RAMBUF_ODATA3", DRV_FIXED), + MTK_PIN(147, "RAMBUF_ODATA4", DRV_FIXED), + MTK_PIN(148, "RAMBUF_ODATA5", DRV_FIXED), + MTK_PIN(149, "RAMBUF_ODATA6", DRV_FIXED), + MTK_PIN(150, "RAMBUF_ODATA7", DRV_FIXED), + MTK_PIN(151, "RAMBUF_ODATA8", DRV_FIXED), + MTK_PIN(152, "RAMBUF_ODATA9", DRV_FIXED), + MTK_PIN(153, "RAMBUF_ODATA10", DRV_FIXED), + MTK_PIN(154, "RAMBUF_ODATA11", DRV_FIXED), + MTK_PIN(155, "RAMBUF_ODATA12", DRV_FIXED), + MTK_PIN(156, "RAMBUF_ODATA13", DRV_FIXED), + MTK_PIN(157, "RAMBUF_ODATA14", DRV_FIXED), + MTK_PIN(158, "RAMBUF_ODATA15", DRV_FIXED), + MTK_PIN(159, "RAMBUF_BE0", DRV_FIXED), + MTK_PIN(160, "RAMBUF_BE1", DRV_FIXED), + MTK_PIN(161, "AP2PT_INT", DRV_FIXED), + MTK_PIN(162, "AP2PT_INT_CLR", DRV_FIXED), + MTK_PIN(163, "PT2AP_INT", DRV_FIXED), + MTK_PIN(164, "PT2AP_INT_CLR", DRV_FIXED), + MTK_PIN(165, "AP2UP_INT", DRV_FIXED), + MTK_PIN(166, "AP2UP_INT_CLR", DRV_FIXED), + MTK_PIN(167, "UP2AP_INT", DRV_FIXED), + MTK_PIN(168, "UP2AP_INT_CLR", DRV_FIXED), + MTK_PIN(169, "RAMBUF_ADDR0", DRV_FIXED), + MTK_PIN(170, "RAMBUF_ADDR1", DRV_FIXED), + MTK_PIN(171, "RAMBUF_ADDR2", DRV_FIXED), + MTK_PIN(172, "RAMBUF_ADDR3", DRV_FIXED), + MTK_PIN(173, "RAMBUF_ADDR4", DRV_FIXED), + MTK_PIN(174, "RAMBUF_ADDR5", DRV_FIXED), + MTK_PIN(175, "RAMBUF_ADDR6", DRV_FIXED), + MTK_PIN(176, "RAMBUF_ADDR7", DRV_FIXED), + MTK_PIN(177, "RAMBUF_ADDR8", DRV_FIXED), + MTK_PIN(178, "RAMBUF_ADDR9", DRV_FIXED), + MTK_PIN(179, "RAMBUF_ADDR10", DRV_FIXED), + MTK_PIN(180, "RAMBUF_RW", DRV_FIXED), + MTK_PIN(181, "RAMBUF_LAST", DRV_FIXED), + MTK_PIN(182, "RAMBUF_HP", DRV_FIXED), + MTK_PIN(183, "RAMBUF_REQ", DRV_FIXED), + MTK_PIN(184, "RAMBUF_ALE", DRV_FIXED), + MTK_PIN(185, "RAMBUF_DLE", DRV_FIXED), + MTK_PIN(186, "RAMBUF_WDLE", DRV_FIXED), + MTK_PIN(187, "RAMBUF_O_CLK", DRV_FIXED), + MTK_PIN(188, "I2S2_MCLK", DRV_GRP1), + MTK_PIN(189, "I2S3_DATA", DRV_GRP1), + MTK_PIN(190, "I2S3_DATA_IN", DRV_GRP1), + MTK_PIN(191, "I2S3_BCK", DRV_GRP1), + MTK_PIN(192, "I2S3_LRCK", DRV_GRP1), + MTK_PIN(193, "I2S3_MCLK", DRV_GRP1), + MTK_PIN(194, "I2S4_DATA", DRV_GRP1), + MTK_PIN(195, "I2S4_DATA_IN", DRV_GRP1), + MTK_PIN(196, "I2S4_BCK", DRV_GRP1), + MTK_PIN(197, "I2S4_LRCK", DRV_GRP1), + MTK_PIN(198, "I2S4_MCLK", DRV_GRP1), + MTK_PIN(199, "SPI1_CLK", DRV_GRP3), + MTK_PIN(200, "SPDIF_OUT", DRV_GRP1), + MTK_PIN(201, "SPDIF_IN0", DRV_GRP1), + MTK_PIN(202, "SPDIF_IN1", DRV_GRP1), + MTK_PIN(203, "PWM0", DRV_GRP1), + MTK_PIN(204, "PWM1", DRV_GRP1), + MTK_PIN(205, "PWM2", DRV_GRP1), + MTK_PIN(206, "PWM3", DRV_GRP1), + MTK_PIN(207, "PWM4", DRV_GRP1), + MTK_PIN(208, "AUD_EXT_CK1", DRV_GRP1), + MTK_PIN(209, "AUD_EXT_CK2", DRV_GRP1), + MTK_PIN(210, "AUD_CLOCK", DRV_GRP3), + MTK_PIN(211, "DVP_RESET", DRV_GRP3), + MTK_PIN(212, "DVP_CLOCK", DRV_GRP3), + MTK_PIN(213, "DVP_CS", DRV_GRP3), + MTK_PIN(214, "DVP_CK", DRV_GRP3), + MTK_PIN(215, "DVP_DI", DRV_GRP3), + MTK_PIN(216, "DVP_DO", DRV_GRP3), + MTK_PIN(217, "AP_CS", DRV_GRP3), + MTK_PIN(218, "AP_CK", DRV_GRP3), + MTK_PIN(219, "AP_DI", DRV_GRP3), + MTK_PIN(220, "AP_DO", DRV_GRP3), + MTK_PIN(221, "DVD_BCLK", DRV_GRP3), + MTK_PIN(222, "T8032_CLK", DRV_GRP3), + MTK_PIN(223, "AP_BCLK", DRV_GRP3), + MTK_PIN(224, "HOST_CS", DRV_GRP3), + MTK_PIN(225, "HOST_CK", DRV_GRP3), + MTK_PIN(226, "HOST_DO0", DRV_GRP3), + MTK_PIN(227, "HOST_DO1", DRV_GRP3), + MTK_PIN(228, "SLV_CS", DRV_GRP3), + MTK_PIN(229, "SLV_CK", DRV_GRP3), + MTK_PIN(230, "SLV_DI0", DRV_GRP3), + MTK_PIN(231, "SLV_DI1", DRV_GRP3), + MTK_PIN(232, "AP2DSP_INT", DRV_GRP3), + MTK_PIN(233, "AP2DSP_INT_CLR", DRV_GRP3), + MTK_PIN(234, "DSP2AP_INT", DRV_GRP3), + MTK_PIN(235, "DSP2AP_INT_CLR", DRV_GRP3), + MTK_PIN(236, "EXT_SDIO3", DRV_GRP1), + MTK_PIN(237, "EXT_SDIO2", DRV_GRP1), + MTK_PIN(238, "EXT_SDIO1", DRV_GRP1), + MTK_PIN(239, "EXT_SDIO0", DRV_GRP1), + MTK_PIN(240, "EXT_XCS", DRV_GRP1), + MTK_PIN(241, "EXT_SCK", DRV_GRP1), + MTK_PIN(242, "URTS2", DRV_GRP1), + MTK_PIN(243, "UCTS2", DRV_GRP1), + MTK_PIN(244, "HDMI_SDA_RX", DRV_FIXED), + MTK_PIN(245, "HDMI_SCL_RX", DRV_FIXED), + MTK_PIN(246, "MHL_SENCE", DRV_FIXED), + MTK_PIN(247, "HDMI_HPD_CBUS_RX", DRV_FIXED), + MTK_PIN(248, "HDMI_TESTOUTP_RX", DRV_GRP1), + MTK_PIN(249, "MSDC0E_RSTB", DRV_GRP4), + MTK_PIN(250, "MSDC0E_DAT7", DRV_GRP4), + MTK_PIN(251, "MSDC0E_DAT6", DRV_GRP4), + MTK_PIN(252, "MSDC0E_DAT5", DRV_GRP4), + MTK_PIN(253, "MSDC0E_DAT4", DRV_GRP4), + MTK_PIN(254, "MSDC0E_DAT3", DRV_GRP4), + MTK_PIN(255, "MSDC0E_DAT2", DRV_GRP4), + MTK_PIN(256, "MSDC0E_DAT1", DRV_GRP4), + MTK_PIN(257, "MSDC0E_DAT0", DRV_GRP4), + MTK_PIN(258, "MSDC0E_CMD", DRV_GRP4), + MTK_PIN(259, "MSDC0E_CLK", DRV_GRP4), + MTK_PIN(260, "MSDC0E_DSL", DRV_GRP4), + MTK_PIN(261, "MSDC1_INS", DRV_GRP4), + MTK_PIN(262, "G2_TXEN", DRV_GRP1), + MTK_PIN(263, "G2_TXD3", DRV_GRP1), + MTK_PIN(264, "G2_TXD2", DRV_GRP1), + MTK_PIN(265, "G2_TXD1", DRV_GRP1), + MTK_PIN(266, "G2_TXD0", DRV_GRP1), + MTK_PIN(267, "G2_TXC", DRV_GRP1), + MTK_PIN(268, "G2_RXC", DRV_GRP1), + MTK_PIN(269, "G2_RXD0", DRV_GRP1), + MTK_PIN(270, "G2_RXD1", DRV_GRP1), + MTK_PIN(271, "G2_RXD2", DRV_GRP1), + MTK_PIN(272, "G2_RXD3", DRV_GRP1), + MTK_PIN(273, "ESW_INT", DRV_GRP1), + MTK_PIN(274, "G2_RXDV", DRV_GRP1), + MTK_PIN(275, "MDC", DRV_GRP1), + MTK_PIN(276, "MDIO", DRV_GRP1), + MTK_PIN(277, "ESW_RST", DRV_GRP1), + MTK_PIN(278, "JTAG_RESET", DRV_GRP3), + MTK_PIN(279, "USB3_RES_BOND", DRV_GRP1), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* AUDIO EXT CLK */ +static int mt7623_aud_ext_clk0_pins[] = { 208, }; +static int mt7623_aud_ext_clk0_funcs[] = { 1, }; +static int mt7623_aud_ext_clk1_pins[] = { 209, }; +static int mt7623_aud_ext_clk1_funcs[] = { 1, }; + +/* DISP PWM */ +static int mt7623_disp_pwm_0_pins[] = { 72, }; +static int mt7623_disp_pwm_0_funcs[] = { 5, }; +static int mt7623_disp_pwm_1_pins[] = { 203, }; +static int mt7623_disp_pwm_1_funcs[] = { 2, }; +static int mt7623_disp_pwm_2_pins[] = { 208, }; +static int mt7623_disp_pwm_2_funcs[] = { 5, }; + +/* ESW */ +static int mt7623_esw_int_pins[] = { 273, }; +static int mt7623_esw_int_funcs[] = { 1, }; +static int mt7623_esw_rst_pins[] = { 277, }; +static int mt7623_esw_rst_funcs[] = { 1, }; + +/* EPHY */ +static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268, + 269, 270, 271, 272, 274, }; +static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* EXT_SDIO */ +static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, }; +static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, }; + +/* HDMI RX */ +static int mt7623_hdmi_rx_pins[] = { 247, 248, }; +static int mt7623_hdmi_rx_funcs[] = { 1, 1 }; +static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, }; +static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 }; + +/* HDMI TX */ +static int mt7623_hdmi_cec_pins[] = { 122, }; +static int mt7623_hdmi_cec_funcs[] = { 1, }; +static int mt7623_hdmi_htplg_pins[] = { 123, }; +static int mt7623_hdmi_htplg_funcs[] = { 1, }; +static int mt7623_hdmi_i2c_pins[] = { 124, 125, }; +static int mt7623_hdmi_i2c_funcs[] = { 1, 1 }; + +/* I2C */ +static int mt7623_i2c0_pins[] = { 75, 76, }; +static int mt7623_i2c0_funcs[] = { 1, 1, }; +static int mt7623_i2c1_0_pins[] = { 57, 58, }; +static int mt7623_i2c1_0_funcs[] = { 1, 1, }; +static int mt7623_i2c1_1_pins[] = { 242, 243, }; +static int mt7623_i2c1_1_funcs[] = { 4, 4, }; +static int mt7623_i2c1_2_pins[] = { 85, 86, }; +static int mt7623_i2c1_2_funcs[] = { 3, 3, }; +static int mt7623_i2c1_3_pins[] = { 105, 106, }; +static int mt7623_i2c1_3_funcs[] = { 3, 3, }; +static int mt7623_i2c1_4_pins[] = { 124, 125, }; +static int mt7623_i2c1_4_funcs[] = { 4, 4, }; +static int mt7623_i2c2_0_pins[] = { 77, 78, }; +static int mt7623_i2c2_0_funcs[] = { 1, 1, }; +static int mt7623_i2c2_1_pins[] = { 89, 90, }; +static int mt7623_i2c2_1_funcs[] = { 3, 3, }; +static int mt7623_i2c2_2_pins[] = { 109, 110, }; +static int mt7623_i2c2_2_funcs[] = { 3, 3, }; +static int mt7623_i2c2_3_pins[] = { 122, 123, }; +static int mt7623_i2c2_3_funcs[] = { 4, 4, }; + +/* I2S */ +static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, }; +static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, }; +static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, }; +static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static int mt7623_i2s2_data_in_pins[] = { 51, }; +static int mt7623_i2s2_data_in_funcs[] = { 1, }; +static int mt7623_i2s2_data_0_pins[] = { 203, }; +static int mt7623_i2s2_data_0_funcs[] = { 9, }; +static int mt7623_i2s2_data_1_pins[] = { 38, }; +static int mt7623_i2s2_data_1_funcs[] = { 4, }; +static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, }; +static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, }; +static int mt7623_i2s3_data_in_pins[] = { 190, }; +static int mt7623_i2s3_data_in_funcs[] = { 1, }; +static int mt7623_i2s3_data_0_pins[] = { 204, }; +static int mt7623_i2s3_data_0_funcs[] = { 9, }; +static int mt7623_i2s3_data_1_pins[] = { 2, }; +static int mt7623_i2s3_data_1_funcs[] = { 0, }; +static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, }; +static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, }; +static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, }; +static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, }; + +/* IR */ +static int mt7623_ir_pins[] = { 46, }; +static int mt7623_ir_funcs[] = { 1, }; + +/* LCD */ +static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98, + 99, 100, }; +static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static int mt7623_dsi_te_pins[] = { 84, }; +static int mt7623_dsi_te_funcs[] = { 1, }; +static int mt7623_lcm_rst_pins[] = { 83, }; +static int mt7623_lcm_rst_funcs[] = { 1, }; + +/* MDC/MDIO */ +static int mt7623_mdc_mdio_pins[] = { 275, 276, }; +static int mt7623_mdc_mdio_funcs[] = { 1, 1, }; + +/* MSDC */ +static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118, + 119, 120, 121, }; +static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, }; +static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc1_ins_pins[] = { 261, }; +static int mt7623_msdc1_ins_funcs[] = { 1, }; +static int mt7623_msdc1_wp_0_pins[] = { 29, }; +static int mt7623_msdc1_wp_0_funcs[] = { 1, }; +static int mt7623_msdc1_wp_1_pins[] = { 55, }; +static int mt7623_msdc1_wp_1_funcs[] = { 3, }; +static int mt7623_msdc1_wp_2_pins[] = { 209, }; +static int mt7623_msdc1_wp_2_funcs[] = { 2, }; +static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, }; +static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256, + 257, 258, 259, 260, }; +static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* NAND */ +static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115, + 116, 117, 118, 119, 120, 121, }; +static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4, 4, }; +static int mt7623_nandc_ceb0_pins[] = { 45, }; +static int mt7623_nandc_ceb0_funcs[] = { 1, }; +static int mt7623_nandc_ceb1_pins[] = { 44, }; +static int mt7623_nandc_ceb1_funcs[] = { 1, }; + +/* RTC */ +static int mt7623_rtc_pins[] = { 10, }; +static int mt7623_rtc_funcs[] = { 1, }; + +/* OTG */ +static int mt7623_otg_iddig0_0_pins[] = { 29, }; +static int mt7623_otg_iddig0_0_funcs[] = { 1, }; +static int mt7623_otg_iddig0_1_pins[] = { 44, }; +static int mt7623_otg_iddig0_1_funcs[] = { 2, }; +static int mt7623_otg_iddig0_2_pins[] = { 236, }; +static int mt7623_otg_iddig0_2_funcs[] = { 2, }; +static int mt7623_otg_iddig1_0_pins[] = { 27, }; +static int mt7623_otg_iddig1_0_funcs[] = { 2, }; +static int mt7623_otg_iddig1_1_pins[] = { 47, }; +static int mt7623_otg_iddig1_1_funcs[] = { 2, }; +static int mt7623_otg_iddig1_2_pins[] = { 238, }; +static int mt7623_otg_iddig1_2_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus0_0_pins[] = { 28, }; +static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, }; +static int mt7623_otg_drv_vbus0_1_pins[] = { 45, }; +static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus0_2_pins[] = { 237, }; +static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_0_pins[] = { 26, }; +static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_1_pins[] = { 48, }; +static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, }; +static int mt7623_otg_drv_vbus1_2_pins[] = { 239, }; +static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, }; + +/* PCIE */ +static int mt7623_pcie0_0_perst_pins[] = { 208, }; +static int mt7623_pcie0_0_perst_funcs[] = { 3, }; +static int mt7623_pcie0_1_perst_pins[] = { 22, }; +static int mt7623_pcie0_1_perst_funcs[] = { 2, }; +static int mt7623_pcie1_0_perst_pins[] = { 209, }; +static int mt7623_pcie1_0_perst_funcs[] = { 3, }; +static int mt7623_pcie1_1_perst_pins[] = { 23, }; +static int mt7623_pcie1_1_perst_funcs[] = { 2, }; +static int mt7623_pcie2_0_perst_pins[] = { 24, }; +static int mt7623_pcie2_0_perst_funcs[] = { 2, }; +static int mt7623_pcie2_1_perst_pins[] = { 29, }; +static int mt7623_pcie2_1_perst_funcs[] = { 6, }; +static int mt7623_pcie0_0_wake_pins[] = { 28, }; +static int mt7623_pcie0_0_wake_funcs[] = { 6, }; +static int mt7623_pcie0_1_wake_pins[] = { 251, }; +static int mt7623_pcie0_1_wake_funcs[] = { 6, }; +static int mt7623_pcie1_0_wake_pins[] = { 27, }; +static int mt7623_pcie1_0_wake_funcs[] = { 6, }; +static int mt7623_pcie1_1_wake_pins[] = { 253, }; +static int mt7623_pcie1_1_wake_funcs[] = { 6, }; +static int mt7623_pcie2_0_wake_pins[] = { 26, }; +static int mt7623_pcie2_0_wake_funcs[] = { 6, }; +static int mt7623_pcie2_1_wake_pins[] = { 255, }; +static int mt7623_pcie2_1_wake_funcs[] = { 6, }; +static int mt7623_pcie0_clkreq_pins[] = { 250, }; +static int mt7623_pcie0_clkreq_funcs[] = { 6, }; +static int mt7623_pcie1_clkreq_pins[] = { 252, }; +static int mt7623_pcie1_clkreq_funcs[] = { 6, }; +static int mt7623_pcie2_clkreq_pins[] = { 254, }; +static int mt7623_pcie2_clkreq_funcs[] = { 6, }; +/* the pcie_*_rev are only used for MT7623 */ +static int mt7623_pcie0_0_rev_perst_pins[] = { 208, }; +static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie0_1_rev_perst_pins[] = { 22, }; +static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, }; +static int mt7623_pcie1_0_rev_perst_pins[] = { 209, }; +static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie1_1_rev_perst_pins[] = { 23, }; +static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, }; +static int mt7623_pcie2_0_rev_perst_pins[] = { 24, }; +static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, }; +static int mt7623_pcie2_1_rev_perst_pins[] = { 29, }; +static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, }; + +/* PCM */ +static int mt7623_pcm_clk_0_pins[] = { 18, }; +static int mt7623_pcm_clk_0_funcs[] = { 1, }; +static int mt7623_pcm_clk_1_pins[] = { 17, }; +static int mt7623_pcm_clk_1_funcs[] = { 3, }; +static int mt7623_pcm_clk_2_pins[] = { 35, }; +static int mt7623_pcm_clk_2_funcs[] = { 3, }; +static int mt7623_pcm_clk_3_pins[] = { 50, }; +static int mt7623_pcm_clk_3_funcs[] = { 3, }; +static int mt7623_pcm_clk_4_pins[] = { 74, }; +static int mt7623_pcm_clk_4_funcs[] = { 3, }; +static int mt7623_pcm_clk_5_pins[] = { 191, }; +static int mt7623_pcm_clk_5_funcs[] = { 3, }; +static int mt7623_pcm_clk_6_pins[] = { 196, }; +static int mt7623_pcm_clk_6_funcs[] = { 3, }; +static int mt7623_pcm_sync_0_pins[] = { 19, }; +static int mt7623_pcm_sync_0_funcs[] = { 1, }; +static int mt7623_pcm_sync_1_pins[] = { 30, }; +static int mt7623_pcm_sync_1_funcs[] = { 3, }; +static int mt7623_pcm_sync_2_pins[] = { 36, }; +static int mt7623_pcm_sync_2_funcs[] = { 3, }; +static int mt7623_pcm_sync_3_pins[] = { 52, }; +static int mt7623_pcm_sync_3_funcs[] = { 31, }; +static int mt7623_pcm_sync_4_pins[] = { 73, }; +static int mt7623_pcm_sync_4_funcs[] = { 3, }; +static int mt7623_pcm_sync_5_pins[] = { 192, }; +static int mt7623_pcm_sync_5_funcs[] = { 3, }; +static int mt7623_pcm_sync_6_pins[] = { 197, }; +static int mt7623_pcm_sync_6_funcs[] = { 3, }; +static int mt7623_pcm_rx_0_pins[] = { 20, }; +static int mt7623_pcm_rx_0_funcs[] = { 1, }; +static int mt7623_pcm_rx_1_pins[] = { 16, }; +static int mt7623_pcm_rx_1_funcs[] = { 3, }; +static int mt7623_pcm_rx_2_pins[] = { 34, }; +static int mt7623_pcm_rx_2_funcs[] = { 3, }; +static int mt7623_pcm_rx_3_pins[] = { 51, }; +static int mt7623_pcm_rx_3_funcs[] = { 3, }; +static int mt7623_pcm_rx_4_pins[] = { 72, }; +static int mt7623_pcm_rx_4_funcs[] = { 3, }; +static int mt7623_pcm_rx_5_pins[] = { 190, }; +static int mt7623_pcm_rx_5_funcs[] = { 3, }; +static int mt7623_pcm_rx_6_pins[] = { 195, }; +static int mt7623_pcm_rx_6_funcs[] = { 3, }; +static int mt7623_pcm_tx_0_pins[] = { 21, }; +static int mt7623_pcm_tx_0_funcs[] = { 1, }; +static int mt7623_pcm_tx_1_pins[] = { 32, }; +static int mt7623_pcm_tx_1_funcs[] = { 3, }; +static int mt7623_pcm_tx_2_pins[] = { 33, }; +static int mt7623_pcm_tx_2_funcs[] = { 3, }; +static int mt7623_pcm_tx_3_pins[] = { 38, }; +static int mt7623_pcm_tx_3_funcs[] = { 3, }; +static int mt7623_pcm_tx_4_pins[] = { 49, }; +static int mt7623_pcm_tx_4_funcs[] = { 3, }; +static int mt7623_pcm_tx_5_pins[] = { 189, }; +static int mt7623_pcm_tx_5_funcs[] = { 3, }; +static int mt7623_pcm_tx_6_pins[] = { 194, }; +static int mt7623_pcm_tx_6_funcs[] = { 3, }; + +/* PWM */ +static int mt7623_pwm_ch1_0_pins[] = { 203, }; +static int mt7623_pwm_ch1_0_funcs[] = { 1, }; +static int mt7623_pwm_ch1_1_pins[] = { 208, }; +static int mt7623_pwm_ch1_1_funcs[] = { 2, }; +static int mt7623_pwm_ch1_2_pins[] = { 72, }; +static int mt7623_pwm_ch1_2_funcs[] = { 4, }; +static int mt7623_pwm_ch1_3_pins[] = { 88, }; +static int mt7623_pwm_ch1_3_funcs[] = { 3, }; +static int mt7623_pwm_ch1_4_pins[] = { 108, }; +static int mt7623_pwm_ch1_4_funcs[] = { 3, }; +static int mt7623_pwm_ch2_0_pins[] = { 204, }; +static int mt7623_pwm_ch2_0_funcs[] = { 1, }; +static int mt7623_pwm_ch2_1_pins[] = { 53, }; +static int mt7623_pwm_ch2_1_funcs[] = { 5, }; +static int mt7623_pwm_ch2_2_pins[] = { 88, }; +static int mt7623_pwm_ch2_2_funcs[] = { 6, }; +static int mt7623_pwm_ch2_3_pins[] = { 108, }; +static int mt7623_pwm_ch2_3_funcs[] = { 6, }; +static int mt7623_pwm_ch2_4_pins[] = { 209, }; +static int mt7623_pwm_ch2_4_funcs[] = { 5, }; +static int mt7623_pwm_ch3_0_pins[] = { 205, }; +static int mt7623_pwm_ch3_0_funcs[] = { 1, }; +static int mt7623_pwm_ch3_1_pins[] = { 55, }; +static int mt7623_pwm_ch3_1_funcs[] = { 5, }; +static int mt7623_pwm_ch3_2_pins[] = { 89, }; +static int mt7623_pwm_ch3_2_funcs[] = { 6, }; +static int mt7623_pwm_ch3_3_pins[] = { 109, }; +static int mt7623_pwm_ch3_3_funcs[] = { 6, }; +static int mt7623_pwm_ch4_0_pins[] = { 206, }; +static int mt7623_pwm_ch4_0_funcs[] = { 1, }; +static int mt7623_pwm_ch4_1_pins[] = { 90, }; +static int mt7623_pwm_ch4_1_funcs[] = { 6, }; +static int mt7623_pwm_ch4_2_pins[] = { 110, }; +static int mt7623_pwm_ch4_2_funcs[] = { 6, }; +static int mt7623_pwm_ch4_3_pins[] = { 124, }; +static int mt7623_pwm_ch4_3_funcs[] = { 5, }; +static int mt7623_pwm_ch5_0_pins[] = { 207, }; +static int mt7623_pwm_ch5_0_funcs[] = { 1, }; +static int mt7623_pwm_ch5_1_pins[] = { 125, }; +static int mt7623_pwm_ch5_1_funcs[] = { 5, }; + +/* PWRAP */ +static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, }; +static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; + +/* SPDIF */ +static int mt7623_spdif_in0_0_pins[] = { 56, }; +static int mt7623_spdif_in0_0_funcs[] = { 3, }; +static int mt7623_spdif_in0_1_pins[] = { 201, }; +static int mt7623_spdif_in0_1_funcs[] = { 1, }; +static int mt7623_spdif_in1_0_pins[] = { 54, }; +static int mt7623_spdif_in1_0_funcs[] = { 3, }; +static int mt7623_spdif_in1_1_pins[] = { 202, }; +static int mt7623_spdif_in1_1_funcs[] = { 1, }; +static int mt7623_spdif_out_pins[] = { 202, }; +static int mt7623_spdif_out_funcs[] = { 1, }; + +/* SPI */ +static int mt7623_spi0_pins[] = { 53, 54, 55, 56, }; +static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, }; +static int mt7623_spi1_pins[] = { 7, 199, 8, 9, }; +static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, }; +static int mt7623_spi2_pins[] = { 101, 104, 102, 103, }; +static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, }; + +/* UART */ +static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, }; +static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, }; +static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, }; +static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, }; +static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart0_rts_cts_pins[] = { 22, 23, }; +static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, }; +static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, }; +static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, }; +static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, }; +static int mt7623_uart1_rts_cts_pins[] = { 24, 25, }; +static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, }; +static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, }; +static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, }; +static int mt7623_uart2_rts_cts_pins[] = { 242, 243, }; +static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, }; +static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, }; +static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, }; +static int mt7623_uart3_rts_cts_pins[] = { 26, 27, }; +static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, }; + +/* Watchdog */ +static int mt7623_watchdog_0_pins[] = { 11, }; +static int mt7623_watchdog_0_funcs[] = { 1, }; +static int mt7623_watchdog_1_pins[] = { 121, }; +static int mt7623_watchdog_1_funcs[] = { 5, }; + +static const struct mtk_group_desc mt7623_groups[] = { + PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0), + PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1), + PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te), + PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0), + PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1), + PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2), + PINCTRL_PIN_GROUP("ephy", mt7623_ephy), + PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int), + PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst), + PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio), + PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec), + PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg), + PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c), + PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx), + PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c), + PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0), + PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0), + PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1), + PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2), + PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3), + PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4), + PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1), + PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2), + PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3), + PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0), + PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1), + PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4), + PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5), + PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk), + PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk), + PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in), + PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in), + PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0), + PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1), + PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0), + PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1), + PINCTRL_PIN_GROUP("ir", mt7623_ir), + PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst), + PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio), + PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx), + PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0), + PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1), + PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins), + PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0), + PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1), + PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2), + PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2), + PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3), + PINCTRL_PIN_GROUP("nandc", mt7623_nandc), + PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0), + PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1), + PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0), + PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1), + PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2), + PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0), + PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1), + PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2), + PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0), + PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1), + PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2), + PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0), + PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1), + PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2), + PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst), + PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst), + PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst), + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst), + PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst), + PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst), + PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst), + PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst), + PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst), + PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst), + PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst), + PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst), + PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake), + PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake), + PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake), + PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake), + PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake), + PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake), + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq), + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq), + PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq), + PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0), + PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1), + PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2), + PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3), + PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4), + PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5), + PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6), + PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0), + PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1), + PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2), + PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3), + PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4), + PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5), + PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6), + PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0), + PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1), + PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2), + PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3), + PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4), + PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5), + PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6), + PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0), + PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1), + PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2), + PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3), + PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4), + PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5), + PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6), + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0), + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1), + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2), + PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3), + PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4), + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0), + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1), + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2), + PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3), + PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4), + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0), + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1), + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2), + PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3), + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0), + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1), + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2), + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3), + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0), + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1), + PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap), + PINCTRL_PIN_GROUP("rtc", mt7623_rtc), + PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0), + PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1), + PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0), + PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1), + PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out), + PINCTRL_PIN_GROUP("spi0", mt7623_spi0), + PINCTRL_PIN_GROUP("spi1", mt7623_spi1), + PINCTRL_PIN_GROUP("spi2", mt7623_spi2), + PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd), + PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd), + PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd), + PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd), + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd), + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd), + PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd), + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd), + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd), + PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd), + PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts), + PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts), + PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts), + PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts), + PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0), + PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ + +static const char *const mt7623_aud_clk_groups[] = { "aud_ext_clk0", + "aud_ext_clk1", }; +static const char *const mt7623_disp_pwm_groups[] = { "disp_pwm_0", + "disp_pwm_1", + "disp_pwm_2", }; +static const char *const mt7623_ethernet_groups[] = { "esw_int", "esw_rst", + "ephy", "mdc_mdio", }; +static const char *const mt7623_ext_sdio_groups[] = { "ext_sdio", }; +static const char *const mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg", + "hdmi_i2c", "hdmi_rx", + "hdmi_rx_i2c", }; +static const char *const mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", + "i2c1_2", "i2c1_3", "i2c1_4", + "i2c2_0", "i2c2_1", "i2c2_2", + "i2c2_3", }; +static const char *const mt7623_i2s_groups[] = { "i2s0", "i2s1", + "i2s2_bclk_lrclk_mclk", + "i2s3_bclk_lrclk_mclk", + "i2s4", "i2s5", + "i2s2_data_in", "i2s3_data_in", + "i2s2_data_0", "i2s2_data_1", + "i2s3_data_0", "i2s3_data_1",}; +static const char *const mt7623_ir_groups[] = { "ir", }; +static const char *const mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", + "mipi_tx", }; +static const char *const mt7623_msdc_groups[] = { "msdc0", "msdc1", + "msdc1_ins", "msdc1_wp_0", + "msdc1_wp_1", "msdc1_wp_2", + "msdc2", "msdc3", }; +static const char *const mt7623_nandc_groups[] = { "nandc", "nandc_ceb0", + "nandc_ceb1", }; +static const char *const mt7623_otg_groups[] = { "otg_iddig0_0", + "otg_iddig0_1", + "otg_iddig0_2", + "otg_iddig1_0", + "otg_iddig1_1", + "otg_iddig1_2", + "otg_drv_vbus0_0", + "otg_drv_vbus0_1", + "otg_drv_vbus0_2", + "otg_drv_vbus1_0", + "otg_drv_vbus1_1", + "otg_drv_vbus1_2", }; +static const char *const mt7623_pcie_groups[] = { "pcie0_0_perst", + "pcie0_1_perst", + "pcie1_0_perst", + "pcie1_1_perst", + "pcie2_0_perst", + "pcie2_1_perst", + "pcie0_0_rev_perst", + "pcie0_1_rev_perst", + "pcie1_0_rev_perst", + "pcie1_1_rev_perst", + "pcie2_0_rev_perst", + "pcie2_1_rev_perst", + "pcie0_0_wake", "pcie0_1_wake", + "pcie2_0_wake", "pcie2_1_wake", + "pcie0_clkreq", "pcie1_clkreq", + "pcie2_clkreq", }; +static const char *const mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1", + "pcm_clk_2", "pcm_clk_3", + "pcm_clk_4", "pcm_clk_5", + "pcm_clk_6", "pcm_sync_0", + "pcm_sync_1", "pcm_sync_2", + "pcm_sync_3", "pcm_sync_4", + "pcm_sync_5", "pcm_sync_6", + "pcm_rx_0", "pcm_rx_1", + "pcm_rx_2", "pcm_rx_3", + "pcm_rx_4", "pcm_rx_5", + "pcm_rx_6", "pcm_tx_0", + "pcm_tx_1", "pcm_tx_2", + "pcm_tx_3", "pcm_tx_4", + "pcm_tx_5", "pcm_tx_6", }; +static const char *const mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", + "pwm_ch1_2", "pwm_ch2_0", + "pwm_ch2_1", "pwm_ch2_2", + "pwm_ch3_0", "pwm_ch3_1", + "pwm_ch3_2", "pwm_ch4_0", + "pwm_ch4_1", "pwm_ch4_2", + "pwm_ch4_3", "pwm_ch5_0", + "pwm_ch5_1", "pwm_ch5_2", + "pwm_ch6_0", "pwm_ch6_1", + "pwm_ch6_2", "pwm_ch6_3", + "pwm_ch7_0", "pwm_ch7_1", + "pwm_ch7_2", }; +static const char *const mt7623_pwrap_groups[] = { "pwrap", }; +static const char *const mt7623_rtc_groups[] = { "rtc", }; +static const char *const mt7623_spi_groups[] = { "spi0", "spi2", "spi2", }; +static const char *const mt7623_spdif_groups[] = { "spdif_in0_0", + "spdif_in0_1", "spdif_in1_0", + "spdif_in1_1", "spdif_out", }; +static const char *const mt7623_uart_groups[] = { "uart0_0_txd_rxd", + "uart0_1_txd_rxd", + "uart0_2_txd_rxd", + "uart0_3_txd_rxd", + "uart1_0_txd_rxd", + "uart1_1_txd_rxd", + "uart1_2_txd_rxd", + "uart2_0_txd_rxd", + "uart2_1_txd_rxd", + "uart3_txd_rxd", + "uart0_rts_cts", + "uart1_rts_cts", + "uart2_rts_cts", + "uart3_rts_cts", }; +static const char *const mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", }; + +static const struct mtk_function_desc mt7623_functions[] = { + {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)}, + {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)}, + {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)}, + {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)}, + {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)}, + {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)}, + {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)}, + {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)}, + {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)}, + {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)}, + {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)}, + {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)}, + {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)}, + {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)}, + {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)}, + {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)}, + {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)}, + {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)}, + {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)}, + {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)}, + {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)}, +}; + +static struct mtk_pinctrl_soc mt7623_data = { + .name = "mt7623_pinctrl", + .reg_cal = mt7623_reg_cals, + .pins = mt7623_pins, + .npins = ARRAY_SIZE(mt7623_pins), + .grps = mt7623_groups, + .ngrps = ARRAY_SIZE(mt7623_groups), + .funcs = mt7623_functions, + .nfuncs = ARRAY_SIZE(mt7623_functions), +}; + +/* + * There are some specific pins have mux functions greater than 8, + * and if we want to switch thees high modes we need to disable + * bonding constraints firstly. + */ +static void mt7623_bonding_disable(struct udevice *dev) +{ + mtk_rmw(dev, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR); + mtk_rmw(dev, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR); + mtk_rmw(dev, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR); +} + +static int mtk_pinctrl_mt7623_probe(struct udevice *dev) +{ + int err; + + err = mtk_pinctrl_common_probe(dev, &mt7623_data); + if (err) + return err; + + mt7623_bonding_disable(dev); + + return 0; +} + +static const struct udevice_id mt7623_pctrl_match[] = { + { .compatible = "mediatek,mt7623-pinctrl", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7623_pinctrl) = { + .name = "mt7623_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7623_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7623_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c new file mode 100644 index 0000000000..aa6d1c2d91 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, false) + +#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1) + +static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = { + PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = { + PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_di_range[] = { + PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_do_range[] = { + PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = { + PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = { + PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = { + PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = { + PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1), + PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1), + PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1), + PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1), + PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1), + PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1), + PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = { + PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4), + PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4), + PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4), + PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4), + PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4), + PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4), + PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4), +}; + +static const struct mtk_pin_reg_calc mt7629_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range), +}; + +static const struct mtk_pin_desc mt7629_pins[] = { + MT7629_PIN(0, "TOP_5G_CLK"), + MT7629_PIN(1, "TOP_5G_DATA"), + MT7629_PIN(2, "WF0_5G_HB0"), + MT7629_PIN(3, "WF0_5G_HB1"), + MT7629_PIN(4, "WF0_5G_HB2"), + MT7629_PIN(5, "WF0_5G_HB3"), + MT7629_PIN(6, "WF0_5G_HB4"), + MT7629_PIN(7, "WF0_5G_HB5"), + MT7629_PIN(8, "WF0_5G_HB6"), + MT7629_PIN(9, "XO_REQ"), + MT7629_PIN(10, "TOP_RST_N"), + MT7629_PIN(11, "SYS_WATCHDOG"), + MT7629_PIN(12, "EPHY_LED0_N_JTDO"), + MT7629_PIN(13, "EPHY_LED1_N_JTDI"), + MT7629_PIN(14, "EPHY_LED2_N_JTMS"), + MT7629_PIN(15, "EPHY_LED3_N_JTCLK"), + MT7629_PIN(16, "EPHY_LED4_N_JTRST_N"), + MT7629_PIN(17, "WF2G_LED_N"), + MT7629_PIN(18, "WF5G_LED_N"), + MT7629_PIN(19, "I2C_SDA"), + MT7629_PIN(20, "I2C_SCL"), + MT7629_PIN(21, "GPIO_9"), + MT7629_PIN(22, "GPIO_10"), + MT7629_PIN(23, "GPIO_11"), + MT7629_PIN(24, "GPIO_12"), + MT7629_PIN(25, "UART1_TXD"), + MT7629_PIN(26, "UART1_RXD"), + MT7629_PIN(27, "UART1_CTS"), + MT7629_PIN(28, "UART1_RTS"), + MT7629_PIN(29, "UART2_TXD"), + MT7629_PIN(30, "UART2_RXD"), + MT7629_PIN(31, "UART2_CTS"), + MT7629_PIN(32, "UART2_RTS"), + MT7629_PIN(33, "MDI_TP_P1"), + MT7629_PIN(34, "MDI_TN_P1"), + MT7629_PIN(35, "MDI_RP_P1"), + MT7629_PIN(36, "MDI_RN_P1"), + MT7629_PIN(37, "MDI_RP_P2"), + MT7629_PIN(38, "MDI_RN_P2"), + MT7629_PIN(39, "MDI_TP_P2"), + MT7629_PIN(40, "MDI_TN_P2"), + MT7629_PIN(41, "MDI_TP_P3"), + MT7629_PIN(42, "MDI_TN_P3"), + MT7629_PIN(43, "MDI_RP_P3"), + MT7629_PIN(44, "MDI_RN_P3"), + MT7629_PIN(45, "MDI_RP_P4"), + MT7629_PIN(46, "MDI_RN_P4"), + MT7629_PIN(47, "MDI_TP_P4"), + MT7629_PIN(48, "MDI_TN_P4"), + MT7629_PIN(49, "SMI_MDC"), + MT7629_PIN(50, "SMI_MDIO"), + MT7629_PIN(51, "PCIE_PERESET_N"), + MT7629_PIN(52, "PWM_0"), + MT7629_PIN(53, "GPIO_0"), + MT7629_PIN(54, "GPIO_1"), + MT7629_PIN(55, "GPIO_2"), + MT7629_PIN(56, "GPIO_3"), + MT7629_PIN(57, "GPIO_4"), + MT7629_PIN(58, "GPIO_5"), + MT7629_PIN(59, "GPIO_6"), + MT7629_PIN(60, "GPIO_7"), + MT7629_PIN(61, "GPIO_8"), + MT7629_PIN(62, "SPI_CLK"), + MT7629_PIN(63, "SPI_CS"), + MT7629_PIN(64, "SPI_MOSI"), + MT7629_PIN(65, "SPI_MISO"), + MT7629_PIN(66, "SPI_WP"), + MT7629_PIN(67, "SPI_HOLD"), + MT7629_PIN(68, "UART0_TXD"), + MT7629_PIN(69, "UART0_RXD"), + MT7629_PIN(70, "TOP_2G_CLK"), + MT7629_PIN(71, "TOP_2G_DATA"), + MT7629_PIN(72, "WF0_2G_HB0"), + MT7629_PIN(73, "WF0_2G_HB1"), + MT7629_PIN(74, "WF0_2G_HB2"), + MT7629_PIN(75, "WF0_2G_HB3"), + MT7629_PIN(76, "WF0_2G_HB4"), + MT7629_PIN(77, "WF0_2G_HB5"), + MT7629_PIN(78, "WF0_2G_HB6"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* WF 5G */ +static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; +static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* LED for EPHY */ +static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; +static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; +static int mt7629_ephy_led0_pins[] = { 12, }; +static int mt7629_ephy_led0_funcs[] = { 1, }; +static int mt7629_ephy_led1_pins[] = { 13, }; +static int mt7629_ephy_led1_funcs[] = { 1, }; +static int mt7629_ephy_led2_pins[] = { 14, }; +static int mt7629_ephy_led2_funcs[] = { 1, }; +static int mt7629_ephy_led3_pins[] = { 15, }; +static int mt7629_ephy_led3_funcs[] = { 1, }; +static int mt7629_ephy_led4_pins[] = { 16, }; +static int mt7629_ephy_led4_funcs[] = { 1, }; +static int mt7629_wf2g_led_pins[] = { 17, }; +static int mt7629_wf2g_led_funcs[] = { 1, }; +static int mt7629_wf5g_led_pins[] = { 18, }; +static int mt7629_wf5g_led_funcs[] = { 1, }; + +/* Watchdog */ +static int mt7629_watchdog_pins[] = { 11, }; +static int mt7629_watchdog_funcs[] = { 1, }; + +/* LED for GPHY */ +static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; +static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; +static int mt7629_gphy_led1_0_pins[] = { 21, }; +static int mt7629_gphy_led1_0_funcs[] = { 2, }; +static int mt7629_gphy_led2_0_pins[] = { 22, }; +static int mt7629_gphy_led2_0_funcs[] = { 2, }; +static int mt7629_gphy_led3_0_pins[] = { 23, }; +static int mt7629_gphy_led3_0_funcs[] = { 2, }; +static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; +static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; +static int mt7629_gphy_led1_1_pins[] = { 57, }; +static int mt7629_gphy_led1_1_funcs[] = { 1, }; +static int mt7629_gphy_led2_1_pins[] = { 58, }; +static int mt7629_gphy_led2_1_funcs[] = { 1, }; +static int mt7629_gphy_led3_1_pins[] = { 59, }; +static int mt7629_gphy_led3_1_funcs[] = { 1, }; + +/* I2C */ +static int mt7629_i2c_0_pins[] = { 19, 20, }; +static int mt7629_i2c_0_funcs[] = { 1, 1, }; +static int mt7629_i2c_1_pins[] = { 53, 54, }; +static int mt7629_i2c_1_funcs[] = { 1, 1, }; + +/* SPI */ +static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; +static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; +static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; +static int mt7629_spi_wp_pins[] = { 66, }; +static int mt7629_spi_wp_funcs[] = { 1, }; +static int mt7629_spi_hold_pins[] = { 67, }; +static int mt7629_spi_hold_funcs[] = { 1, }; + +/* UART */ +static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; +static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; +static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; +static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; +static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; +static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; +static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; +static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; +static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; +static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; +static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; +static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; + +/* MDC/MDIO */ +static int mt7629_mdc_mdio_pins[] = { 49, 50, }; +static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; + +/* PCIE */ +static int mt7629_pcie_pereset_pins[] = { 51, }; +static int mt7629_pcie_pereset_funcs[] = { 1, }; +static int mt7629_pcie_wake_pins[] = { 55, }; +static int mt7629_pcie_wake_funcs[] = { 1, }; +static int mt7629_pcie_clkreq_pins[] = { 56, }; +static int mt7629_pcie_clkreq_funcs[] = { 1, }; + +/* PWM */ +static int mt7629_pwm_0_pins[] = { 52, }; +static int mt7629_pwm_0_funcs[] = { 1, }; +static int mt7629_pwm_1_pins[] = { 61, }; +static int mt7629_pwm_1_funcs[] = { 2, }; + +/* WF 2G */ +static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; +static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; + +/* SNFI */ +static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +/* SPI NOR */ +static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; +static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; + +static const struct mtk_group_desc mt7629_groups[] = { + PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), + PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds), + PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0), + PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1), + PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), + PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), + PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), + PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), + PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), + PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), + PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0), + PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0), + PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0), + PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0), + PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1), + PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1), + PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1), + PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1), + PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0), + PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1), + PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0), + PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1), + PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp), + PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold), + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd), + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd), + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd), + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd), + PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts), + PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts), + PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts), + PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd), + PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio), + PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset), + PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake), + PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq), + PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0), + PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1), + PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g), + PINCTRL_PIN_GROUP("snfi", mt7629_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7629_snor), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7629_ethernet_groups[] = { "mdc_mdio", }; +static const char *const mt7629_i2c_groups[] = { "i2c_0", "i2c_1", }; +static const char *const mt7629_led_groups[] = { "ephy_leds", "ephy_led0", + "ephy_led1", "ephy_led2", + "ephy_led3", "ephy_led4", + "wf2g_led", "wf5g_led", + "gphy_leds_0", "gphy_led1_0", + "gphy_led2_0", "gphy_led3_0", + "gphy_leds_1", "gphy_led1_1", + "gphy_led2_1", "gphy_led3_1",}; +static const char *const mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake", + "pcie_clkreq", }; +static const char *const mt7629_pwm_groups[] = { "pwm_0", "pwm_1", }; +static const char *const mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp", + "spi_hold", }; +static const char *const mt7629_uart_groups[] = { "uart1_0_txd_rxd", + "uart1_1_txd_rxd", + "uart2_0_txd_rxd", + "uart2_1_txd_rxd", + "uart1_0_cts_rts", + "uart1_1_cts_rts", + "uart2_0_cts_rts", + "uart2_1_cts_rts", + "uart0_txd_rxd", }; +static const char *const mt7629_wdt_groups[] = { "watchdog", }; +static const char *const mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; +static const char *const mt7629_flash_groups[] = { "snfi", "spi_nor" }; + +static const struct mtk_function_desc mt7629_functions[] = { + {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, + {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)}, + {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)}, + {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)}, + {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)}, + {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)}, + {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)}, + {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, + {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, + {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, +}; + +static struct mtk_pinctrl_soc mt7629_data = { + .name = "mt7629_pinctrl", + .reg_cal = mt7629_reg_cals, + .pins = mt7629_pins, + .npins = ARRAY_SIZE(mt7629_pins), + .grps = mt7629_groups, + .ngrps = ARRAY_SIZE(mt7629_groups), + .funcs = mt7629_functions, + .nfuncs = ARRAY_SIZE(mt7629_functions), +}; + +static int mtk_pinctrl_mt7629_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7629_data); +} + +static const struct udevice_id mt7629_pctrl_match[] = { + { .compatible = "mediatek,mt7629-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7629_pinctrl) = { + .name = "mt7629_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7629_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7629_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c new file mode 100644 index 0000000000..938cc75496 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" + +/** + * struct mtk_drive_desc - the structure that holds the information + * of the driving current + * @min: the minimum current of this group + * @max: the maximum current of this group + * @step: the step current of this group + * @scal: the weight factor + * + * formula: output = ((input) / step - 1) * scal + */ +struct mtk_drive_desc { + u8 min; + u8 max; + u8 step; + u8 scal; +}; + +/* The groups of drive strength */ +static const struct mtk_drive_desc mtk_drive[] = { + [DRV_GRP0] = { 4, 16, 4, 1 }, + [DRV_GRP1] = { 4, 16, 4, 2 }, + [DRV_GRP2] = { 2, 8, 2, 1 }, + [DRV_GRP3] = { 2, 8, 2, 2 }, + [DRV_GRP4] = { 2, 16, 2, 1 }, +}; + +static const char *mtk_pinctrl_dummy_name = "_dummy"; + +static void mtk_w32(struct udevice *dev, u32 reg, u32 val) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + __raw_writel(val, priv->base + reg); +} + +static u32 mtk_r32(struct udevice *dev, u32 reg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return __raw_readl(priv->base + reg); +} + +static inline int get_count_order(unsigned int count) +{ + int order; + + order = fls(count) - 1; + if (count & (count - 1)) + order++; + return order; +} + +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set) +{ + u32 val; + + val = mtk_r32(dev, reg); + val &= ~mask; + val |= set; + mtk_w32(dev, reg, val); +} + +static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin, + const struct mtk_pin_reg_calc *rc, + struct mtk_pin_field *pfd) +{ + const struct mtk_pin_field_calc *c, *e; + u32 bits; + + c = rc->range; + e = c + rc->nranges; + + while (c < e) { + if (pin >= c->s_pin && pin <= c->e_pin) + break; + c++; + } + + if (c >= e) + return -EINVAL; + + /* Calculated bits as the overall offset the pin is located at, + * if c->fixed is held, that determines the all the pins in the + * range use the same field with the s_pin. + */ + bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits); + + /* Fill pfd from bits. For example 32-bit register applied is assumed + * when c->sz_reg is equal to 32. + */ + pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg); + pfd->bitpos = bits % c->sz_reg; + pfd->mask = (1 << c->x_bits) - 1; + + /* pfd->next is used for indicating that bit wrapping-around happens + * which requires the manipulation for bit 0 starting in the next + * register to form the complete field read/write. + */ + pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0; + + return 0; +} + +static int mtk_hw_pin_field_get(struct udevice *dev, int pin, + int field, struct mtk_pin_field *pfd) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_reg_calc *rc; + + if (field < 0 || field >= PINCTRL_PIN_REG_MAX) + return -EINVAL; + + if (priv->soc->reg_cal && priv->soc->reg_cal[field].range) + rc = &priv->soc->reg_cal[field]; + else + return -EINVAL; + + return mtk_hw_pin_field_lookup(dev, pin, rc, pfd); +} + +static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) +{ + *l = 32 - pf->bitpos; + *h = get_count_order(pf->mask) - *l; +} + +static void mtk_hw_write_cross_field(struct udevice *dev, + struct mtk_pin_field *pf, int value) +{ + int nbits_l, nbits_h; + + mtk_hw_bits_part(pf, &nbits_h, &nbits_l); + + mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos, + (value & pf->mask) << pf->bitpos); + + mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1, + (value & pf->mask) >> nbits_l); +} + +static void mtk_hw_read_cross_field(struct udevice *dev, + struct mtk_pin_field *pf, int *value) +{ + int nbits_l, nbits_h, h, l; + + mtk_hw_bits_part(pf, &nbits_h, &nbits_l); + + l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1); + h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1); + + *value = (h << nbits_l) | l; +} + +static int mtk_hw_set_value(struct udevice *dev, int pin, int field, + int value) +{ + struct mtk_pin_field pf; + int err; + + err = mtk_hw_pin_field_get(dev, pin, field, &pf); + if (err) + return err; + + if (!pf.next) + mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos, + (value & pf.mask) << pf.bitpos); + else + mtk_hw_write_cross_field(dev, &pf, value); + + return 0; +} + +static int mtk_hw_get_value(struct udevice *dev, int pin, int field, + int *value) +{ + struct mtk_pin_field pf; + int err; + + err = mtk_hw_pin_field_get(dev, pin, field, &pf); + if (err) + return err; + + if (!pf.next) + *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask; + else + mtk_hw_read_cross_field(dev, &pf, value); + + return 0; +} + +static int mtk_get_groups_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->ngrps; +} + +static const char *mtk_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->grps[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->pins[selector].name; +} + +static int mtk_get_pins_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->npins; +} + +static const char *mtk_get_group_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->grps[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->grps[selector].name; +} + +static int mtk_get_functions_count(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->soc->nfuncs; +} + +static const char *mtk_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->soc->funcs[selector].name) + return mtk_pinctrl_dummy_name; + + return priv->soc->funcs[selector].name; +} + +static int mtk_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_group_desc *grp = + &priv->soc->grps[group_selector]; + int i; + + for (i = 0; i < grp->num_pins; i++) { + int *pin_modes = grp->data; + + mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, + pin_modes[i]); + } + + return 0; +} + +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param mtk_conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, +}; + +int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; + const struct mtk_drive_desc *tb; + int err = -ENOTSUPP; + + tb = &mtk_drive[desc->drv_n]; + /* 4mA when (e8, e4) = (0, 0) + * 8mA when (e8, e4) = (0, 1) + * 12mA when (e8, e4) = (1, 0) + * 16mA when (e8, e4) = (1, 1) + */ + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { + arg = (arg / tb->step - 1) * tb->scal; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg); + if (err) + return err; + } + + return 0; +} + +static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + int err = 0; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : + (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, + arg & 1); + if (err) + goto err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, + !!(arg & 2)); + if (err) + goto err; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0); + if (err) + goto err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1); + if (err) + goto err; + break; + case PIN_CONFIG_INPUT_ENABLE: + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); + if (err) + goto err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (err) + goto err; + break; + case PIN_CONFIG_OUTPUT: + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1); + if (err) + goto err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg); + if (err) + goto err; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + /* arg = 1: Input mode & SMT enable ; + * arg = 0: Output mode & SMT disable + */ + arg = arg ? 2 : 1; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, + arg & 1); + if (err) + goto err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, + !!(arg & 2)); + if (err) + goto err; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + err = mtk_pinconf_drive_set(dev, pin, arg); + if (err) + goto err; + break; + + default: + err = -ENOTSUPP; + } + +err: + + return err; +} + +static int mtk_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_group_desc *grp = + &priv->soc->grps[group_selector]; + int i, ret; + + for (i = 0; i < grp->num_pins; i++) { + ret = mtk_pinconf_set(dev, grp->pins[i], param, arg); + if (ret) + return ret; + } + + return 0; +} +#endif + +const struct pinctrl_ops mtk_pinctrl_ops = { + .get_pins_count = mtk_get_pins_count, + .get_pin_name = mtk_get_pin_name, + .get_groups_count = mtk_get_groups_count, + .get_group_name = mtk_get_group_name, + .get_functions_count = mtk_get_functions_count, + .get_function_name = mtk_get_function_name, + .pinmux_group_set = mtk_pinmux_group_set, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(mtk_conf_params), + .pinconf_params = mtk_conf_params, + .pinconf_set = mtk_pinconf_set, + .pinconf_group_set = mtk_pinconf_group_set, +#endif + .set_state = pinctrl_generic_set_state, +}; + +static int mtk_gpio_get(struct udevice *dev, unsigned int off) +{ + int val, err; + + err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val); + if (err) + return err; + + return !!val; +} + +static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val) +{ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val); +} + +static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off) +{ + int val, err; + + err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val); + if (err) + return err; + + return val ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off) +{ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0); +} + +static int mtk_gpio_direction_output(struct udevice *dev, + unsigned int off, int val) +{ + mtk_gpio_set(dev, off, val); + + /* And set the requested value */ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1); +} + +static int mtk_gpio_request(struct udevice *dev, unsigned int off, + const char *label) +{ + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0); +} + +static int mtk_gpio_probe(struct udevice *dev) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = priv->soc->name; + uc_priv->gpio_count = priv->soc->npins; + + return 0; +} + +static const struct dm_gpio_ops mtk_gpio_ops = { + .request = mtk_gpio_request, + .set_value = mtk_gpio_set, + .get_value = mtk_gpio_get, + .get_function = mtk_gpio_get_direction, + .direction_input = mtk_gpio_direction_input, + .direction_output = mtk_gpio_direction_output, +}; + +static struct driver mtk_gpio_driver = { + .name = "mediatek_gpio", + .id = UCLASS_GPIO, + .probe = mtk_gpio_probe, + .ops = &mtk_gpio_ops, +}; + +static int mtk_gpiochip_register(struct udevice *parent) +{ + struct uclass_driver *drv; + struct udevice *dev; + int ret; + ofnode node; + + drv = lists_uclass_lookup(UCLASS_GPIO); + if (!drv) + return -ENOENT; + + dev_for_each_subnode(node, parent) + if (ofnode_read_bool(node, "gpio-controller")) { + ret = 0; + break; + } + + if (ret) + return ret; + + ret = device_bind_with_driver_data(parent, &mtk_gpio_driver, + "mediatek_gpio", 0, node, + &dev); + if (ret) + return ret; + + return 0; +} + +int mtk_pinctrl_common_probe(struct udevice *dev, + struct mtk_pinctrl_soc *soc) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (priv->base == (void *)FDT_ADDR_T_NONE) + return -EINVAL; + + priv->soc = soc; + + ret = mtk_gpiochip_register(dev); + if (ret) + return ret; + + return 0; +} diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h new file mode 100644 index 0000000000..86559f0f14 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#ifndef __PINCTRL_MEDIATEK_H__ +#define __PINCTRL_MEDIATEK_H__ + +#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } +#define MTK_PIN(_number, _name, _drv_n) { \ + .number = _number, \ + .name = _name, \ + .drv_n = _drv_n, \ + } + +#define PINCTRL_PIN_GROUP(name, id) \ + { \ + name, \ + id##_pins, \ + ARRAY_SIZE(id##_pins), \ + id##_funcs, \ + } + +#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, _sz_reg, _fixed) { \ + .s_pin = _s_pin, \ + .e_pin = _e_pin, \ + .s_addr = _s_addr, \ + .x_addrs = _x_addrs, \ + .s_bit = _s_bit, \ + .x_bits = _x_bits, \ + .sz_reg = _sz_reg, \ + .fixed = _fixed, \ + } + +/* List these attributes which could be modified for the pin */ +enum { + PINCTRL_PIN_REG_MODE, + PINCTRL_PIN_REG_DIR, + PINCTRL_PIN_REG_DI, + PINCTRL_PIN_REG_DO, + PINCTRL_PIN_REG_IES, + PINCTRL_PIN_REG_SMT, + PINCTRL_PIN_REG_PULLEN, + PINCTRL_PIN_REG_PULLSEL, + PINCTRL_PIN_REG_DRV, + PINCTRL_PIN_REG_MAX, +}; + +/* Group the pins by the driving current */ +enum { + DRV_FIXED, + DRV_GRP0, + DRV_GRP1, + DRV_GRP2, + DRV_GRP3, + DRV_GRP4, +}; + +/** + * struct mtk_pin_field - the structure that holds the information of the field + * used to describe the attribute for the pin + * @offset: the register offset relative to the base address + * @mask: the mask used to filter out the field from the register + * @bitpos: the start bit relative to the register + * @next: the indication that the field would be extended to the + next register + */ +struct mtk_pin_field { + u32 offset; + u32 mask; + u8 bitpos; + u8 next; +}; + +/** + * struct mtk_pin_field_calc - the structure that holds the range providing + * the guide used to look up the relevant field + * @s_pin: the start pin within the range + * @e_pin: the end pin within the range + * @s_addr: the start address for the range + * @x_addrs: the address distance between two consecutive registers + * within the range + * @s_bit: the start bit for the first register within the range + * @x_bits: the bit distance between two consecutive pins within + * the range + * @sz_reg: the size of bits in a register + * @fixed: the consecutive pins share the same bits with the 1st + * pin + */ +struct mtk_pin_field_calc { + u16 s_pin; + u16 e_pin; + u32 s_addr; + u8 x_addrs; + u8 s_bit; + u8 x_bits; + u8 sz_reg; + u8 fixed; +}; + +/** + * struct mtk_pin_reg_calc - the structure that holds all ranges used to + * determine which register the pin would make use of + * for certain pin attribute. + * @range: the start address for the range + * @nranges: the number of items in the range + */ +struct mtk_pin_reg_calc { + const struct mtk_pin_field_calc *range; + unsigned int nranges; +}; + +/** + * struct mtk_pin_desc - the structure that providing information + * for each pin of chips + * @number: unique pin number from the global pin number space + * @name: name for this pin + * @drv_n: the index with the driving group + */ +struct mtk_pin_desc { + unsigned int number; + const char *name; + u8 drv_n; +}; + +/** + * struct mtk_group_desc - generic pin group descriptor + * @name: name of the pin group + * @pins: array of pins that belong to the group + * @num_pins: number of pins in the group + * @data: pin controller driver specific data + */ +struct mtk_group_desc { + const char *name; + int *pins; + int num_pins; + void *data; +}; + +/** + * struct mtk_function_desc - generic function descriptor + * @name: name of the function + * @group_names: array of pin group names + * @num_group_names: number of pin group names + */ +struct mtk_function_desc { + const char *name; + const char * const *group_names; + int num_group_names; +}; + +/* struct mtk_pin_soc - the structure that holds SoC-specific data */ +struct mtk_pinctrl_soc { + const char *name; + const struct mtk_pin_reg_calc *reg_cal; + const struct mtk_pin_desc *pins; + int npins; + const struct mtk_group_desc *grps; + int ngrps; + const struct mtk_function_desc *funcs; + int nfuncs; +}; + +/** + * struct mtk_pinctrl_priv - private data for MTK pinctrl driver + * + * @base: base address of the pinctrl device + * @soc: SoC specific data + */ +struct mtk_pinctrl_priv { + void __iomem *base; + struct mtk_pinctrl_soc *soc; +}; + +extern const struct pinctrl_ops mtk_pinctrl_ops; + +/* A common read-modify-write helper for MediaTek chips */ +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); +int mtk_pinctrl_common_probe(struct udevice *dev, + struct mtk_pinctrl_soc *soc); + +#endif /* __PINCTRL_MEDIATEK_H__ */ diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 27ba8909d7..ee820a57a0 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -1,15 +1,27 @@ if ARCH_MESON config PINCTRL_MESON - depends on PINCTRL_GENERIC + select PINCTRL_GENERIC + bool + +config PINCTRL_MESON_GX_PMX + select PINCTRL_MESON + bool + +config PINCTRL_MESON_AXG_PMX + select PINCTRL_MESON bool config PINCTRL_MESON_GXBB bool "Amlogic Meson GXBB SoC pinctrl driver" - select PINCTRL_MESON + select PINCTRL_MESON_GX_PMX config PINCTRL_MESON_GXL bool "Amlogic Meson GXL SoC pinctrl driver" - select PINCTRL_MESON + select PINCTRL_MESON_GX_PMX + +config PINCTRL_MESON_AXG + bool "Amlogic Meson AXG SoC pinctrl driver" + select PINCTRL_MESON_AXG_PMX endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 965092cd81..707287cd1d 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += pinctrl-meson.o +obj-$(CONFIG_PINCTRL_MESON_GX_PMX) += pinctrl-meson-gx-pmx.o +obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o +obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c new file mode 100644 index 0000000000..c82413d08f --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Jerome Brunet + * Copyright (C) 2017 Xingyu Chen + */ + +#include +#include +#include +#include +#include +#include "pinctrl-meson-axg.h" + +static int meson_axg_pmx_get_bank(struct udevice *dev, unsigned int pin, + struct meson_pmx_bank **bank) +{ + int i; + struct meson_pinctrl *priv = dev_get_priv(dev); + struct meson_axg_pmx_data *pmx = priv->data->pmx_data; + + for (i = 0; i < pmx->num_pmx_banks; i++) + if (pin >= pmx->pmx_banks[i].first && + pin <= pmx->pmx_banks[i].last) { + *bank = &pmx->pmx_banks[i]; + return 0; + } + + return -EINVAL; +} + +static int meson_axg_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank, + unsigned int pin, + unsigned int *reg, + unsigned int *offset) +{ + int shift; + + shift = pin - bank->first; + + *reg = bank->reg + (bank->offset + (shift << 2)) / 32; + *offset = (bank->offset + (shift << 2)) % 32; + + return 0; +} + +static int meson_axg_pmx_update_function(struct udevice *dev, + unsigned int pin, unsigned int func) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + struct meson_pmx_bank *bank; + unsigned int offset; + unsigned int reg; + unsigned int tmp; + int ret; + + ret = meson_axg_pmx_get_bank(dev, pin, &bank); + if (ret) + return ret; + + meson_axg_pmx_calc_reg_and_offset(bank, pin, ®, &offset); + + tmp = readl(priv->reg_mux + (reg << 2)); + tmp &= ~(0xf << offset); + tmp |= (func & 0xf) << offset; + writel(tmp, priv->reg_mux + (reg << 2)); + + return ret; +} + +static int meson_axg_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + const struct meson_pmx_group *group; + const struct meson_pmx_func *func; + struct meson_pmx_axg_data *pmx_data; + int i, ret; + + group = &priv->data->groups[group_selector]; + pmx_data = (struct meson_pmx_axg_data *)group->data; + func = &priv->data->funcs[func_selector]; + + debug("pinmux: set group %s func %s\n", group->name, func->name); + + for (i = 0; i < group->num_pins; i++) { + ret = meson_axg_pmx_update_function(dev, group->pins[i], + pmx_data->func); + if (ret) + return ret; + } + + return 0; +} + +const struct pinctrl_ops meson_axg_pinctrl_ops = { + .get_groups_count = meson_pinctrl_get_groups_count, + .get_group_name = meson_pinctrl_get_group_name, + .get_functions_count = meson_pinmux_get_functions_count, + .get_function_name = meson_pinmux_get_function_name, + .pinmux_group_set = meson_axg_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +static int meson_axg_gpio_request(struct udevice *dev, + unsigned int offset, const char *label) +{ + return meson_axg_pmx_update_function(dev->parent, offset, 0); +} + +static const struct dm_gpio_ops meson_axg_gpio_ops = { + .request = meson_axg_gpio_request, + .set_value = meson_gpio_set, + .get_value = meson_gpio_get, + .get_function = meson_gpio_get_direction, + .direction_input = meson_gpio_direction_input, + .direction_output = meson_gpio_direction_output, +}; + +const struct driver meson_axg_gpio_driver = { + .name = "meson-axg-gpio", + .id = UCLASS_GPIO, + .probe = meson_gpio_probe, + .ops = &meson_axg_gpio_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c new file mode 100644 index 0000000000..3bbbe817b4 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -0,0 +1,979 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright (C) 2018 Neil Armstrong + * + * Based on code from Linux kernel: + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + */ + +#include +#include +#include +#include + +#include "pinctrl-meson-axg.h" + +#define EE_OFF 15 + +/* emmc */ +static const unsigned int emmc_nand_d0_pins[] = {BOOT_0}; +static const unsigned int emmc_nand_d1_pins[] = {BOOT_1}; +static const unsigned int emmc_nand_d2_pins[] = {BOOT_2}; +static const unsigned int emmc_nand_d3_pins[] = {BOOT_3}; +static const unsigned int emmc_nand_d4_pins[] = {BOOT_4}; +static const unsigned int emmc_nand_d5_pins[] = {BOOT_5}; +static const unsigned int emmc_nand_d6_pins[] = {BOOT_6}; +static const unsigned int emmc_nand_d7_pins[] = {BOOT_7}; + +static const unsigned int emmc_clk_pins[] = {BOOT_8}; +static const unsigned int emmc_cmd_pins[] = {BOOT_10}; +static const unsigned int emmc_ds_pins[] = {BOOT_13}; + +/* nand */ +static const unsigned int nand_ce0_pins[] = {BOOT_8}; +static const unsigned int nand_ale_pins[] = {BOOT_9}; +static const unsigned int nand_cle_pins[] = {BOOT_10}; +static const unsigned int nand_wen_clk_pins[] = {BOOT_11}; +static const unsigned int nand_ren_wr_pins[] = {BOOT_12}; +static const unsigned int nand_rb0_pins[] = {BOOT_13}; + +/* nor */ +static const unsigned int nor_hold_pins[] = {BOOT_3}; +static const unsigned int nor_d_pins[] = {BOOT_4}; +static const unsigned int nor_q_pins[] = {BOOT_5}; +static const unsigned int nor_c_pins[] = {BOOT_6}; +static const unsigned int nor_wp_pins[] = {BOOT_9}; +static const unsigned int nor_cs_pins[] = {BOOT_14}; + +/* sdio */ +static const unsigned int sdio_d0_pins[] = {GPIOX_0}; +static const unsigned int sdio_d1_pins[] = {GPIOX_1}; +static const unsigned int sdio_d2_pins[] = {GPIOX_2}; +static const unsigned int sdio_d3_pins[] = {GPIOX_3}; +static const unsigned int sdio_clk_pins[] = {GPIOX_4}; +static const unsigned int sdio_cmd_pins[] = {GPIOX_5}; + +/* spi0 */ +static const unsigned int spi0_clk_pins[] = {GPIOZ_0}; +static const unsigned int spi0_mosi_pins[] = {GPIOZ_1}; +static const unsigned int spi0_miso_pins[] = {GPIOZ_2}; +static const unsigned int spi0_ss0_pins[] = {GPIOZ_3}; +static const unsigned int spi0_ss1_pins[] = {GPIOZ_4}; +static const unsigned int spi0_ss2_pins[] = {GPIOZ_5}; + +/* spi1 */ +static const unsigned int spi1_clk_x_pins[] = {GPIOX_19}; +static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17}; +static const unsigned int spi1_miso_x_pins[] = {GPIOX_18}; +static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16}; + +static const unsigned int spi1_clk_a_pins[] = {GPIOA_4}; +static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2}; +static const unsigned int spi1_miso_a_pins[] = {GPIOA_3}; +static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5}; +static const unsigned int spi1_ss1_pins[] = {GPIOA_6}; + +/* i2c0 */ +static const unsigned int i2c0_sck_pins[] = {GPIOZ_6}; +static const unsigned int i2c0_sda_pins[] = {GPIOZ_7}; + +/* i2c1 */ +static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8}; +static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9}; + +static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16}; +static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17}; + +/* i2c2 */ +static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18}; +static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19}; + +static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17}; +static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18}; + +/* i2c3 */ +static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6}; +static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7}; + +static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12}; +static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13}; + +static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19}; +static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20}; + +/* uart_a */ +static const unsigned int uart_rts_a_pins[] = {GPIOX_11}; +static const unsigned int uart_cts_a_pins[] = {GPIOX_10}; +static const unsigned int uart_tx_a_pins[] = {GPIOX_8}; +static const unsigned int uart_rx_a_pins[] = {GPIOX_9}; + +/* uart_b */ +static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0}; +static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1}; +static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2}; +static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3}; + +static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18}; +static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19}; +static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16}; +static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17}; + +/* uart_ao_b */ +static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8}; +static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9}; +static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6}; +static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7}; + +/* pwm_a */ +static const unsigned int pwm_a_z_pins[] = {GPIOZ_5}; + +static const unsigned int pwm_a_x18_pins[] = {GPIOX_18}; +static const unsigned int pwm_a_x20_pins[] = {GPIOX_20}; + +static const unsigned int pwm_a_a_pins[] = {GPIOA_14}; + +/* pwm_b */ +static const unsigned int pwm_b_z_pins[] = {GPIOZ_4}; + +static const unsigned int pwm_b_x_pins[] = {GPIOX_19}; + +static const unsigned int pwm_b_a_pins[] = {GPIOA_15}; + +/* pwm_c */ +static const unsigned int pwm_c_x10_pins[] = {GPIOX_10}; +static const unsigned int pwm_c_x17_pins[] = {GPIOX_17}; + +static const unsigned int pwm_c_a_pins[] = {GPIOA_16}; + +/* pwm_d */ +static const unsigned int pwm_d_x11_pins[] = {GPIOX_11}; +static const unsigned int pwm_d_x16_pins[] = {GPIOX_16}; + +/* pwm_vs */ +static const unsigned int pwm_vs_pins[] = {GPIOA_0}; + +/* spdif_in */ +static const unsigned int spdif_in_z_pins[] = {GPIOZ_4}; + +static const unsigned int spdif_in_a1_pins[] = {GPIOA_1}; +static const unsigned int spdif_in_a7_pins[] = {GPIOA_7}; +static const unsigned int spdif_in_a19_pins[] = {GPIOA_19}; +static const unsigned int spdif_in_a20_pins[] = {GPIOA_20}; + +/* spdif_out */ +static const unsigned int spdif_out_z_pins[] = {GPIOZ_5}; + +static const unsigned int spdif_out_a1_pins[] = {GPIOA_1}; +static const unsigned int spdif_out_a11_pins[] = {GPIOA_11}; +static const unsigned int spdif_out_a19_pins[] = {GPIOA_19}; +static const unsigned int spdif_out_a20_pins[] = {GPIOA_20}; + +/* jtag_ee */ +static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0}; +static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1}; +static const unsigned int jtag_clk_x_pins[] = {GPIOX_4}; +static const unsigned int jtag_tms_x_pins[] = {GPIOX_5}; + +/* eth */ +static const unsigned int eth_txd0_x_pins[] = {GPIOX_8}; +static const unsigned int eth_txd1_x_pins[] = {GPIOX_9}; +static const unsigned int eth_txen_x_pins[] = {GPIOX_10}; +static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12}; +static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13}; +static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14}; +static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15}; +static const unsigned int eth_mdio_x_pins[] = {GPIOX_21}; +static const unsigned int eth_mdc_x_pins[] = {GPIOX_22}; + +static const unsigned int eth_txd0_y_pins[] = {GPIOY_10}; +static const unsigned int eth_txd1_y_pins[] = {GPIOY_11}; +static const unsigned int eth_txen_y_pins[] = {GPIOY_9}; +static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2}; +static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4}; +static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5}; +static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3}; +static const unsigned int eth_mdio_y_pins[] = {GPIOY_0}; +static const unsigned int eth_mdc_y_pins[] = {GPIOY_1}; + +static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6}; +static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7}; +static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8}; +static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12}; +static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13}; + +/* pdm */ +static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14}; +static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19}; +static const unsigned int pdm_din0_pins[] = {GPIOA_15}; +static const unsigned int pdm_din1_pins[] = {GPIOA_16}; +static const unsigned int pdm_din2_pins[] = {GPIOA_17}; +static const unsigned int pdm_din3_pins[] = {GPIOA_18}; + +/* mclk */ +static const unsigned int mclk_c_pins[] = {GPIOA_0}; +static const unsigned int mclk_b_pins[] = {GPIOA_1}; + +/* tdm */ +static const unsigned int tdma_sclk_pins[] = {GPIOX_12}; +static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12}; +static const unsigned int tdma_fs_pins[] = {GPIOX_13}; +static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13}; +static const unsigned int tdma_din0_pins[] = {GPIOX_14}; +static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14}; +static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15}; +static const unsigned int tdma_dout1_pins[] = {GPIOX_15}; +static const unsigned int tdma_din1_pins[] = {GPIOX_15}; + +static const unsigned int tdmc_sclk_pins[] = {GPIOA_2}; +static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2}; +static const unsigned int tdmc_fs_pins[] = {GPIOA_3}; +static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3}; +static const unsigned int tdmc_din0_pins[] = {GPIOA_4}; +static const unsigned int tdmc_dout0_pins[] = {GPIOA_4}; +static const unsigned int tdmc_din1_pins[] = {GPIOA_5}; +static const unsigned int tdmc_dout1_pins[] = {GPIOA_5}; +static const unsigned int tdmc_din2_pins[] = {GPIOA_6}; +static const unsigned int tdmc_dout2_pins[] = {GPIOA_6}; +static const unsigned int tdmc_din3_pins[] = {GPIOA_7}; +static const unsigned int tdmc_dout3_pins[] = {GPIOA_7}; + +static const unsigned int tdmb_sclk_pins[] = {GPIOA_8}; +static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8}; +static const unsigned int tdmb_fs_pins[] = {GPIOA_9}; +static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9}; +static const unsigned int tdmb_din0_pins[] = {GPIOA_10}; +static const unsigned int tdmb_dout0_pins[] = {GPIOA_10}; +static const unsigned int tdmb_din1_pins[] = {GPIOA_11}; +static const unsigned int tdmb_dout1_pins[] = {GPIOA_11}; +static const unsigned int tdmb_din2_pins[] = {GPIOA_12}; +static const unsigned int tdmb_dout2_pins[] = {GPIOA_12}; +static const unsigned int tdmb_din3_pins[] = {GPIOA_13}; +static const unsigned int tdmb_dout3_pins[] = {GPIOA_13}; + +static struct meson_pmx_group meson_axg_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + + GPIO_GROUP(GPIOA_0, EE_OFF), + GPIO_GROUP(GPIOA_1, EE_OFF), + GPIO_GROUP(GPIOA_2, EE_OFF), + GPIO_GROUP(GPIOA_3, EE_OFF), + GPIO_GROUP(GPIOA_4, EE_OFF), + GPIO_GROUP(GPIOA_5, EE_OFF), + GPIO_GROUP(GPIOA_6, EE_OFF), + GPIO_GROUP(GPIOA_7, EE_OFF), + GPIO_GROUP(GPIOA_8, EE_OFF), + GPIO_GROUP(GPIOA_9, EE_OFF), + GPIO_GROUP(GPIOA_10, EE_OFF), + GPIO_GROUP(GPIOA_11, EE_OFF), + GPIO_GROUP(GPIOA_12, EE_OFF), + GPIO_GROUP(GPIOA_13, EE_OFF), + GPIO_GROUP(GPIOA_14, EE_OFF), + GPIO_GROUP(GPIOA_15, EE_OFF), + GPIO_GROUP(GPIOA_16, EE_OFF), + GPIO_GROUP(GPIOA_17, EE_OFF), + GPIO_GROUP(GPIOA_19, EE_OFF), + GPIO_GROUP(GPIOA_20, EE_OFF), + + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + GPIO_GROUP(GPIOX_19, EE_OFF), + GPIO_GROUP(GPIOX_20, EE_OFF), + GPIO_GROUP(GPIOX_21, EE_OFF), + GPIO_GROUP(GPIOX_22, EE_OFF), + + GPIO_GROUP(GPIOY_0, EE_OFF), + GPIO_GROUP(GPIOY_1, EE_OFF), + GPIO_GROUP(GPIOY_2, EE_OFF), + GPIO_GROUP(GPIOY_3, EE_OFF), + GPIO_GROUP(GPIOY_4, EE_OFF), + GPIO_GROUP(GPIOY_5, EE_OFF), + GPIO_GROUP(GPIOY_6, EE_OFF), + GPIO_GROUP(GPIOY_7, EE_OFF), + GPIO_GROUP(GPIOY_8, EE_OFF), + GPIO_GROUP(GPIOY_9, EE_OFF), + GPIO_GROUP(GPIOY_10, EE_OFF), + GPIO_GROUP(GPIOY_11, EE_OFF), + GPIO_GROUP(GPIOY_12, EE_OFF), + GPIO_GROUP(GPIOY_13, EE_OFF), + GPIO_GROUP(GPIOY_14, EE_OFF), + GPIO_GROUP(GPIOY_15, EE_OFF), + + /* bank BOOT */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_ds, 1), + GROUP(nand_ce0, 2), + GROUP(nand_ale, 2), + GROUP(nand_cle, 2), + GROUP(nand_wen_clk, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_rb0, 2), + GROUP(nor_hold, 3), + GROUP(nor_d, 3), + GROUP(nor_q, 3), + GROUP(nor_c, 3), + GROUP(nor_wp, 3), + GROUP(nor_cs, 3), + + /* bank GPIOZ */ + GROUP(spi0_clk, 1), + GROUP(spi0_mosi, 1), + GROUP(spi0_miso, 1), + GROUP(spi0_ss0, 1), + GROUP(spi0_ss1, 1), + GROUP(spi0_ss2, 1), + GROUP(i2c0_sck, 1), + GROUP(i2c0_sda, 1), + GROUP(i2c1_sck_z, 1), + GROUP(i2c1_sda_z, 1), + GROUP(uart_rts_b_z, 2), + GROUP(uart_cts_b_z, 2), + GROUP(uart_tx_b_z, 2), + GROUP(uart_rx_b_z, 2), + GROUP(pwm_a_z, 2), + GROUP(pwm_b_z, 2), + GROUP(spdif_in_z, 3), + GROUP(spdif_out_z, 3), + GROUP(uart_ao_tx_b_z, 2), + GROUP(uart_ao_rx_b_z, 2), + GROUP(uart_ao_cts_b_z, 2), + GROUP(uart_ao_rts_b_z, 2), + + /* bank GPIOX */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(i2c1_sck_x, 1), + GROUP(i2c1_sda_x, 1), + GROUP(i2c2_sck_x, 1), + GROUP(i2c2_sda_x, 1), + GROUP(uart_rts_a, 1), + GROUP(uart_cts_a, 1), + GROUP(uart_tx_a, 1), + GROUP(uart_rx_a, 1), + GROUP(uart_rts_b_x, 2), + GROUP(uart_cts_b_x, 2), + GROUP(uart_tx_b_x, 2), + GROUP(uart_rx_b_x, 2), + GROUP(jtag_tdo_x, 2), + GROUP(jtag_tdi_x, 2), + GROUP(jtag_clk_x, 2), + GROUP(jtag_tms_x, 2), + GROUP(spi1_clk_x, 4), + GROUP(spi1_mosi_x, 4), + GROUP(spi1_miso_x, 4), + GROUP(spi1_ss0_x, 4), + GROUP(pwm_a_x18, 3), + GROUP(pwm_a_x20, 1), + GROUP(pwm_b_x, 3), + GROUP(pwm_c_x10, 3), + GROUP(pwm_c_x17, 3), + GROUP(pwm_d_x11, 3), + GROUP(pwm_d_x16, 3), + GROUP(eth_txd0_x, 4), + GROUP(eth_txd1_x, 4), + GROUP(eth_txen_x, 4), + GROUP(eth_rgmii_rx_clk_x, 4), + GROUP(eth_rxd0_x, 4), + GROUP(eth_rxd1_x, 4), + GROUP(eth_rx_dv_x, 4), + GROUP(eth_mdio_x, 4), + GROUP(eth_mdc_x, 4), + GROUP(tdma_sclk, 1), + GROUP(tdma_sclk_slv, 2), + GROUP(tdma_fs, 1), + GROUP(tdma_fs_slv, 2), + GROUP(tdma_din0, 1), + GROUP(tdma_dout0_x14, 2), + GROUP(tdma_dout0_x15, 1), + GROUP(tdma_dout1, 2), + GROUP(tdma_din1, 3), + + /* bank GPIOY */ + GROUP(eth_txd0_y, 1), + GROUP(eth_txd1_y, 1), + GROUP(eth_txen_y, 1), + GROUP(eth_rgmii_rx_clk_y, 1), + GROUP(eth_rxd0_y, 1), + GROUP(eth_rxd1_y, 1), + GROUP(eth_rx_dv_y, 1), + GROUP(eth_mdio_y, 1), + GROUP(eth_mdc_y, 1), + GROUP(eth_rxd2_rgmii, 1), + GROUP(eth_rxd3_rgmii, 1), + GROUP(eth_rgmii_tx_clk, 1), + GROUP(eth_txd2_rgmii, 1), + GROUP(eth_txd3_rgmii, 1), + + /* bank GPIOA */ + GROUP(spdif_out_a1, 4), + GROUP(spdif_out_a11, 3), + GROUP(spdif_out_a19, 2), + GROUP(spdif_out_a20, 1), + GROUP(spdif_in_a1, 3), + GROUP(spdif_in_a7, 3), + GROUP(spdif_in_a19, 1), + GROUP(spdif_in_a20, 2), + GROUP(spi1_clk_a, 3), + GROUP(spi1_mosi_a, 3), + GROUP(spi1_miso_a, 3), + GROUP(spi1_ss0_a, 3), + GROUP(spi1_ss1, 3), + GROUP(pwm_a_a, 3), + GROUP(pwm_b_a, 3), + GROUP(pwm_c_a, 3), + GROUP(pwm_vs, 2), + GROUP(i2c2_sda_a, 3), + GROUP(i2c2_sck_a, 3), + GROUP(i2c3_sda_a6, 4), + GROUP(i2c3_sck_a7, 4), + GROUP(i2c3_sda_a12, 4), + GROUP(i2c3_sck_a13, 4), + GROUP(i2c3_sda_a19, 4), + GROUP(i2c3_sck_a20, 4), + GROUP(pdm_dclk_a14, 1), + GROUP(pdm_dclk_a19, 3), + GROUP(pdm_din0, 1), + GROUP(pdm_din1, 1), + GROUP(pdm_din2, 1), + GROUP(pdm_din3, 1), + GROUP(mclk_c, 1), + GROUP(mclk_b, 1), + GROUP(tdmc_sclk, 1), + GROUP(tdmc_sclk_slv, 2), + GROUP(tdmc_fs, 1), + GROUP(tdmc_fs_slv, 2), + GROUP(tdmc_din0, 2), + GROUP(tdmc_dout0, 1), + GROUP(tdmc_din1, 2), + GROUP(tdmc_dout1, 1), + GROUP(tdmc_din2, 2), + GROUP(tdmc_dout2, 1), + GROUP(tdmc_din3, 2), + GROUP(tdmc_dout3, 1), + GROUP(tdmb_sclk, 1), + GROUP(tdmb_sclk_slv, 2), + GROUP(tdmb_fs, 1), + GROUP(tdmb_fs_slv, 2), + GROUP(tdmb_din0, 2), + GROUP(tdmb_dout0, 1), + GROUP(tdmb_din1, 2), + GROUP(tdmb_dout1, 1), + GROUP(tdmb_din2, 2), + GROUP(tdmb_dout2, 1), + GROUP(tdmb_din3, 2), + GROUP(tdmb_dout3, 1), +}; + +/* uart_ao_a */ +static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0}; +static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1}; +static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2}; +static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3}; + +/* uart_ao_b */ +static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4}; +static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5}; +static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2}; +static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3}; + +/* i2c_ao */ +static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4}; +static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5}; +static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8}; +static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9}; +static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10}; +static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11}; + +/* i2c_ao_slave */ +static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10}; +static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11}; + +/* ir_in */ +static const unsigned int remote_input_ao_pins[] = {GPIOAO_6}; + +/* ir_out */ +static const unsigned int remote_out_ao_pins[] = {GPIOAO_7}; + +/* pwm_ao_a */ +static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3}; + +/* pwm_ao_b */ +static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2}; +static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12}; + +/* pwm_ao_c */ +static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8}; +static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13}; + +/* pwm_ao_d */ +static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9}; + +/* jtag_ao */ +static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3}; +static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4}; +static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5}; +static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7}; + +static struct meson_pmx_group meson_axg_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_10, 0), + GPIO_GROUP(GPIOAO_11, 0), + GPIO_GROUP(GPIOAO_12, 0), + GPIO_GROUP(GPIOAO_13, 0), + GPIO_GROUP(GPIO_TEST_N, 0), + + /* bank AO */ + GROUP(uart_ao_tx_a, 1), + GROUP(uart_ao_rx_a, 1), + GROUP(uart_ao_cts_a, 2), + GROUP(uart_ao_rts_a, 2), + GROUP(uart_ao_tx_b, 1), + GROUP(uart_ao_rx_b, 1), + GROUP(uart_ao_cts_b, 1), + GROUP(uart_ao_rts_b, 1), + GROUP(i2c_ao_sck_4, 2), + GROUP(i2c_ao_sda_5, 2), + GROUP(i2c_ao_sck_8, 2), + GROUP(i2c_ao_sda_9, 2), + GROUP(i2c_ao_sck_10, 2), + GROUP(i2c_ao_sda_11, 2), + GROUP(i2c_ao_slave_sck, 1), + GROUP(i2c_ao_slave_sda, 1), + GROUP(remote_input_ao, 1), + GROUP(remote_out_ao, 1), + GROUP(pwm_ao_a, 3), + GROUP(pwm_ao_b_ao2, 3), + GROUP(pwm_ao_b_ao12, 3), + GROUP(pwm_ao_c_ao8, 3), + GROUP(pwm_ao_c_ao13, 3), + GROUP(pwm_ao_d, 3), + GROUP(jtag_ao_tdi, 4), + GROUP(jtag_ao_tdo, 4), + GROUP(jtag_ao_clk, 4), + GROUP(jtag_ao_tms, 4), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", + "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19", + "GPIOA_20", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", + "GPIOX_20", "GPIOX_21", "GPIOX_22", + + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", + "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", + "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", + "GPIOY_15", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "nand_ce0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_rb0", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", + "nor_hold", "nor_wp", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", +}; + +static const char * const spi0_groups[] = { + "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0", + "spi0_ss1", "spi0_ss2" +}; + +static const char * const spi1_groups[] = { + "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x", + "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a", + "spi1_ss1" +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z", + "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x", +}; + +static const char * const uart_ao_b_z_groups[] = { + "uart_ao_tx_b_z", "uart_ao_rx_b_z", + "uart_ao_cts_b_z", "uart_ao_rts_b_z", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sck", "i2c0_sda", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sck_z", "i2c1_sda_z", + "i2c1_sck_x", "i2c1_sda_x", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sck_x", "i2c2_sda_x", + "i2c2_sda_a", "i2c2_sck_a", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_a6", "i2c3_sck_a7", + "i2c3_sda_a12", "i2c3_sck_a13", + "i2c3_sda_a19", "i2c3_sck_a20", +}; + +static const char * const eth_groups[] = { + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", + "eth_txd2_rgmii", "eth_txd3_rgmii", + "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x", + "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x", + "eth_mdc_x", + "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y", + "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y", + "eth_mdc_y", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_z", "pwm_b_x", "pwm_b_a", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_x10", "pwm_c_x17", "pwm_c_a", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_x11", "pwm_d_x16", +}; + +static const char * const pwm_vs_groups[] = { + "pwm_vs", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_z", "spdif_out_a1", "spdif_out_a11", + "spdif_out_a19", "spdif_out_a20", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_z", "spdif_in_a1", "spdif_in_a7", + "spdif_in_a19", "spdif_in_a20", +}; + +static const char * const jtag_ee_groups[] = { + "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x", + "jtag_tms_x", +}; + +static const char * const pdm_groups[] = { + "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3", + "pdm_dclk_a14", "pdm_dclk_a19", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", + "GPIO_TEST_N", +}; + +static const char * const uart_ao_a_groups[] = { + "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_ao_sck_4", "i2c_ao_sda_5", + "i2c_ao_sck_8", "i2c_ao_sda_9", + "i2c_ao_sck_10", "i2c_ao_sda_11", +}; + +static const char * const i2c_ao_slave_groups[] = { + "i2c_ao_slave_sck", "i2c_ao_slave_sda", +}; + +static const char * const remote_input_ao_groups[] = { + "remote_input_ao", +}; + +static const char * const remote_out_ao_groups[] = { + "remote_out_ao", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b_ao2", "pwm_ao_b_ao12", +}; + +static const char * const pwm_ao_c_groups[] = { + "pwm_ao_c_ao8", "pwm_ao_c_ao13", +}; + +static const char * const pwm_ao_d_groups[] = { + "pwm_ao_d", +}; + +static const char * const jtag_ao_groups[] = { + "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms", +}; + +static const char * const mclk_c_groups[] = { + "mclk_c", +}; + +static const char * const mclk_b_groups[] = { + "mclk_b", +}; + +static const char * const tdma_groups[] = { + "tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv", + "tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1", + "tdma_din1", +}; + +static const char * const tdmc_groups[] = { + "tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv", + "tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1", + "tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3", +}; + +static const char * const tdmb_groups[] = { + "tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv", + "tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1", + "tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3", +}; + +static struct meson_pmx_func meson_axg_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi0), + FUNCTION(spi1), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_ao_b_z), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_vs), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(jtag_ee), + FUNCTION(pdm), + FUNCTION(mclk_b), + FUNCTION(mclk_c), + FUNCTION(tdma), + FUNCTION(tdmb), + FUNCTION(tdmc), +}; + +static struct meson_pmx_func meson_axg_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao_a), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_ao_slave), + FUNCTION(remote_input_ao), + FUNCTION(remote_out_ao), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(pwm_ao_c), + FUNCTION(pwm_ao_d), + FUNCTION(jtag_ao), +}; + +static struct meson_bank meson_axg_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), +}; + +static struct meson_bank meson_axg_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { + /* name first lask reg offset */ + BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0), + BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0), + BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0), + BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0), + BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0), +}; + +static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = { + .pmx_banks = meson_axg_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks), +}; + +static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = { + BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0), +}; + +static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = { + .pmx_banks = meson_axg_aobus_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks), +}; + +struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = 15, + .groups = meson_axg_periphs_groups, + .funcs = meson_axg_periphs_functions, + .banks = meson_axg_periphs_banks, + .num_pins = 86, + .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), + .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_axg_periphs_pmx_banks_data, +}; + +struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_axg_aobus_groups, + .funcs = meson_axg_aobus_functions, + .banks = meson_axg_aobus_banks, + .num_pins = 14, + .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), + .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_axg_aobus_pmx_banks_data, +}; + +static const struct udevice_id meson_axg_pinctrl_match[] = { + { + .compatible = "amlogic,meson-axg-periphs-pinctrl", + .data = (ulong)&meson_axg_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-axg-aobus-pinctrl", + .data = (ulong)&meson_axg_aobus_pinctrl_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_axg_pinctrl) = { + .name = "meson-axg-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_axg_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h new file mode 100644 index 0000000000..c8d2b3af03 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Jerome Brunet + * Copyright (C) 2017 Xingyu Chen + */ + +#ifndef __PINCTRL_MESON_AXG_H__ +#define __PINCTRL_MESON_AXG_H__ + +#include "pinctrl-meson.h" + +struct meson_pmx_bank { + const char *name; + unsigned int first; + unsigned int last; + unsigned int reg; + unsigned int offset; +}; + +struct meson_axg_pmx_data { + struct meson_pmx_bank *pmx_banks; + unsigned int num_pmx_banks; +}; + +#define BANK_PMX(n, f, l, r, o) \ + { \ + .name = n, \ + .first = f, \ + .last = l, \ + .reg = r, \ + .offset = o, \ + } + +struct meson_pmx_axg_data { + unsigned int func; +}; + +#define PMX_DATA(f) \ + { \ + .func = f, \ + } + +#define GROUP(grp, f) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .data = (const struct meson_pmx_axg_data[]){ \ + PMX_DATA(f), \ + }, \ + } + +#define GPIO_GROUP(gpio, b) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ PIN(gpio, b) }, \ + .num_pins = 1, \ + .data = (const struct meson_pmx_axg_data[]){ \ + PMX_DATA(0), \ + }, \ + } + +extern const struct pinctrl_ops meson_axg_pinctrl_ops; +extern const struct driver meson_axg_gpio_driver; + +#endif /* __PINCTRL_MESON_AXG_H__ */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c new file mode 100644 index 0000000000..fc1538ea71 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 - Beniamino Galvani + */ + +#include +#include +#include +#include +#include +#include "pinctrl-meson-gx.h" + +static void meson_gx_pinmux_disable_other_groups(struct meson_pinctrl *priv, + unsigned int pin, + int sel_group) +{ + struct meson_pmx_group *group; + struct meson_gx_pmx_data *pmx_data; + void __iomem *addr; + int i, j; + + for (i = 0; i < priv->data->num_groups; i++) { + group = &priv->data->groups[i]; + pmx_data = (struct meson_gx_pmx_data *)group->data; + if (pmx_data->is_gpio || i == sel_group) + continue; + + for (j = 0; j < group->num_pins; j++) { + if (group->pins[j] == pin) { + /* We have found a group using the pin */ + debug("pinmux: disabling %s\n", group->name); + addr = priv->reg_mux + pmx_data->reg * 4; + writel(readl(addr) & ~BIT(pmx_data->bit), addr); + } + } + } +} + +static int meson_gx_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct meson_pinctrl *priv = dev_get_priv(dev); + const struct meson_pmx_group *group; + const struct meson_pmx_func *func; + struct meson_gx_pmx_data *pmx_data; + void __iomem *addr; + int i; + + group = &priv->data->groups[group_selector]; + pmx_data = (struct meson_gx_pmx_data *)group->data; + func = &priv->data->funcs[func_selector]; + + debug("pinmux: set group %s func %s\n", group->name, func->name); + + /* + * Disable groups using the same pins. + * The selected group is not disabled to avoid glitches. + */ + for (i = 0; i < group->num_pins; i++) { + meson_gx_pinmux_disable_other_groups(priv, + group->pins[i], + group_selector); + } + + /* Function 0 (GPIO) doesn't need any additional setting */ + if (func_selector) { + addr = priv->reg_mux + pmx_data->reg * 4; + writel(readl(addr) | BIT(pmx_data->bit), addr); + } + + return 0; +} + +const struct pinctrl_ops meson_gx_pinctrl_ops = { + .get_groups_count = meson_pinctrl_get_groups_count, + .get_group_name = meson_pinctrl_get_group_name, + .get_functions_count = meson_pinmux_get_functions_count, + .get_function_name = meson_pinmux_get_function_name, + .pinmux_group_set = meson_gx_pinmux_group_set, + .set_state = pinctrl_generic_set_state, +}; + +static const struct dm_gpio_ops meson_gx_gpio_ops = { + .set_value = meson_gpio_set, + .get_value = meson_gpio_get, + .get_function = meson_gpio_get_direction, + .direction_input = meson_gpio_direction_input, + .direction_output = meson_gpio_direction_output, +}; + +const struct driver meson_gx_gpio_driver = { + .name = "meson-gx-gpio", + .id = UCLASS_GPIO, + .probe = meson_gpio_probe, + .ops = &meson_gx_gpio_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx.h b/drivers/pinctrl/meson/pinctrl-meson-gx.h new file mode 100644 index 0000000000..4c1aa1a300 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gx.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Beniamino Galvani + * Copyright (C) 2017 Jerome Brunet + */ + +#ifndef __PINCTRL_MESON_GX_H__ +#define __PINCTRL_MESON_GX_H__ + +#include "pinctrl-meson.h" + +struct meson_gx_pmx_data { + bool is_gpio; + unsigned int reg; + unsigned int bit; +}; + +#define PMX_DATA(r, b, g) \ + { \ + .reg = r, \ + .bit = b, \ + .is_gpio = g, \ + } + +#define GROUP(grp, r, b) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .data = (const struct meson_gx_pmx_data[]){ \ + PMX_DATA(r, b, false), \ + }, \ + } + +#define GPIO_GROUP(gpio, b) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ PIN(gpio, b) }, \ + .num_pins = 1, \ + .data = (const struct meson_gx_pmx_data[]){ \ + PMX_DATA(0, 0, true), \ + }, \ + } + +extern const struct pinctrl_ops meson_gx_pinctrl_ops; +extern const struct driver meson_gx_gpio_driver; + +#endif /* __PINCTRL_MESON_GX_H__ */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index a8e47e3c4e..22e8b055d7 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -11,7 +11,7 @@ #include #include -#include "pinctrl-meson.h" +#include "pinctrl-meson-gx.h" #define EE_OFF 15 @@ -417,6 +417,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), + .gpio_driver = &meson_gx_gpio_driver, }; struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { @@ -429,6 +430,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), + .gpio_driver = &meson_gx_gpio_driver, }; static const struct udevice_id meson_gxbb_pinctrl_match[] = { @@ -449,5 +451,5 @@ U_BOOT_DRIVER(meson_gxbb_pinctrl) = { .of_match = of_match_ptr(meson_gxbb_pinctrl_match), .probe = meson_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct meson_pinctrl), - .ops = &meson_pinctrl_ops, + .ops = &meson_gx_pinctrl_ops, }; diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index ba6e3531d9..1819eee4d0 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -11,7 +11,7 @@ #include #include -#include "pinctrl-meson.h" +#include "pinctrl-meson-gx.h" #define EE_OFF 11 @@ -699,6 +699,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), + .gpio_driver = &meson_gx_gpio_driver, }; struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { @@ -711,6 +712,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), + .gpio_driver = &meson_gx_gpio_driver, }; static const struct udevice_id meson_gxl_pinctrl_match[] = { @@ -731,5 +733,5 @@ U_BOOT_DRIVER(meson_gxl_pinctrl) = { .of_match = of_match_ptr(meson_gxl_pinctrl_match), .probe = meson_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct meson_pinctrl), - .ops = &meson_pinctrl_ops, + .ops = &meson_gx_pinctrl_ops, }; diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 387c241d12..b539749752 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR; static const char *meson_pinctrl_dummy_name = "_dummy"; -static int meson_pinctrl_get_groups_count(struct udevice *dev) +int meson_pinctrl_get_groups_count(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->num_groups; } -static const char *meson_pinctrl_get_group_name(struct udevice *dev, - unsigned selector) +const char *meson_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector) { struct meson_pinctrl *priv = dev_get_priv(dev); @@ -38,87 +38,21 @@ static const char *meson_pinctrl_get_group_name(struct udevice *dev, return priv->data->groups[selector].name; } -static int meson_pinmux_get_functions_count(struct udevice *dev) +int meson_pinmux_get_functions_count(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->num_funcs; } -static const char *meson_pinmux_get_function_name(struct udevice *dev, - unsigned selector) +const char *meson_pinmux_get_function_name(struct udevice *dev, + unsigned int selector) { struct meson_pinctrl *priv = dev_get_priv(dev); return priv->data->funcs[selector].name; } -static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv, - unsigned int pin, int sel_group) -{ - struct meson_pmx_group *group; - void __iomem *addr; - int i, j; - - for (i = 0; i < priv->data->num_groups; i++) { - group = &priv->data->groups[i]; - if (group->is_gpio || i == sel_group) - continue; - - for (j = 0; j < group->num_pins; j++) { - if (group->pins[j] == pin) { - /* We have found a group using the pin */ - debug("pinmux: disabling %s\n", group->name); - addr = priv->reg_mux + group->reg * 4; - writel(readl(addr) & ~BIT(group->bit), addr); - } - } - } -} - -static int meson_pinmux_group_set(struct udevice *dev, - unsigned group_selector, - unsigned func_selector) -{ - struct meson_pinctrl *priv = dev_get_priv(dev); - const struct meson_pmx_group *group; - const struct meson_pmx_func *func; - void __iomem *addr; - int i; - - group = &priv->data->groups[group_selector]; - func = &priv->data->funcs[func_selector]; - - debug("pinmux: set group %s func %s\n", group->name, func->name); - - /* - * Disable groups using the same pins. - * The selected group is not disabled to avoid glitches. - */ - for (i = 0; i < group->num_pins; i++) { - meson_pinmux_disable_other_groups(priv, - group->pins[i], - group_selector); - } - - /* Function 0 (GPIO) doesn't need any additional setting */ - if (func_selector) { - addr = priv->reg_mux + group->reg * 4; - writel(readl(addr) | BIT(group->bit), addr); - } - - return 0; -} - -const struct pinctrl_ops meson_pinctrl_ops = { - .get_groups_count = meson_pinctrl_get_groups_count, - .get_group_name = meson_pinctrl_get_group_name, - .get_functions_count = meson_pinmux_get_functions_count, - .get_function_name = meson_pinmux_get_function_name, - .pinmux_group_set = meson_pinmux_group_set, - .set_state = pinctrl_generic_set_state, -}; - static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, enum meson_reg_type reg_type, unsigned int *reg, unsigned int *bit) @@ -149,7 +83,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset, return 0; } -static int meson_gpio_get(struct udevice *dev, unsigned int offset) +int meson_gpio_get(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -162,7 +96,7 @@ static int meson_gpio_get(struct udevice *dev, unsigned int offset) return !!(readl(priv->reg_gpio + reg) & BIT(bit)); } -static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) +int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -177,7 +111,7 @@ static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value) return 0; } -static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) +int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit, val; @@ -192,7 +126,7 @@ static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset) return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT; } -static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) +int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -202,13 +136,13 @@ static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset) if (ret) return ret; - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1); + setbits_le32(priv->reg_gpio + reg, BIT(bit)); return 0; } -static int meson_gpio_direction_output(struct udevice *dev, - unsigned int offset, int value) +int meson_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); unsigned int reg, bit; @@ -218,7 +152,7 @@ static int meson_gpio_direction_output(struct udevice *dev, if (ret) return ret; - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0); + clrbits_le32(priv->reg_gpio + reg, BIT(bit)); ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit); if (ret) @@ -229,7 +163,7 @@ static int meson_gpio_direction_output(struct udevice *dev, return 0; } -static int meson_gpio_probe(struct udevice *dev) +int meson_gpio_probe(struct udevice *dev) { struct meson_pinctrl *priv = dev_get_priv(dev->parent); struct gpio_dev_priv *uc_priv; @@ -241,21 +175,6 @@ static int meson_gpio_probe(struct udevice *dev) return 0; } -static const struct dm_gpio_ops meson_gpio_ops = { - .set_value = meson_gpio_set, - .get_value = meson_gpio_get, - .get_function = meson_gpio_get_direction, - .direction_input = meson_gpio_direction_input, - .direction_output = meson_gpio_direction_output, -}; - -static struct driver meson_gpio_driver = { - .name = "meson-gpio", - .id = UCLASS_GPIO, - .probe = meson_gpio_probe, - .ops = &meson_gpio_ops, -}; - static fdt_addr_t parse_address(int offset, const char *name, int na, int ns) { int index, len = 0; @@ -334,7 +253,7 @@ int meson_pinctrl_probe(struct udevice *dev) sprintf(name, "meson-gpio"); /* Create child device UCLASS_GPIO and bind it */ - device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev); + device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev); dev_set_of_offset(gpio_dev, gpio); return 0; diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 6ec89ba117..bdee721fc0 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -12,9 +12,7 @@ struct meson_pmx_group { const char *name; const unsigned int *pins; unsigned int num_pins; - bool is_gpio; - unsigned int reg; - unsigned int bit; + const void *data; }; struct meson_pmx_func { @@ -33,6 +31,8 @@ struct meson_pinctrl_data { unsigned int num_groups; unsigned int num_funcs; unsigned int num_banks; + const struct driver *gpio_driver; + void *pmx_data; }; struct meson_pinctrl { @@ -89,23 +89,6 @@ struct meson_bank { #define PIN(x, b) (b + x) -#define GROUP(grp, r, b) \ - { \ - .name = #grp, \ - .pins = grp ## _pins, \ - .num_pins = ARRAY_SIZE(grp ## _pins), \ - .reg = r, \ - .bit = b, \ - } - -#define GPIO_GROUP(gpio, b) \ - { \ - .name = #gpio, \ - .pins = (const unsigned int[]){ PIN(gpio, b) }, \ - .num_pins = 1, \ - .is_gpio = true, \ - } - #define FUNCTION(fn) \ { \ .name = #fn, \ @@ -131,6 +114,20 @@ struct meson_bank { extern const struct pinctrl_ops meson_pinctrl_ops; +int meson_pinctrl_get_groups_count(struct udevice *dev); +const char *meson_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector); +int meson_pinmux_get_functions_count(struct udevice *dev); +const char *meson_pinmux_get_function_name(struct udevice *dev, + unsigned int selector); int meson_pinctrl_probe(struct udevice *dev); +int meson_gpio_get(struct udevice *dev, unsigned int offset); +int meson_gpio_set(struct udevice *dev, unsigned int offset, int value); +int meson_gpio_get_direction(struct udevice *dev, unsigned int offset); +int meson_gpio_direction_input(struct udevice *dev, unsigned int offset); +int meson_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value); +int meson_gpio_probe(struct udevice *dev); + #endif /* __PINCTRL_MESON_H__ */ diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig new file mode 100644 index 0000000000..cfc6c06076 --- /dev/null +++ b/drivers/pinctrl/mscc/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +config PINCTRL_MSCC + bool + +config PINCTRL_MSCC_OCELOT + depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL + select PINCTRL_MSCC + default y + bool "Microsemi ocelot family pin control driver" + help + Support pin multiplexing and pin configuration control on + Microsemi ocelot SoCs. + +config PINCTRL_MSCC_LUTON + depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL + select PINCTRL_MSCC + default y + bool "Microsemi luton family pin control driver" + help + Support pin multiplexing and pin configuration control on + Microsemi luton SoCs. diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile new file mode 100644 index 0000000000..6910671728 --- /dev/null +++ b/drivers/pinctrl/mscc/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +obj-y += mscc-common.o +obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o +obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c new file mode 100644 index 0000000000..d74b8a6649 --- /dev/null +++ b/drivers/pinctrl/mscc/mscc-common.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: + * Author: + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mscc-common.h" + +#define MSCC_GPIO_OUT_SET 0x0 +#define MSCC_GPIO_OUT_CLR 0x4 +#define MSCC_GPIO_OUT 0x8 +#define MSCC_GPIO_IN 0xc +#define MSCC_GPIO_OE 0x10 +#define MSCC_GPIO_INTR 0x14 +#define MSCC_GPIO_INTR_ENA 0x18 +#define MSCC_GPIO_INTR_IDENT 0x1c +#define MSCC_GPIO_ALT0 0x20 +#define MSCC_GPIO_ALT1 0x24 + +static int mscc_get_functions_count(struct udevice *dev) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->num_func; +} + +static const char *mscc_get_function_name(struct udevice *dev, + unsigned int function) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->function_names[function]; +} + +static int mscc_pin_function_idx(unsigned int pin, unsigned int function, + const struct mscc_pin_data *mscc_pins) +{ + struct mscc_pin_caps *p = mscc_pins[pin].drv_data; + int i; + + for (i = 0; i < MSCC_FUNC_PER_PIN; i++) { + if (function == p->functions[i]) + return i; + } + + return -1; +} + +static int mscc_pinmux_set_mux(struct udevice *dev, + unsigned int pin_selector, unsigned int selector) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data; + int f; + + f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins); + if (f < 0) + return -EINVAL; + /* + * f is encoded on two bits. + * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of + * ALT1 + * This is racy because both registers can't be updated at the same time + * but it doesn't matter much for now. + */ + if (f & BIT(0)) + setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin)); + else + clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin)); + + if (f & BIT(1)) + setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1)); + else + clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1)); + + return 0; +} + +static int mscc_pctl_get_groups_count(struct udevice *dev) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->num_pins; +} + +static const char *mscc_pctl_get_group_name(struct udevice *dev, + unsigned int group) +{ + struct mscc_pinctrl *info = dev_get_priv(dev); + + return info->mscc_pins[group].name; +} + +static int mscc_create_group_func_map(struct udevice *dev, + struct mscc_pinctrl *info) +{ + u16 pins[info->num_pins]; + int f, npins, i; + + for (f = 0; f < info->num_func; f++) { + for (npins = 0, i = 0; i < info->num_pins; i++) { + if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0) + pins[npins++] = i; + } + + info->func[f].ngroups = npins; + info->func[f].groups = devm_kzalloc(dev, npins * + sizeof(char *), GFP_KERNEL); + if (!info->func[f].groups) + return -ENOMEM; + + for (i = 0; i < npins; i++) + info->func[f].groups[i] = info->mscc_pins[pins[i]].name; + } + + return 0; +} + +static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info) +{ + int ret; + + ret = mscc_create_group_func_map(dev, info); + if (ret) { + dev_err(dev, "Unable to create group func map.\n"); + return ret; + } + + return 0; +} + +static int mscc_gpio_get(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + unsigned int val; + + val = readl(info->regs + MSCC_GPIO_IN); + + return !!(val & BIT(offset)); +} + +static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + if (value) + writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET); + else + writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR); + + return 0; +} + +static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + unsigned int val; + + val = readl(info->regs + MSCC_GPIO_OE); + + return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset)); + + return 0; +} + +static int mscc_gpio_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + struct mscc_pinctrl *info = dev_get_priv(dev->parent); + + setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset)); + + return mscc_gpio_set(dev, offset, value); +} + +const struct dm_gpio_ops mscc_gpio_ops = { + .set_value = mscc_gpio_set, + .get_value = mscc_gpio_get, + .get_function = mscc_gpio_get_direction, + .direction_input = mscc_gpio_direction_input, + .direction_output = mscc_gpio_direction_output, +}; + +const struct pinctrl_ops mscc_pinctrl_ops = { + .get_pins_count = mscc_pctl_get_groups_count, + .get_pin_name = mscc_pctl_get_group_name, + .get_functions_count = mscc_get_functions_count, + .get_function_name = mscc_get_function_name, + .pinmux_set = mscc_pinmux_set_mux, + .set_state = pinctrl_generic_set_state, +}; + +int mscc_pinctrl_probe(struct udevice *dev, int num_func, + const struct mscc_pin_data *mscc_pins, int num_pins, + char *const *function_names) +{ + struct mscc_pinctrl *priv = dev_get_priv(dev); + int ret; + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func), + GFP_KERNEL); + priv->num_func = num_func; + priv->mscc_pins = mscc_pins; + priv->num_pins = num_pins; + priv->function_names = function_names; + ret = mscc_pinctrl_register(dev, priv); + + return ret; +} diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h new file mode 100644 index 0000000000..b0001db44c --- /dev/null +++ b/drivers/pinctrl/mscc/mscc-common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Microsemi SoCs pinctrl driver + * + * Author: + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#define MSCC_FUNC_PER_PIN 4 + +struct mscc_pin_caps { + unsigned int pin; + unsigned char functions[MSCC_FUNC_PER_PIN]; +}; + +struct mscc_pin_data { + const char *name; + struct mscc_pin_caps *drv_data; +}; + +#define MSCC_P(p, f0, f1, f2) \ +static struct mscc_pin_caps mscc_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + }, \ +} + +struct mscc_pmx_func { + const char **groups; + unsigned int ngroups; +}; + +struct mscc_pinctrl { + struct udevice *dev; + struct pinctrl_dev *pctl; + void __iomem *regs; + struct mscc_pmx_func *func; + int num_func; + const struct mscc_pin_data *mscc_pins; + int num_pins; + char * const *function_names; +}; + +int mscc_pinctrl_probe(struct udevice *dev, int num_func, + const struct mscc_pin_data *mscc_pins, int num_pins, + char * const *function_names); +const struct pinctrl_ops mscc_pinctrl_ops; + +const struct dm_gpio_ops mscc_gpio_ops; diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c new file mode 100644 index 0000000000..7166588e3c --- /dev/null +++ b/drivers/pinctrl/mscc/pinctrl-luton.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: + * License: Dual MIT/GPL + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mscc-common.h" + +enum { + FUNC_NONE, + FUNC_GPIO, + FUNC_SIO, + FUNC_TACHO, + FUNC_TWI, + FUNC_PHY_LED, + FUNC_EXT_IRQ, + FUNC_SFP, + FUNC_SI, + FUNC_PWM, + FUNC_UART, + FUNC_MAX +}; + +static char * const luton_function_names[] = { + [FUNC_NONE] = "none", + [FUNC_GPIO] = "gpio", + [FUNC_SIO] = "sio", + [FUNC_TACHO] = "tacho", + [FUNC_TWI] = "twi", + [FUNC_PHY_LED] = "phy_led", + [FUNC_EXT_IRQ] = "ext_irq", + [FUNC_SFP] = "sfp", + [FUNC_SI] = "si", + [FUNC_PWM] = "pwm", + [FUNC_UART] = "uart", +}; + +MSCC_P(0, SIO, NONE, NONE); +MSCC_P(1, SIO, NONE, NONE); +MSCC_P(2, SIO, NONE, NONE); +MSCC_P(3, SIO, NONE, NONE); +MSCC_P(4, TACHO, NONE, NONE); +MSCC_P(5, TWI, PHY_LED, NONE); +MSCC_P(6, TWI, PHY_LED, NONE); +MSCC_P(7, NONE, PHY_LED, NONE); +MSCC_P(8, EXT_IRQ, PHY_LED, NONE); +MSCC_P(9, EXT_IRQ, PHY_LED, NONE); +MSCC_P(10, SFP, PHY_LED, NONE); +MSCC_P(11, SFP, PHY_LED, NONE); +MSCC_P(12, SFP, PHY_LED, NONE); +MSCC_P(13, SFP, PHY_LED, NONE); +MSCC_P(14, SI, PHY_LED, NONE); +MSCC_P(15, SI, PHY_LED, NONE); +MSCC_P(16, SI, PHY_LED, NONE); +MSCC_P(17, SFP, PHY_LED, NONE); +MSCC_P(18, SFP, PHY_LED, NONE); +MSCC_P(19, SFP, PHY_LED, NONE); +MSCC_P(20, SFP, PHY_LED, NONE); +MSCC_P(21, SFP, PHY_LED, NONE); +MSCC_P(22, SFP, PHY_LED, NONE); +MSCC_P(23, SFP, PHY_LED, NONE); +MSCC_P(24, SFP, PHY_LED, NONE); +MSCC_P(25, SFP, PHY_LED, NONE); +MSCC_P(26, SFP, PHY_LED, NONE); +MSCC_P(27, SFP, PHY_LED, NONE); +MSCC_P(28, SFP, PHY_LED, NONE); +MSCC_P(29, PWM, NONE, NONE); +MSCC_P(30, UART, NONE, NONE); +MSCC_P(31, UART, NONE, NONE); + +#define LUTON_PIN(n) { \ + .name = "GPIO_"#n, \ + .drv_data = &mscc_pin_##n \ +} + +static const struct mscc_pin_data luton_pins[] = { + LUTON_PIN(0), + LUTON_PIN(1), + LUTON_PIN(2), + LUTON_PIN(3), + LUTON_PIN(4), + LUTON_PIN(5), + LUTON_PIN(6), + LUTON_PIN(7), + LUTON_PIN(8), + LUTON_PIN(9), + LUTON_PIN(10), + LUTON_PIN(11), + LUTON_PIN(12), + LUTON_PIN(13), + LUTON_PIN(14), + LUTON_PIN(15), + LUTON_PIN(16), + LUTON_PIN(17), + LUTON_PIN(18), + LUTON_PIN(19), + LUTON_PIN(20), + LUTON_PIN(21), + LUTON_PIN(22), + LUTON_PIN(23), + LUTON_PIN(24), + LUTON_PIN(25), + LUTON_PIN(26), + LUTON_PIN(27), + LUTON_PIN(28), + LUTON_PIN(29), + LUTON_PIN(30), + LUTON_PIN(31), +}; + +static int luton_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = "luton-gpio"; + uc_priv->gpio_count = ARRAY_SIZE(luton_pins); + + return 0; +} + +static struct driver luton_gpio_driver = { + .name = "luton-gpio", + .id = UCLASS_GPIO, + .probe = luton_gpio_probe, + .ops = &mscc_gpio_ops, +}; + +int luton_pinctrl_probe(struct udevice *dev) +{ + int ret; + + ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins, + ARRAY_SIZE(luton_pins), luton_function_names); + + if (ret) + return ret; + + ret = device_bind(dev, &luton_gpio_driver, "luton-gpio", NULL, + dev_of_offset(dev), NULL); + + return 0; +} + +static const struct udevice_id luton_pinctrl_of_match[] = { + {.compatible = "mscc,luton-pinctrl"}, + {}, +}; + +U_BOOT_DRIVER(luton_pinctrl) = { + .name = "luton-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(luton_pinctrl_of_match), + .probe = luton_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl), + .ops = &mscc_pinctrl_ops, +}; diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c new file mode 100644 index 0000000000..10f9b90aad --- /dev/null +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Microsemi SoCs pinctrl driver + * + * Author: + * Author: + * License: Dual MIT/GPL + * Copyright (c) 2017 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mscc-common.h" + +enum { + FUNC_NONE, + FUNC_GPIO, + FUNC_IRQ0_IN, + FUNC_IRQ0_OUT, + FUNC_IRQ1_IN, + FUNC_IRQ1_OUT, + FUNC_MIIM1, + FUNC_PCI_WAKE, + FUNC_PTP0, + FUNC_PTP1, + FUNC_PTP2, + FUNC_PTP3, + FUNC_PWM, + FUNC_RECO_CLK0, + FUNC_RECO_CLK1, + FUNC_SFP0, + FUNC_SFP1, + FUNC_SFP2, + FUNC_SFP3, + FUNC_SFP4, + FUNC_SFP5, + FUNC_SG0, + FUNC_SI, + FUNC_TACHO, + FUNC_TWI, + FUNC_TWI_SCL_M, + FUNC_UART, + FUNC_UART2, + FUNC_MAX +}; + +static char * const ocelot_function_names[] = { + [FUNC_NONE] = "none", + [FUNC_GPIO] = "gpio", + [FUNC_IRQ0_IN] = "irq0_in", + [FUNC_IRQ0_OUT] = "irq0_out", + [FUNC_IRQ1_IN] = "irq1_in", + [FUNC_IRQ1_OUT] = "irq1_out", + [FUNC_MIIM1] = "miim1", + [FUNC_PCI_WAKE] = "pci_wake", + [FUNC_PTP0] = "ptp0", + [FUNC_PTP1] = "ptp1", + [FUNC_PTP2] = "ptp2", + [FUNC_PTP3] = "ptp3", + [FUNC_PWM] = "pwm", + [FUNC_RECO_CLK0] = "reco_clk0", + [FUNC_RECO_CLK1] = "reco_clk1", + [FUNC_SFP0] = "sfp0", + [FUNC_SFP1] = "sfp1", + [FUNC_SFP2] = "sfp2", + [FUNC_SFP3] = "sfp3", + [FUNC_SFP4] = "sfp4", + [FUNC_SFP5] = "sfp5", + [FUNC_SG0] = "sg0", + [FUNC_SI] = "si", + [FUNC_TACHO] = "tacho", + [FUNC_TWI] = "twi", + [FUNC_TWI_SCL_M] = "twi_scl_m", + [FUNC_UART] = "uart", + [FUNC_UART2] = "uart2", +}; + +MSCC_P(0, SG0, NONE, NONE); +MSCC_P(1, SG0, NONE, NONE); +MSCC_P(2, SG0, NONE, NONE); +MSCC_P(3, SG0, NONE, NONE); +MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI); +MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE); +MSCC_P(6, UART, TWI_SCL_M, NONE); +MSCC_P(7, UART, TWI_SCL_M, NONE); +MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT); +MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT); +MSCC_P(10, PTP2, TWI_SCL_M, SFP0); +MSCC_P(11, PTP3, TWI_SCL_M, SFP1); +MSCC_P(12, UART2, TWI_SCL_M, SFP2); +MSCC_P(13, UART2, TWI_SCL_M, SFP3); +MSCC_P(14, MIIM1, TWI_SCL_M, SFP4); +MSCC_P(15, MIIM1, TWI_SCL_M, SFP5); +MSCC_P(16, TWI, NONE, SI); +MSCC_P(17, TWI, TWI_SCL_M, SI); +MSCC_P(18, PTP0, TWI_SCL_M, NONE); +MSCC_P(19, PTP1, TWI_SCL_M, NONE); +MSCC_P(20, RECO_CLK0, TACHO, NONE); +MSCC_P(21, RECO_CLK1, PWM, NONE); + +#define OCELOT_PIN(n) { \ + .name = "GPIO_"#n, \ + .drv_data = &mscc_pin_##n \ +} + +static const struct mscc_pin_data ocelot_pins[] = { + OCELOT_PIN(0), + OCELOT_PIN(1), + OCELOT_PIN(2), + OCELOT_PIN(3), + OCELOT_PIN(4), + OCELOT_PIN(5), + OCELOT_PIN(6), + OCELOT_PIN(7), + OCELOT_PIN(8), + OCELOT_PIN(9), + OCELOT_PIN(10), + OCELOT_PIN(11), + OCELOT_PIN(12), + OCELOT_PIN(13), + OCELOT_PIN(14), + OCELOT_PIN(15), + OCELOT_PIN(16), + OCELOT_PIN(17), + OCELOT_PIN(18), + OCELOT_PIN(19), + OCELOT_PIN(20), + OCELOT_PIN(21), +}; + +static int ocelot_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = "ocelot-gpio"; + uc_priv->gpio_count = ARRAY_SIZE(ocelot_pins); + + return 0; +} + +static struct driver ocelot_gpio_driver = { + .name = "ocelot-gpio", + .id = UCLASS_GPIO, + .probe = ocelot_gpio_probe, + .ops = &mscc_gpio_ops, +}; + +int ocelot_pinctrl_probe(struct udevice *dev) +{ + int ret; + + ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins, + ARRAY_SIZE(ocelot_pins), + ocelot_function_names); + + if (ret) + return ret; + + ret = device_bind(dev, &ocelot_gpio_driver, "ocelot-gpio", NULL, + dev_of_offset(dev), NULL); + + return ret; +} + +static const struct udevice_id ocelot_pinctrl_of_match[] = { + {.compatible = "mscc,ocelot-pinctrl"}, + {}, +}; + +U_BOOT_DRIVER(ocelot_pinctrl) = { + .name = "ocelot-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(ocelot_pinctrl_of_match), + .probe = ocelot_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl), + .ops = &mscc_pinctrl_ops, +}; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 799d1d2465..f1d5a5c50d 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -74,3 +74,17 @@ config PINCTRL_IMX8 is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configures related registers. + +config PINCTRL_VYBRID + bool "Vybrid (vf610) pinctrl driver" + depends on ARCH_VF610 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the Vybrid (vf610) pinctrl driver + + This provides a simple pinctrl driver for Vybrid SoC familiy, + vf610. This feature depends on device tree + configuration. This driver is different from the linux one, + this is a simple implementation, only parses the 'fsl,pins' + property and configure related registers. diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 310b3b3a2e..891ee6e477 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o +obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c index 5d17380919..4e831b6f39 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx5.c +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -40,5 +40,7 @@ U_BOOT_DRIVER(imx5_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index e63ecbdee6..d7c95bb738 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -49,5 +49,7 @@ U_BOOT_DRIVER(imx6_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c index 769d428dda..8776fd9650 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -37,5 +37,7 @@ U_BOOT_DRIVER(imx7_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index 598bbfaf35..d778f82aac 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -41,5 +41,7 @@ U_BOOT_DRIVER(imx7ulp_pinctrl) = { .remove = imx_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), .ops = &imx_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c new file mode 100644 index 0000000000..e795b5fd8a --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-vf610.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include +#include +#include + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = { + .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, +}; + +static int vf610_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id vf610_pinctrl_match[] = { + { .compatible = "fsl,vf610-iomuxc", + .data = (ulong)&vf610_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(vf610_pinctrl) = { + .name = "vf610-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(vf610_pinctrl_match), + .probe = vf610_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c index 755ac08bdf..0786afe747 100644 --- a/drivers/pinctrl/pinctrl-sandbox.c +++ b/drivers/pinctrl/pinctrl-sandbox.c @@ -17,6 +17,14 @@ static const char * const sandbox_pins[] = { "W1" }; +static const char * const sandbox_pins_muxing[] = { + "I2C SCL", + "I2C SDA", + "Uart TX", + "Uart RX", + "1-wire gpio", +}; + static const char * const sandbox_groups[] = { "i2c", "serial_a", @@ -56,6 +64,15 @@ static const char *sandbox_get_pin_name(struct udevice *dev, unsigned selector) return sandbox_pins[selector]; } +static int sandbox_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, int size) +{ + snprintf(buf, size, "%s", sandbox_pins_muxing[selector]); + + return 0; +} + static int sandbox_get_groups_count(struct udevice *dev) { return ARRAY_SIZE(sandbox_groups); @@ -123,6 +140,7 @@ static int sandbox_pinconf_group_set(struct udevice *dev, const struct pinctrl_ops sandbox_pinctrl_ops = { .get_pins_count = sandbox_get_pins_count, .get_pin_name = sandbox_get_pin_name, + .get_pin_muxing = sandbox_get_pin_muxing, .get_groups_count = sandbox_get_groups_count, .get_group_name = sandbox_get_group_name, .get_functions_count = sandbox_get_functions_count, diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d80c6eda70..9dec88c1aa 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -136,7 +136,6 @@ U_BOOT_DRIVER(single_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = single_pinctrl_match, .ops = &single_pinctrl_ops, - .flags = DM_FLAG_PRE_RELOC, .platdata_auto_alloc_size = sizeof(struct single_pdata), .ofdata_to_platdata = single_ofdata_to_platdata, }; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index c38bb212ed..c8b38d78f6 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -27,6 +27,28 @@ int pinctrl_decode_pin_config(const void *blob, int node) return flags; } +/* + * TODO: this function is temporary for v2019.01. + * It should be renamed to pinctrl_decode_pin_config(), + * the original pinctrl_decode_pin_config() function should + * be removed and all callers of the original function should + * be migrated to use the new one. + */ +int pinctrl_decode_pin_config_dm(struct udevice *dev) +{ + int pinconfig = 0; + + if (dev->uclass->uc_drv->id != UCLASS_PINCONFIG) + return -EINVAL; + + if (dev_read_bool(dev, "bias-pull-up")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_UP; + else if (dev_read_bool(dev, "bias-pull-down")) + pinconfig |= 1 << PIN_CONFIG_BIAS_PULL_DOWN; + + return pinconfig; +} + #if CONFIG_IS_ENABLED(PINCTRL_FULL) /** * pinctrl_config_one() - apply pinctrl settings for a single node @@ -117,9 +139,9 @@ static int pinconfig_post_bind(struct udevice *dev) int ret; dev_for_each_subnode(node, dev) { - if (pre_reloc_only && - !ofnode_pre_reloc(node)) + if (pre_reloc_only ^ ofnode_pre_reloc(node)) continue; + /* * If this node has "compatible" property, this is not * a pin configuration node, but a normal device. skip. @@ -249,6 +271,40 @@ int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) return ops->get_gpio_mux(dev, banknum, index); } +int pinctrl_get_pins_count(struct udevice *dev) +{ + struct pinctrl_ops *ops = pinctrl_get_ops(dev); + + if (!ops->get_pins_count) + return -ENOSYS; + + return ops->get_pins_count(dev); +} + +int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf, + int size) +{ + struct pinctrl_ops *ops = pinctrl_get_ops(dev); + + if (!ops->get_pin_name) + return -ENOSYS; + + snprintf(buf, size, ops->get_pin_name(dev, selector)); + + return 0; +} + +int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf, + int size) +{ + struct pinctrl_ops *ops = pinctrl_get_ops(dev); + + if (!ops->get_pin_muxing) + return -ENOSYS; + + return ops->get_pin_muxing(dev, selector, buf, size); +} + /** * pinconfig_post_bind() - post binding for PINCTRL uclass * Recursively bind child nodes as pinconfig devices in case of full pinctrl. diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 31285cdd57..24affe0414 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -14,17 +15,242 @@ DECLARE_GLOBAL_DATA_PTR; #define OTYPE_MSK 1 #define AFR_MASK 0xF +struct stm32_pinctrl_priv { + struct hwspinlock hws; + int pinctrl_ngpios; + struct list_head gpio_dev; +}; + +struct stm32_gpio_bank { + struct udevice *gpio_dev; + struct list_head list; +}; + +#ifndef CONFIG_SPL_BUILD + +static char pin_name[PINNAME_SIZE]; +#define PINMUX_MODE_COUNT 5 +static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { + "gpio input", + "gpio output", + "analog", + "unknown", + "alt function", +}; + +static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) +{ + struct stm32_gpio_priv *priv = dev_get_priv(dev); + struct stm32_gpio_regs *regs = priv->regs; + u32 af; + u32 alt_shift = (offset % 8) * 4; + u32 alt_index = offset / 8; + + af = (readl(®s->afr[alt_index]) & + GENMASK(alt_shift + 3, alt_shift)) >> alt_shift; + + return af; +} + +static int stm32_populate_gpio_dev_list(struct udevice *dev) +{ + struct stm32_pinctrl_priv *priv = dev_get_priv(dev); + struct udevice *gpio_dev; + struct udevice *child; + struct stm32_gpio_bank *gpio_bank; + int ret; + + /* + * parse pin-controller sub-nodes (ie gpio bank nodes) and fill + * a list with all gpio device reference which belongs to the + * current pin-controller. This list is used to find pin_name and + * pin muxing + */ + list_for_each_entry(child, &dev->child_head, sibling_node) { + ret = uclass_get_device_by_name(UCLASS_GPIO, child->name, + &gpio_dev); + if (ret < 0) + continue; + + gpio_bank = malloc(sizeof(*gpio_bank)); + if (!gpio_bank) { + dev_err(dev, "Not enough memory\n"); + return -ENOMEM; + } + + gpio_bank->gpio_dev = gpio_dev; + list_add_tail(&gpio_bank->list, &priv->gpio_dev); + } + + return 0; +} + +static int stm32_pinctrl_get_pins_count(struct udevice *dev) +{ + struct stm32_pinctrl_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv; + struct stm32_gpio_bank *gpio_bank; + + /* + * if get_pins_count has already been executed once on this + * pin-controller, no need to run it again + */ + if (priv->pinctrl_ngpios) + return priv->pinctrl_ngpios; + + if (list_empty(&priv->gpio_dev)) + stm32_populate_gpio_dev_list(dev); + /* + * walk through all banks to retrieve the pin-controller + * pins number + */ + list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { + uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); + + priv->pinctrl_ngpios += uc_priv->gpio_count; + } + + return priv->pinctrl_ngpios; +} + +static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev, + unsigned int selector, + unsigned int *idx) +{ + struct stm32_pinctrl_priv *priv = dev_get_priv(dev); + struct stm32_gpio_bank *gpio_bank; + struct gpio_dev_priv *uc_priv; + int pin_count = 0; + + if (list_empty(&priv->gpio_dev)) + stm32_populate_gpio_dev_list(dev); + + /* look up for the bank which owns the requested pin */ + list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { + uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); + + if (selector < (pin_count + uc_priv->gpio_count)) { + /* + * we found the bank, convert pin selector to + * gpio bank index + */ + *idx = stm32_offset_to_index(gpio_bank->gpio_dev, + selector - pin_count); + if (*idx < 0) + return NULL; + + return gpio_bank->gpio_dev; + } + pin_count += uc_priv->gpio_count; + } + + return NULL; +} + +static const char *stm32_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct gpio_dev_priv *uc_priv; + struct udevice *gpio_dev; + unsigned int gpio_idx; + + /* look up for the bank which owns the requested pin */ + gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); + if (!gpio_dev) { + snprintf(pin_name, PINNAME_SIZE, "Error"); + } else { + uc_priv = dev_get_uclass_priv(gpio_dev); + + snprintf(pin_name, PINNAME_SIZE, "%s%d", + uc_priv->bank_name, + gpio_idx); + } + + return pin_name; +} + +static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, + int size) +{ + struct udevice *gpio_dev; + const char *label; + int mode; + int af_num; + unsigned int gpio_idx; + + /* look up for the bank which owns the requested pin */ + gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); + + if (!gpio_dev) + return -ENODEV; + + mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label); + + dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", + selector, gpio_idx, mode); + + + switch (mode) { + case GPIOF_UNKNOWN: + /* should never happen */ + return -EINVAL; + case GPIOF_UNUSED: + snprintf(buf, size, "%s", pinmux_mode[mode]); + break; + case GPIOF_FUNC: + af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); + snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num); + break; + case GPIOF_OUTPUT: + case GPIOF_INPUT: + snprintf(buf, size, "%s %s", + pinmux_mode[mode], label ? label : ""); + break; + } + + return 0; +} + +#endif + +int stm32_pinctrl_probe(struct udevice *dev) +{ + struct stm32_pinctrl_priv *priv = dev_get_priv(dev); + int ret; + + INIT_LIST_HEAD(&priv->gpio_dev); + + /* hwspinlock property is optional, just log the error */ + ret = hwspinlock_get_by_index(dev, 0, &priv->hws); + if (ret) + debug("%s: hwspinlock_get_by_index may have failed (%d)\n", + __func__, ret); + + return 0; +} + static int stm32_gpio_config(struct gpio_desc *desc, const struct stm32_gpio_ctl *ctl) { struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); struct stm32_gpio_regs *regs = priv->regs; + struct stm32_pinctrl_priv *ctrl_priv; + int ret; u32 index; if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || ctl->pupd > 2 || ctl->speed > 3) return -EINVAL; + ctrl_priv = dev_get_priv(dev_get_parent(desc->dev)); + ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10); + if (ret == -ETIME) { + dev_err(desc->dev, "HWSpinlock timeout\n"); + return ret; + } + index = (desc->offset & 0x07) * 4; clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, ctl->af << index); @@ -39,6 +265,8 @@ static int stm32_gpio_config(struct gpio_desc *desc, index = desc->offset; clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + hwspinlock_unlock(&ctrl_priv->hws); + return 0; } @@ -182,6 +410,11 @@ static struct pinctrl_ops stm32_pinctrl_ops = { #else /* PINCTRL_FULL */ .set_state_simple = stm32_pinctrl_set_state_simple, #endif /* PINCTRL_FULL */ +#ifndef CONFIG_SPL_BUILD + .get_pin_name = stm32_pinctrl_get_pin_name, + .get_pins_count = stm32_pinctrl_get_pins_count, + .get_pin_muxing = stm32_pinctrl_get_pin_muxing, +#endif }; static const struct udevice_id stm32_pinctrl_ids[] = { @@ -195,9 +428,11 @@ static const struct udevice_id stm32_pinctrl_ids[] = { }; U_BOOT_DRIVER(pinctrl_stm32) = { - .name = "pinctrl_stm32", - .id = UCLASS_PINCTRL, - .of_match = stm32_pinctrl_ids, - .ops = &stm32_pinctrl_ops, - .bind = dm_scan_fdt_dev, + .name = "pinctrl_stm32", + .id = UCLASS_PINCTRL, + .of_match = stm32_pinctrl_ids, + .ops = &stm32_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = stm32_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv), }; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index bc92dd7c06..5c5af3a0bd 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) 2018 Theobroma Systems Design und Consulting GmbH */ #include @@ -14,11 +15,241 @@ #include #include +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) +static const u32 RK_GRF_P_PULLUP = 1; +static const u32 RK_GRF_P_PULLDOWN = 2; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ + struct rk3399_pinctrl_priv { struct rk3399_grf_regs *grf; struct rk3399_pmugrf_regs *pmugrf; + struct rockchip_pin_bank *banks; }; +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) +/* Location of pinctrl/pinconf registers. */ +enum rk_grf_location { + RK_GRF, + RK_PMUGRF, +}; + +/** + * @nr_pins: number of pins in this bank + * @grf_location: location of pinctrl/pinconf registers + * @bank_num: number of the bank, to account for holes + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u8 nr_pins; + enum rk_grf_location grf_location; + size_t iomux_offset; + size_t pupd_offset; +}; + +#define PIN_BANK(pins, grf, iomux, pupd) \ + { \ + .nr_pins = pins, \ + .grf_location = grf, \ + .iomux_offset = iomux, \ + .pupd_offset = pupd, \ + } + +static struct rockchip_pin_bank rk3399_pin_banks[] = { + PIN_BANK(16, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio0_p)), + PIN_BANK(32, RK_PMUGRF, + offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux), + offsetof(struct rk3399_pmugrf_regs, gpio1_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio2a_iomux), + offsetof(struct rk3399_grf_regs, gpio2_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio3a_iomux), + offsetof(struct rk3399_grf_regs, gpio3_p)), + PIN_BANK(32, RK_GRF, + offsetof(struct rk3399_grf_regs, gpio4a_iomux), + offsetof(struct rk3399_grf_regs, gpio4_p)), +}; + +static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr, + u32 *shift, u32 *mask) +{ + /* + * In general we four subsequent 32-bit configuration registers + * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P). + * The configuration for each pin has two bits. + * + * @base...contains the address to the first register. + * @index...defines the pin within the bank (0..31). + * @addr...will be the address of the actual register to use + * @shift...will be the bit position in the configuration register + * @mask...will be the (unshifted) mask + */ + + const u32 pins_per_register = 8; + const u32 config_bits_per_pin = 2; + + /* Get the address of the configuration register. */ + *addr = base + (index / pins_per_register) * sizeof(u32); + + /* Get the bit offset within the configuration register. */ + *shift = (index & (pins_per_register - 1)) * config_bits_per_pin; + + /* Get the (unshifted) mask for the configuration pins. */ + *mask = ((1 << config_bits_per_pin) - 1); + + pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n", + __func__, *addr, *mask, *shift); +} + +static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, u32 muxval) +{ + uintptr_t iomux_base, addr; + u32 shift, mask; + + iomux_base = grf_addr + bank->iomux_offset; + rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask); + + /* Set pinmux register */ + rk_clrsetreg(addr, mask << shift, muxval << shift); +} + +static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr, + struct rockchip_pin_bank *bank, + u32 index, int pinconfig) +{ + uintptr_t pupd_base, addr; + u32 shift, mask, pupdval; + + /* Fast path in case there's nothing to do. */ + if (!pinconfig) + return; + + if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP)) + pupdval = RK_GRF_P_PULLUP; + else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) { + pupdval = RK_GRF_P_PULLDOWN; + } else { + /* Flag not supported. */ + pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__, + pinconfig); + return; + } + + pupd_base = grf_addr + (uintptr_t)bank->pupd_offset; + rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask); + + /* Set pull-up/pull-down regisrer */ + rk_clrsetreg(addr, mask << shift, pupdval << shift); +} + +static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index, + u32 muxval, int pinconfig) +{ + struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); + struct rockchip_pin_bank *bank = &priv->banks[banknum]; + uintptr_t grf_addr; + + pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval, + pinconfig); + + if (bank->grf_location == RK_GRF) + grf_addr = (uintptr_t)priv->grf; + else if (bank->grf_location == RK_PMUGRF) + grf_addr = (uintptr_t)priv->pmugrf; + else + return -EINVAL; + + rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval); + + rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig); + return 0; +} + +static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + /* + * The order of the fields in this struct must match the order of + * the fields in the "rockchip,pins" property. + */ + struct rk_pin { + u32 banknum; + u32 index; + u32 muxval; + u32 phandle; + } __packed; + + u32 *fields = NULL; + const int fields_per_pin = 4; + int num_fields, num_pins; + int ret; + int size; + int i; + struct rk_pin *pin; + + pr_debug("%s: %s\n", __func__, config->name); + + size = dev_read_size(config, "rockchip,pins"); + if (size < 0) + return -EINVAL; + + num_fields = size / sizeof(u32); + num_pins = num_fields / fields_per_pin; + + if (num_fields * sizeof(u32) != size || + num_pins * fields_per_pin != num_fields) { + pr_warn("Invalid number of rockchip,pins fields.\n"); + return -EINVAL; + } + + fields = calloc(num_fields, sizeof(u32)); + if (!fields) + return -ENOMEM; + + ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields); + if (ret) { + pr_warn("%s: Failed to read rockchip,pins fields.\n", + config->name); + goto end; + } + + pin = (struct rk_pin *)fields; + for (i = 0; i < num_pins; i++, pin++) { + struct udevice *dev_pinconfig; + int pinconfig; + + ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG, + pin->phandle, + &dev_pinconfig); + if (ret) { + pr_debug("Could not get pinconfig device\n"); + goto end; + } + + pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig); + if (pinconfig < 0) { + pr_warn("Could not parse pinconfig\n"); + goto end; + } + + ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index, + pin->muxval, pinconfig); + if (ret) { + pr_warn("Could not set pinctrl settings\n"); + goto end; + } + } + +end: + free(fields); + return ret; +} + +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ + static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, struct rk3399_pmugrf_regs *pmugrf, int pwm_id) { @@ -468,6 +699,9 @@ static int rk3399_pinctrl_set_state_simple(struct udevice *dev, } static struct pinctrl_ops rk3399_pinctrl_ops = { +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) + .set_state = rk3399_pinctrl_set_state, +#endif .set_state_simple = rk3399_pinctrl_set_state_simple, .request = rk3399_pinctrl_request, .get_periph_id = rk3399_pinctrl_get_periph_id, @@ -481,6 +715,9 @@ static int rk3399_pinctrl_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); +#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL) + priv->banks = rk3399_pin_banks; +#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */ return ret; } diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index a1da90baa4..eb5978a166 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -171,5 +171,7 @@ U_BOOT_DRIVER(uniphier_pro4_pinctrl) = { .probe = uniphier_pro4_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 0ba2052b29..685d8be80c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -153,5 +153,7 @@ U_BOOT_DRIVER(uniphier_pro5_pinctrl) = { .probe = uniphier_pro5_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 1a3852442a..9495dca33b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -197,6 +197,49 @@ config AXP_ALDO3_VOLT On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be 3.0V. +choice + prompt "axp pmic (a)ldo3 voltage rate control" + depends on AXP209_POWER + default AXP_ALDO3_VOLT_SLOPE_NONE + ---help--- + The AXP can slowly ramp up voltage to reduce the inrush current when + changing voltages. + Note, this does not apply when enabling/disabling LDO3. See + "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit + inrush current on broken board designs. + +config AXP_ALDO3_VOLT_SLOPE_NONE + bool "No voltage slope" + ---help--- + Tries to reach the next voltage setting near instantaneously. Measurements + indicate that this is about 0.0167 V/uS. + +config AXP_ALDO3_VOLT_SLOPE_16 + bool "1.6 mV per uS" + ---help--- + Increases the voltage by 1.6 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps and thus + the slew rate in reality is about 25 mV/31.250 uS. + +config AXP_ALDO3_VOLT_SLOPE_08 + bool "0.8 mV per uS" + ---help--- + Increases the voltage by 0.8 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps however and thus + the slew rate in reality is about 25 mV/15.625 uS. + This is the slowest supported rate. + +endchoice + +config AXP_ALDO3_INRUSH_QUIRK + bool "axp pmic (a)ldo3 inrush quirk" + depends on AXP209_POWER + default n + ---help--- + The reference design denotes a value of 4.7 uF for the output capacitor + of LDO3. Some boards have too high capacitance causing an inrush current + and resulting an AXP209 shutdown. + config AXP_ALDO4_VOLT int "axp pmic (a)ldo4 voltage" depends on AXP209_POWER diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 6de5ec6825..67b420910c 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -9,6 +9,16 @@ #include #include +#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_08 +# define AXP209_VRC_SLOPE AXP209_VRC_LDO3_800uV_uS +#endif +#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_16 +# define AXP209_VRC_SLOPE AXP209_VRC_LDO3_1600uV_uS +#endif +#if defined CONFIG_AXP_ALDO3_VOLT_SLOPE_NONE || !defined AXP209_VRC_SLOPE +# define AXP209_VRC_SLOPE 0x00 +#endif + static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div) { if (mvolt < min) @@ -81,8 +91,7 @@ int axp_set_aldo2(unsigned int mvolt) if (rc) return rc; - /* LDO2 configuration is in upper 4 bits */ - reg = (reg & 0x0f) | (cfg << 4); + reg |= AXP209_LDO24_LDO2_SET(reg, cfg); rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg); if (rc) return rc; @@ -99,10 +108,49 @@ int axp_set_aldo3(unsigned int mvolt) return pmic_bus_clrbits(AXP209_OUTPUT_CTRL, AXP209_OUTPUT_CTRL_LDO3); - if (mvolt == -1) - cfg = 0x80; /* determined by LDO3IN pin */ - else + /* + * Some boards have trouble reaching the target voltage without causing + * great inrush currents. To prevent this, boards can enable a certain + * slope to ramp up voltage. Note, this only works when changing an + * already active power rail. When toggling power on, the AXP ramps up + * steeply at 0.0167 V/uS. + */ + rc = pmic_bus_read(AXP209_VRC_DCDC2_LDO3, &cfg); + cfg = AXP209_VRC_LDO3_SLOPE_SET(cfg, AXP209_VRC_SLOPE); + rc |= pmic_bus_write(AXP209_VRC_DCDC2_LDO3, cfg); + + if (rc) + return rc; + +#ifdef CONFIG_AXP_ALDO3_INRUSH_QUIRK + /* + * On some boards, LDO3 has a too big capacitor installed. When + * turning on LDO3, this causes the AXP209 to shutdown on + * voltages over 1.9 volt. As a workaround, we enable LDO3 + * first with the lowest possible voltage. If this still causes + * high inrush currents, the voltage slope should be increased. + */ + rc = pmic_bus_read(AXP209_OUTPUT_CTRL, &cfg); + if (rc) + return rc; + + if (!(cfg & AXP209_OUTPUT_CTRL_LDO3)) { + rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, 0x0); /* 0.7 Volt */ + mdelay(1); + rc |= pmic_bus_setbits(AXP209_OUTPUT_CTRL, + AXP209_OUTPUT_CTRL_LDO3); + + if (rc) + return rc; + } +#endif + + if (mvolt == -1) { + cfg = AXP209_LDO3_VOLTAGE_FROM_LDO3IN; + } else { cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); + cfg = AXP209_LDO3_VOLTAGE_SET(cfg); + } rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, cfg); if (rc) @@ -131,8 +179,7 @@ int axp_set_aldo4(unsigned int mvolt) if (rc) return rc; - /* LDO4 configuration is in lower 4 bits */ - reg = (reg & 0xf0) | (cfg << 0); + reg |= AXP209_LDO24_LDO4_SET(reg, cfg); rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg); if (rc) return rc; @@ -153,10 +200,7 @@ int axp_init(void) if (rc) return rc; - /* Low 4 bits is chip version */ - ver &= 0x0f; - - if (ver != 0x1) + if ((ver & AXP209_CHIP_VERSION_MASK) != 0x1) return -EINVAL; /* Mask all interrupts */ diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index a08b4288b4..93deaef809 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC requests to the SCU. +config MTK_POWER_DOMAIN + bool "Enable the MediaTek power domain driver" + depends on POWER_DOMAIN && ARCH_MEDIATEK + help + Enable support for manipulating MediaTek power domains via MMIO + mapped registers. + config MESON_GX_VPU_POWER_DOMAIN bool "Enable Amlogic Meson GX VPU power domain driver" depends on ARCH_MESON diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index b08d18f7ac..695aafe17d 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o +obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c new file mode 100644 index 0000000000..c67e8804b1 --- /dev/null +++ b/drivers/power/domain/mtk-power-domain.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SPM_EN (0xb16 << 16 | 0x1) +#define SPM_VDE_PWR_CON 0x0210 +#define SPM_MFG_PWR_CON 0x0214 +#define SPM_ISP_PWR_CON 0x0238 +#define SPM_DIS_PWR_CON 0x023c +#define SPM_CONN_PWR_CON 0x0280 +#define SPM_BDP_PWR_CON 0x029c +#define SPM_ETH_PWR_CON 0x02a0 +#define SPM_HIF_PWR_CON 0x02a4 +#define SPM_IFR_MSC_PWR_CON 0x02a8 +#define SPM_ETHSYS_PWR_CON 0x2e0 +#define SPM_HIF0_PWR_CON 0x2e4 +#define SPM_HIF1_PWR_CON 0x2e8 +#define SPM_PWR_STATUS 0x60c +#define SPM_PWR_STATUS_2ND 0x610 + +#define PWR_RST_B_BIT BIT(0) +#define PWR_ISO_BIT BIT(1) +#define PWR_ON_BIT BIT(2) +#define PWR_ON_2ND_BIT BIT(3) +#define PWR_CLK_DIS_BIT BIT(4) + +#define PWR_STATUS_CONN BIT(1) +#define PWR_STATUS_DISP BIT(3) +#define PWR_STATUS_MFG BIT(4) +#define PWR_STATUS_ISP BIT(5) +#define PWR_STATUS_VDEC BIT(7) +#define PWR_STATUS_BDP BIT(14) +#define PWR_STATUS_ETH BIT(15) +#define PWR_STATUS_HIF BIT(16) +#define PWR_STATUS_IFR_MSC BIT(17) +#define PWR_STATUS_ETHSYS BIT(24) +#define PWR_STATUS_HIF0 BIT(25) +#define PWR_STATUS_HIF1 BIT(26) + +/* Infrasys configuration */ +#define INFRA_TOPDCM_CTRL 0x10 +#define INFRA_TOPAXI_PROT_EN 0x220 +#define INFRA_TOPAXI_PROT_STA1 0x228 + +#define DCM_TOP_EN BIT(0) + +enum scp_domain_type { + SCPSYS_MT7623, + SCPSYS_MT7629, +}; + +struct scp_domain; + +struct scp_domain_data { + struct scp_domain *scpd; + u32 sta_mask; + int ctl_offs; + u32 sram_pdn_bits; + u32 sram_pdn_ack_bits; + u32 bus_prot_mask; +}; + +struct scp_domain { + void __iomem *base; + void __iomem *infracfg; + enum scp_domain_type type; + struct scp_domain_data *data; +}; + +static struct scp_domain_data scp_domain_mt7623[] = { + [MT7623_POWER_DOMAIN_CONN] = { + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .bus_prot_mask = BIT(8) | BIT(2), + }, + [MT7623_POWER_DOMAIN_DISP] = { + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .bus_prot_mask = BIT(2), + }, + [MT7623_POWER_DOMAIN_MFG] = { + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT7623_POWER_DOMAIN_VDEC] = { + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT7623_POWER_DOMAIN_ISP] = { + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT7623_POWER_DOMAIN_BDP] = { + .sta_mask = PWR_STATUS_BDP, + .ctl_offs = SPM_BDP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + }, + [MT7623_POWER_DOMAIN_ETH] = { + .sta_mask = PWR_STATUS_ETH, + .ctl_offs = SPM_ETH_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT7623_POWER_DOMAIN_HIF] = { + .sta_mask = PWR_STATUS_HIF, + .ctl_offs = SPM_HIF_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT7623_POWER_DOMAIN_IFR_MSC] = { + .sta_mask = PWR_STATUS_IFR_MSC, + .ctl_offs = SPM_IFR_MSC_PWR_CON, + }, +}; + +static struct scp_domain_data scp_domain_mt7629[] = { + [MT7629_POWER_DOMAIN_ETHSYS] = { + .sta_mask = PWR_STATUS_ETHSYS, + .ctl_offs = SPM_ETHSYS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = (BIT(3) | BIT(17)), + }, + [MT7629_POWER_DOMAIN_HIF0] = { + .sta_mask = PWR_STATUS_HIF0, + .ctl_offs = SPM_HIF0_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = GENMASK(25, 24), + }, + [MT7629_POWER_DOMAIN_HIF1] = { + .sta_mask = PWR_STATUS_HIF1, + .ctl_offs = SPM_HIF1_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bus_prot_mask = GENMASK(28, 26), + }, +}; + +/** + * This function enables the bus protection bits for disabled power + * domains so that the system does not hang when some unit accesses the + * bus while in power down. + */ +static int mtk_infracfg_set_bus_protection(void __iomem *infracfg, + u32 mask) +{ + u32 val; + + clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask); + + return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, + (val & mask) == mask, 100); +} + +static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg, + u32 mask) +{ + u32 val; + + clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask); + + return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, + !(val & mask), 100); +} + +static int scpsys_domain_is_on(struct scp_domain_data *data) +{ + struct scp_domain *scpd = data->scpd; + u32 sta = readl(scpd->base + SPM_PWR_STATUS) & + data->sta_mask; + u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) & + data->sta_mask; + + /* + * A domain is on when both status bits are set. If only one is set + * return an error. This happens while powering up a domain + */ + if (sta && sta2) + return true; + if (!sta && !sta2) + return false; + + return -EINVAL; +} + +static int scpsys_power_on(struct power_domain *power_domain) +{ + struct scp_domain *scpd = dev_get_priv(power_domain->dev); + struct scp_domain_data *data = &scpd->data[power_domain->id]; + void __iomem *ctl_addr = scpd->base + data->ctl_offs; + u32 pdn_ack = data->sram_pdn_ack_bits; + u32 val; + int ret, tmp; + + writel(SPM_EN, scpd->base); + + val = readl(ctl_addr); + val |= PWR_ON_BIT; + writel(val, ctl_addr); + + val |= PWR_ON_2ND_BIT; + writel(val, ctl_addr); + + ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0, + 100); + if (ret < 0) + return ret; + + val &= ~PWR_CLK_DIS_BIT; + writel(val, ctl_addr); + + val &= ~PWR_ISO_BIT; + writel(val, ctl_addr); + + val |= PWR_RST_B_BIT; + writel(val, ctl_addr); + + val &= ~data->sram_pdn_bits; + writel(val, ctl_addr); + + ret = readl_poll_timeout(ctl_addr, tmp, !(tmp & pdn_ack), 100); + if (ret < 0) + return ret; + + if (data->bus_prot_mask) { + ret = mtk_infracfg_clear_bus_protection(scpd->infracfg, + data->bus_prot_mask); + if (ret) + return ret; + } + + return 0; +} + +static int scpsys_power_off(struct power_domain *power_domain) +{ + struct scp_domain *scpd = dev_get_priv(power_domain->dev); + struct scp_domain_data *data = &scpd->data[power_domain->id]; + void __iomem *ctl_addr = scpd->base + data->ctl_offs; + u32 pdn_ack = data->sram_pdn_ack_bits; + u32 val; + int ret, tmp; + + if (data->bus_prot_mask) { + ret = mtk_infracfg_set_bus_protection(scpd->infracfg, + data->bus_prot_mask); + if (ret) + return ret; + } + + val = readl(ctl_addr); + val |= data->sram_pdn_bits; + writel(val, ctl_addr); + + ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack, + 100); + if (ret < 0) + return ret; + + val |= PWR_ISO_BIT; + writel(val, ctl_addr); + + val &= ~PWR_RST_B_BIT; + writel(val, ctl_addr); + + val |= PWR_CLK_DIS_BIT; + writel(val, ctl_addr); + + val &= ~PWR_ON_BIT; + writel(val, ctl_addr); + + val &= ~PWR_ON_2ND_BIT; + writel(val, ctl_addr); + + ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100); + if (ret < 0) + return ret; + + return 0; +} + +static int scpsys_power_request(struct power_domain *power_domain) +{ + struct scp_domain *scpd = dev_get_priv(power_domain->dev); + struct scp_domain_data *data; + + data = &scpd->data[power_domain->id]; + data->scpd = scpd; + + return 0; +} + +static int scpsys_power_free(struct power_domain *power_domain) +{ + return 0; +} + +static int mtk_power_domain_hook(struct udevice *dev) +{ + struct scp_domain *scpd = dev_get_priv(dev); + + scpd->type = (enum scp_domain_type)dev_get_driver_data(dev); + + switch (scpd->type) { + case SCPSYS_MT7623: + scpd->data = scp_domain_mt7623; + break; + case SCPSYS_MT7629: + scpd->data = scp_domain_mt7629; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mtk_power_domain_probe(struct udevice *dev) +{ + struct ofnode_phandle_args args; + struct scp_domain *scpd = dev_get_priv(dev); + struct regmap *regmap; + struct clk_bulk bulk; + int err; + + scpd->base = dev_read_addr_ptr(dev); + if (!scpd->base) + return -ENOENT; + + err = mtk_power_domain_hook(dev); + if (err) + return err; + + /* get corresponding syscon phandle */ + err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args); + if (err) + return err; + + regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + scpd->infracfg = regmap_get_range(regmap, 0); + if (!scpd->infracfg) + return -ENOENT; + + /* enable Infra DCM */ + setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN); + + err = clk_get_bulk(dev, &bulk); + if (err) + return err; + + return clk_enable_bulk(&bulk); +} + +static const struct udevice_id mtk_power_domain_ids[] = { + { + .compatible = "mediatek,mt7623-scpsys", + .data = SCPSYS_MT7623, + }, + { + .compatible = "mediatek,mt7629-scpsys", + .data = SCPSYS_MT7629, + }, + { /* sentinel */ } +}; + +struct power_domain_ops mtk_power_domain_ops = { + .free = scpsys_power_free, + .off = scpsys_power_off, + .on = scpsys_power_on, + .request = scpsys_power_request, +}; + +U_BOOT_DRIVER(mtk_power_domain) = { + .name = "mtk_power_domain", + .id = UCLASS_POWER_DOMAIN, + .ops = &mtk_power_domain_ops, + .probe = mtk_power_domain_probe, + .of_match = mtk_power_domain_ids, + .priv_auto_alloc_size = sizeof(struct scp_domain), +}; diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 6d5abba5a7..2584bea38d 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -175,3 +175,42 @@ int twl603x_enable_bb_charge(u8 bb_fields) val, err); return err; } + +#ifdef CONFIG_DM_I2C +int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_write(dev, reg, val); + if (ret) { + pr_err("writing to palmas failed. ret %d\n", ret); + return ret; + } + return 0; +} + +int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_read(dev, reg); + if (ret < 0) { + pr_err("reading from palmas failed. ret %d\n", ret); + return ret; + } + *valp = (u8)ret; + return 0; +} +#endif diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index cba48e12da..8cf60ebcf3 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -48,6 +48,20 @@ config PMIC_AS3722 interface and is designs to cover most of the power managementment required for a tablets or laptop. +config DM_PMIC_FAN53555 + bool "Enable support for OnSemi FAN53555" + depends on DM_PMIC && DM_REGULATOR && DM_I2C + select DM_REGULATOR_FAN53555 + help + This config enables implementation of driver-model PMIC + uclass features for the FAN53555 regulator. The FAN53555 is + a (family of) single-output regulators that supports + transitioning between two different output voltages based on + an voltage selection pin. + + The driver implements read/write operations for use with the FAN53555 + regulator driver and binds the regulator driver to its node. + config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 29ca442933..637352ab2b 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -4,6 +4,7 @@ # Lukasz Majewski obj-$(CONFIG_DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o diff --git a/drivers/power/pmic/act8846.c b/drivers/power/pmic/act8846.c index b0c759c647..186fa907e1 100644 --- a/drivers/power/pmic/act8846.c +++ b/drivers/power/pmic/act8846.c @@ -50,7 +50,7 @@ static int act8846_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/as3722.c b/drivers/power/pmic/as3722.c index 63df613354..54adcbf50f 100644 --- a/drivers/power/pmic/as3722.c +++ b/drivers/power/pmic/as3722.c @@ -45,14 +45,14 @@ static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp) ret = pmic_reg_read(dev, AS3722_ASIC_ID1); if (ret < 0) { - pr_err("failed to read ID1 register: %d", ret); + pr_err("failed to read ID1 register: %d\n", ret); return ret; } *idp = ret; ret = pmic_reg_read(dev, AS3722_ASIC_ID2); if (ret < 0) { - pr_err("failed to read ID2 register: %d", ret); + pr_err("failed to read ID2 register: %d\n", ret); return ret; } *revisionp = ret; @@ -70,7 +70,7 @@ int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value) ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value); if (ret < 0) { - pr_err("failed to write SD%u voltage register: %d", sd, ret); + pr_err("failed to write SD%u voltage register: %d\n", sd, ret); return ret; } @@ -86,8 +86,8 @@ int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value) ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value); if (ret < 0) { - pr_err("failed to write LDO%u voltage register: %d", ldo, - ret); + pr_err("failed to write LDO%u voltage register: %d\n", ldo, + ret); return ret; } @@ -101,12 +101,12 @@ static int as3722_probe(struct udevice *dev) ret = as3722_read_id(dev, &id, &revision); if (ret < 0) { - pr_err("failed to read ID: %d", ret); + pr_err("failed to read ID: %d\n", ret); return ret; } if (id != AS3722_DEVICE_ID) { - pr_err("unknown device"); + pr_err("unknown device\n"); return -ENOENT; } diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c index 36f4fbfa47..96943bc1ad 100644 --- a/drivers/power/pmic/as3722_gpio.c +++ b/drivers/power/pmic/as3722_gpio.c @@ -25,7 +25,7 @@ int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value); if (err) { - pr_err("failed to configure GPIO#%u: %d", gpio, err); + pr_err("failed to configure GPIO#%u: %d\n", gpio, err); return err; } @@ -45,7 +45,7 @@ static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio, err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT); if (err < 0) { - pr_err("failed to read GPIO signal out register: %d", err); + pr_err("failed to read GPIO signal out register: %d\n", err); return err; } value = err; @@ -60,7 +60,7 @@ static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio, err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value); if (err) { - pr_err("failed to set GPIO#%u %s: %d", gpio, l, err); + pr_err("failed to set GPIO#%u %s: %d\n", gpio, l, err); return err; } @@ -83,13 +83,14 @@ int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio, err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value); if (err) { - pr_err("failed to configure GPIO#%u as output: %d", gpio, err); + pr_err("failed to configure GPIO#%u as output: %d\n", gpio, + err); return err; } err = as3722_gpio_set_value(pmic, gpio, value); if (err < 0) { - pr_err("failed to set GPIO#%u high: %d", gpio, err); + pr_err("failed to set GPIO#%u high: %d\n", gpio, err); return err; } diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c new file mode 100644 index 0000000000..1ca59c5f0c --- /dev/null +++ b/drivers/power/pmic/fan53555.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2018 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include +#include +#include +#include + +static int pmic_fan53555_reg_count(struct udevice *dev) +{ + return 1; +}; + +static int pmic_fan53555_read(struct udevice *dev, uint reg, + u8 *buff, int len) +{ + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("%s: read error for register: %#x!", dev->name, reg); + return -EIO; + } + + return 0; +} + +static int pmic_fan53555_write(struct udevice *dev, uint reg, + const u8 *buff, int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("%s: write error for register: %#x!", dev->name, reg); + return -EIO; + } + + return 0; +} + +static int pmic_fan53555_bind(struct udevice *dev) +{ + /* + * The FAN53555 has only a single regulator and therefore doesn't + * have a subnode. So we have to rebind a child device (the one + * regulator) here. + */ + + const char *regulator_driver_name = "fan53555_regulator"; + struct udevice *child; + struct driver *drv; + + debug("%s\n", __func__); + + drv = lists_driver_lookup_name(regulator_driver_name); + if (!drv) { + dev_err(dev, "no driver '%s'\n", regulator_driver_name); + return -ENOENT; + } + + return device_bind_with_driver_data(dev, drv, "SW", 0, + dev_ofnode(dev), &child); +}; + +static struct dm_pmic_ops pmic_fan53555_ops = { + .reg_count = pmic_fan53555_reg_count, + .read = pmic_fan53555_read, + .write = pmic_fan53555_write, +}; + +static const struct udevice_id pmic_fan53555_match[] = { + { .compatible = "fcs,fan53555" }, + { }, +}; + +U_BOOT_DRIVER(pmic_fan53555) = { + .name = "pmic_fan53555", + .id = UCLASS_PMIC, + .of_match = pmic_fan53555_match, + .bind = pmic_fan53555_bind, + .ops = &pmic_fan53555_ops, +}; diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c index 61fa76a561..80efc0265d 100644 --- a/drivers/power/pmic/i2c_pmic_emul.c +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -104,7 +104,7 @@ static int sandbox_i2c_pmic_xfer(struct udevice *emul, struct i2c_msg *msg, static int sandbox_i2c_pmic_ofdata_to_platdata(struct udevice *emul) { struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); - struct udevice *pmic_dev = dev_get_parent(emul); + struct udevice *pmic_dev = i2c_emul_get_device(emul); struct uc_pmic_priv *priv = dev_get_uclass_priv(pmic_dev); const u8 *reg_defaults; diff --git a/drivers/power/pmic/lp873x.c b/drivers/power/pmic/lp873x.c index 432ad4cecf..4ae4043b94 100644 --- a/drivers/power/pmic/lp873x.c +++ b/drivers/power/pmic/lp873x.c @@ -24,7 +24,7 @@ static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -34,7 +34,7 @@ static int lp873x_write(struct udevice *dev, uint reg, const uint8_t *buff, static int lp873x_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -48,7 +48,7 @@ static int lp873x_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c index 450dbb8a78..3e5fc608d2 100644 --- a/drivers/power/pmic/lp87565.c +++ b/drivers/power/pmic/lp87565.c @@ -26,7 +26,7 @@ static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -37,7 +37,7 @@ static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return ret; } @@ -49,7 +49,7 @@ static int lp87565_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c index 834713af28..8e3a8cf870 100644 --- a/drivers/power/pmic/max77686.c +++ b/drivers/power/pmic/max77686.c @@ -28,7 +28,7 @@ static int max77686_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -38,7 +38,7 @@ static int max77686_write(struct udevice *dev, uint reg, const uint8_t *buff, static int max77686_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -52,8 +52,8 @@ static int max77686_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "voltage-regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, - dev->name); + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c index 0dcdbad583..dbae155fb3 100644 --- a/drivers/power/pmic/max8997.c +++ b/drivers/power/pmic/max8997.c @@ -23,7 +23,7 @@ static int max8997_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -34,7 +34,7 @@ static int max8997_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return ret; } diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c index f571add6e6..f58d9f2d74 100644 --- a/drivers/power/pmic/max8998.c +++ b/drivers/power/pmic/max8998.c @@ -23,7 +23,7 @@ static int max8998_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -34,7 +34,7 @@ static int max8998_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return ret; } diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 2b2fc72a47..66253a4a43 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -38,7 +38,7 @@ static int mc34708_write(struct udevice *dev, uint reg, const u8 *buff, ret = dm_i2c_write(dev, reg, buf, len); if (ret) - printf("write error to device: %p register: %#x!", dev, reg); + printf("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -53,7 +53,7 @@ static int mc34708_read(struct udevice *dev, uint reg, u8 *buff, int len) ret = dm_i2c_read(dev, reg, buf, len); if (ret) - printf("read error from device: %p register: %#x!", dev, reg); + printf("read error from device: %p register: %#x!\n", dev, reg); buff[0] = buf[2]; buff[1] = buf[1]; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index 250a5d34bb..36be119b6c 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -24,7 +24,7 @@ static int palmas_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -34,7 +34,7 @@ static int palmas_write(struct udevice *dev, uint reg, const uint8_t *buff, static int palmas_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -60,14 +60,14 @@ static int palmas_bind(struct udevice *dev) } if (!ofnode_valid(pmic_node)) { - debug("%s: %s pmic subnode not found!", __func__, dev->name); + debug("%s: %s pmic subnode not found!\n", __func__, dev->name); return -ENXIO; } regulators_node = ofnode_find_subnode(pmic_node, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s reg subnode not found!", __func__, dev->name); + debug("%s: %s reg subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/pfuze100.c b/drivers/power/pmic/pfuze100.c index 8a5a8996b4..6cf5f35f0f 100644 --- a/drivers/power/pmic/pfuze100.c +++ b/drivers/power/pmic/pfuze100.c @@ -31,7 +31,7 @@ static int pfuze100_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -41,7 +41,7 @@ static int pfuze100_write(struct udevice *dev, uint reg, const uint8_t *buff, static int pfuze100_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -55,7 +55,7 @@ static int pfuze100_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c index f2987de48e..c3977fccc3 100644 --- a/drivers/power/pmic/pmic_tps62362.c +++ b/drivers/power/pmic/pmic_tps62362.c @@ -10,6 +10,10 @@ #include #include +#ifdef CONFIG_DM_I2C +struct udevice *tps62362_dev __attribute__((section(".data"))) = NULL; +#endif + /** * tps62362_voltage_update() - Function to change a voltage level, as this * is a multi-step process. @@ -22,9 +26,16 @@ int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel) if (reg > TPS62362_NUM_REGS) return 1; +#ifndef CONFIG_DM_I2C return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1); +#else + if (!tps62362_dev) + return -ENODEV; + return dm_i2c_reg_write(tps62362_dev, reg, volt_sel); +#endif } +#ifndef CONFIG_DM_I2C int power_tps62362_init(unsigned char bus) { static const char name[] = "TPS62362"; @@ -44,3 +55,16 @@ int power_tps62362_init(unsigned char bus) return 0; } +#else +int power_tps62362_init(unsigned char bus) +{ + struct udevice *dev = NULL; + int rc; + + rc = i2c_get_chip_for_busnum(bus, TPS62362_I2C_ADDR, 1, &dev); + if (rc) + return rc; + tps62362_dev = dev; + return 0; +} +#endif diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c index 01c0ad1a8c..c839e31890 100644 --- a/drivers/power/pmic/pmic_tps65217.c +++ b/drivers/power/pmic/pmic_tps65217.c @@ -8,6 +8,8 @@ #include #include +struct udevice *tps65217_dev __attribute__((section(".data"))) = NULL; + /** * tps65217_reg_read() - Generic function that can read a TPS65217 register * @src_reg: Source register address @@ -16,7 +18,11 @@ */ int tps65217_reg_read(uchar src_reg, uchar *src_val) { +#ifndef CONFIG_DM_I2C return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1); +#else + return dm_i2c_read(tps65217_dev, src_reg, src_val, 1); +#endif } /** @@ -46,9 +52,14 @@ int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, * mask */ if (mask != TPS65217_MASK_ALL_BITS) { +#ifndef CONFIG_DM_I2C ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1); +#else + ret = dm_i2c_read(tps65217_dev, dest_reg, &read_val, 1); +#endif if (ret) return ret; + read_val &= (~mask); read_val |= (dest_val & mask); dest_val = read_val; @@ -56,23 +67,40 @@ int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, if (prot_level > 0) { xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK; +#ifndef CONFIG_DM_I2C ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, &xor_reg, 1); +#else + ret = dm_i2c_write(tps65217_dev, TPS65217_PASSWORD, + &xor_reg, 1); +#endif if (ret) return ret; } - +#ifndef CONFIG_DM_I2C ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); +#else + ret = dm_i2c_write(tps65217_dev, dest_reg, &dest_val, 1); +#endif if (ret) return ret; if (prot_level == TPS65217_PROT_LEVEL_2) { +#ifndef CONFIG_DM_I2C ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1, &xor_reg, 1); +#else + ret = dm_i2c_write(tps65217_dev, TPS65217_PASSWORD, + &xor_reg, 1); +#endif if (ret) return ret; +#ifndef CONFIG_DM_I2C ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1); +#else + ret = dm_i2c_write(tps65217_dev, dest_reg, &dest_val, 1); +#endif if (ret) return ret; } @@ -106,3 +134,17 @@ int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) return 0; } + +int power_tps65217_init(unsigned char bus) +{ +#ifdef CONFIG_DM_I2C + struct udevice *dev = NULL; + int rc; + + rc = i2c_get_chip_for_busnum(bus, TPS65217_CHIP_PM, 1, &dev); + if (rc) + return rc; + tps65217_dev = dev; +#endif + return 0; +} diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index b50953bdc1..7c95e5e758 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -10,6 +10,7 @@ #include #include +#ifndef CONFIG_DM_I2C int tps65218_reg_read(uchar dest_reg, uchar *dest_val) { uchar read_val; @@ -84,6 +85,76 @@ int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, return 0; } +#else +struct udevice *tps65218_dev __attribute__((section(".data"))) = NULL; + +int tps65218_reg_read(uchar dest_reg, uchar *dest_val) +{ + uchar read_val; + int ret; + + if (!tps65218_dev) + return -ENODEV; + + ret = dm_i2c_read(tps65218_dev, dest_reg, &read_val, 1); + if (ret) + return ret; + + *dest_val = read_val; + + return 0; +} + +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + if (!tps65218_dev) + return -ENODEV; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65218_MASK_ALL_BITS) { + ret = dm_i2c_read(tps65218_dev, dest_reg, &read_val, 1); + if (ret) + return ret; + + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK; + ret = dm_i2c_write(tps65218_dev, TPS65218_PASSWORD, &xor_reg, + 1); + if (ret) + return ret; + } + + ret = dm_i2c_write(tps65218_dev, dest_reg, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65218_PROT_LEVEL_2) { + ret = dm_i2c_write(tps65218_dev, TPS65218_PASSWORD, &xor_reg, + 1); + if (ret) + return ret; + + ret = dm_i2c_write(tps65218_dev, dest_reg, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} +#endif /** * tps65218_voltage_update() - Function to change a voltage level, as this @@ -154,6 +225,7 @@ int tps65218_lock_fseal(void) return 0; } +#ifndef CONFIG_DM_I2C int power_tps65218_init(unsigned char bus) { static const char name[] = "TPS65218_PMIC"; @@ -173,3 +245,16 @@ int power_tps65218_init(unsigned char bus) return 0; } +#else +int power_tps65218_init(unsigned char bus) +{ + struct udevice *dev = NULL; + int rc; + + rc = i2c_get_chip_for_busnum(bus, TPS65218_CHIP_PM, 1, &dev); + if (rc) + return rc; + tps65218_dev = dev; + return 0; +} +#endif diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c index f4d2aa1b7a..4772de11be 100644 --- a/drivers/power/pmic/pmic_tps65910.c +++ b/drivers/power/pmic/pmic_tps65910.c @@ -8,6 +8,47 @@ #include #include +struct udevice *tps65910_dev __attribute__((section(".data"))) = NULL; + +static inline int tps65910_read_reg(int addr, uchar *buf) +{ +#ifndef CONFIG_DM_I2C + return i2c_read(TPS65910_CTRL_I2C_ADDR, addr, 1, buf, 1); +#else + int rc; + + rc = dm_i2c_reg_read(tps65910_dev, addr); + if (rc < 0) + return rc; + *buf = (uchar)rc; + return 0; +#endif +} + +static inline int tps65910_write_reg(int addr, uchar *buf) +{ +#ifndef CONFIG_DM_I2C + return i2c_write(TPS65910_CTRL_I2C_ADDR, addr, 1, buf, 1); +#else + return dm_i2c_reg_write(tps65910_dev, addr, *buf); +#endif +} + +int power_tps65910_init(unsigned char bus) +{ +#ifdef CONFIG_DM_I2C + struct udevice *dev = NULL; + int rc; + + rc = i2c_get_chip_for_busnum(bus, TPS65910_CTRL_I2C_ADDR, 1, &dev); + + if (rc) + return rc; + tps65910_dev = dev; +#endif + return 0; +} + /* * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C * interface. @@ -19,16 +60,14 @@ int tps65910_set_i2c_control(void) uchar buf; /* VDD1/2 voltage selection register access by control i/f */ - ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, - &buf, 1); + ret = tps65910_read_reg(TPS65910_DEVCTRL_REG, &buf); if (ret) return ret; buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; - return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, - &buf, 1); + return tps65910_write_reg(TPS65910_DEVCTRL_REG, &buf); } /* @@ -49,29 +88,29 @@ int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) reg_offset = TPS65910_VDD2_OP_REG; /* Select VDDx OP */ - ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + ret = tps65910_read_reg(reg_offset, &buf); if (ret) return ret; buf &= ~TPS65910_OP_REG_CMD_MASK; - ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + ret = tps65910_write_reg(reg_offset, &buf); if (ret) return ret; /* Configure VDDx OP Voltage */ - ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + ret = tps65910_read_reg(reg_offset, &buf); if (ret) return ret; buf &= ~TPS65910_OP_REG_SEL_MASK; buf |= vddx_op_vol_sel; - ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + ret = tps65910_write_reg(reg_offset, &buf); if (ret) return ret; - ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1); + ret = tps65910_read_reg(reg_offset, &buf); if (ret) return ret; diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index c60dfff5bf..25c339ab12 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -29,7 +29,7 @@ static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) { - debug("write error to device: %p register: %#x!", dev, reg); + debug("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -42,7 +42,7 @@ static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) { - debug("read error from device: %p register: %#x!", dev, reg); + debug("read error from device: %p register: %#x!\n", dev, reg); return ret; } @@ -57,7 +57,7 @@ static int rk8xx_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c index c3be3fed4a..f238396d36 100644 --- a/drivers/power/pmic/rn5t567.c +++ b/drivers/power/pmic/rn5t567.c @@ -24,7 +24,7 @@ static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) { - debug("write error to device: %p register: %#x!", dev, reg); + debug("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -37,7 +37,7 @@ static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) { - debug("read error from device: %p register: %#x!", dev, reg); + debug("read error from device: %p register: %#x!\n", dev, reg); return ret; } diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c index e45d4bc6e1..f2aab6c457 100644 --- a/drivers/power/pmic/s2mps11.c +++ b/drivers/power/pmic/s2mps11.c @@ -30,7 +30,7 @@ static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff, ret = dm_i2c_write(dev, reg, buff, len); if (ret) - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return ret; } @@ -41,7 +41,7 @@ static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return ret; } @@ -53,8 +53,8 @@ static int s2mps11_probe(struct udevice *dev) regulators_node = dev_read_subnode(dev, "voltage-regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, - dev->name); + debug("%s: %s regulators subnode not found!\n", __func__, + dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c index 54e44ce864..b5ddd4930e 100644 --- a/drivers/power/pmic/s5m8767.c +++ b/drivers/power/pmic/s5m8767.c @@ -27,7 +27,7 @@ static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -37,7 +37,7 @@ static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff, static int s5m8767_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -56,7 +56,7 @@ static int s5m8767_bind(struct udevice *dev) node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/pmic/sandbox.c b/drivers/power/pmic/sandbox.c index 64e2f276da..d7870915de 100644 --- a/drivers/power/pmic/sandbox.c +++ b/drivers/power/pmic/sandbox.c @@ -28,7 +28,7 @@ static int sandbox_pmic_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -39,7 +39,7 @@ static int sandbox_pmic_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("read error from device: %p register: %#x!", dev, reg); + pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c index 82351b6613..47af012332 100644 --- a/drivers/power/pmic/stpmu1.c +++ b/drivers/power/pmic/stpmu1.c @@ -61,7 +61,7 @@ static int stpmu1_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - dev_dbg(dev, "regulators subnode not found!"); + dev_dbg(dev, "regulators subnode not found!\n"); return -ENXIO; } dev_dbg(dev, "found regulators subnode\n"); diff --git a/drivers/power/pmic/tps65090.c b/drivers/power/pmic/tps65090.c index 1d3bf00b56..5b1d19f3e0 100644 --- a/drivers/power/pmic/tps65090.c +++ b/drivers/power/pmic/tps65090.c @@ -26,7 +26,7 @@ static int tps65090_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - pr_err("write error to device: %p register: %#x!", dev, reg); + pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -39,8 +39,8 @@ static int tps65090_read(struct udevice *dev, uint reg, uint8_t *buff, int len) ret = dm_i2c_read(dev, reg, buff, len); if (ret) { - pr_err("read error %d from device: %p register: %#x!", ret, dev, - reg); + pr_err("read error %d from device: %p register: %#x!\n", ret, + dev, reg); return -EIO; } @@ -54,7 +54,7 @@ static int tps65090_bind(struct udevice *dev) regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { - debug("%s: %s regulators subnode not found!", __func__, + debug("%s: %s regulators subnode not found!\n", __func__, dev->name); return -ENXIO; } diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 2561a8a856..3ed0dd2264 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -61,6 +61,13 @@ config REGULATOR_PWM This driver is controlled by a device tree node which includes voltage limits. +config SPL_REGULATOR_PWM + bool "Enable Driver for PWM regulators in SPL" + depends on REGULATOR_PWM + help + This config enables implementation of driver-model regulator uclass + features for PWM regulators in SPL. + config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 @@ -69,6 +76,22 @@ config DM_REGULATOR_MAX77686 features for REGULATOR MAX77686. The driver implements get/set api for: value, enable and mode. +config DM_REGULATOR_FAN53555 + bool "Enable Driver Model for REGULATOR FAN53555" + depends on DM_PMIC_FAN53555 + help + This config enables implementation of driver-model regulator + uclass features for the FAN53555 regulator. The FAN53555 is + a (family of) single-output regulators that supports + transitioning between two different output voltages based on + an voltage selection pin. + + The driver implements a get/set api for the voltage of the + 'normal mode' voltage only. Switching to 'suspend mode' + (i.e. the alternate voltage), disabling output via software, + or switching the mode is not supported by this driver (at + this time). + config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index a5f5683d6e..f617ce723a 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -9,7 +9,8 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o -obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c new file mode 100644 index 0000000000..dbd5502377 --- /dev/null +++ b/drivers/power/regulator/fan53555.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) 2018 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct ic_types - definition of fan53555-family devices + * + * @die_id: Identifies the DIE_ID (lower nibble of the ID1 register) + * @die_rev: Identifies the DIE_REV (lower nibble of the ID2 register) + * @vsel_min: starting voltage (step 0) in uV + * @vsel_step: increment of the voltage in uV + * + * The voltage ramp (i.e. minimum voltage and step) is selected from the + * combination of 2 nibbles: DIE_ID and DIE_REV. + * + * See http://www.onsemi.com/pub/Collateral/FAN53555-D.pdf for details. + */ +static const struct { + u8 die_id; + u8 die_rev; + u32 vsel_min; + u32 vsel_step; +} ic_types[] = { + { 0x0, 0x3, 600000, 10000 }, /* Option 00 */ + { 0x0, 0xf, 800000, 10000 }, /* Option 13 */ + { 0x0, 0xc, 600000, 12500 }, /* Option 23 */ + { 0x1, 0x3, 600000, 10000 }, /* Option 01 */ + { 0x3, 0x3, 600000, 10000 }, /* Option 03 */ + { 0x4, 0xf, 603000, 12826 }, /* Option 04 */ + { 0x5, 0x3, 600000, 10000 }, /* Option 05 */ + { 0x8, 0x1, 600000, 10000 }, /* Option 08 */ + { 0x8, 0xf, 600000, 10000 }, /* Option 08 */ + { 0xc, 0xf, 603000, 12826 }, /* Option 09 */ +}; + +/* I2C-accessible byte-sized registers */ +enum { + /* Voltage setting */ + FAN53555_VSEL0 = 0x00, + FAN53555_VSEL1, + /* Control register */ + FAN53555_CONTROL, + /* IC Type */ + FAN53555_ID1, + /* IC mask version */ + FAN53555_ID2, + /* Monitor register */ + FAN53555_MONITOR, +}; + +struct fan53555_platdata { + /* Voltage setting register */ + unsigned int vol_reg; + unsigned int sleep_reg; + +}; + +struct fan53555_priv { + /* IC Vendor */ + unsigned int vendor; + /* IC Type and Rev */ + unsigned int die_id; + unsigned int die_rev; + /* Voltage range and step(linear) */ + unsigned int vsel_min; + unsigned int vsel_step; + /* Voltage slew rate limiting */ + unsigned int slew_rate; + /* Sleep voltage cache */ + unsigned int sleep_vol_cache; +}; + +static int fan53555_regulator_ofdata_to_platdata(struct udevice *dev) +{ + struct fan53555_platdata *dev_pdata = dev_get_platdata(dev); + struct dm_regulator_uclass_platdata *uc_pdata = + dev_get_uclass_platdata(dev); + u32 sleep_vsel; + + /* This is a buck regulator */ + uc_pdata->type = REGULATOR_TYPE_BUCK; + + sleep_vsel = dev_read_u32_default(dev, "fcs,suspend-voltage-selector", + FAN53555_VSEL1); + + /* + * Depending on the device-tree settings, the 'normal mode' + * voltage is either controlled by VSEL0 or VSEL1. + */ + switch (sleep_vsel) { + case FAN53555_VSEL0: + dev_pdata->sleep_reg = FAN53555_VSEL0; + dev_pdata->vol_reg = FAN53555_VSEL1; + break; + case FAN53555_VSEL1: + dev_pdata->sleep_reg = FAN53555_VSEL1; + dev_pdata->vol_reg = FAN53555_VSEL0; + break; + default: + pr_err("%s: invalid vsel id %d\n", dev->name, sleep_vsel); + return -EINVAL; + } + + return 0; +} + +static int fan53555_regulator_get_value(struct udevice *dev) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + int reg; + int voltage; + + /* We only support a single voltage selector (i.e. 'normal' mode). */ + reg = pmic_reg_read(dev->parent, pdata->vol_reg); + if (reg < 0) + return reg; + voltage = priv->vsel_min + (reg & 0x3f) * priv->vsel_step; + + debug("%s: %d uV\n", __func__, voltage); + return voltage; +} + +static int fan53555_regulator_set_value(struct udevice *dev, int uV) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + u8 vol; + + vol = (uV - priv->vsel_min) / priv->vsel_step; + debug("%s: uV=%d; writing volume %d: %02x\n", + __func__, uV, pdata->vol_reg, vol); + + return pmic_clrsetbits(dev, pdata->vol_reg, GENMASK(6, 0), vol); +} + +static int fan53555_voltages_setup(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + int i; + + /* Init voltage range and step */ + for (i = 0; i < ARRAY_SIZE(ic_types); ++i) { + if (ic_types[i].die_id != priv->die_id) + continue; + + if (ic_types[i].die_rev != priv->die_rev) + continue; + + priv->vsel_min = ic_types[i].vsel_min; + priv->vsel_step = ic_types[i].vsel_step; + + return 0; + } + + pr_err("%s: %s: die id %d rev %d not supported!\n", + dev->name, __func__, priv->die_id, priv->die_rev); + return -EINVAL; +} + +enum { + DIE_ID_SHIFT = 0, + DIE_ID_WIDTH = 4, + DIE_REV_SHIFT = 0, + DIE_REV_WIDTH = 4, +}; + +static int fan53555_probe(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + int ID1, ID2; + + debug("%s\n", __func__); + + /* read chip ID1 and ID2 (two registers, starting at ID1) */ + ID1 = pmic_reg_read(dev->parent, FAN53555_ID1); + if (ID1 < 0) + return ID1; + + ID2 = pmic_reg_read(dev->parent, FAN53555_ID2); + if (ID2 < 0) + return ID2; + + /* extract vendor, die_id and die_rev */ + priv->vendor = bitfield_extract(ID1, 5, 3); + priv->die_id = ID1 & GENMASK(3, 0); + priv->die_rev = ID2 & GENMASK(3, 0); + + if (fan53555_voltages_setup(dev) < 0) + return -ENODATA; + + debug("%s: FAN53555 option %d rev %d detected\n", + __func__, priv->die_id, priv->die_rev); + + return 0; +} + +static const struct dm_regulator_ops fan53555_regulator_ops = { + .get_value = fan53555_regulator_get_value, + .set_value = fan53555_regulator_set_value, +}; + +U_BOOT_DRIVER(fan53555_regulator) = { + .name = "fan53555_regulator", + .id = UCLASS_REGULATOR, + .ops = &fan53555_regulator_ops, + .ofdata_to_platdata = fan53555_regulator_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fan53555_platdata), + .priv_auto_alloc_size = sizeof(struct fan53555_priv), + .probe = fan53555_probe, +}; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4da8e43259..39e46279d5 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -106,10 +106,15 @@ int regulator_get_enable(struct udevice *dev) int regulator_set_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; if (!ops || !ops->set_enable) return -ENOSYS; + uc_pdata = dev_get_uclass_platdata(dev); + if (!enable && uc_pdata->always_on) + return 0; + return ops->set_enable(dev, enable); } diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index 52460014bf..42c9001518 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -179,3 +179,42 @@ int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } #endif + +#ifdef CONFIG_DM_I2C +int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_write(dev, reg, val); + if (ret) { + pr_err("writing to twl4030 failed. ret %d\n", ret); + return ret; + } + return 0; +} + +int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_read(dev, reg); + if (ret < 0) { + pr_err("reading from twl4030 failed. ret %d\n", ret); + return ret; + } + *valp = (u8)ret; + return 0; +} +#endif diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index e0cbda1f8c..103960d48d 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -268,3 +268,42 @@ void twl6030_usb_device_settings() value &= ~TWL6030_MISC2_VUSB_IN_PMID; twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_MISC2, value); } + +#ifdef CONFIG_DM_I2C +int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_write(dev, reg, val); + if (ret) { + pr_err("writing to twl6030 failed. ret %d\n", ret); + return ret; + } + return 0; +} + +int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, chip_no, 1, &dev); + if (ret) { + pr_err("unable to get I2C bus. ret %d\n", ret); + return ret; + } + ret = dm_i2c_reg_read(dev, reg); + if (ret < 0) { + pr_err("reading from twl6030 failed. ret %d\n", ret); + return ret; + } + *valp = (u8)ret; + return 0; +} +#endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 7010bbc230..70d02d3f93 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -13,12 +13,15 @@ #include #include #include +#include +#include + #ifdef CONFIG_ARCH_LS1021A #include #endif - -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC -#include +#ifdef CONFIG_ARM64 +#include +#include #endif #define MPC85xx_DEVDISR_QE_DISABLE 0x1 @@ -170,6 +173,33 @@ void qe_put_snum(u8 snum) } } +#ifdef CONFIG_TFABOOT +void qe_init(uint qe_base) +{ + enum boot_src src = get_boot_src(); + + /* Init the QE IMMR base */ + qe_immr = (qe_map_t *)qe_base; + + if (src == BOOT_SOURCE_IFC_NOR) { + /* + * Upload microcode to IRAM for those SOCs + * which do not have ROM in QE. + */ + qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR + + CONFIG_SYS_FSL_IFC_BASE)); + + /* enable the microcode in IRAM */ + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + } + + gd->arch.mp_alloc_base = QE_DATAONLY_BASE; + gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE; + + qe_sdma_init(); + qe_snums_init(); +} +#else void qe_init(uint qe_base) { /* Init the QE IMMR base */ @@ -192,8 +222,53 @@ void qe_init(uint qe_base) qe_snums_init(); } #endif +#endif #ifdef CONFIG_U_QE +#ifdef CONFIG_TFABOOT +void u_qe_init(void) +{ + enum boot_src src = get_boot_src(); + + qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); + + void *addr = (void *)CONFIG_SYS_QE_FW_ADDR; + + if (src == BOOT_SOURCE_IFC_NOR) + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE); + + if (src == BOOT_SOURCE_QSPI_NOR) + addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE); + + if (src == BOOT_SOURCE_SD_MMC) { + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; + + if (mmc_initialize(gd->bd)) { + printf("%s: mmc_initialize() failed\n", __func__); + return; + } + addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + free(addr); + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, + addr); + } + } + if (!u_qe_upload_firmware(addr)) + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); + if (src == BOOT_SOURCE_SD_MMC) + free(addr); +} +#else void u_qe_init(void) { qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); @@ -229,6 +304,7 @@ void u_qe_init(void) #endif } #endif +#endif #ifdef CONFIG_U_QE void u_qe_resume(void) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 54bb4b419f..fbf7d7b20f 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -43,4 +43,15 @@ config MPC83XX_SDRAM the RAM through the use of SPD (Serial Presence Detect) is supported via device tree settings. +config K3_AM654_DDRSS + bool "Enable AM654 DDRSS support" + depends on RAM && SOC_K3_AM6 + help + K3 based AM654 devices has DDR memory subsystem that comprises + Synopys DDR controller, Synopsis DDR phy and wrapper logic to + intergrate these blocks into the device. This DDR subsystem + provides an interface to external SDRAM devices. Enabling this + config add support for the initialization of the external + SDRAM devices connected to DDR subsystem. + source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index cfba57f0fd..976ec66df7 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -11,3 +11,6 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + +obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c index b5f19c983c..3e1dd9e241 100644 --- a/drivers/ram/bmips_ram.c +++ b/drivers/ram/bmips_ram.c @@ -173,5 +173,4 @@ U_BOOT_DRIVER(bmips_ram) = { .probe = bmips_ram_probe, .priv_auto_alloc_size = sizeof(struct bmips_ram_priv), .ops = &bmips_ram_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c new file mode 100644 index 0000000000..7957f678a1 --- /dev/null +++ b/drivers/ram/k3-am654-ddrss.c @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' AM654 DDRSS driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "k3-am654-ddrss.h" + +#define LDELAY 10000 + +/* DDRSS PHY configuration register fixed values */ +#define DDRSS_DDRPHY_RANKIDR_RANK0 0 + +/** + * struct am654_ddrss_desc - Description of ddrss integration. + * @dev: DDRSS device pointer + * @ddrss_ss_cfg: DDRSS wrapper logic region base address + * @ddrss_ctl_cfg: DDRSS controller region base address + * @ddrss_phy_cfg: DDRSS PHY region base address + * @ddrss_clk: DDRSS clock description + * @vtt_supply: VTT Supply regulator + * @ddrss_pwrdmn: DDRSS power domain description + * @params: SDRAM configuration parameters + */ +struct am654_ddrss_desc { + struct udevice *dev; + void __iomem *ddrss_ss_cfg; + void __iomem *ddrss_ctl_cfg; + void __iomem *ddrss_phy_cfg; + struct clk ddrss_clk; + struct udevice *vtt_supply; + struct power_domain ddrcfg_pwrdmn; + struct power_domain ddrdata_pwrdmn; + struct ddrss_params params; +}; + +static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset) +{ + return readl(addr + offset); +} + +static inline void ddrss_writel(void __iomem *addr, unsigned int offset, + u32 data) +{ + debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data); + writel(data, addr + offset); +} + +#define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val) +#define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off) + +static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss) +{ + return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK; +} + +/** + * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete + * + * After detecting the DDR type this function will pause until the + * initialization is complete. Each DDR type has mask of multiple bits. + * The size of the field depends on the DDR Type. If the initialization + * does not complete and error will be returned and will cause the boot to halt. + * + */ +static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss) +{ + u32 val, mask; + + val = am654_ddrss_get_type(ddrss); + + switch (val) { + case DDR_TYPE_LPDDR4: + case DDR_TYPE_DDR4: + mask = DDR4_STAT_MODE_MASK; + break; + case DDR_TYPE_DDR3: + mask = DDR3_STAT_MODE_MASK; + break; + default: + printf("Unsupported DDR type 0x%x\n", val); + return -EINVAL; + } + + if (!wait_on_value(mask, DDR_MODE_NORMAL, + ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY)) + return -ETIMEDOUT; + + return 0; +} + +/** + * am654_ddrss_ctrl_configuration() - Configure Controller specific registers + * @dev: corresponding ddrss device + */ +static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss) +{ + struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing; + struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg; + struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc; + struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc; + struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map; + u32 val; + + debug("%s: DDR controller register configuration started\n", __func__); + + ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr); + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg); + + ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1); + ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2); + + ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6); + ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7); + + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15); + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17); + + ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0); + ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1); + + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0); + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1); + ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2); + + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10); + ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11); + + ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg); + ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap); + + /* Disable refreshes */ + val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3); + val |= 0x01; + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val); + + debug("%s: DDR controller configuration completed\n", __func__); +} + +#define ddrss_phy_writel(off, val) \ + do { \ + ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \ + sdelay(10); /* Delay at least 20 clock cycles */ \ + } while (0) + +#define ddrss_phy_readl(off) \ + ({ \ + u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \ + sdelay(10); /* Delay at least 20 clock cycles */ \ + val; \ + }) + +/** + * am654_ddrss_phy_configuration() - Configure PHY specific registers + * @ddrss: corresponding ddrss device + */ +static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) +{ + struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl; + struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing; + struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; + struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg; + struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq; + + debug("%s: DDR phy register configuration started\n", __func__); + + ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3); + ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6); + + ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3); + ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4); + ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5); + ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6); + + ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr); + ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5); + ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6); + + ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr); + ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0); + ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0); + + ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0); + ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1); + ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2); + ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3); + ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4); + ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5); + ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6); + + ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1); + + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); + ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3); + + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4); + + ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5); + + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0); + + ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0); + ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr); + + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2); + + debug("%s: DDR phy register configuration completed\n", __func__); +} + +static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss, + u32 init_value, u32 sts_mask, + u32 err_mask) +{ + int ret; + + ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK); + + sdelay(5); /* Delay at least 10 clock cycles */ + + if (!wait_on_value(sts_mask, sts_mask, + ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY)) + return -ETIMEDOUT; + + sdelay(16); /* Delay at least 32 clock cycles */ + + ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0); + debug("%s: PGSR0 val = 0x%x\n", __func__, ret); + if (ret & err_mask) + return -EINVAL; + + return 0; +} + +int write_leveling(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Write leveling started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK, + PGSR0_WLERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write leveling timedout\n", + __func__); + else + printf("%s:ERROR: Write leveling failed\n", __func__); + return ret; + } + + debug("%s: Write leveling completed\n", __func__); + return 0; +} + +int read_dqs_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s: Read DQS training started\n", __func__); + + ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK, + PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read DQS timedout\n", __func__); + else + printf("%s:ERROR: Read DQS Gate training failed\n", + __func__); + return ret; + } + + debug("%s: Read DQS training completed\n", __func__); + return 0; +} + +int rest_training(struct am654_ddrss_desc *ddrss) +{ + int ret; + u32 val; + u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd; + + debug("%s: Rest of the training started\n", __func__); + + debug("%s: Write Leveling adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK, + PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s:ERROR: Write Leveling adjustment timedout\n", + __func__); + else + printf("%s: ERROR: Write Leveling adjustment failed\n", + __func__); + return ret; + } + + debug("%s: Read Deskew adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK, + PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read Deskew timedout\n", __func__); + else + printf("%s: ERROR: Read Deskew failed\n", __func__); + return ret; + } + + debug("%s: Write Deskew adjustment\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK, + PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write Deskew timedout\n", __func__); + else + printf("%s: ERROR: Write Deskew failed\n", __func__); + return ret; + } + + debug("%s: Read Eye training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK, + PGSR0_REDONE_MASK, PGSR0_REERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Read Eye training timedout\n", + __func__); + else + printf("%s: ERROR: Read Eye training failed\n", + __func__); + return ret; + } + + debug("%s: Write Eye training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK, + PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: Write Eye training timedout\n", + __func__); + else + printf("%s: ERROR: Write Eye training failed\n", + __func__); + return ret; + } + + debug("%s: VREF training\n", __func__); + ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK, + PGSR0_VERR_MASK); + if (ret) { + if (ret == -ETIMEDOUT) + printf("%s: ERROR: VREF training timedout\n", __func__); + else + printf("%s: ERROR: VREF training failed\n", __func__); + return ret; + } + + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); + dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2; + dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2; + dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2; + dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2; + + rddly = dgsl0; + if (dgsl1 < rddly) + rddly = dgsl1; + if (dgsl2 < rddly) + rddly = dgsl2; + if (dgsl3 < rddly) + rddly = dgsl3; + + rddly += 5; + + /* Update rddly based on dgsl values */ + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val); + + val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000); + val |= (rddly << 20); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val); + + /* + * Add system latency derived from training back into rd2wr and wr2rd + * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2 + * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2 + */ + + /* Select rank 0 */ + ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000); + + dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F); + dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F); + dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F); + dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F); + + /* Find maximum value across all bytes */ + rd2wr_wr2rd = dgsl0; + if (dgsl1 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl1; + if (dgsl2 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl2; + if (dgsl3 > rd2wr_wr2rd) + rd2wr_wr2rd = dgsl3; + + rd2wr_wr2rd >>= 1; + + /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */ + /* Clear VSWCTL.sw_done */ + ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, + ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1); + /* Adjust rd2wr */ + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, + ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + + (rd2wr_wr2rd << 8)); + /* Adjust wr2rd */ + ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, + ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) + + rd2wr_wr2rd); + /* Set VSWCTL.sw_done */ + ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL, + ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1); + /* Wait until settings are applied */ + while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) { + /* Do nothing */ + }; + + debug("%s: Rest of the training completed\n", __func__); + return 0; +} + +/** + * am654_ddrss_init() - Initialization sequence for enabling the SDRAM + * device attached to ddrss. + * @dev: corresponding ddrss device + * + * Does all the initialization sequence that is required to get attached + * ddr in a working state. After this point, ddr should be accessible. + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF); + + am654_ddrss_ctrl_configuration(ddrss); + + /* Release the reset to the controller */ + clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG, + SS_CTL_REG_CTL_ARST_MASK); + + am654_ddrss_phy_configuration(ddrss); + + ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0); + if (ret) { + dev_err(ddrss->dev, "PHY initialization failed %d\n", ret); + return ret; + } + + ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT, + PGSR0_DRAM_INIT_MASK, 0); + if (ret) { + dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret); + return ret; + } + + ret = am654_ddrss_dram_wait_for_init_complt(ddrss); + if (ret) { + printf("%s: ERROR: DRAM Wait for init complete timedout\n", + __func__); + return ret; + } + + ret = write_leveling(ddrss); + if (ret) + return ret; + + ret = read_dqs_training(ddrss); + if (ret) + return ret; + + ret = rest_training(ddrss); + if (ret) + return ret; + + /* Enabling refreshes after training is done */ + ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, + ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1); + + /* Disable PUBMODE after training is done */ + ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, + ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40); + + return 0; +} + +/** + * am654_ddrss_power_on() - Enable power and clocks for ddrss + * @dev: corresponding ddrss device + * + * Tries to enable all the corresponding clocks to the ddrss and sets it + * to the right frequency and then power on the ddrss. + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss) +{ + int ret; + + debug("%s(ddrss=%p)\n", __func__, ddrss); + + ret = clk_enable(&ddrss->ddrss_clk); + if (ret) { + dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrcfg_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = power_domain_on(&ddrss->ddrdata_pwrdmn); + if (ret) { + dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret); + return ret; + } + + /* VTT enable */ +#if CONFIG_IS_ENABLED(DM_REGULATOR) + device_get_supply_regulator(ddrss->dev, "vtt-supply", + &ddrss->vtt_supply); + ret = regulator_set_value(ddrss->vtt_supply, 3300000); + if (ret) + return ret; + debug("VTT regulator enabled\n"); +#endif + + return 0; +} + +/** + * am654_ddrss_ofdata_to_priv() - generate private data from device tree + * @dev: corresponding ddrss device + * + * Return: 0 if all went ok, else corresponding error message. + */ +static int am654_ddrss_ofdata_to_priv(struct udevice *dev) +{ + struct am654_ddrss_desc *ddrss = dev_get_priv(dev); + phys_addr_t reg; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk); + if (ret) { + dev_err(dev, "clk_get failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1); + if (ret) { + dev_err(dev, "power_domain_get() failed: %d\n", ret); + return ret; + } + + reg = devfdt_get_addr_name(dev, "ss"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for DDRSS wrapper logic\n"); + return -EINVAL; + } + ddrss->ddrss_ss_cfg = (void *)reg; + + reg = devfdt_get_addr_name(dev, "ctl"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for Controller region\n"); + return -EINVAL; + } + ddrss->ddrss_ctl_cfg = (void *)reg; + + reg = devfdt_get_addr_name(dev, "phy"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for PHY region\n"); + return -EINVAL; + } + ddrss->ddrss_phy_cfg = (void *)reg; + + ret = dev_read_u32_array(dev, "ti,ctl-reg", + (u32 *)&ddrss->params.ctl_reg, + sizeof(ddrss->params.ctl_reg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-reg params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-crc", + (u32 *)&ddrss->params.ctl_crc, + sizeof(ddrss->params.ctl_crc) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-crc params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-ecc", + (u32 *)&ddrss->params.ctl_ecc, + sizeof(ddrss->params.ctl_ecc) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-ecc params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-map", + (u32 *)&ddrss->params.ctl_map, + sizeof(ddrss->params.ctl_map) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-map params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-pwr", + (u32 *)&ddrss->params.ctl_pwr, + sizeof(ddrss->params.ctl_pwr) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-pwr params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,ctl-timing", + (u32 *)&ddrss->params.ctl_timing, + sizeof(ddrss->params.ctl_timing) / + sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ctl-timing params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-cfg", + (u32 *)&ddrss->params.phy_cfg, + sizeof(ddrss->params.phy_cfg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-cfg params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-ctl", + (u32 *)&ddrss->params.phy_ctrl, + sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-ctl params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-ioctl", + (u32 *)&ddrss->params.phy_ioctl, + sizeof(ddrss->params.phy_ioctl) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-ioctl params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-timing", + (u32 *)&ddrss->params.phy_timing, + sizeof(ddrss->params.phy_timing) / + sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-timing params\n"); + return ret; + } + + ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq, + sizeof(ddrss->params.phy_zq) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,phy-zq params\n"); + return ret; + } + + return ret; +} + +/** + * am654_ddrss_probe() - Basic probe + * @dev: corresponding ddrss device + * + * Return: 0 if all went ok, else corresponding error message + */ +static int am654_ddrss_probe(struct udevice *dev) +{ + struct am654_ddrss_desc *ddrss = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = am654_ddrss_ofdata_to_priv(dev); + if (ret) + return ret; + + ddrss->dev = dev; + ret = am654_ddrss_power_on(ddrss); + if (ret) + return ret; + + ret = am654_ddrss_init(ddrss); + + return ret; +} + +static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info) +{ + return 0; +} + +static struct ram_ops am654_ddrss_ops = { + .get_info = am654_ddrss_get_info, +}; + +static const struct udevice_id am654_ddrss_ids[] = { + { .compatible = "ti,am654-ddrss" }, + { } +}; + +U_BOOT_DRIVER(am654_ddrss) = { + .name = "am654_ddrss", + .id = UCLASS_RAM, + .of_match = am654_ddrss_ids, + .ops = &am654_ddrss_ops, + .probe = am654_ddrss_probe, + .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc), +}; diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h new file mode 100644 index 0000000000..78d73cd9fc --- /dev/null +++ b/drivers/ram/k3-am654-ddrss.h @@ -0,0 +1,1189 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AM654: DDRSS Register definitions and structures. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla + * + */ + +#ifndef __K3_AM654_DDRSS_H +#define __K3_AM654_DDRSS_H + +/* DDRSS subsystem wrapper logic registers */ +#define DDRSS_SS_ID_REV_REG 0x00000000 +#define DDRSS_SS_CTL_REG 0x00000004 +#define DDRSS_V2H_CTL_REG 0x00000020 + +#define SS_CTL_REG_CTL_ARST_SHIFT 0x0 +#define SS_CTL_REG_CTL_ARST_MASK BIT(SS_CTL_REG_CTL_ARST_SHIFT) + +/* DDRSS controller configuration registers */ +#define DDRSS_DDRCTL_MSTR 0x00000000 +#define DDRSS_DDRCTL_STAT 0x00000004 +#define DDRSS_DDRCTL_MRCTRL0 0x00000010 +#define DDRSS_DDRCTL_MRCTRL1 0x00000014 +#define DDRSS_DDRCTL_MRSTAT 0x00000018 +#define DDRSS_DDRCTL_MRCTRL2 0x0000001C +#define DDRSS_DDRCTL_DERATEEN 0x00000020 +#define DDRSS_DDRCTL_DERATEINT 0x00000024 +#define DDRSS_DDRCTL_MSTR2 0x00000028 +#define DDRSS_DDRCTL_PWRCTL 0x00000030 +#define DDRSS_DDRCTL_PWRTMG 0x00000034 +#define DDRSS_DDRCTL_HWLPCTL 0x00000038 +#define DDRSS_DDRCTL_RFSHCTL0 0x00000050 +#define DDRSS_DDRCTL_RFSHCTL1 0x00000054 +#define DDRSS_DDRCTL_RFSHCTL2 0x00000058 +#define DDRSS_DDRCTL_RFSHCTL3 0x00000060 +#define DDRSS_DDRCTL_RFSHTMG 0x00000064 +#define DDRSS_DDRCTL_ECCCFG0 0x00000070 +#define DDRSS_DDRCTL_ECCCFG1 0x00000074 +#define DDRSS_DDRCTL_ECCSTAT 0x00000078 +#define DDRSS_DDRCTL_ECCCLR 0x0000007C +#define DDRSS_DDRCTL_ECCERRCNT 0x00000080 +#define DDRSS_DDRCTL_ECCCADDR0 0x00000084 +#define DDRSS_DDRCTL_ECCCADDR1 0x00000088 +#define DDRSS_DDRCTL_ECCCSYN0 0x0000008C +#define DDRSS_DDRCTL_ECCCSYN2 0x00000094 +#define DDRSS_DDRCTL_ECCBITMASK0 0x00000098 +#define DDRSS_DDRCTL_ECCBITMASK2 0x000000A0 +#define DDRSS_DDRCTL_ECCUADDR0 0x000000A4 +#define DDRSS_DDRCTL_ECCUADDR1 0x000000A8 +#define DDRSS_DDRCTL_ECCUSYN0 0x000000AC +#define DDRSS_DDRCTL_ECCUSYN2 0x000000B4 +#define DDRSS_DDRCTL_ECCPOISONADDR0 0x000000B8 +#define DDRSS_DDRCTL_ECCPOISONADDR1 0x000000BC +#define DDRSS_DDRCTL_CRCPARCTL0 0x000000C0 +#define DDRSS_DDRCTL_CRCPARCTL1 0x000000C4 +#define DDRSS_DDRCTL_CRCPARCTL2 0x000000C8 +#define DDRSS_DDRCTL_CRCPARSTAT 0x000000CC +#define DDRSS_DDRCTL_INIT0 0x000000D0 +#define DDRSS_DDRCTL_INIT1 0x000000D4 +#define DDRSS_DDRCTL_INIT2 0x000000D8 +#define DDRSS_DDRCTL_INIT3 0x000000DC +#define DDRSS_DDRCTL_INIT4 0x000000E0 +#define DDRSS_DDRCTL_INIT5 0x000000E4 +#define DDRSS_DDRCTL_INIT6 0x000000E8 +#define DDRSS_DDRCTL_INIT7 0x000000EC +#define DDRSS_DDRCTL_DIMMCTL 0x000000F0 +#define DDRSS_DDRCTL_RANKCTL 0x000000F4 +#define DDRSS_DDRCTL_DRAMTMG0 0x00000100 +#define DDRSS_DDRCTL_DRAMTMG1 0x00000104 +#define DDRSS_DDRCTL_DRAMTMG2 0x00000108 +#define DDRSS_DDRCTL_DRAMTMG3 0x0000010C +#define DDRSS_DDRCTL_DRAMTMG4 0x00000110 +#define DDRSS_DDRCTL_DRAMTMG5 0x00000114 +#define DDRSS_DDRCTL_DRAMTMG6 0x00000118 +#define DDRSS_DDRCTL_DRAMTMG7 0x0000011C +#define DDRSS_DDRCTL_DRAMTMG8 0x00000120 +#define DDRSS_DDRCTL_DRAMTMG9 0x00000124 +#define DDRSS_DDRCTL_DRAMTMG10 0x00000128 +#define DDRSS_DDRCTL_DRAMTMG11 0x0000012C +#define DDRSS_DDRCTL_DRAMTMG12 0x00000130 +#define DDRSS_DDRCTL_DRAMTMG13 0x00000134 +#define DDRSS_DDRCTL_DRAMTMG14 0x00000138 +#define DDRSS_DDRCTL_DRAMTMG15 0x0000013C +#define DDRSS_DDRCTL_DRAMTMG17 0x00000144 +#define DDRSS_DDRCTL_ZQCTL0 0x00000180 +#define DDRSS_DDRCTL_ZQCTL1 0x00000184 +#define DDRSS_DDRCTL_ZQCTL2 0x00000188 +#define DDRSS_DDRCTL_ZQSTAT 0x0000018C +#define DDRSS_DDRCTL_DFITMG0 0x00000190 +#define DDRSS_DDRCTL_DFITMG1 0x00000194 +#define DDRSS_DDRCTL_DFILPCFG0 0x00000198 +#define DDRSS_DDRCTL_DFILPCFG1 0x0000019C +#define DDRSS_DDRCTL_DFIUPD0 0x000001A0 +#define DDRSS_DDRCTL_DFIUPD1 0x000001A4 +#define DDRSS_DDRCTL_DFIUPD2 0x000001A8 +#define DDRSS_DDRCTL_DFIMISC 0x000001B0 +#define DDRSS_DDRCTL_DFITMG2 0x000001B4 +#define DDRSS_DDRCTL_DFITMG3 0x000001B8 +#define DDRSS_DDRCTL_DFISTAT 0x000001BC +#define DDRSS_DDRCTL_DBICTL 0x000001C0 +#define DDRSS_DDRCTL_DFIPHYMSTR 0x000001C4 +#define DDRSS_DDRCTL_ADDRMAP0 0x00000200 +#define DDRSS_DDRCTL_ADDRMAP1 0x00000204 +#define DDRSS_DDRCTL_ADDRMAP2 0x00000208 +#define DDRSS_DDRCTL_ADDRMAP3 0x0000020C +#define DDRSS_DDRCTL_ADDRMAP4 0x00000210 +#define DDRSS_DDRCTL_ADDRMAP5 0x00000214 +#define DDRSS_DDRCTL_ADDRMAP6 0x00000218 +#define DDRSS_DDRCTL_ADDRMAP7 0x0000021C +#define DDRSS_DDRCTL_ADDRMAP8 0x00000220 +#define DDRSS_DDRCTL_ADDRMAP9 0x00000224 +#define DDRSS_DDRCTL_ADDRMAP10 0x00000228 +#define DDRSS_DDRCTL_ADDRMAP11 0x0000022C +#define DDRSS_DDRCTL_ODTCFG 0x00000240 +#define DDRSS_DDRCTL_ODTMAP 0x00000244 +#define DDRSS_DDRCTL_SCHED 0x00000250 +#define DDRSS_DDRCTL_SCHED1 0x00000254 +#define DDRSS_DDRCTL_PERFHPR1 0x0000025C +#define DDRSS_DDRCTL_PERFLPR1 0x00000264 +#define DDRSS_DDRCTL_PERFWR1 0x0000026C +#define DDRSS_DDRCTL_DQMAP0 0x00000280 +#define DDRSS_DDRCTL_DQMAP1 0x00000284 +#define DDRSS_DDRCTL_DQMAP4 0x00000290 +#define DDRSS_DDRCTL_DQMAP5 0x00000294 +#define DDRSS_DDRCTL_DBG0 0x00000300 +#define DDRSS_DDRCTL_DBG1 0x00000304 +#define DDRSS_DDRCTL_DBGCAM 0x00000308 +#define DDRSS_DDRCTL_DBGCMD 0x0000030C +#define DDRSS_DDRCTL_DBGSTAT 0x00000310 +#define DDRSS_DDRCTL_SWCTL 0x00000320 +#define DDRSS_DDRCTL_SWSTAT 0x00000324 +#define DDRSS_DDRCTL_ADVECCINDEX 0x00000374 +#define DDRSS_DDRCTL_ECCPOISONPAT0 0x0000037C +#define DDRSS_DDRCTL_ECCPOISONPAT2 0x00000384 +#define DDRSS_DDRCTL_CAPARPOISONCTL 0x000003A0 +#define DDRSS_DDRCTL_CAPARPOISONSTAT 0x000003A4 +#define DDRSS_DDRCTL_DERATEEN_SHDW 0x00002020 +#define DDRSS_DDRCTL_DERATEINT_SHDW 0x00002024 +#define DDRSS_DDRCTL_RFSHCTL0_SHDW 0x00002050 +#define DDRSS_DDRCTL_RFSHTMG_SHDW 0x00002064 +#define DDRSS_DDRCTL_INIT3_SHDW 0x000020DC +#define DDRSS_DDRCTL_INIT4_SHDW 0x000020E0 +#define DDRSS_DDRCTL_INIT6_SHDW 0x000020E8 +#define DDRSS_DDRCTL_INIT7_SHDW 0x000020EC +#define DDRSS_DDRCTL_DRAMTMG0_SHDW 0x00002100 +#define DDRSS_DDRCTL_DRAMTMG1_SHDW 0x00002104 +#define DDRSS_DDRCTL_DRAMTMG2_SHDW 0x00002108 +#define DDRSS_DDRCTL_DRAMTMG3_SHDW 0x0000210C +#define DDRSS_DDRCTL_DRAMTMG4_SHDW 0x00002110 +#define DDRSS_DDRCTL_DRAMTMG5_SHDW 0x00002114 +#define DDRSS_DDRCTL_DRAMTMG6_SHDW 0x00002118 +#define DDRSS_DDRCTL_DRAMTMG7_SHDW 0x0000211C +#define DDRSS_DDRCTL_DRAMTMG8_SHDW 0x00002120 +#define DDRSS_DDRCTL_DRAMTMG9_SHDW 0x00002124 +#define DDRSS_DDRCTL_DRAMTMG10_SHDW 0x00002128 +#define DDRSS_DDRCTL_DRAMTMG11_SHDW 0x0000212C +#define DDRSS_DDRCTL_DRAMTMG12_SHDW 0x00002130 +#define DDRSS_DDRCTL_DRAMTMG13_SHDW 0x00002134 +#define DDRSS_DDRCTL_DRAMTMG14_SHDW 0x00002138 +#define DDRSS_DDRCTL_DRAMTMG15_SHDW 0x0000213C +#define DDRSS_DDRCTL_ZQCTL0_SHDW 0x00002180 +#define DDRSS_DDRCTL_DFITMG0_SHDW 0x00002190 +#define DDRSS_DDRCTL_DFITMG1_SHDW 0x00002194 +#define DDRSS_DDRCTL_DFITMG2_SHDW 0x000021B4 +#define DDRSS_DDRCTL_DFITMG3_SHDW 0x000021B8 +#define DDRSS_DDRCTL_ODTCFG_SHDW 0x00002240 + +#define MSTR_DDR_TYPE_MASK GENMASK(5, 0) +#define DDR_TYPE_LPDDR4 0x20 +#define DDR_TYPE_DDR4 0x10 +#define DDR_TYPE_DDR3 0x1 + +#define DDR3_STAT_MODE_MASK GENMASK(1, 0) +#define DDR4_STAT_MODE_MASK GENMASK(2, 0) +#define DDR_MODE_NORMAL 0x1 + +/* DDRSS PHY configuration registers */ +#define DDRSS_DDRPHY_RIDR 0x00000000 +#define DDRSS_DDRPHY_PIR 0x00000004 +#define DDRSS_DDRPHY_PGCR0 0x00000010 +#define DDRSS_DDRPHY_PGCR1 0x00000014 +#define DDRSS_DDRPHY_PGCR2 0x00000018 +#define DDRSS_DDRPHY_PGCR3 0x0000001C +#define DDRSS_DDRPHY_PGCR4 0x00000020 +#define DDRSS_DDRPHY_PGCR5 0x00000024 +#define DDRSS_DDRPHY_PGCR6 0x00000028 +#define DDRSS_DDRPHY_PGCR7 0x0000002C +#define DDRSS_DDRPHY_PGSR0 0x00000030 +#define DDRSS_DDRPHY_PGSR1 0x00000034 +#define DDRSS_DDRPHY_PGSR2 0x00000038 +#define DDRSS_DDRPHY_PTR0 0x00000040 +#define DDRSS_DDRPHY_PTR1 0x00000044 +#define DDRSS_DDRPHY_PTR2 0x00000048 +#define DDRSS_DDRPHY_PTR3 0x0000004C +#define DDRSS_DDRPHY_PTR4 0x00000050 +#define DDRSS_DDRPHY_PTR5 0x00000054 +#define DDRSS_DDRPHY_PTR6 0x00000058 +#define DDRSS_DDRPHY_PLLCR0 0x00000068 +#define DDRSS_DDRPHY_PLLCR1 0x0000006C +#define DDRSS_DDRPHY_PLLCR2 0x00000070 +#define DDRSS_DDRPHY_PLLCR3 0x00000074 +#define DDRSS_DDRPHY_PLLCR4 0x00000078 +#define DDRSS_DDRPHY_PLLCR5 0x0000007C +#define DDRSS_DDRPHY_DXCCR 0x00000088 +#define DDRSS_DDRPHY_DSGCR 0x00000090 +#define DDRSS_DDRPHY_ODTCR 0x00000098 +#define DDRSS_DDRPHY_AACR 0x000000A0 +#define DDRSS_DDRPHY_GPR0 0x000000C0 +#define DDRSS_DDRPHY_GPR1 0x000000C4 +#define DDRSS_DDRPHY_DCR 0x00000100 +#define DDRSS_DDRPHY_DTPR0 0x00000110 +#define DDRSS_DDRPHY_DTPR1 0x00000114 +#define DDRSS_DDRPHY_DTPR2 0x00000118 +#define DDRSS_DDRPHY_DTPR3 0x0000011C +#define DDRSS_DDRPHY_DTPR4 0x00000120 +#define DDRSS_DDRPHY_DTPR5 0x00000124 +#define DDRSS_DDRPHY_DTPR6 0x00000128 +#define DDRSS_DDRPHY_RDIMMGCR0 0x00000140 +#define DDRSS_DDRPHY_RDIMMGCR1 0x00000144 +#define DDRSS_DDRPHY_RDIMMGCR2 0x00000148 +#define DDRSS_DDRPHY_RDIMMCR0 0x00000150 +#define DDRSS_DDRPHY_RDIMMCR1 0x00000154 +#define DDRSS_DDRPHY_RDIMMCR2 0x00000158 +#define DDRSS_DDRPHY_RDIMMCR3 0x0000015C +#define DDRSS_DDRPHY_RDIMMCR4 0x00000160 +#define DDRSS_DDRPHY_SCHCR0 0x00000168 +#define DDRSS_DDRPHY_SCHCR1 0x0000016C +#define DDRSS_DDRPHY_MR0 0x00000180 +#define DDRSS_DDRPHY_MR1 0x00000184 +#define DDRSS_DDRPHY_MR2 0x00000188 +#define DDRSS_DDRPHY_MR3 0x0000018C +#define DDRSS_DDRPHY_MR4 0x00000190 +#define DDRSS_DDRPHY_MR5 0x00000194 +#define DDRSS_DDRPHY_MR6 0x00000198 +#define DDRSS_DDRPHY_MR7 0x0000019C +#define DDRSS_DDRPHY_MR11 0x000001AC +#define DDRSS_DDRPHY_MR12 0x000001B0 +#define DDRSS_DDRPHY_MR13 0x000001B4 +#define DDRSS_DDRPHY_MR14 0x000001B8 +#define DDRSS_DDRPHY_MR22 0x000001D8 +#define DDRSS_DDRPHY_DTCR0 0x00000200 +#define DDRSS_DDRPHY_DTCR1 0x00000204 +#define DDRSS_DDRPHY_DTAR0 0x00000208 +#define DDRSS_DDRPHY_DTAR1 0x0000020C +#define DDRSS_DDRPHY_DTAR2 0x00000210 +#define DDRSS_DDRPHY_DTDR0 0x00000218 +#define DDRSS_DDRPHY_DTDR1 0x0000021C +#define DDRSS_DDRPHY_DTEDR0 0x00000230 +#define DDRSS_DDRPHY_DTEDR1 0x00000234 +#define DDRSS_DDRPHY_DTEDR2 0x00000238 +#define DDRSS_DDRPHY_VTDR 0x0000023C +#define DDRSS_DDRPHY_CATR0 0x00000240 +#define DDRSS_DDRPHY_CATR1 0x00000244 +#define DDRSS_DDRPHY_PGCR8 0x00000248 +#define DDRSS_DDRPHY_DQSDR0 0x00000250 +#define DDRSS_DDRPHY_DQSDR1 0x00000254 +#define DDRSS_DDRPHY_DQSDR2 0x00000258 +#define DDRSS_DDRPHY_DCUAR 0x00000300 +#define DDRSS_DDRPHY_DCUDR 0x00000304 +#define DDRSS_DDRPHY_DCURR 0x00000308 +#define DDRSS_DDRPHY_DCULR 0x0000030C +#define DDRSS_DDRPHY_DCUGCR 0x00000310 +#define DDRSS_DDRPHY_DCUTPR 0x00000314 +#define DDRSS_DDRPHY_DCUSR0 0x00000318 +#define DDRSS_DDRPHY_DCUSR1 0x0000031C +#define DDRSS_DDRPHY_BISTRR 0x00000400 +#define DDRSS_DDRPHY_BISTWCR 0x00000404 +#define DDRSS_DDRPHY_BISTMSKR0 0x00000408 +#define DDRSS_DDRPHY_BISTMSKR1 0x0000040C +#define DDRSS_DDRPHY_BISTMSKR2 0x00000410 +#define DDRSS_DDRPHY_BISTLSR 0x00000414 +#define DDRSS_DDRPHY_BISTAR0 0x00000418 +#define DDRSS_DDRPHY_BISTAR1 0x0000041C +#define DDRSS_DDRPHY_BISTAR2 0x00000420 +#define DDRSS_DDRPHY_BISTAR3 0x00000424 +#define DDRSS_DDRPHY_BISTAR4 0x00000428 +#define DDRSS_DDRPHY_BISTUDPR 0x0000042C +#define DDRSS_DDRPHY_BISTGSR 0x00000430 +#define DDRSS_DDRPHY_BISTWER0 0x00000434 +#define DDRSS_DDRPHY_BISTWER1 0x00000438 +#define DDRSS_DDRPHY_BISTBER0 0x0000043C +#define DDRSS_DDRPHY_BISTBER1 0x00000440 +#define DDRSS_DDRPHY_BISTBER2 0x00000444 +#define DDRSS_DDRPHY_BISTBER3 0x00000448 +#define DDRSS_DDRPHY_BISTBER4 0x0000044C +#define DDRSS_DDRPHY_BISTWCSR 0x00000450 +#define DDRSS_DDRPHY_BISTFWR0 0x00000454 +#define DDRSS_DDRPHY_BISTFWR1 0x00000458 +#define DDRSS_DDRPHY_BISTFWR2 0x0000045C +#define DDRSS_DDRPHY_BISTBER5 0x00000460 +#define DDRSS_DDRPHY_RANKIDR 0x000004DC +#define DDRSS_DDRPHY_RIOCR0 0x000004E0 +#define DDRSS_DDRPHY_RIOCR1 0x000004E4 +#define DDRSS_DDRPHY_RIOCR2 0x000004E8 +#define DDRSS_DDRPHY_RIOCR3 0x000004EC +#define DDRSS_DDRPHY_RIOCR4 0x000004F0 +#define DDRSS_DDRPHY_RIOCR5 0x000004F4 +#define DDRSS_DDRPHY_ACIOCR0 0x00000500 +#define DDRSS_DDRPHY_ACIOCR1 0x00000504 +#define DDRSS_DDRPHY_ACIOCR2 0x00000508 +#define DDRSS_DDRPHY_ACIOCR3 0x0000050C +#define DDRSS_DDRPHY_ACIOCR4 0x00000510 +#define DDRSS_DDRPHY_ACIOCR5 0x00000514 +#define DDRSS_DDRPHY_IOVCR0 0x00000520 +#define DDRSS_DDRPHY_IOVCR1 0x00000524 +#define DDRSS_DDRPHY_VTCR0 0x00000528 +#define DDRSS_DDRPHY_VTCR1 0x0000052C +#define DDRSS_DDRPHY_ACBDLR0 0x00000540 +#define DDRSS_DDRPHY_ACBDLR1 0x00000544 +#define DDRSS_DDRPHY_ACBDLR2 0x00000548 +#define DDRSS_DDRPHY_ACBDLR3 0x0000054C +#define DDRSS_DDRPHY_ACBDLR4 0x00000550 +#define DDRSS_DDRPHY_ACBDLR5 0x00000554 +#define DDRSS_DDRPHY_ACBDLR6 0x00000558 +#define DDRSS_DDRPHY_ACBDLR7 0x0000055C +#define DDRSS_DDRPHY_ACBDLR8 0x00000560 +#define DDRSS_DDRPHY_ACBDLR9 0x00000564 +#define DDRSS_DDRPHY_ACBDLR10 0x00000568 +#define DDRSS_DDRPHY_ACBDLR11 0x0000056C +#define DDRSS_DDRPHY_ACBDLR12 0x00000570 +#define DDRSS_DDRPHY_ACBDLR13 0x00000574 +#define DDRSS_DDRPHY_ACBDLR14 0x00000578 +#define DDRSS_DDRPHY_ACBDLR15 0x0000057C +#define DDRSS_DDRPHY_ACBDLR16 0x00000580 +#define DDRSS_DDRPHY_ACLCDLR 0x00000584 +#define DDRSS_DDRPHY_ACMDLR0 0x000005A0 +#define DDRSS_DDRPHY_ACMDLR1 0x000005A4 +#define DDRSS_DDRPHY_ZQCR 0x00000680 +#define DDRSS_DDRPHY_ZQ0PR0 0x00000684 +#define DDRSS_DDRPHY_ZQ0PR1 0x00000688 +#define DDRSS_DDRPHY_ZQ0DR0 0x0000068C +#define DDRSS_DDRPHY_ZQ0DR1 0x00000690 +#define DDRSS_DDRPHY_ZQ0OR0 0x00000694 +#define DDRSS_DDRPHY_ZQ0OR1 0x00000698 +#define DDRSS_DDRPHY_ZQ0SR 0x0000069C +#define DDRSS_DDRPHY_ZQ1PR0 0x000006A4 +#define DDRSS_DDRPHY_ZQ1PR1 0x000006A8 +#define DDRSS_DDRPHY_ZQ1DR0 0x000006AC +#define DDRSS_DDRPHY_ZQ1DR1 0x000006B0 +#define DDRSS_DDRPHY_ZQ1OR0 0x000006B4 +#define DDRSS_DDRPHY_ZQ1OR1 0x000006B8 +#define DDRSS_DDRPHY_ZQ1SR 0x000006BC +#define DDRSS_DDRPHY_ZQ2PR0 0x000006C4 +#define DDRSS_DDRPHY_ZQ2PR1 0x000006C8 +#define DDRSS_DDRPHY_ZQ2DR0 0x000006CC +#define DDRSS_DDRPHY_ZQ2DR1 0x000006D0 +#define DDRSS_DDRPHY_ZQ2OR0 0x000006D4 +#define DDRSS_DDRPHY_ZQ2OR1 0x000006D8 +#define DDRSS_DDRPHY_ZQ2SR 0x000006DC +#define DDRSS_DDRPHY_ZQ3PR0 0x000006E4 +#define DDRSS_DDRPHY_ZQ3PR1 0x000006E8 +#define DDRSS_DDRPHY_ZQ3DR0 0x000006EC +#define DDRSS_DDRPHY_ZQ3DR1 0x000006F0 +#define DDRSS_DDRPHY_ZQ3OR0 0x000006F4 +#define DDRSS_DDRPHY_ZQ3OR1 0x000006F8 +#define DDRSS_DDRPHY_ZQ3SR 0x000006FC +#define DDRSS_DDRPHY_DX0GCR0 0x00000700 +#define DDRSS_DDRPHY_DX0GCR1 0x00000704 +#define DDRSS_DDRPHY_DX0GCR2 0x00000708 +#define DDRSS_DDRPHY_DX0GCR3 0x0000070C +#define DDRSS_DDRPHY_DX0GCR4 0x00000710 +#define DDRSS_DDRPHY_DX0GCR5 0x00000714 +#define DDRSS_DDRPHY_DX0GCR6 0x00000718 +#define DDRSS_DDRPHY_DX0GCR7 0x0000071C +#define DDRSS_DDRPHY_DX0GCR8 0x00000720 +#define DDRSS_DDRPHY_DX0GCR9 0x00000724 +#define DDRSS_DDRPHY_DX0DQMAP0 0x00000728 +#define DDRSS_DDRPHY_DX0DQMAP1 0x0000072C +#define DDRSS_DDRPHY_DX0BDLR0 0x00000740 +#define DDRSS_DDRPHY_DX0BDLR1 0x00000744 +#define DDRSS_DDRPHY_DX0BDLR2 0x00000748 +#define DDRSS_DDRPHY_DX0BDLR3 0x00000750 +#define DDRSS_DDRPHY_DX0BDLR4 0x00000754 +#define DDRSS_DDRPHY_DX0BDLR5 0x00000758 +#define DDRSS_DDRPHY_DX0BDLR6 0x00000760 +#define DDRSS_DDRPHY_DX0BDLR7 0x00000764 +#define DDRSS_DDRPHY_DX0BDLR8 0x00000768 +#define DDRSS_DDRPHY_DX0BDLR9 0x0000076C +#define DDRSS_DDRPHY_DX0LCDLR0 0x00000780 +#define DDRSS_DDRPHY_DX0LCDLR1 0x00000784 +#define DDRSS_DDRPHY_DX0LCDLR2 0x00000788 +#define DDRSS_DDRPHY_DX0LCDLR3 0x0000078C +#define DDRSS_DDRPHY_DX0LCDLR4 0x00000790 +#define DDRSS_DDRPHY_DX0LCDLR5 0x00000794 +#define DDRSS_DDRPHY_DX0MDLR0 0x000007A0 +#define DDRSS_DDRPHY_DX0MDLR1 0x000007A4 +#define DDRSS_DDRPHY_DX0GTR0 0x000007C0 +#define DDRSS_DDRPHY_DX0RSR0 0x000007D0 +#define DDRSS_DDRPHY_DX0RSR1 0x000007D4 +#define DDRSS_DDRPHY_DX0RSR2 0x000007D8 +#define DDRSS_DDRPHY_DX0RSR3 0x000007DC +#define DDRSS_DDRPHY_DX0GSR0 0x000007E0 +#define DDRSS_DDRPHY_DX0GSR1 0x000007E4 +#define DDRSS_DDRPHY_DX0GSR2 0x000007E8 +#define DDRSS_DDRPHY_DX0GSR3 0x000007EC +#define DDRSS_DDRPHY_DX0GSR4 0x000007F0 +#define DDRSS_DDRPHY_DX0GSR5 0x000007F4 +#define DDRSS_DDRPHY_DX0GSR6 0x000007F8 +#define DDRSS_DDRPHY_DX1GCR0 0x00000800 +#define DDRSS_DDRPHY_DX1GCR1 0x00000804 +#define DDRSS_DDRPHY_DX1GCR2 0x00000808 +#define DDRSS_DDRPHY_DX1GCR3 0x0000080C +#define DDRSS_DDRPHY_DX1GCR4 0x00000810 +#define DDRSS_DDRPHY_DX1GCR5 0x00000814 +#define DDRSS_DDRPHY_DX1GCR6 0x00000818 +#define DDRSS_DDRPHY_DX1GCR7 0x0000081C +#define DDRSS_DDRPHY_DX1GCR8 0x00000820 +#define DDRSS_DDRPHY_DX1GCR9 0x00000824 +#define DDRSS_DDRPHY_DX1DQMAP0 0x00000828 +#define DDRSS_DDRPHY_DX1DQMAP1 0x0000082C +#define DDRSS_DDRPHY_DX1BDLR0 0x00000840 +#define DDRSS_DDRPHY_DX1BDLR1 0x00000844 +#define DDRSS_DDRPHY_DX1BDLR2 0x00000848 +#define DDRSS_DDRPHY_DX1BDLR3 0x00000850 +#define DDRSS_DDRPHY_DX1BDLR4 0x00000854 +#define DDRSS_DDRPHY_DX1BDLR5 0x00000858 +#define DDRSS_DDRPHY_DX1BDLR6 0x00000860 +#define DDRSS_DDRPHY_DX1BDLR7 0x00000864 +#define DDRSS_DDRPHY_DX1BDLR8 0x00000868 +#define DDRSS_DDRPHY_DX1BDLR9 0x0000086C +#define DDRSS_DDRPHY_DX1LCDLR0 0x00000880 +#define DDRSS_DDRPHY_DX1LCDLR1 0x00000884 +#define DDRSS_DDRPHY_DX1LCDLR2 0x00000888 +#define DDRSS_DDRPHY_DX1LCDLR3 0x0000088C +#define DDRSS_DDRPHY_DX1LCDLR4 0x00000890 +#define DDRSS_DDRPHY_DX1LCDLR5 0x00000894 +#define DDRSS_DDRPHY_DX1MDLR0 0x000008A0 +#define DDRSS_DDRPHY_DX1MDLR1 0x000008A4 +#define DDRSS_DDRPHY_DX1GTR0 0x000008C0 +#define DDRSS_DDRPHY_DX1RSR0 0x000008D0 +#define DDRSS_DDRPHY_DX1RSR1 0x000008D4 +#define DDRSS_DDRPHY_DX1RSR2 0x000008D8 +#define DDRSS_DDRPHY_DX1RSR3 0x000008DC +#define DDRSS_DDRPHY_DX1GSR0 0x000008E0 +#define DDRSS_DDRPHY_DX1GSR1 0x000008E4 +#define DDRSS_DDRPHY_DX1GSR2 0x000008E8 +#define DDRSS_DDRPHY_DX1GSR3 0x000008EC +#define DDRSS_DDRPHY_DX1GSR4 0x000008F0 +#define DDRSS_DDRPHY_DX1GSR5 0x000008F4 +#define DDRSS_DDRPHY_DX1GSR6 0x000008F8 +#define DDRSS_DDRPHY_DX2GCR0 0x00000900 +#define DDRSS_DDRPHY_DX2GCR1 0x00000904 +#define DDRSS_DDRPHY_DX2GCR2 0x00000908 +#define DDRSS_DDRPHY_DX2GCR3 0x0000090C +#define DDRSS_DDRPHY_DX2GCR4 0x00000910 +#define DDRSS_DDRPHY_DX2GCR5 0x00000914 +#define DDRSS_DDRPHY_DX2GCR6 0x00000918 +#define DDRSS_DDRPHY_DX2GCR7 0x0000091C +#define DDRSS_DDRPHY_DX2GCR8 0x00000920 +#define DDRSS_DDRPHY_DX2GCR9 0x00000924 +#define DDRSS_DDRPHY_DX2DQMAP0 0x00000928 +#define DDRSS_DDRPHY_DX2DQMAP1 0x0000092C +#define DDRSS_DDRPHY_DX2BDLR0 0x00000940 +#define DDRSS_DDRPHY_DX2BDLR1 0x00000944 +#define DDRSS_DDRPHY_DX2BDLR2 0x00000948 +#define DDRSS_DDRPHY_DX2BDLR3 0x00000950 +#define DDRSS_DDRPHY_DX2BDLR4 0x00000954 +#define DDRSS_DDRPHY_DX2BDLR5 0x00000958 +#define DDRSS_DDRPHY_DX2BDLR6 0x00000960 +#define DDRSS_DDRPHY_DX2BDLR7 0x00000964 +#define DDRSS_DDRPHY_DX2BDLR8 0x00000968 +#define DDRSS_DDRPHY_DX2BDLR9 0x0000096C +#define DDRSS_DDRPHY_DX2LCDLR0 0x00000980 +#define DDRSS_DDRPHY_DX2LCDLR1 0x00000984 +#define DDRSS_DDRPHY_DX2LCDLR2 0x00000988 +#define DDRSS_DDRPHY_DX2LCDLR3 0x0000098C +#define DDRSS_DDRPHY_DX2LCDLR4 0x00000990 +#define DDRSS_DDRPHY_DX2LCDLR5 0x00000994 +#define DDRSS_DDRPHY_DX2MDLR0 0x000009A0 +#define DDRSS_DDRPHY_DX2MDLR1 0x000009A4 +#define DDRSS_DDRPHY_DX2GTR0 0x000009C0 +#define DDRSS_DDRPHY_DX2RSR0 0x000009D0 +#define DDRSS_DDRPHY_DX2RSR1 0x000009D4 +#define DDRSS_DDRPHY_DX2RSR2 0x000009D8 +#define DDRSS_DDRPHY_DX2RSR3 0x000009DC +#define DDRSS_DDRPHY_DX2GSR0 0x000009E0 +#define DDRSS_DDRPHY_DX2GSR1 0x000009E4 +#define DDRSS_DDRPHY_DX2GSR2 0x000009E8 +#define DDRSS_DDRPHY_DX2GSR3 0x000009EC +#define DDRSS_DDRPHY_DX2GSR4 0x000009F0 +#define DDRSS_DDRPHY_DX2GSR5 0x000009F4 +#define DDRSS_DDRPHY_DX2GSR6 0x000009F8 +#define DDRSS_DDRPHY_DX3GCR0 0x00000A00 +#define DDRSS_DDRPHY_DX3GCR1 0x00000A04 +#define DDRSS_DDRPHY_DX3GCR2 0x00000A08 +#define DDRSS_DDRPHY_DX3GCR3 0x00000A0C +#define DDRSS_DDRPHY_DX3GCR4 0x00000A10 +#define DDRSS_DDRPHY_DX3GCR5 0x00000A14 +#define DDRSS_DDRPHY_DX3GCR6 0x00000A18 +#define DDRSS_DDRPHY_DX3GCR7 0x00000A1C +#define DDRSS_DDRPHY_DX3GCR8 0x00000A20 +#define DDRSS_DDRPHY_DX3GCR9 0x00000A24 +#define DDRSS_DDRPHY_DX3DQMAP0 0x00000A28 +#define DDRSS_DDRPHY_DX3DQMAP1 0x00000A2C +#define DDRSS_DDRPHY_DX3BDLR0 0x00000A40 +#define DDRSS_DDRPHY_DX3BDLR1 0x00000A44 +#define DDRSS_DDRPHY_DX3BDLR2 0x00000A48 +#define DDRSS_DDRPHY_DX3BDLR3 0x00000A50 +#define DDRSS_DDRPHY_DX3BDLR4 0x00000A54 +#define DDRSS_DDRPHY_DX3BDLR5 0x00000A58 +#define DDRSS_DDRPHY_DX3BDLR6 0x00000A60 +#define DDRSS_DDRPHY_DX3BDLR7 0x00000A64 +#define DDRSS_DDRPHY_DX3BDLR8 0x00000A68 +#define DDRSS_DDRPHY_DX3BDLR9 0x00000A6C +#define DDRSS_DDRPHY_DX3LCDLR0 0x00000A80 +#define DDRSS_DDRPHY_DX3LCDLR1 0x00000A84 +#define DDRSS_DDRPHY_DX3LCDLR2 0x00000A88 +#define DDRSS_DDRPHY_DX3LCDLR3 0x00000A8C +#define DDRSS_DDRPHY_DX3LCDLR4 0x00000A90 +#define DDRSS_DDRPHY_DX3LCDLR5 0x00000A94 +#define DDRSS_DDRPHY_DX3MDLR0 0x00000AA0 +#define DDRSS_DDRPHY_DX3MDLR1 0x00000AA4 +#define DDRSS_DDRPHY_DX3GTR0 0x00000AC0 +#define DDRSS_DDRPHY_DX3RSR0 0x00000AD0 +#define DDRSS_DDRPHY_DX3RSR1 0x00000AD4 +#define DDRSS_DDRPHY_DX3RSR2 0x00000AD8 +#define DDRSS_DDRPHY_DX3RSR3 0x00000ADC +#define DDRSS_DDRPHY_DX3GSR0 0x00000AE0 +#define DDRSS_DDRPHY_DX3GSR1 0x00000AE4 +#define DDRSS_DDRPHY_DX3GSR2 0x00000AE8 +#define DDRSS_DDRPHY_DX3GSR3 0x00000AEC +#define DDRSS_DDRPHY_DX3GSR4 0x00000AF0 +#define DDRSS_DDRPHY_DX3GSR5 0x00000AF4 +#define DDRSS_DDRPHY_DX3GSR6 0x00000AF8 +#define DDRSS_DDRPHY_DX4GCR0 0x00000B00 +#define DDRSS_DDRPHY_DX4GCR1 0x00000B04 +#define DDRSS_DDRPHY_DX4GCR2 0x00000B08 +#define DDRSS_DDRPHY_DX4GCR3 0x00000B0C +#define DDRSS_DDRPHY_DX4GCR4 0x00000B10 +#define DDRSS_DDRPHY_DX4GCR5 0x00000B14 +#define DDRSS_DDRPHY_DX4GCR6 0x00000B18 +#define DDRSS_DDRPHY_DX4GCR7 0x00000B1C +#define DDRSS_DDRPHY_DX4GCR8 0x00000B20 +#define DDRSS_DDRPHY_DX4GCR9 0x00000B24 +#define DDRSS_DDRPHY_DX4DQMAP0 0x00000B28 +#define DDRSS_DDRPHY_DX4DQMAP1 0x00000B2C +#define DDRSS_DDRPHY_DX4BDLR0 0x00000B40 +#define DDRSS_DDRPHY_DX4BDLR1 0x00000B44 +#define DDRSS_DDRPHY_DX4BDLR2 0x00000B48 +#define DDRSS_DDRPHY_DX4BDLR3 0x00000B50 +#define DDRSS_DDRPHY_DX4BDLR4 0x00000B54 +#define DDRSS_DDRPHY_DX4BDLR5 0x00000B58 +#define DDRSS_DDRPHY_DX4BDLR6 0x00000B60 +#define DDRSS_DDRPHY_DX4BDLR7 0x00000B64 +#define DDRSS_DDRPHY_DX4BDLR8 0x00000B68 +#define DDRSS_DDRPHY_DX4BDLR9 0x00000B6C +#define DDRSS_DDRPHY_DX4LCDLR0 0x00000B80 +#define DDRSS_DDRPHY_DX4LCDLR1 0x00000B84 +#define DDRSS_DDRPHY_DX4LCDLR2 0x00000B88 +#define DDRSS_DDRPHY_DX4LCDLR3 0x00000B8C +#define DDRSS_DDRPHY_DX4LCDLR4 0x00000B90 +#define DDRSS_DDRPHY_DX4LCDLR5 0x00000B94 +#define DDRSS_DDRPHY_DX4MDLR0 0x00000BA0 +#define DDRSS_DDRPHY_DX4MDLR1 0x00000BA4 +#define DDRSS_DDRPHY_DX4GTR0 0x00000BC0 +#define DDRSS_DDRPHY_DX4RSR0 0x00000BD0 +#define DDRSS_DDRPHY_DX4RSR1 0x00000BD4 +#define DDRSS_DDRPHY_DX4RSR2 0x00000BD8 +#define DDRSS_DDRPHY_DX4RSR3 0x00000BDC +#define DDRSS_DDRPHY_DX4GSR0 0x00000BE0 +#define DDRSS_DDRPHY_DX4GSR1 0x00000BE4 +#define DDRSS_DDRPHY_DX4GSR2 0x00000BE8 +#define DDRSS_DDRPHY_DX4GSR3 0x00000BEC +#define DDRSS_DDRPHY_DX4GSR4 0x00000BF0 +#define DDRSS_DDRPHY_DX4GSR5 0x00000BF4 +#define DDRSS_DDRPHY_DX4GSR6 0x00000BF8 +#define DDRSS_DDRPHY_DX5GCR0 0x00000C00 +#define DDRSS_DDRPHY_DX5GCR1 0x00000C04 +#define DDRSS_DDRPHY_DX5GCR2 0x00000C08 +#define DDRSS_DDRPHY_DX5GCR3 0x00000C0C +#define DDRSS_DDRPHY_DX5GCR4 0x00000C10 +#define DDRSS_DDRPHY_DX5GCR5 0x00000C14 +#define DDRSS_DDRPHY_DX5GCR6 0x00000C18 +#define DDRSS_DDRPHY_DX5GCR7 0x00000C1C +#define DDRSS_DDRPHY_DX5GCR8 0x00000C20 +#define DDRSS_DDRPHY_DX5GCR9 0x00000C24 +#define DDRSS_DDRPHY_DX5DQMAP0 0x00000C28 +#define DDRSS_DDRPHY_DX5DQMAP1 0x00000C2C +#define DDRSS_DDRPHY_DX5BDLR0 0x00000C40 +#define DDRSS_DDRPHY_DX5BDLR1 0x00000C44 +#define DDRSS_DDRPHY_DX5BDLR2 0x00000C48 +#define DDRSS_DDRPHY_DX5BDLR3 0x00000C50 +#define DDRSS_DDRPHY_DX5BDLR4 0x00000C54 +#define DDRSS_DDRPHY_DX5BDLR5 0x00000C58 +#define DDRSS_DDRPHY_DX5BDLR6 0x00000C60 +#define DDRSS_DDRPHY_DX5BDLR7 0x00000C64 +#define DDRSS_DDRPHY_DX5BDLR8 0x00000C68 +#define DDRSS_DDRPHY_DX5BDLR9 0x00000C6C +#define DDRSS_DDRPHY_DX5LCDLR0 0x00000C80 +#define DDRSS_DDRPHY_DX5LCDLR1 0x00000C84 +#define DDRSS_DDRPHY_DX5LCDLR2 0x00000C88 +#define DDRSS_DDRPHY_DX5LCDLR3 0x00000C8C +#define DDRSS_DDRPHY_DX5LCDLR4 0x00000C90 +#define DDRSS_DDRPHY_DX5LCDLR5 0x00000C94 +#define DDRSS_DDRPHY_DX5MDLR0 0x00000CA0 +#define DDRSS_DDRPHY_DX5MDLR1 0x00000CA4 +#define DDRSS_DDRPHY_DX5GTR0 0x00000CC0 +#define DDRSS_DDRPHY_DX5RSR0 0x00000CD0 +#define DDRSS_DDRPHY_DX5RSR1 0x00000CD4 +#define DDRSS_DDRPHY_DX5RSR2 0x00000CD8 +#define DDRSS_DDRPHY_DX5RSR3 0x00000CDC +#define DDRSS_DDRPHY_DX5GSR0 0x00000CE0 +#define DDRSS_DDRPHY_DX5GSR1 0x00000CE4 +#define DDRSS_DDRPHY_DX5GSR2 0x00000CE8 +#define DDRSS_DDRPHY_DX5GSR3 0x00000CEC +#define DDRSS_DDRPHY_DX5GSR4 0x00000CF0 +#define DDRSS_DDRPHY_DX5GSR5 0x00000CF4 +#define DDRSS_DDRPHY_DX5GSR6 0x00000CF8 +#define DDRSS_DDRPHY_DX6GCR0 0x00000D00 +#define DDRSS_DDRPHY_DX6GCR1 0x00000D04 +#define DDRSS_DDRPHY_DX6GCR2 0x00000D08 +#define DDRSS_DDRPHY_DX6GCR3 0x00000D0C +#define DDRSS_DDRPHY_DX6GCR4 0x00000D10 +#define DDRSS_DDRPHY_DX6GCR5 0x00000D14 +#define DDRSS_DDRPHY_DX6GCR6 0x00000D18 +#define DDRSS_DDRPHY_DX6GCR7 0x00000D1C +#define DDRSS_DDRPHY_DX6GCR8 0x00000D20 +#define DDRSS_DDRPHY_DX6GCR9 0x00000D24 +#define DDRSS_DDRPHY_DX6DQMAP0 0x00000D28 +#define DDRSS_DDRPHY_DX6DQMAP1 0x00000D2C +#define DDRSS_DDRPHY_DX6BDLR0 0x00000D40 +#define DDRSS_DDRPHY_DX6BDLR1 0x00000D44 +#define DDRSS_DDRPHY_DX6BDLR2 0x00000D48 +#define DDRSS_DDRPHY_DX6BDLR3 0x00000D50 +#define DDRSS_DDRPHY_DX6BDLR4 0x00000D54 +#define DDRSS_DDRPHY_DX6BDLR5 0x00000D58 +#define DDRSS_DDRPHY_DX6BDLR6 0x00000D60 +#define DDRSS_DDRPHY_DX6BDLR7 0x00000D64 +#define DDRSS_DDRPHY_DX6BDLR8 0x00000D68 +#define DDRSS_DDRPHY_DX6BDLR9 0x00000D6C +#define DDRSS_DDRPHY_DX6LCDLR0 0x00000D80 +#define DDRSS_DDRPHY_DX6LCDLR1 0x00000D84 +#define DDRSS_DDRPHY_DX6LCDLR2 0x00000D88 +#define DDRSS_DDRPHY_DX6LCDLR3 0x00000D8C +#define DDRSS_DDRPHY_DX6LCDLR4 0x00000D90 +#define DDRSS_DDRPHY_DX6LCDLR5 0x00000D94 +#define DDRSS_DDRPHY_DX6MDLR0 0x00000DA0 +#define DDRSS_DDRPHY_DX6MDLR1 0x00000DA4 +#define DDRSS_DDRPHY_DX6GTR0 0x00000DC0 +#define DDRSS_DDRPHY_DX6RSR0 0x00000DD0 +#define DDRSS_DDRPHY_DX6RSR1 0x00000DD4 +#define DDRSS_DDRPHY_DX6RSR2 0x00000DD8 +#define DDRSS_DDRPHY_DX6RSR3 0x00000DDC +#define DDRSS_DDRPHY_DX6GSR0 0x00000DE0 +#define DDRSS_DDRPHY_DX6GSR1 0x00000DE4 +#define DDRSS_DDRPHY_DX6GSR2 0x00000DE8 +#define DDRSS_DDRPHY_DX6GSR3 0x00000DEC +#define DDRSS_DDRPHY_DX6GSR4 0x00000DF0 +#define DDRSS_DDRPHY_DX6GSR5 0x00000DF4 +#define DDRSS_DDRPHY_DX6GSR6 0x00000DF8 +#define DDRSS_DDRPHY_DX7GCR0 0x00000E00 +#define DDRSS_DDRPHY_DX7GCR1 0x00000E04 +#define DDRSS_DDRPHY_DX7GCR2 0x00000E08 +#define DDRSS_DDRPHY_DX7GCR3 0x00000E0C +#define DDRSS_DDRPHY_DX7GCR4 0x00000E10 +#define DDRSS_DDRPHY_DX7GCR5 0x00000E14 +#define DDRSS_DDRPHY_DX7GCR6 0x00000E18 +#define DDRSS_DDRPHY_DX7GCR7 0x00000E1C +#define DDRSS_DDRPHY_DX7GCR8 0x00000E20 +#define DDRSS_DDRPHY_DX7GCR9 0x00000E24 +#define DDRSS_DDRPHY_DX7DQMAP0 0x00000E28 +#define DDRSS_DDRPHY_DX7DQMAP1 0x00000E2C +#define DDRSS_DDRPHY_DX7BDLR0 0x00000E40 +#define DDRSS_DDRPHY_DX7BDLR1 0x00000E44 +#define DDRSS_DDRPHY_DX7BDLR2 0x00000E48 +#define DDRSS_DDRPHY_DX7BDLR3 0x00000E50 +#define DDRSS_DDRPHY_DX7BDLR4 0x00000E54 +#define DDRSS_DDRPHY_DX7BDLR5 0x00000E58 +#define DDRSS_DDRPHY_DX7BDLR6 0x00000E60 +#define DDRSS_DDRPHY_DX7BDLR7 0x00000E64 +#define DDRSS_DDRPHY_DX7BDLR8 0x00000E68 +#define DDRSS_DDRPHY_DX7BDLR9 0x00000E6C +#define DDRSS_DDRPHY_DX7LCDLR0 0x00000E80 +#define DDRSS_DDRPHY_DX7LCDLR1 0x00000E84 +#define DDRSS_DDRPHY_DX7LCDLR2 0x00000E88 +#define DDRSS_DDRPHY_DX7LCDLR3 0x00000E8C +#define DDRSS_DDRPHY_DX7LCDLR4 0x00000E90 +#define DDRSS_DDRPHY_DX7LCDLR5 0x00000E94 +#define DDRSS_DDRPHY_DX7MDLR0 0x00000EA0 +#define DDRSS_DDRPHY_DX7MDLR1 0x00000EA4 +#define DDRSS_DDRPHY_DX7GTR0 0x00000EC0 +#define DDRSS_DDRPHY_DX7RSR0 0x00000ED0 +#define DDRSS_DDRPHY_DX7RSR1 0x00000ED4 +#define DDRSS_DDRPHY_DX7RSR2 0x00000ED8 +#define DDRSS_DDRPHY_DX7RSR3 0x00000EDC +#define DDRSS_DDRPHY_DX7GSR0 0x00000EE0 +#define DDRSS_DDRPHY_DX7GSR1 0x00000EE4 +#define DDRSS_DDRPHY_DX7GSR2 0x00000EE8 +#define DDRSS_DDRPHY_DX7GSR3 0x00000EEC +#define DDRSS_DDRPHY_DX7GSR4 0x00000EF0 +#define DDRSS_DDRPHY_DX7GSR5 0x00000EF4 +#define DDRSS_DDRPHY_DX7GSR6 0x00000EF8 +#define DDRSS_DDRPHY_DX8GCR0 0x00000F00 +#define DDRSS_DDRPHY_DX8GCR1 0x00000F04 +#define DDRSS_DDRPHY_DX8GCR2 0x00000F08 +#define DDRSS_DDRPHY_DX8GCR3 0x00000F0C +#define DDRSS_DDRPHY_DX8GCR4 0x00000F10 +#define DDRSS_DDRPHY_DX8GCR5 0x00000F14 +#define DDRSS_DDRPHY_DX8GCR6 0x00000F18 +#define DDRSS_DDRPHY_DX8GCR7 0x00000F1C +#define DDRSS_DDRPHY_DX8GCR8 0x00000F20 +#define DDRSS_DDRPHY_DX8GCR9 0x00000F24 +#define DDRSS_DDRPHY_DX8DQMAP0 0x00000F28 +#define DDRSS_DDRPHY_DX8DQMAP1 0x00000F2C +#define DDRSS_DDRPHY_DX8BDLR0 0x00000F40 +#define DDRSS_DDRPHY_DX8BDLR1 0x00000F44 +#define DDRSS_DDRPHY_DX8BDLR2 0x00000F48 +#define DDRSS_DDRPHY_DX8BDLR3 0x00000F50 +#define DDRSS_DDRPHY_DX8BDLR4 0x00000F54 +#define DDRSS_DDRPHY_DX8BDLR5 0x00000F58 +#define DDRSS_DDRPHY_DX8BDLR6 0x00000F60 +#define DDRSS_DDRPHY_DX8BDLR7 0x00000F64 +#define DDRSS_DDRPHY_DX8BDLR8 0x00000F68 +#define DDRSS_DDRPHY_DX8BDLR9 0x00000F6C +#define DDRSS_DDRPHY_DX8LCDLR0 0x00000F80 +#define DDRSS_DDRPHY_DX8LCDLR1 0x00000F84 +#define DDRSS_DDRPHY_DX8LCDLR2 0x00000F88 +#define DDRSS_DDRPHY_DX8LCDLR3 0x00000F8C +#define DDRSS_DDRPHY_DX8LCDLR4 0x00000F90 +#define DDRSS_DDRPHY_DX8LCDLR5 0x00000F94 +#define DDRSS_DDRPHY_DX8MDLR0 0x00000FA0 +#define DDRSS_DDRPHY_DX8MDLR1 0x00000FA4 +#define DDRSS_DDRPHY_DX8GTR0 0x00000FC0 +#define DDRSS_DDRPHY_DX8RSR0 0x00000FD0 +#define DDRSS_DDRPHY_DX8RSR1 0x00000FD4 +#define DDRSS_DDRPHY_DX8RSR2 0x00000FD8 +#define DDRSS_DDRPHY_DX8RSR3 0x00000FDC +#define DDRSS_DDRPHY_DX8GSR0 0x00000FE0 +#define DDRSS_DDRPHY_DX8GSR1 0x00000FE4 +#define DDRSS_DDRPHY_DX8GSR2 0x00000FE8 +#define DDRSS_DDRPHY_DX8GSR3 0x00000FEC +#define DDRSS_DDRPHY_DX8GSR4 0x00000FF0 +#define DDRSS_DDRPHY_DX8GSR5 0x00000FF4 +#define DDRSS_DDRPHY_DX8GSR6 0x00000FF8 +#define DDRSS_DDRPHY_DX8SL0OSC 0x00001400 +#define DDRSS_DDRPHY_DX8SL0PLLCR0 0x00001404 +#define DDRSS_DDRPHY_DX8SL0PLLCR1 0x00001408 +#define DDRSS_DDRPHY_DX8SL0PLLCR2 0x0000140C +#define DDRSS_DDRPHY_DX8SL0PLLCR3 0x00001410 +#define DDRSS_DDRPHY_DX8SL0PLLCR4 0x00001414 +#define DDRSS_DDRPHY_DX8SL0PLLCR5 0x00001418 +#define DDRSS_DDRPHY_DX8SL0DQSCTL 0x0000141C +#define DDRSS_DDRPHY_DX8SL0TRNCTL 0x00001420 +#define DDRSS_DDRPHY_DX8SL0DDLCTL 0x00001424 +#define DDRSS_DDRPHY_DX8SL0DXCTL1 0x00001428 +#define DDRSS_DDRPHY_DX8SL0DXCTL2 0x0000142C +#define DDRSS_DDRPHY_DX8SL0IOCR 0x00001430 +#define DDRSS_DDRPHY_DX4SL0IOCR 0x00001434 +#define DDRSS_DDRPHY_DX8SL1OSC 0x00001440 +#define DDRSS_DDRPHY_DX8SL1PLLCR0 0x00001444 +#define DDRSS_DDRPHY_DX8SL1PLLCR1 0x00001448 +#define DDRSS_DDRPHY_DX8SL1PLLCR2 0x0000144C +#define DDRSS_DDRPHY_DX8SL1PLLCR3 0x00001450 +#define DDRSS_DDRPHY_DX8SL1PLLCR4 0x00001454 +#define DDRSS_DDRPHY_DX8SL1PLLCR5 0x00001458 +#define DDRSS_DDRPHY_DX8SL1DQSCTL 0x0000145C +#define DDRSS_DDRPHY_DX8SL1TRNCTL 0x00001460 +#define DDRSS_DDRPHY_DX8SL1DDLCTL 0x00001464 +#define DDRSS_DDRPHY_DX8SL1DXCTL1 0x00001468 +#define DDRSS_DDRPHY_DX8SL1DXCTL2 0x0000146C +#define DDRSS_DDRPHY_DX8SL1IOCR 0x00001470 +#define DDRSS_DDRPHY_DX4SL1IOCR 0x00001474 +#define DDRSS_DDRPHY_DX8SL2OSC 0x00001480 +#define DDRSS_DDRPHY_DX8SL2PLLCR0 0x00001484 +#define DDRSS_DDRPHY_DX8SL2PLLCR1 0x00001488 +#define DDRSS_DDRPHY_DX8SL2PLLCR2 0x0000148C +#define DDRSS_DDRPHY_DX8SL2PLLCR3 0x00001490 +#define DDRSS_DDRPHY_DX8SL2PLLCR4 0x00001494 +#define DDRSS_DDRPHY_DX8SL2PLLCR5 0x00001498 +#define DDRSS_DDRPHY_DX8SL2DQSCTL 0x0000149C +#define DDRSS_DDRPHY_DX8SL2TRNCTL 0x000014A0 +#define DDRSS_DDRPHY_DX8SL2DDLCTL 0x000014A4 +#define DDRSS_DDRPHY_DX8SL2DXCTL1 0x000014A8 +#define DDRSS_DDRPHY_DX8SL2DXCTL2 0x000014AC +#define DDRSS_DDRPHY_DX8SL2IOCR 0x000014B0 +#define DDRSS_DDRPHY_DX4SL2IOCR 0x000014B4 +#define DDRSS_DDRPHY_DX8SL3OSC 0x000014C0 +#define DDRSS_DDRPHY_DX8SL3PLLCR0 0x000014C4 +#define DDRSS_DDRPHY_DX8SL3PLLCR1 0x000014C8 +#define DDRSS_DDRPHY_DX8SL3PLLCR2 0x000014CC +#define DDRSS_DDRPHY_DX8SL3PLLCR3 0x000014D0 +#define DDRSS_DDRPHY_DX8SL3PLLCR4 0x000014D4 +#define DDRSS_DDRPHY_DX8SL3PLLCR5 0x000014D8 +#define DDRSS_DDRPHY_DX8SL3DQSCTL 0x000014DC +#define DDRSS_DDRPHY_DX8SL3TRNCTL 0x000014E0 +#define DDRSS_DDRPHY_DX8SL3DDLCTL 0x000014E4 +#define DDRSS_DDRPHY_DX8SL3DXCTL1 0x000014E8 +#define DDRSS_DDRPHY_DX8SL3DXCTL2 0x000014EC +#define DDRSS_DDRPHY_DX8SL3IOCR 0x000014F0 +#define DDRSS_DDRPHY_DX4SL3IOCR 0x000014F4 +#define DDRSS_DDRPHY_DX8SL4OSC 0x00001500 +#define DDRSS_DDRPHY_DX8SL4PLLCR0 0x00001504 +#define DDRSS_DDRPHY_DX8SL4PLLCR1 0x00001508 +#define DDRSS_DDRPHY_DX8SL4PLLCR2 0x0000150C +#define DDRSS_DDRPHY_DX8SL4PLLCR3 0x00001510 +#define DDRSS_DDRPHY_DX8SL4PLLCR4 0x00001514 +#define DDRSS_DDRPHY_DX8SL4PLLCR5 0x00001518 +#define DDRSS_DDRPHY_DX8SL4DQSCTL 0x0000151C +#define DDRSS_DDRPHY_DX8SL4TRNCTL 0x00001520 +#define DDRSS_DDRPHY_DX8SL4DDLCTL 0x00001524 +#define DDRSS_DDRPHY_DX8SL4DXCTL1 0x00001528 +#define DDRSS_DDRPHY_DX8SL4DXCTL2 0x0000152C +#define DDRSS_DDRPHY_DX8SL4IOCR 0x00001530 +#define DDRSS_DDRPHY_DX4SL4IOCR 0x00001534 +#define DDRSS_DDRPHY_DX8SL5OSC 0x00001540 +#define DDRSS_DDRPHY_DX8SL5PLLCR0 0x00001544 +#define DDRSS_DDRPHY_DX8SL5PLLCR1 0x00001548 +#define DDRSS_DDRPHY_DX8SL5PLLCR2 0x0000154C +#define DDRSS_DDRPHY_DX8SL5PLLCR3 0x00001550 +#define DDRSS_DDRPHY_DX8SL5PLLCR4 0x00001554 +#define DDRSS_DDRPHY_DX8SL5PLLCR5 0x00001558 +#define DDRSS_DDRPHY_DX8SL5DQSCTL 0x0000155C +#define DDRSS_DDRPHY_DX8SL5TRNCTL 0x00001560 +#define DDRSS_DDRPHY_DX8SL5DDLCTL 0x00001564 +#define DDRSS_DDRPHY_DX8SL5DXCTL1 0x00001568 +#define DDRSS_DDRPHY_DX8SL5DXCTL2 0x0000156C +#define DDRSS_DDRPHY_DX8SL5IOCR 0x00001570 +#define DDRSS_DDRPHY_DX4SL5IOCR 0x00001574 +#define DDRSS_DDRPHY_DX8SL6OSC 0x00001580 +#define DDRSS_DDRPHY_DX8SL6PLLCR0 0x00001584 +#define DDRSS_DDRPHY_DX8SL6PLLCR1 0x00001588 +#define DDRSS_DDRPHY_DX8SL6PLLCR2 0x0000158C +#define DDRSS_DDRPHY_DX8SL6PLLCR3 0x00001590 +#define DDRSS_DDRPHY_DX8SL6PLLCR4 0x00001594 +#define DDRSS_DDRPHY_DX8SL6PLLCR5 0x00001598 +#define DDRSS_DDRPHY_DX8SL6DQSCTL 0x0000159C +#define DDRSS_DDRPHY_DX8SL6TRNCTL 0x000015A0 +#define DDRSS_DDRPHY_DX8SL6DDLCTL 0x000015A4 +#define DDRSS_DDRPHY_DX8SL6DXCTL1 0x000015A8 +#define DDRSS_DDRPHY_DX8SL6DXCTL2 0x000015AC +#define DDRSS_DDRPHY_DX8SL6IOCR 0x000015B0 +#define DDRSS_DDRPHY_DX4SL6IOCR 0x000015B4 +#define DDRSS_DDRPHY_DX8SL7OSC 0x000015C0 +#define DDRSS_DDRPHY_DX8SL7PLLCR0 0x000015C4 +#define DDRSS_DDRPHY_DX8SL7PLLCR1 0x000015C8 +#define DDRSS_DDRPHY_DX8SL7PLLCR2 0x000015CC +#define DDRSS_DDRPHY_DX8SL7PLLCR3 0x000015D0 +#define DDRSS_DDRPHY_DX8SL7PLLCR4 0x000015D4 +#define DDRSS_DDRPHY_DX8SL7PLLCR5 0x000015D8 +#define DDRSS_DDRPHY_DX8SL7DQSCTL 0x000015DC +#define DDRSS_DDRPHY_DX8SL7TRNCTL 0x000015E0 +#define DDRSS_DDRPHY_DX8SL7DDLCTL 0x000015E4 +#define DDRSS_DDRPHY_DX8SL7DXCTL1 0x000015E8 +#define DDRSS_DDRPHY_DX8SL7DXCTL2 0x000015EC +#define DDRSS_DDRPHY_DX8SL7IOCR 0x000015F0 +#define DDRSS_DDRPHY_DX4SL7IOCR 0x000015F4 +#define DDRSS_DDRPHY_DX8SL8OSC 0x00001600 +#define DDRSS_DDRPHY_DX8SL8PLLCR0 0x00001604 +#define DDRSS_DDRPHY_DX8SL8PLLCR1 0x00001608 +#define DDRSS_DDRPHY_DX8SL8PLLCR2 0x0000160C +#define DDRSS_DDRPHY_DX8SL8PLLCR3 0x00001610 +#define DDRSS_DDRPHY_DX8SL8PLLCR4 0x00001614 +#define DDRSS_DDRPHY_DX8SL8PLLCR5 0x00001618 +#define DDRSS_DDRPHY_DX8SL8DQSCTL 0x0000161C +#define DDRSS_DDRPHY_DX8SL8TRNCTL 0x00001620 +#define DDRSS_DDRPHY_DX8SL8DDLCTL 0x00001624 +#define DDRSS_DDRPHY_DX8SL8DXCTL1 0x00001628 +#define DDRSS_DDRPHY_DX8SL8DXCTL2 0x0000162C +#define DDRSS_DDRPHY_DX8SL8IOCR 0x00001630 +#define DDRSS_DDRPHY_DX4SL8IOCR 0x00001634 +#define DDRSS_DDRPHY_DX8SLBOSC 0x000017C0 +#define DDRSS_DDRPHY_DX8SLBPLLCR0 0x000017C4 +#define DDRSS_DDRPHY_DX8SLBPLLCR1 0x000017C8 +#define DDRSS_DDRPHY_DX8SLBPLLCR2 0x000017CC +#define DDRSS_DDRPHY_DX8SLBPLLCR3 0x000017D0 +#define DDRSS_DDRPHY_DX8SLBPLLCR4 0x000017D4 +#define DDRSS_DDRPHY_DX8SLBPLLCR5 0x000017D8 +#define DDRSS_DDRPHY_DX8SLBDQSCTL 0x000017DC +#define DDRSS_DDRPHY_DX8SLBTRNCTL 0x000017E0 +#define DDRSS_DDRPHY_DX8SLBDDLCTL 0x000017E4 +#define DDRSS_DDRPHY_DX8SLBDXCTL1 0x000017E8 +#define DDRSS_DDRPHY_DX8SLBDXCTL2 0x000017EC +#define DDRSS_DDRPHY_DX8SLBIOCR 0x000017F0 +#define DDRSS_DDRPHY_DX4SLBIOCR 0x000017F4 + +#define PIR_INIT_SHIFT 0 +#define PIR_INIT_MASK BIT(PIR_INIT_SHIFT) +#define PIR_ZCAL_SHIFT 1 +#define PIR_ZCAL_MASK BIT(PIR_ZCAL_SHIFT) +#define PIR_CA_SHIFT 2 +#define PIR_CA_MASK BIT(PIR_CA_SHIFT) +#define PIR_PLLINIT_SHIFT 4 +#define PIR_PLLINIT_MASK BIT(PIR_PLLINIT_SHIFT) +#define PIR_DCAL_SHIFT 5 +#define PIR_DCAL_MASK BIT(PIR_DCAL_SHIFT) +#define PIR_PHYRST_SHIFT 6 +#define PIR_PHYRST_MASK BIT(PIR_PHYRST_SHIFT) +#define PIR_DRAMRST_SHIFT 7 +#define PIR_DRAMRST_MASK BIT(PIR_DRAMRST_SHIFT) +#define PIR_DRAMINIT_SHIFT 8 +#define PIR_DRAMINIT_MASK BIT(PIR_DRAMINIT_SHIFT) +#define PIR_WL_SHIFT 9 +#define PIR_WL_MASK BIT(PIR_WL_SHIFT) +#define PIR_QSGATE_SHIFT 10 +#define PIR_QSGATE_MASK BIT(PIR_QSGATE_SHIFT) +#define PIR_WLADJ_SHIFT 11 +#define PIR_WLADJ_MASK BIT(PIR_WLADJ_SHIFT) +#define PIR_RDDSKW_SHIFT 12 +#define PIR_RDDSKW_MASK BIT(PIR_RDDSKW_SHIFT) +#define PIR_WRDSKW_SHIFT 13 +#define PIR_WRDSKW_MASK BIT(PIR_WRDSKW_SHIFT) +#define PIR_RDEYE_SHIFT 14 +#define PIR_RDEYE_MASK BIT(PIR_RDEYE_SHIFT) +#define PIR_WREYE_SHIFT 15 +#define PIR_WREYE_MASK BIT(PIR_WREYE_SHIFT) +#define PIR_SRD_SHIFT 16 +#define PIR_SRD_MASK BIT(PIR_SRD_SHIFT) +#define PIR_VREF_SHIFT 17 +#define PIR_VREF_MASK BIT(PIR_VREF_SHIFT) +#define PIR_CTLDINIT_SHIFT 18 +#define PIR_CTLDINIT_MASK BIT(PIR_CTLDINIT_SHIFT) +#define PIR_RDIMMINIT_SHIFT 19 +#define PIR_RDIMMINIT_MASK BIT(PIR_RDIMMINIT_SHIFT) +#define PIR_DQS2DQ_SHIFT 20 +#define PIR_DQS2DQ_MASK BIT(PIR_DQS2DQ_SHIFT) +#define PIR_DCALPSE_SHIFT 29 +#define PIR_DCALPSE_MASK BIT(PIR_DCALPSE_SHIFT) +#define PIR_ZCALBYP_SHIFT 30 +#define PIR_ZCALBYP_MASK BIT(PIR_ZCALBYP_SHIFT) + +#define PIR_PHY_INIT (PIR_ZCAL_MASK | PIR_PLLINIT_MASK | \ + PIR_DCAL_MASK | PIR_PHYRST_MASK) +#define PIR_DRAM_INIT (PIR_DRAMRST_MASK | PIR_DRAMINIT_MASK) +#define PIR_DATA_TR_INIT (PIR_WL_MASK | PIR_QSGATE_MASK | \ + PIR_WLADJ_MASK | PIR_RDDSKW_MASK | \ + PIR_WRDSKW_MASK | PIR_RDEYE_MASK \ + PIR_WREYE_MASK) + +#define PGSR0_IDONE_SHIFT 0 +#define PGSR0_IDONE_MASK BIT(PGSR0_IDONE_SHIFT) +#define PGSR0_PLDONE_SHIFT 1 +#define PGSR0_PLDONE_MASK BIT(PGSR0_PLDONE_SHIFT) +#define PGSR0_DCDONE_SHIFT 2 +#define PGSR0_DCDONE_MASK BIT(PGSR0_DCDONE_SHIFT) +#define PGSR0_ZCDONE_SHIFT 3 +#define PGSR0_ZCDONE_MASK BIT(PGSR0_ZCDONE_SHIFT) +#define PGSR0_DIDONE_SHIFT 4 +#define PGSR0_DIDONE_MASK BIT(PGSR0_DIDONE_SHIFT) +#define PGSR0_WLDONE_SHIFT 5 +#define PGSR0_WLDONE_MASK BIT(PGSR0_WLDONE_SHIFT) +#define PGSR0_QSGDONE_SHIFT 6 +#define PGSR0_QSGDONE_MASK BIT(PGSR0_QSGDONE_SHIFT) +#define PGSR0_WLADONE_SHIFT 7 +#define PGSR0_WLADONE_MASK BIT(PGSR0_WLADONE_SHIFT) +#define PGSR0_RDDONE_SHIFT 8 +#define PGSR0_RDDONE_MASK BIT(PGSR0_RDDONE_SHIFT) +#define PGSR0_WDDONE_SHIFT 9 +#define PGSR0_WDDONE_MASK BIT(PGSR0_WDDONE_SHIFT) +#define PGSR0_REDONE_SHIFT 10 +#define PGSR0_REDONE_MASK BIT(PGSR0_REDONE_SHIFT) +#define PGSR0_WEDONE_SHIFT 11 +#define PGSR0_WEDONE_MASK BIT(PGSR0_WEDONE_SHIFT) +#define PGSR0_CADONE_SHIFT 12 +#define PGSR0_CADONE_MASK BIT(PGSR0_CADONE_SHIFT) +#define PGSR0_SRDDONE_SHIFT 13 +#define PGSR0_SRDDONE_MASK BIT(PGSR0_SRDDONE_SHIFT) +#define PGSR0_VDONE_SHIFT 14 +#define PGSR0_VDONE_MASK BIT(PGSR0_VDONE_SHIFT) +#define PGSR0_DQS2DQDONE_SHIFT 15 +#define PGSR0_DQS2DQDONE_MASK BIT(PGSR0_DQS2DQDONE_SHIFT) +#define PGSR0_DQS2DQERR_SHIFT 18 +#define PGSR0_DQS2DQERR_MASK BIT(PGSR0_DQS2DQERR_SHIFT) +#define PGSR0_VERR_SHIFT 19 +#define PGSR0_VERR_MASK BIT(PGSR0_VERR_SHIFT) +#define PGSR0_ZCERR_SHIFT 20 +#define PGSR0_ZCERR_MASK BIT(PGSR0_ZCERR_SHIFT) +#define PGSR0_WLERR_SHIFT 21 +#define PGSR0_WLERR_MASK BIT(PGSR0_WLERR_SHIFT) +#define PGSR0_QSGERR_SHIFT 22 +#define PGSR0_QSGERR_MASK BIT(PGSR0_QSGERR_SHIFT) +#define PGSR0_WLAERR_SHIFT 23 +#define PGSR0_WLAERR_MASK BIT(PGSR0_WLAERR_SHIFT) +#define PGSR0_RDERR_SHIFT 24 +#define PGSR0_RDERR_MASK BIT(PGSR0_RDERR_SHIFT) +#define PGSR0_WDERR_SHIFT 25 +#define PGSR0_WDERR_MASK BIT(PGSR0_WDERR_SHIFT) +#define PGSR0_REERR_SHIFT 26 +#define PGSR0_REERR_MASK BIT(PGSR0_REERR_SHIFT) +#define PGSR0_WEERR_SHIFT 27 +#define PGSR0_WEERR_MASK BIT(PGSR0_WEERR_SHIFT) +#define PGSR0_CAERR_SHIFT 28 +#define PGSR0_CAERR_MASK BIT(PGSR0_CAERR_SHIFT) +#define PGSR0_CAWRN_SHIFT 29 +#define PGSR0_CAWRN_MASK BIT(PGSR0_CAWRN_SHIFT) +#define PGSR0_SRDERR_SHIFT 30 +#define PGSR0_SRDERR_MASK BIT(PGSR0_SRDERR_SHIFT) +#define PGSR0_APLOCK_SHIFT 31 +#define PGSR0_APLOCK_MASK BIT(PGSR0_APLOCK_SHIFT) + +#define PGSR0_PHY_INIT_MASK (PGSR0_IDONE_MASK | PGSR0_PLDONE_MASK |\ + PGSR0_DCDONE_MASK | PGSR0_ZCDONE_MASK |\ + PGSR0_APLOCK_MASK) +#define PGSR0_DRAM_INIT_MASK (PGSR0_PHY_INIT_MASK | \ + PGSR0_DIDONE_MASK) +#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK) + +struct ddrss_ddrctl_reg_params { + u32 ddrctl_dfimisc; + u32 ddrctl_dfitmg0; + u32 ddrctl_dfitmg1; + u32 ddrctl_dfitmg2; + u32 ddrctl_init0; + u32 ddrctl_init1; + u32 ddrctl_init3; + u32 ddrctl_init4; + u32 ddrctl_init5; + u32 ddrctl_init6; + u32 ddrctl_init7; + u32 ddrctl_mstr; + u32 ddrctl_odtcfg; + u32 ddrctl_odtmap; + u32 ddrctl_rankctl; + u32 ddrctl_rfshctl0; + u32 ddrctl_rfshtmg; + u32 ddrctl_zqctl0; + u32 ddrctl_zqctl1; +}; + +struct ddrss_ddrctl_crc_params { + u32 ddrctl_crcparctl0; + u32 ddrctl_crcparctl1; + u32 ddrctl_crcparctl2; +}; + +struct ddrss_ddrctl_ecc_params { + u32 ddrctl_ecccfg0; +}; + +struct ddrss_ddrctl_map_params { + u32 ddrctl_addrmap0; + u32 ddrctl_addrmap1; + u32 ddrctl_addrmap2; + u32 ddrctl_addrmap3; + u32 ddrctl_addrmap4; + u32 ddrctl_addrmap5; + u32 ddrctl_addrmap6; + u32 ddrctl_addrmap7; + u32 ddrctl_addrmap8; + u32 ddrctl_addrmap9; + u32 ddrctl_addrmap10; + u32 ddrctl_addrmap11; + u32 ddrctl_dqmap0; + u32 ddrctl_dqmap1; + u32 ddrctl_dqmap4; + u32 ddrctl_dqmap5; +}; + +struct ddrss_ddrctl_pwr_params { + u32 ddrctl_pwrctl; +}; + +struct ddrss_ddrctl_timing_params { + u32 ddrctl_dramtmg0; + u32 ddrctl_dramtmg1; + u32 ddrctl_dramtmg2; + u32 ddrctl_dramtmg3; + u32 ddrctl_dramtmg4; + u32 ddrctl_dramtmg5; + u32 ddrctl_dramtmg6; + u32 ddrctl_dramtmg7; + u32 ddrctl_dramtmg8; + u32 ddrctl_dramtmg9; + u32 ddrctl_dramtmg11; + u32 ddrctl_dramtmg12; + u32 ddrctl_dramtmg13; + u32 ddrctl_dramtmg14; + u32 ddrctl_dramtmg15; + u32 ddrctl_dramtmg17; +}; + +struct ddrss_ddrphy_cfg_params { + u32 ddrphy_dcr; + u32 ddrphy_dsgcr; + u32 ddrphy_dx0gcr0; + u32 ddrphy_dx0gcr1; + u32 ddrphy_dx0gcr2; + u32 ddrphy_dx0gcr3; + u32 ddrphy_dx0gcr4; + u32 ddrphy_dx0gcr5; + u32 ddrphy_dx0gtr0; + u32 ddrphy_dx1gcr0; + u32 ddrphy_dx1gcr1; + u32 ddrphy_dx1gcr2; + u32 ddrphy_dx1gcr3; + u32 ddrphy_dx1gcr4; + u32 ddrphy_dx1gcr5; + u32 ddrphy_dx1gtr0; + u32 ddrphy_dx2gcr0; + u32 ddrphy_dx2gcr1; + u32 ddrphy_dx2gcr2; + u32 ddrphy_dx2gcr3; + u32 ddrphy_dx2gcr4; + u32 ddrphy_dx2gcr5; + u32 ddrphy_dx2gtr0; + u32 ddrphy_dx3gcr0; + u32 ddrphy_dx3gcr1; + u32 ddrphy_dx3gcr2; + u32 ddrphy_dx3gcr3; + u32 ddrphy_dx3gcr4; + u32 ddrphy_dx3gcr5; + u32 ddrphy_dx3gtr0; + u32 ddrphy_dx4gcr0; + u32 ddrphy_dx4gcr1; + u32 ddrphy_dx4gcr2; + u32 ddrphy_dx4gcr3; + u32 ddrphy_dx4gcr4; + u32 ddrphy_dx4gcr5; + u32 ddrphy_dx4gtr0; + u32 ddrphy_dx8sl0dxctl2; + u32 ddrphy_dx8sl0iocr; + u32 ddrphy_dx8sl0pllcr0; + u32 ddrphy_dx8sl1dxctl2; + u32 ddrphy_dx8sl1iocr; + u32 ddrphy_dx8sl1pllcr0; + u32 ddrphy_dx8sl2dxctl2; + u32 ddrphy_dx8sl2iocr; + u32 ddrphy_dx8sl2pllcr0; + u32 ddrphy_dxccr; + u32 ddrphy_odtcr; + u32 ddrphy_pgcr0; + u32 ddrphy_pgcr1; + u32 ddrphy_pgcr2; + u32 ddrphy_pgcr3; + u32 ddrphy_pgcr5; + u32 ddrphy_pgcr6; +}; + +struct ddrss_ddrphy_ctrl_params { + u32 ddrphy_dtcr0; + u32 ddrphy_dtcr1; + u32 ddrphy_mr0; + u32 ddrphy_mr1; + u32 ddrphy_mr2; + u32 ddrphy_mr3; + u32 ddrphy_mr4; + u32 ddrphy_mr5; + u32 ddrphy_mr6; + u32 ddrphy_mr11; + u32 ddrphy_mr12; + u32 ddrphy_mr13; + u32 ddrphy_mr14; + u32 ddrphy_mr22; + u32 ddrphy_pllcr0; + u32 ddrphy_vtcr0; +}; + +struct ddrss_ddrphy_ioctl_params { + u32 ddrphy_aciocr5; + u32 ddrphy_iovcr0; +}; + +struct ddrss_ddrphy_timing_params { + u32 ddrphy_dtpr0; + u32 ddrphy_dtpr1; + u32 ddrphy_dtpr2; + u32 ddrphy_dtpr3; + u32 ddrphy_dtpr4; + u32 ddrphy_dtpr5; + u32 ddrphy_dtpr6; + u32 ddrphy_ptr2; + u32 ddrphy_ptr3; + u32 ddrphy_ptr4; + u32 ddrphy_ptr5; + u32 ddrphy_ptr6; +}; + +struct ddrss_ddrphy_zq_params { + u32 ddrphy_zq0pr0; + u32 ddrphy_zq1pr0; + u32 ddrphy_zqcr; +}; + +struct ddrss_params { + struct ddrss_ddrctl_reg_params ctl_reg; + struct ddrss_ddrctl_crc_params ctl_crc; + struct ddrss_ddrctl_ecc_params ctl_ecc; + struct ddrss_ddrctl_map_params ctl_map; + struct ddrss_ddrctl_pwr_params ctl_pwr; + struct ddrss_ddrctl_timing_params ctl_timing; + struct ddrss_ddrphy_cfg_params phy_cfg; + struct ddrss_ddrphy_ctrl_params phy_ctrl; + struct ddrss_ddrphy_ioctl_params phy_ioctl; + struct ddrss_ddrphy_timing_params phy_timing; + struct ddrss_ddrphy_zq_params phy_zq; +}; + +#endif /* __K3_AM654_DDRSS_H */ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 0000000000..95507b593c --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 0000000000..b413f499d0 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + * Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL1 0x0000 +#define DDRPHY_PLL2 0x0004 +#define DDRPHY_PLL3 0x0008 +#define DDRPHY_PLL4 0x000c +#define DDRPHY_PLL5 0x0010 +#define DDRPHY_PLL7 0x0018 +#define DDRPHY_B0_DLL_ARPI0 0x0080 +#define DDRPHY_B0_DLL_ARPI1 0x0084 +#define DDRPHY_B0_DLL_ARPI2 0x0088 +#define DDRPHY_B0_DLL_ARPI3 0x008c +#define DDRPHY_B0_DLL_ARPI4 0x0090 +#define DDRPHY_B0_DLL_ARPI5 0x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI0 0x0100 +#define DDRPHY_B1_DLL_ARPI1 0x0104 +#define DDRPHY_B1_DLL_ARPI2 0x0108 +#define DDRPHY_B1_DLL_ARPI3 0x010c +#define DDRPHY_B1_DLL_ARPI4 0x0110 +#define DDRPHY_B1_DLL_ARPI5 0x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI0 0x0180 +#define DDRPHY_CA_DLL_ARPI1 0x0184 +#define DDRPHY_CA_DLL_ARPI2 0x0188 +#define DDRPHY_CA_DLL_ARPI3 0x018c +#define DDRPHY_CA_DLL_ARPI4 0x0190 +#define DDRPHY_CA_DLL_ARPI5 0x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT 0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD2 0x0d08 +#define DDRPHY_SHU1_CA_CMD4 0x0d10 +#define DDRPHY_SHU1_CA_CMD5 0x0d14 +#define DDRPHY_SHU1_CA_CMD6 0x0d18 +#define DDRPHY_SHU1_CA_CMD7 0x0d1c +#define DDRPHY_SHU1_PLL0 0x0d80 +#define DDRPHY_SHU1_PLL1 0x0d84 +#define DDRPHY_SHU1_PLL4 0x0d90 +#define DDRPHY_SHU1_PLL5 0x0d94 +#define DDRPHY_SHU1_PLL6 0x0d98 +#define DDRPHY_SHU1_PLL7 0x0d9C +#define DDRPHY_SHU1_PLL8 0x0da0 +#define DDRPHY_SHU1_PLL9 0x0da4 +#define DDRPHY_SHU1_PLL10 0x0da8 +#define DDRPHY_SHU1_PLL11 0x0dac +#define DDRPHY_SHU1_R0_B0_DQ2 0x0e08 +#define DDRPHY_SHU1_R0_B0_DQ3 0x0e0c +#define DDRPHY_SHU1_R0_B0_DQ4 0x0e10 +#define DDRPHY_SHU1_R0_B0_DQ5 0x0e14 +#define DDRPHY_SHU1_R0_B0_DQ6 0x0e18 +#define DDRPHY_SHU1_R0_B0_DQ7 0x0e1c +#define DDRPHY_SHU1_R0_B1_DQ2 0x0e58 +#define DDRPHY_SHU1_R0_B1_DQ3 0x0e5c +#define DDRPHY_SHU1_R0_B1_DQ4 0x0e60 +#define DDRPHY_SHU1_R0_B1_DQ5 0x0e64 +#define DDRPHY_SHU1_R0_B1_DQ6 0x0e68 +#define DDRPHY_SHU1_R0_B1_DQ7 0x0e6c +#define DDRPHY_SHU1_R0_CA_CMD9 0x0ec4 +#define DDRPHY_SHU1_R1_B0_DQ2 0x0f08 +#define DDRPHY_SHU1_R1_B0_DQ3 0x0f0c +#define DDRPHY_SHU1_R1_B0_DQ4 0x0f10 +#define DDRPHY_SHU1_R1_B0_DQ5 0x0f14 +#define DDRPHY_SHU1_R1_B0_DQ6 0x0f18 +#define DDRPHY_SHU1_R1_B0_DQ7 0x0f1c +#define DDRPHY_SHU1_R1_B1_DQ2 0x0f58 +#define DDRPHY_SHU1_R1_B1_DQ3 0x0f5c +#define DDRPHY_SHU1_R1_B1_DQ4 0x0f60 +#define DDRPHY_SHU1_R1_B1_DQ5 0x0f64 +#define DDRPHY_SHU1_R1_B1_DQ6 0x0f68 +#define DDRPHY_SHU1_R1_B1_DQ7 0x0f6c +#define DDRPHY_SHU1_R1_CA_CMD9 0x0fc4 + +/* DRAMC */ +#define DRAMC_DDRCONF0 0x0000 +#define DRAMC_DRAMCTRL 0x0004 +#define DRAMC_MISCTL0 0x0008 +#define DRAMC_PERFCTL0 0x000c +#define DRAMC_ARBCTL 0x0010 +#define DRAMC_RSTMASK 0x001c +#define DRAMC_PADCTRL 0x0020 +#define DRAMC_CKECTRL 0x0024 +#define DRAMC_RKCFG 0x0034 +#define DRAMC_DRAMC_PD_CTRL 0x0038 +#define DRAMC_CLKAR 0x003c +#define DRAMC_CLKCTRL 0x0040 +#define DRAMC_SREFCTRL 0x0048 +#define DRAMC_REFCTRL0 0x004c +#define DRAMC_REFCTRL1 0x0050 +#define DRAMC_REFRATRE_FILTER 0x0054 +#define DRAMC_ZQCS 0x0058 +#define DRAMC_MRS 0x005c +#define DRAMC_SPCMD 0x0060 +#define DRAMC_SPCMDCTRL 0x0064 +#define DRAMC_HW_MRR_FUN 0x0074 +#define DRAMC_TEST2_1 0x0094 +#define DRAMC_TEST2_2 0x0098 +#define DRAMC_TEST2_3 0x009c +#define DRAMC_TEST2_4 0x00a0 +#define DRAMC_CATRAINING1 0x00b0 +#define DRAMC_DUMMY_RD 0x00d0 +#define DRAMC_SHUCTRL 0x00d4 +#define DRAMC_SHUCTRL2 0x00dc +#define DRAMC_STBCAL 0x0200 +#define DRAMC_STBCAL1 0x0204 +#define DRAMC_EYESCAN 0x020c +#define DRAMC_DVFSDLL 0x0210 +#define DRAMC_SHU_ACTIM0 0x0800 +#define DRAMC_SHU_ACTIM1 0x0804 +#define DRAMC_SHU_ACTIM2 0x0808 +#define DRAMC_SHU_ACTIM3 0x080c +#define DRAMC_SHU_ACTIM4 0x0810 +#define DRAMC_SHU_ACTIM5 0x0814 +#define DRAMC_SHU_ACTIM_XRT 0x081c +#define DRAMC_SHU_AC_TIME_05T 0x0820 +#define DRAMC_SHU_CONF0 0x0840 +#define DRAMC_SHU_CONF1 0x0844 +#define DRAMC_SHU_CONF2 0x0848 +#define DRAMC_SHU_CONF3 0x084c +#define DRAMC_SHU_RANKCTL 0x0858 +#define DRAMC_SHU_CKECTRL 0x085c +#define DRAMC_SHU_ODTCTRL 0x0860 +#define DRAMC_SHU_PIPE 0x0878 +#define DRAMC_SHU_SELPH_CA1 0x0880 +#define DRAMC_SHU_SELPH_CA2 0x0884 +#define DRAMC_SHU_SELPH_CA3 0x0888 +#define DRAMC_SHU_SELPH_CA4 0x088c +#define DRAMC_SHU_SELPH_CA5 0x0890 +#define DRAMC_SHU_SELPH_CA6 0x0894 +#define DRAMC_SHU_SELPH_CA7 0x0898 +#define DRAMC_SHU_SELPH_CA8 0x089c +#define DRAMC_SHU_SELPH_DQS0 0x08a0 +#define DRAMC_SHU_SELPH_DQS1 0x08a4 +#define DRAMC_SHU1_DRVING1 0x08a8 +#define DRAMC_SHU1_DRVING2 0x08ac +#define DRAMC_SHU1_WODT 0x08c0 +#define DRAMC_SHU_SCINTV 0x08c8 +#define DRAMC_SHURK0_DQSCTL 0x0a00 +#define DRAMC_SHURK0_DQSIEN 0x0a04 +#define DRAMC_SHURK0_SELPH_ODTEN0 0x0a1c +#define DRAMC_SHURK0_SELPH_ODTEN1 0x0a20 +#define DRAMC_SHURK0_SELPH_DQSG0 0x0a24 +#define DRAMC_SHURK0_SELPH_DQSG1 0x0a28 +#define DRAMC_SHURK0_SELPH_DQ0 0x0a2c +#define DRAMC_SHURK0_SELPH_DQ1 0x0a30 +#define DRAMC_SHURK0_SELPH_DQ2 0x0a34 +#define DRAMC_SHURK0_SELPH_DQ3 0x0a38 +#define DRAMC_SHURK1_DQSCTL 0x0b00 +#define DRAMC_SHURK1_SELPH_ODTEN0 0x0b1c +#define DRAMC_SHURK1_SELPH_ODTEN1 0x0b20 +#define DRAMC_SHURK1_SELPH_DQSG0 0x0b24 +#define DRAMC_SHURK1_SELPH_DQSG1 0x0b28 +#define DRAMC_SHURK1_SELPH_DQ0 0x0b2c +#define DRAMC_SHURK1_SELPH_DQ1 0x0b30 +#define DRAMC_SHURK1_SELPH_DQ2 0x0b34 +#define DRAMC_SHURK1_SELPH_DQ3 0x0b38 +#define DRAMC_SHURK2_SELPH_ODTEN0 0x0c1c +#define DRAMC_SHURK2_SELPH_ODTEN1 0x0c20 +#define DRAMC_SHU_DQSG_RETRY 0x0c54 + +#define EMI_COL_ADDR_MASK GENMASK(13, 12) +#define EMI_COL_ADDR_SHIFT 12 +#define WALKING_PATTERN 0x12345678 +#define WALKING_STEP 0x4000000 + +struct mtk_ddr3_priv { + fdt_addr_t emi; + fdt_addr_t ddrphy; + fdt_addr_t dramc_ao; + struct clk phy; + struct clk phy_mux; + struct clk mem; + struct clk mem_mux; +}; + +#ifdef CONFIG_SPL_BUILD +static int mtk_ddr3_rank_size_detect(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + int step; + u32 start, test; + + /* To detect size, we have to make sure it's single rank + * and it has maximum addressing region + */ + + writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); + + if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN) + return -EINVAL; + + for (step = 0; step < 5; step++) { + writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + + (WALKING_STEP << step)); + + start = readl(CONFIG_SYS_SDRAM_BASE); + test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step)); + if ((test != ~WALKING_PATTERN) || test == start) + break; + } + + step = step ? step - 1 : 3; + clrsetbits_le32(priv->emi + EMI_CONA, EMI_COL_ADDR_MASK, + step << EMI_COL_ADDR_SHIFT); + + return 0; +} + +static int mtk_ddr3_init(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_set_parent(&priv->phy, &priv->phy_mux); + if (ret) + return ret; + + /* EMI Setting */ + writel(0x00003010, priv->emi + EMI_CONA); + writel(0x00000000, priv->emi + EMI_CONF); + writel(0x000006b8, priv->emi + EMI_CONM); + /* DQS */ + writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1); + /* Clock */ + writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2); + + /* DDRPHY setting */ + writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); + writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5); + writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5); + writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2); + writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2); + writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); + + writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7); + writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); + writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); + writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2); + writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1); + writel(0x10, priv->ddrphy + DDRPHY_PLL3); + writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL); + writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0); + writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); + writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); + udelay(1); + + writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1); + writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4); + writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4); + writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3); + writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6); + writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2); + writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8); + writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1); + writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); + writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT); + writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); + + writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + writel(0x40000, priv->ddrphy + DDRPHY_PLL4); + writel(0x0, priv->ddrphy + DDRPHY_PLL1); + writel(0x0, priv->ddrphy + DDRPHY_PLL2); + writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); + writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); + writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11); + writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0); + writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8); + writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10); + writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4); + writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6); + + writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5); + writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7); + + writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5); + writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7); + writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8); + writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10); + writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1); + writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4); + writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1); + writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1); + writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1); + writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3); + writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3); + writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4); + writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + writel(0x80010000, priv->ddrphy + DDRPHY_PLL1); + writel(0x80000000, priv->ddrphy + DDRPHY_PLL2); + udelay(100); + + writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); + writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); + writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); + writel(0xd0000, priv->ddrphy + DDRPHY_PLL4); + udelay(1); + + writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); + writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); + writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); + udelay(1); + + writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); + writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); + writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x80000000, priv->ddrphy + DDRPHY_PLL1); + udelay(1); + + writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); + udelay(1); + + writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); + udelay(1); + + writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); + udelay(1); + + ret = clk_set_parent(&priv->mem, &priv->mem_mux); + if (ret) + return ret; + + /* DDR PHY PLL setting */ + writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8); + writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7); + writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7); + writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7); + writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2); + + /* Update initial setting */ + writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3); + writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3); + writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6); + writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6); + writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6); + writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2); + writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2); + writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8); + writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); + writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); + writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); + writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); + writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR); + writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0); + + /* Dramc setting PC3 */ + writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); + + writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); + writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY); + writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2); + writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL); + writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0); + writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0); + writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0); + writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL); + writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL); + writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE); + writel(0x731004, priv->dramc_ao + DRAMC_RKCFG); + writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2); + writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL); + writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1); + writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER); + + /* Update PCDDR3 default setting */ + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4); + writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5); + writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7); + writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9); + writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); + writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2); + writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7); + writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0); + writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1); + writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0); + writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1); + writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0); + writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1); + writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1); + writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); + writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); + writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0); + writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4); + writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5); + writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6); + writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL); + writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL); + writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL); + writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0); + writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1); + writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2); + writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3); + writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4); + writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5); + writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT); + writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T); + writel(0x80010000, priv->ddrphy + DDRPHY_PLL2); + udelay(500); + + writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0); + writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0); + writel(0x80, priv->dramc_ao + DRAMC_ARBCTL); + writel(0x9, priv->dramc_ao + DRAMC_PADCTRL); + writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); + writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x731414, priv->dramc_ao + DRAMC_RKCFG); + writel(0x733414, priv->dramc_ao + DRAMC_RKCFG); + udelay(20); + + writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL); + udelay(100); + + writel(0x400000, priv->dramc_ao + DRAMC_MRS); + writel(0x401800, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x601800, priv->dramc_ao + DRAMC_MRS); + writel(0x600000, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x200000, priv->dramc_ao + DRAMC_MRS); + writel(0x200400, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x400, priv->dramc_ao + DRAMC_MRS); + writel(0x1d7000, priv->dramc_ao + DRAMC_MRS); + writel(0x1, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + udelay(100); + + writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x10, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + writel(0x20, priv->dramc_ao + DRAMC_SPCMD); + writel(0x0, priv->dramc_ao + DRAMC_SPCMD); + writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN); + writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); + writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3); + writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1); + writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL); + writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); + writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1); + writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1); + writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2); + writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3); + writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2); + writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL); + writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD); + writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4); + writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1); + writel(0x0, priv->dramc_ao + DRAMC_RSTMASK); + writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL); + writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); + + /* Apply config before calibration */ + writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); + writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); + writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); + writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV); + writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3); + writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); + writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); + writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT); + writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); + writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); + writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); + writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); + + /* Write leveling */ + writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); + writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); + + /* RX dqs gating cal */ + writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); + writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); + writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN); + + /* RX window per-bit cal */ + writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); + writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); + writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); + writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); + writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); + writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); + writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); + writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); + + /* RX datlat cal */ + writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1); + + /* TX window per-byte with 2UI cal */ + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); + writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); + writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); + writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); + writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); + writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); + + return mtk_ddr3_rank_size_detect(dev); +} +#endif + +static int mtk_ddr3_probe(struct udevice *dev) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + + priv->emi = dev_read_addr_index(dev, 0); + if (priv->emi == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->ddrphy = dev_read_addr_index(dev, 1); + if (priv->ddrphy == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->dramc_ao = dev_read_addr_index(dev, 2); + if (priv->dramc_ao == FDT_ADDR_T_NONE) + return -EINVAL; + +#ifdef CONFIG_SPL_BUILD + int ret; + + ret = clk_get_by_index(dev, 0, &priv->phy); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &priv->phy_mux); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 2, &priv->mem); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 3, &priv->mem_mux); + if (ret) + return ret; + + ret = mtk_ddr3_init(dev); + if (ret) + return ret; +#endif + return 0; +} + +static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info) +{ + struct mtk_ddr3_priv *priv = dev_get_priv(dev); + u32 val = readl(priv->emi + EMI_CONA); + + info->base = CONFIG_SYS_SDRAM_BASE; + + switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) { + case 0: + info->size = SZ_128M; + break; + case 1: + info->size = SZ_256M; + break; + case 2: + info->size = SZ_512M; + break; + case 3: + info->size = SZ_1G; + break; + default: + return -EINVAL; + } + + return 0; +} + +static struct ram_ops mtk_ddr3_ops = { + .get_info = mtk_ddr3_get_info, +}; + +static const struct udevice_id mtk_ddr3_ids[] = { + { .compatible = "mediatek,mt7629-dramc" }, + { } +}; + +U_BOOT_DRIVER(mediatek_ddr3) = { + .name = "mediatek_ddr3", + .id = UCLASS_RAM, + .of_match = mtk_ddr3_ids, + .ops = &mtk_ddr3_ops, + .probe = mtk_ddr3_probe, + .priv_auto_alloc_size = sizeof(struct mtk_ddr3_priv), +}; diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 4968900211..df7b988703 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 3774abfa98..fdd500aa47 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 8bafd17f8f..53835a9cd0 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ @@ -49,7 +49,7 @@ struct rk322x_sdram_params { struct regmap *map; }; -#ifdef CONFIG_TPL_BUILD +#ifdef CONFIG_SPL_BUILD /* * [7:6] bank(n:n bit bank) * [5:4] row(13+n) @@ -750,7 +750,7 @@ static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev) return 0; } -#endif /* CONFIG_TPL_BUILD */ +#endif /* CONFIG_SPL_BUILD */ #if CONFIG_IS_ENABLED(OF_PLATDATA) static int conv_of_platdata(struct udevice *dev) @@ -778,7 +778,7 @@ static int conv_of_platdata(struct udevice *dev) static int rk322x_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_TPL_BUILD +#ifdef CONFIG_SPL_BUILD struct rk322x_sdram_params *plat = dev_get_platdata(dev); int ret; struct udevice *dev_clk; @@ -786,7 +786,7 @@ static int rk322x_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -#ifdef CONFIG_TPL_BUILD +#ifdef CONFIG_SPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -842,12 +842,12 @@ U_BOOT_DRIVER(dmc_rk322x) = { .id = UCLASS_RAM, .of_match = rk322x_dmc_ids, .ops = &rk322x_dmc_ops, -#ifdef CONFIG_TPL_BUILD +#ifdef CONFIG_SPL_BUILD .ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata, #endif .probe = rk322x_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_TPL_BUILD +#ifdef CONFIG_SPL_BUILD .platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params), #endif }; diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index bb3cf48788..d1e52d84e7 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 89d95b4f89..e8b234d866 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 49ebd8809f..94dd01156a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * (C) Copyright 2016-2017 Rockchip Inc. * diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index bcc01b135e..fd0009b2e2 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -60,6 +60,16 @@ config RTC_ISL1208 This driver supports reading and writing the RTC/calendar and detects total power failures. +config RTC_RV3029 + bool "Enable RV3029 driver" + depends on DM_RTC + help + The MicroCrystal RV3029 is a I2C Real Time Clock (RTC) with 8-byte + battery-backed SRAM. + + This driver supports reading and writing the RTC/calendar and the + battery-baced SRAM section. + config RTC_RX8010SJ bool "Enable RX8010SJ driver" depends on DM_RTC @@ -94,4 +104,10 @@ config RTC_MC146818 clock with a wide array of features and 50 bytes of general-purpose, battery-backed RAM. The driver supports access to the clock and RAM. +config RTC_M41T62 + bool "Enable M41T62 driver" + help + Enable driver for ST's M41T62 compatible RTC devices (like RV-4162). + It is a serial (I2C) real-time clock (RTC) with alarm. + endmenu diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 137438389d..2ee7e00b02 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -15,6 +18,7 @@ #include #include +#include #include #include @@ -49,12 +53,8 @@ #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ -int rtc_get(struct rtc_time *tm) +static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) { - u8 buf[M41T62_DATETIME_REG_SIZE]; - - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); - debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", __FUNCTION__, @@ -77,20 +77,14 @@ int rtc_get(struct rtc_time *tm) __FUNCTION__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); - - return 0; } -int rtc_set(struct rtc_time *tm) +static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf) { - u8 buf[M41T62_DATETIME_REG_SIZE]; - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); - /* Merge time-data and register flags into buf[0..7] */ buf[M41T62_REG_SSEC] = 0; buf[M41T62_REG_SEC] = @@ -107,8 +101,99 @@ int rtc_set(struct rtc_time *tm) bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100); +} - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { +#ifdef CONFIG_DM_RTC +static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + int ret; + + ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); + if (ret) + return ret; + + m41t62_update_rtc_time(tm, buf); + + return 0; +} + +static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + int ret; + + ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); + if (ret) + return ret; + + m41t62_set_rtc_buf(tm, buf); + + ret = dm_i2c_write(dev, 0, buf, sizeof(buf)); + if (ret) { + printf("I2C write failed in %s()\n", __func__); + return ret; + } + + return 0; +} + +static int m41t62_rtc_reset(struct udevice *dev) +{ + u8 val; + + /* + * M41T82: Make sure HT (Halt Update) bit is cleared. + * This bit is 0 in M41T62 so its save to clear it always. + */ + + int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + + val &= ~M41T80_ALHOUR_HT; + ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + + return ret; +} + +static const struct rtc_ops m41t62_rtc_ops = { + .get = m41t62_rtc_get, + .set = m41t62_rtc_set, + .reset = m41t62_rtc_reset, +}; + +static const struct udevice_id m41t62_rtc_ids[] = { + { .compatible = "st,m41t62" }, + { .compatible = "microcrystal,rv4162" }, + { } +}; + +U_BOOT_DRIVER(rtc_m41t62) = { + .name = "rtc-m41t62", + .id = UCLASS_RTC, + .of_match = m41t62_rtc_ids, + .ops = &m41t62_rtc_ops, +}; + +#else /* NON DM RTC code - will be removed */ +int rtc_get(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + m41t62_update_rtc_time(tm, buf); + + return 0; +} + +int rtc_set(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + m41t62_set_rtc_buf(tm, buf); + + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, + M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; } @@ -128,3 +213,4 @@ void rtc_reset(void) val &= ~M41T80_ALHOUR_HT; i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } +#endif /* CONFIG_DM_RTC */ diff --git a/drivers/rtc/rtc-lib.c b/drivers/rtc/rtc-lib.c index b8a7a8b2d3..6528ddfebb 100644 --- a/drivers/rtc/rtc-lib.c +++ b/drivers/rtc/rtc-lib.c @@ -31,10 +31,14 @@ static int rtc_month_days(unsigned int month, unsigned int year) /* * rtc_to_tm - Converts u64 to rtc_time. * Convert seconds since 01-01-1970 00:00:00 to Gregorian date. + * + * This function is copied from rtc_time64_to_tm() in the Linux kernel. + * But in U-Boot January is month 1 and we do not subtract 1900 from the year. */ void rtc_to_tm(u64 time, struct rtc_time *tm) { - unsigned int month, year, secs, days; + unsigned int month, year, secs; + int days; days = div_u64_rem(time, 86400, &secs); diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index c676f0ff35..a0a238aedd 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -122,4 +122,5 @@ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value) UCLASS_DRIVER(rtc) = { .name = "rtc", .id = UCLASS_RTC, + .post_bind = dm_scan_fdt_dev, }; diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c index dd4d0607a8..38acb9c992 100644 --- a/drivers/rtc/rv3029.c +++ b/drivers/rtc/rv3029.c @@ -1,189 +1,495 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de + * (C) Copyright 2018 Theobroma Systems Design und Consulting GmbH + * + * Based on a the Linux rtc-rv3029c2.c driver written by: + * Gregory Hermant + * Michael Buesch */ + #include #include +#include #include #include -#define RTC_RV3029_CTRL1 0x00 -#define RTC_RV3029_CTRL1_EERE (1 << 3) +#define RTC_RV3029_PAGE_LEN 7 -#define RTC_RV3029_CTRL_STATUS 0x03 -#define RTC_RV3029_CTRLS_EEBUSY (1 << 7) +/* control section */ +#define RV3029_ONOFF_CTRL 0x00 +#define RV3029_ONOFF_CTRL_WE BIT(0) +#define RV3029_ONOFF_CTRL_TE BIT(1) +#define RV3029_ONOFF_CTRL_TAR BIT(2) +#define RV3029_ONOFF_CTRL_EERE BIT(3) +#define RV3029_ONOFF_CTRL_SRON BIT(4) +#define RV3029_ONOFF_CTRL_TD0 BIT(5) +#define RV3029_ONOFF_CTRL_TD1 BIT(6) +#define RV3029_ONOFF_CTRL_CLKINT BIT(7) +#define RV3029_IRQ_CTRL 0x01 +#define RV3029_IRQ_CTRL_AIE BIT(0) +#define RV3029_IRQ_CTRL_TIE BIT(1) +#define RV3029_IRQ_CTRL_V1IE BIT(2) +#define RV3029_IRQ_CTRL_V2IE BIT(3) +#define RV3029_IRQ_CTRL_SRIE BIT(4) +#define RV3029_IRQ_FLAGS 0x02 +#define RV3029_IRQ_FLAGS_AF BIT(0) +#define RV3029_IRQ_FLAGS_TF BIT(1) +#define RV3029_IRQ_FLAGS_V1IF BIT(2) +#define RV3029_IRQ_FLAGS_V2IF BIT(3) +#define RV3029_IRQ_FLAGS_SRF BIT(4) +#define RV3029_STATUS 0x03 +#define RV3029_STATUS_VLOW1 BIT(2) +#define RV3029_STATUS_VLOW2 BIT(3) +#define RV3029_STATUS_SR BIT(4) +#define RV3029_STATUS_PON BIT(5) +#define RV3029_STATUS_EEBUSY BIT(7) +#define RV3029_RST_CTRL 0x04 +#define RV3029_RST_CTRL_SYSR BIT(4) +#define RV3029_CONTROL_SECTION_LEN 0x05 -#define RTC_RV3029_CTRL_RESET 0x04 -#define RTC_RV3029_CTRL_SYS_R (1 << 4) +/* watch section */ +#define RV3029_W_SEC 0x08 +#define RV3029_W_MINUTES 0x09 +#define RV3029_W_HOURS 0x0A +#define RV3029_REG_HR_12_24 BIT(6) /* 24h/12h mode */ +#define RV3029_REG_HR_PM BIT(5) /* PM/AM bit in 12h mode */ +#define RV3029_W_DATE 0x0B +#define RV3029_W_DAYS 0x0C +#define RV3029_W_MONTHS 0x0D +#define RV3029_W_YEARS 0x0E -#define RTC_RV3029_CLOCK_PAGE 0x08 -#define RTC_RV3029_PAGE_LEN 7 +/* eeprom control section */ +#define RV3029_CONTROL_E2P_EECTRL 0x30 +#define RV3029_TRICKLE_1K BIT(4) /* 1.5K resistance */ +#define RV3029_TRICKLE_5K BIT(5) /* 5K resistance */ +#define RV3029_TRICKLE_20K BIT(6) /* 20K resistance */ +#define RV3029_TRICKLE_80K BIT(7) /* 80K resistance */ +#define RV3029_TRICKLE_MASK (RV3029_TRICKLE_1K |\ + RV3029_TRICKLE_5K |\ + RV3029_TRICKLE_20K |\ + RV3029_TRICKLE_80K) +#define RV3029_TRICKLE_SHIFT 4 -#define RV3029C2_W_SECONDS 0x00 -#define RV3029C2_W_MINUTES 0x01 -#define RV3029C2_W_HOURS 0x02 -#define RV3029C2_W_DATE 0x03 -#define RV3029C2_W_DAYS 0x04 -#define RV3029C2_W_MONTHS 0x05 -#define RV3029C2_W_YEARS 0x06 -#define RV3029C2_REG_HR_12_24 (1 << 6) /* 24h/12h mode */ -#define RV3029C2_REG_HR_PM (1 << 5) /* PM/AM bit in 12h mode */ - -#define RTC_RV3029_EEPROM_CTRL 0x30 -#define RTC_RV3029_TRICKLE_1K (1 << 4) -#define RTC_RV3029_TRICKLE_5K (1 << 5) -#define RTC_RV3029_TRICKLE_20K (1 << 6) -#define RTC_RV3029_TRICKLE_80K (1 << 7) - -int rtc_get( struct rtc_time *tmp ) +static int rv3029_rtc_get(struct udevice *dev, struct rtc_time *tm) { - int ret; - unsigned char buf[RTC_RV3029_PAGE_LEN]; + u8 regs[RTC_RV3029_PAGE_LEN]; + int ret; - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1, buf, \ - RTC_RV3029_PAGE_LEN); - if (ret) { + ret = dm_i2c_read(dev, RV3029_W_SEC, regs, sizeof(regs)); + if (ret < 0) { printf("%s: error reading RTC: %x\n", __func__, ret); - return -1; + return -EIO; } - tmp->tm_sec = bcd2bin( buf[RV3029C2_W_SECONDS] & 0x7f); - tmp->tm_min = bcd2bin( buf[RV3029C2_W_MINUTES] & 0x7f); - if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_12_24) { - /* 12h format */ - tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x1f); - if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_PM) - /* PM flag set */ - tmp->tm_hour += 12; - } else - tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x3f); - tmp->tm_mday = bcd2bin( buf[RV3029C2_W_DATE] & 0x3F ); - tmp->tm_mon = bcd2bin( buf[RV3029C2_W_MONTHS] & 0x1F ); - tmp->tm_wday = bcd2bin( buf[RV3029C2_W_DAYS] & 0x07 ); + tm->tm_sec = bcd2bin(regs[RV3029_W_SEC - RV3029_W_SEC]); + tm->tm_min = bcd2bin(regs[RV3029_W_MINUTES - RV3029_W_SEC]); + + /* HR field has a more complex interpretation */ + { + const u8 _hr = regs[RV3029_W_HOURS - RV3029_W_SEC]; + + if (_hr & RV3029_REG_HR_12_24) { + /* 12h format */ + tm->tm_hour = bcd2bin(_hr & 0x1f); + if (_hr & RV3029_REG_HR_PM) /* PM flag set */ + tm->tm_hour += 12; + } else { + /* 24h format */ + tm->tm_hour = bcd2bin(_hr & 0x3f); + } + } + + tm->tm_mday = bcd2bin(regs[RV3029_W_DATE - RV3029_W_SEC]); + tm->tm_mon = bcd2bin(regs[RV3029_W_MONTHS - RV3029_W_SEC]) - 1; /* RTC supports only years > 1999 */ - tmp->tm_year = bcd2bin( buf[RV3029C2_W_YEARS]) + 2000; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; + tm->tm_year = bcd2bin(regs[RV3029_W_YEARS - RV3029_W_SEC]) + 2000; + tm->tm_wday = bcd2bin(regs[RV3029_W_DAYS - RV3029_W_SEC]) - 1; - debug( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); + tm->tm_yday = 0; + tm->tm_isdst = 0; + + debug("%s: %4d-%02d-%02d (wday=%d) %2d:%02d:%02d\n", + __func__, tm->tm_year, tm->tm_mon, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); return 0; } -int rtc_set( struct rtc_time *tmp ) +static int rv3029_rtc_set(struct udevice *dev, const struct rtc_time *tm) { - int ret; - unsigned char buf[RTC_RV3029_PAGE_LEN]; + u8 regs[RTC_RV3029_PAGE_LEN]; - debug( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + debug("%s: %4d-%02d-%02d (wday=%d( %2d:%02d:%02d\n", + __func__, tm->tm_year, tm->tm_mon, tm->tm_mday, + tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); - if (tmp->tm_year < 2000) { - printf("RTC: year %d < 2000 not possible\n", tmp->tm_year); - return -1; + + if (tm->tm_year < 2000) { + printf("%s: year %d (before 2000) not supported\n", + __func__, tm->tm_year); + return -EINVAL; } - buf[RV3029C2_W_SECONDS] = bin2bcd(tmp->tm_sec); - buf[RV3029C2_W_MINUTES] = bin2bcd(tmp->tm_min); - buf[RV3029C2_W_HOURS] = bin2bcd(tmp->tm_hour); - /* set 24h format */ - buf[RV3029C2_W_HOURS] &= ~RV3029C2_REG_HR_12_24; - buf[RV3029C2_W_DATE] = bin2bcd(tmp->tm_mday); - buf[RV3029C2_W_DAYS] = bin2bcd(tmp->tm_wday); - buf[RV3029C2_W_MONTHS] = bin2bcd(tmp->tm_mon); - tmp->tm_year -= 2000; - buf[RV3029C2_W_YEARS] = bin2bcd(tmp->tm_year); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1, - buf, RTC_RV3029_PAGE_LEN); - /* give the RTC some time to update */ - udelay(1000); - return ret; + regs[RV3029_W_SEC - RV3029_W_SEC] = bin2bcd(tm->tm_sec); + regs[RV3029_W_MINUTES - RV3029_W_SEC] = bin2bcd(tm->tm_min); + regs[RV3029_W_HOURS - RV3029_W_SEC] = bin2bcd(tm->tm_hour); + regs[RV3029_W_DATE - RV3029_W_SEC] = bin2bcd(tm->tm_mday); + regs[RV3029_W_MONTHS - RV3029_W_SEC] = bin2bcd(tm->tm_mon + 1); + regs[RV3029_W_DAYS - RV3029_W_SEC] = bin2bcd(tm->tm_wday + 1) & 0x7; + regs[RV3029_W_YEARS - RV3029_W_SEC] = bin2bcd(tm->tm_year - 2000); + + return dm_i2c_write(dev, RV3029_W_SEC, regs, sizeof(regs)); } -/* sets EERE-Bit (automatic EEPROM refresh) */ -static void set_eere_bit(int state) +static int rv3029_rtc_reset(struct udevice *dev) { - unsigned char reg_ctrl1; + u8 ctrl = RV3029_RST_CTRL_SYSR; + unsigned long start; + const unsigned long timeout_ms = 10000; + int ret; - (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1, - ®_ctrl1, 1); + /* trigger the system-reset */ + ret = dm_i2c_write(dev, RV3029_RST_CTRL, &ctrl, 1); + if (ret < 0) + return -EIO; - if (state) - reg_ctrl1 |= RTC_RV3029_CTRL1_EERE; - else - reg_ctrl1 &= (~RTC_RV3029_CTRL1_EERE); + /* wait for the system-reset to complete */ + start = get_timer(0); + do { + if (get_timer(start) > timeout_ms) + return -ETIMEDOUT; - (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1, - ®_ctrl1, 1); + ret = dm_i2c_read(dev, RV3029_RST_CTRL, &ctrl, 1); + if (ret < 0) + return -EIO; + } while (ctrl & RV3029_RST_CTRL_SYSR); + + return 0; } -/* waits until EEPROM page is no longer busy (times out after 10ms*loops) */ -static int wait_eebusy(int loops) +static int rv3029_rtc_read8(struct udevice *dev, unsigned int reg) { - int i; - unsigned char ctrl_status; + u8 data; + int ret; - for (i = 0; i < loops; i++) { - (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_STATUS, - 1, &ctrl_status, 1); + ret = dm_i2c_read(dev, reg, &data, sizeof(data)); + return ret < 0 ? ret : data; +} - if ((ctrl_status & RTC_RV3029_CTRLS_EEBUSY) == 0) +static int rv3029_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + u8 data = val; + + return dm_i2c_write(dev, reg, &data, 1); +} + +#if defined(OF_CONTROL) +static int rv3029_get_sr(struct udevice *dev, u8 *buf) +{ + int ret = dm_i2c_read(dev, RV3029_STATUS, buf, 1); + + if (ret < 0) + return -EIO; + + dev_dbg(dev, "status = 0x%.2x (%d)\n", buf[0], buf[0]); + return 0; +} + +static int rv3029_set_sr(struct udevice *dev, u8 val) +{ + int ret; + + ret = dm_i2c_read(dev, RV3029_STATUS, &val, 1); + if (ret < 0) + return -EIO; + + dev_dbg(dev, "status = 0x%.2x (%d)\n", val, val); + return 0; +} + +static int rv3029_eeprom_busywait(struct udevice *dev) +{ + int i, ret; + u8 sr; + + for (i = 100; i > 0; i--) { + ret = rv3029_get_sr(dev, &sr); + if (ret < 0) + break; + if (!(sr & RV3029_STATUS_EEBUSY)) break; udelay(10000); } - return i; -} - -void rtc_reset (void) -{ - unsigned char buf[RTC_RV3029_PAGE_LEN]; - - buf[0] = RTC_RV3029_CTRL_SYS_R; - (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1, - buf, 1); - -#if defined(CONFIG_SYS_RV3029_TCR) - /* - * because EEPROM_CTRL register is in EEPROM page it is necessary to - * disable automatic EEPROM refresh and check if EEPROM is busy - * before EEPORM_CTRL register may be accessed - */ - set_eere_bit(0); - wait_eebusy(100); - /* read current trickle charger setting */ - (void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_EEPROM_CTRL, - 1, buf, 1); - /* enable automatic EEPROM refresh again */ - set_eere_bit(1); - - /* - * to minimize EEPROM access write trickle charger setting only if it - * differs from current value - */ - if ((buf[0] & 0xF0) != CONFIG_SYS_RV3029_TCR) { - buf[0] = (buf[0] & 0x0F) | CONFIG_SYS_RV3029_TCR; - /* - * write trickle charger setting (disable autom. EEPROM - * refresh and wait until EEPROM is idle) - */ - set_eere_bit(0); - wait_eebusy(100); - (void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, - RTC_RV3029_EEPROM_CTRL, 1, buf, 1); - /* - * it is necessary to wait 10ms before EEBUSY-Bit may be read - * (this is not documented in the data sheet yet, but the - * manufacturer recommends it) - */ - udelay(10000); - /* wait until EEPROM write access is finished */ - wait_eebusy(100); - set_eere_bit(1); + if (i <= 0) { + dev_err(dev, "EEPROM busy wait timeout.\n"); + return -ETIMEDOUT; } -#endif + + return ret; } + +static int rv3029_update_bits(struct udevice *dev, u8 reg, u8 mask, u8 set) +{ + u8 buf; + int ret; + + ret = dm_i2c_read(dev, reg, &buf, 1); + if (ret < 0) + return ret; + + if ((buf & mask) == (set && mask)) + return 0; + + buf = (buf & ~mask) | (set & mask); + ret = dm_i2c_read(dev, reg, &buf, 1); + if (ret < 0) + return ret; + + return 0; +} + +static int rv3029_eeprom_exit(struct udevice *dev) +{ + /* Re-enable eeprom refresh */ + return rv3029_update_bits(dev, RV3029_ONOFF_CTRL, + RV3029_ONOFF_CTRL_EERE, + RV3029_ONOFF_CTRL_EERE); +} + +static int rv3029_eeprom_enter(struct udevice *dev) +{ + int ret; + u8 sr; + + /* Check whether we are in the allowed voltage range. */ + ret = rv3029_get_sr(dev, &sr); + if (ret < 0) + return ret; + if (sr & (RV3029_STATUS_VLOW1 | RV3029_STATUS_VLOW2)) { + /* We clear the bits and retry once just in case + * we had a brown out in early startup. + */ + sr &= ~RV3029_STATUS_VLOW1; + sr &= ~RV3029_STATUS_VLOW2; + ret = rv3029_set_sr(dev, sr); + if (ret < 0) + return ret; + udelay(10000); + ret = rv3029_get_sr(dev, &sr); + if (ret < 0) + return ret; + if (sr & (RV3029_STATUS_VLOW1 | RV3029_STATUS_VLOW2)) { + dev_err(dev, "Supply voltage is too low to safely access the EEPROM.\n"); + return -ENODEV; + } + } + + /* Disable eeprom refresh. */ + ret = rv3029_update_bits(dev, + RV3029_ONOFF_CTRL, RV3029_ONOFF_CTRL_EERE, 0); + if (ret < 0) + return ret; + + /* Wait for any previous eeprom accesses to finish. */ + ret = rv3029_eeprom_busywait(dev); + if (ret < 0) + rv3029_eeprom_exit(dev); + + return ret; +} + +static int rv3029_eeprom_read(struct udevice *dev, u8 reg, + u8 buf[], size_t len) +{ + int ret, err; + + err = rv3029_eeprom_enter(dev); + if (err < 0) + return err; + + ret = dm_i2c_read(dev, reg, buf, len); + + err = rv3029_eeprom_exit(dev); + if (err < 0) + return err; + + return ret; +} + +static int rv3029_eeprom_write(struct udevice *dev, u8 reg, + u8 const buf[], size_t len) +{ + int ret; + size_t i; + u8 tmp; + + ret = rv3029_eeprom_enter(dev); + if (ret < 0) + return ret; + + for (i = 0; i < len; i++, reg++) { + ret = dm_i2c_read(dev, reg, &tmp, 1); + if (ret < 0) + break; + if (tmp != buf[i]) { + ret = dm_i2c_write(dev, reg, &buf[i], 1); + if (ret < 0) + break; + } + ret = rv3029_eeprom_busywait(dev); + if (ret < 0) + break; + } + + ret = rv3029_eeprom_exit(dev); + if (ret < 0) + return ret; + + return 0; +} + +static int rv3029_eeprom_update_bits(struct udevice *dev, + u8 reg, u8 mask, u8 set) +{ + u8 buf; + int ret; + + ret = rv3029_eeprom_read(dev, reg, &buf, 1); + if (ret < 0) + return ret; + + /* + * If the EEPROM already reads the correct bitpattern, we don't need + * to update it. + */ + if ((buf & mask) == (set & mask)) + return 0; + + buf = (buf & ~mask) | (set & mask); + ret = rv3029_eeprom_write(dev, reg, &buf, 1); + if (ret < 0) + return ret; + + return 0; +} + +static void rv3029_trickle_config(struct udevice *dev) +{ + static const struct rv3029_trickle_tab_elem { + u32 r; /* resistance in ohms */ + u8 conf; /* trickle config bits */ + } rv3029_trickle_tab[] = { + { + .r = 1076, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K | + RV3029_TRICKLE_20K | RV3029_TRICKLE_80K, + }, { + .r = 1091, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K | + RV3029_TRICKLE_20K, + }, { + .r = 1137, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K | + RV3029_TRICKLE_80K, + }, { + .r = 1154, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K, + }, { + .r = 1371, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K | + RV3029_TRICKLE_80K, + }, { + .r = 1395, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K, + }, { + .r = 1472, + .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_80K, + }, { + .r = 1500, + .conf = RV3029_TRICKLE_1K, + }, { + .r = 3810, + .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K | + RV3029_TRICKLE_80K, + }, { + .r = 4000, + .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K, + }, { + .r = 4706, + .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_80K, + }, { + .r = 5000, + .conf = RV3029_TRICKLE_5K, + }, { + .r = 16000, + .conf = RV3029_TRICKLE_20K | RV3029_TRICKLE_80K, + }, { + .r = 20000, + .conf = RV3029_TRICKLE_20K, + }, { + .r = 80000, + .conf = RV3029_TRICKLE_80K, + }, + }; + int err; + u32 ohms; + u8 trickle_set_bits = 0; + + /* Configure the trickle charger. */ + err = dev_read_u32(dev, "trickle-resistor-ohms", &ohms); + + if (!err) { + /* Find trickle-charger config */ + for (int i = 0; i < ARRAY_SIZE(rv3029_trickle_tab); i++) + if (rv3029_trickle_tab[i].r >= ohms) { + dev_dbg(dev, "trickle charger at %d ohms\n", + rv3029_trickle_tab[i].r); + trickle_set_bits = rv3029_trickle_tab[i].conf; + break; + } + } + + dev_dbg(dev, "trickle charger config 0x%x\n", trickle_set_bits); + err = rv3029_eeprom_update_bits(dev, RV3029_CONTROL_E2P_EECTRL, + RV3029_TRICKLE_MASK, + trickle_set_bits); + if (err < 0) + dev_dbg(dev, "failed to update trickle charger\n"); +} +#else +static inline void rv3029_trickle_config(struct udevice *dev) +{ +} +#endif + +static int rv3029_probe(struct udevice *dev) +{ + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | + DM_I2C_CHIP_WR_ADDRESS); + + rv3029_trickle_config(dev); + return 0; +} + +static const struct rtc_ops rv3029_rtc_ops = { + .get = rv3029_rtc_get, + .set = rv3029_rtc_set, + .read8 = rv3029_rtc_read8, + .write8 = rv3029_rtc_write8, + .reset = rv3029_rtc_reset, +}; + +static const struct udevice_id rv3029_rtc_ids[] = { + { .compatible = "mc,rv3029" }, + { .compatible = "mc,rv3029c2" }, + { } +}; + +U_BOOT_DRIVER(rtc_rv3029) = { + .name = "rtc-rv3029", + .id = UCLASS_RTC, + .probe = rv3029_probe, + .of_match = rv3029_rtc_ids, + .ops = &rv3029_rtc_ops, +}; diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index bc6ac8cd32..df47e2fc78 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -592,7 +592,6 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor)); memcpy(&bdesc->product, &bd.product, sizeof(bd.product)); memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision)); - part_init(bdesc); if (verbose) { printf(" Device %d: ", 0); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 597db4b9cb..b7ff2960ab 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SIFIVE + bool "SiFive UART" + help + Select this to enable a debug UART using the serial_sifive driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_STM32 bool "STMicroelectronics STM32" depends on STM32_SERIAL @@ -368,6 +375,16 @@ config DEBUG_UART_OMAP You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_MTK + bool "MediaTek High-speed UART" + depends on MTK_SERIAL + help + Select this to enable a debug UART using the MediaTek High-speed + UART driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + endchoice config DEBUG_UART_BASE @@ -496,7 +513,7 @@ config BCM283X_PL011_SERIAL config BCM6345_SERIAL bool "Support for BCM6345 UART" - depends on DM_SERIAL && ARCH_BMIPS + depends on DM_SERIAL help Select this to enable UART on BCM6345 SoCs. @@ -669,6 +686,12 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config SIFIVE_SERIAL + bool "SiFive UART support" + depends on DM_SERIAL + help + This driver supports the SiFive UART. If unsure say N. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI @@ -692,6 +715,16 @@ config ZYNQ_SERIAL This driver supports the Cadence UART. It is found e.g. in Xilinx Zynq/ZynqMP. +config MTK_SERIAL + bool "MediaTek High-speed UART support" + depends on DM_SERIAL + help + Select this to enable UART support for MediaTek High-speed UART + devices. This driver uses driver model and requires a device + tree binding to operate. + The High-speed UART is compatible with the ns16550a UART and have + its own high-speed registers. + config MPC8XX_CONS bool "Console driver for MPC8XX" depends on MPC8xx diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 03dc29ee2e..06ee30697d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -66,6 +66,8 @@ obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o +obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o +obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 61052a92d6..86c3de4e45 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -121,7 +121,6 @@ U_BOOT_DRIVER(altera_jtaguart) = { .platdata_auto_alloc_size = sizeof(struct altera_jtaguart_platdata), .probe = altera_jtaguart_probe, .ops = &altera_jtaguart_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_ALTERA_JTAGUART diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index b7b0a13ca1..67d47199aa 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -117,7 +117,6 @@ U_BOOT_DRIVER(altera_uart) = { .platdata_auto_alloc_size = sizeof(struct altera_uart_platdata), .probe = altera_uart_probe, .ops = &altera_uart_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_ALTERA_UART diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 43e8691a93..dfcb6fd698 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -155,7 +155,6 @@ U_BOOT_DRIVER(serial_dcc) = { .id = UCLASS_SERIAL, .of_match = arm_dcc_ids, .ops = &arm_dcc_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_ARM_DCC diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 9414f5f692..aa8cdff840 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -294,7 +294,9 @@ U_BOOT_DRIVER(serial_atmel) = { #endif .probe = atmel_serial_probe, .ops = &atmel_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif .priv_auto_alloc_size = sizeof(struct atmel_serial_priv), }; #endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index f9041aa626..560ca2ae34 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -148,10 +148,13 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) { - serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + /* to keep serial format, read lcr before writing BKSE */ + int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; + + serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); serial_out(baud_divisor & 0xff, &com_port->dll); serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(lcr_val, &com_port->lcr); } void NS16550_init(NS16550_t com_port, int baud_divisor) @@ -181,6 +184,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(UART_MCRVAL, &com_port->mcr); serial_out(ns16550_getfcr(com_port), &com_port->fcr); + /* initialize serial config to 8N1 before writing baudrate */ + serial_out(UART_LCRVAL, &com_port->lcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ @@ -334,6 +339,58 @@ static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) return 0; } +static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + int lcr_val = UART_LCR_WLS_8; + uint parity = SERIAL_GET_PARITY(serial_config); + uint bits = SERIAL_GET_BITS(serial_config); + uint stop = SERIAL_GET_STOP(serial_config); + + /* + * only parity config is implemented, check if other serial settings + * are the default one. + */ + if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP) + return -ENOTSUPP; /* not supported in driver*/ + + switch (parity) { + case SERIAL_PAR_NONE: + /* no bits to add */ + break; + case SERIAL_PAR_ODD: + lcr_val |= UART_LCR_PEN; + break; + case SERIAL_PAR_EVEN: + lcr_val |= UART_LCR_PEN | UART_LCR_EPS; + break; + default: + return -ENOTSUPP; /* not supported in driver*/ + } + + serial_out(lcr_val, &com_port->lcr); + return 0; +} + +static int ns16550_serial_getinfo(struct udevice *dev, + struct serial_device_info *info) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + struct ns16550_platdata *plat = com_port->plat; + + info->type = SERIAL_CHIP_16550_COMPATIBLE; +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + info->addr_space = SERIAL_ADDRESS_SPACE_IO; +#else + info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY; +#endif + info->addr = plat->base; + info->reg_width = plat->reg_width; + info->reg_shift = plat->reg_shift; + info->reg_offset = plat->reg_offset; + return 0; +} + int ns16550_serial_probe(struct udevice *dev) { struct NS16550 *const com_port = dev_get_priv(dev); @@ -368,7 +425,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) /* try Processor Local Bus device first */ addr = dev_read_addr(dev); -#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) +#if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI) if (addr == FDT_ADDR_T_NONE) { /* then try pci device */ struct fdt_pci_addr pci_addr; @@ -408,6 +465,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); + plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); err = clk_get_by_index(dev, 0, &clk); if (!err) { @@ -440,6 +498,8 @@ const struct dm_serial_ops ns16550_serial_ops = { .pending = ns16550_serial_pending, .getc = ns16550_serial_getc, .setbrg = ns16550_serial_setbrg, + .setconfig = ns16550_serial_setconfig, + .getinfo = ns16550_serial_getinfo, }; #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) @@ -473,7 +533,9 @@ U_BOOT_DRIVER(ns16550_serial) = { .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif #endif /* SERIAL_PRESENT */ diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 4a05ea44ce..33102fc872 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -163,6 +163,18 @@ DEBUG_UART_FUNCS #endif /* CONFIG_DEBUG_UART_SANDBOX */ +static int sandbox_serial_getconfig(struct udevice *dev, uint *serial_config) +{ + uint config = SERIAL_DEFAULT_CONFIG; + + if (!serial_config) + return -EINVAL; + + *serial_config = config; + + return 0; +} + static int sandbox_serial_setconfig(struct udevice *dev, uint serial_config) { u8 parity = SERIAL_GET_PARITY(serial_config); @@ -176,6 +188,26 @@ static int sandbox_serial_setconfig(struct udevice *dev, uint serial_config) return 0; } +static int sandbox_serial_getinfo(struct udevice *dev, + struct serial_device_info *serial_info) +{ + struct serial_device_info info = { + .type = SERIAL_CHIP_UNKNOWN, + .addr_space = SERIAL_ADDRESS_SPACE_IO, + .addr = SERIAL_DEFAULT_ADDRESS, + .reg_width = 1, + .reg_offset = 0, + .reg_shift = 0, + }; + + if (!serial_info) + return -EINVAL; + + *serial_info = info; + + return 0; +} + #if CONFIG_IS_ENABLED(OF_CONTROL) static const char * const ansi_colour[] = { "black", "red", "green", "yellow", "blue", "megenta", "cyan", @@ -207,7 +239,9 @@ static const struct dm_serial_ops sandbox_serial_ops = { .putc = sandbox_serial_putc, .pending = sandbox_serial_pending, .getc = sandbox_serial_getc, + .getconfig = sandbox_serial_getconfig, .setconfig = sandbox_serial_setconfig, + .getinfo = sandbox_serial_getinfo, }; static const struct udevice_id sandbox_serial_ids[] = { diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 665cca85cb..ffcd6d15af 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -62,7 +62,7 @@ static int serial_check_stdout(const void *blob, struct udevice **devp) * anyway. */ if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node), - devp)) { + devp, false)) { if (!device_probe(*devp)) return 0; } @@ -294,6 +294,20 @@ void serial_setbrg(void) ops->setbrg(gd->cur_serial_dev, gd->baudrate); } +int serial_getconfig(uint *config) +{ + struct dm_serial_ops *ops; + + if (!gd->cur_serial_dev) + return 0; + + ops = serial_get_ops(gd->cur_serial_dev); + if (ops->getconfig) + return ops->getconfig(gd->cur_serial_dev, config); + + return 0; +} + int serial_setconfig(uint config) { struct dm_serial_ops *ops; @@ -308,6 +322,25 @@ int serial_setconfig(uint config) return 0; } +int serial_getinfo(struct serial_device_info *info) +{ + struct dm_serial_ops *ops; + + if (!gd->cur_serial_dev) + return -ENODEV; + + if (!info) + return -EINVAL; + + info->baudrate = gd->baudrate; + + ops = serial_get_ops(gd->cur_serial_dev); + if (ops->getinfo) + return ops->getinfo(gd->cur_serial_dev, info); + + return -EINVAL; +} + void serial_stdio_init(void) { } @@ -419,12 +452,16 @@ static int serial_post_probe(struct udevice *dev) ops->pending += gd->reloc_off; if (ops->clear) ops->clear += gd->reloc_off; + if (ops->getconfig) + ops->getconfig += gd->reloc_off; if (ops->setconfig) ops->setconfig += gd->reloc_off; #if CONFIG_POST & CONFIG_SYS_POST_UART if (ops->loop) ops->loop += gd->reloc_off; #endif + if (ops->getinfo) + ops->getinfo += gd->reloc_off; #endif /* Set the baud rate */ if (ops->setbrg) { diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c499601f00..09365ba6a1 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -119,7 +119,6 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); serial_initfunc(atmel_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(mpc85xx_serial_initialize); -serial_initfunc(mpc8xx_serial_initialize); serial_initfunc(mxc_serial_initialize); serial_initfunc(ns16550_serial_initialize); serial_initfunc(pl01x_serial_initialize); @@ -173,7 +172,6 @@ void serial_initialize(void) atmel_serial_initialize(); mcf_serial_initialize(); mpc85xx_serial_initialize(); - mpc8xx_serial_initialize(); mxc_serial_initialize(); ns16550_serial_initialize(); pl01x_serial_initialize(); diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index e91a5f7b24..5249c55398 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -189,7 +189,6 @@ U_BOOT_DRIVER(serial_ar933x) = { .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv), .probe = ar933x_serial_probe, .ops = &ar933x_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_AR933X diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 925f0c2555..980b38d2a1 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -128,7 +128,6 @@ U_BOOT_DRIVER(serial_arc) = { .ofdata_to_platdata = arc_serial_ofdata_to_platdata, .probe = arc_serial_probe, .ops = &arc_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_ARC_SERIAL diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index 1f87f0cb28..bd1d89ec83 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -199,6 +199,8 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = { .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata), .probe = bcm283x_mu_serial_probe, .ops = &bcm283x_mu_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv), }; diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index 54fc9b5b39..2527bb8b1c 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -90,6 +90,8 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = { .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &bcm283x_pl011_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif .priv_auto_alloc_size = sizeof(struct pl01x_priv), }; diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c index ee5d561bfd..9ad8c770d5 100644 --- a/drivers/serial/serial_bcm6345.c +++ b/drivers/serial/serial_bcm6345.c @@ -89,26 +89,26 @@ struct bcm6345_serial_priv { /* enable rx & tx operation on uart */ static void bcm6345_serial_enable(void __iomem *base) { - setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | - UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); + setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); } /* disable rx & tx operation on uart */ static void bcm6345_serial_disable(void __iomem *base) { - clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | - UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); + clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | + UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); } /* clear all unread data in rx fifo and unsent data in tx fifo */ static void bcm6345_serial_flush(void __iomem *base) { /* empty rx and tx fifo */ - setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | - UART_CTL_RSTTXFIFO_MASK); + setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | + UART_CTL_RSTTXFIFO_MASK); /* read any pending char to make sure all irq status are cleared */ - readl_be(base + UART_FIFO_REG); + readl(base + UART_FIFO_REG); } static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) @@ -120,40 +120,40 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) bcm6345_serial_flush(base); /* set uart control config */ - clrsetbits_be32(base + UART_CTL_REG, - /* clear rx timeout */ - UART_CTL_RXTIMEOUT_MASK | - /* clear stop bits */ - UART_CTL_STOPBITS_MASK | - /* clear bits per symbol */ - UART_CTL_BITSPERSYM_MASK | - /* clear xmit break */ - UART_CTL_XMITBRK_MASK | - /* clear reserved bit */ - UART_CTL_RSVD_MASK | - /* disable parity */ - UART_CTL_RXPAREN_MASK | - UART_CTL_TXPAREN_MASK | - /* disable loopback */ - UART_CTL_LOOPBACK_MASK, - /* set timeout to 5 */ - UART_CTL_RXTIMEOUT_5 | - /* set 8 bits/symbol */ - UART_CTL_BITSPERSYM_8 | - /* set 1 stop bit */ - UART_CTL_STOPBITS_1 | - /* set parity to even */ - UART_CTL_RXPAREVEN_MASK | - UART_CTL_TXPAREVEN_MASK); + clrsetbits_32(base + UART_CTL_REG, + /* clear rx timeout */ + UART_CTL_RXTIMEOUT_MASK | + /* clear stop bits */ + UART_CTL_STOPBITS_MASK | + /* clear bits per symbol */ + UART_CTL_BITSPERSYM_MASK | + /* clear xmit break */ + UART_CTL_XMITBRK_MASK | + /* clear reserved bit */ + UART_CTL_RSVD_MASK | + /* disable parity */ + UART_CTL_RXPAREN_MASK | + UART_CTL_TXPAREN_MASK | + /* disable loopback */ + UART_CTL_LOOPBACK_MASK, + /* set timeout to 5 */ + UART_CTL_RXTIMEOUT_5 | + /* set 8 bits/symbol */ + UART_CTL_BITSPERSYM_8 | + /* set 1 stop bit */ + UART_CTL_STOPBITS_1 | + /* set parity to even */ + UART_CTL_RXPAREVEN_MASK | + UART_CTL_TXPAREVEN_MASK); /* set uart fifo config */ - clrsetbits_be32(base + UART_FIFO_CFG_REG, - /* clear fifo config */ - UART_FIFO_CFG_RX_MASK | - UART_FIFO_CFG_TX_MASK, - /* set fifo config to 4 */ - UART_FIFO_CFG_RX_4 | - UART_FIFO_CFG_TX_4); + clrsetbits_32(base + UART_FIFO_CFG_REG, + /* clear fifo config */ + UART_FIFO_CFG_RX_MASK | + UART_FIFO_CFG_TX_MASK, + /* set fifo config to 4 */ + UART_FIFO_CFG_RX_4 | + UART_FIFO_CFG_TX_4); /* set baud rate */ val = ((clk / baudrate) >> 4); @@ -161,10 +161,10 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) val = (val >> 1); else val = (val >> 1) - 1; - writel_be(val, base + UART_BAUD_REG); + writel(val, base + UART_BAUD_REG); /* clear interrupts */ - writel_be(0, base + UART_IR_REG); + writel(0, base + UART_IR_REG); /* enable uart */ bcm6345_serial_enable(base); @@ -175,7 +175,7 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) static int bcm6345_serial_pending(struct udevice *dev, bool input) { struct bcm6345_serial_priv *priv = dev_get_priv(dev); - u32 val = readl_be(priv->base + UART_IR_REG); + u32 val = readl(priv->base + UART_IR_REG); if (input) return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)); @@ -195,11 +195,11 @@ static int bcm6345_serial_putc(struct udevice *dev, const char ch) struct bcm6345_serial_priv *priv = dev_get_priv(dev); u32 val; - val = readl_be(priv->base + UART_IR_REG); + val = readl(priv->base + UART_IR_REG); if (!(val & UART_IR_STAT(UART_IR_TXEMPTY))) return -EAGAIN; - writel_be(ch, priv->base + UART_FIFO_REG); + writel(ch, priv->base + UART_FIFO_REG); return 0; } @@ -209,14 +209,13 @@ static int bcm6345_serial_getc(struct udevice *dev) struct bcm6345_serial_priv *priv = dev_get_priv(dev); u32 val; - val = readl_be(priv->base + UART_IR_REG); + val = readl(priv->base + UART_IR_REG); if (val & UART_IR_STAT(UART_IR_RXOVER)) - setbits_be32(priv->base + UART_CTL_REG, - UART_CTL_RSTRXFIFO_MASK); + setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY))) return -EAGAIN; - val = readl_be(priv->base + UART_FIFO_REG); + val = readl(priv->base + UART_FIFO_REG); if (val & UART_FIFO_ANYERR_MASK) return -EAGAIN; @@ -264,7 +263,6 @@ U_BOOT_DRIVER(bcm6345_serial) = { .probe = bcm6345_serial_probe, .priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv), .ops = &bcm6345_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_BCM6345 @@ -278,7 +276,7 @@ static inline void _debug_uart_init(void) static inline void wait_xfered(void __iomem *base) { do { - u32 val = readl_be(base + UART_IR_REG); + u32 val = readl(base + UART_IR_REG); if (val & UART_IR_STAT(UART_IR_TXEMPTY)) break; } while (1); @@ -289,7 +287,7 @@ static inline void _debug_uart_putc(int ch) void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; wait_xfered(base); - writel_be(ch, base + UART_FIFO_REG); + writel(ch, base + UART_FIFO_REG); wait_xfered(base); } diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index 1b54d1880f..dd3e511fc9 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -152,5 +152,4 @@ U_BOOT_DRIVER(serial_efi) = { .priv_auto_alloc_size = sizeof(struct serial_efi_priv), .probe = serial_efi_probe, .ops = &serial_efi_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c index bdb5adb2a4..39bd40e68b 100644 --- a/drivers/serial/serial_intel_mid.c +++ b/drivers/serial/serial_intel_mid.c @@ -64,5 +64,4 @@ U_BOOT_DRIVER(serial_intel_mid) = { .priv_auto_alloc_size = sizeof(struct NS16550), .probe = mid_serial_probe, .ops = &ns16550_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 6106c1f9ec..a357b00d28 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -540,5 +540,4 @@ U_BOOT_DRIVER(serial_lpuart) = { .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata), .probe = lpuart_serial_probe, .ops = &lpuart_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index dbb853735f..b3dad77aa2 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -132,7 +132,6 @@ U_BOOT_DRIVER(serial_meson) = { .of_match = meson_serial_ids, .probe = meson_serial_probe, .ops = &meson_serial_ops, - .flags = DM_FLAG_PRE_RELOC, .ofdata_to_platdata = meson_serial_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct meson_serial_platdata), }; diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index 292912b7ee..50d6e70f17 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -35,9 +36,9 @@ struct serialbuffer { uchar txbuf; /* tx buffers */ }; -static void serial_setdivisor(cpm8xx_t __iomem *cp) +static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate) { - int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate; + int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate; if (divisor / 16 > 0x1000) { /* bad divisor, assume 50MHz clock and 9600 baud */ @@ -58,7 +59,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp) * as serial console interface. */ -static void smc_setbrg(void) +static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &(im->im_cpm); @@ -71,10 +72,12 @@ static void smc_setbrg(void) out_be32(&cp->cp_simode, 0); - serial_setdivisor(cp); + serial_setdivisor(cp, baudrate); + + return 0; } -static int smc_init(void) +static int serial_mpc8xx_probe(struct udevice *dev) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; smc_t __iomem *sp; @@ -139,7 +142,7 @@ static int smc_init(void) out_8(&sp->smc_smce, 0xff); /* Set up the baud rate generator */ - smc_setbrg(); + serial_mpc8xx_setbrg(dev, gd->baudrate); /* Make the first buffer the only buffer. */ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP); @@ -166,14 +169,14 @@ static int smc_init(void) return 0; } -static void smc_putc(const char c) +static int serial_mpc8xx_putc(struct udevice *dev, const char c) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); struct serialbuffer __iomem *rtx; if (c == '\n') - smc_putc('\r'); + serial_mpc8xx_putc(dev, '\r'); rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; @@ -184,15 +187,11 @@ static void smc_putc(const char c) while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) WATCHDOG_RESET(); + + return 0; } -static void smc_puts(const char *s) -{ - while (*s) - smc_putc(*s++); -} - -static int smc_getc(void) +static int serial_mpc8xx_getc(struct udevice *dev) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); @@ -222,34 +221,37 @@ static int smc_getc(void) return c; } -static int smc_tstc(void) +static int serial_mpc8xx_pending(struct udevice *dev, bool input) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); struct serialbuffer __iomem *rtx; + if (!input) + return 0; + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY); } -struct serial_device serial_smc_device = { - .name = "serial_smc", - .start = smc_init, - .stop = NULL, - .setbrg = smc_setbrg, - .getc = smc_getc, - .tstc = smc_tstc, - .putc = smc_putc, - .puts = smc_puts, +static const struct dm_serial_ops serial_mpc8xx_ops = { + .putc = serial_mpc8xx_putc, + .pending = serial_mpc8xx_pending, + .getc = serial_mpc8xx_getc, + .setbrg = serial_mpc8xx_setbrg, }; -__weak struct serial_device *default_serial_console(void) -{ - return &serial_smc_device; -} +static const struct udevice_id serial_mpc8xx_ids[] = { + { .compatible = "fsl,pq1-smc" }, + { } +}; -void mpc8xx_serial_initialize(void) -{ - serial_register(&serial_smc_device); -} +U_BOOT_DRIVER(serial_mpc8xx) = { + .name = "serial_mpc8xx", + .id = UCLASS_SERIAL, + .of_match = serial_mpc8xx_ids, + .probe = serial_mpc8xx_probe, + .ops = &serial_mpc8xx_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c new file mode 100644 index 0000000000..bce1be8227 --- /dev/null +++ b/drivers/serial/serial_mtk.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek High-speed UART driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_serial_regs { + u32 rbr; + u32 ier; + u32 fcr; + u32 lcr; + u32 mcr; + u32 lsr; + u32 msr; + u32 spr; + u32 mdr1; + u32 highspeed; + u32 sample_count; + u32 sample_point; + u32 fracdiv_l; + u32 fracdiv_m; + u32 escape_en; + u32 guard; + u32 rx_sel; +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +/* the data is correct if the real baud is within 3%. */ +#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100) +#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100) + +struct mtk_serial_priv { + struct mtk_serial_regs __iomem *regs; + u32 clock; +}; + +static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud) +{ + bool support_clk12m_baud115200; + u32 quot, samplecount, realbaud; + + if ((baud <= 115200) && (priv->clock == 12000000)) + support_clk12m_baud115200 = true; + else + support_clk12m_baud115200 = false; + + if (baud <= 115200) { + writel(0, &priv->regs->highspeed); + quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud); + + if (support_clk12m_baud115200) { + writel(3, &priv->regs->highspeed); + quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud); + if (quot == 0) + quot = 1; + + samplecount = DIV_ROUND_CLOSEST(priv->clock, + quot * baud); + if (samplecount != 0) { + realbaud = priv->clock / samplecount / quot; + if ((realbaud > BAUD_ALLOW_MAX(baud)) || + (realbaud < BAUD_ALLOW_MIX(baud))) { + pr_info("baud %d can't be handled\n", + baud); + } + } else { + pr_info("samplecount is 0\n"); + } + } + } else if (baud <= 576000) { + writel(2, &priv->regs->highspeed); + + /* Set to next lower baudrate supported */ + if ((baud == 500000) || (baud == 576000)) + baud = 460800; + quot = DIV_ROUND_UP(priv->clock, 4 * baud); + } else { + writel(3, &priv->regs->highspeed); + quot = DIV_ROUND_UP(priv->clock, 256 * baud); + } + + /* set divisor */ + writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr); + writel(quot & 0xff, &priv->regs->dll); + writel((quot >> 8) & 0xff, &priv->regs->dlm); + writel(UART_LCR_WLS_8, &priv->regs->lcr); + + if (baud > 460800) { + u32 tmp; + + tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud); + writel(tmp - 1, &priv->regs->sample_count); + writel((tmp - 2) >> 1, &priv->regs->sample_point); + } else { + writel(0, &priv->regs->sample_count); + writel(0xff, &priv->regs->sample_point); + } + + if (support_clk12m_baud115200) { + writel(samplecount - 1, &priv->regs->sample_count); + writel((samplecount - 2) >> 1, &priv->regs->sample_point); + } +} + +static int mtk_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + _mtk_serial_setbrg(priv, baudrate); + + return 0; +} + +static int mtk_serial_putc(struct udevice *dev, const char ch) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs->lsr) & UART_LSR_THRE)) + return -EAGAIN; + + writel(ch, &priv->regs->thr); + + if (ch == '\n') + WATCHDOG_RESET(); + + return 0; +} + +static int mtk_serial_getc(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs->lsr) & UART_LSR_DR)) + return -EAGAIN; + + return readl(&priv->regs->rbr); +} + +static int mtk_serial_pending(struct udevice *dev, bool input) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + if (input) + return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0; + else + return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; +} + +static int mtk_serial_probe(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + + /* Disable interrupt */ + writel(0, &priv->regs->ier); + + return 0; +} + +static int mtk_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct mtk_serial_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + struct clk clk; + int err; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, 0, MAP_NOCACHE); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + priv->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("mtk_serial: failed to get clock\n"); + return err; + } + + if (!priv->clock) + priv->clock = dev_read_u32_default(dev, "clock-frequency", 0); + + if (!priv->clock) { + debug("mtk_serial: clock not defined\n"); + return -EINVAL; + } + + return 0; +} + +static const struct dm_serial_ops mtk_serial_ops = { + .putc = mtk_serial_putc, + .pending = mtk_serial_pending, + .getc = mtk_serial_getc, + .setbrg = mtk_serial_setbrg, +}; + +static const struct udevice_id mtk_serial_ids[] = { + { .compatible = "mediatek,hsuart" }, + { .compatible = "mediatek,mt6577-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_mtk) = { + .name = "serial_mtk", + .id = UCLASS_SERIAL, + .of_match = mtk_serial_ids, + .ofdata_to_platdata = mtk_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct mtk_serial_priv), + .probe = mtk_serial_probe, + .ops = &mtk_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_MTK + +#include + +static inline void _debug_uart_init(void) +{ + struct mtk_serial_priv priv; + + priv.regs = (void *) CONFIG_DEBUG_UART_BASE; + priv.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &priv.regs->ier); + + _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + struct mtk_serial_regs __iomem *regs = + (void *) CONFIG_DEBUG_UART_BASE; + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; + + writel(ch, ®s->thr); +} + +DEBUG_UART_FUNCS + +#endif \ No newline at end of file diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index ce26d2bd15..7e4cd6c4b4 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -129,7 +129,6 @@ U_BOOT_DRIVER(serial_mvebu) = { .platdata_auto_alloc_size = sizeof(struct mvebu_platdata), .probe = mvebu_serial_probe, .ops = &mvebu_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_MVEBU_A3700_UART diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e586c18cf0..7e4e6d36b8 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -354,7 +354,9 @@ U_BOOT_DRIVER(serial_mxc) = { #endif .probe = mxc_serial_probe, .ops = &mxc_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index af3c755f96..a31d73766d 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include @@ -20,6 +19,47 @@ #ifdef CONFIG_DEBUG_UART_OMAP +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif + +#define UART_MCRVAL 0x00 +#define UART_LCRVAL UART_LCR_8N1 + +static inline void serial_out_shift(void *addr, int shift, int value) +{ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + outb(value, (ulong)addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) + out_le32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + out_be32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) + writel(value, addr); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + writeb(value, addr + (1 << shift) - 1); +#else + writeb(value, addr); +#endif +} + +static inline int serial_in_shift(void *addr, int shift) +{ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + return inb((ulong)addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) + return in_le32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + return in_be32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) + return readl(addr); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + return readb(addr + (1 << shift) - 1); +#else + return readb(addr); +#endif +} + #include static inline void _debug_uart_init(void) @@ -121,7 +161,9 @@ U_BOOT_DRIVER(omap_serial) = { .priv_auto_alloc_size = sizeof(struct NS16550), .probe = ns16550_serial_probe, .ops = &ns16550_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #endif #endif /* DM_SERIAL */ diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 6fd97e2502..7ead73e6b7 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -132,5 +132,4 @@ U_BOOT_DRIVER(serial_owl) = { .priv_auto_alloc_size = sizeof(struct owl_serial_priv), .probe = owl_serial_probe, .ops = &owl_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c index ba73978e25..84600b1201 100644 --- a/drivers/serial/serial_pic32.c +++ b/drivers/serial/serial_pic32.c @@ -176,7 +176,6 @@ U_BOOT_DRIVER(pic32_serial) = { .of_match = pic32_uart_ids, .probe = pic32_uart_probe, .ops = &pic32_uart_ops, - .flags = DM_FLAG_PRE_RELOC, .priv_auto_alloc_size = sizeof(struct pic32_uart_priv), }; diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index f4f33b13ff..2f3d4de5e7 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -389,7 +389,9 @@ U_BOOT_DRIVER(serial_pl01x) = { .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif .priv_auto_alloc_size = sizeof(struct pl01x_priv), }; diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index faea6d4c99..e3160cf1bd 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -211,7 +211,6 @@ U_BOOT_DRIVER(serial_s5p) = { .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata), .probe = s5p_serial_probe, .ops = &s5p_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #endif diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index b1534981f8..c934d5f25a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -247,7 +247,9 @@ U_BOOT_DRIVER(serial_sh) = { .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata), .probe = sh_serial_probe, .ops = &sh_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif .priv_auto_alloc_size = sizeof(struct uart_port), }; diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c new file mode 100644 index 0000000000..341728a690 --- /dev/null +++ b/drivers/serial/serial_sifive.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_TXFIFO_FULL 0x80000000 +#define UART_RXFIFO_EMPTY 0x80000000 +#define UART_RXFIFO_DATA 0x000000ff +#define UART_TXCTRL_TXEN 0x1 +#define UART_RXCTRL_RXEN 0x1 + +struct uart_sifive { + u32 txfifo; + u32 rxfifo; + u32 txctrl; + u32 rxctrl; + u32 ie; + u32 ip; + u32 div; +}; + +struct sifive_uart_platdata { + unsigned int clock; + int saved_input_char; + struct uart_sifive *regs; +}; + +/* Set up the baud rate in gd struct */ +static void _sifive_serial_setbrg(struct uart_sifive *regs, + unsigned long clock, unsigned long baud) +{ + writel((u32)((clock / baud) - 1), ®s->div); +} + +static void _sifive_serial_init(struct uart_sifive *regs) +{ + writel(UART_TXCTRL_TXEN, ®s->txctrl); + writel(UART_RXCTRL_RXEN, ®s->rxctrl); + writel(0, ®s->ie); +} + +static int _sifive_serial_putc(struct uart_sifive *regs, const char c) +{ + if (readl(®s->txfifo) & UART_TXFIFO_FULL) + return -EAGAIN; + + writel(c, ®s->txfifo); + + return 0; +} + +static int _sifive_serial_getc(struct uart_sifive *regs) +{ + int ch = readl(®s->rxfifo); + + if (ch & UART_RXFIFO_EMPTY) + return -EAGAIN; + ch &= UART_RXFIFO_DATA; + + return (!ch) ? -EAGAIN : ch; +} + +static int sifive_serial_setbrg(struct udevice *dev, int baudrate) +{ + int err; + struct clk clk; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + platdata->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("SiFive UART failed to get clock\n"); + return err; + } + + if (!platdata->clock) + platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); + if (!platdata->clock) { + debug("SiFive UART clock not defined\n"); + return -EINVAL; + } + + _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); + + return 0; +} + +static int sifive_serial_probe(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + platdata->saved_input_char = 0; + _sifive_serial_init(platdata->regs); + + return 0; +} + +static int sifive_serial_getc(struct udevice *dev) +{ + int c; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (platdata->saved_input_char > 0) { + c = platdata->saved_input_char; + platdata->saved_input_char = 0; + return c; + } + + while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; + + return c; +} + +static int sifive_serial_putc(struct udevice *dev, const char ch) +{ + int rc; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ; + + return rc; +} + +static int sifive_serial_pending(struct udevice *dev, bool input) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + if (input) { + if (platdata->saved_input_char > 0) + return 1; + platdata->saved_input_char = _sifive_serial_getc(regs); + return (platdata->saved_input_char > 0) ? 1 : 0; + } else { + return !!(readl(®s->txfifo) & UART_TXFIFO_FULL); + } +} + +static int sifive_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + platdata->regs = (struct uart_sifive *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); + + return 0; +} + +static const struct dm_serial_ops sifive_serial_ops = { + .putc = sifive_serial_putc, + .getc = sifive_serial_getc, + .pending = sifive_serial_pending, + .setbrg = sifive_serial_setbrg, +}; + +static const struct udevice_id sifive_serial_ids[] = { + { .compatible = "sifive,uart0" }, + { } +}; + +U_BOOT_DRIVER(serial_sifive) = { + .name = "serial_sifive", + .id = UCLASS_SERIAL, + .of_match = sifive_serial_ids, + .ofdata_to_platdata = sifive_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata), + .probe = sifive_serial_probe, + .ops = &sifive_serial_ops, +}; + +#ifdef CONFIG_DEBUG_UART_SIFIVE +static inline void _debug_uart_init(void) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + _sifive_serial_init(regs); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +} + +DEBUG_UART_FUNCS + +#endif diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 5dfc6171eb..c972f1e9af 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -205,6 +205,5 @@ U_BOOT_DRIVER(serial_sti_asc) = { .ops = &sti_asc_serial_ops, .probe = sti_asc_serial_probe, .priv_auto_alloc_size = sizeof(struct sti_asc_serial), - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 66e02d5689..e31c87b9ac 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,7 @@ static int stm32_serial_probe(struct udevice *dev) { struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); struct clk clk; + struct reset_ctl reset; int ret; plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev); @@ -185,6 +187,13 @@ static int stm32_serial_probe(struct udevice *dev) return ret; } + ret = reset_get_by_index(dev, 0, &reset); + if (!ret) { + reset_assert(&reset); + udelay(2); + reset_deassert(&reset); + } + plat->clock_rate = clk_get_rate(&clk); if (plat->clock_rate < 0) { clk_disable(&clk); @@ -230,7 +239,9 @@ U_BOOT_DRIVER(serial_stm32) = { .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata), .ops = &stm32_serial_ops, .probe = stm32_serial_probe, +#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, +#endif }; #ifdef CONFIG_DEBUG_UART_STM32 diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index cead3c62f5..1be777bd3b 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -109,7 +109,6 @@ U_BOOT_DRIVER(serial_uartlite) = { .platdata_auto_alloc_size = sizeof(struct uartlite_platdata), .probe = uartlite_serial_probe, .ops = &uartlite_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_UARTLITE diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index f689015b4a..7e486a68ff 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -210,7 +210,6 @@ U_BOOT_DRIVER(serial_zynq) = { .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata), .probe = zynq_serial_probe, .ops = &zynq_serial_ops, - .flags = DM_FLAG_PRE_RELOC, }; #ifdef CONFIG_DEBUG_UART_ZYNQ diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 5de86c05c6..c0d97cca33 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -31,6 +31,14 @@ config I2S_SAMSUNG option provides an implementation for sound_init() and sound_play(). +config SOUND_MAX98090 + bool "Support Maxim max98090 audio codec" + depends on I2S_SAMSUNG + help + Enable the max98090 audio codec. This is connected via I2S for + audio data and I2C for codec control. At present it only works + with the Samsung I2S driver. + config SOUND_MAX98095 bool "Support Maxim max98095 audio codec" depends on I2S_SAMSUNG diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 696c5aecbe..1de4346ec7 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -4,8 +4,12 @@ # R. Chandrasekar obj-$(CONFIG_SOUND) += sound.o -obj-$(CONFIG_I2S) += sound-i2s.o +obj-$(CONFIG_SOUND) += codec-uclass.o +obj-$(CONFIG_SOUND) += i2s-uclass.o +obj-$(CONFIG_SOUND) += sound-uclass.o obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o +obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o -obj-$(CONFIG_SOUND_MAX98095) += max98095.o +obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o +obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o diff --git a/drivers/sound/codec-uclass.c b/drivers/sound/codec-uclass.c new file mode 100644 index 0000000000..1ec77acfc1 --- /dev/null +++ b/drivers/sound/codec-uclass.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include + +int audio_codec_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels) +{ + struct audio_codec_ops *ops = audio_codec_get_ops(dev); + + if (!ops->set_params) + return -ENOSYS; + + return ops->set_params(dev, interface, rate, mclk_freq, bits_per_sample, + channels); +} + +UCLASS_DRIVER(audio_codec) = { + .id = UCLASS_AUDIO_CODEC, + .name = "audio-codec", +}; diff --git a/drivers/sound/i2s-uclass.c b/drivers/sound/i2s-uclass.c new file mode 100644 index 0000000000..b741e3952d --- /dev/null +++ b/drivers/sound/i2s-uclass.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include + +int i2s_tx_data(struct udevice *dev, void *data, uint data_size) +{ + struct i2s_ops *ops = i2s_get_ops(dev); + + if (!ops->tx_data) + return -ENOSYS; + + return ops->tx_data(dev, data, data_size); +} + +UCLASS_DRIVER(i2s) = { + .id = UCLASS_I2S, + .name = "i2s", + .per_device_auto_alloc_size = sizeof(struct i2s_uc_priv), +}; diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c new file mode 100644 index 0000000000..346ff5ffbe --- /dev/null +++ b/drivers/sound/max98090.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * max98090.c -- MAX98090 ALSA SoC Audio driver + * + * Copyright 2011 Maxim Integrated Products + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "maxim_codec.h" +#include "max98090.h" + +/* + * Sets hw params for max98090 + * + * @priv: max98090 information pointer + * @rate: Sampling rate + * @bits_per_sample: Bits per sample + * + * @return -EIO for error, 0 for success. + */ +int max98090_hw_params(struct maxim_priv *priv, unsigned int rate, + unsigned int bits_per_sample) +{ + int error; + unsigned char value; + + switch (bits_per_sample) { + case 16: + maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value); + error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT, + M98090_WS_MASK, 0); + maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value); + break; + default: + debug("%s: Illegal bits per sample %d.\n", + __func__, bits_per_sample); + return -1; + } + + /* Update filter mode */ + if (rate < 240000) + error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, + M98090_MODE_MASK, 0); + else + error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, + M98090_MODE_MASK, M98090_MODE_MASK); + + /* Update sample rate mode */ + if (rate < 50000) + error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, + M98090_DHF_MASK, 0); + else + error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG, + M98090_DHF_MASK, M98090_DHF_MASK); + + if (error < 0) { + debug("%s: Error setting hardware params.\n", __func__); + return -EIO; + } + priv->rate = rate; + + return 0; +} + +/* + * Configures Audio interface system clock for the given frequency + * + * @priv: max98090 information + * @freq: Sampling frequency in Hz + * + * @return -EIO for error, 0 for success. + */ +int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq) +{ + int error = 0; + + /* Requested clock frequency is already setup */ + if (freq == priv->sysclk) + return 0; + + /* Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 40MHz).. + * 0x03 (when master clk is 40MHz to 60MHz).. + */ + if (freq >= 10000000 && freq < 20000000) { + error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV1); + } else if (freq >= 20000000 && freq < 40000000) { + error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV2); + } else if (freq >= 40000000 && freq < 60000000) { + error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK, + M98090_PSCLK_DIV4); + } else { + debug("%s: Invalid master clock frequency\n", __func__); + return -1; + } + + debug("%s: Clock at %uHz\n", __func__, freq); + + if (error < 0) + return -1; + + priv->sysclk = freq; + + return 0; +} + +/* + * Sets Max98090 I2S format + * + * @priv: max98090 information + * @fmt: i2S format - supports a subset of the options defined in i2s.h. + * + * @return -EIO for error, 0 for success. + */ +int max98090_set_fmt(struct maxim_priv *priv, int fmt) +{ + u8 regval = 0; + int error = 0; + + if (fmt == priv->fmt) + return 0; + + priv->fmt = fmt; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* Set to slave mode PLL - MAS mode off */ + error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, + 0x00); + error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, + 0x00); + error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE, + M98090_USE_M1_MASK, 0); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Set to master mode */ + debug("Master mode not supported\n"); + break; + case SND_SOC_DAIFMT_CBS_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + default: + debug("%s: Clock mode unsupported\n", __func__); + return -EINVAL; + } + + error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval); + + regval = 0; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + regval |= M98090_DLY_MASK; + break; + case SND_SOC_DAIFMT_LEFT_J: + break; + case SND_SOC_DAIFMT_RIGHT_J: + regval |= M98090_RJ_MASK; + break; + case SND_SOC_DAIFMT_DSP_A: + /* Not supported mode */ + default: + debug("%s: Unrecognized format.\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + regval |= M98090_WCI_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + regval |= M98090_BCI_MASK; + break; + case SND_SOC_DAIFMT_IB_IF: + regval |= M98090_BCI_MASK | M98090_WCI_MASK; + break; + default: + debug("%s: Unrecognized inversion settings.\n", __func__); + return -EINVAL; + } + + error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval); + + if (error < 0) { + debug("%s: Error setting i2s format.\n", __func__); + return -EIO; + } + + return 0; +} + +/* + * resets the audio codec + * + * @priv: max98090 information + * @return -EIO for error, 0 for success. + */ +static int max98090_reset(struct maxim_priv *priv) +{ + int ret; + + /* + * Gracefully reset the DSP core and the codec hardware in a proper + * sequence. + */ + ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET, + M98090_SWRESET_MASK); + if (ret != 0) { + debug("%s: Failed to reset DSP: %d\n", __func__, ret); + return ret; + } + mdelay(20); + + return 0; +} + +/* + * Initialise max98090 codec device + * + * @priv: max98090 information + * + * @return -EIO for error, 0 for success. + */ +int max98090_device_init(struct maxim_priv *priv) +{ + unsigned char id; + int error = 0; + + /* Enable codec clock */ + set_xclkout(); + + /* reset the codec, the DSP core, and disable all interrupts */ + error = max98090_reset(priv); + if (error != 0) { + debug("Reset\n"); + return error; + } + + /* initialize private data */ + priv->sysclk = -1U; + priv->rate = -1U; + priv->fmt = -1U; + + error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id); + if (error < 0) { + debug("%s: Failure reading hardware revision: %d\n", + __func__, id); + return -EIO; + } + debug("%s: Hardware revision: %d\n", __func__, id); + + return 0; +} + +static int max98090_setup_interface(struct maxim_priv *priv) +{ + unsigned char id; + int error; + + /* Reading interrupt status to clear them */ + error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id); + + error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL, + M98090_DACHP_MASK); + error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL, + M98090_VCM_MODE_MASK); + + error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1); + error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2); + + error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25); + error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25); + + error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0); + error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0); + error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0); + error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0); + error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION, + M98090_SDIEN_MASK); + error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN, + M98090_SHDNN_MASK); + error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE, + M98090_HPREN_MASK | M98090_HPLEN_MASK | + M98090_SPREN_MASK | M98090_SPLEN_MASK | + M98090_DAREN_MASK | M98090_DALEN_MASK); + error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION, + M98090_SDOEN_MASK | M98090_SDIEN_MASK); + + if (error < 0) + return -EIO; + + return 0; +} + +static int max98090_do_init(struct maxim_priv *priv, int sampling_rate, + int mclk_freq, int bits_per_sample) +{ + int ret = 0; + + ret = max98090_setup_interface(priv); + if (ret < 0) { + debug("%s: max98090 setup interface failed\n", __func__); + return ret; + } + + ret = max98090_set_sysclk(priv, mclk_freq); + if (ret < 0) { + debug("%s: max98090 codec set sys clock failed\n", __func__); + return ret; + } + + ret = max98090_hw_params(priv, sampling_rate, bits_per_sample); + + if (ret == 0) { + ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS); + } + + return ret; +} + +static int max98090_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, + uint channels) +{ + struct maxim_priv *priv = dev_get_priv(dev); + + return max98090_do_init(priv, rate, mclk_freq, bits_per_sample); +} + +static int max98090_probe(struct udevice *dev) +{ + struct maxim_priv *priv = dev_get_priv(dev); + int ret; + + priv->dev = dev; + ret = max98090_device_init(priv); + if (ret < 0) { + debug("%s: max98090 codec chip init failed\n", __func__); + return ret; + } + + return 0; +} + +static const struct audio_codec_ops max98090_ops = { + .set_params = max98090_set_params, +}; + +static const struct udevice_id max98090_ids[] = { + { .compatible = "maxim,max98090" }, + { } +}; + +U_BOOT_DRIVER(max98090) = { + .name = "max98090", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98090_ids, + .probe = max98090_probe, + .ops = &max98090_ops, + .priv_auto_alloc_size = sizeof(struct maxim_priv), +}; diff --git a/drivers/sound/max98090.h b/drivers/sound/max98090.h new file mode 100644 index 0000000000..3a6983b8e2 --- /dev/null +++ b/drivers/sound/max98090.h @@ -0,0 +1,663 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * max98090.h -- MAX98090 ALSA SoC Audio driver + * + * Copyright 2011 Maxim Integrated Products + */ + +#ifndef _MAX98090_H +#define _MAX98090_H + +#include "maxim_codec.h" + +/* MAX98090 Registers Definition */ + +#define M98090_REG_SOFTWARE_RESET 0x00 +#define M98090_REG_DEVICE_STATUS 0x01 + +#define M98090_REG_QUICK_SAMPLE_RATE 0x05 +#define M98090_REG_DAI_INTERFACE 0x06 +#define M98090_REG_DAC_PATH 0x07 + +#define M98090_REG_MIC_BIAS_VOLTAGE 0x12 +#define M98090_REG_DIGITAL_MIC_ENABLE 0x13 +#define M98090_REG_DIGITAL_MIC_CONFIG 0x14 +#define M98090_REG_SYSTEM_CLOCK 0x1B +#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D +#define M98090_REG_CLOCK_MODE 0x1C +#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E + +#define M98090_REG_MASTER_MODE 0x21 +#define M98090_REG_INTERFACE_FORMAT 0x22 +#define M98090_REG_IO_CONFIGURATION 0x25 +#define M98090_REG_FILTER_CONFIG 0x26 + +#define M98090_REG_LEFT_HP_MIXER 0x29 +#define M98090_REG_RIGHT_HP_MIXER 0x2a +#define M98090_REG_HP_CONTROL 0x2b +#define M98090_REG_LEFT_HP_VOLUME 0x2c +#define M98090_REG_RIGHT_HP_VOLUME 0x2d +#define M98090_REG_LEFT_SPK_MIXER 0x2e +#define M98090_REG_RIGHT_SPK_MIXER 0x2f +#define M98090_REG_SPK_CONTROL 0x30 +#define M98090_REG_LEFT_SPK_VOLUME 0x31 +#define M98090_REG_RIGHT_SPK_VOLUME 0x32 + +#define M98090_REG_RCV_LOUTL_CONTROL 0x38 +#define M98090_REG_RCV_LOUTL_VOLUME 0x39 +#define M98090_REG_LOUTR_MIXER 0x3a +#define M98090_REG_LOUTR_CONTROL 0x3b +#define M98090_REG_LOUTR_VOLUME 0x3c +#define M98090_REG_JACK_DETECT 0x3d +#define M98090_REG_INPUT_ENABLE 0x3e +#define M98090_REG_OUTPUT_ENABLE 0x3f +#define M98090_REG_LEVEL_CONTROL 0x40 +#define M98090_REG_DSP_FILTER_ENABLE 0x41 +#define M98090_REG_BIAS_CONTROL 0x42 +#define M98090_REG_DAC_CONTROL 0x43 +#define M98090_REG_ADC_CONTROL 0x44 +#define M98090_REG_DEVICE_SHUTDOWN 0x45 + +#define M98090_REG_REVISION_ID 0xff + +#define M98090_REG_CNT (0xff + 1) +#define M98090_REG_MAX_CACHed 0x45 + +/* MAX98090 Registers Bit Fields */ + +/* + * M98090_REG_SOFTWARE_RESET 0x00 + */ +#define M98090_SWRESET_MASK BIT(7) + +/* + * M98090_REG_QUICK_SAMPLE_RATE 0x05 + */ +#define M98090_SR_96K_MASK BIT(5) +#define M98090_SR_96K_SHIFT 5 +#define M98090_SR_96K_WIDTH 1 +#define M98090_SR_32K_MASK BIT(4) +#define M98090_SR_32K_SHIFT 4 +#define M98090_SR_32K_WIDTH 1 +#define M98090_SR_48K_MASK BIT(3) +#define M98090_SR_48K_SHIFT 3 +#define M98090_SR_48K_WIDTH 1 +#define M98090_SR_44K1_MASK BIT(2) +#define M98090_SR_44K1_SHIFT 2 +#define M98090_SR_44K1_WIDTH 1 +#define M98090_SR_16K_MASK BIT(1) +#define M98090_SR_16K_SHIFT 1 +#define M98090_SR_16K_WIDTH 1 +#define M98090_SR_8K_MASK BIT(0) +#define M98090_SR_8K_SHIFT 0 +#define M98090_SR_8K_WIDTH 1 +#define M98090_SR_MASK 0x3F +#define M98090_SR_ALL_SHIFT 0 +#define M98090_SR_ALL_WIDTH 8 +#define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH) + +/* + * M98090_REG_DAI_INTERFACE 0x06 + */ +#define M98090_RJ_M_MASK BIT(5) +#define M98090_RJ_M_SHIFT 5 +#define M98090_RJ_M_WIDTH 1 +#define M98090_RJ_S_MASK BIT(4) +#define M98090_RJ_S_SHIFT 4 +#define M98090_RJ_S_WIDTH 1 +#define M98090_LJ_M_MASK BIT(3) +#define M98090_LJ_M_SHIFT 3 +#define M98090_LJ_M_WIDTH 1 +#define M98090_LJ_S_MASK BIT(2) +#define M98090_LJ_S_SHIFT 2 +#define M98090_LJ_S_WIDTH 1 +#define M98090_I2S_M_MASK BIT(1) +#define M98090_I2S_M_SHIFT 1 +#define M98090_I2S_M_WIDTH 1 +#define M98090_I2S_S_MASK BIT(0) +#define M98090_I2S_S_SHIFT 0 +#define M98090_I2S_S_WIDTH 1 +#define M98090_DAI_ALL_SHIFT 0 +#define M98090_DAI_ALL_WIDTH 8 +#define M98090_DAI_ALL_NUM BIT(M98090_DAI_ALL_WIDTH) + +/* + * M98090_REG_DAC_PATH 0x07 + */ +#define M98090_DIG2_HP_MASK BIT(7) +#define M98090_DIG2_HP_SHIFT 7 +#define M98090_DIG2_HP_WIDTH 1 +#define M98090_DIG2_EAR_MASK BIT(6) +#define M98090_DIG2_EAR_SHIFT 6 +#define M98090_DIG2_EAR_WIDTH 1 +#define M98090_DIG2_SPK_MASK BIT(5) +#define M98090_DIG2_SPK_SHIFT 5 +#define M98090_DIG2_SPK_WIDTH 1 +#define M98090_DIG2_LOUT_MASK BIT(4) +#define M98090_DIG2_LOUT_SHIFT 4 +#define M98090_DIG2_LOUT_WIDTH 1 +#define M98090_DIG2_ALL_SHIFT 0 +#define M98090_DIG2_ALL_WIDTH 8 +#define M98090_DIG2_ALL_NUM BIT(M98090_DIG2_ALL_WIDTH) + +/* + * M98090_REG_MIC_BIAS_VOLTAGE 0x12 + */ +#define M98090_MBVSEL_MASK (3 << 0) +#define M98090_MBVSEL_SHIFT 0 +#define M98090_MBVSEL_WIDTH 2 +#define M98090_MBVSEL_2V8 (3 << 0) +#define M98090_MBVSEL_2V55 (2 << 0) +#define M98090_MBVSEL_2V4 BIT(0) +#define M98090_MBVSEL_2V2 (0 << 0) + +/* + * M98090_REG_DIGITAL_MIC_ENABLE 0x13 + */ +#define M98090_MICCLK_MASK (7 << 4) +#define M98090_MICCLK_SHIFT 4 +#define M98090_MICCLK_WIDTH 3 +#define M98090_DIGMIC4_MASK BIT(3) +#define M98090_DIGMIC4_SHIFT 3 +#define M98090_DIGMIC4_WIDTH 1 +#define M98090_DIGMIC4_NUM BIT(M98090_DIGMIC4_WIDTH) +#define M98090_DIGMIC3_MASK BIT(2) +#define M98090_DIGMIC3_SHIFT 2 +#define M98090_DIGMIC3_WIDTH 1 +#define M98090_DIGMIC3_NUM BIT(M98090_DIGMIC3_WIDTH) +#define M98090_DIGMICR_MASK BIT(1) +#define M98090_DIGMICR_SHIFT 1 +#define M98090_DIGMICR_WIDTH 1 +#define M98090_DIGMICR_NUM BIT(M98090_DIGMICR_WIDTH) +#define M98090_DIGMICL_MASK BIT(0) +#define M98090_DIGMICL_SHIFT 0 +#define M98090_DIGMICL_WIDTH 1 +#define M98090_DIGMICL_NUM BIT(M98090_DIGMICL_WIDTH) + +/* + * M98090_REG_DIGITAL_MIC_CONFIG 0x14 + */ +#define M98090_DMIC_COMP_MASK (15 << 4) +#define M98090_DMIC_COMP_SHIFT 4 +#define M98090_DMIC_COMP_WIDTH 4 +#define M98090_DMIC_COMP_NUM BIT(M98090_DMIC_COMP_WIDTH) +#define M98090_DMIC_FREQ_MASK (3 << 0) +#define M98090_DMIC_FREQ_SHIFT 0 +#define M98090_DMIC_FREQ_WIDTH 2 + +/* + * M98090_REG_CLOCK_MODE 0x1B + */ +#define M98090_PSCLK_MASK (3 << 4) +#define M98090_PSCLK_SHIFT 4 +#define M98090_PSCLK_WIDTH 2 +#define M98090_PSCLK_DISABLED (0 << 4) +#define M98090_PSCLK_DIV1 BIT(4) +#define M98090_PSCLK_DIV2 (2 << 4) +#define M98090_PSCLK_DIV4 (3 << 4) + +/* + * M98090_REG_INTERFACE_FORMAT 0x22 + */ +#define M98090_RJ_MASK BIT(5) +#define M98090_RJ_SHIFT 5 +#define M98090_RJ_WIDTH 1 +#define M98090_WCI_MASK BIT(4) +#define M98090_WCI_SHIFT 4 +#define M98090_WCI_WIDTH 1 +#define M98090_BCI_MASK BIT(3) +#define M98090_BCI_SHIFT 3 +#define M98090_BCI_WIDTH 1 +#define M98090_DLY_MASK BIT(2) +#define M98090_DLY_SHIFT 2 +#define M98090_DLY_WIDTH 1 +#define M98090_WS_MASK (3 << 0) +#define M98090_WS_SHIFT 0 +#define M98090_WS_WIDTH 2 +#define M98090_WS_NUM BIT(M98090_WS_WIDTH) + +/* M98090_REG_IO_CONFIGURATION 0x25 */ +#define M98090_LTEN_MASK BIT(5) +#define M98090_LTEN_SHIFT 5 +#define M98090_LTEN_WIDTH 1 +#define M98090_LTEN_NUM BIT(M98090_LTEN_WIDTH) +#define M98090_LBEN_MASK BIT(4) +#define M98090_LBEN_SHIFT 4 +#define M98090_LBEN_WIDTH 1 +#define M98090_LBEN_NUM BIT(M98090_LBEN_WIDTH) +#define M98090_DMONO_MASK BIT(3) +#define M98090_DMONO_SHIFT 3 +#define M98090_DMONO_WIDTH 1 +#define M98090_DMONO_NUM BIT(M98090_DMONO_WIDTH) +#define M98090_HIZOFF_MASK BIT(2) +#define M98090_HIZOFF_SHIFT 2 +#define M98090_HIZOFF_WIDTH 1 +#define M98090_HIZOFF_NUM BIT(M98090_HIZOFF_WIDTH) +#define M98090_SDOEN_MASK BIT(1) +#define M98090_SDOEN_SHIFT 1 +#define M98090_SDOEN_WIDTH 1 +#define M98090_SDOEN_NUM BIT(M98090_SDOEN_WIDTH) +#define M98090_SDIEN_MASK BIT(0) +#define M98090_SDIEN_SHIFT 0 +#define M98090_SDIEN_WIDTH 1 +#define M98090_SDIEN_NUM BIT(M98090_SDIEN_WIDTH) + +/* + * M98090_REG_FILTER_CONFIG 0x26 + */ +#define M98090_MODE_MASK BIT(7) +#define M98090_MODE_SHIFT 7 +#define M98090_MODE_WIDTH 1 +#define M98090_AHPF_MASK BIT(6) +#define M98090_AHPF_SHIFT 6 +#define M98090_AHPF_WIDTH 1 +#define M98090_AHPF_NUM BIT(M98090_AHPF_WIDTH) +#define M98090_DHPF_MASK BIT(5) +#define M98090_DHPF_SHIFT 5 +#define M98090_DHPF_WIDTH 1 +#define M98090_DHPF_NUM BIT(M98090_DHPF_WIDTH) +#define M98090_DHF_MASK BIT(4) +#define M98090_DHF_SHIFT 4 +#define M98090_DHF_WIDTH 1 +#define M98090_FLT_DMIC34MODE_MASK BIT(3) +#define M98090_FLT_DMIC34MODE_SHIFT 3 +#define M98090_FLT_DMIC34MODE_WIDTH 1 +#define M98090_FLT_DMIC34HPF_MASK BIT(2) +#define M98090_FLT_DMIC34HPF_SHIFT 2 +#define M98090_FLT_DMIC34HPF_WIDTH 1 +#define M98090_FLT_DMIC34HPF_NUM BIT(M98090_FLT_DMIC34HPF_WIDTH) + +/* + * M98090_REG_CLOCK_MODE + */ +#define M98090_FREQ_MASK (15 << 4) +#define M98090_FREQ_SHIFT 4 +#define M98090_FREQ_WIDTH 4 +#define M98090_USE_M1_MASK BIT(0) +#define M98090_USE_M1_SHIFT 0 +#define M98090_USE_M1_WIDTH 1 +#define M98090_USE_M1_NUM BIT(M98090_USE_M1_WIDTH) + +/* + * M98090_REG_LEFT_HP_MIXER 0x29 + */ +#define M98090_MIXHPL_MIC2_MASK BIT(5) +#define M98090_MIXHPL_MIC2_SHIFT 5 +#define M98090_MIXHPL_MIC2_WIDTH 1 +#define M98090_MIXHPL_MIC1_MASK BIT(4) +#define M98090_MIXHPL_MIC1_SHIFT 4 +#define M98090_MIXHPL_MIC1_WIDTH 1 +#define M98090_MIXHPL_LINEB_MASK BIT(3) +#define M98090_MIXHPL_LINEB_SHIFT 3 +#define M98090_MIXHPL_LINEB_WIDTH 1 +#define M98090_MIXHPL_LINEA_MASK BIT(2) +#define M98090_MIXHPL_LINEA_SHIFT 2 +#define M98090_MIXHPL_LINEA_WIDTH 1 +#define M98090_MIXHPL_DACR_MASK BIT(1) +#define M98090_MIXHPL_DACR_SHIFT 1 +#define M98090_MIXHPL_DACR_WIDTH 1 +#define M98090_MIXHPL_DACL_MASK BIT(0) +#define M98090_MIXHPL_DACL_SHIFT 0 +#define M98090_MIXHPL_DACL_WIDTH 1 +#define M98090_MIXHPL_MASK (63 << 0) +#define M98090_MIXHPL_SHIFT 0 +#define M98090_MIXHPL_WIDTH 6 + +/* + * M98090_REG_RIGHT_HP_MIXER 0x2A + */ +#define M98090_MIXHPR_MIC2_MASK BIT(5) +#define M98090_MIXHPR_MIC2_SHIFT 5 +#define M98090_MIXHPR_MIC2_WIDTH 1 +#define M98090_MIXHPR_MIC1_MASK BIT(4) +#define M98090_MIXHPR_MIC1_SHIFT 4 +#define M98090_MIXHPR_MIC1_WIDTH 1 +#define M98090_MIXHPR_LINEB_MASK BIT(3) +#define M98090_MIXHPR_LINEB_SHIFT 3 +#define M98090_MIXHPR_LINEB_WIDTH 1 +#define M98090_MIXHPR_LINEA_MASK BIT(2) +#define M98090_MIXHPR_LINEA_SHIFT 2 +#define M98090_MIXHPR_LINEA_WIDTH 1 +#define M98090_MIXHPR_DACR_MASK BIT(1) +#define M98090_MIXHPR_DACR_SHIFT 1 +#define M98090_MIXHPR_DACR_WIDTH 1 +#define M98090_MIXHPR_DACL_MASK BIT(0) +#define M98090_MIXHPR_DACL_SHIFT 0 +#define M98090_MIXHPR_DACL_WIDTH 1 +#define M98090_MIXHPR_MASK (63 << 0) +#define M98090_MIXHPR_SHIFT 0 +#define M98090_MIXHPR_WIDTH 6 + +/* + * M98090_REG_LEFT_HP_VOLUME 0x2C + */ +#define M98090_HPLM_MASK BIT(7) +#define M98090_HPLM_SHIFT 7 +#define M98090_HPLM_WIDTH 1 +#define M98090_HPVOLL_MASK (31 << 0) +#define M98090_HPVOLL_SHIFT 0 +#define M98090_HPVOLL_WIDTH 5 +#define M98090_HPVOLL_NUM BIT(M98090_HPVOLL_WIDTH) + +/* + * M98090_REG_RIGHT_HP_VOLUME 0x2D + */ +#define M98090_HPRM_MASK BIT(7) +#define M98090_HPRM_SHIFT 7 +#define M98090_HPRM_WIDTH 1 +#define M98090_HPVOLR_MASK (31 << 0) +#define M98090_HPVOLR_SHIFT 0 +#define M98090_HPVOLR_WIDTH 5 +#define M98090_HPVOLR_NUM BIT(M98090_HPVOLR_WIDTH) + +/* + * M98090_REG_LEFT_SPK_MIXER 0x2E + */ +#define M98090_MIXSPL_MIC2_MASK BIT(5) +#define M98090_MIXSPL_MIC2_SHIFT 5 +#define M98090_MIXSPL_MIC2_WIDTH 1 +#define M98090_MIXSPL_MIC1_MASK BIT(4) +#define M98090_MIXSPL_MIC1_SHIFT 4 +#define M98090_MIXSPL_MIC1_WIDTH 1 +#define M98090_MIXSPL_LINEB_MASK BIT(3) +#define M98090_MIXSPL_LINEB_SHIFT 3 +#define M98090_MIXSPL_LINEB_WIDTH 1 +#define M98090_MIXSPL_LINEA_MASK BIT(2) +#define M98090_MIXSPL_LINEA_SHIFT 2 +#define M98090_MIXSPL_LINEA_WIDTH 1 +#define M98090_MIXSPL_DACR_MASK BIT(1) +#define M98090_MIXSPL_DACR_SHIFT 1 +#define M98090_MIXSPL_DACR_WIDTH 1 +#define M98090_MIXSPL_DACL_MASK BIT(0) +#define M98090_MIXSPL_DACL_SHIFT 0 +#define M98090_MIXSPL_DACL_WIDTH 1 +#define M98090_MIXSPL_MASK (63 << 0) +#define M98090_MIXSPL_SHIFT 0 +#define M98090_MIXSPL_WIDTH 6 +#define M98090_MIXSPR_DACR_MASK BIT(1) +#define M98090_MIXSPR_DACR_SHIFT 1 +#define M98090_MIXSPR_DACR_WIDTH 1 + +/* + * M98090_REG_RIGHT_SPK_MIXER 0x2F + */ +#define M98090_SPK_SLAVE_MASK BIT(6) +#define M98090_SPK_SLAVE_SHIFT 6 +#define M98090_SPK_SLAVE_WIDTH 1 +#define M98090_MIXSPR_MIC2_MASK BIT(5) +#define M98090_MIXSPR_MIC2_SHIFT 5 +#define M98090_MIXSPR_MIC2_WIDTH 1 +#define M98090_MIXSPR_MIC1_MASK BIT(4) +#define M98090_MIXSPR_MIC1_SHIFT 4 +#define M98090_MIXSPR_MIC1_WIDTH 1 +#define M98090_MIXSPR_LINEB_MASK BIT(3) +#define M98090_MIXSPR_LINEB_SHIFT 3 +#define M98090_MIXSPR_LINEB_WIDTH 1 +#define M98090_MIXSPR_LINEA_MASK BIT(2) +#define M98090_MIXSPR_LINEA_SHIFT 2 +#define M98090_MIXSPR_LINEA_WIDTH 1 +#define M98090_MIXSPR_DACR_MASK BIT(1) +#define M98090_MIXSPR_DACR_SHIFT 1 +#define M98090_MIXSPR_DACR_WIDTH 1 +#define M98090_MIXSPR_DACL_MASK BIT(0) +#define M98090_MIXSPR_DACL_SHIFT 0 +#define M98090_MIXSPR_DACL_WIDTH 1 +#define M98090_MIXSPR_MASK (63 << 0) +#define M98090_MIXSPR_SHIFT 0 +#define M98090_MIXSPR_WIDTH 6 + +/* + * M98090_REG_LEFT_SPK_VOLUME 0x31 + */ +#define M98090_SPLM_MASK BIT(7) +#define M98090_SPLM_SHIFT 7 +#define M98090_SPLM_WIDTH 1 +#define M98090_SPVOLL_MASK (63 << 0) +#define M98090_SPVOLL_SHIFT 0 +#define M98090_SPVOLL_WIDTH 6 +#define M98090_SPVOLL_NUM 40 + +/* + * M98090_REG_RIGHT_SPK_VOLUME 0x32 + */ +#define M98090_SPRM_MASK BIT(7) +#define M98090_SPRM_SHIFT 7 +#define M98090_SPRM_WIDTH 1 +#define M98090_SPVOLR_MASK (63 << 0) +#define M98090_SPVOLR_SHIFT 0 +#define M98090_SPVOLR_WIDTH 6 +#define M98090_SPVOLR_NUM 40 + +/* + * M98090_REG_RCV_LOUTL_MIXER 0x37 + */ +#define M98090_MIXRCVL_MIC2_MASK BIT(5) +#define M98090_MIXRCVL_MIC2_SHIFT 5 +#define M98090_MIXRCVL_MIC2_WIDTH 1 +#define M98090_MIXRCVL_MIC1_MASK BIT(4) +#define M98090_MIXRCVL_MIC1_SHIFT 4 +#define M98090_MIXRCVL_MIC1_WIDTH 1 +#define M98090_MIXRCVL_LINEB_MASK BIT(3) +#define M98090_MIXRCVL_LINEB_SHIFT 3 +#define M98090_MIXRCVL_LINEB_WIDTH 1 +#define M98090_MIXRCVL_LINEA_MASK BIT(2) +#define M98090_MIXRCVL_LINEA_SHIFT 2 +#define M98090_MIXRCVL_LINEA_WIDTH 1 +#define M98090_MIXRCVL_DACR_MASK BIT(1) +#define M98090_MIXRCVL_DACR_SHIFT 1 +#define M98090_MIXRCVL_DACR_WIDTH 1 +#define M98090_MIXRCVL_DACL_MASK BIT(0) +#define M98090_MIXRCVL_DACL_SHIFT 0 +#define M98090_MIXRCVL_DACL_WIDTH 1 +#define M98090_MIXRCVL_MASK (63 << 0) +#define M98090_MIXRCVL_SHIFT 0 +#define M98090_MIXRCVL_WIDTH 6 + +/* + * M98090_REG_RCV_LOUTL_CONTROL 0x38 + */ +#define M98090_MIXRCVLG_MASK (3 << 0) +#define M98090_MIXRCVLG_SHIFT 0 +#define M98090_MIXRCVLG_WIDTH 2 +#define M98090_MIXRCVLG_NUM BIT(M98090_MIXRCVLG_WIDTH) + +/* + * M98090_REG_RCV_LOUTL_VOLUME 0x39 + */ +#define M98090_RCVLM_MASK BIT(7) +#define M98090_RCVLM_SHIFT 7 +#define M98090_RCVLM_WIDTH 1 +#define M98090_RCVLVOL_MASK (31 << 0) +#define M98090_RCVLVOL_SHIFT 0 +#define M98090_RCVLVOL_WIDTH 5 +#define M98090_RCVLVOL_NUM BIT(M98090_RCVLVOL_WIDTH) + +/* + * M98090_REG_LOUTR_MIXER 0x3A + */ +#define M98090_LINMOD_MASK BIT(7) +#define M98090_LINMOD_SHIFT 7 +#define M98090_LINMOD_WIDTH 1 +#define M98090_MIXRCVR_MIC2_MASK BIT(5) +#define M98090_MIXRCVR_MIC2_SHIFT 5 +#define M98090_MIXRCVR_MIC2_WIDTH 1 +#define M98090_MIXRCVR_MIC1_MASK BIT(4) +#define M98090_MIXRCVR_MIC1_SHIFT 4 +#define M98090_MIXRCVR_MIC1_WIDTH 1 +#define M98090_MIXRCVR_LINEB_MASK BIT(3) +#define M98090_MIXRCVR_LINEB_SHIFT 3 +#define M98090_MIXRCVR_LINEB_WIDTH 1 +#define M98090_MIXRCVR_LINEA_MASK BIT(2) +#define M98090_MIXRCVR_LINEA_SHIFT 2 +#define M98090_MIXRCVR_LINEA_WIDTH 1 +#define M98090_MIXRCVR_DACR_MASK BIT(1) +#define M98090_MIXRCVR_DACR_SHIFT 1 +#define M98090_MIXRCVR_DACR_WIDTH 1 +#define M98090_MIXRCVR_DACL_MASK BIT(0) +#define M98090_MIXRCVR_DACL_SHIFT 0 +#define M98090_MIXRCVR_DACL_WIDTH 1 +#define M98090_MIXRCVR_MASK (63 << 0) +#define M98090_MIXRCVR_SHIFT 0 +#define M98090_MIXRCVR_WIDTH 6 + +/* + * M98090_REG_LOUTR_VOLUME 0x3C + */ +#define M98090_RCVRM_MASK BIT(7) +#define M98090_RCVRM_SHIFT 7 +#define M98090_RCVRM_WIDTH 1 +#define M98090_RCVRVOL_MASK (31 << 0) +#define M98090_RCVRVOL_SHIFT 0 +#define M98090_RCVRVOL_WIDTH 5 +#define M98090_RCVRVOL_NUM BIT(M98090_RCVRVOL_WIDTH) + +/* + * M98090_REG_JACK_DETECT 0x3D + */ +#define M98090_JDETEN_MASK BIT(7) +#define M98090_JDETEN_SHIFT 7 +#define M98090_JDETEN_WIDTH 1 +#define M98090_JDWK_MASK BIT(6) +#define M98090_JDWK_SHIFT 6 +#define M98090_JDWK_WIDTH 1 +#define M98090_JDEB_MASK (3 << 0) +#define M98090_JDEB_SHIFT 0 +#define M98090_JDEB_WIDTH 2 +#define M98090_JDEB_25MS (0 << 0) +#define M98090_JDEB_50MS BIT(0) +#define M98090_JDEB_100MS (2 << 0) +#define M98090_JDEB_200MS (3 << 0) + +/* + * M98090_REG_INPUT_ENABLE 0x3E + */ +#define M98090_MBEN_MASK BIT(4) +#define M98090_MBEN_SHIFT 4 +#define M98090_MBEN_WIDTH 1 +#define M98090_LINEAEN_MASK BIT(3) +#define M98090_LINEAEN_SHIFT 3 +#define M98090_LINEAEN_WIDTH 1 +#define M98090_LINEBEN_MASK BIT(2) +#define M98090_LINEBEN_SHIFT 2 +#define M98090_LINEBEN_WIDTH 1 +#define M98090_ADREN_MASK BIT(1) +#define M98090_ADREN_SHIFT 1 +#define M98090_ADREN_WIDTH 1 +#define M98090_ADLEN_MASK BIT(0) +#define M98090_ADLEN_SHIFT 0 +#define M98090_ADLEN_WIDTH 1 + +/* + * M98090_REG_OUTPUT_ENABLE 0x3F + */ +#define M98090_HPREN_MASK BIT(7) +#define M98090_HPREN_SHIFT 7 +#define M98090_HPREN_WIDTH 1 +#define M98090_HPLEN_MASK BIT(6) +#define M98090_HPLEN_SHIFT 6 +#define M98090_HPLEN_WIDTH 1 +#define M98090_SPREN_MASK BIT(5) +#define M98090_SPREN_SHIFT 5 +#define M98090_SPREN_WIDTH 1 +#define M98090_SPLEN_MASK BIT(4) +#define M98090_SPLEN_SHIFT 4 +#define M98090_SPLEN_WIDTH 1 +#define M98090_RCVLEN_MASK BIT(3) +#define M98090_RCVLEN_SHIFT 3 +#define M98090_RCVLEN_WIDTH 1 +#define M98090_RCVREN_MASK BIT(2) +#define M98090_RCVREN_SHIFT 2 +#define M98090_RCVREN_WIDTH 1 +#define M98090_DAREN_MASK BIT(1) +#define M98090_DAREN_SHIFT 1 +#define M98090_DAREN_WIDTH 1 +#define M98090_DALEN_MASK BIT(0) +#define M98090_DALEN_SHIFT 0 +#define M98090_DALEN_WIDTH 1 + +/* + * M98090_REG_LEVEL_CONTROL 0x40 + */ +#define M98090_ZDENN_MASK BIT(2) +#define M98090_ZDENN_SHIFT 2 +#define M98090_ZDENN_WIDTH 1 +#define M98090_ZDENN_NUM BIT(M98090_ZDENN_WIDTH) +#define M98090_VS2ENN_MASK BIT(1) +#define M98090_VS2ENN_SHIFT 1 +#define M98090_VS2ENN_WIDTH 1 +#define M98090_VS2ENN_NUM BIT(M98090_VS2ENN_WIDTH) +#define M98090_VSENN_MASK BIT(0) +#define M98090_VSENN_SHIFT 0 +#define M98090_VSENN_WIDTH 1 +#define M98090_VSENN_NUM BIT(M98090_VSENN_WIDTH) + +/* + * M98090_REG_BIAS_CONTROL 0x42 + */ +#define M98090_VCM_MODE_MASK BIT(0) +#define M98090_VCM_MODE_SHIFT 0 +#define M98090_VCM_MODE_WIDTH 1 +#define M98090_VCM_MODE_NUM BIT(M98090_VCM_MODE_WIDTH) + +/* + * M98090_REG_DAC_CONTROL 0x43 + */ +#define M98090_PERFMODE_MASK BIT(1) +#define M98090_PERFMODE_SHIFT 1 +#define M98090_PERFMODE_WIDTH 1 +#define M98090_PERFMODE_NUM BIT(M98090_PERFMODE_WIDTH) +#define M98090_DACHP_MASK BIT(0) +#define M98090_DACHP_SHIFT 0 +#define M98090_DACHP_WIDTH 1 +#define M98090_DACHP_NUM BIT(M98090_DACHP_WIDTH) + +/* + * M98090_REG_ADC_CONTROL 0x44 + */ +#define M98090_OSR128_MASK BIT(2) +#define M98090_OSR128_SHIFT 2 +#define M98090_OSR128_WIDTH 1 +#define M98090_ADCDITHER_MASK BIT(1) +#define M98090_ADCDITHER_SHIFT 1 +#define M98090_ADCDITHER_WIDTH 1 +#define M98090_ADCDITHER_NUM BIT(M98090_ADCDITHER_WIDTH) +#define M98090_ADCHP_MASK BIT(0) +#define M98090_ADCHP_SHIFT 0 +#define M98090_ADCHP_WIDTH 1 +#define M98090_ADCHP_NUM BIT(M98090_ADCHP_WIDTH) + +/* + * M98090_REG_DEVICE_SHUTDOWN 0x45 + */ +#define M98090_SHDNN_MASK BIT(7) +#define M98090_SHDNN_SHIFT 7 +#define M98090_SHDNN_WIDTH 1 + +/* + * M98090_REG_REVISION_ID 0xFF + */ +#define M98090_REVID_MASK (255 << 0) +#define M98090_REVID_SHIFT 0 +#define M98090_REVID_WIDTH 8 +#define M98090_REVID_NUM BIT(M98090_REVID_WIDTH) + +/* function prototype */ + +/* + * initialise max98090 sound codec device for the given configuration + * + * @param blob FDT node for codec values + * @param sampling_rate Sampling rate (Hz) + * @param mclk_freq MCLK Frequency (Hz) + * @param bits_per_sample bits per Sample (must be 16 or 24) + * + * @returns -1 for error and 0 Success. + */ +int max98090_init(const void *blob, int sampling_rate, int mclk_freq, + int bits_per_sample); +int max98090_set_sysclk(struct maxim_priv *max98090, uint freq); +int max98090_hw_params(struct maxim_priv *max98090, uint rate, + uint bits_per_sample); +int max98090_device_init(struct maxim_priv *max98090); +int max98090_set_fmt(struct maxim_priv *max98090, int fmt); +#endif diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index 7c37bd0701..99c0e996b4 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -1,112 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * max98095.c -- MAX98095 ALSA SoC Audio driver * * Copyright 2011 Maxim Integrated Products * - * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com) */ #include -#include -#include -#include -#include -#include -#include +#include +#include #include #include #include #include +#include +#include +#include +#include +#include #include "i2s.h" #include "max98095.h" -enum max98095_type { - MAX98095, -}; - -struct max98095_priv { - enum max98095_type devtype; - unsigned int sysclk; - unsigned int rate; - unsigned int fmt; -}; - -static struct sound_codec_info g_codec_info; -struct max98095_priv g_max98095_info; -unsigned int g_max98095_i2c_dev_addr; - /* Index 0 is reserved. */ int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 88200, 96000}; -/* - * Writes value to a device register through i2c - * - * @param reg reg number to be write - * @param data data to be writen to the above registor - * - * @return int value 1 for change, 0 for no change or negative error code. - */ -static int max98095_i2c_write(unsigned int reg, unsigned char data) -{ - debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", - __func__, reg, data); - return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1); -} - -/* - * Read a value from a device register through i2c - * - * @param reg reg number to be read - * @param data address of read data to be stored - * - * @return int value 0 for success, -1 in case of error. - */ -static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data) -{ - int ret; - - ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1); - if (ret != 0) { - debug("%s: Error while reading register %#04x\n", - __func__, reg); - return -1; - } - - return 0; -} - -/* - * update device register bits through i2c - * - * @param reg codec register - * @param mask register mask - * @param value new value - * - * @return int value 0 for success, non-zero error code. - */ -static int max98095_update_bits(unsigned int reg, unsigned char mask, - unsigned char value) -{ - int change, ret = 0; - unsigned char old, new; - - if (max98095_i2c_read(reg, &old) != 0) - return -1; - new = (old & ~mask) | (value & mask); - change = (old != new) ? 1 : 0; - if (change) - ret = max98095_i2c_write(reg, new); - if (ret < 0) - return ret; - - return change; -} - /* * codec mclk clock divider coefficients based on sampling rate * @@ -127,19 +46,19 @@ static int rate_value(int rate, u8 *value) } *value = 1; - return -1; + return -EINVAL; } /* * Sets hw params for max98095 * - * @param max98095 max98095 information pointer + * @param priv max98095 information pointer * @param rate Sampling rate * @param bits_per_sample Bits per sample * - * @return -1 for error and 0 Success. + * @return 0 for success or negative error code. */ -static int max98095_hw_params(struct max98095_priv *max98095, +static int max98095_hw_params(struct maxim_priv *priv, enum en_max_audio_interface aif_id, unsigned int rate, unsigned int bits_per_sample) { @@ -161,40 +80,39 @@ static int max98095_hw_params(struct max98095_priv *max98095, switch (bits_per_sample) { case 16: - error = max98095_update_bits(M98095_DAI_FORMAT, - M98095_DAI_WS, 0); + error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0); break; case 24: - error = max98095_update_bits(M98095_DAI_FORMAT, - M98095_DAI_WS, M98095_DAI_WS); + error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, + M98095_DAI_WS); break; default: debug("%s: Illegal bits per sample %d.\n", __func__, bits_per_sample); - return -1; + return -EINVAL; } if (rate_value(rate, ®val)) { debug("%s: Failed to set sample rate to %d.\n", __func__, rate); - return -1; + return -EINVAL; } - max98095->rate = rate; + priv->rate = rate; - error |= max98095_update_bits(M98095_DAI_CLKMODE, - M98095_CLKMODE_MASK, regval); + error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK, + regval); /* Update sample rate mode */ if (rate < 50000) - error |= max98095_update_bits(M98095_DAI_FILTERS, - M98095_DAI_DHF, 0); + error |= maxim_bic_or(priv, M98095_DAI_FILTERS, + M98095_DAI_DHF, 0); else - error |= max98095_update_bits(M98095_DAI_FILTERS, - M98095_DAI_DHF, M98095_DAI_DHF); + error |= maxim_bic_or(priv, M98095_DAI_FILTERS, + M98095_DAI_DHF, M98095_DAI_DHF); if (error < 0) { debug("%s: Error setting hardware params.\n", __func__); - return -1; + return -EIO; } return 0; @@ -203,18 +121,17 @@ static int max98095_hw_params(struct max98095_priv *max98095, /* * Configures Audio interface system clock for the given frequency * - * @param max98095 max98095 information + * @param priv max98095 information * @param freq Sampling frequency in Hz * - * @return -1 for error and 0 success. + * @return 0 for success or negative error code. */ -static int max98095_set_sysclk(struct max98095_priv *max98095, - unsigned int freq) +static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq) { int error = 0; /* Requested clock frequency is already setup */ - if (freq == max98095->sysclk) + if (freq == priv->sysclk) return 0; /* Setup clocks for slave mode, and using the PLL @@ -223,35 +140,35 @@ static int max98095_set_sysclk(struct max98095_priv *max98095, * 0x03 (when master clk is 40MHz to 60MHz).. */ if ((freq >= 10000000) && (freq < 20000000)) { - error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10); + error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10); } else if ((freq >= 20000000) && (freq < 40000000)) { - error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20); + error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20); } else if ((freq >= 40000000) && (freq < 60000000)) { - error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30); + error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30); } else { debug("%s: Invalid master clock frequency\n", __func__); - return -1; + return -EINVAL; } debug("%s: Clock at %uHz\n", __func__, freq); if (error < 0) - return -1; + return -EIO; - max98095->sysclk = freq; + priv->sysclk = freq; return 0; } /* * Sets Max98095 I2S format * - * @param max98095 max98095 information + * @param priv max98095 information * @param fmt i2S format - supports a subset of the options defined * in i2s.h. * - * @return -1 for error and 0 Success. + * @return 0 for success or negative error code. */ -static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, +static int max98095_set_fmt(struct maxim_priv *priv, int fmt, enum en_max_audio_interface aif_id) { u8 regval = 0; @@ -261,10 +178,10 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, unsigned short M98095_DAI_FORMAT; unsigned short M98095_DAI_CLOCK; - if (fmt == max98095->fmt) + if (fmt == priv->fmt) return 0; - max98095->fmt = fmt; + priv->fmt = fmt; if (aif_id == AIF1) { M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI; @@ -281,10 +198,8 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Slave mode PLL */ - error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI, - 0x80); - error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO, - 0x00); + error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80); + error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00); break; case SND_SOC_DAIFMT_CBM_CFM: /* Set to master mode */ @@ -294,7 +209,7 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, case SND_SOC_DAIFMT_CBM_CFS: default: debug("%s: Clock mode unsupported\n", __func__); - return -1; + return -EINVAL; } switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -305,7 +220,7 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, break; default: debug("%s: Unrecognized format.\n", __func__); - return -1; + return -EINVAL; } switch (fmt & SND_SOC_DAIFMT_INV_MASK) { @@ -322,20 +237,18 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, break; default: debug("%s: Unrecognized inversion settings.\n", __func__); - return -1; + return -EINVAL; } - error |= max98095_update_bits(M98095_DAI_FORMAT, - M98095_DAI_MAS | M98095_DAI_DLY | - M98095_DAI_BCI | M98095_DAI_WCI, - regval); + error |= maxim_bic_or(priv, M98095_DAI_FORMAT, + M98095_DAI_MAS | M98095_DAI_DLY | + M98095_DAI_BCI | M98095_DAI_WCI, regval); - error |= max98095_i2c_write(M98095_DAI_CLOCK, - M98095_DAI_BSEL64); + error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64); if (error < 0) { debug("%s: Error setting i2s format.\n", __func__); - return -1; + return -EIO; } return 0; @@ -344,9 +257,10 @@ static int max98095_set_fmt(struct max98095_priv *max98095, int fmt, /* * resets the audio codec * - * @return -1 for error and 0 success. + * @param priv Private data for driver + * @return 0 for success or negative error code. */ -static int max98095_reset(void) +static int max98095_reset(struct maxim_priv *priv) { int i, ret; @@ -354,13 +268,13 @@ static int max98095_reset(void) * Gracefully reset the DSP core and the codec hardware in a proper * sequence. */ - ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0); + ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0); if (ret != 0) { debug("%s: Failed to reset DSP: %d\n", __func__, ret); return ret; } - ret = max98095_i2c_write(M98095_097_PWR_SYS, 0); + ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0); if (ret != 0) { debug("%s: Failed to reset codec: %d\n", __func__, ret); return ret; @@ -371,7 +285,7 @@ static int max98095_reset(void) * reset hardware control register. */ for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { - ret = max98095_i2c_write(i, 0); + ret = maxim_i2c_write(priv, i, 0); if (ret < 0) { debug("%s: Failed to reset: %d\n", __func__, ret); return ret; @@ -384,132 +298,128 @@ static int max98095_reset(void) /* * Intialise max98095 codec device * - * @param max98095 max98095 information - * - * @returns -1 for error and 0 Success. + * @param priv max98095 information + * @return 0 for success or negative error code. */ -static int max98095_device_init(struct max98095_priv *max98095, - enum en_max_audio_interface aif_id) +static int max98095_device_init(struct maxim_priv *priv) { unsigned char id; - int error = 0; + int ret; + + /* Enable codec clock */ + set_xclkout(); /* reset the codec, the DSP core, and disable all interrupts */ - error = max98095_reset(); - if (error != 0) { + ret = max98095_reset(priv); + if (ret != 0) { debug("Reset\n"); - return error; + return ret; } /* initialize private data */ - max98095->sysclk = -1U; - max98095->rate = -1U; - max98095->fmt = -1U; + priv->sysclk = -1U; + priv->rate = -1U; + priv->fmt = -1U; - error = max98095_i2c_read(M98095_0FF_REV_ID, &id); - if (error < 0) { + ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id); + if (ret < 0) { debug("%s: Failure reading hardware revision: %d\n", __func__, id); - goto err_access; + return ret; } debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A'); - error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV); + return 0; +} + +static int max98095_setup_interface(struct maxim_priv *priv, + enum en_max_audio_interface aif_id) +{ + int error; + + error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV); /* * initialize registers to hardware default configuring audio * interface2 to DAC */ if (aif_id == AIF1) - error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, + error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR, M98095_DAI1L_TO_DACL | M98095_DAI1R_TO_DACR); else - error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, + error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR, M98095_DAI2M_TO_DACL | M98095_DAI2M_TO_DACR); - error |= max98095_i2c_write(M98095_092_PWR_EN_OUT, + error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); - error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL); + error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL); if (aif_id == AIF1) - error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG, + error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG, M98095_S1NORMAL | M98095_SDATA); else - error |= max98095_i2c_write(M98095_036_DAI2_IOCFG, + error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG, M98095_S2NORMAL | M98095_SDATA); /* take the codec out of the shut down */ - error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN, - M98095_SHDNRUN); - /* route DACL and DACR output to HO and Spekers */ - error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */ - error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */ - error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */ - error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */ + error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN, + M98095_SHDNRUN); + /* + * route DACL and DACR output to HO and Speakers + * Ordering: DACL, DACR, DACL, DACR + */ + error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01); + error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01); + error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01); + error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01); /* power Enable */ - error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3); + error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3); /* set Volume */ - error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15); - error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15); - error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16); - error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16); + error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15); + error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15); + error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16); + error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16); /* Enable DAIs */ - error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30); + error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30); if (aif_id == AIF1) - error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01); + error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01); else - error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07); + error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07); -err_access: if (error < 0) - return -1; + return -EIO; return 0; } -static int max98095_do_init(struct sound_codec_info *pcodec_info, +static int max98095_do_init(struct maxim_priv *priv, enum en_max_audio_interface aif_id, int sampling_rate, int mclk_freq, int bits_per_sample) { int ret = 0; - /* Enable codec clock */ - set_xclkout(); - - /* shift the device address by 1 for 7 bit addressing */ - g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1; - - if (pcodec_info->codec_type == CODEC_MAX_98095) { - g_max98095_info.devtype = MAX98095; - } else { - debug("%s: Codec id [%d] not defined\n", __func__, - pcodec_info->codec_type); - return -1; - } - - ret = max98095_device_init(&g_max98095_info, aif_id); + ret = max98095_setup_interface(priv, aif_id); if (ret < 0) { - debug("%s: max98095 codec chip init failed\n", __func__); + debug("%s: max98095 setup interface failed\n", __func__); return ret; } - ret = max98095_set_sysclk(&g_max98095_info, mclk_freq); + ret = max98095_set_sysclk(priv, mclk_freq); if (ret < 0) { debug("%s: max98095 codec set sys clock failed\n", __func__); return ret; } - ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate, + ret = max98095_hw_params(priv, aif_id, sampling_rate, bits_per_sample); if (ret == 0) { - ret = max98095_set_fmt(&g_max98095_info, - SND_SOC_DAIFMT_I2S | + ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS, aif_id); @@ -518,76 +428,45 @@ static int max98095_do_init(struct sound_codec_info *pcodec_info, return ret; } -static int get_max98095_codec_values(struct sound_codec_info *pcodec_info, - const void *blob) +static int max98095_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, + uint channels) { - int error = 0; -#if CONFIG_IS_ENABLED(OF_CONTROL) - enum fdt_compat_id compat; - int node; - int parent; + struct maxim_priv *priv = dev_get_priv(dev); - /* Get the node from FDT for codec */ - node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for codec in device tree\n"); - debug("node = %d\n", node); - return -1; - } + return max98095_do_init(priv, interface, rate, mclk_freq, + bits_per_sample); +} - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -1; - } +static int max98095_probe(struct udevice *dev) +{ + struct maxim_priv *priv = dev_get_priv(dev); + int ret; - compat = fdtdec_lookup(blob, parent); - switch (compat) { - case COMPAT_SAMSUNG_S3C2440_I2C: - pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); - error |= pcodec_info->i2c_bus; - debug("i2c bus = %d\n", pcodec_info->i2c_bus); - pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, - "reg", 0); - error |= pcodec_info->i2c_dev_addr; - debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr); - break; - default: - debug("%s: Unknown compat id %d\n", __func__, compat); - return -1; - } -#else - pcodec_info->i2c_bus = AUDIO_I2C_BUS; - pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; - debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); -#endif - pcodec_info->codec_type = CODEC_MAX_98095; - if (error == -1) { - debug("fail to get max98095 codec node properties\n"); - return -1; + priv->dev = dev; + ret = max98095_device_init(priv); + if (ret < 0) { + debug("%s: max98095 codec chip init failed\n", __func__); + return ret; } return 0; } -/* max98095 Device Initialisation */ -int max98095_init(const void *blob, enum en_max_audio_interface aif_id, - int sampling_rate, int mclk_freq, - int bits_per_sample) -{ - int ret; - int old_bus = i2c_get_bus_num(); - struct sound_codec_info *pcodec_info = &g_codec_info; +static const struct audio_codec_ops max98095_ops = { + .set_params = max98095_set_params, +}; - if (get_max98095_codec_values(pcodec_info, blob) < 0) { - debug("FDT Codec values failed\n"); - return -1; - } +static const struct udevice_id max98095_ids[] = { + { .compatible = "maxim,max98095" }, + { } +}; - i2c_set_bus_num(pcodec_info->i2c_bus); - ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq, - bits_per_sample); - i2c_set_bus_num(old_bus); - - return ret; -} +U_BOOT_DRIVER(max98095) = { + .name = "max98095", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98095_ids, + .probe = max98095_probe, + .ops = &max98095_ops, + .priv_auto_alloc_size = sizeof(struct maxim_priv), +}; diff --git a/drivers/sound/max98095.h b/drivers/sound/max98095.h index 44b1e3a97b..1521f3f02f 100644 --- a/drivers/sound/max98095.h +++ b/drivers/sound/max98095.h @@ -1,19 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * max98095.h -- MAX98095 ALSA SoC Audio driver * * Copyright 2011 Maxim Integrated Products - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _MAX98095_H #define _MAX98095_H +#include "maxim_codec.h" + /* Available audio interface ports in wm8994 codec */ enum en_max_audio_interface { - AIF1 = 1, + AIF1, AIF2, }; diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c new file mode 100644 index 0000000000..dcaf081988 --- /dev/null +++ b/drivers/sound/maxim_codec.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * maxim_codec.c -- MAXIM CODEC Common driver + * + * Copyright 2011 Maxim Integrated Products + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "maxim_codec.h" + +/* + * Writes value to a device register through i2c + * + * @param priv Private data for driver + * @param reg reg number to be write + * @param data data to be writen to the above registor + * + * @return int value 1 for change, 0 for no change or negative error code. + */ +int maxim_i2c_write(struct maxim_priv *priv, unsigned int reg, + unsigned char data) +{ + debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", + __func__, reg, data); + return dm_i2c_write(priv->dev, reg, &data, 1); +} + +/* + * Read a value from a device register through i2c + * + * @param priv Private data for driver + * @param reg reg number to be read + * @param data address of read data to be stored + * + * @return int value 0 for success, -1 in case of error. + */ +unsigned int maxim_i2c_read(struct maxim_priv *priv, unsigned int reg, + unsigned char *data) +{ + int ret; + + return dm_i2c_read(priv->dev, reg, data, 1); + if (ret != 0) { + debug("%s: Error while reading register %#04x\n", + __func__, reg); + return -1; + } + + return 0; +} + +/* + * update device register bits through i2c + * + * @param priv Private data for driver + * @param reg codec register + * @param mask register mask + * @param value new value + * + * @return int value 0 for success, non-zero error code. + */ +int maxim_bic_or(struct maxim_priv *priv, unsigned int reg, unsigned char mask, + unsigned char value) +{ + int change, ret = 0; + unsigned char old, new; + + if (maxim_i2c_read(priv, reg, &old) != 0) + return -1; + new = (old & ~mask) | (value & mask); + change = (old != new) ? 1 : 0; + if (change) + ret = maxim_i2c_write(priv, reg, new); + if (ret < 0) + return ret; + + return change; +} diff --git a/drivers/sound/maxim_codec.h b/drivers/sound/maxim_codec.h new file mode 100644 index 0000000000..a3128e0bb7 --- /dev/null +++ b/drivers/sound/maxim_codec.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * maxim_codec.h -- MAXIM codec common interface file + * + * Copyright (C) 2013 Samsung Electronics + * D Krishna Mohan + */ + +#ifndef __MAXIM_COMMON_H__ +#define __MAXIM_COMMON_H__ + +enum maxim_codec_type { + MAX98095, + MAX98090, +}; + +struct maxim_priv { + enum maxim_codec_type devtype; + unsigned int sysclk; + unsigned int rate; + unsigned int fmt; + struct udevice *dev; +}; + +#define MAXIM_AUDIO_I2C_BUS 7 +#define MAXIM_AUDIO_I2C_REG_98095 0x22 + +#define MAXIM_AUDIO_I2C_REG MAXIM_AUDIO_I2C_REG_98095 + +/* + * Writes value to a device register through i2c + * + * @param priv Private data for driver + * @param reg reg number to be write + * @param data data to be writen to the above registor + * + * @return int value 1 for change, 0 for no change or negative error code. + */ +int maxim_i2c_write(struct maxim_priv *priv, unsigned int reg, + unsigned char data); + +/* + * Read a value from a device register through i2c + * + * @param priv Private data for driver + * @param reg reg number to be read + * @param data address of read data to be stored + * + * @return int value 0 for success, -1 in case of error. + */ +unsigned int maxim_i2c_read(struct maxim_priv *priv, unsigned int reg, + unsigned char *data); + +/* + * update device register bits through i2c + * + * @param priv Private data for driver + * @param reg codec register + * @param mask register mask + * @param value new value + * + * @return int value 0 for success, non-zero error code. + */ +int maxim_bic_or(struct maxim_priv *priv, unsigned int reg, unsigned char mask, + unsigned char value); + +#endif /* __MAXIM_COMMON_H__ */ diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index f39abf5e2a..c19e08e7e3 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -4,13 +4,14 @@ * R. Chandrasekar */ +#include +#include +#include +#include #include #include #include #include -#include -#include -#include #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) @@ -111,7 +112,7 @@ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) * @param flush Tx fifo flush command (0x00 - do not flush * 0x80 - flush tx fifo) */ -void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) +static void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) { /* Flush the FIFO */ setbits_le32(&i2s_reg->fic, flush); @@ -126,7 +127,7 @@ void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) * * @return int value 0 for success, -1 in case of error */ -int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) +static int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) { unsigned int mod = readl(&i2s_reg->mod); @@ -148,7 +149,7 @@ int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) * * @return int value 0 for success, -1 in case of error */ -int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) +static int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) { unsigned int mod = readl(&i2s_reg->mod); unsigned int tmp = 0; @@ -170,7 +171,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) default: debug("%s: Invalid format priority [0x%x]\n", __func__, (fmt & SND_SOC_DAIFMT_FORMAT_MASK)); - return -1; + return -ERANGE; } /* @@ -189,7 +190,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) default: debug("%s: Invalid clock ploarity input [0x%x]\n", __func__, (fmt & SND_SOC_DAIFMT_INV_MASK)); - return -1; + return -ERANGE; } switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -201,13 +202,13 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT); if (ret != 0) { debug("%s:set i2s clock direction failed\n", __func__); - return -1; + return ret; } break; default: debug("%s: Invalid master selection [0x%x]\n", __func__, (fmt & SND_SOC_DAIFMT_MASTER_MASK)); - return -1; + return -ERANGE; } mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE); @@ -225,7 +226,7 @@ int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) * * @return int value 0 for success, -1 in case of error */ -int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc) +static int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc) { unsigned int mod = readl(&i2s_reg->mod); @@ -248,43 +249,43 @@ int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc) default: debug("%s: Invalid sample size input [0x%x]\n", __func__, blc); - return -1; + return -ERANGE; } writel(mod, &i2s_reg->mod); return 0; } -int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data, - unsigned long data_size) +int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, + uint data_size) { + struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; + u32 *ptr; int i; int start; - struct i2s_reg *i2s_reg = - (struct i2s_reg *)pi2s_tx->base_address; if (data_size < FIFO_LENGTH) { debug("%s : Invalid data size\n", __func__); - return -1; /* invalid pcm data size */ + return -ENODATA; /* invalid pcm data size */ } /* fill the tx buffer before stating the tx transmit */ - for (i = 0; i < FIFO_LENGTH; i++) - writel(*data++, &i2s_reg->txd); + for (i = 0, ptr = data; i < FIFO_LENGTH; i++) + writel(*ptr++, &i2s_reg->txd); - data_size -= FIFO_LENGTH; + data_size -= sizeof(*ptr) * FIFO_LENGTH; i2s_txctrl(i2s_reg, I2S_TX_ON); while (data_size > 0) { start = get_timer(0); if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { - writel(*data++, &i2s_reg->txd); - data_size--; + writel(*ptr++, &i2s_reg->txd); + data_size -= sizeof(*ptr); } else { if (get_timer(start) > TIMEOUT_I2S_TX) { i2s_txctrl(i2s_reg, I2S_TX_OFF); debug("%s: I2S Transfer Timeout\n", __func__); - return -1; + return -ETIMEDOUT; } } } @@ -293,11 +294,11 @@ int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data, return 0; } -int i2s_tx_init(struct i2stx_info *pi2s_tx) +int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) { int ret; - struct i2s_reg *i2s_reg = - (struct i2s_reg *)pi2s_tx->base_address; + struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; + if (pi2s_tx->id == 0) { /* Initialize GPIO for I2S-0 */ exynos_pinmux_config(PERIPH_ID_I2S0, 0); @@ -312,20 +313,20 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx) ret = set_epll_clk(pi2s_tx->audio_pll_clk); } else { debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id); - return -1; + return -ERANGE; } - if (ret != 0) { + if (ret) { debug("%s: epll clock set rate failed\n", __func__); - return -1; + return ret; } /* Select Clk Source for Audio 0 or 1 */ ret = set_i2s_clk_source(pi2s_tx->id); - if (ret == -1) { + if (ret) { debug("%s: unsupported clock for i2s-%d\n", __func__, pi2s_tx->id); - return -1; + return ret; } if (pi2s_tx->id == 0) { @@ -341,21 +342,21 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx) (pi2s_tx->samplingrate * (pi2s_tx->rfs)), pi2s_tx->id); } - if (ret == -1) { + if (ret) { debug("%s: unsupported prescalar for i2s-%d\n", __func__, pi2s_tx->id); - return -1; + return ret; } /* Configure I2s format */ - ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBM_CFM)); + ret = i2s_set_fmt(i2s_reg, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); if (ret == 0) { i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs); ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample); if (ret != 0) { debug("%s:set sample rate failed\n", __func__); - return -1; + return ret; } i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs); @@ -368,3 +369,87 @@ int i2s_tx_init(struct i2stx_info *pi2s_tx) return ret; } + +static int samsung_i2s_tx_data(struct udevice *dev, void *data, uint data_size) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + + return i2s_transfer_tx_data(priv, data, data_size); +} + +static int samsung_i2s_probe(struct udevice *dev) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + + return i2s_tx_init(priv); +} + +static int samsung_i2s_ofdata_to_platdata(struct udevice *dev) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + ulong base; + + /* + * Get the pre-defined sound specific values from FDT. + * All of these are expected to be correct otherwise + * wrong register values in i2s setup parameters + * may result in no sound play. + */ + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Missing i2s base\n", __func__); + return -EINVAL; + } + priv->base_address = base; + + if (dev_read_u32u(dev, "samsung,i2s-epll-clock-frequency", + &priv->audio_pll_clk)) + goto err; + debug("audio_pll_clk = %d\n", priv->audio_pll_clk); + if (dev_read_u32u(dev, "samsung,i2s-sampling-rate", + &priv->samplingrate)) + goto err; + debug("samplingrate = %d\n", priv->samplingrate); + if (dev_read_u32u(dev, "samsung,i2s-bits-per-sample", + &priv->bitspersample)) + goto err; + debug("bitspersample = %d\n", priv->bitspersample); + if (dev_read_u32u(dev, "samsung,i2s-channels", &priv->channels)) + goto err; + debug("channels = %d\n", priv->channels); + if (dev_read_u32u(dev, "samsung,i2s-lr-clk-framesize", &priv->rfs)) + goto err; + debug("rfs = %d\n", priv->rfs); + if (dev_read_u32u(dev, "samsung,i2s-bit-clk-framesize", &priv->bfs)) + goto err; + debug("bfs = %d\n", priv->bfs); + + if (dev_read_u32u(dev, "samsung,i2s-id", &priv->id)) + goto err; + debug("id = %d\n", priv->id); + + return 0; + +err: + debug("fail to get sound i2s node properties\n"); + + return -EINVAL; +} + +static const struct i2s_ops samsung_i2s_ops = { + .tx_data = samsung_i2s_tx_data, +}; + +static const struct udevice_id samsung_i2s_ids[] = { + { .compatible = "samsung,s5pv210-i2s" }, + { } +}; + +U_BOOT_DRIVER(samsung_i2s) = { + .name = "samsung_i2s", + .id = UCLASS_I2S, + .of_match = samsung_i2s_ids, + .probe = samsung_i2s_probe, + .ofdata_to_platdata = samsung_i2s_ofdata_to_platdata, + .ops = &samsung_i2s_ops, +}; diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c new file mode 100644 index 0000000000..1d711c8732 --- /dev/null +++ b/drivers/sound/samsung_sound.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google, LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +static int samsung_sound_setup(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s); + int ret; + + if (uc_priv->setup_done) + return -EALREADY; + ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id, + i2c_priv->samplingrate, + i2c_priv->samplingrate * i2c_priv->rfs, + i2c_priv->bitspersample, + i2c_priv->channels); + if (ret) + return ret; + uc_priv->setup_done = true; + + return 0; +} + +static int samsung_sound_play(struct udevice *dev, void *data, uint data_size) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + + return i2s_tx_data(uc_priv->i2s, data, data_size); +} + +static int samsung_sound_probe(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct ofnode_phandle_args args; + struct gpio_desc en_gpio; + ofnode node; + int ret; + + ret = gpio_request_by_name(dev, "codec-enable-gpio", 0, &en_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* Turn on the GPIO which connects to the codec's "enable" line. */ + if (!ret) + gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE); + + ret = uclass_get_device_by_phandle(UCLASS_AUDIO_CODEC, dev, + "samsung,audio-codec", + &uc_priv->codec); + if (ret) { + debug("Failed to probe audio codec\n"); + return ret; + } + node = ofnode_find_subnode(dev_ofnode(dev), "cpu"); + if (!ofnode_valid(node)) { + debug("Failed to find /cpu subnode\n"); + return -EINVAL; + } + ret = ofnode_parse_phandle_with_args(node, "sound-dai", + "#sound-dai-cells", 0, 0, &args); + if (ret) { + debug("Cannot find phandle: %d\n", ret); + return ret; + } + ret = uclass_get_device_by_ofnode(UCLASS_I2S, args.node, &uc_priv->i2s); + if (ret) { + debug("Cannot find i2s: %d\n", ret); + return ret; + } + debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, + uc_priv->codec->name, uc_priv->i2s->name); + + return 0; +} + +static const struct sound_ops samsung_sound_ops = { + .setup = samsung_sound_setup, + .play = samsung_sound_play, +}; + +static const struct udevice_id samsung_sound_ids[] = { + { .compatible = "google,snow-audio-max98095" }, + { .compatible = "google,spring-audio-max98095" }, + { .compatible = "samsung,smdk5420-audio-wm8994" }, + { .compatible = "google,peach-audio-max98090" }, + { } +}; + +U_BOOT_DRIVER(samsung_sound) = { + .name = "samsung_sound", + .id = UCLASS_SOUND, + .of_match = samsung_sound_ids, + .probe = samsung_sound_probe, + .ops = &samsung_sound_ops, +}; diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c index 94eff54282..b0b07f3239 100644 --- a/drivers/sound/sandbox.c +++ b/drivers/sound/sandbox.c @@ -4,19 +4,185 @@ */ #include -#include +#include +#include +#include +#include #include -int sound_play(uint32_t msec, uint32_t frequency) +struct sandbox_codec_priv { + int interface; + int rate; + int mclk_freq; + int bits_per_sample; + uint channels; +}; + +struct sandbox_i2s_priv { + int sum; /* Use to sum the provided audio data */ +}; + +struct sandbox_sound_priv { + int setup_called; + int sum; /* Use to sum the provided audio data */ +}; + +void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep, + int *mclk_freqp, int *bits_per_samplep, + uint *channelsp) { - sandbox_sdl_sound_start(frequency); - mdelay(msec); - sandbox_sdl_sound_stop(); + struct sandbox_codec_priv *priv = dev_get_priv(dev); + + *interfacep = priv->interface; + *ratep = priv->rate; + *mclk_freqp = priv->mclk_freq; + *bits_per_samplep = priv->bits_per_sample; + *channelsp = priv->channels; +} + +int sandbox_get_i2s_sum(struct udevice *dev) +{ + struct sandbox_i2s_priv *priv = dev_get_priv(dev); + + return priv->sum; +} + +int sandbox_get_setup_called(struct udevice *dev) +{ + struct sandbox_sound_priv *priv = dev_get_priv(dev); + + return priv->setup_called; +} + +int sandbox_get_sound_sum(struct udevice *dev) +{ + struct sandbox_sound_priv *priv = dev_get_priv(dev); + + return priv->sum; +} + +static int sandbox_codec_set_params(struct udevice *dev, int interface, + int rate, int mclk_freq, + int bits_per_sample, uint channels) +{ + struct sandbox_codec_priv *priv = dev_get_priv(dev); + + priv->interface = interface; + priv->rate = rate; + priv->mclk_freq = mclk_freq; + priv->bits_per_sample = bits_per_sample; + priv->channels = channels; return 0; } -int sound_init(const void *blob) +static int sandbox_i2s_tx_data(struct udevice *dev, void *data, + uint data_size) { - return sandbox_sdl_sound_init(); + struct sandbox_i2s_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < data_size; i++) + priv->sum += ((uint8_t *)data)[i]; + + return sandbox_sdl_sound_play(data, data_size); } + +static int sandbox_i2s_probe(struct udevice *dev) +{ + struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev); + + /* Use hard-coded values here */ + uc_priv->rfs = 256; + uc_priv->bfs = 32; + uc_priv->audio_pll_clk = 192000000; + uc_priv->samplingrate = 48000; + uc_priv->bitspersample = 16; + uc_priv->channels = 2; + uc_priv->id = 1; + + /* Ignore any error here - we'll just have no sound */ + sandbox_sdl_sound_init(uc_priv->samplingrate, uc_priv->channels); + + return 0; +} + +static int sandbox_sound_setup(struct udevice *dev) +{ + struct sandbox_sound_priv *priv = dev_get_priv(dev); + + priv->setup_called++; + + return 0; +} + +static int sandbox_sound_play(struct udevice *dev, void *data, uint data_size) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct sandbox_sound_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < data_size; i++) + priv->sum += ((uint8_t *)data)[i]; + + return i2s_tx_data(uc_priv->i2s, data, data_size); +} + +static int sandbox_sound_probe(struct udevice *dev) +{ + return sound_find_codec_i2s(dev); +} + +static const struct audio_codec_ops sandbox_codec_ops = { + .set_params = sandbox_codec_set_params, +}; + +static const struct udevice_id sandbox_codec_ids[] = { + { .compatible = "sandbox,audio-codec" }, + { } +}; + +U_BOOT_DRIVER(sandbox_codec) = { + .name = "sandbox_codec", + .id = UCLASS_AUDIO_CODEC, + .of_match = sandbox_codec_ids, + .ops = &sandbox_codec_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_codec_priv), +}; + +static const struct i2s_ops sandbox_i2s_ops = { + .tx_data = sandbox_i2s_tx_data, +}; + +static const struct udevice_id sandbox_i2s_ids[] = { + { .compatible = "sandbox,i2s" }, + { } +}; + +U_BOOT_DRIVER(sandbox_i2s) = { + .name = "sandbox_i2s", + .id = UCLASS_I2S, + .of_match = sandbox_i2s_ids, + .ops = &sandbox_i2s_ops, + .probe = sandbox_i2s_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_i2s_priv), +}; + +static const struct sound_ops sandbox_sound_ops = { + .setup = sandbox_sound_setup, + .play = sandbox_sound_play, +}; + +static const struct udevice_id sandbox_sound_ids[] = { + { .compatible = "sandbox,sound" }, + { } +}; + +U_BOOT_DRIVER(sandbox_sound) = { + .name = "sandbox_sound", + .id = UCLASS_SOUND, + .of_match = sandbox_sound_ids, + .ops = &sandbox_sound_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_sound_priv), + .probe = sandbox_sound_probe, +}; diff --git a/drivers/sound/sound-i2s.c b/drivers/sound/sound-i2s.c deleted file mode 100644 index 9f09e3bf93..0000000000 --- a/drivers/sound/sound-i2s.c +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * R. Chandrasekar - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "wm8994.h" -#include "max98095.h" - -/* defines */ -#define SOUND_400_HZ 400 -#define SOUND_BITS_IN_BYTE 8 - -static struct i2stx_info g_i2stx_pri; - -/* - * get_sound_i2s_values gets values for i2s parameters - * - * @param i2stx_info i2s transmitter transfer param structure - * @param blob FDT blob if enabled else NULL - */ -static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob) -{ - int node; - int error = 0; - int base; - - node = fdt_path_offset(blob, "i2s"); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - return -1; - } - - /* - * Get the pre-defined sound specific values from FDT. - * All of these are expected to be correct otherwise - * wrong register values in i2s setup parameters - * may result in no sound play. - */ - base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) { - debug("%s: Missing i2s base\n", __func__); - return -1; - } - i2s->base_address = base; - - i2s->audio_pll_clk = fdtdec_get_int(blob, - node, "samsung,i2s-epll-clock-frequency", -1); - error |= i2s->audio_pll_clk; - debug("audio_pll_clk = %d\n", i2s->audio_pll_clk); - i2s->samplingrate = fdtdec_get_int(blob, - node, "samsung,i2s-sampling-rate", -1); - error |= i2s->samplingrate; - debug("samplingrate = %d\n", i2s->samplingrate); - i2s->bitspersample = fdtdec_get_int(blob, - node, "samsung,i2s-bits-per-sample", -1); - error |= i2s->bitspersample; - debug("bitspersample = %d\n", i2s->bitspersample); - i2s->channels = fdtdec_get_int(blob, - node, "samsung,i2s-channels", -1); - error |= i2s->channels; - debug("channels = %d\n", i2s->channels); - i2s->rfs = fdtdec_get_int(blob, - node, "samsung,i2s-lr-clk-framesize", -1); - error |= i2s->rfs; - debug("rfs = %d\n", i2s->rfs); - i2s->bfs = fdtdec_get_int(blob, - node, "samsung,i2s-bit-clk-framesize", -1); - error |= i2s->bfs; - debug("bfs = %d\n", i2s->bfs); - - i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1); - error |= i2s->id; - debug("id = %d\n", i2s->id); - - if (error == -1) { - debug("fail to get sound i2s node properties\n"); - return -1; - } - - return 0; -} - -/* - * Init codec - * - * @param blob FDT blob - * @param pi2s_tx i2s parameters required by codec - * @return int value, 0 for success - */ -static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) -{ - int ret; - const char *codectype; - int node; - - /* Get the node from FDT for sound */ - node = fdt_path_offset(blob, "i2s"); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for sound in device tree\n"); - debug("node = %d\n", node); - return -1; - } - - /* - * Get the pre-defined sound codec specific values from FDT. - * All of these are expected to be correct otherwise sound - * can not be played - */ - codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL); - debug("device = %s\n", codectype); - if (!strcmp(codectype, "wm8994")) { - /* Check the codec type and initialise the same */ - ret = wm8994_init(blob, pi2s_tx->id + 1, - pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample, pi2s_tx->channels); - } else if (!strcmp(codectype, "max98095")) { - ret = max98095_init(blob, pi2s_tx->id + 1, - pi2s_tx->samplingrate, - (pi2s_tx->samplingrate * (pi2s_tx->rfs)), - pi2s_tx->bitspersample); - } else { - debug("%s: Unknown codec type %s\n", __func__, codectype); - return -1; - } - - if (ret) { - debug("%s: Codec init failed\n", __func__); - return -1; - } - - return 0; -} - -int sound_init(const void *blob) -{ - int ret; - struct i2stx_info *pi2s_tx = &g_i2stx_pri; - - /* Get the I2S Values */ - if (get_sound_i2s_values(pi2s_tx, blob) < 0) { - debug(" FDT I2S values failed\n"); - return -1; - } - - if (codec_init(blob, pi2s_tx) < 0) { - debug(" Codec init failed\n"); - return -1; - } - - ret = i2s_tx_init(pi2s_tx); - if (ret) { - debug("%s: Failed to init i2c transmit: ret=%d\n", __func__, - ret); - return ret; - } - - - return ret; -} - -int sound_play(uint32_t msec, uint32_t frequency) -{ - unsigned int *data; - unsigned long data_size; - unsigned int ret = 0; - - /*Buffer length computation */ - data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels; - data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE); - data = malloc(data_size); - - if (data == NULL) { - debug("%s: malloc failed\n", __func__); - return -1; - } - - sound_create_square_wave((unsigned short *)data, - data_size / sizeof(unsigned short), - frequency); - - while (msec >= 1000) { - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, - (data_size / sizeof(int))); - msec -= 1000; - } - if (msec) { - unsigned long size = - (data_size * msec) / (sizeof(int) * 1000); - - ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size); - } - - free(data); - - return ret; -} diff --git a/drivers/sound/sound-uclass.c b/drivers/sound/sound-uclass.c new file mode 100644 index 0000000000..2b83626889 --- /dev/null +++ b/drivers/sound/sound-uclass.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include + +#define SOUND_BITS_IN_BYTE 8 + +int sound_setup(struct udevice *dev) +{ + struct sound_ops *ops = sound_get_ops(dev); + + if (!ops->setup) + return -ENOSYS; + + return ops->setup(dev); +} + +int sound_play(struct udevice *dev, void *data, uint data_size) +{ + struct sound_ops *ops = sound_get_ops(dev); + + if (!ops->play) + return -ENOSYS; + + return ops->play(dev, data, data_size); +} + +int sound_beep(struct udevice *dev, int msecs, int frequency_hz) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct i2s_uc_priv *i2s_uc_priv = dev_get_uclass_priv(uc_priv->i2s); + unsigned short *data; + uint data_size; + int ret; + + ret = sound_setup(dev); + if (ret && ret != -EALREADY) + return ret; + + /* Buffer length computation */ + data_size = i2s_uc_priv->samplingrate * i2s_uc_priv->channels; + data_size *= (i2s_uc_priv->bitspersample / SOUND_BITS_IN_BYTE); + data = malloc(data_size); + if (!data) { + debug("%s: malloc failed\n", __func__); + return -ENOMEM; + } + + sound_create_square_wave(i2s_uc_priv->samplingrate, data, data_size, + frequency_hz, i2s_uc_priv->channels); + + while (msecs >= 1000) { + ret = sound_play(dev, data, data_size); + msecs -= 1000; + } + if (msecs) { + unsigned long size = + (data_size * msecs) / (sizeof(int) * 1000); + + ret = sound_play(dev, data, size); + } + + free(data); + + return ret; +} + +int sound_find_codec_i2s(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct ofnode_phandle_args args; + ofnode node; + int ret; + + /* First the codec */ + node = ofnode_find_subnode(dev_ofnode(dev), "codec"); + if (!ofnode_valid(node)) { + debug("Failed to find /cpu subnode\n"); + return -EINVAL; + } + ret = ofnode_parse_phandle_with_args(node, "sound-dai", + "#sound-dai-cells", 0, 0, &args); + if (ret) { + debug("Cannot find phandle: %d\n", ret); + return ret; + } + ret = uclass_get_device_by_ofnode(UCLASS_AUDIO_CODEC, args.node, + &uc_priv->codec); + if (ret) { + debug("Cannot find codec: %d\n", ret); + return ret; + } + + /* Now the i2s */ + node = ofnode_find_subnode(dev_ofnode(dev), "cpu"); + if (!ofnode_valid(node)) { + debug("Failed to find /cpu subnode\n"); + return -EINVAL; + } + ret = ofnode_parse_phandle_with_args(node, "sound-dai", + "#sound-dai-cells", 0, 0, &args); + if (ret) { + debug("Cannot find phandle: %d\n", ret); + return ret; + } + ret = uclass_get_device_by_ofnode(UCLASS_I2S, args.node, &uc_priv->i2s); + if (ret) { + debug("Cannot find i2s: %d\n", ret); + return ret; + } + debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, + uc_priv->codec->name, uc_priv->i2s->name); + + return 0; +} + +UCLASS_DRIVER(sound) = { + .id = UCLASS_SOUND, + .name = "sound", + .per_device_auto_alloc_size = sizeof(struct sound_uc_priv), +}; diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index 969408186f..dd3f9db4f7 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -7,11 +7,11 @@ #include #include -void sound_create_square_wave(unsigned short *data, int size, uint32_t freq) +void sound_create_square_wave(uint sample_rate, unsigned short *data, int size, + uint freq, uint channels) { - const int sample = 48000; const unsigned short amplitude = 16000; /* between 1 and 32767 */ - const int period = freq ? sample / freq : 0; + const int period = freq ? sample_rate / freq : 0; const int half = period / 2; assert(freq); @@ -21,16 +21,17 @@ void sound_create_square_wave(unsigned short *data, int size, uint32_t freq) size--; while (size) { - int i; + int i, j; + for (i = 0; size && i < half; i++) { size -= 2; - *data++ = amplitude; - *data++ = amplitude; + for (j = 0; j < channels; j++) + *data++ = amplitude; } for (i = 0; size && i < period - half; i++) { size -= 2; - *data++ = -amplitude; - *data++ = -amplitude; + for (j = 0; j < channels; j++) + *data++ = -amplitude; } } } diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c index aaaa3241aa..b290c4e879 100644 --- a/drivers/sound/wm8994.c +++ b/drivers/sound/wm8994.c @@ -4,15 +4,17 @@ * R. Chandrasekar */ #include -#include -#include -#include -#include +#include +#include #include #include #include #include #include +#include +#include +#include +#include #include #include "wm8994.h" #include "wm8994_registers.h" @@ -38,6 +40,7 @@ struct wm8994_priv { int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */ int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */ struct wm8994_fll_config fll[2]; /* fll config to configure fll */ + struct udevice *dev; }; /* wm 8994 supported sampling rate values */ @@ -60,29 +63,17 @@ static int bclk_divs[] = { 640, 880, 960, 1280, 1760, 1920 }; -static struct wm8994_priv g_wm8994_info; -static unsigned char g_wm8994_i2c_dev_addr; -static struct sound_codec_info g_codec_info; - -/* - * Initialise I2C for wm 8994 - * - * @param bus no i2c bus number in which wm8994 is connected - */ -static void wm8994_i2c_init(int bus_no) -{ - i2c_set_bus_num(bus_no); -} - /* * Writes value to a device register through i2c * + * @param priv Private data for driver * @param reg reg number to be write * @param data data to be writen to the above registor * * @return int value 1 for change, 0 for no change or negative error code. */ -static int wm8994_i2c_write(unsigned int reg, unsigned short data) +static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg, + unsigned short data) { unsigned char val[2]; @@ -90,23 +81,25 @@ static int wm8994_i2c_write(unsigned int reg, unsigned short data) val[1] = (unsigned char)(data & 0xff); debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); - return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2); + return dm_i2c_write(priv->dev, reg, val, 2); } /* * Read a value from a device register through i2c * + * @param priv Private data for driver * @param reg reg number to be read * @param data address of read data to be stored * * @return int value 0 for success, -1 in case of error. */ -static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) +static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg, + unsigned short *data) { unsigned char val[2]; int ret; - ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2); + ret = dm_i2c_read(priv->dev, reg, val, 1); if (ret != 0) { debug("%s: Error while reading register %#04x\n", __func__, reg); @@ -123,6 +116,7 @@ static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) /* * update device register bits through i2c * + * @param priv Private data for driver * @param reg codec register * @param mask register mask * @param value new value @@ -130,18 +124,18 @@ static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) * @return int value 1 if change in the register value, * 0 for no change or negative error code. */ -static int wm8994_update_bits(unsigned int reg, unsigned short mask, - unsigned short value) +static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg, + unsigned short mask, unsigned short value) { int change , ret = 0; unsigned short old, new; - if (wm8994_i2c_read(reg, &old) != 0) + if (wm8994_i2c_read(priv, reg, &old) != 0) return -1; new = (old & ~mask) | (value & mask); change = (old != new) ? 1 : 0; if (change) - ret = wm8994_i2c_write(reg, new); + ret = wm8994_i2c_write(priv, reg, new); if (ret < 0) return ret; @@ -151,12 +145,13 @@ static int wm8994_update_bits(unsigned int reg, unsigned short mask, /* * Sets i2s set format * + * @param priv wm8994 information * @param aif_id Interface ID * @param fmt i2S format * * @return -1 for error and 0 Success. */ -int wm8994_set_fmt(int aif_id, unsigned int fmt) +static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt) { int ms_reg; int aif_reg; @@ -254,12 +249,13 @@ int wm8994_set_fmt(int aif_id, unsigned int fmt) return -1; } - error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV | - WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif); + error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV | + WM8994_AIF1_LRCLK_INV_MASK | + WM8994_AIF1_FMT_MASK, aif); - error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms); - error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK, - WM8994_AIF1CLK_ENA); + error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms); + error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK, + WM8994_AIF1CLK_ENA); if (error < 0) { debug("%s: codec register access error\n", __func__); return -1; @@ -271,7 +267,7 @@ int wm8994_set_fmt(int aif_id, unsigned int fmt) /* * Sets hw params FOR WM8994 * - * @param wm8994 wm8994 information pointer + * @param priv wm8994 information pointer * @param aif_id Audio interface ID * @param sampling_rate Sampling rate * @param bits_per_sample Bits per sample @@ -279,9 +275,9 @@ int wm8994_set_fmt(int aif_id, unsigned int fmt) * * @return -1 for error and 0 Success. */ -static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, - unsigned int sampling_rate, unsigned int bits_per_sample, - unsigned int channels) +static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id, + uint sampling_rate, uint bits_per_sample, + uint channels) { int aif1_reg; int aif2_reg; @@ -349,12 +345,10 @@ static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, /* AIFCLK/fs ratio; look for a close match in either direction */ best = 0; - best_val = abs((fs_ratios[0] * sampling_rate) - - wm8994->aifclk[id]); + best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]); for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { - cur_val = abs((fs_ratios[i] * sampling_rate) - - wm8994->aifclk[id]); + cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]); if (cur_val >= best_val) continue; best = i; @@ -371,7 +365,7 @@ static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, */ best = 0; for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { - cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; + cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; if (cur_val < 0) /* BCLK table is sorted */ break; best = i; @@ -383,10 +377,10 @@ static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, return -1; } - bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; + bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best]; bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; - if (wm8994_i2c_read(aif1_reg, ®_data) != 0) { + if (wm8994_i2c_read(priv, aif1_reg, ®_data) != 0) { debug("%s: AIF1 register read Failed\n", __func__); return -1; } @@ -394,16 +388,17 @@ static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, if ((channels == 1) && ((reg_data & 0x18) == 0x18)) aif2 |= WM8994_AIF1_MONO; - if (wm8994->aifclk[id] == 0) { + if (priv->aifclk[id] == 0) { debug("%s:Audio interface clock not set\n", __func__); return -1; } - ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1); - ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2); - ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); - ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK | - WM8994_AIF1CLK_RATE_MASK, rate_val); + ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1); + ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2); + ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, + bclk); + ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK | + WM8994_AIF1CLK_RATE_MASK, rate_val); debug("rate vale = %x , bclk val= %x\n", rate_val, bclk); @@ -418,12 +413,12 @@ static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, /* * Configures Audio interface Clock * - * @param wm8994 wm8994 information pointer + * @param priv wm8994 information pointer * @param aif Audio Interface ID * * @return -1 for error and 0 Success. */ -static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) +static int configure_aif_clock(struct wm8994_priv *priv, int aif) { int rate; int reg1 = 0; @@ -436,30 +431,30 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) else offset = 0; - switch (wm8994->sysclk[aif-1]) { + switch (priv->sysclk[aif - 1]) { case WM8994_SYSCLK_MCLK1: reg1 |= SEL_MCLK1; - rate = wm8994->mclk[0]; + rate = priv->mclk[0]; break; case WM8994_SYSCLK_MCLK2: reg1 |= SEL_MCLK2; - rate = wm8994->mclk[1]; + rate = priv->mclk[1]; break; case WM8994_SYSCLK_FLL1: reg1 |= SEL_FLL1; - rate = wm8994->fll[0].out; + rate = priv->fll[0].out; break; case WM8994_SYSCLK_FLL2: reg1 |= SEL_FLL2; - rate = wm8994->fll[1].out; + rate = priv->fll[1].out; break; default: debug("%s: Invalid input clock selection [%d]\n", - __func__, wm8994->sysclk[aif-1]); + __func__, priv->sysclk[aif - 1]); return -1; } @@ -469,18 +464,18 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) reg1 |= WM8994_AIF1CLK_DIV; } - wm8994->aifclk[aif-1] = rate; + priv->aifclk[aif - 1] = rate; - ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, - WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, - reg1); + ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset, + WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, + reg1); if (aif == WM8994_AIF1) - ret |= wm8994_update_bits(WM8994_CLOCKING_1, + ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1, WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); else if (aif == WM8994_AIF2) - ret |= wm8994_update_bits(WM8994_CLOCKING_1, + ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); @@ -496,33 +491,33 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) /* * Configures Audio interface for the given frequency * - * @param wm8994 wm8994 information + * @param priv wm8994 information * @param aif_id Audio Interface * @param clk_id Input Clock ID * @param freq Sampling frequency in Hz * * @return -1 for error and 0 success. */ -static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, - int clk_id, unsigned int freq) +static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id, + unsigned int freq) { int i; int ret = 0; - wm8994->sysclk[aif_id - 1] = clk_id; + priv->sysclk[aif_id - 1] = clk_id; switch (clk_id) { case WM8994_SYSCLK_MCLK1: - wm8994->mclk[0] = freq; + priv->mclk[0] = freq; if (aif_id == 2) { - ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 , - WM8994_AIF2DAC_DIV_MASK , 0); + ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2, + WM8994_AIF2DAC_DIV_MASK, 0); } break; case WM8994_SYSCLK_MCLK2: /* TODO: Set GPIO AF */ - wm8994->mclk[1] = freq; + priv->mclk[1] = freq; break; case WM8994_SYSCLK_FLL1: @@ -543,13 +538,14 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, __func__); return -1; } - ret = wm8994_update_bits(WM8994_CLOCKING_2, + ret = wm8994_bic_or(priv, WM8994_CLOCKING_2, WM8994_OPCLK_DIV_MASK, i); - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, - WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); + ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2, + WM8994_OPCLK_ENA, + WM8994_OPCLK_ENA); } else { - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, - WM8994_OPCLK_ENA, 0); + ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2, + WM8994_OPCLK_ENA, 0); } default: @@ -558,7 +554,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, return -1; } - ret |= configure_aif_clock(wm8994, aif_id); + ret |= configure_aif_clock(priv, aif_id); if (ret < 0) { debug("%s: codec register access error\n", __func__); @@ -571,37 +567,38 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, /* * Initializes Volume for AIF2 to HP path * + * @param priv wm8994 information * @returns -1 for error and 0 Success. * */ -static int wm8994_init_volume_aif2_dac1(void) +static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv) { int ret; /* Unmute AIF2DAC */ - ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1, - WM8994_AIF2DAC_MUTE_MASK, 0); + ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1, + WM8994_AIF2DAC_MUTE_MASK, 0); - ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME, - WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, - WM8994_AIF2DAC_VU | 0xff); + ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME, + WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, + WM8994_AIF2DAC_VU | 0xff); - ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME, - WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, - WM8994_AIF2DAC_VU | 0xff); + ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME, + WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, + WM8994_AIF2DAC_VU | 0xff); - ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, - WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | - WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | + WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); - ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, - WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | - WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | + WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); /* Head Phone Volume */ - ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); - ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); + ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D); + ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); if (ret < 0) { debug("%s: codec register access error\n", __func__); @@ -614,26 +611,27 @@ static int wm8994_init_volume_aif2_dac1(void) /* * Initializes Volume for AIF1 to HP path * + * @param priv wm8994 information * @returns -1 for error and 0 Success. * */ -static int wm8994_init_volume_aif1_dac1(void) +static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv) { int ret = 0; /* Unmute AIF1DAC */ - ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000); + ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000); - ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, - WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | - WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | + WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); - ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, - WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | - WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); + ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME, + WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | + WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); /* Head Phone Volume */ - ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); - ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); + ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D); + ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); if (ret < 0) { debug("%s: codec register access error\n", __func__); @@ -646,93 +644,99 @@ static int wm8994_init_volume_aif1_dac1(void) /* * Intialise wm8994 codec device * - * @param wm8994 wm8994 information + * @param priv wm8994 information * * @returns -1 for error and 0 Success. */ -static int wm8994_device_init(struct wm8994_priv *wm8994, - enum en_audio_interface aif_id) +static int wm8994_device_init(struct wm8994_priv *priv) { const char *devname; unsigned short reg_data; int ret; - wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */ + wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET); - ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data); + ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, ®_data); if (ret < 0) { debug("Failed to read ID register\n"); - goto err; + return ret; } if (reg_data == WM8994_ID) { devname = "WM8994"; - debug("Device registered as type %d\n", wm8994->type); - wm8994->type = WM8994; + debug("Device registered as type %d\n", priv->type); + priv->type = WM8994; } else { debug("Device is not a WM8994, ID is %x\n", ret); - ret = -1; - goto err; + return -ENXIO; } - ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data); + ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, ®_data); if (ret < 0) { debug("Failed to read revision register: %d\n", ret); - goto err; + return ret; } - wm8994->revision = reg_data; - debug("%s revision %c\n", devname, 'A' + wm8994->revision); + priv->revision = reg_data; + debug("%s revision %c\n", devname, 'A' + priv->revision); + + return 0; +} + +static int wm8994_setup_interface(struct wm8994_priv *priv, + enum en_audio_interface aif_id) +{ + int ret; /* VMID Selection */ - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, - WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); + ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1, + WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); /* Charge Pump Enable */ - ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, - WM8994_CP_ENA); + ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, + WM8994_CP_ENA); /* Head Phone Power Enable */ - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, - WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); + ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1, + WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, - WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); + ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1, + WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); if (aif_id == WM8994_AIF1) { - ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, + ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2, WM8994_TSHUT_ENA | WM8994_MIXINL_ENA | WM8994_MIXINR_ENA | WM8994_IN2L_ENA | WM8994_IN2R_ENA); - ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, + ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4, WM8994_ADCL_ENA | WM8994_ADCR_ENA | WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC1L_ENA); /* Power enable for AIF1 and DAC1 */ - ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, + ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5, WM8994_AIF1DACL_ENA | WM8994_AIF1DACR_ENA | WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); } else if (aif_id == WM8994_AIF2) { /* Power enable for AIF2 and DAC1 */ - ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, + ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5, WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); } /* Head Phone Initialisation */ - ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, + ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1, WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY); - ret |= wm8994_update_bits(WM8994_DC_SERVO_1, + ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1, WM8994_DCS_ENA_CHAN_0_MASK | WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 | WM8994_DCS_ENA_CHAN_1); - ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, + ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1, WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK | WM8994_HPOUT1R_OUTP_MASK | @@ -743,172 +747,130 @@ static int wm8994_device_init(struct wm8994_priv *wm8994, WM8994_HPOUT1R_RMV_SHORT); /* MIXER Config DAC1 to HP */ - ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1, - WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L); + ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1, + WM8994_DAC1L_TO_HPOUT1L_MASK, + WM8994_DAC1L_TO_HPOUT1L); - ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, - WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); + ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2, + WM8994_DAC1R_TO_HPOUT1R_MASK, + WM8994_DAC1R_TO_HPOUT1R); if (aif_id == WM8994_AIF1) { /* Routing AIF1 to DAC1 */ - ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING, - WM8994_AIF1DAC1L_TO_DAC1L); + ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING, + WM8994_AIF1DAC1L_TO_DAC1L); - ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING, + ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING, WM8994_AIF1DAC1R_TO_DAC1R); /* GPIO Settings for AIF1 */ - ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT - | WM8994_GPIO_FUNCTION_I2S_CLK - | WM8994_GPIO_INPUT_DEBOUNCE); + ret |= wm8994_i2c_write(priv, WM8994_GPIO_1, + WM8994_GPIO_DIR_OUTPUT | + WM8994_GPIO_FUNCTION_I2S_CLK | + WM8994_GPIO_INPUT_DEBOUNCE); - ret |= wm8994_init_volume_aif1_dac1(); + ret |= wm8994_init_volume_aif1_dac1(priv); } else if (aif_id == WM8994_AIF2) { /* Routing AIF2 to DAC1 */ - ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, - WM8994_AIF2DACL_TO_DAC1L_MASK, - WM8994_AIF2DACL_TO_DAC1L); + ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING, + WM8994_AIF2DACL_TO_DAC1L_MASK, + WM8994_AIF2DACL_TO_DAC1L); - ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, - WM8994_AIF2DACR_TO_DAC1R_MASK, - WM8994_AIF2DACR_TO_DAC1R); + ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING, + WM8994_AIF2DACR_TO_DAC1R_MASK, + WM8994_AIF2DACR_TO_DAC1R); /* GPIO Settings for AIF2 */ /* B CLK */ - ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK , - WM8994_GPIO_DIR_OUTPUT); + ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK, + WM8994_GPIO_DIR_OUTPUT); /* LR CLK */ - ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK, - WM8994_GPIO_DIR_OUTPUT); + ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK, + WM8994_GPIO_DIR_OUTPUT); /* DATA */ - ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | - WM8994_GPIO_FUNCTION_MASK, - WM8994_GPIO_DIR_OUTPUT); + ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | + WM8994_GPIO_FUNCTION_MASK, + WM8994_GPIO_DIR_OUTPUT); - ret |= wm8994_init_volume_aif2_dac1(); + ret |= wm8994_init_volume_aif2_dac1(priv); } if (ret < 0) goto err; - debug("%s: Codec chip init ok\n", __func__); + debug("%s: Codec chip setup ok\n", __func__); return 0; err: - debug("%s: Codec chip init error\n", __func__); + debug("%s: Codec chip setup error\n", __func__); return -1; } -/* - * Gets fdt values for wm8994 config parameters - * - * @param pcodec_info codec information structure - * @param blob FDT blob - * @return int value, 0 for success - */ -static int get_codec_values(struct sound_codec_info *pcodec_info, - const void *blob) +static int _wm8994_init(struct wm8994_priv *priv, + enum en_audio_interface aif_id, int sampling_rate, + int mclk_freq, int bits_per_sample, + unsigned int channels) { - int error = 0; -#if CONFIG_IS_ENABLED(OF_CONTROL) - enum fdt_compat_id compat; - int node; - int parent; + int ret; - /* Get the node from FDT for codec */ - node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC); - if (node <= 0) { - debug("EXYNOS_SOUND: No node for codec in device tree\n"); - debug("node = %d\n", node); - return -1; - } - - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -1; - } - - compat = fdtdec_lookup(blob, parent); - switch (compat) { - case COMPAT_SAMSUNG_S3C2440_I2C: - pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); - error |= pcodec_info->i2c_bus; - debug("i2c bus = %d\n", pcodec_info->i2c_bus); - pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, - "reg", 0); - error |= pcodec_info->i2c_dev_addr; - debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); - break; - default: - debug("%s: Unknown compat id %d\n", __func__, compat); - return -1; - } -#else - pcodec_info->i2c_bus = AUDIO_I2C_BUS; - pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; - debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); -#endif - - pcodec_info->codec_type = CODEC_WM_8994; - - if (error == -1) { - debug("fail to get wm8994 codec node properties\n"); - return -1; - } - - return 0; -} - -/* WM8994 Device Initialisation */ -int wm8994_init(const void *blob, enum en_audio_interface aif_id, - int sampling_rate, int mclk_freq, - int bits_per_sample, unsigned int channels) -{ - int ret = 0; - struct sound_codec_info *pcodec_info = &g_codec_info; - - /* Get the codec Values */ - if (get_codec_values(pcodec_info, blob) < 0) { - debug("FDT Codec values failed\n"); - return -1; - } - - /* shift the device address by 1 for 7 bit addressing */ - g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; - wm8994_i2c_init(pcodec_info->i2c_bus); - - if (pcodec_info->codec_type == CODEC_WM_8994) { - g_wm8994_info.type = WM8994; - } else { - debug("%s: Codec id [%d] not defined\n", __func__, - pcodec_info->codec_type); - return -1; - } - - ret = wm8994_device_init(&g_wm8994_info, aif_id); + ret = wm8994_setup_interface(priv, aif_id); if (ret < 0) { debug("%s: wm8994 codec chip init failed\n", __func__); return ret; } - ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1, - mclk_freq); + ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq); if (ret < 0) { debug("%s: wm8994 codec set sys clock failed\n", __func__); return ret; } - ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate, - bits_per_sample, channels); + ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample, + channels); if (ret == 0) { - ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S | - SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBS_CFS); + ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS); } + return ret; } + +static int wm8994_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels) +{ + struct wm8994_priv *priv = dev_get_priv(dev); + + return _wm8994_init(priv, interface, rate, mclk_freq, bits_per_sample, + channels); +} + +static int wm8994_probe(struct udevice *dev) +{ + struct wm8994_priv *priv = dev_get_priv(dev); + + priv->dev = dev; + return wm8994_device_init(priv); +} + +static const struct audio_codec_ops wm8994_ops = { + .set_params = wm8994_set_params, +}; + +static const struct udevice_id wm8994_ids[] = { + { .compatible = "wolfson,wm8994" }, + { } +}; + +U_BOOT_DRIVER(wm8994) = { + .name = "wm8994", + .id = UCLASS_AUDIO_CODEC, + .of_match = wm8994_ids, + .probe = wm8994_probe, + .ops = &wm8994_ops, + .priv_auto_alloc_size = sizeof(struct wm8994_priv), +}; diff --git a/drivers/sound/wm8994.h b/drivers/sound/wm8994.h index ef2878f87c..e36e6269f0 100644 --- a/drivers/sound/wm8994.h +++ b/drivers/sound/wm8994.h @@ -15,7 +15,7 @@ /* Avilable audi interface ports in wm8994 codec */ enum en_audio_interface { - WM8994_AIF1 = 1, + WM8994_AIF1, WM8994_AIF2, WM8994_AIF3 }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 516188ea88..a7bb5b35c2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -116,6 +116,20 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MESON_SPIFC + bool "Amlogic Meson SPI Flash Controller driver" + depends on ARCH_MESON + help + Enable the Amlogic Meson SPI Flash Controller SPIFC) driver. + This driver can be used to access the SPI NOR flash chips on + Amlogic Meson SoCs. + +config MPC8XX_SPI + bool "MPC8XX SPI Driver" + depends on MPC8xx + help + Enable support for SPI on MPC8XX + config MT7621_SPI bool "MediaTek MT7621 SPI driver" depends on ARCH_MT7620 @@ -124,6 +138,13 @@ config MT7621_SPI the SPI NOR flash on platforms embedding this Ralink / MediaTek SPI core, like MT7621/7628/7688. +config MTK_QSPI + bool "Mediatek QSPI driver" + help + Enable the Mediatek QSPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Mediatek QSPI IP core. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720 @@ -328,12 +349,6 @@ config LPC32XX_SSP help Enable support for SPI on LPC32xx -config MPC8XX_SPI - bool "MPC8XX SPI Driver" - depends on MPC8xx - help - Enable support for SPI on MPC8XX - config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7242ea7e40..392a925795 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,8 +31,10 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o +obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 1db8bbef2b..cf4de9ee1a 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -34,11 +34,6 @@ static int spi_has_wdrbt(struct atmel_spi_slave *slave) return (ATMEL_SPI_VERSION_REV(ver) >= 0x210); } -void spi_init() -{ - -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 29db6fa368..11fce9c4fe 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -329,7 +329,7 @@ static const struct dm_spi_ops cadence_spi_ops = { }; static const struct udevice_id cadence_spi_ids[] = { - { .compatible = "cadence,qspi" }, + { .compatible = "cdns,qspi-nor" }, { } }; diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 07fa5e3b8a..4d2c106440 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -388,11 +388,6 @@ void spi_cs_deactivate(struct spi_slave *slave) /* do nothing */ } -void spi_init(void) -{ - /* do nothing */ -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5cca414486..02d93763d4 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -369,7 +369,13 @@ static int poll_transfer(struct dw_spi_priv *priv) return 0; } -static void external_cs_manage(struct udevice *dev, bool on) +/* + * We define external_cs_manage function as 'weak' as some targets + * (like MSCC Ocelot) don't control the external CS pin using a GPIO + * controller. These SoCs use specific registers to control by + * software the SPI pins (and especially the CS). + */ +__weak void external_cs_manage(struct udevice *dev, bool on) { #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) struct dw_spi_priv *priv = dev_get_priv(dev->parent); diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index f7ed8fbe08..764c94215e 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -390,11 +390,6 @@ static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) return 0; } #ifndef CONFIG_DM_SPI -void spi_init(void) -{ - /* Nothing to do */ -} - int spi_cs_is_valid(unsigned int bus, unsigned int cs) { if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index e9941593f5..7444ae1a06 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -118,11 +118,6 @@ void spi_free_slave(struct spi_slave *slave) free(fsl); } -void spi_init(void) -{ - -} - int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c index ce12eee657..4b09366317 100644 --- a/drivers/spi/lpc32xx_ssp.c +++ b/drivers/spi/lpc32xx_ssp.c @@ -47,15 +47,6 @@ static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave( return container_of(slave, struct lpc32xx_spi_slave, slave); } -/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ -void spi_init(void) -{ - /* - * nothing to do: clocking was enabled in lpc32xx_ssp_enable() - * and configuration will be done in spi_setup_slave() - */ -} - /* the following is called in sequence by do_spi_xfer() */ struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c new file mode 100644 index 0000000000..3d551694cb --- /dev/null +++ b/drivers/spi/meson_spifc.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Beniamino Galvani + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + * + * Amlogic Meson SPI Flash Controller driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* register map */ +#define REG_CMD 0x00 +#define REG_ADDR 0x04 +#define REG_CTRL 0x08 +#define REG_CTRL1 0x0c +#define REG_STATUS 0x10 +#define REG_CTRL2 0x14 +#define REG_CLOCK 0x18 +#define REG_USER 0x1c +#define REG_USER1 0x20 +#define REG_USER2 0x24 +#define REG_USER3 0x28 +#define REG_USER4 0x2c +#define REG_SLAVE 0x30 +#define REG_SLAVE1 0x34 +#define REG_SLAVE2 0x38 +#define REG_SLAVE3 0x3c +#define REG_C0 0x40 +#define REG_B8 0x60 +#define REG_MAX 0x7c + +/* register fields */ +#define CMD_USER BIT(18) +#define CTRL_ENABLE_AHB BIT(17) +#define CLOCK_SOURCE BIT(31) +#define CLOCK_DIV_SHIFT 12 +#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT) +#define CLOCK_CNT_HIGH_SHIFT 6 +#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT) +#define CLOCK_CNT_LOW_SHIFT 0 +#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT) +#define USER_DIN_EN_MS BIT(0) +#define USER_CMP_MODE BIT(2) +#define USER_CLK_NOT_INV BIT(7) +#define USER_UC_DOUT_SEL BIT(27) +#define USER_UC_DIN_SEL BIT(28) +#define USER_UC_MASK ((BIT(5) - 1) << 27) +#define USER1_BN_UC_DOUT_SHIFT 17 +#define USER1_BN_UC_DOUT_MASK (0xff << 16) +#define USER1_BN_UC_DIN_SHIFT 8 +#define USER1_BN_UC_DIN_MASK (0xff << 8) +#define USER4_CS_POL_HIGH BIT(23) +#define USER4_IDLE_CLK_HIGH BIT(29) +#define USER4_CS_ACT BIT(30) +#define SLAVE_TRST_DONE BIT(4) +#define SLAVE_OP_MODE BIT(30) +#define SLAVE_SW_RST BIT(31) + +#define SPIFC_BUFFER_SIZE 64 + +struct meson_spifc_priv { + struct regmap *regmap; + struct clk clk; +}; + +/** + * meson_spifc_drain_buffer() - copy data from device buffer to memory + * @spifc: the Meson SPI device + * @buf: the destination buffer + * @len: number of bytes to copy + */ +static void meson_spifc_drain_buffer(struct meson_spifc_priv *spifc, + u8 *buf, int len) +{ + u32 data; + int i = 0; + + while (i < len) { + regmap_read(spifc->regmap, REG_C0 + i, &data); + + if (len - i >= 4) { + *((u32 *)buf) = data; + buf += 4; + } else { + memcpy(buf, &data, len - i); + break; + } + i += 4; + } +} + +/** + * meson_spifc_fill_buffer() - copy data from memory to device buffer + * @spifc: the Meson SPI device + * @buf: the source buffer + * @len: number of bytes to copy + */ +static void meson_spifc_fill_buffer(struct meson_spifc_priv *spifc, + const u8 *buf, int len) +{ + u32 data = 0; + int i = 0; + + while (i < len) { + if (len - i >= 4) + data = *(u32 *)buf; + else + memcpy(&data, buf, len - i); + + regmap_write(spifc->regmap, REG_C0 + i, data); + + buf += 4; + i += 4; + } +} + +/** + * meson_spifc_txrx() - transfer a chunk of data + * @spifc: the Meson SPI device + * @dout: data buffer for TX + * @din: data buffer for RX + * @offset: offset of the data to transfer + * @len: length of the data to transfer + * @last_xfer: whether this is the last transfer of the message + * @last_chunk: whether this is the last chunk of the transfer + * Return: 0 on success, a negative value on error + */ +static int meson_spifc_txrx(struct meson_spifc_priv *spifc, + const u8 *dout, u8 *din, int offset, + int len, bool last_xfer, bool last_chunk) +{ + bool keep_cs = true; + u32 data; + int ret; + + if (dout) + meson_spifc_fill_buffer(spifc, dout + offset, len); + + /* enable DOUT stage */ + regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK, + USER_UC_DOUT_SEL); + regmap_write(spifc->regmap, REG_USER1, + (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT); + + /* enable data input during DOUT */ + regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS, + USER_DIN_EN_MS); + + if (last_chunk && last_xfer) + keep_cs = false; + + regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT, + keep_cs ? USER4_CS_ACT : 0); + + /* clear transition done bit */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0); + /* start transfer */ + regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER); + + /* wait for the current operation to terminate */ + ret = regmap_read_poll_timeout(spifc->regmap, REG_SLAVE, data, + (data & SLAVE_TRST_DONE), + 0, 5 * CONFIG_SYS_HZ); + + if (!ret && din) + meson_spifc_drain_buffer(spifc, din + offset, len); + + return ret; +} + +/** + * meson_spifc_xfer() - perform a single transfer + * @dev: the SPI controller device + * @bitlen: length of the transfer + * @dout: data buffer for TX + * @din: data buffer for RX + * @flags: transfer flags + * Return: 0 on success, a negative value on error + */ +static int meson_spifc_xfer(struct udevice *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct meson_spifc_priv *spifc = dev_get_priv(slave->parent); + int blen = bitlen / 8; + int len, done = 0, ret = 0; + + if (bitlen % 8) + return -EINVAL; + + debug("xfer len %d (%d) dout %p din %p\n", bitlen, blen, dout, din); + + regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0); + + while (done < blen && !ret) { + len = min_t(int, blen - done, SPIFC_BUFFER_SIZE); + ret = meson_spifc_txrx(spifc, dout, din, done, len, + flags & SPI_XFER_END, + done + len >= blen); + done += len; + } + + regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, + CTRL_ENABLE_AHB); + + return ret; +} + +/** + * meson_spifc_set_speed() - program the clock divider + * @dev: the SPI controller device + * @speed: desired speed in Hz + */ +static int meson_spifc_set_speed(struct udevice *dev, uint speed) +{ + struct meson_spifc_priv *spifc = dev_get_priv(dev); + unsigned long parent, value; + int n; + + parent = clk_get_rate(&spifc->clk); + n = max_t(int, parent / speed - 1, 1); + + debug("parent %lu, speed %u, n %d\n", parent, speed, n); + + value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK; + value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK; + value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) & + CLOCK_CNT_HIGH_MASK; + + regmap_write(spifc->regmap, REG_CLOCK, value); + + return 0; +} + +/** + * meson_spifc_set_mode() - setups the SPI bus mode + * @dev: the SPI controller device + * @mode: desired mode bitfield + * Return: 0 on success, -ENODEV on error + */ +static int meson_spifc_set_mode(struct udevice *dev, uint mode) +{ + struct meson_spifc_priv *spifc = dev_get_priv(dev); + + if (mode & (SPI_CPHA | SPI_RX_QUAD | SPI_RX_DUAL | + SPI_TX_QUAD | SPI_TX_DUAL)) + return -ENODEV; + + regmap_update_bits(spifc->regmap, REG_USER, USER_CLK_NOT_INV, + mode & SPI_CPOL ? USER_CLK_NOT_INV : 0); + + regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_POL_HIGH, + mode & SPI_CS_HIGH ? USER4_CS_POL_HIGH : 0); + + return 0; +} + +/** + * meson_spifc_hw_init() - reset and initialize the SPI controller + * @spifc: the Meson SPI device + */ +static void meson_spifc_hw_init(struct meson_spifc_priv *spifc) +{ + /* reset device */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST, + SLAVE_SW_RST); + /* disable compatible mode */ + regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0); + /* set master mode */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0); +} + +static const struct dm_spi_ops meson_spifc_ops = { + .xfer = meson_spifc_xfer, + .set_speed = meson_spifc_set_speed, + .set_mode = meson_spifc_set_mode, +}; + +static int meson_spifc_probe(struct udevice *dev) +{ + struct meson_spifc_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + meson_spifc_hw_init(priv); + + return 0; +} + +static const struct udevice_id meson_spifc_ids[] = { + { .compatible = "amlogic,meson-gxbb-spifc", }, + { } +}; + +U_BOOT_DRIVER(meson_spifc) = { + .name = "meson_spifc", + .id = UCLASS_SPI, + .of_match = meson_spifc_ids, + .ops = &meson_spifc_ops, + .probe = meson_spifc_probe, + .priv_auto_alloc_size = sizeof(struct meson_spifc_priv), +}; diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 285fd4d2cc..b020ce2b9d 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -17,64 +17,19 @@ */ #include +#include #include +#include + #include -#include -#include -#include -#include - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif +#include #define CPM_SPI_BASE_RX CPM_SPI_BASE #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - #define MAX_BUFFER 0x104 -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) +static int mpc8xx_spi_probe(struct udevice *dev) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immr->im_cpm; @@ -180,117 +135,24 @@ void spi_init_f(void) clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - /* 10 + 11 */ out_8(&cp->cp_spim, 0); /* Mask all SPI events */ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - return; + return 0; } -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) +static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; cbd_t __iomem *tbdf, *rbdf; int tm; + size_t count = (bitlen + 7) / 8; - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); + if (count > MAX_BUFFER) + return -EINVAL; tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; @@ -299,10 +161,12 @@ ssize_t spi_xfer(size_t count) clrbits_be32(&cp->cp_pbdat, 0x0001); /* Setting tx bd status and data length */ + out_be32(&tbdf->cbd_bufaddr, (ulong)dout); out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); out_be16(&tbdf->cbd_datlen, count); /* Setting rx bd status and data length */ + out_be32(&rbdf->cbd_bufaddr, (ulong)din); out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ @@ -333,3 +197,20 @@ ssize_t spi_xfer(size_t count) return count; } + +static const struct dm_spi_ops mpc8xx_spi_ops = { + .xfer = mpc8xx_spi_xfer, +}; + +static const struct udevice_id mpc8xx_spi_ids[] = { + { .compatible = "fsl,mpc8xx-spi" }, + { } +}; + +U_BOOT_DRIVER(mpc8xx_spi) = { + .name = "mpc8xx_spi", + .id = UCLASS_SPI, + .of_match = mpc8xx_spi_ids, + .ops = &mpc8xx_spi_ops, + .probe = mpc8xx_spi_probe, +}; diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c new file mode 100644 index 0000000000..b510733e92 --- /dev/null +++ b/drivers/spi/mtk_qspi.c @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek, Inc. + * Author : Guochun.Mao@mediatek.com + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Register Offset */ +struct mtk_qspi_regs { + u32 cmd; + u32 cnt; + u32 rdsr; + u32 rdata; + u32 radr[3]; + u32 wdata; + u32 prgdata[6]; + u32 shreg[10]; + u32 cfg[2]; + u32 shreg10; + u32 mode_mon; + u32 status[4]; + u32 flash_time; + u32 flash_cfg; + u32 reserved_0[3]; + u32 sf_time; + u32 pp_dw_data; + u32 reserved_1; + u32 delsel_0[2]; + u32 intrstus; + u32 intren; + u32 reserved_2; + u32 cfg3; + u32 reserved_3; + u32 chksum; + u32 aaicmd; + u32 wrprot; + u32 radr3; + u32 dual; + u32 delsel_1[3]; +}; + +struct mtk_qspi_platdata { + fdt_addr_t reg_base; + fdt_addr_t mem_base; +}; + +struct mtk_qspi_priv { + struct mtk_qspi_regs *regs; + unsigned long *mem_base; + u8 op; + u8 tx[3]; /* only record max 3 bytes paras, when it's address. */ + u32 txlen; /* dout buffer length - op code length */ + u8 *rx; + u32 rxlen; +}; + +#define MTK_QSPI_CMD_POLLINGREG_US 500000 +#define MTK_QSPI_WRBUF_SIZE 256 +#define MTK_QSPI_COMMAND_ENABLE 0x30 + +/* NOR flash controller commands */ +#define MTK_QSPI_RD_TRIGGER BIT(0) +#define MTK_QSPI_READSTATUS BIT(1) +#define MTK_QSPI_PRG_CMD BIT(2) +#define MTK_QSPI_WR_TRIGGER BIT(4) +#define MTK_QSPI_WRITESTATUS BIT(5) +#define MTK_QSPI_AUTOINC BIT(7) + +#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6 +#define MTK_QSPI_MAX_SHIFT 0x8 + +#define MTK_QSPI_WR_BUF_ENABLE 0x1 +#define MTK_QSPI_WR_BUF_DISABLE 0x0 + +static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd) +{ + u8 tmp; + u8 val = cmd & ~MTK_QSPI_AUTOINC; + + writeb(cmd, &priv->regs->cmd); + + return readb_poll_timeout(&priv->regs->cmd, tmp, !(val & tmp), + MTK_QSPI_CMD_POLLINGREG_US); +} + +static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv) +{ + int len = 1 + priv->txlen + priv->rxlen; + int i, ret, idx; + + if (len > MTK_QSPI_MAX_SHIFT) + return -ERR_INVAL; + + writeb(len * 8, &priv->regs->cnt); + + /* start at PRGDATA5, go down to PRGDATA0 */ + idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1; + + /* opcode */ + writeb(priv->op, &priv->regs->prgdata[idx]); + idx--; + + /* program TX data */ + for (i = 0; i < priv->txlen; i++, idx--) + writeb(priv->tx[i], &priv->regs->prgdata[idx]); + + /* clear out rest of TX registers */ + while (idx >= 0) { + writeb(0, &priv->regs->prgdata[idx]); + idx--; + } + + ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD); + if (ret) + return ret; + + /* restart at first RX byte */ + idx = priv->rxlen - 1; + + /* read out RX data */ + for (i = 0; i < priv->rxlen; i++, idx--) + priv->rx[i] = readb(&priv->regs->shreg[idx]); + + return 0; +} + +static int mtk_qspi_read(struct mtk_qspi_priv *priv, + u32 addr, u8 *buf, u32 len) +{ + memcpy(buf, (u8 *)priv->mem_base + addr, len); + return 0; +} + +static void mtk_qspi_set_addr(struct mtk_qspi_priv *priv, u32 addr) +{ + int i; + + for (i = 0; i < 3; i++) { + writeb(addr & 0xff, &priv->regs->radr[i]); + addr >>= 8; + } +} + +static int mtk_qspi_write_single_byte(struct mtk_qspi_priv *priv, + u32 addr, u32 length, const u8 *data) +{ + int i, ret; + + mtk_qspi_set_addr(priv, addr); + + for (i = 0; i < length; i++) { + writeb(*data++, &priv->regs->wdata); + ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER); + if (ret < 0) + return ret; + } + return 0; +} + +static int mtk_qspi_write_buffer(struct mtk_qspi_priv *priv, u32 addr, + const u8 *buf) +{ + int i, data; + + mtk_qspi_set_addr(priv, addr); + + for (i = 0; i < MTK_QSPI_WRBUF_SIZE; i += 4) { + data = buf[i + 3] << 24 | buf[i + 2] << 16 | + buf[i + 1] << 8 | buf[i]; + writel(data, &priv->regs->pp_dw_data); + } + + return mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER); +} + +static int mtk_qspi_write(struct mtk_qspi_priv *priv, + u32 addr, const u8 *buf, u32 len) +{ + int ret; + + /* setting pre-fetch buffer for page program */ + writel(MTK_QSPI_WR_BUF_ENABLE, &priv->regs->cfg[1]); + while (len >= MTK_QSPI_WRBUF_SIZE) { + ret = mtk_qspi_write_buffer(priv, addr, buf); + if (ret < 0) + return ret; + + len -= MTK_QSPI_WRBUF_SIZE; + addr += MTK_QSPI_WRBUF_SIZE; + buf += MTK_QSPI_WRBUF_SIZE; + } + /* disable pre-fetch buffer for page program */ + writel(MTK_QSPI_WR_BUF_DISABLE, &priv->regs->cfg[1]); + + if (len) + return mtk_qspi_write_single_byte(priv, addr, len, buf); + + return 0; +} + +static int mtk_qspi_claim_bus(struct udevice *dev) +{ + /* nothing to do */ + return 0; +} + +static int mtk_qspi_release_bus(struct udevice *dev) +{ + /* nothing to do */ + return 0; +} + +static int mtk_qspi_transfer(struct mtk_qspi_priv *priv, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + u32 bytes = DIV_ROUND_UP(bitlen, 8); + u32 addr; + + if (!bytes) + return -ERR_INVAL; + + if (dout) { + if (flags & SPI_XFER_BEGIN) { + /* parse op code and potential paras first */ + priv->op = *(u8 *)dout; + if (bytes > 1) + memcpy(priv->tx, (u8 *)dout + 1, + bytes <= 4 ? bytes - 1 : 3); + priv->txlen = bytes - 1; + } + + if (flags == SPI_XFER_ONCE) { + /* operations without receiving or sending data. + * for example: erase, write flash register or write + * enable... + */ + priv->rx = NULL; + priv->rxlen = 0; + return mtk_qspi_tx_rx(priv); + } + + if (flags & SPI_XFER_END) { + /* here, dout should be data to be written. + * and priv->tx should be filled 3Bytes address. + */ + addr = priv->tx[0] << 16 | priv->tx[1] << 8 | + priv->tx[2]; + return mtk_qspi_write(priv, addr, (u8 *)dout, bytes); + } + } + + if (din) { + if (priv->txlen >= 3) { + /* if run to here, priv->tx[] should be the address + * where read data from, + * and, din is the buf to receive data. + */ + addr = priv->tx[0] << 16 | priv->tx[1] << 8 | + priv->tx[2]; + return mtk_qspi_read(priv, addr, (u8 *)din, bytes); + } + + /* should be reading flash's register */ + priv->rx = (u8 *)din; + priv->rxlen = bytes; + return mtk_qspi_tx_rx(priv); + } + + return 0; +} + +static int mtk_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct mtk_qspi_priv *priv = dev_get_priv(bus); + + return mtk_qspi_transfer(priv, bitlen, dout, din, flags); +} + +static int mtk_qspi_set_speed(struct udevice *bus, uint speed) +{ + /* nothing to do */ + return 0; +} + +static int mtk_qspi_set_mode(struct udevice *bus, uint mode) +{ + /* nothing to do */ + return 0; +} + +static int mtk_qspi_ofdata_to_platdata(struct udevice *bus) +{ + struct resource res_reg, res_mem; + struct mtk_qspi_platdata *plat = bus->platdata; + int ret; + + ret = dev_read_resource_byname(bus, "reg_base", &res_reg); + if (ret) { + debug("can't get reg_base resource(ret = %d)\n", ret); + return -ENOMEM; + } + + ret = dev_read_resource_byname(bus, "mem_base", &res_mem); + if (ret) { + debug("can't get map_base resource(ret = %d)\n", ret); + return -ENOMEM; + } + + plat->mem_base = res_mem.start; + plat->reg_base = res_reg.start; + + return 0; +} + +static int mtk_qspi_probe(struct udevice *bus) +{ + struct mtk_qspi_platdata *plat = dev_get_platdata(bus); + struct mtk_qspi_priv *priv = dev_get_priv(bus); + + priv->regs = (struct mtk_qspi_regs *)plat->reg_base; + priv->mem_base = (unsigned long *)plat->mem_base; + + writel(MTK_QSPI_COMMAND_ENABLE, &priv->regs->wrprot); + + return 0; +} + +static const struct dm_spi_ops mtk_qspi_ops = { + .claim_bus = mtk_qspi_claim_bus, + .release_bus = mtk_qspi_release_bus, + .xfer = mtk_qspi_xfer, + .set_speed = mtk_qspi_set_speed, + .set_mode = mtk_qspi_set_mode, +}; + +static const struct udevice_id mtk_qspi_ids[] = { + { .compatible = "mediatek,mt7629-qspi" }, + { } +}; + +U_BOOT_DRIVER(mtk_qspi) = { + .name = "mtk_qspi", + .id = UCLASS_SPI, + .of_match = mtk_qspi_ids, + .ops = &mtk_qspi_ops, + .ofdata_to_platdata = mtk_qspi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mtk_qspi_platdata), + .priv_auto_alloc_size = sizeof(struct mtk_qspi_priv), + .probe = mtk_qspi_probe, +}; diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 0dccc38b82..b2636909ce 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -400,10 +400,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); } -void spi_init(void) -{ -} - /* * Some SPI devices require active chip-select over multiple * transactions, we achieve this using a GPIO. Still, the SPI diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 006fe8281c..5065e407f8 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -39,10 +39,6 @@ static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) return container_of(slave, struct mxs_spi_slave, slave); } -void spi_init(void) -{ -} - int spi_cs_is_valid(unsigned int bus, unsigned int cs) { /* MXS SPI: 4 ports and 3 chip selects maximum */ diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index ecf54bb714..c7fcf050a5 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -461,11 +461,6 @@ static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave) return container_of(slave, struct omap3_spi_priv, slave); } -void spi_init(void) -{ - /* do nothing */ -} - void spi_free_slave(struct spi_slave *slave) { struct omap3_spi_priv *priv = to_omap3_spi(slave); diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index 86b71d2e21..32bb8c8d21 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -9,16 +9,11 @@ * Driver for ARM PL022 SPI Controller. */ -#include #include #include #include -#include -#include -#include -#include +#include #include -#include #include #define SSP_CR0 0x000 @@ -72,11 +67,7 @@ struct pl022_spi_slave { void *base; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct clk clk; -#else unsigned int freq; -#endif }; /* @@ -96,30 +87,13 @@ static int pl022_is_supported(struct pl022_spi_slave *ps) return 0; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) -static int pl022_spi_ofdata_to_platdata(struct udevice *bus) -{ - struct pl022_spi_pdata *plat = bus->platdata; - const void *fdt = gd->fdt_blob; - int node = dev_of_offset(bus); - - plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size); - - return clk_get_by_index(bus, 0, &plat->clk); -} -#endif - static int pl022_spi_probe(struct udevice *bus) { struct pl022_spi_pdata *plat = dev_get_platdata(bus); struct pl022_spi_slave *ps = dev_get_priv(bus); ps->base = ioremap(plat->addr, plat->size); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - ps->clk = plat->clk; -#else ps->freq = plat->freq; -#endif /* Check the PL022 version */ if (!pl022_is_supported(ps)) @@ -240,11 +214,7 @@ static int pl022_spi_set_speed(struct udevice *bus, uint speed) u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr, best_cpsr = cpsr; u32 min, max, best_freq = 0, tmp; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - u32 rate = clk_get_rate(&ps->clk); -#else u32 rate = ps->freq; -#endif bool found = false; max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN); @@ -316,6 +286,25 @@ static const struct dm_spi_ops pl022_spi_ops = { }; #if !CONFIG_IS_ENABLED(OF_PLATDATA) +static int pl022_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct pl022_spi_pdata *plat = bus->platdata; + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(bus); + struct clk clkdev; + int ret; + + plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size); + + ret = clk_get_by_index(bus, 0, &clkdev); + if (ret) + return ret; + + plat->freq = clk_get_rate(&clkdev); + + return 0; +} + static const struct udevice_id pl022_spi_ids[] = { { .compatible = "arm,pl022-spi" }, { } @@ -327,11 +316,9 @@ U_BOOT_DRIVER(pl022_spi) = { .id = UCLASS_SPI, #if !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = pl022_spi_ids, -#endif - .ops = &pl022_spi_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) .ofdata_to_platdata = pl022_spi_ofdata_to_platdata, #endif + .ops = &pl022_spi_ops, .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata), .priv_auto_alloc_size = sizeof(struct pl022_spi_slave), .probe = pl022_spi_probe, diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 64dfd748d6..5ae203d8d4 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -247,11 +247,6 @@ void spi_cs_deactivate(struct spi_slave *slave) sh_qspi_cs_deactivate(ss); } -void spi_init(void) -{ - /* nothing to do */ -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index bc2bd638e6..c58fd0ebc4 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -66,10 +66,6 @@ static int write_fifo_empty_wait(struct sh_spi *ss) return 0; } -void spi_init(void) -{ -} - static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs) { unsigned long val = 0; diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c index 0aac0c065d..cc5ab5f991 100644 --- a/drivers/spi/soft_spi_legacy.c +++ b/drivers/spi/soft_spi_legacy.c @@ -36,13 +36,6 @@ static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) /* Public Functions */ /*=====================================================================*/ -/*----------------------------------------------------------------------- - * Initialization - */ -void spi_init (void) -{ -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index b84255bd27..2bc289a74c 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -15,6 +15,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define SPI_DEFAULT_SPEED_HZ 100000 + static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) { struct dm_spi_ops *ops; @@ -58,7 +60,7 @@ int dm_spi_claim_bus(struct udevice *dev) speed = spi->max_hz; } if (!speed) - speed = 100000; + speed = SPI_DEFAULT_SPEED_HZ; if (speed != slave->speed) { int ret = spi_set_speed_mode(bus, speed, slave->mode); @@ -300,7 +302,13 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, } plat = dev_get_parent_platdata(dev); plat->cs = cs; - plat->max_hz = speed; + if (speed) { + plat->max_hz = speed; + } else { + printf("Warning: SPI speed fallback to %u kHz\n", + SPI_DEFAULT_SPEED_HZ / 1000); + plat->max_hz = SPI_DEFAULT_SPEED_HZ; + } plat->mode = mode; created = true; } else if (ret) { @@ -374,7 +382,8 @@ int spi_slave_ofdata_to_platdata(struct udevice *dev, int value; plat->cs = dev_read_u32_default(dev, "reg", -1); - plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", 0); + plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", + SPI_DEFAULT_SPEED_HZ); if (dev_read_bool(dev, "spi-cpol")) mode |= SPI_CPOL; if (dev_read_bool(dev, "spi-cpha")) diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c index b86b5a00ad..38cc743c61 100644 --- a/drivers/spi/sun4i_spi.c +++ b/drivers/spi/sun4i_spi.c @@ -129,7 +129,8 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) while (len--) { byte = readb(&priv->regs->rxdata); - *priv->rx_buf++ = byte; + if (priv->rx_buf) + *priv->rx_buf++ = byte; } } diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 7f6d4186e1..38e2a7e241 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -84,7 +84,13 @@ int sandbox_sysreset_get_status(struct udevice *dev, char *buf, int size) int sandbox_sysreset_get_last(struct udevice *dev) { - return SYSRESET_COLD; + struct sandbox_state *state = state_get_current(); + + /* + * The first phase is a power reset, after that we assume we don't + * know. + */ + return state->jumped_fname ? SYSRESET_WARM : SYSRESET_POWER; } static struct sysreset_ops sandbox_sysreset_ops = { diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index 5943a63854..20b958cfd4 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -45,5 +45,4 @@ U_BOOT_DRIVER(x86_sysreset) = { .id = UCLASS_SYSRESET, .of_match = x86_sysreset_ids, .ops = &x86_sysreset_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/tee/optee/supplicant.c b/drivers/tee/optee/supplicant.c index b1ea65bdb2..c5726ecb91 100644 --- a/drivers/tee/optee/supplicant.c +++ b/drivers/tee/optee/supplicant.c @@ -82,8 +82,8 @@ void optee_suppl_cmd(struct udevice *dev, struct tee_shm *shm_arg, cmd_shm_free(arg); break; case OPTEE_MSG_RPC_CMD_FS: - debug("OPTEE_MSG_RPC_CMD_FS not implemented\n"); - arg->ret = TEE_ERROR_NOT_IMPLEMENTED; + debug("REE FS storage isn't available\n"); + arg->ret = TEE_ERROR_STORAGE_NOT_AVAILABLE; break; case OPTEE_MSG_RPC_CMD_RPMB: optee_suppl_cmd_rpmb(dev, arg); diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index d012cf71a9..df37a798bd 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -40,6 +40,12 @@ config TIMER_EARLY use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). +config AG101P_TIMER + bool "AG101P timer support" + depends on TIMER && NDS32 + help + Select this to enable a timer for AG01P devices. + config ALTERA_TIMER bool "Altera timer support" depends on TIMER @@ -47,6 +53,34 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ARC_TIMER + bool "ARC timer support" + depends on TIMER && ARC && CLK + help + Select this to enable built-in ARC timers. + ARC cores may have up to 2 built-in timers: timer0 and timer1, + usually at least one of them exists. Either of them is supported + in U-Boot. + +config AST_TIMER + bool "Aspeed ast2400/ast2500 timer support" + depends on TIMER + default y if ARCH_ASPEED + help + Select this to enable timer for Aspeed ast2400/ast2500 devices. + This is a simple sys timer driver, it is compatible with lib/time.c, + but does not support any interrupts. Even though SoC has 8 hardware + counters, they are all treated as a single device by this driver. + This is mostly because they all share several registers which + makes it difficult to completely separate them. + +config ATCPIT100_TIMER + bool "ATCPIT100 timer support" + depends on TIMER + help + Select this to enable a ATCPIT100 timer which will be embedded + in AE3XX, AE250 boards. + config ATMEL_PIT_TIMER bool "Atmel periodic interval timer support" depends on TIMER @@ -69,18 +103,12 @@ config DESIGNWARE_APB_TIMER Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. -config SANDBOX_TIMER - bool "Sandbox timer support" - depends on SANDBOX && TIMER +config MPC83XX_TIMER + bool "MPC83xx timer support" + depends on TIMER help - Select this to enable an emulated timer for sandbox. It gets - time from host os. - -config X86_TSC_TIMER - bool "x86 Time-Stamp Counter (TSC) timer support" - depends on TIMER && X86 - help - Select this to enable Time-Stamp Counter (TSC) timer for x86. + Select this to enable support for the timer found on + devices based on the MPC83xx family of SoCs. config X86_TSC_TIMER_EARLY_FREQ int "x86 TSC timer frequency in MHz when used as the early timer" @@ -98,17 +126,26 @@ config OMAP_TIMER help Select this to enable an timer for Omap devices. -config AST_TIMER - bool "Aspeed ast2400/ast2500 timer support" - depends on TIMER - default y if ARCH_ASPEED +config RISCV_TIMER + bool "RISC-V timer support" + depends on TIMER && RISCV help - Select this to enable timer for Aspeed ast2400/ast2500 devices. - This is a simple sys timer driver, it is compatible with lib/time.c, - but does not support any interrupts. Even though SoC has 8 hardware - counters, they are all treated as a single device by this driver. - This is mostly because they all share several registers which - makes it difficult to completely separate them. + Select this to enable support for the timer as defined + by the RISC-V privileged architecture spec. + +config ROCKCHIP_TIMER + bool "Rockchip timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Rockchip devices. + +config SANDBOX_TIMER + bool "Sandbox timer support" + depends on SANDBOX && TIMER + help + Select this to enable an emulated timer for sandbox. It gets + time from host os. config STI_TIMER bool "STi timer support" @@ -117,47 +154,24 @@ config STI_TIMER help Select this to enable a timer for STi devices. -config ARC_TIMER - bool "ARC timer support" - depends on TIMER && ARC && CLK - help - Select this to enable built-in ARC timers. - ARC cores may have up to 2 built-in timers: timer0 and timer1, - usually at least one of them exists. Either of them is supported - in U-Boot. - -config AG101P_TIMER - bool "AG101P timer support" - depends on TIMER && NDS32 - help - Select this to enable a timer for AG01P devices. - -config ATCPIT100_TIMER - bool "ATCPIT100 timer support" - depends on TIMER - help - Select this to enable a ATCPIT100 timer which will be embeded - in AE3XX, AE250 boards. - -config ROCKCHIP_TIMER - bool "Rockchip timer support" - depends on TIMER - help - Select this to enable support for the timer found on - Rockchip devices. - config STM32_TIMER - bool "STM32 timer support" + bool "STM32 timer support" depends on TIMER help Select this to enable support for the timer found on STM32 devices. -config MPC83XX_TIMER - bool "MPC83xx timer support" +config X86_TSC_TIMER + bool "x86 Time-Stamp Counter (TSC) timer support" + depends on TIMER && X86 + help + Select this to enable Time-Stamp Counter (TSC) timer for x86. + +config MTK_TIMER + bool "MediaTek timer support" depends on TIMER help Select this to enable support for the timer found on - devices based on the MPC83xx family of SoCs. + MediaTek devices. endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 7f19c4970a..d0bf218b11 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,8 +13,10 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o +obj-$(CONFIG_MTK_TIMER) += mtk_timer.o diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c index 6e1ae68b32..6e20b4fc33 100644 --- a/drivers/timer/ag101p_timer.c +++ b/drivers/timer/ag101p_timer.c @@ -115,5 +115,4 @@ U_BOOT_DRIVER(altera_timer) = { .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), .probe = atftmr_timer_probe, .ops = &ag101p_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index bc76819674..6f504f7cc4 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -92,5 +92,4 @@ U_BOOT_DRIVER(altera_timer) = { .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata), .probe = altera_timer_probe, .ops = &altera_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c index cf9671ebbe..8c574ec5af 100644 --- a/drivers/timer/arc_timer.c +++ b/drivers/timer/arc_timer.c @@ -107,6 +107,5 @@ U_BOOT_DRIVER(arc_timer) = { .of_match = arc_timer_ids, .probe = arc_timer_probe, .ops = &arc_timer_ops, - .flags = DM_FLAG_PRE_RELOC, .priv_auto_alloc_size = sizeof(struct arc_timer_priv), }; diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c index 9973506f6b..21ffdbf575 100644 --- a/drivers/timer/ast_timer.c +++ b/drivers/timer/ast_timer.c @@ -90,5 +90,4 @@ U_BOOT_DRIVER(ast_timer) = { .priv_auto_alloc_size = sizeof(struct ast_timer_priv), .ofdata_to_platdata = ast_timer_ofdata_to_platdata, .ops = &ast_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c index f650c1bf66..c5d43b4a4a 100644 --- a/drivers/timer/atcpit100_timer.c +++ b/drivers/timer/atcpit100_timer.c @@ -110,5 +110,4 @@ U_BOOT_DRIVER(atcpit100_timer) = { .platdata_auto_alloc_size = sizeof(struct atcpit_timer_platdata), .probe = atcpit_timer_probe, .ops = &atcpit_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c index 603563d3de..009af2f929 100644 --- a/drivers/timer/atmel_pit_timer.c +++ b/drivers/timer/atmel_pit_timer.c @@ -85,5 +85,4 @@ U_BOOT_DRIVER(atmel_pit) = { .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata), .probe = atmel_pit_probe, .ops = &atmel_pit_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 4125a078b3..75263c5375 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -111,5 +111,4 @@ U_BOOT_DRIVER(cadence_ttc) = { .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv), .probe = cadence_ttc_probe, .ops = &cadence_ttc_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 031f429acb..085bfb02c5 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -83,7 +83,6 @@ U_BOOT_DRIVER(dw_apb_timer) = { .id = UCLASS_TIMER, .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, - .flags = DM_FLAG_PRE_RELOC, .of_match = dw_apb_timer_ids, .ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata, .priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv), diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 84a9ab072a..8e541109d4 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -244,6 +244,5 @@ U_BOOT_DRIVER(mpc83xx_timer) = { .of_match = mpc83xx_timer_ids, .probe = mpc83xx_timer_probe, .ops = &mpc83xx_timer_ops, - .flags = DM_FLAG_PRE_RELOC, .priv_auto_alloc_size = sizeof(struct mpc83xx_timer_priv), }; diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c new file mode 100644 index 0000000000..b5e76bd358 --- /dev/null +++ b/drivers/timer/mtk_timer.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek timer driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include +#include + +#define MTK_GPT4_CTRL 0x40 +#define MTK_GPT4_CLK 0x44 +#define MTK_GPT4_CNT 0x48 + +#define GPT4_ENABLE BIT(0) +#define GPT4_CLEAR BIT(1) +#define GPT4_FREERUN GENMASK(5, 4) +#define GPT4_CLK_SYS 0x0 +#define GPT4_CLK_DIV1 0x0 + +struct mtk_timer_priv { + void __iomem *base; +}; + +static int mtk_timer_get_count(struct udevice *dev, u64 *count) +{ + struct mtk_timer_priv *priv = dev_get_priv(dev); + u32 val = readl(priv->base + MTK_GPT4_CNT); + + *count = timer_conv_64(val); + + return 0; +} + +static int mtk_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mtk_timer_priv *priv = dev_get_priv(dev); + struct clk clk, parent; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &parent); + if (!ret) { + ret = clk_set_parent(&clk, &parent); + if (ret) + return ret; + } + + uc_priv->clock_rate = clk_get_rate(&clk); + if (!uc_priv->clock_rate) + return -EINVAL; + + return 0; +} + +static const struct timer_ops mtk_timer_ops = { + .get_count = mtk_timer_get_count, +}; + +static const struct udevice_id mtk_timer_ids[] = { + { .compatible = "mediatek,timer" }, + { } +}; + +U_BOOT_DRIVER(mtk_timer) = { + .name = "mtk_timer", + .id = UCLASS_TIMER, + .of_match = mtk_timer_ids, + .priv_auto_alloc_size = sizeof(struct mtk_timer_priv), + .probe = mtk_timer_probe, + .ops = &mtk_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index f10df69092..a13fb71165 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -104,5 +104,4 @@ U_BOOT_DRIVER(omap_timer) = { .priv_auto_alloc_size = sizeof(struct omap_timer_priv), .probe = omap_timer_probe, .ops = &omap_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c new file mode 100644 index 0000000000..9f9f070e0b --- /dev/null +++ b/drivers/timer/riscv_timer.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * RISC-V privileged architecture defined generic timer driver + * + * This driver relies on RISC-V platform codes to provide the essential API + * riscv_get_time() which is supposed to return the timer counter as defined + * by the RISC-V privileged architecture spec. + * + * This driver can be used in both M-mode and S-mode U-Boot. + */ + +#include +#include +#include +#include +#include + +/** + * riscv_get_time() - get the timer counter + * + * Platform codes should provide this API in order to make this driver function. + * + * @time: the 64-bit timer count as defined by the RISC-V privileged + * architecture spec. + * @return: 0 on success, -ve on error. + */ +extern int riscv_get_time(u64 *time); + +static int riscv_timer_get_count(struct udevice *dev, u64 *count) +{ + return riscv_get_time(count); +} + +static int riscv_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* clock frequency was passed from the cpu driver as driver data */ + uc_priv->clock_rate = dev->driver_data; + + return 0; +} + +static const struct timer_ops riscv_timer_ops = { + .get_count = riscv_timer_get_count, +}; + +U_BOOT_DRIVER(riscv_timer) = { + .name = "riscv_timer", + .id = UCLASS_TIMER, + .probe = riscv_timer_probe, + .ops = &riscv_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 17bf6a44c3..69019740b0 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -163,7 +163,6 @@ U_BOOT_DRIVER(rockchip_rk3368_timer) = { .of_match = rockchip_timer_ids, .probe = rockchip_timer_probe, .ops = &rockchip_timer_ops, - .flags = DM_FLAG_PRE_RELOC, .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv), #if CONFIG_IS_ENABLED(OF_PLATDATA) .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat), diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c index f7f0e72fe1..9def7e02f4 100644 --- a/drivers/timer/sti-timer.c +++ b/drivers/timer/sti-timer.c @@ -74,5 +74,4 @@ U_BOOT_DRIVER(sti_timer) = { .priv_auto_alloc_size = sizeof(struct sti_timer_priv), .probe = sti_timer_probe, .ops = &sti_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index 9a856b1b5a..76315100e2 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -132,6 +132,5 @@ U_BOOT_DRIVER(stm32_timer) = { .priv_auto_alloc_size = sizeof(struct stm32_timer_priv), .probe = stm32_timer_probe, .ops = &stm32_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index fe73f71819..12ee6eb804 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -108,7 +108,7 @@ int notrace dm_timer_init(void) * If the timer is not marked to be bound before * relocation, bind it anyway. */ - if (!lists_bind_fdt(dm_root(), node, &dev)) { + if (!lists_bind_fdt(dm_root(), node, &dev, false)) { ret = device_probe(dev); if (ret) return ret; diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index da7c812908..ba940ebf1c 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -424,5 +424,4 @@ U_BOOT_DRIVER(tsc_timer) = { .of_match = tsc_timer_ids, .probe = tsc_timer_probe, .ops = &tsc_timer_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index e993fd9f83..30194bce07 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -388,31 +388,6 @@ static int tis_readresponse(struct udevice *dev, u8 *buffer, size_t len) return offset; } -static int tpm_tis_lpc_open(struct udevice *dev) -{ - struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); - struct tpm_locality *regs = priv->regs; - u8 locality = 0; /* we use locality zero for everything. */ - int ret; - - /* now request access to locality. */ - tpm_write_word(priv, TIS_ACCESS_REQUEST_USE, ®s[locality].access); - - /* did we get a lock? */ - ret = tis_wait_reg(priv, ®s[locality].access, - TIS_ACCESS_ACTIVE_LOCALITY, - TIS_ACCESS_ACTIVE_LOCALITY); - if (ret == -ETIMEDOUT) { - printf("%s:%d - failed to lock locality %d\n", - __FILE__, __LINE__, locality); - return ret; - } - - tpm_write_word(priv, TIS_STS_COMMAND_READY, - ®s[locality].tpm_status); - return 0; -} - static int tpm_tis_lpc_close(struct udevice *dev) { struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); @@ -434,6 +409,38 @@ static int tpm_tis_lpc_close(struct udevice *dev) return 0; } +static int tpm_tis_lpc_open(struct udevice *dev) +{ + struct tpm_tis_lpc_priv *priv = dev_get_priv(dev); + struct tpm_locality *regs = priv->regs; + u8 locality = 0; /* we use locality zero for everything. */ + int ret; + + ret = tpm_tis_lpc_close(dev); + if (ret) { + printf("%s: Failed to close TPM\n", __func__); + return ret; + } + + /* now request access to locality. */ + tpm_write_word(priv, TIS_ACCESS_REQUEST_USE, ®s[locality].access); + + /* did we get a lock? */ + ret = tis_wait_reg(priv, ®s[locality].access, + TIS_ACCESS_ACTIVE_LOCALITY, + TIS_ACCESS_ACTIVE_LOCALITY); + if (ret == -ETIMEDOUT) { + printf("%s:%d - failed to lock locality %d\n", + __FILE__, __LINE__, locality); + return ret; + } + + tpm_write_word(priv, TIS_STS_COMMAND_READY, + ®s[locality].tpm_status); + + return 0; +} + static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size) { ulong chip_type = dev_get_driver_data(dev); diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c index 79517f015a..3336f559e5 100644 --- a/drivers/tpm/tpm_tis_sandbox.c +++ b/drivers/tpm/tpm_tis_sandbox.c @@ -187,9 +187,11 @@ static int sandbox_tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, code = get_unaligned_be32(sendbuf + sizeof(uint16_t) + sizeof(uint32_t)); +#ifdef DEBUG printf("tpm: %zd bytes, recv_len %zd, cmd = %x\n", send_size, *recv_len, code); print_buffer(0, sendbuf, 1, send_size, 0); +#endif switch (code) { case TPM_CMD_GET_CAPABILITY: type = get_unaligned_be32(sendbuf + 14); @@ -306,6 +308,10 @@ static int sandbox_tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, printf("Unknown tpm command %02x\n", code); return -ENOSYS; } +#ifdef DEBUG + printf("tpm: rx recv_len %zd\n", *recv_len); + print_buffer(0, recvbuf, 1, *recv_len, 0); +#endif return 0; } diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 4fbe172e05..3b53bf2c58 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -47,6 +47,25 @@ config DM_USB declared with the U_BOOT_USB_DEVICE() macro and will be automatically probed when found on the bus. +config SPL_DM_USB + bool "Enable driver model for USB in SPL" + depends on SPL_DM && DM_USB + default y + +config DM_USB_GADGET + bool "Enable driver model for USB Gadget" + depends on DM_USB + help + Enable driver model for USB Gadget (Peripheral + mode) + +config SPL_DM_USB_GADGET + bool "Enable driver model for USB Gadget in sPL" + depends on SPL_DM_USB + help + Enable driver model for USB Gadget in SPL + (Peripheral mode) + source "drivers/usb/host/Kconfig" source "drivers/usb/dwc3/Kconfig" @@ -65,6 +84,7 @@ comment "USB peripherals" config USB_STORAGE bool "USB Mass Storage support" + depends on !(BLK && !DM_USB) ---help--- Say Y here if you want to connect USB mass storage devices to your board's USB port. diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile index 55e0547b16..3bedbf213f 100644 --- a/drivers/usb/common/Makefile +++ b/drivers/usb/common/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2016 Freescale Semiconductor, Inc. # -obj-$(CONFIG_DM_USB) += common.o +obj-$(CONFIG_$(SPL_)DM_USB) += common.o obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o fsl-errata.o diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 9f0b8a2d0b..bbd8105c06 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -38,10 +38,11 @@ config USB_DWC3_OMAP Say 'Y' here if you have one such device config USB_DWC3_GENERIC - bool "Xilinx ZynqMP and similar Platforms" + bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue)" depends on DM_USB && USB_DWC3 && MISC help - Some platforms can reuse this DWC3 generic implementation. + Select this for Xilinx ZynqMP and similar Platforms. + This wrapper supports Host and Peripheral operation modes. config USB_DWC3_UNIPHIER bool "DesignWare USB3 Host Support on UniPhier Platforms" diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1ab5cee609..56e2a046bf 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -19,7 +19,7 @@ #include #include #include - +#include #include #include @@ -789,8 +789,92 @@ MODULE_AUTHOR("Felipe Balbi "); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) +int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys) +{ + int i, ret, count; + struct phy *usb_phys; + /* Return if no phy declared */ + if (!dev_read_prop(dev, "phys", NULL)) + return 0; + count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); + if (count <= 0) + return count; + + usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), + GFP_KERNEL); + if (!usb_phys) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(dev, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, dev->name); + return ret; + } + } + + for (i = 0; i < count; i++) { + ret = generic_phy_init(&usb_phys[i]); + if (ret) { + pr_err("Can't init USB PHY%d for %s\n", + i, dev->name); + goto phys_init_err; + } + } + + for (i = 0; i < count; i++) { + ret = generic_phy_power_on(&usb_phys[i]); + if (ret) { + pr_err("Can't power USB PHY%d for %s\n", + i, dev->name); + goto phys_poweron_err; + } + } + + *array = usb_phys; + *num_phys = count; + return 0; + +phys_poweron_err: + for (i = count - 1; i >= 0; i--) + generic_phy_power_off(&usb_phys[i]); + + for (i = 0; i < count; i++) + generic_phy_exit(&usb_phys[i]); + + return ret; + +phys_init_err: + for (; i >= 0; i--) + generic_phy_exit(&usb_phys[i]); + + return ret; +} + +int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys) +{ + int i, ret; + + for (i = 0; i < num_phys; i++) { + if (!generic_phy_valid(&usb_phys[i])) + continue; + + ret = generic_phy_power_off(&usb_phys[i]); + ret |= generic_phy_exit(&usb_phys[i]); + if (ret) { + pr_err("Can't shutdown USB PHY%d for %s\n", + i, dev->name); + } + } + + return 0; +} +#endif + +#if CONFIG_IS_ENABLED(DM_USB_GADGET) int dwc3_init(struct dwc3 *dwc) { int ret; @@ -841,5 +925,4 @@ void dwc3_remove(struct dwc3 *dwc) dwc3_core_exit(dwc); kfree(dwc->mem); } - #endif diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 58fe91dc51..cfe29884e7 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -712,7 +712,7 @@ struct dwc3 { /* device lock */ spinlock_t lock; -#if defined(__UBOOT__) && defined(CONFIG_DM_USB) +#if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; #else struct device *dev; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 56c9fd657f..3e6c494dc6 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -8,72 +8,89 @@ */ #include +#include #include #include #include -#include -#include +#include #include #include #include #include #include "core.h" #include "gadget.h" -#include "linux-compat.h" +#include +#include -DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +struct dwc3_generic_peripheral { + struct dwc3 dwc3; + struct phy *phys; + int num_phys; + fdt_addr_t base; +}; -int usb_gadget_handle_interrupts(int index) +int dm_usb_gadget_handle_interrupts(struct udevice *dev) { - struct dwc3 *priv; - struct udevice *dev; - int ret; + struct dwc3_generic_peripheral *priv = dev_get_priv(dev); + struct dwc3 *dwc3 = &priv->dwc3; - ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev); - if (!dev || ret) { - pr_err("No USB device found\n"); - return -ENODEV; - } - - priv = dev_get_priv(dev); - - dwc3_gadget_uboot_handle_interrupt(priv); + dwc3_gadget_uboot_handle_interrupt(dwc3); return 0; } static int dwc3_generic_peripheral_probe(struct udevice *dev) { - struct dwc3 *priv = dev_get_priv(dev); + int rc; + struct dwc3_generic_peripheral *priv = dev_get_priv(dev); + struct dwc3 *dwc3 = &priv->dwc3; - return dwc3_init(priv); + rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); + if (rc) + return rc; + + dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE); + dwc3->regs += DWC3_GLOBALS_REGS_START; + dwc3->dev = dev; + + rc = dwc3_init(dwc3); + if (rc) { + unmap_physmem(dwc3->regs, MAP_NOCACHE); + return rc; + } + + return 0; } static int dwc3_generic_peripheral_remove(struct udevice *dev) { - struct dwc3 *priv = dev_get_priv(dev); + struct dwc3_generic_peripheral *priv = dev_get_priv(dev); + struct dwc3 *dwc3 = &priv->dwc3; - dwc3_remove(priv); + dwc3_remove(dwc3); + dwc3_shutdown_phy(dev, priv->phys, priv->num_phys); + unmap_physmem(dwc3->regs, MAP_NOCACHE); return 0; } static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) { - struct dwc3 *priv = dev_get_priv(dev); + struct dwc3_generic_peripheral *priv = dev_get_priv(dev); + struct dwc3 *dwc3 = &priv->dwc3; int node = dev_of_offset(dev); - priv->regs = (void *)devfdt_get_addr(dev); - priv->regs += DWC3_GLOBALS_REGS_START; + priv->base = devfdt_get_addr(dev); - priv->maximum_speed = usb_get_maximum_speed(node); - if (priv->maximum_speed == USB_SPEED_UNKNOWN) { + dwc3->maximum_speed = usb_get_maximum_speed(node); + if (dwc3->maximum_speed == USB_SPEED_UNKNOWN) { pr_err("Invalid usb maximum speed\n"); return -ENODEV; } - priv->dr_mode = usb_get_dr_mode(node); - if (priv->dr_mode == USB_DR_MODE_UNKNOWN) { + dwc3->dr_mode = usb_get_dr_mode(node); + if (dwc3->dr_mode == USB_DR_MODE_UNKNOWN) { pr_err("Invalid usb mode setup\n"); return -ENODEV; } @@ -81,24 +98,112 @@ static int dwc3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) return 0; } -static int dwc3_generic_peripheral_bind(struct udevice *dev) -{ - return device_probe(dev); -} - U_BOOT_DRIVER(dwc3_generic_peripheral) = { .name = "dwc3-generic-peripheral", - .id = UCLASS_USB_DEV_GENERIC, + .id = UCLASS_USB_GADGET_GENERIC, .ofdata_to_platdata = dwc3_generic_peripheral_ofdata_to_platdata, .probe = dwc3_generic_peripheral_probe, .remove = dwc3_generic_peripheral_remove, - .bind = dwc3_generic_peripheral_bind, - .platdata_auto_alloc_size = sizeof(struct usb_platdata), - .priv_auto_alloc_size = sizeof(struct dwc3), - .flags = DM_FLAG_ALLOC_PRIV_DMA, + .priv_auto_alloc_size = sizeof(struct dwc3_generic_peripheral), +}; +#endif + +struct dwc3_glue_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + fdt_addr_t regs; }; -static int dwc3_generic_bind(struct udevice *parent) +struct dwc3_glue_ops { + void (*select_dr_mode)(struct udevice *dev, int index, + enum usb_dr_mode mode); +}; + +void dwc3_ti_select_dr_mode(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ +#define USBOTGSS_UTMI_OTG_STATUS 0x0084 +#define USBOTGSS_UTMI_OTG_OFFSET 0x0480 + +/* UTMI_OTG_STATUS REGISTER */ +#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31) +#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9) +#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8) +#define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4) +#define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3) +#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2) +#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1) +enum dwc3_omap_utmi_mode { + DWC3_OMAP_UTMI_MODE_UNKNOWN = 0, + DWC3_OMAP_UTMI_MODE_HW, + DWC3_OMAP_UTMI_MODE_SW, +}; + + u32 use_id_pin; + u32 host_mode; + u32 reg; + u32 utmi_mode; + u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS; + + struct dwc3_glue_data *glue = dev_get_platdata(dev); + void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE); + + if (device_is_compatible(dev, "ti,am437x-dwc3")) + utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET; + + utmi_mode = dev_read_u32_default(dev, "utmi-mode", + DWC3_OMAP_UTMI_MODE_UNKNOWN); + if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) { + debug("%s: OTG is not supported. defaulting to PERIPHERAL\n", + dev->name); + mode = USB_DR_MODE_PERIPHERAL; + } + + switch (mode) { + case USB_DR_MODE_PERIPHERAL: + use_id_pin = 0; + host_mode = 0; + break; + case USB_DR_MODE_HOST: + use_id_pin = 0; + host_mode = 1; + break; + case USB_DR_MODE_OTG: + default: + use_id_pin = 1; + host_mode = 0; + break; + } + + reg = readl(base + utmi_status_offset); + + reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE); + if (!use_id_pin) + reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; + + writel(reg, base + utmi_status_offset); + + reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND | + USBOTGSS_UTMI_OTG_STATUS_VBUSVALID | + USBOTGSS_UTMI_OTG_STATUS_IDDIG); + + reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID | + USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; + + if (!host_mode) + reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG | + USBOTGSS_UTMI_OTG_STATUS_VBUSVALID; + + writel(reg, base + utmi_status_offset); + + unmap_physmem(base, MAP_NOCACHE); +} + +struct dwc3_glue_ops ti_ops = { + .select_dr_mode = dwc3_ti_select_dr_mode, +}; + +static int dwc3_glue_bind(struct udevice *parent) { const void *fdt = gd->fdt_blob; int node; @@ -109,29 +214,32 @@ static int dwc3_generic_bind(struct udevice *parent) const char *name = fdt_get_name(fdt, node, NULL); enum usb_dr_mode dr_mode; struct udevice *dev; - const char *driver; + const char *driver = NULL; debug("%s: subnode name: %s\n", __func__, name); - if (strncmp(name, "dwc3@", 4)) - continue; dr_mode = usb_get_dr_mode(node); switch (dr_mode) { case USB_DR_MODE_PERIPHERAL: case USB_DR_MODE_OTG: +#if CONFIG_IS_ENABLED(DM_USB_GADGET) debug("%s: dr_mode: OTG or Peripheral\n", __func__); driver = "dwc3-generic-peripheral"; +#endif break; case USB_DR_MODE_HOST: debug("%s: dr_mode: HOST\n", __func__); - driver = "dwc3-generic-host"; + driver = "xhci-dwc3"; break; default: debug("%s: unsupported dr_mode\n", __func__); return -ENODEV; }; + if (!driver) + continue; + ret = device_bind_driver_to_node(parent, driver, name, offset_to_ofnode(node), &dev); if (ret) { @@ -144,14 +252,109 @@ static int dwc3_generic_bind(struct udevice *parent) return 0; } -static const struct udevice_id dwc3_generic_ids[] = { +static int dwc3_glue_reset_init(struct udevice *dev, + struct dwc3_glue_data *glue) +{ + int ret; + + ret = reset_get_bulk(dev, &glue->resets); + if (ret == -ENOTSUPP) + return 0; + else if (ret) + return ret; + + ret = reset_deassert_bulk(&glue->resets); + if (ret) { + reset_release_bulk(&glue->resets); + return ret; + } + + return 0; +} + +static int dwc3_glue_clk_init(struct udevice *dev, + struct dwc3_glue_data *glue) +{ + int ret; + + ret = clk_get_bulk(dev, &glue->clks); + if (ret == -ENOSYS) + return 0; + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable_bulk(&glue->clks); + if (ret) { + clk_release_bulk(&glue->clks); + return ret; + } +#endif + + return 0; +} + +static int dwc3_glue_probe(struct udevice *dev) +{ + struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev); + struct dwc3_glue_data *glue = dev_get_platdata(dev); + struct udevice *child = NULL; + int index = 0; + int ret; + + glue->regs = dev_read_addr(dev); + + ret = dwc3_glue_clk_init(dev, glue); + if (ret) + return ret; + + ret = dwc3_glue_reset_init(dev, glue); + if (ret) + return ret; + + ret = device_find_first_child(dev, &child); + if (ret) + return ret; + + while (child) { + enum usb_dr_mode dr_mode; + + dr_mode = usb_get_dr_mode(dev_of_offset(child)); + device_find_next_child(&child); + if (ops && ops->select_dr_mode) + ops->select_dr_mode(dev, index, dr_mode); + index++; + } + + return 0; +} + +static int dwc3_glue_remove(struct udevice *dev) +{ + struct dwc3_glue_data *glue = dev_get_platdata(dev); + + reset_release_bulk(&glue->resets); + + clk_release_bulk(&glue->clks); + + return dm_scan_fdt_dev(dev); +} + +static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "xlnx,zynqmp-dwc3" }, + { .compatible = "ti,keystone-dwc3"}, + { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, + { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, { } }; U_BOOT_DRIVER(dwc3_generic_wrapper) = { .name = "dwc3-generic-wrapper", .id = UCLASS_MISC, - .of_match = dwc3_generic_ids, - .bind = dwc3_generic_bind, + .of_match = dwc3_glue_ids, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data), + }; diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 4f68887b8d..818efb3e8d 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -12,7 +12,7 @@ * * commit c00552ebaf : Merge 3.18-rc7 into usb-next */ - +#include #include #include diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index a711e8dc98..d6c6a33ada 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c index d168e868e3..e7ea12c163 100644 --- a/drivers/usb/dwc3/ti_usb_phy.c +++ b/drivers/usb/dwc3/ti_usb_phy.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 941158abdd..e5f73e3d4c 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include "usb_ether.h" diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 1ce3361b45..3aca9ac265 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -271,7 +271,7 @@ int usb_host_eth_scan(int mode) } usb_max_eth_dev = 0; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /* * TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB * Ethernet driver and then most of this file can be removed. diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 39ea87005c..2a6626b443 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "at91_udc.h" diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index c9d483318f..dffa5117f9 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "atmel_usba_udc.h" diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 0a84f6850d..bd596ce977 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1015,7 +1015,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) return -EINVAL; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) ret = usb_setup_ehci_gadget(&controller.ctrl); #else ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index e3edd10e29..3c7ad033e3 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -33,7 +33,6 @@ #include "dwc2_udc_otg_regs.h" #include "dwc2_udc_otg_priv.h" -#include /***********************************************************/ diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c index 47aa78ae94..c4338af0d7 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_phy.c +++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c @@ -33,7 +33,6 @@ #include "dwc2_udc_otg_regs.h" #include "dwc2_udc_otg_priv.h" -#include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg_priv.h b/drivers/usb/gadget/dwc2_udc_otg_priv.h index b64e222b6d..aaa90187fb 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_priv.h +++ b/drivers/usb/gadget/dwc2_udc_otg_priv.h @@ -12,7 +12,6 @@ #include #include #include -#include #include /*-------------------------------------------------------------------------*/ diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 90ef1f055f..3b3d9af681 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -100,9 +100,6 @@ struct eth_dev { struct usb_gadget *gadget; struct usb_request *req; /* for control responses */ struct usb_request *stat_req; /* for cdc & rndis status */ -#ifdef CONFIG_DM_USB - struct udevice *usb_udev; -#endif u8 config; struct usb_ep *in_ep, *out_ep, *status_ep; @@ -2336,40 +2333,17 @@ fail: } /*-------------------------------------------------------------------------*/ - -#ifdef CONFIG_DM_USB -int dm_usb_init(struct eth_dev *e_dev) -{ - struct udevice *dev = NULL; - int ret; - - ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev); - if (!dev || ret) { - pr_err("No USB device found\n"); - return -ENODEV; - } - - e_dev->usb_udev = dev; - - return ret; -} -#endif - static int _usb_eth_init(struct ether_priv *priv) { struct eth_dev *dev = &priv->ethdev; struct usb_gadget *gadget; unsigned long ts; + int ret; unsigned long timeout = USB_CONNECT_TIMEOUT; -#ifdef CONFIG_DM_USB - if (dm_usb_init(dev)) { - pr_err("USB ether not found\n"); - return -ENODEV; - } -#else - board_usb_init(0, USB_INIT_DEVICE); -#endif + ret = usb_gadget_initialize(0); + if (ret) + return ret; /* Configure default mac-addresses for the USB ethernet device */ #ifdef CONFIG_USBNET_DEV_ADDR @@ -2541,9 +2515,7 @@ void _usb_eth_halt(struct ether_priv *priv) } usb_gadget_unregister_driver(&priv->eth_driver); -#ifndef CONFIG_DM_USB - board_usb_cleanup(0, USB_INIT_DEVICE); -#endif + usb_gadget_release(0); } #ifndef CONFIG_DM_ETH @@ -2699,7 +2671,7 @@ int usb_ether_init(void) struct udevice *usb_dev; int ret; - ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &usb_dev); + ret = uclass_first_device(UCLASS_USB_GADGET_GENERIC, &usb_dev); if (!usb_dev || ret) { pr_err("No USB device found\n"); return ret; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index a3101afa0d..45c7b58eed 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -256,7 +256,7 @@ #include #include #include -#include +#include #include /*------------------------------------------------------------------------*/ diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 00a9f88a41..ae97ab2b49 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -100,6 +100,7 @@ struct f_sdp { enum sdp_state state; enum sdp_state next_state; u32 dnl_address; + u32 dnl_bytes; u32 dnl_bytes_remaining; u32 jmp_address; bool always_send_status; @@ -276,6 +277,7 @@ static void sdp_rx_command_complete(struct usb_ep *ep, struct usb_request *req) sdp->state = SDP_STATE_RX_FILE_DATA; sdp->dnl_address = be32_to_cpu(cmd->addr); sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt); + sdp->dnl_bytes = sdp->dnl_bytes_remaining; sdp->next_state = SDP_STATE_IDLE; printf("Downloading file of size %d to 0x%08x... ", @@ -355,6 +357,9 @@ static void sdp_rx_data_complete(struct usb_ep *ep, struct usb_request *req) if (sdp->dnl_bytes_remaining) return; +#ifndef CONFIG_SPL_BUILD + env_set_hex("filesize", sdp->dnl_bytes); +#endif printf("done\n"); switch (sdp->state) { diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index 44092df25b..09c0a30b2b 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -29,7 +29,6 @@ #include #include -#include #include #include "pxa25x_udc.h" diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 449339f2c4..38ac2dd475 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -2,4 +2,8 @@ # # USB peripheral controller drivers +ifndef CONFIG_$(SPL_)DM_USB_GADGET obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o +endif + +obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-uclass.o udc-core.o diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index f5c30dd750..62b47781dd 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -18,7 +18,8 @@ #include #include #include - +#include +#include #include #include diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c new file mode 100644 index 0000000000..062051857a --- /dev/null +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Written by Jean-Jacques Hiblot + */ + +#include +#include +#include +#include + +#define MAX_UDC_DEVICES 4 +static struct udevice *dev_array[MAX_UDC_DEVICES]; +int usb_gadget_initialize(int index) +{ + int ret; + struct udevice *dev = NULL; + + if (index < 0 || index >= ARRAY_SIZE(dev_array)) + return -EINVAL; + if (dev_array[index]) + return 0; + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, index, &dev); + if (!dev || ret) { + pr_err("No USB device found\n"); + return -ENODEV; + } + dev_array[index] = dev; + return 0; +} + +int usb_gadget_release(int index) +{ +#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE) + int ret; + if (index < 0 || index >= ARRAY_SIZE(dev_array)) + return -EINVAL; + + ret = device_remove(dev_array[index], DM_REMOVE_NORMAL); + if (!ret) + dev_array[index] = NULL; + return ret; +#else + return -ENOTSUPP; +#endif +} + +int usb_gadget_handle_interrupts(int index) +{ + if (index < 0 || index >= ARRAY_SIZE(dev_array)) + return -EINVAL; + return dm_usb_gadget_handle_interrupts(dev_array[index]); +} + +UCLASS_DRIVER(usb_gadget_generic) = { + .id = UCLASS_USB_GADGET_GENERIC, + .name = "usb_gadget_generic", +}; diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cb8c315a15..948683a52b 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -3,8 +3,8 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_DM_USB -obj-$(CONFIG_CMD_USB) += usb-uclass.o +ifdef CONFIG_$(SPL_)DM_USB +obj-y += usb-uclass.o obj-$(CONFIG_SANDBOX) += usb-sandbox.o endif @@ -50,7 +50,6 @@ obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o -obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index b6f008a400..a62a2f8a95 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -29,7 +29,7 @@ #define MAX_ENDPOINT 16 struct dwc2_priv { -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); #ifdef CONFIG_DM_REGULATOR @@ -54,7 +54,7 @@ struct dwc2_priv { struct reset_ctl_bulk resets; }; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* We need cacheline-aligned buffers for DMA transfers and dcache support */ DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, ARCH_DMA_MINALIGN); @@ -168,7 +168,7 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs) mdelay(100); } -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) +#if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR) static int dwc_vbus_supply_init(struct udevice *dev) { struct dwc2_priv *priv = dev_get_priv(dev); @@ -211,7 +211,7 @@ static int dwc_vbus_supply_init(struct udevice *dev) return 0; } -#if defined(CONFIG_DM_USB) +#if CONFIG_IS_ENABLED(DM_USB) static int dwc_vbus_supply_exit(struct udevice *dev) { return 0; @@ -1222,7 +1222,7 @@ static void dwc2_uninit_common(struct dwc2_core_regs *regs) DWC2_HPRT0_PRTRST); } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int len, struct devrequest *setup) { @@ -1267,7 +1267,7 @@ int usb_lowlevel_stop(int index) } #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 66dc63da08..6900848df1 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -14,7 +14,7 @@ #include "ehci.h" -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index a8fb2b8ac3..23e7e7125f 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct ehci_fsl_priv { struct ehci_ctrl ehci; fdt_addr_t hcd_base; @@ -34,7 +34,7 @@ struct ehci_fsl_priv { #endif static void set_txfifothresh(struct usb_ehci *, u32); -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor); #else @@ -54,7 +54,7 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) } } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_ofdata_to_platdata(struct udevice *dev) { struct ehci_fsl_priv *priv = dev_get_priv(dev); @@ -183,7 +183,7 @@ int ehci_hcd_stop(int index) } #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, struct ehci_hccr *hccr, struct ehci_hcor *hcor) #else @@ -192,7 +192,7 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci, #endif { const char *phy_type = NULL; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) size_t len; char current_usb_controller[5]; #endif @@ -218,7 +218,7 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) if (priv->phy_type) phy_type = priv->phy_type; #else diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index d1d8f08d98..4b28db70a5 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -30,7 +30,7 @@ */ #define HCHALT_TIMEOUT (8 * 1000) -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; #endif @@ -111,7 +111,7 @@ static struct descriptor { static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev) { -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) return dev_get_priv(usb_get_bus(udev->dev)); #else return udev->controller; @@ -973,7 +973,7 @@ static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) } } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops) { struct ehci_ctrl *ctrl = &ehcic[index]; @@ -1097,7 +1097,7 @@ static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int usb_lowlevel_stop(int index) { ehci_shutdown(&ehcic[index]); @@ -1518,7 +1518,7 @@ static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe, return result; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int length) { @@ -1556,7 +1556,7 @@ int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) } #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 73432f2acd..8efe6b63b9 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * USB 2.0 Bridge Address Decoding registers setup */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct ehci_mvebu_priv { struct ehci_ctrl ehci; @@ -228,4 +228,4 @@ int ehci_hcd_stop(int index) return 0; } -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index be010b1adb..1acf08dfb7 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -335,7 +335,7 @@ int ehci_mx6_common_init(struct usb_ehci *ehci, int index) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 6150f3d888..04e7c5e37f 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -19,7 +19,7 @@ struct ehci_pci_priv { struct phy phy; }; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) { @@ -121,9 +121,9 @@ int ehci_hcd_stop(int index) { return 0; } -#endif /* nCONFIG_DM_USB */ +#endif /* !CONFIG_IS_ENABLED(DM_USB) */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ehci_pci_probe(struct udevice *dev) { struct ehci_hccr *hccr; @@ -173,4 +173,4 @@ static struct pci_device_id ehci_pci_supported[] = { U_BOOT_PCI_DEVICE(ehci_pci, ehci_pci_supported); -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 22e5afad6e..a16cf135e3 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -153,7 +153,7 @@ int ehci_vf_common_init(struct usb_ehci *ehci, int index) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 6ea9f105a6..3b6f889f7b 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -120,7 +120,7 @@ static struct pci_device_id ehci_pci_ids[] = { #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /* * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep * them around when building for older boards not yet converted to the dm @@ -131,7 +131,7 @@ static struct pci_device_id ehci_pci_ids[] = { #define ohci_mdelay(x) mdelay(x) #endif -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* global ohci_t */ static ohci_t gohci; /* this must be aligned to a 256 byte boundary */ @@ -1691,7 +1691,7 @@ static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev, return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* submit routines called from usb.c */ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len) @@ -1980,7 +1980,7 @@ static int hc_interrupt(ohci_t *ohci) /*-------------------------------------------------------------------------*/ -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /*-------------------------------------------------------------------------*/ @@ -2130,7 +2130,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, } #endif -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h index fba78dcf7a..f9f02cb09c 100644 --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -27,7 +27,7 @@ #define ED_ALIGNMENT 16 #endif -#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32 +#if CONFIG_IS_ENABLED(DM_USB) && ARCH_DMA_MINALIGN > 32 #define TD_ALIGNMENT ARCH_DMA_MINALIGN #else #define TD_ALIGNMENT 32 @@ -406,7 +406,7 @@ typedef struct ohci { const char *slot_name; } ohci_t; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) extern struct dm_usb_ops ohci_usb_ops; int ohci_register(struct udevice *dev, struct ohci_regs *regs); diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 80754d76d0..83b9f119e7 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "xhci.h" #include @@ -109,106 +110,22 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) GFLADJ_30MHZ(val)); } -#ifdef CONFIG_DM_USB -static int xhci_dwc3_setup_phy(struct udevice *dev) -{ - struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); - int i, ret, count; - - /* Return if no phy declared */ - if (!dev_read_prop(dev, "phys", NULL)) - return 0; - - count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (count <= 0) - return count; - - plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), - GFP_KERNEL); - if (!plat->usb_phys) - return -ENOMEM; - - for (i = 0; i < count; i++) { - ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]); - if (ret && ret != -ENOENT) { - pr_err("Failed to get USB PHY%d for %s\n", - i, dev->name); - return ret; - } - - ++plat->num_phys; - } - - for (i = 0; i < plat->num_phys; i++) { - ret = generic_phy_init(&plat->usb_phys[i]); - if (ret) { - pr_err("Can't init USB PHY%d for %s\n", - i, dev->name); - goto phys_init_err; - } - } - - for (i = 0; i < plat->num_phys; i++) { - ret = generic_phy_power_on(&plat->usb_phys[i]); - if (ret) { - pr_err("Can't power USB PHY%d for %s\n", - i, dev->name); - goto phys_poweron_err; - } - } - - return 0; - -phys_poweron_err: - for (; i >= 0; i--) - generic_phy_power_off(&plat->usb_phys[i]); - - for (i = 0; i < plat->num_phys; i++) - generic_phy_exit(&plat->usb_phys[i]); - - return ret; - -phys_init_err: - for (; i >= 0; i--) - generic_phy_exit(&plat->usb_phys[i]); - - return ret; -} - -static int xhci_dwc3_shutdown_phy(struct udevice *dev) -{ - struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); - int i, ret; - - for (i = 0; i < plat->num_phys; i++) { - if (!generic_phy_valid(&plat->usb_phys[i])) - continue; - - ret = generic_phy_power_off(&plat->usb_phys[i]); - ret |= generic_phy_exit(&plat->usb_phys[i]); - if (ret) { - pr_err("Can't shutdown USB PHY%d for %s\n", - i, dev->name); - } - } - - return 0; -} - +#if CONFIG_IS_ENABLED(DM_USB) static int xhci_dwc3_probe(struct udevice *dev) { struct xhci_hcor *hcor; struct xhci_hccr *hccr; struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); int ret; hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); hcor = (struct xhci_hcor *)((uintptr_t)hccr + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); - ret = xhci_dwc3_setup_phy(dev); - if (ret) + ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys); + if (ret && (ret != -ENOTSUPP)) return ret; dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); @@ -227,7 +144,9 @@ static int xhci_dwc3_probe(struct udevice *dev) static int xhci_dwc3_remove(struct udevice *dev) { - xhci_dwc3_shutdown_phy(dev); + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); + + dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys); return xhci_deregister(dev); } diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 047a8dfdef..c0b98a8ec7 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -19,7 +19,7 @@ #include /* Declare global data pointer */ -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) static struct fsl_xhci fsl_xhci; unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; #else @@ -107,7 +107,7 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) return 0; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int xhci_fsl_probe(struct udevice *dev) { struct xhci_fsl_priv *priv = dev_get_priv(dev); diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c deleted file mode 100644 index 200b3f0e10..0000000000 --- a/drivers/usb/host/xhci-keystone.c +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * USB 3.0 DRD Controller - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "xhci.h" - -struct kdwc3_irq_regs { - u32 revision; /* 0x000 */ - u32 rsvd0[3]; - u32 sysconfig; /* 0x010 */ - u32 rsvd1[1]; - u32 irq_eoi; - u32 rsvd2[1]; - struct { - u32 raw_status; - u32 status; - u32 enable_set; - u32 enable_clr; - } irqs[16]; -}; - -struct keystone_xhci { - struct xhci_hccr *hcd; - struct dwc3 *dwc3_reg; - struct xhci_hcor *hcor; - struct kdwc3_irq_regs *usbss; - struct keystone_xhci_phy *phy; -}; - -struct keystone_xhci keystone; - -static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy) -{ - u32 val; - - /* - * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. - * It should always be cleared because our USB PHY has an onchip VBUS - * analog comparator. - */ - val = readl(&phy->phy_clock); - /* quit selecting the vbusvldextsel by default! */ - val &= ~USB3_PHY_OTG_VBUSVLDECTSEL; - writel(val, &phy->phy_clock); -} - -static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy) -{ - u32 val; - - /* Disable the PHY REFCLK clock gate */ - val = readl(&phy->phy_clock); - val &= ~USB3_PHY_REF_SSP_EN; - writel(val, &phy->phy_clock); -} - -static int keystone_xhci_core_init(struct dwc3 *dwc3_reg) -{ - int ret; - - ret = dwc3_core_init(dwc3_reg); - if (ret) { - debug("failed to initialize core\n"); - return -EINVAL; - } - - /* We are hard-coding DWC3 core to Host Mode */ - dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST); - - return 0; -} - -int xhci_hcd_init(int index, - struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) -{ - u32 val; - int ret; - struct xhci_hccr *hcd; - struct xhci_hcor *hcor; - struct kdwc3_irq_regs *usbss; - struct keystone_xhci_phy *phy; - - usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE; - phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE; - - /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */ - val = readl(&(phy->phy_clock)); - val |= USB3_PHY_REF_SSP_EN; - writel(val, &phy->phy_clock); - - mdelay(100); - - /* Release USB from reset */ - ret = psc_enable_module(KS2_LPSC_USB); - if (ret) { - puts("Cannot enable USB module"); - return -1; - } - - mdelay(100); - - /* Initialize usb phy */ - keystone_xhci_phy_set(phy); - - /* soft reset usbss */ - writel(1, &usbss->sysconfig); - while (readl(&usbss->sysconfig) & 1) - ; - - val = readl(&usbss->revision); - debug("usbss revision %x\n", val); - - /* Initialize usb core */ - hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE; - keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE + - DWC3_REG_OFFSET); - - keystone_xhci_core_init(keystone.dwc3_reg); - - /* set register addresses */ - hcor = (struct xhci_hcor *)((uint32_t)hcd + - HC_LENGTH(readl(&hcd->cr_capbase))); - - debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n", - (u32)hcd, (u32)hcor, - (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase))); - - keystone.usbss = usbss; - keystone.phy = phy; - keystone.hcd = hcd; - keystone.hcor = hcor; - - *ret_hccr = hcd; - *ret_hcor = hcor; - - return 0; -} - -static int keystone_xhci_phy_suspend(void) -{ - int loop_cnt = 0; - struct xhci_hcor *hcor; - uint32_t *portsc_1 = NULL; - uint32_t *portsc_2 = NULL; - u32 val, usb2_pls, usb3_pls, event_q; - struct dwc3 *dwc3_reg = keystone.dwc3_reg; - - /* set register addresses */ - hcor = keystone.hcor; - - /* Bypass Scrambling and Set Shorter Training sequence for simulation */ - val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2); - writel(val, &dwc3_reg->g_ctl); - - /* GUSB2PHYCFG */ - val = readl(&dwc3_reg->g_usb2phycfg[0]); - - /* assert bit 6 (SusPhy) */ - val |= DWC3_GUSB2PHYCFG_SUSPHY; - writel(val, &dwc3_reg->g_usb2phycfg[0]); - - /* GUSB3PIPECTL */ - val = readl(&dwc3_reg->g_usb3pipectl[0]); - - /* - * assert bit 29 to allow PHY to go to suspend when idle - * and cause the USB3 SS PHY to enter suspend mode - */ - val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY); - writel(val, &dwc3_reg->g_usb3pipectl[0]); - - /* - * Steps necessary to allow controller to suspend even when - * VBUS is HIGH: - * - Init DCFG[2:0] (DevSpd) to: 1=FS - * - Init GEVNTADR0 to point to an eventQ - * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ - * - Init DCTL::Run_nStop = 1 - */ - writel(0x00020001, &dwc3_reg->d_cfg); - /* TODO: local2global( (Uint32) eventQ )? */ - writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo); - writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi); - writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz); - /* Run */ - writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl); - - mdelay(100); - - /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */ - portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc); - portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc); - usb2_pls = 0; - usb3_pls = 0; - do { - ++loop_cnt; - usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5; - usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5; - } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000); - - if (usb2_pls != 0x4 || usb3_pls != 0x4) { - debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n", - usb2_pls, usb3_pls); - return -1; - } - - debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt); - return 0; -} - -void xhci_hcd_stop(int index) -{ - /* Disable USB */ - if (keystone_xhci_phy_suspend()) - return; - - if (psc_disable_module(KS2_LPSC_USB)) { - debug("PSC disable module USB failed!\n"); - return; - } - - /* Disable PHY */ - keystone_xhci_phy_unset(keystone.phy); - -/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */ - debug("xhci_hcd_stop OK.\n"); -} diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index da5dbd94ed..04ab540695 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -723,7 +723,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id = udev->slot_id; int speed = udev->speed; int route = 0; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct usb_device *dev = udev; struct usb_hub_device *hub; #endif @@ -739,7 +739,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, /* Only the control endpoint is valid - one endpoint context */ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /* Calculate the route string for this device */ port_num = dev->portnr; while (!usb_hub_is_root_hub(dev->dev)) { @@ -782,7 +782,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, BUG(); } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /* Set up TT fields to support FS/LS devices */ if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { struct udevice *parent = udev->dev; diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 9ded14cc3c..44c5f2d264 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -108,13 +108,13 @@ static struct descriptor { }, }; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; #endif struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) { -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; /* Find the USB controller */ @@ -741,7 +741,7 @@ static int _xhci_alloc_device(struct usb_device *udev) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int usb_alloc_device(struct usb_device *udev) { return _xhci_alloc_device(udev); @@ -1256,7 +1256,7 @@ static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) { @@ -1340,9 +1340,9 @@ int usb_lowlevel_stop(int index) return 0; } -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index a7555b2fa8..6017504488 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1211,7 +1211,7 @@ void xhci_hcd_stop(int index); #define XHCI_STS_CNR (1 << 11) struct xhci_ctrl { -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; #endif struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index 251b4e9969..bda099c63f 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -406,7 +406,7 @@ static int am35x_musb_init(struct musb *musb) musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); /* Start the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 1); msleep(5); @@ -437,7 +437,7 @@ static int am35x_musb_exit(struct musb *musb) #endif /* Shutdown the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 0); #ifndef __UBOOT__ @@ -628,7 +628,7 @@ static int am35x_suspend(struct device *dev) struct omap_musb_board_data *data = plat->board_data; /* Shutdown the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 0); clk_disable(glue->phy_clk); @@ -645,7 +645,7 @@ static int am35x_resume(struct device *dev) int ret; /* Start the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 1); ret = clk_enable(glue->phy_clk); diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index 9b814f4cd4..0c794b310a 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -450,7 +450,7 @@ static int dsps_musb_init(struct musb *musb) dsps_writel(reg_base, wrp->control, (1 << wrp->reset)); /* Start the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 1); musb->isr = dsps_interrupt; @@ -491,7 +491,7 @@ static int dsps_musb_exit(struct musb *musb) #endif /* Shutdown the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 0); #ifndef __UBOOT__ @@ -691,7 +691,7 @@ static int dsps_suspend(struct device *dev) struct omap_musb_board_data *data = plat->board_data; /* Shutdown the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 0); return 0; @@ -703,7 +703,7 @@ static int dsps_resume(struct device *dev) struct omap_musb_board_data *data = plat->board_data; /* Start the on-chip PHY and its PLL. */ - if (data->set_phy_power) + if (data && data->set_phy_power) data->set_phy_power(data->dev, 1); return 0; diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 8b6cec192f..b35d33ffed 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -1775,6 +1775,14 @@ static int musb_gadget_start(struct usb_gadget *g, struct usb_gadget_driver *driver); static int musb_gadget_stop(struct usb_gadget *g, struct usb_gadget_driver *driver); +#else +static int musb_gadget_stop(struct usb_gadget *g) +{ + struct musb *musb = gadget_to_musb(g); + + musb_stop(musb); + return 0; +} #endif static const struct usb_gadget_ops musb_gadget_operations = { @@ -1787,6 +1795,9 @@ static const struct usb_gadget_ops musb_gadget_operations = { #ifndef __UBOOT__ .udc_start = musb_gadget_start, .udc_stop = musb_gadget_stop, +#else + .udc_start = musb_gadget_start, + .udc_stop = musb_gadget_stop, #endif }; diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 2bf918eab4..9c8cc6e584 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -19,7 +19,7 @@ struct int_queue { struct urb urb; }; -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) struct musb_host_data musb_host; #endif @@ -243,7 +243,7 @@ int musb_lowlevel_init(struct musb_host_data *host) return 0; } -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) int usb_lowlevel_stop(int index) { if (!musb_host.host) { @@ -300,9 +300,9 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) { return musb_lowlevel_init(&musb_host); } -#endif /* !CONFIG_DM_USB */ +#endif /* !CONFIG_IS_ENABLED(DM_USB) */ -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static int musb_submit_control_msg(struct udevice *dev, struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) @@ -364,10 +364,10 @@ struct dm_usb_ops musb_usb_ops = { .destroy_int_queue = musb_destroy_int_queue, .reset_root_port = musb_reset_root_port, }; -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ #endif /* CONFIG_USB_MUSB_HOST */ -#ifdef CONFIG_USB_MUSB_GADGET +#if defined(CONFIG_USB_MUSB_GADGET) && !CONFIG_IS_ENABLED(DM_USB_GADGET) static struct musb *gadget; int usb_gadget_handle_interrupts(int index) @@ -425,12 +425,12 @@ struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata, struct musb **musbp; switch (plat->mode) { -#if defined(CONFIG_USB_MUSB_HOST) && !defined(CONFIG_DM_USB) +#if defined(CONFIG_USB_MUSB_HOST) && !CONFIG_IS_ENABLED(DM_USB) case MUSB_HOST: musbp = &musb_host.host; break; #endif -#ifdef CONFIG_USB_MUSB_GADGET +#if defined(CONFIG_USB_MUSB_GADGET) && !CONFIG_IS_ENABLED(DM_USB_GADGET) case MUSB_PERIPHERAL: musbp = &gadget; break; diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 342d76bd6f..32743aa72c 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -135,7 +135,7 @@ const struct musb_platform_ops omap2430_ops = { .disable = omap2430_musb_disable, }; -#if defined(CONFIG_DM_USB) +#if CONFIG_IS_ENABLED(DM_USB) struct omap2430_musb_platdata { void *base; @@ -263,7 +263,7 @@ U_BOOT_DRIVER(omap2430_musb) = { #ifdef CONFIG_USB_MUSB_HOST .id = UCLASS_USB, #else - .id = UCLASS_USB_DEV_GENERIC, + .id = UCLASS_USB_GADGET_GENERIC, #endif .of_match = omap2430_musb_ids, .ofdata_to_platdata = omap2430_musb_ofdata_to_platdata, @@ -276,4 +276,4 @@ U_BOOT_DRIVER(omap2430_musb) = { .priv_auto_alloc_size = sizeof(struct musb_host_data), }; -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 6cf9826cda..f542a181fa 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -435,11 +435,14 @@ static int musb_usb_probe(struct udevice *dev) { struct sunxi_glue *glue = dev_get_priv(dev); struct musb_host_data *host = &glue->mdata; - struct usb_bus_priv *priv = dev_get_uclass_priv(dev); struct musb_hdrc_platform_data pdata; void *base = dev_read_addr_ptr(dev); int ret; +#ifdef CONFIG_USB_MUSB_HOST + struct usb_bus_priv *priv = dev_get_uclass_priv(dev); +#endif + if (!base) return -EINVAL; @@ -459,7 +462,6 @@ static int musb_usb_probe(struct udevice *dev) return ret; } - priv->desc_before_addr = true; memset(&pdata, 0, sizeof(pdata)); pdata.power = 250; @@ -467,6 +469,8 @@ static int musb_usb_probe(struct udevice *dev) pdata.config = glue->cfg->config; #ifdef CONFIG_USB_MUSB_HOST + priv->desc_before_addr = true; + pdata.mode = MUSB_HOST; host->host = musb_init_controller(&pdata, &glue->dev, base); if (!host->host) @@ -535,7 +539,7 @@ U_BOOT_DRIVER(usb_musb) = { #ifdef CONFIG_USB_MUSB_HOST .id = UCLASS_USB, #else - .id = UCLASS_USB_DEV_GENERIC, + .id = UCLASS_USB_GADGET_GENERIC, #endif .of_match = sunxi_musb_ids, .probe = musb_usb_probe, diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index 9fbe2d6861..20ca2731b4 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -19,23 +19,34 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_DM_USB - +#if CONFIG_IS_ENABLED(DM_USB) /* USB 2.0 PHY Control */ #define CM_PHY_PWRDN (1 << 0) #define CM_PHY_OTG_PWRDN (1 << 1) #define OTGVDET_EN (1 << 19) #define OTGSESSENDEN (1 << 20) +#define AM335X_USB0_CTRL 0x0 #define AM335X_USB1_CTRL 0x8 -struct ti_musb_platdata { - void *base; - void *ctrl_mod_base; - struct musb_hdrc_platform_data plat; - struct musb_hdrc_config musb_config; - struct omap_musb_board_data otg_board_data; -}; +static void ti_musb_set_phy_power(struct udevice *dev, u8 on) +{ + struct ti_musb_platdata *platdata = dev_get_platdata(dev); + + if (!platdata->ctrl_mod_base) + return; + + if (on) { + clrsetbits_le32(platdata->ctrl_mod_base, + CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, + OTGVDET_EN | OTGSESSENDEN); + } else { + clrsetbits_le32(platdata->ctrl_mod_base, 0, + CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); + } +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) static int ti_musb_get_usb_index(int node) { @@ -64,20 +75,6 @@ static int ti_musb_get_usb_index(int node) return -ENOENT; } -static void ti_musb_set_phy_power(struct udevice *dev, u8 on) -{ - struct ti_musb_platdata *platdata = dev_get_platdata(dev); - - if (on) { - clrsetbits_le32(platdata->ctrl_mod_base, - CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, - OTGVDET_EN | OTGSESSENDEN); - } else { - clrsetbits_le32(platdata->ctrl_mod_base, 0, - CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); - } -} - static int ti_musb_ofdata_to_platdata(struct udevice *dev) { struct ti_musb_platdata *platdata = dev_get_platdata(dev); @@ -86,6 +83,7 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev) int phys; int ctrl_mod; int usb_index; + struct musb_hdrc_config *musb_config; platdata->base = (void *)devfdt_get_addr_index(dev, 1); @@ -96,38 +94,41 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev) switch (usb_index) { case 1: platdata->ctrl_mod_base += AM335X_USB1_CTRL; + break; case 0: + platdata->ctrl_mod_base += AM335X_USB0_CTRL; + break; default: break; } - platdata->musb_config.multipoint = fdtdec_get_int(fdt, node, - "mentor,multipoint", - -1); - if (platdata->musb_config.multipoint < 0) { + musb_config = malloc(sizeof(struct musb_hdrc_config)); + memset(musb_config, 0, sizeof(struct musb_hdrc_config)); + + musb_config->multipoint = fdtdec_get_int(fdt, node, + "mentor,multipoint", -1); + if (musb_config->multipoint < 0) { pr_err("MUSB multipoint DT entry missing\n"); return -ENOENT; } - platdata->musb_config.dyn_fifo = 1; + musb_config->dyn_fifo = 1; - platdata->musb_config.num_eps = fdtdec_get_int(fdt, node, - "mentor,num-eps", -1); - if (platdata->musb_config.num_eps < 0) { + musb_config->num_eps = fdtdec_get_int(fdt, node, "mentor,num-eps", + -1); + if (musb_config->num_eps < 0) { pr_err("MUSB num-eps DT entry missing\n"); return -ENOENT; } - platdata->musb_config.ram_bits = fdtdec_get_int(fdt, node, - "mentor,ram-bits", -1); - if (platdata->musb_config.ram_bits < 0) { + musb_config->ram_bits = fdtdec_get_int(fdt, node, "mentor,ram-bits", + -1); + if (musb_config->ram_bits < 0) { pr_err("MUSB ram-bits DT entry missing\n"); return -ENOENT; } - platdata->otg_board_data.set_phy_power = ti_musb_set_phy_power; - platdata->otg_board_data.dev = dev; - platdata->plat.config = &platdata->musb_config; + platdata->plat.config = musb_config; platdata->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1); if (platdata->plat.power < 0) { @@ -136,29 +137,27 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev) } platdata->plat.platform_ops = &musb_dsps_ops; - platdata->plat.board_data = &platdata->otg_board_data; return 0; } +#endif static int ti_musb_host_probe(struct udevice *dev) { struct musb_host_data *host = dev_get_priv(dev); struct ti_musb_platdata *platdata = dev_get_platdata(dev); struct usb_bus_priv *priv = dev_get_uclass_priv(dev); - struct omap_musb_board_data *otg_board_data; int ret; priv->desc_before_addr = true; - otg_board_data = &platdata->otg_board_data; - host->host = musb_init_controller(&platdata->plat, - (struct device *)otg_board_data, + NULL, platdata->base); if (!host->host) return -EIO; + ti_musb_set_phy_power(dev, 1); ret = musb_lowlevel_init(host); return ret; @@ -169,10 +168,12 @@ static int ti_musb_host_remove(struct udevice *dev) struct musb_host_data *host = dev_get_priv(dev); musb_stop(host->host); + ti_musb_set_phy_power(dev, 0); return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int ti_musb_host_ofdata_to_platdata(struct udevice *dev) { struct ti_musb_platdata *platdata = dev_get_platdata(dev); @@ -190,11 +191,14 @@ static int ti_musb_host_ofdata_to_platdata(struct udevice *dev) return 0; } +#endif U_BOOT_DRIVER(ti_musb_host) = { .name = "ti-musb-host", .id = UCLASS_USB, +#if CONFIG_IS_ENABLED(OF_CONTROL) .ofdata_to_platdata = ti_musb_host_ofdata_to_platdata, +#endif .probe = ti_musb_host_probe, .remove = ti_musb_host_remove, .ops = &musb_usb_ops, @@ -202,6 +206,82 @@ U_BOOT_DRIVER(ti_musb_host) = { .priv_auto_alloc_size = sizeof(struct musb_host_data), }; +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +struct ti_musb_peripheral { + struct musb *periph; +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int ti_musb_peripheral_ofdata_to_platdata(struct udevice *dev) +{ + struct ti_musb_platdata *platdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + int ret; + + ret = ti_musb_ofdata_to_platdata(dev); + if (ret) { + pr_err("platdata dt parse error\n"); + return ret; + } + platdata->plat.mode = MUSB_PERIPHERAL; + + return 0; +} +#endif + +int dm_usb_gadget_handle_interrupts(struct udevice *dev) +{ + struct ti_musb_peripheral *priv = dev_get_priv(dev); + + priv->periph->isr(0, priv->periph); + + return 0; +} + +static int ti_musb_peripheral_probe(struct udevice *dev) +{ + struct ti_musb_peripheral *priv = dev_get_priv(dev); + struct ti_musb_platdata *platdata = dev_get_platdata(dev); + int ret; + + priv->periph = musb_init_controller(&platdata->plat, + NULL, + platdata->base); + if (!priv->periph) + return -EIO; + + ti_musb_set_phy_power(dev, 1); + musb_gadget_setup(priv->periph); + return usb_add_gadget_udc((struct device *)dev, &priv->periph->g); +} + +static int ti_musb_peripheral_remove(struct udevice *dev) +{ + struct ti_musb_peripheral *priv = dev_get_priv(dev); + + usb_del_gadget_udc(&priv->periph->g); + ti_musb_set_phy_power(dev, 0); + + return 0; +} + +U_BOOT_DRIVER(ti_musb_peripheral) = { + .name = "ti-musb-peripheral", + .id = UCLASS_USB_GADGET_GENERIC, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .ofdata_to_platdata = ti_musb_peripheral_ofdata_to_platdata, +#endif + .probe = ti_musb_peripheral_probe, + .remove = ti_musb_peripheral_remove, + .ops = &musb_usb_ops, + .platdata_auto_alloc_size = sizeof(struct ti_musb_platdata), + .priv_auto_alloc_size = sizeof(struct ti_musb_peripheral), + .flags = DM_FLAG_PRE_RELOC, +}; +#endif + +#if CONFIG_IS_ENABLED(OF_CONTROL) static int ti_musb_wrapper_bind(struct udevice *parent) { const void *fdt = gd->fdt_blob; @@ -222,15 +302,23 @@ static int ti_musb_wrapper_bind(struct udevice *parent) switch (dr_mode) { case USB_DR_MODE_PERIPHERAL: /* Bind MUSB device */ + ret = device_bind_driver_to_node(parent, + "ti-musb-peripheral", + name, + offset_to_ofnode(node), + &dev); + if (ret) + pr_err("musb - not able to bind usb peripheral node\n"); break; case USB_DR_MODE_HOST: /* Bind MUSB host */ - ret = device_bind_driver_to_node(parent, "ti-musb-host", - name, offset_to_ofnode(node), &dev); - if (ret) { + ret = device_bind_driver_to_node(parent, + "ti-musb-host", + name, + offset_to_ofnode(node), + &dev); + if (ret) pr_err("musb - not able to bind usb host node\n"); - return ret; - } break; default: break; @@ -250,5 +338,6 @@ U_BOOT_DRIVER(ti_musb_wrapper) = { .of_match = ti_musb_ids, .bind = ti_musb_wrapper_bind, }; +#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ -#endif /* CONFIG_DM_USB */ +#endif /* CONFIG_IS_ENABLED(DM_USB) */ diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h index 760bd787bc..f2c18ad3a2 100644 --- a/drivers/usb/musb-new/usb-compat.h +++ b/drivers/usb/musb-new/usb-compat.h @@ -67,7 +67,7 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, return 0; } -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) { struct udevice *parent = udev->dev->parent; diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig index dd42f69a6b..2508b6ed0d 100644 --- a/drivers/usb/musb/Kconfig +++ b/drivers/usb/musb/Kconfig @@ -11,17 +11,10 @@ config USB_MUSB_HCD config USB_MUSB_UDC bool "Legacy USB Device Controller" -config USB_DAVINCI - bool "Legacy MUSB DaVinci" - config USB_OMAP3 bool "Legacy MUSB OMAP3 / OMAP4" depends on ARCH_OMAP2PLUS -config USB_DA8XX - bool "Legacy MUSB DA8xx/OMAP-L1x" - depends on ARCH_DAVINCI - config USB_AM35X bool"Legacy MUSB AM35x" depends on ARCH_OMAP2PLUS && !USB_OMAP3 diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index bdb3cd87f6..744f2cfaa2 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -5,7 +5,5 @@ obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o -obj-$(CONFIG_USB_DAVINCI) += davinci.o obj-$(CONFIG_USB_OMAP3) += omap3.o -obj-$(CONFIG_USB_DA8XX) += da8xx.o obj-$(CONFIG_USB_AM35X) += am35x.o diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c deleted file mode 100644 index a652a7c3c1..0000000000 --- a/drivers/usb/musb/da8xx.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * da8xx.c - TI's DA8xx platform specific usb wrapper functions. - * - * Author: Ajay Kumar Gupta - * - * Based on drivers/usb/musb/davinci.c - * - * Copyright (C) 2009 Texas Instruments Incorporated - */ -#include - -#include "musb_core.h" -#include - -/* MUSB platform configuration */ -struct musb_config musb_cfg = { - .regs = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, - .timeout = DA8XX_USB_OTG_TIMEOUT, - .musb_speed = 0, -}; - -/* - * This function enables VBUS by driving the GPIO Bank4 Pin 15 high. - */ -static void enable_vbus(void) -{ - u32 value; - - /* configure GPIO bank4 pin 15 in output direction */ - value = readl(&davinci_gpio_bank45->dir); - writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir); - - /* set GPIO bank4 pin 15 high to drive VBUS */ - value = readl(&davinci_gpio_bank45->set_data); - writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data); -} - -/* - * Enable the usb0 phy. This initialization procedure is explained in - * the DA8xx USB user guide document. - */ -static u8 phy_on(void) -{ - u32 timeout; - u32 cfgchip2; - - cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); - - cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | - CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ); - cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | - CFGCHIP2_REFFREQ_24MHZ; - - writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); - - /* wait until the usb phy pll locks */ - timeout = musb_cfg.timeout; - while (timeout--) - if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) - return 1; - - /* USB phy was not turned on */ - return 0; -} - -/* - * Disable the usb phy - */ -static void phy_off(void) -{ - u32 cfgchip2; - - /* - * Power down the on-chip PHY. - */ - cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); - cfgchip2 &= ~CFGCHIP2_PHY_PLLON; - cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; - writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); -} - -/* - * This function performs DA8xx platform specific initialization for usb0. - */ -int musb_platform_init(void) -{ - u32 revision; - - /* enable psc for usb2.0 */ - lpsc_on(33); - - /* enable usb vbus */ - enable_vbus(); - - /* reset the controller */ - writel(0x1, &da8xx_usb_regs->control); - udelay(5000); - - /* start the on-chip usb phy and its pll */ - if (phy_on() == 0) - return -1; - - /* Returns zero if e.g. not clocked */ - revision = readl(&da8xx_usb_regs->revision); - if (revision == 0) - return -1; - - /* Disable all interrupts */ - writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | - DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set); - return 0; -} - -/* - * This function performs DA8xx platform specific deinitialization for usb0. - */ -void musb_platform_deinit(void) -{ - /* Turn of the phy */ - phy_off(); - - /* flush any interrupts */ - writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | - DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr); - writel(0, &da8xx_usb_regs->eoi); -} diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c deleted file mode 100644 index 46cdb5ad1f..0000000000 --- a/drivers/usb/musb/davinci.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI's Davinci platform specific USB wrapper functions. - * - * Copyright (c) 2008 Texas Instruments - * - * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments - */ - -#include -#include -#include "davinci.h" -#include - -#if !defined(CONFIG_DV_USBPHY_CTL) -#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN) -#endif - -/* MUSB platform configuration */ -struct musb_config musb_cfg = { - .regs = (struct musb_regs *)MENTOR_USB0_BASE, - .timeout = DAVINCI_USB_TIMEOUT, - .musb_speed = 0, -}; - -/* MUSB module register overlay */ -struct davinci_usb_regs *dregs; - -/* - * Enable the USB phy - */ -static u8 phy_on(void) -{ - u32 timeout; -#ifdef DAVINCI_DM365EVM - u32 val; -#endif - /* Wait until the USB phy is turned on */ -#ifdef DAVINCI_DM365EVM - writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN | - USBPHY_VBDTCTEN, USBPHY_CTL_PADDR); -#else - writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR); -#endif - timeout = musb_cfg.timeout; - -#ifdef DAVINCI_DM365EVM - /* Set the ownership of GIO33 to USB */ - val = readl(PINMUX4); - val &= ~(PINMUX4_USBDRVBUS_BITCLEAR); - val |= PINMUX4_USBDRVBUS_BITSET; - writel(val, PINMUX4); -#endif - while (timeout--) - if (readl(USBPHY_CTL_PADDR) & USBPHY_PHYCLKGD) - return 1; - - /* USB phy was not turned on */ - return 0; -} - -/* - * Disable the USB phy - */ -static void phy_off(void) -{ - /* powerdown the on-chip PHY and its oscillator */ - writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR); -} - -void __enable_vbus(void) -{ - /* - * nothing to do, vbus is handled through the cpu. - * Define this function in board code, if it is - * different on your board. - */ -} -void enable_vbus(void) - __attribute__((weak, alias("__enable_vbus"))); - -/* - * This function performs Davinci platform specific initialization for usb0. - */ -int musb_platform_init(void) -{ - u32 revision; - - /* enable USB VBUS */ - enable_vbus(); - - /* start the on-chip USB phy and its pll */ - if (!phy_on()) - return -1; - - /* reset the controller */ - dregs = (struct davinci_usb_regs *)DAVINCI_USB0_BASE; - writel(1, &dregs->ctrlr); - udelay(5000); - - /* Returns zero if e.g. not clocked */ - revision = readl(&dregs->version); - if (!revision) - return -1; - - /* Disable all interrupts */ - writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_RXINT_MASK | - DAVINCI_USB_TXINT_MASK , &dregs->intmsksetr); - return 0; -} - -/* - * This function performs Davinci platform specific deinitialization for usb0. - */ -void musb_platform_deinit(void) -{ - /* Turn of the phy */ - phy_off(); - - /* flush any interrupts */ - writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_TXINT_MASK | - DAVINCI_USB_RXINT_MASK , &dregs->intclrr); -} diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h deleted file mode 100644 index 29bb08c307..0000000000 --- a/drivers/usb/musb/davinci.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * TI's Davinci platform specific USB wrapper functions. - * - * Copyright (c) 2008 Texas Instruments - * - * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments - */ - -#ifndef __DAVINCI_USB_H__ -#define __DAVINCI_USB_H__ - -#include -#include "musb_core.h" - -/* Base address of DAVINCI usb0 wrapper */ -#define DAVINCI_USB0_BASE 0x01C64000 - -/* Base address of DAVINCI musb core */ -#define MENTOR_USB0_BASE (DAVINCI_USB0_BASE+0x400) - -/* - * Davinci platform USB wrapper register overlay. Note: Only the required - * registers are included in this structure. It can be expanded as required. - */ -struct davinci_usb_regs { - u32 version; - u32 ctrlr; - u32 reserved[0x20]; - u32 intclrr; - u32 intmskr; - u32 intmsksetr; -}; - -#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ -#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ -#define DAVINCI_USB_USBINT_SHIFT 16 -#define DAVINCI_USB_TXINT_SHIFT 0 -#define DAVINCI_USB_RXINT_SHIFT 8 -#define DAVINCI_INTR_DRVVBUS 0x0100 - -#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ -#define DAVINCI_USB_TXINT_MASK \ - (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT) -#define DAVINCI_USB_RXINT_MASK \ - (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT) -#define MGC_BUSCTL_OFFSET(_bEnd, _bOffset) \ - (0x80 + (8*(_bEnd)) + (_bOffset)) - -/* Integrated highspeed/otg PHY */ -#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34) -#define USBPHY_PHY24MHZ (1 << 13) -#define USBPHY_PHYCLKGD (1 << 8) -#define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */ -#define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */ -#define USBPHY_PHYPLLON (1 << 4) /* override pll suspend */ -#define USBPHY_CLKO1SEL (1 << 3) -#define USBPHY_OSCPDWN (1 << 2) -#define USBPHY_PHYPDWN (1 << 0) - -/* Timeout for Davinci USB module */ -#define DAVINCI_USB_TIMEOUT 0x3FFFFFF - -/* IO Expander I2C address and VBUS enable mask */ -#define IOEXP_I2C_ADDR 0x3A -#define IOEXP_VBUSEN_MASK 1 - -/* extern functions */ -extern void lpsc_on(unsigned int id); -extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); -extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); -extern void enable_vbus(void); -#endif /* __DAVINCI_USB_H__ */ diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index f1d6d85862..7620114bec 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -46,8 +46,6 @@ #include "omap3.h" #elif defined(CONFIG_USB_AM35X) #include "am35x.h" -#elif defined(CONFIG_USB_DAVINCI) -#include "davinci.h" #endif /* Define MUSB_DEBUG for debugging */ diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index cd4959cc71..5fecb4cfd5 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -106,13 +106,19 @@ static int video_bridge_pre_probe(struct udevice *dev) int video_bridge_set_active(struct udevice *dev, bool active) { struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); - int ret; + int ret = 0; debug("%s: %d\n", __func__, active); - ret = dm_gpio_set_value(&uc_priv->sleep, !active); - if (ret) - return ret; - if (active) { + if (uc_priv->sleep.dev) { + ret = dm_gpio_set_value(&uc_priv->sleep, !active); + if (ret) + return ret; + } + + if (!active) + return 0; + + if (uc_priv->reset.dev) { ret = dm_gpio_set_value(&uc_priv->reset, true); if (ret) return ret; diff --git a/drivers/video/fonts/Kconfig b/drivers/video/fonts/Kconfig index 3f1398db50..c692fa9602 100644 --- a/drivers/video/fonts/Kconfig +++ b/drivers/video/fonts/Kconfig @@ -7,6 +7,7 @@ menu "TrueType Fonts" config CONSOLE_TRUETYPE_NIMBUS bool "Nimbus Sans Regular" depends on CONSOLE_TRUETYPE + default y help Nimbus Sans L is a version of Nimbus Sans using Adobe font sources. It was designed in 1987. A subset of Nimbus Sans L were released diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c index c13a907709..bd733f5f1c 100644 --- a/drivers/video/pwm_backlight.c +++ b/drivers/video/pwm_backlight.c @@ -78,7 +78,7 @@ static int enable_sequence(struct udevice *dev, int seq) ret = regulator_set_enable(priv->reg, true); if (ret) { log_debug("Cannot enable regulator for PWM '%s'\n", - __func__, dev->name); + dev->name); return log_ret(ret); } mdelay(120); diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 4fe8f47441..4f1a0f3a5f 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -106,7 +106,7 @@ int rk_mipi_dsi_enable(struct udevice *dev, rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0; - rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val); + rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val); val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0; rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); @@ -241,7 +241,7 @@ int rk_mipi_phy_enable(struct udevice *dev) /* select the suitable value for fsfreqrang reg */ for (i = 0; i < ARRAY_SIZE(freq_rang); i++) { - if (ddr_clk / (MHz) >= freq_rang[i][0]) + if (ddr_clk / (MHz) <= freq_rang[i][0]) break; } if (i == ARRAY_SIZE(freq_rang)) { diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 3b8da808bd..1679d20002 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -68,5 +68,4 @@ U_BOOT_DRIVER(simple_video) = { .id = UCLASS_VIDEO, .of_match = simple_video_ids, .probe = simple_video_probe, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 63c47bf1bc..4cf3a0eb75 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, int *clk_div, int *clk_double, bool is_composite) { - int value, n, m, min_m, max_m, diff; + int value, n, m, min_m, max_m, diff, step; int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; int best_double = 0; bool use_mipi_pll = false; +#ifdef CONFIG_SUNXI_DE2 + step = 6000; +#else + step = 3000; +#endif + if (tcon == 0) { #if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2) min_m = 6; @@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, */ for (m = min_m; m <= max_m; m++) { #ifndef CONFIG_SUNXI_DE2 - n = (m * dotclock) / 3000; + n = (m * dotclock) / step; if ((n >= 9) && (n <= 127)) { - value = (3000 * n) / m; + value = (step * n) / m; diff = dotclock - value; if (diff < best_diff) { best_diff = diff; @@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, #endif /* No double clock on DE2 */ - n = (m * dotclock) / 6000; + n = (m * dotclock) / (step * 2); if ((n >= 9) && (n <= 127)) { - value = (6000 * n) / m; + value = (step * 2 * n) / m; diff = dotclock - value; if (diff < best_diff) { best_diff = diff; @@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, } else #endif { - clock_set_pll3(best_n * 3000000); - debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n", + clock_set_pll3(best_n * step * 1000); + debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n", dotclock, (best_double + 1) * clock_get_pll3() / best_m / 1000, - best_double + 1, best_n, best_m); + best_double + 1, step, best_n, best_m); } if (tcon == 0) { diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 1874887f2f..2ca19d4049 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -272,6 +272,14 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) s++; /* ; */ s = parsenum(s, &col); + /* + * Video origin is [0, 0], terminal origin is [1, 1]. + */ + if (row) + --row; + if (col) + --col; + set_cursor_position(priv, row, col); break; @@ -344,7 +352,7 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) switch (val) { case 0: /* all attributes off */ - video_set_default_colors(vid_priv); + video_set_default_colors(dev->parent, false); break; case 1: /* bold */ diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 44dfa71b6f..f307cf243b 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -115,18 +115,29 @@ int video_clear(struct udevice *dev) return 0; } -void video_set_default_colors(struct video_priv *priv) +void video_set_default_colors(struct udevice *dev, bool invert) { + struct video_priv *priv = dev_get_uclass_priv(dev); + int fore, back; + #ifdef CONFIG_SYS_WHITE_ON_BLACK /* White is used when switching to bold, use light gray here */ - priv->fg_col_idx = VID_LIGHT_GRAY; - priv->colour_fg = vid_console_color(priv, VID_LIGHT_GRAY); - priv->colour_bg = vid_console_color(priv, VID_BLACK); + fore = VID_LIGHT_GRAY; + back = VID_BLACK; #else - priv->fg_col_idx = VID_BLACK; - priv->colour_fg = vid_console_color(priv, VID_BLACK); - priv->colour_bg = vid_console_color(priv, VID_WHITE); + fore = VID_BLACK; + back = VID_WHITE; #endif + if (invert) { + int temp; + + temp = fore; + fore = back; + back = temp; + } + priv->fg_col_idx = fore; + priv->colour_fg = vid_console_color(priv, fore); + priv->colour_bg = vid_console_color(priv, back); } /* Flush video activity to the caches */ @@ -215,11 +226,13 @@ static int video_post_probe(struct udevice *dev) /* Set up the line and display size */ priv->fb = map_sysmem(plat->base, plat->size); - priv->line_length = priv->xsize * VNBYTES(priv->bpix); + if (!priv->line_length) + priv->line_length = priv->xsize * VNBYTES(priv->bpix); + priv->fb_size = priv->line_length * priv->ysize; /* Set up colors */ - video_set_default_colors(priv); + video_set_default_colors(dev, false); if (!CONFIG_IS_ENABLED(NO_FB_CLEAR)) video_clear(dev); diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 1377e19081..2898b0b55d 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -140,8 +141,6 @@ __weak void fb_put_word(uchar **fb, uchar **from) } #endif /* CONFIG_BMP_16BPP */ -#define BMP_ALIGN_CENTER 0x7fff - /** * video_splash_align_axis() - Align a single coordinate * diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig new file mode 100644 index 0000000000..a9d5fd07b7 --- /dev/null +++ b/drivers/virtio/Kconfig @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Tuomas Tynkkynen +# Copyright (C) 2018, Bin Meng +# +# VirtIO is a virtualization standard for network and disk device drivers +# where just the guest's device driver "knows" it is running in a virtual +# environment, and cooperates with the hypervisor. This enables guests to +# get high performance network and disk operations, and gives most of the +# performance benefits of paravirtualization. In the U-Boot case, the guest +# is U-Boot itself, while the virtual environment are normally QEMU targets +# like ARM, RISC-V and x86. +# +# See http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf for +# the VirtIO specification v1.0. + +menu "VirtIO Drivers" + +config VIRTIO + bool + help + This option is selected by any driver which implements the virtio + transport, such as CONFIG_VIRTIO_MMIO or CONFIG_VIRTIO_PCI. + +config VIRTIO_MMIO + bool "Platform bus driver for memory mapped virtio devices" + select VIRTIO + help + This driver provides support for memory mapped virtio + platform device driver. + +config VIRTIO_PCI + bool "PCI driver for virtio devices" + depends on DM_PCI + select VIRTIO + help + This driver provides support for virtio based paravirtual device + drivers over PCI. + +config VIRTIO_SANDBOX + bool "Sandbox driver for virtio devices" + depends on SANDBOX + select VIRTIO + help + This driver provides support for Sandbox implementation of virtio + transport driver which is used for testing purpose only. + +config VIRTIO_NET + bool "virtio net driver" + depends on VIRTIO + help + This is the virtual net driver for virtio. It can be used with + QEMU based targets. + +config VIRTIO_BLK + bool "virtio block driver" + depends on VIRTIO + help + This is the virtual block driver for virtio. It can be used with + QEMU based targets. + +endmenu diff --git a/drivers/virtio/Makefile b/drivers/virtio/Makefile new file mode 100644 index 0000000000..4579044ae3 --- /dev/null +++ b/drivers/virtio/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Tuomas Tynkkynen +# Copyright (C) 2018, Bin Meng + +obj-y += virtio-uclass.o virtio_ring.o +obj-$(CONFIG_VIRTIO_MMIO) += virtio_mmio.o +obj-$(CONFIG_VIRTIO_PCI) += virtio_pci_legacy.o virtio_pci_modern.o +obj-$(CONFIG_VIRTIO_SANDBOX) += virtio_sandbox.o +obj-$(CONFIG_VIRTIO_NET) += virtio_net.o +obj-$(CONFIG_VIRTIO_BLK) += virtio_blk.o diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c new file mode 100644 index 0000000000..34397d7dbb --- /dev/null +++ b/drivers/virtio/virtio-uclass.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * VirtIO is a virtualization standard for network and disk device drivers + * where just the guest's device driver "knows" it is running in a virtual + * environment, and cooperates with the hypervisor. This enables guests to + * get high performance network and disk operations, and gives most of the + * performance benefits of paravirtualization. In the U-Boot case, the guest + * is U-Boot itself, while the virtual environment are normally QEMU targets + * like ARM, RISC-V and x86. + * + * See http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf for + * the VirtIO specification v1.0. + */ + +#include +#include +#include +#include +#include + +static const char *const virtio_drv_name[VIRTIO_ID_MAX_NUM] = { + [VIRTIO_ID_NET] = VIRTIO_NET_DRV_NAME, + [VIRTIO_ID_BLOCK] = VIRTIO_BLK_DRV_NAME, +}; + +int virtio_get_config(struct udevice *vdev, unsigned int offset, + void *buf, unsigned int len) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->get_config(vdev->parent, offset, buf, len); +} + +int virtio_set_config(struct udevice *vdev, unsigned int offset, + void *buf, unsigned int len) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->set_config(vdev->parent, offset, buf, len); +} + +int virtio_generation(struct udevice *vdev, u32 *counter) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + if (!ops->generation) + return -ENOSYS; + + return ops->generation(vdev->parent, counter); +} + +int virtio_get_status(struct udevice *vdev, u8 *status) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->get_status(vdev->parent, status); +} + +int virtio_set_status(struct udevice *vdev, u8 status) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->set_status(vdev->parent, status); +} + +int virtio_reset(struct udevice *vdev) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->reset(vdev->parent); +} + +int virtio_get_features(struct udevice *vdev, u64 *features) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->get_features(vdev->parent, features); +} + +int virtio_set_features(struct udevice *vdev) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->set_features(vdev->parent); +} + +int virtio_find_vqs(struct udevice *vdev, unsigned int nvqs, + struct virtqueue *vqs[]) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->find_vqs(vdev->parent, nvqs, vqs); +} + +int virtio_del_vqs(struct udevice *vdev) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->del_vqs(vdev->parent); +} + +int virtio_notify(struct udevice *vdev, struct virtqueue *vq) +{ + struct dm_virtio_ops *ops; + + ops = virtio_get_ops(vdev->parent); + + return ops->notify(vdev->parent, vq); +} + +void virtio_add_status(struct udevice *vdev, u8 status) +{ + u8 old; + + if (!virtio_get_status(vdev, &old)) + virtio_set_status(vdev, old | status); +} + +int virtio_finalize_features(struct udevice *vdev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(vdev->parent); + u8 status; + int ret; + + ret = virtio_set_features(vdev); + if (ret) + return ret; + + if (uc_priv->legacy) + return 0; + + virtio_add_status(vdev, VIRTIO_CONFIG_S_FEATURES_OK); + ret = virtio_get_status(vdev, &status); + if (ret) + return ret; + if (!(status & VIRTIO_CONFIG_S_FEATURES_OK)) { + debug("(%s): device refuses features %x\n", vdev->name, status); + return -ENODEV; + } + + return 0; +} + +void virtio_driver_features_init(struct virtio_dev_priv *priv, + const u32 *feature, + u32 feature_size, + const u32 *feature_legacy, + u32 feature_legacy_size) +{ + priv->feature_table = feature; + priv->feature_table_size = feature_size; + priv->feature_table_legacy = feature_legacy; + priv->feature_table_size_legacy = feature_legacy_size; +} + +int virtio_init(void) +{ + struct udevice *bus; + int ret; + + /* Enumerate all known virtio devices */ + ret = uclass_first_device(UCLASS_VIRTIO, &bus); + if (ret) + return ret; + + while (bus) { + ret = uclass_next_device(&bus); + if (ret) + break; + } + + return ret; +} + +static int virtio_uclass_pre_probe(struct udevice *udev) +{ + struct dm_virtio_ops *ops; + + ops = (struct dm_virtio_ops *)(udev->driver->ops); + + /* + * Check virtio transport driver ops here so that we don't need + * check these ops each time when the virtio_xxx APIs are called. + * + * Only generation op is optional. All other ops are must-have. + */ + if (!ops->get_config || !ops->set_config || + !ops->get_status || !ops->set_status || + !ops->get_features || !ops->set_features || + !ops->find_vqs || !ops->del_vqs || + !ops->reset || !ops->notify) + return -ENOENT; + + return 0; +} + +static int virtio_uclass_post_probe(struct udevice *udev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + char dev_name[30], *str; + struct udevice *vdev; + int ret; + + if (uc_priv->device > VIRTIO_ID_MAX_NUM) { + debug("(%s): virtio device ID %d exceeds maximum num\n", + udev->name, uc_priv->device); + return 0; + } + + if (!virtio_drv_name[uc_priv->device]) { + debug("(%s): underlying virtio device driver unavailable\n", + udev->name); + return 0; + } + + snprintf(dev_name, sizeof(dev_name), "%s#%d", + virtio_drv_name[uc_priv->device], udev->seq); + str = strdup(dev_name); + if (!str) + return -ENOMEM; + + ret = device_bind_driver(udev, virtio_drv_name[uc_priv->device], + str, &vdev); + if (ret == -ENOENT) { + debug("(%s): no driver configured\n", udev->name); + return 0; + } + if (ret) { + free(str); + return ret; + } + device_set_name_alloced(vdev); + + INIT_LIST_HEAD(&uc_priv->vqs); + + return 0; +} + +static int virtio_uclass_child_post_bind(struct udevice *vdev) +{ + /* Acknowledge that we've seen the device */ + virtio_add_status(vdev, VIRTIO_CONFIG_S_ACKNOWLEDGE); + + return 0; +} + +static int virtio_uclass_child_pre_probe(struct udevice *vdev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(vdev->parent); + u64 device_features; + u64 driver_features; + u64 driver_features_legacy; + int i; + int ret; + + /* + * Save the real virtio device (eg: virtio-net, virtio-blk) to + * the transport (parent) device's uclass priv for future use. + */ + uc_priv->vdev = vdev; + + /* + * We always start by resetting the device, in case a previous driver + * messed it up. This also tests that code path a little. + */ + ret = virtio_reset(vdev); + if (ret) + goto err; + + /* We have a driver! */ + virtio_add_status(vdev, VIRTIO_CONFIG_S_DRIVER); + + /* Figure out what features the device supports */ + virtio_get_features(vdev, &device_features); + debug("(%s) plain device features supported %016llx\n", + vdev->name, device_features); + if (!(device_features & (1ULL << VIRTIO_F_VERSION_1))) + uc_priv->legacy = true; + + /* Figure out what features the driver supports */ + driver_features = 0; + for (i = 0; i < uc_priv->feature_table_size; i++) { + unsigned int f = uc_priv->feature_table[i]; + + WARN_ON(f >= 64); + driver_features |= (1ULL << f); + } + + /* Some drivers have a separate feature table for virtio v1.0 */ + if (uc_priv->feature_table_legacy) { + driver_features_legacy = 0; + for (i = 0; i < uc_priv->feature_table_size_legacy; i++) { + unsigned int f = uc_priv->feature_table_legacy[i]; + + WARN_ON(f >= 64); + driver_features_legacy |= (1ULL << f); + } + } else { + driver_features_legacy = driver_features; + } + + if (uc_priv->legacy) { + debug("(%s): legacy virtio device\n", vdev->name); + uc_priv->features = driver_features_legacy & device_features; + } else { + debug("(%s): v1.0 complaint virtio device\n", vdev->name); + uc_priv->features = driver_features & device_features; + } + + /* Transport features always preserved to pass to finalize_features */ + for (i = VIRTIO_TRANSPORT_F_START; i < VIRTIO_TRANSPORT_F_END; i++) + if ((device_features & (1ULL << i)) && + (i == VIRTIO_F_VERSION_1)) + __virtio_set_bit(vdev->parent, i); + + debug("(%s) final negotiated features supported %016llx\n", + vdev->name, uc_priv->features); + ret = virtio_finalize_features(vdev); + if (ret) + goto err; + + return 0; + +err: + virtio_add_status(vdev, VIRTIO_CONFIG_S_FAILED); + return ret; +} + +static int virtio_uclass_child_post_probe(struct udevice *vdev) +{ + /* Indicates that the driver is set up and ready to drive the device */ + virtio_add_status(vdev, VIRTIO_CONFIG_S_DRIVER_OK); + + return 0; +} + +UCLASS_DRIVER(virtio) = { + .name = "virtio", + .id = UCLASS_VIRTIO, + .flags = DM_UC_FLAG_SEQ_ALIAS, + .pre_probe = virtio_uclass_pre_probe, + .post_probe = virtio_uclass_post_probe, + .child_post_bind = virtio_uclass_child_post_bind, + .child_pre_probe = virtio_uclass_child_pre_probe, + .child_post_probe = virtio_uclass_child_post_probe, + .per_device_auto_alloc_size = sizeof(struct virtio_dev_priv), +}; diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c new file mode 100644 index 0000000000..e793e34e83 --- /dev/null +++ b/drivers/virtio/virtio_blk.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include "virtio_blk.h" + +struct virtio_blk_priv { + struct virtqueue *vq; +}; + +static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, + lbaint_t blkcnt, void *buffer, u32 type) +{ + struct virtio_blk_priv *priv = dev_get_priv(dev); + unsigned int num_out = 0, num_in = 0; + struct virtio_sg *sgs[3]; + u8 status; + int ret; + + struct virtio_blk_outhdr out_hdr = { + .type = cpu_to_virtio32(dev, type), + .sector = cpu_to_virtio64(dev, sector), + }; + struct virtio_sg hdr_sg = { &out_hdr, sizeof(out_hdr) }; + struct virtio_sg data_sg = { buffer, blkcnt * 512 }; + struct virtio_sg status_sg = { &status, sizeof(status) }; + + sgs[num_out++] = &hdr_sg; + + if (type & VIRTIO_BLK_T_OUT) + sgs[num_out++] = &data_sg; + else + sgs[num_out + num_in++] = &data_sg; + + sgs[num_out + num_in++] = &status_sg; + + ret = virtqueue_add(priv->vq, sgs, num_out, num_in); + if (ret) + return ret; + + virtqueue_kick(priv->vq); + + while (!virtqueue_get_buf(priv->vq, NULL)) + ; + + return status == VIRTIO_BLK_S_OK ? blkcnt : -EIO; +} + +static ulong virtio_blk_read(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt, void *buffer) +{ + return virtio_blk_do_req(dev, start, blkcnt, buffer, + VIRTIO_BLK_T_IN); +} + +static ulong virtio_blk_write(struct udevice *dev, lbaint_t start, + lbaint_t blkcnt, const void *buffer) +{ + return virtio_blk_do_req(dev, start, blkcnt, (void *)buffer, + VIRTIO_BLK_T_OUT); +} + +static int virtio_blk_bind(struct udevice *dev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); + struct blk_desc *desc = dev_get_uclass_platdata(dev); + int devnum; + + desc->if_type = IF_TYPE_VIRTIO; + /* + * Initialize the devnum to -ENODEV. This is to make sure that + * blk_next_free_devnum() works as expected, since the default + * value 0 is a valid devnum. + */ + desc->devnum = -ENODEV; + devnum = blk_next_free_devnum(IF_TYPE_VIRTIO); + if (devnum < 0) + return devnum; + desc->devnum = devnum; + desc->part_type = PART_TYPE_UNKNOWN; + /* + * virtio mmio transport supplies string identification for us, + * while pci trnasport uses a 2-byte subvendor value. + */ + if (uc_priv->vendor >> 16) + sprintf(desc->vendor, "%s", (char *)&uc_priv->vendor); + else + sprintf(desc->vendor, "%04x", uc_priv->vendor); + desc->bdev = dev; + + /* Indicate what driver features we support */ + virtio_driver_features_init(uc_priv, NULL, 0, NULL, 0); + + return 0; +} + +static int virtio_blk_probe(struct udevice *dev) +{ + struct virtio_blk_priv *priv = dev_get_priv(dev); + struct blk_desc *desc = dev_get_uclass_platdata(dev); + u64 cap; + int ret; + + ret = virtio_find_vqs(dev, 1, &priv->vq); + if (ret) + return ret; + + desc->blksz = 512; + virtio_cread(dev, struct virtio_blk_config, capacity, &cap); + desc->lba = cap; + + return 0; +} + +static const struct blk_ops virtio_blk_ops = { + .read = virtio_blk_read, + .write = virtio_blk_write, +}; + +U_BOOT_DRIVER(virtio_blk) = { + .name = VIRTIO_BLK_DRV_NAME, + .id = UCLASS_BLK, + .ops = &virtio_blk_ops, + .bind = virtio_blk_bind, + .probe = virtio_blk_probe, + .remove = virtio_reset, + .priv_auto_alloc_size = sizeof(struct virtio_blk_priv), + .flags = DM_FLAG_ACTIVE_DMA, +}; diff --git a/drivers/virtio/virtio_blk.h b/drivers/virtio/virtio_blk.h new file mode 100644 index 0000000000..8d8e02fa2e --- /dev/null +++ b/drivers/virtio/virtio_blk.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_blk.h + */ + +#ifndef _LINUX_VIRTIO_BLK_H +#define _LINUX_VIRTIO_BLK_H + +/* Feature bits */ +#define VIRTIO_BLK_F_SIZE_MAX 1 /* Indicates maximum segment size */ +#define VIRTIO_BLK_F_SEG_MAX 2 /* Indicates maximum # of segments */ +#define VIRTIO_BLK_F_GEOMETRY 4 /* Legacy geometry available */ +#define VIRTIO_BLK_F_RO 5 /* Disk is read-only */ +#define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available */ +#define VIRTIO_BLK_F_TOPOLOGY 10 /* Topology information is available */ +#define VIRTIO_BLK_F_MQ 12 /* Support more than one vq */ + +/* Legacy feature bits */ +#ifndef VIRTIO_BLK_NO_LEGACY +#define VIRTIO_BLK_F_BARRIER 0 /* Does host support barriers? */ +#define VIRTIO_BLK_F_SCSI 7 /* Supports scsi command passthru */ +#define VIRTIO_BLK_F_FLUSH 9 /* Flush command supported */ +#define VIRTIO_BLK_F_CONFIG_WCE 11 /* Writeback mode available in config */ +#ifndef __KERNEL__ +/* Old (deprecated) name for VIRTIO_BLK_F_FLUSH */ +#define VIRTIO_BLK_F_WCE VIRTIO_BLK_F_FLUSH +#endif +#endif /* !VIRTIO_BLK_NO_LEGACY */ + +#define VIRTIO_BLK_ID_BYTES 20 /* ID string length */ + +struct __packed virtio_blk_config { + /* The capacity (in 512-byte sectors) */ + __u64 capacity; + /* The maximum segment size (if VIRTIO_BLK_F_SIZE_MAX) */ + __u32 size_max; + /* The maximum number of segments (if VIRTIO_BLK_F_SEG_MAX) */ + __u32 seg_max; + /* geometry of the device (if VIRTIO_BLK_F_GEOMETRY) */ + struct virtio_blk_geometry { + __u16 cylinders; + __u8 heads; + __u8 sectors; + } geometry; + + /* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */ + __u32 blk_size; + + /* the next 4 entries are guarded by VIRTIO_BLK_F_TOPOLOGY */ + /* exponent for physical block per logical block */ + __u8 physical_block_exp; + /* alignment offset in logical blocks */ + __u8 alignment_offset; + /* minimum I/O size without performance penalty in logical blocks */ + __u16 min_io_size; + /* optimal sustained I/O size in logical blocks */ + __u32 opt_io_size; + + /* writeback mode (if VIRTIO_BLK_F_CONFIG_WCE) */ + __u8 wce; + __u8 unused; + + /* number of vqs, only available when VIRTIO_BLK_F_MQ is set */ + __u16 num_queues; +}; + +/* + * Command types + * + * Usage is a bit tricky as some bits are used as flags and some are not. + * + * Rules: + * VIRTIO_BLK_T_OUT may be combined with VIRTIO_BLK_T_SCSI_CMD or + * VIRTIO_BLK_T_BARRIER. VIRTIO_BLK_T_FLUSH is a command of its own + * and may not be combined with any of the other flags. + */ + +/* These two define direction */ +#define VIRTIO_BLK_T_IN 0 +#define VIRTIO_BLK_T_OUT 1 + +#ifndef VIRTIO_BLK_NO_LEGACY +/* This bit says it's a scsi command, not an actual read or write */ +#define VIRTIO_BLK_T_SCSI_CMD 2 +#endif /* VIRTIO_BLK_NO_LEGACY */ + +/* Cache flush command */ +#define VIRTIO_BLK_T_FLUSH 4 + +/* Get device ID command */ +#define VIRTIO_BLK_T_GET_ID 8 + +#ifndef VIRTIO_BLK_NO_LEGACY +/* Barrier before this op */ +#define VIRTIO_BLK_T_BARRIER 0x80000000 +#endif /* !VIRTIO_BLK_NO_LEGACY */ + +/* + * This comes first in the read scatter-gather list. + * For legacy virtio, if VIRTIO_F_ANY_LAYOUT is not negotiated, + * this is the first element of the read scatter-gather list. + */ +struct virtio_blk_outhdr { + /* VIRTIO_BLK_T* */ + __virtio32 type; + /* io priority */ + __virtio32 ioprio; + /* Sector (ie. 512 byte offset) */ + __virtio64 sector; +}; + +#ifndef VIRTIO_BLK_NO_LEGACY +struct virtio_scsi_inhdr { + __virtio32 errors; + __virtio32 data_len; + __virtio32 sense_len; + __virtio32 residual; +}; +#endif /* !VIRTIO_BLK_NO_LEGACY */ + +/* And this is the final byte of the write scatter-gather list */ +#define VIRTIO_BLK_S_OK 0 +#define VIRTIO_BLK_S_IOERR 1 +#define VIRTIO_BLK_S_UNSUPP 2 + +#endif /* _LINUX_VIRTIO_BLK_H */ diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c new file mode 100644 index 0000000000..7b738703b8 --- /dev/null +++ b/drivers/virtio/virtio_mmio.c @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * VirtIO memory-maped I/O transport driver + * Ported from Linux drivers/virtio/virtio_mmio.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include "virtio_mmio.h" + +static int virtio_mmio_get_config(struct udevice *udev, unsigned int offset, + void *buf, unsigned int len) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; + u8 b; + __le16 w; + __le32 l; + + if (priv->version == 1) { + u8 *ptr = buf; + int i; + + for (i = 0; i < len; i++) + ptr[i] = readb(base + offset + i); + + return 0; + } + + switch (len) { + case 1: + b = readb(base + offset); + memcpy(buf, &b, sizeof(b)); + break; + case 2: + w = cpu_to_le16(readw(base + offset)); + memcpy(buf, &w, sizeof(w)); + break; + case 4: + l = cpu_to_le32(readl(base + offset)); + memcpy(buf, &l, sizeof(l)); + break; + case 8: + l = cpu_to_le32(readl(base + offset)); + memcpy(buf, &l, sizeof(l)); + l = cpu_to_le32(readl(base + offset + sizeof(l))); + memcpy(buf + sizeof(l), &l, sizeof(l)); + break; + default: + WARN_ON(true); + } + + return 0; +} + +static int virtio_mmio_set_config(struct udevice *udev, unsigned int offset, + const void *buf, unsigned int len) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; + u8 b; + __le16 w; + __le32 l; + + if (priv->version == 1) { + const u8 *ptr = buf; + int i; + + for (i = 0; i < len; i++) + writeb(ptr[i], base + offset + i); + + return 0; + } + + switch (len) { + case 1: + memcpy(&b, buf, sizeof(b)); + writeb(b, base + offset); + break; + case 2: + memcpy(&w, buf, sizeof(w)); + writew(le16_to_cpu(w), base + offset); + break; + case 4: + memcpy(&l, buf, sizeof(l)); + writel(le32_to_cpu(l), base + offset); + break; + case 8: + memcpy(&l, buf, sizeof(l)); + writel(le32_to_cpu(l), base + offset); + memcpy(&l, buf + sizeof(l), sizeof(l)); + writel(le32_to_cpu(l), base + offset + sizeof(l)); + break; + default: + WARN_ON(true); + } + + return 0; +} + +static int virtio_mmio_generation(struct udevice *udev, u32 *counter) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + if (priv->version == 1) + *counter = 0; + else + *counter = readl(priv->base + VIRTIO_MMIO_CONFIG_GENERATION); + + return 0; +} + +static int virtio_mmio_get_status(struct udevice *udev, u8 *status) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + *status = readl(priv->base + VIRTIO_MMIO_STATUS) & 0xff; + + return 0; +} + +static int virtio_mmio_set_status(struct udevice *udev, u8 status) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + /* We should never be setting status to 0 */ + WARN_ON(status == 0); + + writel(status, priv->base + VIRTIO_MMIO_STATUS); + + return 0; +} + +static int virtio_mmio_reset(struct udevice *udev) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + /* 0 status means a reset */ + writel(0, priv->base + VIRTIO_MMIO_STATUS); + + return 0; +} + +static int virtio_mmio_get_features(struct udevice *udev, u64 *features) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + writel(1, priv->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); + *features = readl(priv->base + VIRTIO_MMIO_DEVICE_FEATURES); + *features <<= 32; + + writel(0, priv->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); + *features |= readl(priv->base + VIRTIO_MMIO_DEVICE_FEATURES); + + return 0; +} + +static int virtio_mmio_set_features(struct udevice *udev) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* Make sure there is are no mixed devices */ + if (priv->version == 2 && uc_priv->legacy) { + debug("New virtio-mmio devices (version 2) must provide VIRTIO_F_VERSION_1 feature!\n"); + return -EINVAL; + } + + writel(1, priv->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); + writel((u32)(uc_priv->features >> 32), + priv->base + VIRTIO_MMIO_DRIVER_FEATURES); + + writel(0, priv->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); + writel((u32)uc_priv->features, + priv->base + VIRTIO_MMIO_DRIVER_FEATURES); + + return 0; +} + +static struct virtqueue *virtio_mmio_setup_vq(struct udevice *udev, + unsigned int index) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtqueue *vq; + unsigned int num; + int err; + + /* Select the queue we're interested in */ + writel(index, priv->base + VIRTIO_MMIO_QUEUE_SEL); + + /* Queue shouldn't already be set up */ + if (readl(priv->base + (priv->version == 1 ? + VIRTIO_MMIO_QUEUE_PFN : VIRTIO_MMIO_QUEUE_READY))) { + err = -ENOENT; + goto error_available; + } + + num = readl(priv->base + VIRTIO_MMIO_QUEUE_NUM_MAX); + if (num == 0) { + err = -ENOENT; + goto error_new_virtqueue; + } + + /* Create the vring */ + vq = vring_create_virtqueue(index, num, VIRTIO_MMIO_VRING_ALIGN, udev); + if (!vq) { + err = -ENOMEM; + goto error_new_virtqueue; + } + + /* Activate the queue */ + writel(virtqueue_get_vring_size(vq), + priv->base + VIRTIO_MMIO_QUEUE_NUM); + if (priv->version == 1) { + u64 q_pfn = virtqueue_get_desc_addr(vq) >> PAGE_SHIFT; + + /* + * virtio-mmio v1 uses a 32bit QUEUE PFN. If we have something + * that doesn't fit in 32bit, fail the setup rather than + * pretending to be successful. + */ + if (q_pfn >> 32) { + debug("platform bug: legacy virtio-mmio must not be used with RAM above 0x%llxGB\n", + 0x1ULL << (32 + PAGE_SHIFT - 30)); + err = -E2BIG; + goto error_bad_pfn; + } + + writel(PAGE_SIZE, priv->base + VIRTIO_MMIO_QUEUE_ALIGN); + writel(q_pfn, priv->base + VIRTIO_MMIO_QUEUE_PFN); + } else { + u64 addr; + + addr = virtqueue_get_desc_addr(vq); + writel((u32)addr, priv->base + VIRTIO_MMIO_QUEUE_DESC_LOW); + writel((u32)(addr >> 32), + priv->base + VIRTIO_MMIO_QUEUE_DESC_HIGH); + + addr = virtqueue_get_avail_addr(vq); + writel((u32)addr, priv->base + VIRTIO_MMIO_QUEUE_AVAIL_LOW); + writel((u32)(addr >> 32), + priv->base + VIRTIO_MMIO_QUEUE_AVAIL_HIGH); + + addr = virtqueue_get_used_addr(vq); + writel((u32)addr, priv->base + VIRTIO_MMIO_QUEUE_USED_LOW); + writel((u32)(addr >> 32), + priv->base + VIRTIO_MMIO_QUEUE_USED_HIGH); + + writel(1, priv->base + VIRTIO_MMIO_QUEUE_READY); + } + + return vq; + +error_bad_pfn: + vring_del_virtqueue(vq); + +error_new_virtqueue: + if (priv->version == 1) { + writel(0, priv->base + VIRTIO_MMIO_QUEUE_PFN); + } else { + writel(0, priv->base + VIRTIO_MMIO_QUEUE_READY); + WARN_ON(readl(priv->base + VIRTIO_MMIO_QUEUE_READY)); + } + +error_available: + return ERR_PTR(err); +} + +static void virtio_mmio_del_vq(struct virtqueue *vq) +{ + struct virtio_mmio_priv *priv = dev_get_priv(vq->vdev); + unsigned int index = vq->index; + + /* Select and deactivate the queue */ + writel(index, priv->base + VIRTIO_MMIO_QUEUE_SEL); + if (priv->version == 1) { + writel(0, priv->base + VIRTIO_MMIO_QUEUE_PFN); + } else { + writel(0, priv->base + VIRTIO_MMIO_QUEUE_READY); + WARN_ON(readl(priv->base + VIRTIO_MMIO_QUEUE_READY)); + } + + vring_del_virtqueue(vq); +} + +static int virtio_mmio_del_vqs(struct udevice *udev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtqueue *vq, *n; + + list_for_each_entry_safe(vq, n, &uc_priv->vqs, list) + virtio_mmio_del_vq(vq); + + return 0; +} + +static int virtio_mmio_find_vqs(struct udevice *udev, unsigned int nvqs, + struct virtqueue *vqs[]) +{ + int i; + + for (i = 0; i < nvqs; ++i) { + vqs[i] = virtio_mmio_setup_vq(udev, i); + if (IS_ERR(vqs[i])) { + virtio_mmio_del_vqs(udev); + return PTR_ERR(vqs[i]); + } + } + + return 0; +} + +static int virtio_mmio_notify(struct udevice *udev, struct virtqueue *vq) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + /* + * We write the queue's selector into the notification register + * to signal the other end + */ + writel(vq->index, priv->base + VIRTIO_MMIO_QUEUE_NOTIFY); + + return 0; +} + +static int virtio_mmio_ofdata_to_platdata(struct udevice *udev) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + + priv->base = (void __iomem *)(ulong)dev_read_addr(udev); + if (priv->base == (void __iomem *)FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static int virtio_mmio_probe(struct udevice *udev) +{ + struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + u32 magic; + + /* Check magic value */ + magic = readl(priv->base + VIRTIO_MMIO_MAGIC_VALUE); + if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { + debug("(%s): wrong magic value 0x%08x!\n", udev->name, magic); + return 0; + } + + /* Check device version */ + priv->version = readl(priv->base + VIRTIO_MMIO_VERSION); + if (priv->version < 1 || priv->version > 2) { + debug("(%s): version %d not supported!\n", + udev->name, priv->version); + return 0; + } + + /* Check devicd ID */ + uc_priv->device = readl(priv->base + VIRTIO_MMIO_DEVICE_ID); + if (uc_priv->device == 0) { + /* + * virtio-mmio device with an ID 0 is a (dummy) placeholder + * with no function. End probing now with no error reported. + */ + return 0; + } + uc_priv->vendor = readl(priv->base + VIRTIO_MMIO_VENDOR_ID); + + if (priv->version == 1) + writel(PAGE_SIZE, priv->base + VIRTIO_MMIO_GUEST_PAGE_SIZE); + + debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name, + uc_priv->device, uc_priv->vendor, priv->version); + + return 0; +} + +static const struct dm_virtio_ops virtio_mmio_ops = { + .get_config = virtio_mmio_get_config, + .set_config = virtio_mmio_set_config, + .generation = virtio_mmio_generation, + .get_status = virtio_mmio_get_status, + .set_status = virtio_mmio_set_status, + .reset = virtio_mmio_reset, + .get_features = virtio_mmio_get_features, + .set_features = virtio_mmio_set_features, + .find_vqs = virtio_mmio_find_vqs, + .del_vqs = virtio_mmio_del_vqs, + .notify = virtio_mmio_notify, +}; + +static const struct udevice_id virtio_mmio_ids[] = { + { .compatible = "virtio,mmio" }, + { } +}; + +U_BOOT_DRIVER(virtio_mmio) = { + .name = "virtio-mmio", + .id = UCLASS_VIRTIO, + .of_match = virtio_mmio_ids, + .ops = &virtio_mmio_ops, + .probe = virtio_mmio_probe, + .ofdata_to_platdata = virtio_mmio_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct virtio_mmio_priv), +}; diff --git a/drivers/virtio/virtio_mmio.h b/drivers/virtio/virtio_mmio.h new file mode 100644 index 0000000000..b3408828a5 --- /dev/null +++ b/drivers/virtio/virtio_mmio.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_mmio.h + */ + +#ifndef _LINUX_VIRTIO_MMIO_H +#define _LINUX_VIRTIO_MMIO_H + +/* Control registers */ + +/* Magic value ("virt" string) - Read Only */ +#define VIRTIO_MMIO_MAGIC_VALUE 0x000 + +/* Virtio device version - Read Only */ +#define VIRTIO_MMIO_VERSION 0x004 + +/* Virtio device ID - Read Only */ +#define VIRTIO_MMIO_DEVICE_ID 0x008 + +/* Virtio vendor ID - Read Only */ +#define VIRTIO_MMIO_VENDOR_ID 0x00c + +/* + * Bitmask of the features supported by the device (host) + * (32 bits per set) - Read Only + */ +#define VIRTIO_MMIO_DEVICE_FEATURES 0x010 + +/* Device (host) features set selector - Write Only */ +#define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014 + +/* + * Bitmask of features activated by the driver (guest) + * (32 bits per set) - Write Only + */ +#define VIRTIO_MMIO_DRIVER_FEATURES 0x020 + +/* Activated features set selector - Write Only */ +#define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024 + +#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */ + +/* Guest's memory page size in bytes - Write Only */ +#define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 + +#endif + +/* Queue selector - Write Only */ +#define VIRTIO_MMIO_QUEUE_SEL 0x030 + +/* Maximum size of the currently selected queue - Read Only */ +#define VIRTIO_MMIO_QUEUE_NUM_MAX 0x034 + +/* Queue size for the currently selected queue - Write Only */ +#define VIRTIO_MMIO_QUEUE_NUM 0x038 + +#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */ + +/* Used Ring alignment for the currently selected queue - Write Only */ +#define VIRTIO_MMIO_QUEUE_ALIGN 0x03c + +/* Guest's PFN for the currently selected queue - Read Write */ +#define VIRTIO_MMIO_QUEUE_PFN 0x040 + +#endif + +/* Ready bit for the currently selected queue - Read Write */ +#define VIRTIO_MMIO_QUEUE_READY 0x044 + +/* Queue notifier - Write Only */ +#define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 + +/* Interrupt status - Read Only */ +#define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 + +/* Interrupt acknowledge - Write Only */ +#define VIRTIO_MMIO_INTERRUPT_ACK 0x064 + +/* Device status register - Read Write */ +#define VIRTIO_MMIO_STATUS 0x070 + +/* Selected queue's Descriptor Table address, 64 bits in two halves */ +#define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 +#define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084 + +/* Selected queue's Available Ring address, 64 bits in two halves */ +#define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090 +#define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094 + +/* Selected queue's Used Ring address, 64 bits in two halves */ +#define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0 +#define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4 + +/* Configuration atomicity value */ +#define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc + +/* + * The config space is defined by each driver as + * the per-driver configuration space - Read Write + */ +#define VIRTIO_MMIO_CONFIG 0x100 + +/* Interrupt flags (re: interrupt status & acknowledge registers) */ + +#define VIRTIO_MMIO_INT_VRING BIT(0) +#define VIRTIO_MMIO_INT_CONFIG BIT(1) + +/* + * The alignment to use between consumer and producer parts of vring. + * Currently hardcoded to the page size. + */ +#define PAGE_SHIFT 12 +#define VIRTIO_MMIO_VRING_ALIGN PAGE_SIZE + +/** + * virtio mmio transport driver private data + * + * @base: mmio transport device register base + * @version: mmio transport device version + */ +struct virtio_mmio_priv { + void __iomem *base; + u32 version; +}; + +#endif /* _LINUX_VIRTIO_MMIO_H */ diff --git a/drivers/virtio/virtio_net.c b/drivers/virtio/virtio_net.c new file mode 100644 index 0000000000..0dbbd78023 --- /dev/null +++ b/drivers/virtio/virtio_net.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include "virtio_net.h" + +/* Amount of buffers to keep in the RX virtqueue */ +#define VIRTIO_NET_NUM_RX_BUFS 32 + +/* + * This value comes from the VirtIO spec: 1500 for maximum packet size, + * 14 for the Ethernet header, 12 for virtio_net_hdr. In total 1526 bytes. + */ +#define VIRTIO_NET_RX_BUF_SIZE 1526 + +struct virtio_net_priv { + union { + struct virtqueue *vqs[2]; + struct { + struct virtqueue *rx_vq; + struct virtqueue *tx_vq; + }; + }; + + char rx_buff[VIRTIO_NET_NUM_RX_BUFS][VIRTIO_NET_RX_BUF_SIZE]; + bool rx_running; + int net_hdr_len; +}; + +/* + * For simplicity, the driver only negotiates the VIRTIO_NET_F_MAC feature. + * For the VIRTIO_NET_F_STATUS feature, we don't negotiate it, hence per spec + * we should assume the link is always active. + */ +static const u32 feature[] = { + VIRTIO_NET_F_MAC +}; + +static const u32 feature_legacy[] = { + VIRTIO_NET_F_MAC +}; + +static int virtio_net_start(struct udevice *dev) +{ + struct virtio_net_priv *priv = dev_get_priv(dev); + struct virtio_sg sg; + struct virtio_sg *sgs[] = { &sg }; + int i; + + if (!priv->rx_running) { + /* receive buffer length is always 1526 */ + sg.length = VIRTIO_NET_RX_BUF_SIZE; + + /* setup the receive buffer address */ + for (i = 0; i < VIRTIO_NET_NUM_RX_BUFS; i++) { + sg.addr = priv->rx_buff[i]; + virtqueue_add(priv->rx_vq, sgs, 0, 1); + } + + virtqueue_kick(priv->rx_vq); + + /* setup the receive queue only once */ + priv->rx_running = true; + } + + return 0; +} + +static int virtio_net_send(struct udevice *dev, void *packet, int length) +{ + struct virtio_net_priv *priv = dev_get_priv(dev); + struct virtio_net_hdr hdr; + struct virtio_net_hdr_v1 hdr_v1; + struct virtio_sg hdr_sg; + struct virtio_sg data_sg = { packet, length }; + struct virtio_sg *sgs[] = { &hdr_sg, &data_sg }; + int ret; + + if (priv->net_hdr_len == sizeof(struct virtio_net_hdr)) + hdr_sg.addr = &hdr; + else + hdr_sg.addr = &hdr_v1; + hdr_sg.length = priv->net_hdr_len; + + memset(hdr_sg.addr, 0, priv->net_hdr_len); + + ret = virtqueue_add(priv->tx_vq, sgs, 2, 0); + if (ret) + return ret; + + virtqueue_kick(priv->tx_vq); + + while (1) { + if (virtqueue_get_buf(priv->tx_vq, NULL)) + break; + } + + return 0; +} + +static int virtio_net_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct virtio_net_priv *priv = dev_get_priv(dev); + unsigned int len; + void *buf; + + buf = virtqueue_get_buf(priv->rx_vq, &len); + if (!buf) + return -EAGAIN; + + *packetp = buf + priv->net_hdr_len; + return len - priv->net_hdr_len; +} + +static int virtio_net_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct virtio_net_priv *priv = dev_get_priv(dev); + void *buf = packet - priv->net_hdr_len; + struct virtio_sg sg = { buf, VIRTIO_NET_RX_BUF_SIZE }; + struct virtio_sg *sgs[] = { &sg }; + + /* Put the buffer back to the rx ring */ + virtqueue_add(priv->rx_vq, sgs, 0, 1); + + return 0; +} + +static void virtio_net_stop(struct udevice *dev) +{ + /* + * There is no way to stop the queue from running, unless we issue + * a reset to the virtio device, and re-do the queue initialization + * from the beginning. + */ +} + +static int virtio_net_write_hwaddr(struct udevice *dev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); + struct eth_pdata *pdata = dev_get_platdata(dev); + int i; + + /* + * v1.0 compliant device's MAC address is set through control channel, + * which we don't support for now. + */ + if (!uc_priv->legacy) + return -ENOSYS; + + for (i = 0; i < sizeof(pdata->enetaddr); i++) { + virtio_cwrite8(dev, + offsetof(struct virtio_net_config, mac) + i, + pdata->enetaddr[i]); + } + + return 0; +} + +static int virtio_net_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + if (!pdata) + return -ENOSYS; + + if (virtio_has_feature(dev, VIRTIO_NET_F_MAC)) { + virtio_cread_bytes(dev, + offsetof(struct virtio_net_config, mac), + pdata->enetaddr, sizeof(pdata->enetaddr)); + } + + return 0; +} + +static int virtio_net_bind(struct udevice *dev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); + + /* Indicate what driver features we support */ + virtio_driver_features_init(uc_priv, feature, ARRAY_SIZE(feature), + feature_legacy, ARRAY_SIZE(feature_legacy)); + + return 0; +} + +static int virtio_net_probe(struct udevice *dev) +{ + struct virtio_net_priv *priv = dev_get_priv(dev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(dev->parent); + int ret; + + ret = virtio_find_vqs(dev, 2, priv->vqs); + if (ret < 0) + return ret; + + /* + * For v1.0 compliant device, it always assumes the member + * 'num_buffers' exists in the struct virtio_net_hdr while + * the legacy driver only presented 'num_buffers' when + * VIRTIO_NET_F_MRG_RXBUF was negotiated. Without that feature + * the structure was 2 bytes shorter. + */ + if (uc_priv->legacy) + priv->net_hdr_len = sizeof(struct virtio_net_hdr); + else + priv->net_hdr_len = sizeof(struct virtio_net_hdr_v1); + + return 0; +} + +static const struct eth_ops virtio_net_ops = { + .start = virtio_net_start, + .send = virtio_net_send, + .recv = virtio_net_recv, + .free_pkt = virtio_net_free_pkt, + .stop = virtio_net_stop, + .write_hwaddr = virtio_net_write_hwaddr, + .read_rom_hwaddr = virtio_net_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(virtio_net) = { + .name = VIRTIO_NET_DRV_NAME, + .id = UCLASS_ETH, + .bind = virtio_net_bind, + .probe = virtio_net_probe, + .remove = virtio_reset, + .ops = &virtio_net_ops, + .priv_auto_alloc_size = sizeof(struct virtio_net_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ACTIVE_DMA, +}; diff --git a/drivers/virtio/virtio_net.h b/drivers/virtio/virtio_net.h new file mode 100644 index 0000000000..c92bae5269 --- /dev/null +++ b/drivers/virtio/virtio_net.h @@ -0,0 +1,268 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_net.h + */ + +#ifndef _LINUX_VIRTIO_NET_H +#define _LINUX_VIRTIO_NET_H + +/* TODO: needs to be removed! */ +#define ETH_ALEN 6 + +/* The feature bitmap for virtio net */ + +/* Host handles pkts w/ partial csum */ +#define VIRTIO_NET_F_CSUM 0 +/* Guest handles pkts w/ partial csum */ +#define VIRTIO_NET_F_GUEST_CSUM 1 +/* Dynamic offload configuration */ +#define VIRTIO_NET_F_CTRL_GUEST_OFFLOADS 2 +/* Initial MTU advice */ +#define VIRTIO_NET_F_MTU 3 +/* Host has given MAC address */ +#define VIRTIO_NET_F_MAC 5 +/* Guest can handle TSOv4 in */ +#define VIRTIO_NET_F_GUEST_TSO4 7 +/* Guest can handle TSOv6 in */ +#define VIRTIO_NET_F_GUEST_TSO6 8 +/* Guest can handle TSO[6] w/ ECN in */ +#define VIRTIO_NET_F_GUEST_ECN 9 +/* Guest can handle UFO in */ +#define VIRTIO_NET_F_GUEST_UFO 10 +/* Host can handle TSOv4 in */ +#define VIRTIO_NET_F_HOST_TSO4 11 +/* Host can handle TSOv6 in */ +#define VIRTIO_NET_F_HOST_TSO6 12 +/* Host can handle TSO[6] w/ ECN in */ +#define VIRTIO_NET_F_HOST_ECN 13 +/* Host can handle UFO in */ +#define VIRTIO_NET_F_HOST_UFO 14 +/* Host can merge receive buffers */ +#define VIRTIO_NET_F_MRG_RXBUF 15 +/* virtio_net_config.status available */ +#define VIRTIO_NET_F_STATUS 16 +/* Control channel available */ +#define VIRTIO_NET_F_CTRL_VQ 17 +/* Control channel RX mode support */ +#define VIRTIO_NET_F_CTRL_RX 18 +/* Control channel VLAN filtering */ +#define VIRTIO_NET_F_CTRL_VLAN 19 +/* Extra RX mode control support */ +#define VIRTIO_NET_F_CTRL_RX_EXTRA 20 +/* Guest can announce device on the network */ +#define VIRTIO_NET_F_GUEST_ANNOUNCE 21 +/* Device supports receive flow steering */ +#define VIRTIO_NET_F_MQ 22 +/* Set MAC address */ +#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 +/* Device set linkspeed and duplex */ +#define VIRTIO_NET_F_SPEED_DUPLEX 63 + +#ifndef VIRTIO_NET_NO_LEGACY +/* Host handles pkts w/ any GSO type */ +#define VIRTIO_NET_F_GSO 6 +#endif /* VIRTIO_NET_NO_LEGACY */ + +#define VIRTIO_NET_S_LINK_UP 1 /* Link is up */ +#define VIRTIO_NET_S_ANNOUNCE 2 /* Announcement is needed */ + +struct __packed virtio_net_config { + /* The config defining mac address (if VIRTIO_NET_F_MAC) */ + __u8 mac[ETH_ALEN]; + /* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */ + __u16 status; + /* + * Maximum number of each of transmit and receive queues; + * see VIRTIO_NET_F_MQ and VIRTIO_NET_CTRL_MQ. + * Legal values are between 1 and 0x8000 + */ + __u16 max_virtqueue_pairs; + /* Default maximum transmit unit advice */ + __u16 mtu; + /* + * speed, in units of 1Mb. All values 0 to INT_MAX are legal. + * Any other value stands for unknown. + */ + __u32 speed; + /* + * 0x00 - half duplex + * 0x01 - full duplex + * Any other value stands for unknown. + */ + __u8 duplex; +}; + +/* + * This header comes first in the scatter-gather list. If you don't + * specify GSO or CSUM features, you can simply ignore the header. + * + * This is bitwise-equivalent to the legacy struct virtio_net_hdr_mrg_rxbuf, + * only flattened. + */ +struct virtio_net_hdr_v1 { +#define VIRTIO_NET_HDR_F_NEEDS_CSUM 0x01 /* Use csum_start, csum_offset */ +#define VIRTIO_NET_HDR_F_DATA_VALID 0x02 /* Csum is valid */ + __u8 flags; +#define VIRTIO_NET_HDR_GSO_NONE 0x00 /* Not a GSO frame */ +#define VIRTIO_NET_HDR_GSO_TCPV4 0x01 /* GSO frame, IPv4 TCP (TSO) */ +#define VIRTIO_NET_HDR_GSO_UDP 0x03 /* GSO frame, IPv4 UDP (UFO) */ +#define VIRTIO_NET_HDR_GSO_TCPV6 0x04 /* GSO frame, IPv6 TCP */ +#define VIRTIO_NET_HDR_GSO_ECN 0x80 /* TCP has ECN set */ + __u8 gso_type; + __virtio16 hdr_len; /* Ethernet + IP + tcp/udp hdrs */ + __virtio16 gso_size; /* Bytes to append to hdr_len per frame */ + __virtio16 csum_start; /* Position to start checksumming from */ + __virtio16 csum_offset; /* Offset after that to place checksum */ + __virtio16 num_buffers; /* Number of merged rx buffers */ +}; + +#ifndef VIRTIO_NET_NO_LEGACY +/* + * This header comes first in the scatter-gather list. + * + * For legacy virtio, if VIRTIO_F_ANY_LAYOUT is not negotiated, it must + * be the first element of the scatter-gather list. If you don't + * specify GSO or CSUM features, you can simply ignore the header. + */ +struct virtio_net_hdr { + /* See VIRTIO_NET_HDR_F_* */ + __u8 flags; + /* See VIRTIO_NET_HDR_GSO_* */ + __u8 gso_type; + __virtio16 hdr_len; /* Ethernet + IP + tcp/udp hdrs */ + __virtio16 gso_size; /* Bytes to append to hdr_len per frame */ + __virtio16 csum_start; /* Position to start checksumming from */ + __virtio16 csum_offset; /* Offset after that to place checksum */ +}; + +/* + * This is the version of the header to use when the MRG_RXBUF + * feature has been negotiated. + */ +struct virtio_net_hdr_mrg_rxbuf { + struct virtio_net_hdr hdr; + __virtio16 num_buffers; /* Number of merged rx buffers */ +}; +#endif /* ...VIRTIO_NET_NO_LEGACY */ + +/* + * Control virtqueue data structures + * + * The control virtqueue expects a header in the first sg entry + * and an ack/status response in the last entry. Data for the + * command goes in between. + */ +struct __packed virtio_net_ctrl_hdr { + __u8 class; + __u8 cmd; +}; + +typedef __u8 virtio_net_ctrl_ack; + +#define VIRTIO_NET_OK 0 +#define VIRTIO_NET_ERR 1 + +/* + * Control the RX mode, ie. promisucous, allmulti, etc... + * + * All commands require an "out" sg entry containing a 1 byte state value, + * zero = disable, non-zero = enable. + * + * Commands 0 and 1 are supported with the VIRTIO_NET_F_CTRL_RX feature. + * Commands 2-5 are added with VIRTIO_NET_F_CTRL_RX_EXTRA. + */ +#define VIRTIO_NET_CTRL_RX 0 +#define VIRTIO_NET_CTRL_RX_PROMISC 0 +#define VIRTIO_NET_CTRL_RX_ALLMULTI 1 +#define VIRTIO_NET_CTRL_RX_ALLUNI 2 +#define VIRTIO_NET_CTRL_RX_NOMULTI 3 +#define VIRTIO_NET_CTRL_RX_NOUNI 4 +#define VIRTIO_NET_CTRL_RX_NOBCAST 5 + +/* + * Control the MAC + * + * The MAC filter table is managed by the hypervisor, the guest should assume + * the size is infinite. Filtering should be considered non-perfect, ie. based + * on hypervisor resources, the guest may received packets from sources not + * specified in the filter list. + * + * In addition to the class/cmd header, the TABLE_SET command requires two + * out scatterlists. Each contains a 4 byte count of entries followed by a + * concatenated byte stream of the ETH_ALEN MAC addresses. The first sg list + * contains unicast addresses, the second is for multicast. This functionality + * is present if the VIRTIO_NET_F_CTRL_RX feature is available. + * + * The ADDR_SET command requests one out scatterlist, it contains a 6 bytes MAC + * address. This functionality is present if the VIRTIO_NET_F_CTRL_MAC_ADDR + * feature is available. + */ +struct __packed virtio_net_ctrl_mac { + __virtio32 entries; + __u8 macs[][ETH_ALEN]; +}; + +#define VIRTIO_NET_CTRL_MAC 1 +#define VIRTIO_NET_CTRL_MAC_TABLE_SET 0 +#define VIRTIO_NET_CTRL_MAC_ADDR_SET 1 + +/* + * Control VLAN filtering + * + * The VLAN filter table is controlled via a simple ADD/DEL interface. VLAN IDs + * not added may be filterd by the hypervisor. Del is the opposite of add. Both + * commands expect an out entry containing a 2 byte VLAN ID. VLAN filterting is + * available with the VIRTIO_NET_F_CTRL_VLAN feature bit. + */ +#define VIRTIO_NET_CTRL_VLAN 2 +#define VIRTIO_NET_CTRL_VLAN_ADD 0 +#define VIRTIO_NET_CTRL_VLAN_DEL 1 + +/* + * Control link announce acknowledgment + * + * The command VIRTIO_NET_CTRL_ANNOUNCE_ACK is used to indicate that driver has + * recevied the notification; device would clear the VIRTIO_NET_S_ANNOUNCE bit + * in the status field after it receives this command. + */ +#define VIRTIO_NET_CTRL_ANNOUNCE 3 +#define VIRTIO_NET_CTRL_ANNOUNCE_ACK 0 + +/* + * Control receive flow steering + * + * The command VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET enables receive flow steering, + * specifying the number of the transmit and receive queues that will be used. + * After the command is consumed and acked by the device, the device will not + * steer new packets on receive virtqueues other than specified nor read from + * transmit virtqueues other than specified. Accordingly, driver should not + * transmit new packets on virtqueues other than specified. + */ +struct virtio_net_ctrl_mq { + __virtio16 virtqueue_pairs; +}; + +#define VIRTIO_NET_CTRL_MQ 4 +#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET 0 +#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MIN 1 +#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MAX 0x8000 + +/* + * Control network offloads + * + * Reconfigures the network offloads that guest can handle. + * + * Available with the VIRTIO_NET_F_CTRL_GUEST_OFFLOADS feature bit. + * + * Command data format matches the feature bit mask exactly. + * + * See VIRTIO_NET_F_GUEST_* for the list of offloads + * that can be enabled/disabled. + */ +#define VIRTIO_NET_CTRL_GUEST_OFFLOADS 5 +#define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET 0 + +#endif /* _LINUX_VIRTIO_NET_H */ diff --git a/drivers/virtio/virtio_pci.h b/drivers/virtio/virtio_pci.h new file mode 100644 index 0000000000..cc753ed7b3 --- /dev/null +++ b/drivers/virtio/virtio_pci.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_pci.h + */ + +#ifndef _LINUX_VIRTIO_PCI_H +#define _LINUX_VIRTIO_PCI_H + +#ifndef VIRTIO_PCI_NO_LEGACY + +/* A 32-bit r/o bitmask of the features supported by the host */ +#define VIRTIO_PCI_HOST_FEATURES 0 + +/* A 32-bit r/w bitmask of features activated by the guest */ +#define VIRTIO_PCI_GUEST_FEATURES 4 + +/* A 32-bit r/w PFN for the currently selected queue */ +#define VIRTIO_PCI_QUEUE_PFN 8 + +/* A 16-bit r/o queue size for the currently selected queue */ +#define VIRTIO_PCI_QUEUE_NUM 12 + +/* A 16-bit r/w queue selector */ +#define VIRTIO_PCI_QUEUE_SEL 14 + +/* A 16-bit r/w queue notifier */ +#define VIRTIO_PCI_QUEUE_NOTIFY 16 + +/* An 8-bit device status register */ +#define VIRTIO_PCI_STATUS 18 + +/* + * An 8-bit r/o interrupt status register. Reading the value will return the + * current contents of the ISR and will also clear it. This is effectively + * a read-and-acknowledge. + */ +#define VIRTIO_PCI_ISR 19 + +/* MSI-X registers: only enabled if MSI-X is enabled */ + +/* A 16-bit vector for configuration changes */ +#define VIRTIO_MSI_CONFIG_VECTOR 20 +/* A 16-bit vector for selected queue notifications */ +#define VIRTIO_MSI_QUEUE_VECTOR 22 + +/* + * The remaining space is defined by each driver as the per-driver + * configuration space + */ +#define VIRTIO_PCI_CONFIG_OFF(msix) ((msix) ? 24 : 20) + +/* Virtio ABI version, this must match exactly */ +#define VIRTIO_PCI_ABI_VERSION 0 + +/* + * How many bits to shift physical queue address written to QUEUE_PFN. + * 12 is historical, and due to x86 page size. + */ +#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 + +/* + * The alignment to use between consumer and producer parts of vring. + * x86 pagesize again. + */ +#define VIRTIO_PCI_VRING_ALIGN 4096 + +#endif /* VIRTIO_PCI_NO_LEGACY */ + +/* The bit of the ISR which indicates a device configuration change */ +#define VIRTIO_PCI_ISR_CONFIG 0x2 +/* Vector value used to disable MSI for queue */ +#define VIRTIO_MSI_NO_VECTOR 0xffff + +#ifndef VIRTIO_PCI_NO_MODERN + +/* IDs for different capabilities. Must all exist. */ + +/* Common configuration */ +#define VIRTIO_PCI_CAP_COMMON_CFG 1 +/* Notifications */ +#define VIRTIO_PCI_CAP_NOTIFY_CFG 2 +/* ISR access */ +#define VIRTIO_PCI_CAP_ISR_CFG 3 +/* Device specific configuration */ +#define VIRTIO_PCI_CAP_DEVICE_CFG 4 +/* PCI configuration access */ +#define VIRTIO_PCI_CAP_PCI_CFG 5 + +/* This is the PCI capability header: */ +struct virtio_pci_cap { + __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ + __u8 cap_next; /* Generic PCI field: next ptr */ + __u8 cap_len; /* Generic PCI field: capability length */ + __u8 cfg_type; /* Identifies the structure */ + __u8 bar; /* Where to find it */ + __u8 padding[3]; /* Pad to full dword */ + __le32 offset; /* Offset within bar */ + __le32 length; /* Length of the structure, in bytes */ +}; + +struct virtio_pci_notify_cap { + struct virtio_pci_cap cap; + __le32 notify_off_multiplier; /* Multiplier for queue_notify_off */ +}; + +/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ +struct virtio_pci_common_cfg { + /* About the whole device */ + __le32 device_feature_select; /* read-write */ + __le32 device_feature; /* read-only */ + __le32 guest_feature_select; /* read-write */ + __le32 guest_feature; /* read-write */ + __le16 msix_config; /* read-write */ + __le16 num_queues; /* read-only */ + __u8 device_status; /* read-write */ + __u8 config_generation; /* read-only */ + + /* About a specific virtqueue */ + __le16 queue_select; /* read-write */ + __le16 queue_size; /* read-write, power of 2 */ + __le16 queue_msix_vector; /* read-write */ + __le16 queue_enable; /* read-write */ + __le16 queue_notify_off; /* read-only */ + __le32 queue_desc_lo; /* read-write */ + __le32 queue_desc_hi; /* read-write */ + __le32 queue_avail_lo; /* read-write */ + __le32 queue_avail_hi; /* read-write */ + __le32 queue_used_lo; /* read-write */ + __le32 queue_used_hi; /* read-write */ +}; + +/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ +struct virtio_pci_cfg_cap { + struct virtio_pci_cap cap; + __u8 pci_cfg_data[4]; /* Data for BAR access */ +}; + +/* Macro versions of offsets for the Old Timers! */ +#define VIRTIO_PCI_CAP_VNDR 0 +#define VIRTIO_PCI_CAP_NEXT 1 +#define VIRTIO_PCI_CAP_LEN 2 +#define VIRTIO_PCI_CAP_CFG_TYPE 3 +#define VIRTIO_PCI_CAP_BAR 4 +#define VIRTIO_PCI_CAP_OFFSET 8 +#define VIRTIO_PCI_CAP_LENGTH 12 + +#define VIRTIO_PCI_NOTIFY_CAP_MULT 16 + +#define VIRTIO_PCI_COMMON_DFSELECT 0 +#define VIRTIO_PCI_COMMON_DF 4 +#define VIRTIO_PCI_COMMON_GFSELECT 8 +#define VIRTIO_PCI_COMMON_GF 12 +#define VIRTIO_PCI_COMMON_MSIX 16 +#define VIRTIO_PCI_COMMON_NUMQ 18 +#define VIRTIO_PCI_COMMON_STATUS 20 +#define VIRTIO_PCI_COMMON_CFGGENERATION 21 +#define VIRTIO_PCI_COMMON_Q_SELECT 22 +#define VIRTIO_PCI_COMMON_Q_SIZE 24 +#define VIRTIO_PCI_COMMON_Q_MSIX 26 +#define VIRTIO_PCI_COMMON_Q_ENABLE 28 +#define VIRTIO_PCI_COMMON_Q_NOFF 30 +#define VIRTIO_PCI_COMMON_Q_DESCLO 32 +#define VIRTIO_PCI_COMMON_Q_DESCHI 36 +#define VIRTIO_PCI_COMMON_Q_AVAILLO 40 +#define VIRTIO_PCI_COMMON_Q_AVAILHI 44 +#define VIRTIO_PCI_COMMON_Q_USEDLO 48 +#define VIRTIO_PCI_COMMON_Q_USEDHI 52 + +#endif /* VIRTIO_PCI_NO_MODERN */ + +#endif /* _LINUX_VIRTIO_PCI_H */ diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c new file mode 100644 index 0000000000..08764ee6f2 --- /dev/null +++ b/drivers/virtio/virtio_pci_legacy.c @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * VirtIO PCI bus transport driver + * Ported from Linux drivers/virtio/virtio_pci*.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "virtio_pci.h" + +#define VIRTIO_PCI_DRV_NAME "virtio-pci.l" + +/* PCI device ID in the range 0x1000 to 0x103f */ +#define VIRTIO_PCI_VENDOR_ID 0x1af4 +#define VIRTIO_PCI_DEVICE_ID00 0x1000 +#define VIRTIO_PCI_DEVICE_ID01 0x1001 +#define VIRTIO_PCI_DEVICE_ID02 0x1002 +#define VIRTIO_PCI_DEVICE_ID03 0x1003 +#define VIRTIO_PCI_DEVICE_ID04 0x1004 +#define VIRTIO_PCI_DEVICE_ID05 0x1005 +#define VIRTIO_PCI_DEVICE_ID06 0x1006 +#define VIRTIO_PCI_DEVICE_ID07 0x1007 +#define VIRTIO_PCI_DEVICE_ID08 0x1008 +#define VIRTIO_PCI_DEVICE_ID09 0x1009 +#define VIRTIO_PCI_DEVICE_ID0A 0x100a +#define VIRTIO_PCI_DEVICE_ID0B 0x100b +#define VIRTIO_PCI_DEVICE_ID0C 0x100c +#define VIRTIO_PCI_DEVICE_ID0D 0x100d +#define VIRTIO_PCI_DEVICE_ID0E 0x100e +#define VIRTIO_PCI_DEVICE_ID0F 0x100f +#define VIRTIO_PCI_DEVICE_ID10 0x1010 +#define VIRTIO_PCI_DEVICE_ID11 0x1011 +#define VIRTIO_PCI_DEVICE_ID12 0x1012 +#define VIRTIO_PCI_DEVICE_ID13 0x1013 +#define VIRTIO_PCI_DEVICE_ID14 0x1014 +#define VIRTIO_PCI_DEVICE_ID15 0x1015 +#define VIRTIO_PCI_DEVICE_ID16 0x1016 +#define VIRTIO_PCI_DEVICE_ID17 0x1017 +#define VIRTIO_PCI_DEVICE_ID18 0x1018 +#define VIRTIO_PCI_DEVICE_ID19 0x1019 +#define VIRTIO_PCI_DEVICE_ID1A 0x101a +#define VIRTIO_PCI_DEVICE_ID1B 0x101b +#define VIRTIO_PCI_DEVICE_ID1C 0x101c +#define VIRTIO_PCI_DEVICE_ID1D 0x101d +#define VIRTIO_PCI_DEVICE_ID1E 0x101e +#define VIRTIO_PCI_DEVICE_ID1F 0x101f +#define VIRTIO_PCI_DEVICE_ID20 0x1020 +#define VIRTIO_PCI_DEVICE_ID21 0x1021 +#define VIRTIO_PCI_DEVICE_ID22 0x1022 +#define VIRTIO_PCI_DEVICE_ID23 0x1023 +#define VIRTIO_PCI_DEVICE_ID24 0x1024 +#define VIRTIO_PCI_DEVICE_ID25 0x1025 +#define VIRTIO_PCI_DEVICE_ID26 0x1026 +#define VIRTIO_PCI_DEVICE_ID27 0x1027 +#define VIRTIO_PCI_DEVICE_ID28 0x1028 +#define VIRTIO_PCI_DEVICE_ID29 0x1029 +#define VIRTIO_PCI_DEVICE_ID2A 0x102a +#define VIRTIO_PCI_DEVICE_ID2B 0x102b +#define VIRTIO_PCI_DEVICE_ID2C 0x102c +#define VIRTIO_PCI_DEVICE_ID2D 0x102d +#define VIRTIO_PCI_DEVICE_ID2E 0x102e +#define VIRTIO_PCI_DEVICE_ID2F 0x102f +#define VIRTIO_PCI_DEVICE_ID30 0x1030 +#define VIRTIO_PCI_DEVICE_ID31 0x1031 +#define VIRTIO_PCI_DEVICE_ID32 0x1032 +#define VIRTIO_PCI_DEVICE_ID33 0x1033 +#define VIRTIO_PCI_DEVICE_ID34 0x1034 +#define VIRTIO_PCI_DEVICE_ID35 0x1035 +#define VIRTIO_PCI_DEVICE_ID36 0x1036 +#define VIRTIO_PCI_DEVICE_ID37 0x1037 +#define VIRTIO_PCI_DEVICE_ID38 0x1038 +#define VIRTIO_PCI_DEVICE_ID39 0x1039 +#define VIRTIO_PCI_DEVICE_ID3A 0x103a +#define VIRTIO_PCI_DEVICE_ID3B 0x103b +#define VIRTIO_PCI_DEVICE_ID3C 0x103c +#define VIRTIO_PCI_DEVICE_ID3D 0x103d +#define VIRTIO_PCI_DEVICE_ID3E 0x103e +#define VIRTIO_PCI_DEVICE_ID3F 0x103f + +/** + * virtio pci transport driver private data + * + * @ioaddr: pci transport device register base + * @version: pci transport device version + */ +struct virtio_pci_priv { + void __iomem *ioaddr; +}; + +static int virtio_pci_get_config(struct udevice *udev, unsigned int offset, + void *buf, unsigned int len) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + void __iomem *ioaddr = priv->ioaddr + VIRTIO_PCI_CONFIG_OFF(false); + u8 *ptr = buf; + int i; + + for (i = 0; i < len; i++) + ptr[i] = ioread8(ioaddr + i); + + return 0; +} + +static int virtio_pci_set_config(struct udevice *udev, unsigned int offset, + const void *buf, unsigned int len) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + void __iomem *ioaddr = priv->ioaddr + VIRTIO_PCI_CONFIG_OFF(false); + const u8 *ptr = buf; + int i; + + for (i = 0; i < len; i++) + iowrite8(ptr[i], ioaddr + i); + + return 0; +} + +static int virtio_pci_get_status(struct udevice *udev, u8 *status) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + *status = ioread8(priv->ioaddr + VIRTIO_PCI_STATUS); + + return 0; +} + +static int virtio_pci_set_status(struct udevice *udev, u8 status) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* We should never be setting status to 0 */ + WARN_ON(status == 0); + + iowrite8(status, priv->ioaddr + VIRTIO_PCI_STATUS); + + return 0; +} + +static int virtio_pci_reset(struct udevice *udev) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* 0 status means a reset */ + iowrite8(0, priv->ioaddr + VIRTIO_PCI_STATUS); + + /* + * Flush out the status write, and flush in device writes, + * including MSI-X interrupts, if any. + */ + ioread8(priv->ioaddr + VIRTIO_PCI_STATUS); + + return 0; +} + +static int virtio_pci_get_features(struct udevice *udev, u64 *features) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* + * When someone needs more than 32 feature bits, we'll need to + * steal a bit to indicate that the rest are somewhere else. + */ + *features = ioread32(priv->ioaddr + VIRTIO_PCI_HOST_FEATURES); + + return 0; +} + +static int virtio_pci_set_features(struct udevice *udev) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* Make sure we don't have any features > 32 bits! */ + WARN_ON((u32)uc_priv->features != uc_priv->features); + + /* We only support 32 feature bits */ + iowrite32(uc_priv->features, priv->ioaddr + VIRTIO_PCI_GUEST_FEATURES); + + return 0; +} + +static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev, + unsigned int index) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + struct virtqueue *vq; + unsigned int num; + int err; + + /* Select the queue we're interested in */ + iowrite16(index, priv->ioaddr + VIRTIO_PCI_QUEUE_SEL); + + /* Check if queue is either not available or already active */ + num = ioread16(priv->ioaddr + VIRTIO_PCI_QUEUE_NUM); + if (!num || ioread32(priv->ioaddr + VIRTIO_PCI_QUEUE_PFN)) { + err = -ENOENT; + goto error_available; + } + + /* Create the vring */ + vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev); + if (!vq) { + err = -ENOMEM; + goto error_available; + } + + /* Activate the queue */ + iowrite32(virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT, + priv->ioaddr + VIRTIO_PCI_QUEUE_PFN); + + return vq; + +error_available: + return ERR_PTR(err); +} + +static void virtio_pci_del_vq(struct virtqueue *vq) +{ + struct virtio_pci_priv *priv = dev_get_priv(vq->vdev); + unsigned int index = vq->index; + + iowrite16(index, priv->ioaddr + VIRTIO_PCI_QUEUE_SEL); + + /* Select and deactivate the queue */ + iowrite32(0, priv->ioaddr + VIRTIO_PCI_QUEUE_PFN); + + vring_del_virtqueue(vq); +} + +static int virtio_pci_del_vqs(struct udevice *udev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtqueue *vq, *n; + + list_for_each_entry_safe(vq, n, &uc_priv->vqs, list) + virtio_pci_del_vq(vq); + + return 0; +} + +static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs, + struct virtqueue *vqs[]) +{ + int i; + + for (i = 0; i < nvqs; ++i) { + vqs[i] = virtio_pci_setup_vq(udev, i); + if (IS_ERR(vqs[i])) { + virtio_pci_del_vqs(udev); + return PTR_ERR(vqs[i]); + } + } + + return 0; +} + +static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* + * We write the queue's selector into the notification register + * to signal the other end + */ + iowrite16(vq->index, priv->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY); + + return 0; +} + +static int virtio_pci_bind(struct udevice *udev) +{ + static int num_devs; + char name[20]; + + /* Create a unique device name for PCI type devices */ + sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++); + device_set_name(udev, name); + + return 0; +} + +static int virtio_pci_probe(struct udevice *udev) +{ + struct pci_child_platdata *pplat = dev_get_parent_platdata(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtio_pci_priv *priv = dev_get_priv(udev); + u16 subvendor, subdevice; + u8 revision; + + /* We only own devices >= 0x1000 and <= 0x103f: leave the rest. */ + if (pplat->device < 0x1000 || pplat->device > 0x103f) + return -ENODEV; + + /* Transitional devices must have a PCI revision ID of 0 */ + dm_pci_read_config8(udev, PCI_REVISION_ID, &revision); + if (revision != VIRTIO_PCI_ABI_VERSION) { + printf("(%s): virtio_pci expected ABI version %d, got %d\n", + udev->name, VIRTIO_PCI_ABI_VERSION, revision); + return -ENODEV; + } + + /* + * Transitional devices must have the PCI subsystem device ID matching + * the virtio device ID + */ + dm_pci_read_config16(udev, PCI_SUBSYSTEM_ID, &subdevice); + dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor); + uc_priv->device = subdevice; + uc_priv->vendor = subvendor; + + priv->ioaddr = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, PCI_REGION_IO); + if (!priv->ioaddr) + return -ENXIO; + debug("(%s): virtio legacy device reg base %04lx\n", + udev->name, (ulong)priv->ioaddr); + + debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name, + uc_priv->device, uc_priv->vendor, revision); + + return 0; +} + +static const struct dm_virtio_ops virtio_pci_ops = { + .get_config = virtio_pci_get_config, + .set_config = virtio_pci_set_config, + .get_status = virtio_pci_get_status, + .set_status = virtio_pci_set_status, + .reset = virtio_pci_reset, + .get_features = virtio_pci_get_features, + .set_features = virtio_pci_set_features, + .find_vqs = virtio_pci_find_vqs, + .del_vqs = virtio_pci_del_vqs, + .notify = virtio_pci_notify, +}; + +U_BOOT_DRIVER(virtio_pci_legacy) = { + .name = VIRTIO_PCI_DRV_NAME, + .id = UCLASS_VIRTIO, + .ops = &virtio_pci_ops, + .bind = virtio_pci_bind, + .probe = virtio_pci_probe, + .priv_auto_alloc_size = sizeof(struct virtio_pci_priv), +}; + +static struct pci_device_id virtio_pci_supported[] = { + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) }, + {}, +}; + +U_BOOT_PCI_DEVICE(virtio_pci_legacy, virtio_pci_supported); diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c new file mode 100644 index 0000000000..da76aea8d1 --- /dev/null +++ b/drivers/virtio/virtio_pci_modern.c @@ -0,0 +1,609 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * VirtIO PCI bus transport driver + * Ported from Linux drivers/virtio/virtio_pci*.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "virtio_pci.h" + +#define VIRTIO_PCI_DRV_NAME "virtio-pci.m" + +/* PCI device ID in the range 0x1040 to 0x107f */ +#define VIRTIO_PCI_VENDOR_ID 0x1af4 +#define VIRTIO_PCI_DEVICE_ID00 0x1040 +#define VIRTIO_PCI_DEVICE_ID01 0x1041 +#define VIRTIO_PCI_DEVICE_ID02 0x1042 +#define VIRTIO_PCI_DEVICE_ID03 0x1043 +#define VIRTIO_PCI_DEVICE_ID04 0x1044 +#define VIRTIO_PCI_DEVICE_ID05 0x1045 +#define VIRTIO_PCI_DEVICE_ID06 0x1046 +#define VIRTIO_PCI_DEVICE_ID07 0x1047 +#define VIRTIO_PCI_DEVICE_ID08 0x1048 +#define VIRTIO_PCI_DEVICE_ID09 0x1049 +#define VIRTIO_PCI_DEVICE_ID0A 0x104a +#define VIRTIO_PCI_DEVICE_ID0B 0x104b +#define VIRTIO_PCI_DEVICE_ID0C 0x104c +#define VIRTIO_PCI_DEVICE_ID0D 0x104d +#define VIRTIO_PCI_DEVICE_ID0E 0x104e +#define VIRTIO_PCI_DEVICE_ID0F 0x104f +#define VIRTIO_PCI_DEVICE_ID10 0x1050 +#define VIRTIO_PCI_DEVICE_ID11 0x1051 +#define VIRTIO_PCI_DEVICE_ID12 0x1052 +#define VIRTIO_PCI_DEVICE_ID13 0x1053 +#define VIRTIO_PCI_DEVICE_ID14 0x1054 +#define VIRTIO_PCI_DEVICE_ID15 0x1055 +#define VIRTIO_PCI_DEVICE_ID16 0x1056 +#define VIRTIO_PCI_DEVICE_ID17 0x1057 +#define VIRTIO_PCI_DEVICE_ID18 0x1058 +#define VIRTIO_PCI_DEVICE_ID19 0x1059 +#define VIRTIO_PCI_DEVICE_ID1A 0x105a +#define VIRTIO_PCI_DEVICE_ID1B 0x105b +#define VIRTIO_PCI_DEVICE_ID1C 0x105c +#define VIRTIO_PCI_DEVICE_ID1D 0x105d +#define VIRTIO_PCI_DEVICE_ID1E 0x105e +#define VIRTIO_PCI_DEVICE_ID1F 0x105f +#define VIRTIO_PCI_DEVICE_ID20 0x1060 +#define VIRTIO_PCI_DEVICE_ID21 0x1061 +#define VIRTIO_PCI_DEVICE_ID22 0x1062 +#define VIRTIO_PCI_DEVICE_ID23 0x1063 +#define VIRTIO_PCI_DEVICE_ID24 0x1064 +#define VIRTIO_PCI_DEVICE_ID25 0x1065 +#define VIRTIO_PCI_DEVICE_ID26 0x1066 +#define VIRTIO_PCI_DEVICE_ID27 0x1067 +#define VIRTIO_PCI_DEVICE_ID28 0x1068 +#define VIRTIO_PCI_DEVICE_ID29 0x1069 +#define VIRTIO_PCI_DEVICE_ID2A 0x106a +#define VIRTIO_PCI_DEVICE_ID2B 0x106b +#define VIRTIO_PCI_DEVICE_ID2C 0x106c +#define VIRTIO_PCI_DEVICE_ID2D 0x106d +#define VIRTIO_PCI_DEVICE_ID2E 0x106e +#define VIRTIO_PCI_DEVICE_ID2F 0x106f +#define VIRTIO_PCI_DEVICE_ID30 0x1070 +#define VIRTIO_PCI_DEVICE_ID31 0x1071 +#define VIRTIO_PCI_DEVICE_ID32 0x1072 +#define VIRTIO_PCI_DEVICE_ID33 0x1073 +#define VIRTIO_PCI_DEVICE_ID34 0x1074 +#define VIRTIO_PCI_DEVICE_ID35 0x1075 +#define VIRTIO_PCI_DEVICE_ID36 0x1076 +#define VIRTIO_PCI_DEVICE_ID37 0x1077 +#define VIRTIO_PCI_DEVICE_ID38 0x1078 +#define VIRTIO_PCI_DEVICE_ID39 0x1079 +#define VIRTIO_PCI_DEVICE_ID3A 0x107a +#define VIRTIO_PCI_DEVICE_ID3B 0x107b +#define VIRTIO_PCI_DEVICE_ID3C 0x107c +#define VIRTIO_PCI_DEVICE_ID3D 0x107d +#define VIRTIO_PCI_DEVICE_ID3E 0x107e +#define VIRTIO_PCI_DEVICE_ID3F 0x107f + +/** + * virtio pci transport driver private data + * + * @common: pci transport device common register block base + * @notify_base: pci transport device notify register block base + * @device: pci transport device device-specific register block base + * @device_len: pci transport device device-specific register block length + * @notify_offset_multiplier: multiply queue_notify_off by this value + */ +struct virtio_pci_priv { + struct virtio_pci_common_cfg __iomem *common; + void __iomem *notify_base; + void __iomem *device; + u32 device_len; + u32 notify_offset_multiplier; +}; + +static int virtio_pci_get_config(struct udevice *udev, unsigned int offset, + void *buf, unsigned int len) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + u8 b; + __le16 w; + __le32 l; + + WARN_ON(offset + len > priv->device_len); + + switch (len) { + case 1: + b = ioread8(priv->device + offset); + memcpy(buf, &b, sizeof(b)); + break; + case 2: + w = cpu_to_le16(ioread16(priv->device + offset)); + memcpy(buf, &w, sizeof(w)); + break; + case 4: + l = cpu_to_le32(ioread32(priv->device + offset)); + memcpy(buf, &l, sizeof(l)); + break; + case 8: + l = cpu_to_le32(ioread32(priv->device + offset)); + memcpy(buf, &l, sizeof(l)); + l = cpu_to_le32(ioread32(priv->device + offset + sizeof(l))); + memcpy(buf + sizeof(l), &l, sizeof(l)); + break; + default: + WARN_ON(true); + } + + return 0; +} + +static int virtio_pci_set_config(struct udevice *udev, unsigned int offset, + const void *buf, unsigned int len) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + u8 b; + __le16 w; + __le32 l; + + WARN_ON(offset + len > priv->device_len); + + switch (len) { + case 1: + memcpy(&b, buf, sizeof(b)); + iowrite8(b, priv->device + offset); + break; + case 2: + memcpy(&w, buf, sizeof(w)); + iowrite16(le16_to_cpu(w), priv->device + offset); + break; + case 4: + memcpy(&l, buf, sizeof(l)); + iowrite32(le32_to_cpu(l), priv->device + offset); + break; + case 8: + memcpy(&l, buf, sizeof(l)); + iowrite32(le32_to_cpu(l), priv->device + offset); + memcpy(&l, buf + sizeof(l), sizeof(l)); + iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l)); + break; + default: + WARN_ON(true); + } + + return 0; +} + +static int virtio_pci_generation(struct udevice *udev, u32 *counter) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + *counter = ioread8(&priv->common->config_generation); + + return 0; +} + +static int virtio_pci_get_status(struct udevice *udev, u8 *status) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + *status = ioread8(&priv->common->device_status); + + return 0; +} + +static int virtio_pci_set_status(struct udevice *udev, u8 status) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* We should never be setting status to 0 */ + WARN_ON(status == 0); + + iowrite8(status, &priv->common->device_status); + + return 0; +} + +static int virtio_pci_reset(struct udevice *udev) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + /* 0 status means a reset */ + iowrite8(0, &priv->common->device_status); + + /* + * After writing 0 to device_status, the driver MUST wait for a read + * of device_status to return 0 before reinitializing the device. + * This will flush out the status write, and flush in device writes, + * including MSI-X interrupts, if any. + */ + while (ioread8(&priv->common->device_status)) + udelay(1000); + + return 0; +} + +static int virtio_pci_get_features(struct udevice *udev, u64 *features) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + + iowrite32(0, &priv->common->device_feature_select); + *features = ioread32(&priv->common->device_feature); + iowrite32(1, &priv->common->device_feature_select); + *features |= ((u64)ioread32(&priv->common->device_feature) << 32); + + return 0; +} + +static int virtio_pci_set_features(struct udevice *udev) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + if (!__virtio_test_bit(udev, VIRTIO_F_VERSION_1)) { + debug("virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1\n"); + return -EINVAL; + } + + iowrite32(0, &priv->common->guest_feature_select); + iowrite32((u32)uc_priv->features, &priv->common->guest_feature); + iowrite32(1, &priv->common->guest_feature_select); + iowrite32(uc_priv->features >> 32, &priv->common->guest_feature); + + return 0; +} + +static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev, + unsigned int index) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + struct virtio_pci_common_cfg __iomem *cfg = priv->common; + struct virtqueue *vq; + u16 num; + u64 addr; + int err; + + if (index >= ioread16(&cfg->num_queues)) + return ERR_PTR(-ENOENT); + + /* Select the queue we're interested in */ + iowrite16(index, &cfg->queue_select); + + /* Check if queue is either not available or already active */ + num = ioread16(&cfg->queue_size); + if (!num || ioread16(&cfg->queue_enable)) + return ERR_PTR(-ENOENT); + + if (num & (num - 1)) { + printf("(%s): bad queue size %u", udev->name, num); + return ERR_PTR(-EINVAL); + } + + /* Create the vring */ + vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev); + if (!vq) { + err = -ENOMEM; + goto error_available; + } + + /* Activate the queue */ + iowrite16(virtqueue_get_vring_size(vq), &cfg->queue_size); + + addr = virtqueue_get_desc_addr(vq); + iowrite32((u32)addr, &cfg->queue_desc_lo); + iowrite32(addr >> 32, &cfg->queue_desc_hi); + + addr = virtqueue_get_avail_addr(vq); + iowrite32((u32)addr, &cfg->queue_avail_lo); + iowrite32(addr >> 32, &cfg->queue_avail_hi); + + addr = virtqueue_get_used_addr(vq); + iowrite32((u32)addr, &cfg->queue_used_lo); + iowrite32(addr >> 32, &cfg->queue_used_hi); + + iowrite16(1, &cfg->queue_enable); + + return vq; + +error_available: + return ERR_PTR(err); +} + +static void virtio_pci_del_vq(struct virtqueue *vq) +{ + struct virtio_pci_priv *priv = dev_get_priv(vq->vdev); + unsigned int index = vq->index; + + iowrite16(index, &priv->common->queue_select); + + /* Select and deactivate the queue */ + iowrite16(0, &priv->common->queue_enable); + + vring_del_virtqueue(vq); +} + +static int virtio_pci_del_vqs(struct udevice *udev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtqueue *vq, *n; + + list_for_each_entry_safe(vq, n, &uc_priv->vqs, list) + virtio_pci_del_vq(vq); + + return 0; +} + +static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs, + struct virtqueue *vqs[]) +{ + int i; + + for (i = 0; i < nvqs; ++i) { + vqs[i] = virtio_pci_setup_vq(udev, i); + if (IS_ERR(vqs[i])) { + virtio_pci_del_vqs(udev); + return PTR_ERR(vqs[i]); + } + } + + return 0; +} + +static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq) +{ + struct virtio_pci_priv *priv = dev_get_priv(udev); + u16 off; + + /* Select the queue we're interested in */ + iowrite16(vq->index, &priv->common->queue_select); + + /* get offset of notification word for this vq */ + off = ioread16(&priv->common->queue_notify_off); + + /* + * We write the queue's selector into the notification register + * to signal the other end + */ + iowrite16(vq->index, + priv->notify_base + off * priv->notify_offset_multiplier); + + return 0; +} + +/** + * virtio_pci_find_capability - walk capabilities to find device info + * + * @udev: the transport device + * @cfg_type: the VIRTIO_PCI_CAP_* value we seek + * + * @return offset of the configuration structure + */ +static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type) +{ + int pos; + int offset; + u8 type, bar; + + for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR); + pos > 0; + pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) { + offset = pos + offsetof(struct virtio_pci_cap, cfg_type); + dm_pci_read_config8(udev, offset, &type); + offset = pos + offsetof(struct virtio_pci_cap, bar); + dm_pci_read_config8(udev, offset, &bar); + + /* Ignore structures with reserved BAR values */ + if (bar > 0x5) + continue; + + if (type == cfg_type) + return pos; + } + + return 0; +} + +/** + * virtio_pci_map_capability - map base address of the capability + * + * @udev: the transport device + * @off: offset of the configuration structure + * + * @return base address of the capability + */ +static void __iomem *virtio_pci_map_capability(struct udevice *udev, int off) +{ + u8 bar; + u32 offset; + ulong base; + void __iomem *p; + + if (!off) + return NULL; + + offset = off + offsetof(struct virtio_pci_cap, bar); + dm_pci_read_config8(udev, offset, &bar); + offset = off + offsetof(struct virtio_pci_cap, offset); + dm_pci_read_config32(udev, offset, &offset); + + /* + * TODO: adding 64-bit BAR support + * + * Per spec, the BAR is permitted to be either 32-bit or 64-bit. + * For simplicity, only read the BAR address as 32-bit. + */ + base = dm_pci_read_bar32(udev, bar); + p = (void __iomem *)base + offset; + + return p; +} + +static int virtio_pci_bind(struct udevice *udev) +{ + static int num_devs; + char name[20]; + + /* Create a unique device name */ + sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++); + device_set_name(udev, name); + + return 0; +} + +static int virtio_pci_probe(struct udevice *udev) +{ + struct pci_child_platdata *pplat = dev_get_parent_platdata(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtio_pci_priv *priv = dev_get_priv(udev); + u16 subvendor; + u8 revision; + int common, notify, device; + int offset; + + /* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */ + if (pplat->device < 0x1040 || pplat->device > 0x107f) + return -ENODEV; + + /* Transitional devices must not have a PCI revision ID of 0 */ + dm_pci_read_config8(udev, PCI_REVISION_ID, &revision); + + /* Modern devices: simply use PCI device id, but start from 0x1040. */ + uc_priv->device = pplat->device - 0x1040; + dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor); + uc_priv->vendor = subvendor; + + /* Check for a common config: if not, use legacy mode (bar 0) */ + common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG); + if (!common) { + printf("(%s): leaving for legacy driver\n", udev->name); + return -ENODEV; + } + + /* If common is there, notify should be too */ + notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG); + if (!notify) { + printf("(%s): missing capabilities %i/%i\n", udev->name, + common, notify); + return -EINVAL; + } + + /* + * Device capability is only mandatory for devices that have + * device-specific configuration. + */ + device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG); + if (device) { + offset = notify + offsetof(struct virtio_pci_cap, length); + dm_pci_read_config32(udev, offset, &priv->device_len); + } + + /* Map configuration structures */ + priv->common = virtio_pci_map_capability(udev, common); + priv->notify_base = virtio_pci_map_capability(udev, notify); + priv->device = virtio_pci_map_capability(udev, device); + debug("(%p): common @ %p, notify base @ %p, device @ %p\n", + udev, priv->common, priv->notify_base, priv->device); + + /* Read notify_off_multiplier from config space */ + offset = notify + offsetof(struct virtio_pci_notify_cap, + notify_off_multiplier); + dm_pci_read_config32(udev, offset, &priv->notify_offset_multiplier); + + debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name, + uc_priv->device, uc_priv->vendor, revision); + + return 0; +} + +static const struct dm_virtio_ops virtio_pci_ops = { + .get_config = virtio_pci_get_config, + .set_config = virtio_pci_set_config, + .generation = virtio_pci_generation, + .get_status = virtio_pci_get_status, + .set_status = virtio_pci_set_status, + .reset = virtio_pci_reset, + .get_features = virtio_pci_get_features, + .set_features = virtio_pci_set_features, + .find_vqs = virtio_pci_find_vqs, + .del_vqs = virtio_pci_del_vqs, + .notify = virtio_pci_notify, +}; + +U_BOOT_DRIVER(virtio_pci_modern) = { + .name = VIRTIO_PCI_DRV_NAME, + .id = UCLASS_VIRTIO, + .ops = &virtio_pci_ops, + .bind = virtio_pci_bind, + .probe = virtio_pci_probe, + .priv_auto_alloc_size = sizeof(struct virtio_pci_priv), +}; + +static struct pci_device_id virtio_pci_supported[] = { + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) }, + { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) }, + {}, +}; + +U_BOOT_PCI_DEVICE(virtio_pci_modern, virtio_pci_supported); diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c new file mode 100644 index 0000000000..0eeb3501c2 --- /dev/null +++ b/drivers/virtio/virtio_ring.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * virtio ring implementation + */ + +#include +#include +#include +#include +#include +#include + +int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[], + unsigned int out_sgs, unsigned int in_sgs) +{ + struct vring_desc *desc; + unsigned int total_sg = out_sgs + in_sgs; + unsigned int i, n, avail, descs_used, uninitialized_var(prev); + int head; + + WARN_ON(total_sg == 0); + + head = vq->free_head; + + desc = vq->vring.desc; + i = head; + descs_used = total_sg; + + if (vq->num_free < descs_used) { + debug("Can't add buf len %i - avail = %i\n", + descs_used, vq->num_free); + /* + * FIXME: for historical reasons, we force a notify here if + * there are outgoing parts to the buffer. Presumably the + * host should service the ring ASAP. + */ + if (out_sgs) + virtio_notify(vq->vdev, vq); + return -ENOSPC; + } + + for (n = 0; n < out_sgs; n++) { + struct virtio_sg *sg = sgs[n]; + + desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT); + desc[i].addr = cpu_to_virtio64(vq->vdev, (u64)(size_t)sg->addr); + desc[i].len = cpu_to_virtio32(vq->vdev, sg->length); + + prev = i; + i = virtio16_to_cpu(vq->vdev, desc[i].next); + } + for (; n < (out_sgs + in_sgs); n++) { + struct virtio_sg *sg = sgs[n]; + + desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT | + VRING_DESC_F_WRITE); + desc[i].addr = cpu_to_virtio64(vq->vdev, + (u64)(uintptr_t)sg->addr); + desc[i].len = cpu_to_virtio32(vq->vdev, sg->length); + + prev = i; + i = virtio16_to_cpu(vq->vdev, desc[i].next); + } + /* Last one doesn't continue */ + desc[prev].flags &= cpu_to_virtio16(vq->vdev, ~VRING_DESC_F_NEXT); + + /* We're using some buffers from the free list. */ + vq->num_free -= descs_used; + + /* Update free pointer */ + vq->free_head = i; + + /* + * Put entry in available array (but don't update avail->idx + * until they do sync). + */ + avail = vq->avail_idx_shadow & (vq->vring.num - 1); + vq->vring.avail->ring[avail] = cpu_to_virtio16(vq->vdev, head); + + /* + * Descriptors and available array need to be set before we expose the + * new available array entries. + */ + virtio_wmb(); + vq->avail_idx_shadow++; + vq->vring.avail->idx = cpu_to_virtio16(vq->vdev, vq->avail_idx_shadow); + vq->num_added++; + + /* + * This is very unlikely, but theoretically possible. + * Kick just in case. + */ + if (unlikely(vq->num_added == (1 << 16) - 1)) + virtqueue_kick(vq); + + return 0; +} + +static bool virtqueue_kick_prepare(struct virtqueue *vq) +{ + u16 new, old; + bool needs_kick; + + /* + * We need to expose available array entries before checking + * avail event. + */ + virtio_mb(); + + old = vq->avail_idx_shadow - vq->num_added; + new = vq->avail_idx_shadow; + vq->num_added = 0; + + if (vq->event) { + needs_kick = vring_need_event(virtio16_to_cpu(vq->vdev, + vring_avail_event(&vq->vring)), new, old); + } else { + needs_kick = !(vq->vring.used->flags & cpu_to_virtio16(vq->vdev, + VRING_USED_F_NO_NOTIFY)); + } + + return needs_kick; +} + +void virtqueue_kick(struct virtqueue *vq) +{ + if (virtqueue_kick_prepare(vq)) + virtio_notify(vq->vdev, vq); +} + +static void detach_buf(struct virtqueue *vq, unsigned int head) +{ + unsigned int i; + __virtio16 nextflag = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT); + + /* Put back on free list: unmap first-level descriptors and find end */ + i = head; + + while (vq->vring.desc[i].flags & nextflag) { + i = virtio16_to_cpu(vq->vdev, vq->vring.desc[i].next); + vq->num_free++; + } + + vq->vring.desc[i].next = cpu_to_virtio16(vq->vdev, vq->free_head); + vq->free_head = head; + + /* Plus final descriptor */ + vq->num_free++; +} + +static inline bool more_used(const struct virtqueue *vq) +{ + return vq->last_used_idx != virtio16_to_cpu(vq->vdev, + vq->vring.used->idx); +} + +void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len) +{ + unsigned int i; + u16 last_used; + + if (!more_used(vq)) { + debug("(%s.%d): No more buffers in queue\n", + vq->vdev->name, vq->index); + return NULL; + } + + /* Only get used array entries after they have been exposed by host */ + virtio_rmb(); + + last_used = (vq->last_used_idx & (vq->vring.num - 1)); + i = virtio32_to_cpu(vq->vdev, vq->vring.used->ring[last_used].id); + if (len) { + *len = virtio32_to_cpu(vq->vdev, + vq->vring.used->ring[last_used].len); + debug("(%s.%d): last used idx %u with len %u\n", + vq->vdev->name, vq->index, i, *len); + } + + if (unlikely(i >= vq->vring.num)) { + printf("(%s.%d): id %u out of range\n", + vq->vdev->name, vq->index, i); + return NULL; + } + + detach_buf(vq, i); + vq->last_used_idx++; + /* + * If we expect an interrupt for the next entry, tell host + * by writing event index and flush out the write before + * the read in the next get_buf call. + */ + if (!(vq->avail_flags_shadow & VRING_AVAIL_F_NO_INTERRUPT)) + virtio_store_mb(&vring_used_event(&vq->vring), + cpu_to_virtio16(vq->vdev, vq->last_used_idx)); + + return (void *)(uintptr_t)virtio64_to_cpu(vq->vdev, + vq->vring.desc[i].addr); +} + +static struct virtqueue *__vring_new_virtqueue(unsigned int index, + struct vring vring, + struct udevice *udev) +{ + unsigned int i; + struct virtqueue *vq; + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct udevice *vdev = uc_priv->vdev; + + vq = malloc(sizeof(*vq)); + if (!vq) + return NULL; + + vq->vdev = vdev; + vq->index = index; + vq->num_free = vring.num; + vq->vring = vring; + vq->last_used_idx = 0; + vq->avail_flags_shadow = 0; + vq->avail_idx_shadow = 0; + vq->num_added = 0; + list_add_tail(&vq->list, &uc_priv->vqs); + + vq->event = virtio_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX); + + /* Tell other side not to bother us */ + vq->avail_flags_shadow |= VRING_AVAIL_F_NO_INTERRUPT; + if (!vq->event) + vq->vring.avail->flags = cpu_to_virtio16(vdev, + vq->avail_flags_shadow); + + /* Put everything in free lists */ + vq->free_head = 0; + for (i = 0; i < vring.num - 1; i++) + vq->vring.desc[i].next = cpu_to_virtio16(vdev, i + 1); + + return vq; +} + +struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, + unsigned int vring_align, + struct udevice *udev) +{ + struct virtqueue *vq; + void *queue = NULL; + struct vring vring; + + /* We assume num is a power of 2 */ + if (num & (num - 1)) { + printf("Bad virtqueue length %u\n", num); + return NULL; + } + + /* TODO: allocate each queue chunk individually */ + for (; num && vring_size(num, vring_align) > PAGE_SIZE; num /= 2) { + queue = memalign(PAGE_SIZE, vring_size(num, vring_align)); + if (queue) + break; + } + + if (!num) + return NULL; + + if (!queue) { + /* Try to get a single page. You are my only hope! */ + queue = memalign(PAGE_SIZE, vring_size(num, vring_align)); + } + if (!queue) + return NULL; + + memset(queue, 0, vring_size(num, vring_align)); + vring_init(&vring, num, queue, vring_align); + + vq = __vring_new_virtqueue(index, vring, udev); + if (!vq) { + free(queue); + return NULL; + } + debug("(%s): created vring @ %p for vq @ %p with num %u\n", udev->name, + queue, vq, num); + + return vq; +} + +void vring_del_virtqueue(struct virtqueue *vq) +{ + free(vq->vring.desc); + list_del(&vq->list); + free(vq); +} + +unsigned int virtqueue_get_vring_size(struct virtqueue *vq) +{ + return vq->vring.num; +} + +ulong virtqueue_get_desc_addr(struct virtqueue *vq) +{ + return (ulong)vq->vring.desc; +} + +ulong virtqueue_get_avail_addr(struct virtqueue *vq) +{ + return (ulong)vq->vring.desc + + ((char *)vq->vring.avail - (char *)vq->vring.desc); +} + +ulong virtqueue_get_used_addr(struct virtqueue *vq) +{ + return (ulong)vq->vring.desc + + ((char *)vq->vring.used - (char *)vq->vring.desc); +} + +bool virtqueue_poll(struct virtqueue *vq, u16 last_used_idx) +{ + virtio_mb(); + + return last_used_idx != virtio16_to_cpu(vq->vdev, vq->vring.used->idx); +} + +void virtqueue_dump(struct virtqueue *vq) +{ + unsigned int i; + + printf("virtqueue %p for dev %s:\n", vq, vq->vdev->name); + printf("\tindex %u, phys addr %p num %u\n", + vq->index, vq->vring.desc, vq->vring.num); + printf("\tfree_head %u, num_added %u, num_free %u\n", + vq->free_head, vq->num_added, vq->num_free); + printf("\tlast_used_idx %u, avail_flags_shadow %u, avail_idx_shadow %u\n", + vq->last_used_idx, vq->avail_flags_shadow, vq->avail_idx_shadow); + + printf("Descriptor dump:\n"); + for (i = 0; i < vq->vring.num; i++) { + printf("\tdesc[%u] = { 0x%llx, len %u, flags %u, next %u }\n", + i, vq->vring.desc[i].addr, vq->vring.desc[i].len, + vq->vring.desc[i].flags, vq->vring.desc[i].next); + } + + printf("Avail ring dump:\n"); + printf("\tflags %u, idx %u\n", + vq->vring.avail->flags, vq->vring.avail->idx); + for (i = 0; i < vq->vring.num; i++) { + printf("\tavail[%u] = %u\n", + i, vq->vring.avail->ring[i]); + } + + printf("Used ring dump:\n"); + printf("\tflags %u, idx %u\n", + vq->vring.used->flags, vq->vring.used->idx); + for (i = 0; i < vq->vring.num; i++) { + printf("\tused[%u] = { %u, %u }\n", i, + vq->vring.used->ring[i].id, vq->vring.used->ring[i].len); + } +} diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c new file mode 100644 index 0000000000..2addb1ebc5 --- /dev/null +++ b/drivers/virtio/virtio_sandbox.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * VirtIO Sandbox transport driver, for testing purpose only + */ + +#include +#include +#include +#include +#include +#include +#include + +struct virtio_sandbox_priv { + u8 id; + u8 status; + u64 device_features; + u64 driver_features; + ulong queue_desc; + ulong queue_available; + ulong queue_used; +}; + +static int virtio_sandbox_get_config(struct udevice *udev, unsigned int offset, + void *buf, unsigned int len) +{ + return 0; +} + +static int virtio_sandbox_set_config(struct udevice *udev, unsigned int offset, + const void *buf, unsigned int len) +{ + return 0; +} + +static int virtio_sandbox_get_status(struct udevice *udev, u8 *status) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + + *status = priv->status; + + return 0; +} + +static int virtio_sandbox_set_status(struct udevice *udev, u8 status) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + + /* We should never be setting status to 0 */ + WARN_ON(status == 0); + + priv->status = status; + + return 0; +} + +static int virtio_sandbox_reset(struct udevice *udev) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + + /* 0 status means a reset */ + priv->status = 0; + + return 0; +} + +static int virtio_sandbox_get_features(struct udevice *udev, u64 *features) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + + *features = priv->device_features; + + return 0; +} + +static int virtio_sandbox_set_features(struct udevice *udev) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + priv->driver_features = uc_priv->features; + + return 0; +} + +static struct virtqueue *virtio_sandbox_setup_vq(struct udevice *udev, + unsigned int index) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + struct virtqueue *vq; + ulong addr; + int err; + + /* Create the vring */ + vq = vring_create_virtqueue(index, 4, 4096, udev); + if (!vq) { + err = -ENOMEM; + goto error_new_virtqueue; + } + + addr = virtqueue_get_desc_addr(vq); + priv->queue_desc = addr; + + addr = virtqueue_get_avail_addr(vq); + priv->queue_available = addr; + + addr = virtqueue_get_used_addr(vq); + priv->queue_used = addr; + + return vq; + +error_new_virtqueue: + return ERR_PTR(err); +} + +static void virtio_sandbox_del_vq(struct virtqueue *vq) +{ + vring_del_virtqueue(vq); +} + +static int virtio_sandbox_del_vqs(struct udevice *udev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + struct virtqueue *vq, *n; + + list_for_each_entry_safe(vq, n, &uc_priv->vqs, list) + virtio_sandbox_del_vq(vq); + + return 0; +} + +static int virtio_sandbox_find_vqs(struct udevice *udev, unsigned int nvqs, + struct virtqueue *vqs[]) +{ + int i; + + for (i = 0; i < nvqs; ++i) { + vqs[i] = virtio_sandbox_setup_vq(udev, i); + if (IS_ERR(vqs[i])) { + virtio_sandbox_del_vqs(udev); + return PTR_ERR(vqs[i]); + } + } + + return 0; +} + +static int virtio_sandbox_notify(struct udevice *udev, struct virtqueue *vq) +{ + return 0; +} + +static int virtio_sandbox_probe(struct udevice *udev) +{ + struct virtio_sandbox_priv *priv = dev_get_priv(udev); + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* fake some information for testing */ + priv->device_features = VIRTIO_F_VERSION_1; + uc_priv->device = VIRTIO_ID_BLOCK; + uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't'; + + return 0; +} + +/* check virtio device driver's remove routine was called to reset the device */ +static int virtio_sandbox_child_post_remove(struct udevice *vdev) +{ + u8 status; + + virtio_get_status(vdev, &status); + if (status) + panic("virtio device was not reset\n"); + + return 0; +} + +static const struct dm_virtio_ops virtio_sandbox1_ops = { + .get_config = virtio_sandbox_get_config, + .set_config = virtio_sandbox_set_config, + .get_status = virtio_sandbox_get_status, + .set_status = virtio_sandbox_set_status, + .reset = virtio_sandbox_reset, + .get_features = virtio_sandbox_get_features, + .set_features = virtio_sandbox_set_features, + .find_vqs = virtio_sandbox_find_vqs, + .del_vqs = virtio_sandbox_del_vqs, + .notify = virtio_sandbox_notify, +}; + +static const struct udevice_id virtio_sandbox1_ids[] = { + { .compatible = "sandbox,virtio1" }, + { } +}; + +U_BOOT_DRIVER(virtio_sandbox1) = { + .name = "virtio-sandbox1", + .id = UCLASS_VIRTIO, + .of_match = virtio_sandbox1_ids, + .ops = &virtio_sandbox1_ops, + .probe = virtio_sandbox_probe, + .child_post_remove = virtio_sandbox_child_post_remove, + .priv_auto_alloc_size = sizeof(struct virtio_sandbox_priv), +}; + +/* this one without notify op */ +static const struct dm_virtio_ops virtio_sandbox2_ops = { + .get_config = virtio_sandbox_get_config, + .set_config = virtio_sandbox_set_config, + .get_status = virtio_sandbox_get_status, + .set_status = virtio_sandbox_set_status, + .reset = virtio_sandbox_reset, + .get_features = virtio_sandbox_get_features, + .set_features = virtio_sandbox_set_features, + .find_vqs = virtio_sandbox_find_vqs, + .del_vqs = virtio_sandbox_del_vqs, +}; + +static const struct udevice_id virtio_sandbox2_ids[] = { + { .compatible = "sandbox,virtio2" }, + { } +}; + +U_BOOT_DRIVER(virtio_sandbox2) = { + .name = "virtio-sandbox2", + .id = UCLASS_VIRTIO, + .of_match = virtio_sandbox2_ids, + .ops = &virtio_sandbox2_ops, + .probe = virtio_sandbox_probe, + .priv_auto_alloc_size = sizeof(struct virtio_sandbox_priv), +}; diff --git a/drivers/w1-eeprom/Kconfig b/drivers/w1-eeprom/Kconfig index 4b7f3c4e0b..34aca4b900 100644 --- a/drivers/w1-eeprom/Kconfig +++ b/drivers/w1-eeprom/Kconfig @@ -18,6 +18,19 @@ config W1_EEPROM_DS24XXX help Maxim DS24 EEPROMs 1-Wire EEPROM support +config W1_EEPROM_DS2502 + bool "Enable Maxim DS2502 Add-Only Memory support" + depends on W1 + help + Maxim DS2502 1-Wire add-only memory support. + This device has 128 bytes of data memory, organized as 4 pages of + 32 bytes and 8 out of band status bytes that may be used to redirect + pages, allowing data to be modified up to 4 times (by external + programming). + + The device may be seen as a 32 byte memory, using the page redirection + or as a 128 byte memory, ignoring the page redirection. + config W1_EEPROM_SANDBOX bool "Enable sandbox onewire EEPROM driver" depends on W1 diff --git a/drivers/w1-eeprom/Makefile b/drivers/w1-eeprom/Makefile index 03cc4c8ac8..83f4008bb5 100644 --- a/drivers/w1-eeprom/Makefile +++ b/drivers/w1-eeprom/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_W1_EEPROM) += w1-eeprom-uclass.o obj-$(CONFIG_W1_EEPROM_DS24XXX) += ds24xxx.o +obj-$(CONFIG_W1_EEPROM_DS2502) += ds2502.o obj-$(CONFIG_W1_EEPROM_SANDBOX) += eep_sandbox.o diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c new file mode 100644 index 0000000000..76ca460ed7 --- /dev/null +++ b/drivers/w1-eeprom/ds2502.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for DS-2502 One wire "Add only Memory". + * + * The chip has 4 pages of 32 bytes. + * In addition it has 8 out of band status bytes that are used, by software, + * as page redirection bytes by an algorithm described in the data sheet. + * This is useful since data cannot be erased once written but it can be + * "patched" up to four times by switching pages. + * + * So, when a read request is entirely in the first page automatically + * apply the page redirection bytes (which allows the device to be seen as + * a 32 byte PROM, writable 4 times). + * + * If the read request is outside of or larger than the first page then read + * the raw data (which allows the device to be seen as a 128 byte PROM, + * writable once). + * + * Copyright (c) 2018 Flowbird + * Martin Fuzzey + */ + +#include +#include +#include +#include +#include + +#define DS2502_PAGE_SIZE 32 +#define DS2502_PAGE_COUNT 4 +#define DS2502_STATUS_SIZE 8 + +#define DS2502_CMD_READ_STATUS 0xAA +#define DS2502_CMD_READ_GEN_CRC 0xC3 + +/* u-boot crc8() is CCITT CRC8, we need x^8 + x^5 + x^4 + 1 LSB first */ +static unsigned int ds2502_crc8(const u8 *buf, int len) +{ + static const u8 poly = 0x8C; /* (1 + x^4 + x^5) + x^8 */ + u8 crc = 0; + int i; + + for (i = 0; i < len; i++) { + u8 data = buf[i]; + int j; + + for (j = 0; j < 8; j++) { + u8 mix = (crc ^ data) & 1; + + crc >>= 1; + if (mix) + crc ^= poly; + data >>= 1; + } + } + return crc; +} + +static int ds2502_read(struct udevice *dev, u8 cmd, + int bytes_in_page, int pos, + u8 *buf, int bytes_for_user) +{ + int retry; + int ret = 0; + + for (retry = 0; retry < 3; retry++) { + u8 pagebuf[DS2502_PAGE_SIZE + 1]; /* 1 byte for CRC8 */ + u8 crc; + int i; + + ret = w1_reset_select(dev); + if (ret) + return ret; + + /* send read to end of page and generate CRC command */ + pagebuf[0] = cmd; + pagebuf[1] = pos & 0xff; + pagebuf[2] = pos >> 8; + crc = ds2502_crc8(pagebuf, 3); + for (i = 0; i < 3; i++) + w1_write_byte(dev, pagebuf[i]); + + /* Check command CRC */ + ret = w1_read_byte(dev); + if (ret < 0) { + dev_dbg(dev, "Error %d reading command CRC\n", ret); + continue; + } + + if (ret != crc) { + dev_dbg(dev, + "bad CRC8 for cmd %02x got=%02X exp=%02X\n", + cmd, ret, crc); + ret = -EIO; + continue; + } + + /* read data and check CRC */ + ret = w1_read_buf(dev, pagebuf, bytes_in_page + 1); + if (ret < 0) { + dev_dbg(dev, "Error %d reading data\n", ret); + continue; + } + + crc = ds2502_crc8(pagebuf, bytes_in_page); + if (crc == pagebuf[bytes_in_page]) { + memcpy(buf, pagebuf, bytes_for_user); + ret = 0; + break; + } + dev_dbg(dev, "Bad CRC8 got=%02X exp=%02X pos=%04X\n", + pagebuf[bytes_in_page], crc, pos); + ret = -EIO; + } + + return ret; +} + +static inline int ds2502_read_status_bytes(struct udevice *dev, u8 *buf) +{ + return ds2502_read(dev, DS2502_CMD_READ_STATUS, + DS2502_STATUS_SIZE, 0, + buf, DS2502_STATUS_SIZE); +} + +/* + * Status bytes (from index 1) contain 1's complement page indirection + * So for N writes: + * N=1: ff ff ff ff ff ff ff 00 + * N=2: ff fe ff ff ff ff ff 00 + * N=3: ff fe fd ff ff ff ff 00 + * N=4: ff fe fd fc ff ff ff 00 + */ +static int ds2502_indirect_page(struct udevice *dev, u8 *status, int page) +{ + int page_seen = 0; + + do { + u8 sb = status[page + 1]; + + if (sb == 0xff) + break; + + page = ~sb & 0xff; + + if (page >= DS2502_PAGE_COUNT) { + dev_err(dev, + "Illegal page redirection status byte %02x\n", + sb); + return -EINVAL; + } + + if (page_seen & (1 << page)) { + dev_err(dev, "Infinite loop in page redirection\n"); + return -EINVAL; + } + + page_seen |= (1 << page); + } while (1); + + return page; +} + +static int ds2502_read_buf(struct udevice *dev, unsigned int offset, + u8 *buf, unsigned int count) +{ + unsigned int min_page = offset / DS2502_PAGE_SIZE; + unsigned int max_page = (offset + count - 1) / DS2502_PAGE_SIZE; + int xfered = 0; + u8 status_bytes[DS2502_STATUS_SIZE]; + int i; + int ret; + + if (min_page >= DS2502_PAGE_COUNT || max_page >= DS2502_PAGE_COUNT) + return -EINVAL; + + if (min_page == 0 && max_page == 0) { + ret = ds2502_read_status_bytes(dev, status_bytes); + if (ret) + return ret; + } else { + /* Dummy one to one page redirection */ + memset(status_bytes, 0xff, sizeof(status_bytes)); + } + + for (i = min_page; i <= max_page; i++) { + int page; + int pos; + int bytes_in_page; + int bytes_for_user; + + page = ds2502_indirect_page(dev, status_bytes, i); + if (page < 0) + return page; + dev_dbg(dev, "page logical %d => physical %d\n", i, page); + + pos = page * DS2502_PAGE_SIZE; + if (i == min_page) + pos += offset % DS2502_PAGE_SIZE; + + bytes_in_page = DS2502_PAGE_SIZE - (pos % DS2502_PAGE_SIZE); + + if (i == max_page) + bytes_for_user = count - xfered; + else + bytes_for_user = bytes_in_page; + + ret = ds2502_read(dev, DS2502_CMD_READ_GEN_CRC, + bytes_in_page, pos, + &buf[xfered], bytes_for_user); + if (ret < 0) + return ret; + + xfered += bytes_for_user; + } + + return 0; +} + +static int ds2502_probe(struct udevice *dev) +{ + struct w1_device *w1; + + w1 = dev_get_parent_platdata(dev); + w1->id = 0; + return 0; +} + +static const struct w1_eeprom_ops ds2502_ops = { + .read_buf = ds2502_read_buf, +}; + +static const struct udevice_id ds2502_id[] = { + { .compatible = "maxim,ds2502", .data = W1_FAMILY_DS2502 }, + { }, +}; + +U_BOOT_DRIVER(ds2502) = { + .name = "ds2502", + .id = UCLASS_W1_EEPROM, + .of_match = ds2502_id, + .ops = &ds2502_ops, + .probe = ds2502_probe, +}; diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index d6e045739d..031bab25ae 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,6 +20,20 @@ config W1_GPIO help Emulate a 1-wire bus using a GPIO. +config W1_MXC + bool "Enable 1-wire controller on i.MX processors" + default no + depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 + help + Support the one wire controller found in some members of the NXP + i.MX SoC family. + There are currently two silicon variants: + V1: i.MX21, i.MX27, i.MX31, i.MX51 + V2: i.MX25, i.MX35, i.MX50, i.MX53 + Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + + The driver supports both silicon variants. + endif endmenu diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile index 7fd8697f84..9825187b65 100644 --- a/drivers/w1/Makefile +++ b/drivers/w1/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_W1) += w1-uclass.o obj-$(CONFIG_W1_GPIO) += w1-gpio.o +obj-$(CONFIG_W1_MXC) += mxc_w1.o diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c new file mode 100644 index 0000000000..9279ba32b8 --- /dev/null +++ b/drivers/w1/mxc_w1.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for one wire controller in some i.MX Socs + * + * There are currently two silicon variants: + * V1: i.MX21, i.MX27, i.MX31, i.MX51 + * V2: i.MX25, i.MX35, i.MX50, i.MX53 + * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + * + * The V1 controller only supports single bit operations. + * The V2 controller is backwards compatible on the register level but adds + * byte size operations and a "search ROM accelerator mode" + * + * This driver does not currently support the search ROM accelerator + * + * Copyright (c) 2018 Flowbird + * Martin Fuzzey + */ + +#include +#include +#include +#include +#include + +struct mxc_w1_regs { + u16 control; +#define MXC_W1_CONTROL_RPP BIT(7) +#define MXC_W1_CONTROL_PST BIT(6) +#define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) +#define MXC_W1_CONTROL_RDST BIT(3) + + u16 time_divider; + u16 reset; + + /* Registers below on V2 silicon only */ + u16 command; + u16 tx_rx; + u16 interrupt; +#define MXC_W1_INTERRUPT_TBE BIT(2) +#define MXC_W1_INTERRUPT_TSRE BIT(3) +#define MXC_W1_INTERRUPT_RBF BIT(4) +#define MXC_W1_INTERRUPT_RSRF BIT(5) + + u16 interrupt_en; +}; + +struct mxc_w1_pdata { + struct mxc_w1_regs *regs; +}; + +/* + * this is the low level routine to read/write a bit on the One Wire + * interface on the hardware. It does write 0 if parameter bit is set + * to 0, otherwise a write 1/read. + */ +static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit) +{ + u16 *ctrl_addr = &pdata->regs->control; + u16 mask = MXC_W1_CONTROL_WR(bit); + unsigned int timeout_cnt = 400; /* Takes max. 120us according to + * datasheet. + */ + + writew(mask, ctrl_addr); + + while (timeout_cnt--) { + if (!(readw(ctrl_addr) & mask)) + break; + + udelay(1); + } + + return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0; +} + +static u8 mxc_w1_read_byte(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + u8 ret = 0; + + for (i = 0; i < 8; i++) + ret |= (mxc_w1_touch_bit(pdata, 1) << i); + + return ret; + } + + readw(®s->tx_rx); + writew(0xFF, ®s->tx_rx); + + do { + udelay(1); /* Without this bytes are sometimes duplicated... */ + status = readw(®s->interrupt); + } while (!(status & MXC_W1_INTERRUPT_RBF)); + + return (u8)readw(®s->tx_rx); +} + +static void mxc_w1_write_byte(struct udevice *dev, u8 byte) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + + for (i = 0; i < 8; i++) + mxc_w1_touch_bit(pdata, (byte >> i) & 0x1); + + return; + } + + readw(®s->tx_rx); + writew(byte, ®s->tx_rx); + + do { + udelay(1); + status = readw(®s->interrupt); + } while (!(status & MXC_W1_INTERRUPT_TSRE)); +} + +static bool mxc_w1_reset(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u16 reg_val; + + writew(MXC_W1_CONTROL_RPP, &pdata->regs->control); + + do { + reg_val = readw(&pdata->regs->control); + } while (reg_val & MXC_W1_CONTROL_RPP); + + return !(reg_val & MXC_W1_CONTROL_PST); +} + +static u8 mxc_w1_triplet(struct udevice *dev, bool bdir) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u8 id_bit = mxc_w1_touch_bit(pdata, 1); + u8 comp_bit = mxc_w1_touch_bit(pdata, 1); + u8 retval; + + if (id_bit && comp_bit) + return 0x03; /* error */ + + if (!id_bit && !comp_bit) { + /* Both bits are valid, take the direction given */ + retval = bdir ? 0x04 : 0; + } else { + /* Only one bit is valid, take that direction */ + bdir = id_bit; + retval = id_bit ? 0x05 : 0x02; + } + + mxc_w1_touch_bit(pdata, bdir); + + return retval; +} + +static int mxc_w1_ofdata_to_platdata(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->regs = (struct mxc_w1_regs *)addr; + + return 0; +}; + +static int mxc_w1_probe(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK); + unsigned int clkdiv; + + if (clkrate < 10000000) { + dev_err(dev, "input clock frequency (%u Hz) too low\n", + clkrate); + return -EINVAL; + } + + clkdiv = clkrate / 1000000; + clkrate /= clkdiv; + if (clkrate < 980000 || clkrate > 1020000) { + dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate); + return -EINVAL; + } + + writew(clkdiv - 1, &pdata->regs->time_divider); + + return 0; +} + +static const struct w1_ops mxc_w1_ops = { + .read_byte = mxc_w1_read_byte, + .reset = mxc_w1_reset, + .triplet = mxc_w1_triplet, + .write_byte = mxc_w1_write_byte, +}; + +static const struct udevice_id mxc_w1_id[] = { + { .compatible = "fsl,imx21-owire", .data = 1 }, + { .compatible = "fsl,imx27-owire", .data = 1 }, + { .compatible = "fsl,imx31-owire", .data = 1 }, + { .compatible = "fsl,imx51-owire", .data = 1 }, + + { .compatible = "fsl,imx25-owire", .data = 2 }, + { .compatible = "fsl,imx35-owire", .data = 2 }, + { .compatible = "fsl,imx50-owire", .data = 2 }, + { .compatible = "fsl,imx53-owire", .data = 2 }, + { }, +}; + +U_BOOT_DRIVER(mxc_w1_drv) = { + .id = UCLASS_W1, + .name = "mxc_w1_drv", + .of_match = mxc_w1_id, + .ofdata_to_platdata = mxc_w1_ofdata_to_platdata, + .ops = &mxc_w1_ops, + .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata), + .probe = mxc_w1_probe, +}; diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c index cb41b68eff..042b3b5ce0 100644 --- a/drivers/w1/w1-uclass.c +++ b/drivers/w1/w1-uclass.c @@ -84,10 +84,6 @@ static int w1_enumerate(struct udevice *bus) rn |= (tmp64 << i); } - /* last device or error, aborting here */ - if ((triplet_ret & 0x03) == 0x03) - last_device = true; - if ((triplet_ret & 0x03) != 0x03) { if (desc_bit == last_zero || last_zero < 0) { last_device = 1; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 02f4e1e32f..10fd3039aa 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -11,6 +11,12 @@ config WATCHDOG config HW_WATCHDOG bool +config WATCHDOG_RESET_DISABLE + bool "Disable reset watchdog" + help + Disable reset watchdog, which can let WATCHDOG_RESET invalid, so + that the watchdog will not be fed in u-boot. + config BCM2835_WDT bool "Enable BCM2835/2836 watchdog driver" select HW_WATCHDOG @@ -103,6 +109,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform. +config WDT_MTK + bool "MediaTek watchdog timer support" + depends on WDT && ARCH_MEDIATEK + help + Select this to enable watchdog timer for MediaTek SoCs. + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config XILINX_TB_WATCHDOG bool "Xilinx Axi watchdog timer support" depends on WDT @@ -118,4 +132,29 @@ config IMX_WATCHDOG Select this to enable the IMX and LSCH2 of Layerscape watchdog driver. +config WDT_AT91 + bool "AT91 watchdog timer support" + depends on WDT + help + Select this to enable Microchip watchdog timer, which can be found on + some AT91 devices. + +config AT91_HW_WDT_TIMEOUT + bool "AT91 watchdog timeout specified" + depends on WDT_AT91 + +config WDT_MT7621 + bool "MediaTek MT7621 watchdog timer support" + depends on WDT && ARCH_MT7620 + help + Select this to enable Ralink / Mediatek watchdog timer, + which can be found on some MediaTek chips. + +config WDT_MPC8xx + bool "MPC8xx watchdog timer support" + depends on WDT && MPC8xx + select CONFIG_MPC8xx_WATCHDOG + help + Select this to enable mpc8xx watchdog timer + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 08406caa0f..d901240ad1 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -3,10 +3,12 @@ # (C) Copyright 2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o +obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o +else +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o @@ -23,3 +25,5 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o +obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o +obj-$(CONFIG_WDT_MTK) += mtk_wdt.o diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index 59afa21efa..523484b1ff 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -119,5 +119,4 @@ U_BOOT_DRIVER(ast_wdt) = { .priv_auto_alloc_size = sizeof(struct ast_wdt_priv), .ofdata_to_platdata = ast_wdt_ofdata_to_platdata, .ops = &ast_wdt_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index fca2849918..13f8772e41 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -2,7 +2,7 @@ /* * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] * - * Watchdog driver for Atmel AT91SAM9x processors. + * Watchdog driver for AT91SAM9x processors. * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr @@ -14,38 +14,47 @@ * write to this register. Inform Linux to it too */ -#include -#include -#include #include #include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog - * value from/to milliseconds. + * value from seconds. */ -#define ms_to_ticks(t) (((t << 8) / 1000) - 1) -#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) +#define WDT_SEC2TICKS(s) (((s) << 8) - 1) /* Hardware timeout in seconds */ -#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT) -#define WDT_HW_TIMEOUT 2 -#else -#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT -#endif +#define WDT_MAX_TIMEOUT 16 +#define WDT_MIN_TIMEOUT 0 +#define WDT_DEFAULT_TIMEOUT 2 + +struct at91_wdt_priv { + void __iomem *regs; + u32 regval; + u32 timeout; +}; /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_settimeout(unsigned int timeout) +static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) { - unsigned int reg; - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; + struct at91_wdt_priv *priv = dev_get_priv(dev); + u32 timeout = WDT_SEC2TICKS(timeout_s); + + if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) + timeout = priv->timeout; /* Check if disabled */ - if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { + if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -57,24 +66,71 @@ static int at91_wdt_settimeout(unsigned int timeout) * 4096 / 256 = 16 seconds. */ - reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ + priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ | AT91_WDT_MR_WDV(timeout); /* timer value */ - writel(reg, &wd->mr); + writel(priv->regval, priv->regs + AT91_WDT_MR); return 0; } -void hw_watchdog_reset(void) +static int at91_wdt_stop(struct udevice *dev) { - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; - writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + /* Disable Watchdog Timer */ + priv->regval |= AT91_WDT_MR_WDDIS; + writel(priv->regval, priv->regs + AT91_WDT_MR); + + return 0; } -void hw_watchdog_init(void) +static int at91_wdt_reset(struct udevice *dev) { - /* 16 seconds timer, resets enabled */ - at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR); + + return 0; } + +static const struct wdt_ops at91_wdt_ops = { + .start = at91_wdt_start, + .stop = at91_wdt_stop, + .reset = at91_wdt_reset, +}; + +static const struct udevice_id at91_wdt_ids[] = { + { .compatible = "atmel,at91sam9260-wdt" }, + {} +}; + +static int at91_wdt_probe(struct udevice *dev) +{ + struct at91_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + +#ifdef CONFIG_AT91_HW_WDT_TIMEOUT + priv->timeout = dev_read_u32_default(dev, "timeout-sec", + WDT_DEFAULT_TIMEOUT); + debug("%s: timeout %d", __func__, priv->timeout); +#endif + + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + return 0; +} + +U_BOOT_DRIVER(at91_wdt) = { + .name = "at91_wdt", + .id = UCLASS_WDT, + .of_match = at91_wdt_ids, + .priv_auto_alloc_size = sizeof(struct at91_wdt_priv), + .ops = &at91_wdt_ops, + .probe = at91_wdt_probe, +}; diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d10eb..14cc618074 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,15 +8,20 @@ #include #include #include +#ifdef CONFIG_FSL_LSCH2 +#include +#endif #include #ifdef CONFIG_IMX_WATCHDOG void hw_watchdog_reset(void) { +#ifndef CONFIG_WATCHDOG_RESET_DISABLE struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); +#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/ } void hw_watchdog_init(void) @@ -33,8 +38,12 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +#ifdef CONFIG_FSL_LSCH2 + writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); +#else writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); +#endif /* CONFIG_FSL_LSCH2*/ hw_watchdog_reset(); } #endif diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c index ccb06ac425..c24c2a9da6 100644 --- a/drivers/watchdog/mpc8xx_wdt.c +++ b/drivers/watchdog/mpc8xx_wdt.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -16,3 +18,52 @@ void hw_watchdog_reset(void) out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ } +#ifdef CONFIG_WDT_MPC8xx +static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR); + + if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) + return -EBUSY; + return 0; + +} + +static int mpc8xx_wdt_stop(struct udevice *dev) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); + + if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) + return -EBUSY; + return 0; +} + +static int mpc8xx_wdt_reset(struct udevice *dev) +{ + hw_watchdog_reset(); + + return 0; +} + +static const struct wdt_ops mpc8xx_wdt_ops = { + .start = mpc8xx_wdt_start, + .reset = mpc8xx_wdt_reset, + .stop = mpc8xx_wdt_stop, +}; + +static const struct udevice_id mpc8xx_wdt_ids[] = { + { .compatible = "fsl,pq1-wdt" }, + {} +}; + +U_BOOT_DRIVER(wdt_mpc8xx) = { + .name = "wdt_mpc8xx", + .id = UCLASS_WDT, + .of_match = mpc8xx_wdt_ids, + .ops = &mpc8xx_wdt_ops, +}; +#endif /* CONFIG_WDT_MPC8xx */ diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c new file mode 100644 index 0000000000..38866141e4 --- /dev/null +++ b/drivers/watchdog/mt7621_wdt.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ralink / Mediatek RT288x/RT3xxx/MT76xx built-in hardware watchdog timer + * + * Copyright (C) 2018 Stefan Roese + * + * Based on the Linux driver version which is: + * Copyright (C) 2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mt762x_wdt { + void __iomem *regs; +}; + +#define TIMER_REG_TMRSTAT 0x00 +#define TIMER_REG_TMR1CTL 0x20 +#define TIMER_REG_TMR1LOAD 0x24 + +#define TMR1CTL_ENABLE BIT(7) +#define TMR1CTL_RESTART BIT(9) +#define TMR1CTL_PRESCALE_SHIFT 16 + +static int mt762x_wdt_ping(struct mt762x_wdt *priv) +{ + writel(TMR1CTL_RESTART, priv->regs + TIMER_REG_TMRSTAT); + + return 0; +} + +static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + /* set the prescaler to 1ms == 1000us */ + writel(1000 << TMR1CTL_PRESCALE_SHIFT, priv->regs + TIMER_REG_TMR1CTL); + writel(ms, priv->regs + TIMER_REG_TMR1LOAD); + + setbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE); + + return 0; +} + +static int mt762x_wdt_stop(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + mt762x_wdt_ping(priv); + + clrbits_le32(priv->regs + TIMER_REG_TMR1CTL, TMR1CTL_ENABLE); + + return 0; +} + +static int mt762x_wdt_reset(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + mt762x_wdt_ping(priv); + + return 0; +} + +static int mt762x_wdt_probe(struct udevice *dev) +{ + struct mt762x_wdt *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + + mt762x_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops mt762x_wdt_ops = { + .start = mt762x_wdt_start, + .reset = mt762x_wdt_reset, + .stop = mt762x_wdt_stop, +}; + +static const struct udevice_id mt762x_wdt_ids[] = { + { .compatible = "mediatek,mt7621-wdt" }, + {} +}; + +U_BOOT_DRIVER(mt762x_wdt) = { + .name = "mt762x_wdt", + .id = UCLASS_WDT, + .of_match = mt762x_wdt_ids, + .probe = mt762x_wdt_probe, + .priv_auto_alloc_size = sizeof(struct mt762x_wdt), + .ops = &mt762x_wdt_ops, +}; diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c new file mode 100644 index 0000000000..0b501733f2 --- /dev/null +++ b/drivers/watchdog/mtk_wdt.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Watchdog driver for MediaTek SoCs + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#include +#include +#include +#include + +#define MTK_WDT_MODE 0x00 +#define MTK_WDT_LENGTH 0x04 +#define MTK_WDT_RESTART 0x08 +#define MTK_WDT_STATUS 0x0c +#define MTK_WDT_INTERVAL 0x10 +#define MTK_WDT_SWRST 0x14 +#define MTK_WDT_REQ_MODE 0x30 +#define MTK_WDT_DEBUG_CTL 0x40 + +#define WDT_MODE_KEY (0x22 << 24) +#define WDT_MODE_EN BIT(0) +#define WDT_MODE_EXTPOL BIT(1) +#define WDT_MODE_EXTEN BIT(2) +#define WDT_MODE_IRQ_EN BIT(3) +#define WDT_MODE_DUAL_EN BIT(6) + +#define WDT_LENGTH_KEY 0x8 +#define WDT_LENGTH_TIMEOUT(n) ((n) << 5) + +#define WDT_RESTART_KEY 0x1971 +#define WDT_SWRST_KEY 0x1209 + +struct mtk_wdt_priv { + void __iomem *base; +}; + +static int mtk_wdt_reset(struct udevice *dev) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + /* Reload watchdog duration */ + writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART); + + return 0; +} + +static int mtk_wdt_stop(struct udevice *dev) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY); + + return 0; +} + +static int mtk_wdt_expire_now(struct udevice *dev, ulong flags) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + /* Kick watchdog to prevent counter == 0 */ + writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART); + + /* Reset */ + writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST); + hang(); + + return 0; +} + +static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + /* + * One bit is the value of 512 ticks + * The clock has 32 KHz + */ + timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY; + writel(timeout, priv->base + MTK_WDT_LENGTH); + + mtk_wdt_reset(dev); +} + +static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + mtk_wdt_set_timeout(dev, timeout); + + /* Enable watchdog reset signal */ + setbits_le32(priv->base + MTK_WDT_MODE, + WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN); + + return 0; +} + +static int mtk_wdt_probe(struct udevice *dev) +{ + struct mtk_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + /* Clear status */ + clrsetbits_le32(priv->base + MTK_WDT_MODE, + WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY); + + return mtk_wdt_stop(dev); +} + +static const struct wdt_ops mtk_wdt_ops = { + .start = mtk_wdt_start, + .reset = mtk_wdt_reset, + .stop = mtk_wdt_stop, + .expire_now = mtk_wdt_expire_now, +}; + +static const struct udevice_id mtk_wdt_ids[] = { + { .compatible = "mediatek,wdt"}, + {} +}; + +U_BOOT_DRIVER(mtk_wdt) = { + .name = "mtk_wdt", + .id = UCLASS_WDT, + .of_match = mtk_wdt_ids, + .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv), + .probe = mtk_wdt_probe, + .ops = &mtk_wdt_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/dts/Makefile b/dts/Makefile index 9a9a3d5c98..cd6e9a968e 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -61,4 +61,4 @@ dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb clean-files := dt.dtb.S dt-spl.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts ../arch/riscv/dts diff --git a/env/flash.c b/env/flash.c index 32236c716e..dca6567a09 100644 --- a/env/flash.c +++ b/env/flash.c @@ -44,16 +44,16 @@ DECLARE_GLOBAL_DATA_PTR; #define INITENV #endif +#if defined(CONFIG_ENV_ADDR_REDUND) && defined(CMD_SAVEENV) || \ + !defined(CONFIG_ENV_ADDR_REDUND) && defined(INITENV) #ifdef ENV_IS_EMBEDDED -env_t *env_ptr = &environment; - -static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; - +static env_t *env_ptr = &environment; #else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; -static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; +static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; #endif /* ENV_IS_EMBEDDED */ +#endif +static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; /* CONFIG_ENV_ADDR is supposed to be on sector boundary */ static ulong __maybe_unused end_addr = diff --git a/env/nand.c b/env/nand.c index 3698e68957..29eda66fad 100644 --- a/env/nand.c +++ b/env/nand.c @@ -40,11 +40,9 @@ #endif #if defined(ENV_IS_EMBEDDED) -env_t *env_ptr = &environment; +static env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) -env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; +static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; diff --git a/env/sf.c b/env/sf.c index 2e3c600483..23cbad5d88 100644 --- a/env/sf.c +++ b/env/sf.c @@ -298,10 +298,17 @@ out: } #endif +#ifdef CONFIG_ENV_ADDR +__weak void *env_sf_get_env_addr(void) +{ + return (void *)CONFIG_ENV_ADDR; +} +#endif + #if defined(INITENV) && defined(CONFIG_ENV_ADDR) static int env_sf_init(void) { - env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR); + env_t *env_ptr = (env_t *)env_sf_get_env_addr(); if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data); diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 09364d84a0..f01816f24f 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -45,6 +45,8 @@ endif # source file. ccflags-y += $(call cc-option,-fno-toplevel-reorder) +LDFLAGS_STANDALONE += -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) + ######################################################################### quiet_cmd_link_lib = LD $@ @@ -54,17 +56,17 @@ $(LIB): $(LIBOBJS) FORCE $(call if_changed,link_lib) quiet_cmd_link_elf = LD $@ - cmd_link_elf = $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ + cmd_link_elf = $(LD) $(LDFLAGS) $(LDFLAGS_STANDALONE) -g \ -o $@ -e $(SYM_PREFIX)$(@F) $< $(LIB) $(PLATFORM_LIBGCC) $(ELF): $(obj)/%: $(obj)/%.o $(LIB) FORCE $(call if_changed,link_elf) -$(obj)/%.srec: OBJCOPYFLAGS := -O srec +$(obj)/%.srec: OBJCOPYFLAGS += -O srec $(obj)/%.srec: $(obj)/% FORCE $(call if_changed,objcopy) -$(obj)/%.bin: OBJCOPYFLAGS := -O binary +$(obj)/%.bin: OBJCOPYFLAGS += -O binary $(obj)/%.bin: $(obj)/% FORCE $(call if_changed,objcopy) diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c index 2e14aba390..b7bd243730 100644 --- a/examples/standalone/atmel_df_pow2.c +++ b/examples/standalone/atmel_df_pow2.c @@ -126,8 +126,6 @@ int atmel_df_pow2(int argc, char * const argv[]) return 1; } - spi_init(); - while (1) { struct spi_slave *slave; char *line, *p; diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds deleted file mode 100644 index 163d6efefd..0000000000 --- a/examples/standalone/mips.lds +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -OUTPUT_ARCH(mips) -SECTIONS -{ - .text : - { - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata*) } - - . = ALIGN(4); - __bss_start = .; - .sbss (NOLOAD) : { *(.sbss*) } - .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } - - _end = .; -} diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds deleted file mode 100644 index d67396ab71..0000000000 --- a/examples/standalone/mips64.lds +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips") -OUTPUT_ARCH(mips) -SECTIONS -{ - .text : - { - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = .; - _gp = ALIGN(16) + 0x7ff0; - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - .sdata : { *(.sdata*) } - - . = ALIGN(4); - __bss_start = .; - .sbss (NOLOAD) : { *(.sbss*) } - .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } - - _end = .; -} diff --git a/fs/Makefile b/fs/Makefile index bad0c2cc33..f21cd23f03 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -5,6 +5,7 @@ # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_FS_LOADER) += fs.o obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/ obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/ else diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c index 0dce639b49..7b2513cb24 100644 --- a/fs/cbfs/cbfs.c +++ b/fs/cbfs/cbfs.c @@ -96,8 +96,7 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32 align, } swap_file_header(&header, fileHeader); - if (header.offset < sizeof(struct cbfs_fileheader) || - header.offset > header.len) { + if (header.offset < sizeof(struct cbfs_fileheader)) { file_cbfs_result = CBFS_BAD_FILE; return -1; } @@ -190,8 +189,8 @@ void file_cbfs_init(uintptr_t end_of_rom) start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size); - file_cbfs_fill_cache(start_of_rom + cbfs_header.offset, - cbfs_header.rom_size, cbfs_header.align); + file_cbfs_fill_cache(start_of_rom, cbfs_header.rom_size, + cbfs_header.align); if (file_cbfs_result == CBFS_SUCCESS) initialized = 1; } diff --git a/fs/fat/fat.c b/fs/fat/fat.c index b08949d370..ac8913e719 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -571,6 +571,17 @@ static int get_fs_info(fsdata *mydata) mydata->sect_size, cur_part_info.blksz); return -1; } + if (mydata->clust_size == 0) { + printf("Error: FAT cluster size not set\n"); + return -1; + } + if ((unsigned int)mydata->clust_size * mydata->sect_size > + MAX_CLUSTSIZE) { + printf("Error: FAT cluster size too big (cs=%u, max=%u)\n", + (unsigned int)mydata->clust_size * mydata->sect_size, + MAX_CLUSTSIZE); + return -1; + } if (mydata->fatsize == 32) { mydata->data_begin = mydata->rootdir_sect - @@ -725,7 +736,10 @@ static void *next_cluster(fat_itr *itr) if (itr->last_cluster) return NULL; - sect = clust_to_sect(itr->fsdata, itr->next_clust); + if (itr->fsdata->fatsize != 32 && itr->is_root) + sect = mydata->rootdir_sect; + else + sect = clust_to_sect(itr->fsdata, itr->next_clust); debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n", sect, itr->fsdata->clust_size, DIRENTSPERBLOCK); @@ -807,6 +821,9 @@ static dir_entry *extract_vfat_name(fat_itr *itr) slot2str((dir_slot *)dent, buf, &idx); + if (n + idx >= sizeof(itr->l_name)) + return NULL; + /* shift accumulated long-name up and copy new part in: */ memmove(itr->l_name + idx, itr->l_name, n); memcpy(itr->l_name, buf, idx); diff --git a/fs/fs.c b/fs/fs.c index adae98d021..cb265174e2 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -365,6 +365,7 @@ int fs_set_blk_dev_with_part(struct blk_desc *desc, int part) for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes); i++, info++) { if (!info->probe(fs_dev_desc, &fs_partition)) { fs_type = info->fstype; + fs_dev_part = part; return 0; } } diff --git a/include/_exports.h b/include/_exports.h index 5416041243..c15050e30b 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -50,11 +50,9 @@ #endif #if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI) - EXPORT_FUNC(dummy, void, spi_init, void) EXPORT_FUNC(dummy, void, spi_setup_slave, void) EXPORT_FUNC(dummy, void, spi_free_slave, void) #else - EXPORT_FUNC(spi_init, void, spi_init, void) EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave, unsigned int, unsigned int, unsigned int, unsigned int) EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *) diff --git a/include/adc.h b/include/adc.h index d04c9c4926..5841dfb54b 100644 --- a/include/adc.h +++ b/include/adc.h @@ -218,6 +218,17 @@ int adc_channels_data(struct udevice *dev, unsigned int channel_mask, */ int adc_data_mask(struct udevice *dev, unsigned int *data_mask); +/** + * adc_channel_mask() - get channel mask for given ADC device + * + * This can be used if adc uclass platform data is filled. + * + * @dev: ADC device to check + * @channel_mask: pointer to the returned channel bitmask + * @return: 0 if OK, -ve on error + */ +int adc_channel_mask(struct udevice *dev, unsigned int *channel_mask); + /** * adc_channel_single_shot() - get output data of conversion for the ADC * device's channel. This function searches for the device with the given name, @@ -284,4 +295,14 @@ int adc_vss_value(struct udevice *dev, int *uV); */ int adc_stop(struct udevice *dev); +/** + * adc_raw_to_uV() - converts raw value to microvolts for given ADC device. + * + * @dev: ADC device used from conversion + * @raw: raw value to convert + * @uV: converted value in microvolts + * @return: 0 on success or -ve on error + */ +int adc_raw_to_uV(struct udevice *dev, unsigned int raw, int *uV); + #endif diff --git a/include/altera.h b/include/altera.h index ead5d3d810..22d55cfd73 100644 --- a/include/altera.h +++ b/include/altera.h @@ -39,6 +39,8 @@ enum altera_iface { fast_passive_parallel, /* fast passive parallel with security (FPPS) */ fast_passive_parallel_security, + /* secure device manager (SDM) mailbox */ + secure_device_manager_mailbox, /* insert all new types before this */ max_altera_iface_type, }; @@ -54,6 +56,8 @@ enum altera_family { Altera_StratixII, /* StratixV Family */ Altera_StratixV, + /* Stratix10 Family */ + Intel_FPGA_Stratix10, /* SoCFPGA Family */ Altera_SoCFPGA, @@ -116,4 +120,8 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); #endif +#ifdef CONFIG_FPGA_STRATIX10 +int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + #endif /* _ALTERA_H_ */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index c83fc01b76..78dcf40bff 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -77,6 +77,10 @@ typedef struct global_data { #ifdef CONFIG_OF_LIVE struct device_node *of_root; #endif + +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) + const void *multi_dtb_fit; /* uncompressed multi-dtb FIT image */ +#endif struct jt_funcs *jt; /* jump table */ char env_buf[32]; /* buffer for env_get() before reloc. */ #ifdef CONFIG_TRACE @@ -122,6 +126,13 @@ typedef struct global_data { struct list_head log_head; /* List of struct log_device */ int log_fmt; /* Mask containing log format info */ #endif +#if CONFIG_IS_ENABLED(BLOBLIST) + struct bloblist_hdr *bloblist; /* Bloblist information */ + struct bloblist_hdr *new_bloblist; /* Relocated blolist info */ +# ifdef CONFIG_SPL + struct spl_handoff *spl_handoff; +# endif +#endif } gd_t; #endif diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h index 9a8b5e82e3..faae534e37 100644 --- a/include/asm-generic/pe.h +++ b/include/asm-generic/pe.h @@ -11,6 +11,24 @@ #ifndef _ASM_PE_H #define _ASM_PE_H +/* Characteristics */ +#define IMAGE_FILE_RELOCS_STRIPPED 0x0001 +#define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 +#define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 +#define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +/* Reserved 0x0040 */ +#define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 +#define IMAGE_FILE_32BIT_MACHINE 0x0100 +#define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 +#define IMAGE_FILE_NET_RUN_FROM_SWAP 0x0800 +#define IMAGE_FILE_SYSTEM 0x1000 +#define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 +#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 + /* Subsystem type */ #define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 #define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 diff --git a/include/audio_codec.h b/include/audio_codec.h new file mode 100644 index 0000000000..2587099546 --- /dev/null +++ b/include/audio_codec.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#ifndef __AUDIO_CODEC_H__ +#define __AUDIO_CODEC_H__ + +/* + * An audio codec turns digital data into sound with various parameters to + * control its operation. + */ + +/* Operations for sound */ +struct audio_codec_ops { + /** + * set_params() - Set audio codec parameters + * + * @dev: Sound device + * @inteface: Interface number to use on codec + * @rate: Sampling rate in Hz + * @mclk_freq: Codec clock frequency in Hz + * @bits_per_sample: Must be 16 or 24 + * @channels: Number of channels to use (1=mono, 2=stereo) + * @return 0 if OK, -ve on error + */ + int (*set_params)(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels); +}; + +#define audio_codec_get_ops(dev) ((struct audio_codec_ops *)(dev)->driver->ops) + +/** + * audio_codec_set_params() - Set audio codec parameters + * + * @dev: Sound device + * @inteface: Interface number to use on codec + * @rate: Sampling rate in Hz + * @mclk_freq: Codec clock frequency in Hz + * @bits_per_sample: Must be 16 or 24 + * @channels: Number of channels to use (1=mono, 2=stereo) + * @return 0 if OK, -ve on error + */ +int audio_codec_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, uint channels); + +#endif /* __AUDIO_CODEC_H__ */ diff --git a/include/axp209.h b/include/axp209.h index b7de6ed73c..f4f1b2fe56 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -3,11 +3,14 @@ * (C) Copyright 2012 Henrik Nordstrom */ +#include + enum axp209_reg { AXP209_POWER_STATUS = 0x00, AXP209_CHIP_VERSION = 0x03, AXP209_OUTPUT_CTRL = 0x12, AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_VRC_DCDC2_LDO3 = 0x25, AXP209_DCDC3_VOLTAGE = 0x27, AXP209_LDO24_VOLTAGE = 0x28, AXP209_LDO3_VOLTAGE = 0x29, @@ -20,29 +23,64 @@ enum axp209_reg { AXP209_SHUTDOWN = 0x32, }; -#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) -#define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4) +#define AXP209_POWER_STATUS_ON_BY_DC BIT(0) +#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4) -#define AXP209_OUTPUT_CTRL_EXTEN (1 << 0) -#define AXP209_OUTPUT_CTRL_DCDC3 (1 << 1) -#define AXP209_OUTPUT_CTRL_LDO2 (1 << 2) -#define AXP209_OUTPUT_CTRL_LDO4 (1 << 3) -#define AXP209_OUTPUT_CTRL_DCDC2 (1 << 4) -#define AXP209_OUTPUT_CTRL_LDO3 (1 << 6) +#define AXP209_CHIP_VERSION_MASK 0x0f -#define AXP209_IRQ5_PEK_UP (1 << 6) -#define AXP209_IRQ5_PEK_DOWN (1 << 5) +#define AXP209_OUTPUT_CTRL_EXTEN BIT(0) +#define AXP209_OUTPUT_CTRL_DCDC3 BIT(1) +#define AXP209_OUTPUT_CTRL_LDO2 BIT(2) +#define AXP209_OUTPUT_CTRL_LDO4 BIT(3) +#define AXP209_OUTPUT_CTRL_DCDC2 BIT(4) +#define AXP209_OUTPUT_CTRL_LDO3 BIT(6) -#define AXP209_POWEROFF (1 << 7) +/* + * AXP209 datasheet contains wrong information about LDO3 VRC: + * - VRC is actually enabled when BIT(1) is True + * - VRC is actually not enabled by default (BIT(3) = 0 after reset) + */ +#define AXP209_VRC_LDO3_EN BIT(3) +#define AXP209_VRC_DCDC2_EN BIT(2) +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN) +#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN +#define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN) +#define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN +#define AXP209_VRC_LDO3_MASK 0xa +#define AXP209_VRC_DCDC2_MASK 0x5 +#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_DCDC2_MASK) | \ + ((cfg) & AXP209_VRC_DCDC2_MASK)) +#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \ + (((reg) & ~AXP209_VRC_LDO3_MASK) | \ + ((cfg) & AXP209_VRC_LDO3_MASK)) + +#define AXP209_LDO24_LDO2_MASK 0xf0 +#define AXP209_LDO24_LDO4_MASK 0x0f +#define AXP209_LDO24_LDO2_SET(reg, cfg) \ + (((reg) & ~AXP209_LDO24_LDO2_MASK) | \ + (((cfg) << 4) & AXP209_LDO24_LDO2_MASK)) +#define AXP209_LDO24_LDO4_SET(reg, cfg) \ + (((reg) & ~AXP209_LDO24_LDO4_MASK) | \ + (((cfg) << 0) & AXP209_LDO24_LDO4_MASK)) + +#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN BIT(7) +#define AXP209_LDO3_VOLTAGE_MASK 0x7f +#define AXP209_LDO3_VOLTAGE_SET(x) ((x) & AXP209_LDO3_VOLTAGE_MASK) + +#define AXP209_IRQ5_PEK_UP BIT(6) +#define AXP209_IRQ5_PEK_DOWN BIT(5) + +#define AXP209_POWEROFF BIT(7) /* For axp_gpio.c */ #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO2_CTRL 0x93 -#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ -#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ -#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ +#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ +#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ +#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ #define AXP_GPIO_STATE 0x94 -#define AXP_GPIO_STATE_OFFSET 4 +#define AXP_GPIO_STATE_OFFSET 4 diff --git a/include/blk.h b/include/blk.h index 6af219681c..d0c033aece 100644 --- a/include/blk.h +++ b/include/blk.h @@ -33,6 +33,7 @@ enum if_type { IF_TYPE_HOST, IF_TYPE_NVME, IF_TYPE_EFI, + IF_TYPE_VIRTIO, IF_TYPE_COUNT, /* Number of interface types */ }; @@ -356,16 +357,6 @@ int blk_create_devicef(struct udevice *parent, const char *drv_name, const char *name, int if_type, int devnum, int blksz, lbaint_t lba, struct udevice **devp); -/** - * blk_prepare_device() - Prepare a block device for use - * - * This reads partition information from the device if supported. - * - * @dev: Device to prepare - * @return 0 if ok, -ve on error - */ -int blk_prepare_device(struct udevice *dev); - /** * blk_unbind_all() - Unbind all device of the given interface type * @@ -388,6 +379,17 @@ int blk_unbind_all(int if_type); */ int blk_find_max_devnum(enum if_type if_type); +/** + * blk_next_free_devnum() - get the next device number for an interface type + * + * Finds the next number that is safe to use for a newly allocated device for + * an interface type @if_type. + * + * @if_type: Interface type to scan + * @return next device number safe to use, or -ve on error + */ +int blk_next_free_devnum(enum if_type if_type); + /** * blk_select_hwpart() - select a hardware partition * diff --git a/include/bloblist.h b/include/bloblist.h new file mode 100644 index 0000000000..85144010ab --- /dev/null +++ b/include/bloblist.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This provides a standard way of passing information between boot phases + * (TPL -> SPL -> U-Boot proper.) + * + * A list of blobs of data, tagged with their owner. The list resides in memory + * and can be updated by SPL, U-Boot, etc. + * + * Copyright 2018 Google, Inc + * Written by Simon Glass + */ + +#ifndef __BLOBLIST_H +#define __BLOBLIST_H + +enum { + BLOBLIST_VERSION = 0, + BLOBLIST_MAGIC = 0xb00757a3, + BLOBLIST_ALIGN = 16, +}; + +enum bloblist_tag_t { + BLOBLISTT_NONE = 0, + + /* Vendor-specific tags are permitted here */ + BLOBLISTT_EC_HOSTEVENT, /* Chromium OS EC host-event mask */ + BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */ + BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ + BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ +}; + +/** + * struct bloblist_hdr - header for the bloblist + * + * This is stored at the start of the bloblist which is always on a 16-byte + * boundary. Records follow this header. The bloblist normally stays in the + * same place in memory as SPL and U-Boot execute, but it can be safely moved + * around. + * + * None of the bloblist structures contain pointers but it is possible to put + * pointers inside a bloblist record if desired. This is not encouraged, + * since it can make part of the bloblist inaccessible if the pointer is + * no-longer valid. It is better to just store all the data inside a bloblist + * record. + * + * Each bloblist record is aligned to a 16-byte boundary and follows immediately + * from the last. + * + * @version: BLOBLIST_VERSION + * @hdr_size: Size of this header, normally sizeof(struct bloblist_hdr). The + * first bloblist_rec starts at this offset from the start of the header + * @flags: Space for BLOBLISTF_... flags (none yet) + * @magic: BLOBLIST_MAGIC + * @size: Total size of all records (non-zero if valid) including this header. + * The bloblist extends for this many bytes from the start of this header. + * @alloced: Total size allocated for this bloblist. When adding new records, + * the bloblist can grow up to this size. This starts out as + * sizeof(bloblist_hdr) since we need at least that much space to store a + * valid bloblist + * @spare: Space space + * @chksum: CRC32 for the entire bloblist allocated area. Since any of the + * blobs can be altered after being created, this checksum is only valid + * when the bloblist is finalised before jumping to the next stage of boot. + * Note: @chksum is last to make it easier to exclude it from the checksum + * calculation. + */ +struct bloblist_hdr { + u32 version; + u32 hdr_size; + u32 flags; + u32 magic; + + u32 size; + u32 alloced; + u32 spare; + u32 chksum; +}; + +/** + * struct bloblist_rec - record for the bloblist + * + * NOTE: Only exported for testing purposes. Do not use this struct. + * + * The bloblist contains a number of records each consisting of this record + * structure followed by the data contained. Each records is 16-byte aligned. + * + * @tag: Tag indicating what the record contains + * @hdr_size: Size of this header, normally sizeof(struct bloblist_rec). The + * record's data starts at this offset from the start of the record + * @size: Size of record in bytes, excluding the header size. This does not + * need to be aligned (e.g. 3 is OK). + * @spare: Spare space for other things + */ +struct bloblist_rec { + u32 tag; + u32 hdr_size; + u32 size; + u32 spare; +}; + +/** + * bloblist_find() - Find a blob + * + * Searches the bloblist and returns the blob with the matching tag + * + * @tag: Tag to search for (enum bloblist_tag_t) + * @size: Expected size of the blob + * @return pointer to blob if found, or NULL if not found, or a blob was found + * but it is the wrong size + */ +void *bloblist_find(uint tag, int size); + +/** + * bloblist_add() - Add a new blob + * + * Add a new blob to the bloblist + * + * This should only be called if you konw there is no existing blob for a + * particular tag. It is typically safe to call in the first phase of U-Boot + * (e.g. TPL or SPL). After that, bloblist_ensure() should be used instead. + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @return pointer to the newly added block, or NULL if there is not enough + * space for the blob + */ +void *bloblist_add(uint tag, int size); + +/** + * bloblist_ensure_size() - Find or add a blob + * + * Find an existing blob, or add a new one if not found + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @blobp: Returns a pointer to blob on success + * @return 0 if OK, -ENOSPC if it is missing and could not be added due to lack + * of space, or -ESPIPE it exists but has the wrong size + */ +int bloblist_ensure_size(uint tag, int size, void **blobp); + +/** + * bloblist_ensure() - Find or add a blob + * + * Find an existing blob, or add a new one if not found + * + * @tag: Tag to add (enum bloblist_tag_t) + * @size: Size of the blob + * @return pointer to blob, or NULL if it is missing and could not be added due + * to lack of space, or it exists but has the wrong size + */ +void *bloblist_ensure(uint tag, int size); + +/** + * bloblist_new() - Create a new, empty bloblist of a given size + * + * @addr: Address of bloblist + * @size: Initial size for bloblist + * @flags: Flags to use for bloblist + * @return 0 if OK, -EFAULT if addr is not aligned correctly, -ENOSPC is the + * area is not large enough + */ +int bloblist_new(ulong addr, uint size, uint flags); + +/** + * bloblist_check() - Check if a bloblist exists + * + * @addr: Address of bloblist + * @size: Expected size of blobsize, or 0 to detect the size + * @return 0 if OK, -ENOENT if the magic number doesn't match (indicating that + * there problem is no bloblist at the given address), -EPROTONOSUPPORT + * if the version does not match, -EIO if the checksum does not match, + * -EFBIG if the expected size does not match the detected size + */ +int bloblist_check(ulong addr, uint size); + +/** + * bloblist_finish() - Set up the bloblist for the next U-Boot part + * + * This sets the correct checksum for the bloblist. This ensures that the + * bloblist will be detected correctly by the next phase of U-Boot. + * + * @return 0 + */ +int bloblist_finish(void); + +/** + * bloblist_init() - Init the bloblist system with a single bloblist + * + * This uses CONFIG_BLOBLIST_ADDR and CONFIG_BLOBLIST_SIZE to set up a bloblist + * for use by U-Boot. + */ +int bloblist_init(void); + +#endif /* __BLOBLIST_H */ diff --git a/include/bootcount.h b/include/bootcount.h index 671adcc410..daee84316c 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -10,6 +10,54 @@ #include #include +#ifdef CONFIG_DM_BOOTCOUNT + +struct bootcount_ops { + /** + * get() - get the current bootcount value + * + * Returns the current counter value of the bootcount backing + * store. + * + * @dev: Device to read from + * @bootcount: Address to put the current bootcount value + */ + int (*get)(struct udevice *dev, u32 *bootcount); + + /** + * set() - set a bootcount value (e.g. to reset or increment) + * + * Sets the value in the bootcount backing store. + * + * @dev: Device to read from + * @bootcount: New bootcount value to store + */ + int (*set)(struct udevice *dev, const u32 bootcount); +}; + +/* Access the operations for a bootcount device */ +#define bootcount_get_ops(dev) ((struct bootcount_ops *)(dev)->driver->ops) + +/** + * dm_bootcount_get() - Read the current value from a bootcount storage + * + * @dev: Device to read from + * @bootcount: Place to put the current bootcount + * @return 0 if OK, -ve on error + */ +int dm_bootcount_get(struct udevice *dev, u32 *bootcount); + +/** + * dm_bootcount_set() - Write a value to a bootcount storage + * + * @dev: Device to read from + * @bootcount: Value to be written to the backing storage + * @return 0 if OK, -ve on error + */ +int dm_bootcount_set(struct udevice *dev, u32 bootcount); + +#endif + #if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT) #if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE) diff --git a/include/bootm.h b/include/bootm.h index 0501414e0d..dbd6f49c2d 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -35,6 +35,8 @@ typedef int boot_os_fn(int flag, int argc, char * const argv[], bootm_headers_t *images); extern boot_os_fn do_bootm_linux; +extern boot_os_fn do_bootm_vxworks; + int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); void lynxkdi_boot(image_header_t *hdr); diff --git a/include/cbfs.h b/include/cbfs.h index 1b88ec04ae..bd1bf75bbf 100644 --- a/include/cbfs.h +++ b/include/cbfs.h @@ -18,16 +18,26 @@ enum cbfs_result { }; enum cbfs_filetype { + CBFS_TYPE_BOOTBLOCK = 0x01, + CBFS_TYPE_CBFSHEADER = 0x02, CBFS_TYPE_STAGE = 0x10, CBFS_TYPE_PAYLOAD = 0x20, + CBFS_TYPE_FIT = 0x21, CBFS_TYPE_OPTIONROM = 0x30, CBFS_TYPE_BOOTSPLASH = 0x40, CBFS_TYPE_RAW = 0x50, CBFS_TYPE_VSA = 0x51, CBFS_TYPE_MBI = 0x52, CBFS_TYPE_MICROCODE = 0x53, - CBFS_COMPONENT_CMOS_DEFAULT = 0xaa, - CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa + CBFS_TYPE_FSP = 0x60, + CBFS_TYPE_MRC = 0x61, + CBFS_TYPE_MMA = 0x62, + CBFS_TYPE_EFI = 0x63, + CBFS_TYPE_STRUCT = 0x70, + CBFS_TYPE_CMOS_DEFAULT = 0xaa, + CBFS_TYPE_SPD = 0xab, + CBFS_TYPE_MRC_CACHE = 0xac, + CBFS_TYPE_CMOS_LAYOUT = 0x01aa }; struct cbfs_header { diff --git a/include/common.h b/include/common.h index 8b9f859c07..657cc404cf 100644 --- a/include/common.h +++ b/include/common.h @@ -14,9 +14,6 @@ typedef volatile unsigned long vu_long; typedef volatile unsigned short vu_short; typedef volatile unsigned char vu_char; -/* Allow sharing constants with type modifiers between C and assembly. */ -#define _AC(X, Y) (X##Y) - #include #include #include @@ -108,6 +105,17 @@ int mdm_init(void); */ void board_show_dram(phys_size_t size); +/** + * Get the uppermost pointer that is valid to access + * + * Some systems may not map all of their address space. This function allows + * boards to indicate what their highest support pointer value is for DRAM + * access. + * + * @param total_size Size of U-Boot (unused?) + */ +ulong board_get_usable_ram_top(ulong total_size); + /** * arch_fixup_fdt() - Write arch-specific information to fdt * @@ -279,13 +287,6 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned c # define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR #endif -#if defined(CONFIG_MPC8XX_SPI) -extern void spi_init_f (void); -extern void spi_init_r (void); -extern ssize_t spi_read (uchar *, int, uchar *, int); -extern ssize_t spi_write (uchar *, int, uchar *, int); -#endif - /* $(BOARD)/$(BOARD).c */ int board_early_init_f (void); int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */ @@ -349,6 +350,8 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr); void smp_kick_all_cpus(void); /* $(CPU)/serial.c */ +struct serial_device_info; + int serial_init (void); void serial_setbrg (void); void serial_putc (const char); @@ -356,7 +359,9 @@ void serial_putc_raw(const char); void serial_puts (const char *); int serial_getc (void); int serial_tstc (void); +int serial_getconfig(uint *config); int serial_setconfig(uint config); +int serial_getinfo(struct serial_device_info *info); /* $(CPU)/speed.c */ int get_clocks (void); @@ -541,16 +546,10 @@ int cpu_release(u32 nr, int argc, char * const argv[]); #else /* __ASSEMBLY__ */ -/* Drop a C type modifier (like in 3UL) for constants used in assembly. */ -#define _AC(X, Y) X - #endif /* __ASSEMBLY__ */ /* Put only stuff here that the assembler can digest */ -/* Declare an unsigned long constant digestable both by C and an assembler. */ -#define UL(x) _AC(x, UL) - #ifdef CONFIG_POST #define CONFIG_HAS_POST #ifndef CONFIG_POST_ALT_LIST @@ -558,11 +557,6 @@ int cpu_release(u32 nr, int argc, char * const argv[]); #endif #endif -#ifdef CONFIG_INIT_CRITICAL -#error CONFIG_INIT_CRITICAL is deprecated! -#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. -#endif - #define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1)) /* diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 373fee78a9..555efb7433 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -99,9 +99,9 @@ #define BOOTEFI_NAME "bootia32.efi" #elif defined(CONFIG_X86_RUN_64BIT) #define BOOTEFI_NAME "bootx64.efi" -#elif defined(CONFIG_CPU_RISCV_32) +#elif defined(CONFIG_ARCH_RV32I) #define BOOTEFI_NAME "bootriscv32.efi" -#elif defined(CONFIG_CPU_RISCV_64) +#elif defined(CONFIG_ARCH_RV64I) #define BOOTEFI_NAME "bootriscv64.efi" #endif #endif @@ -242,6 +242,18 @@ BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB #endif +#ifdef CONFIG_CMD_VIRTIO +#define BOOTENV_SHARED_VIRTIO BOOTENV_SHARED_BLKDEV(virtio) +#define BOOTENV_DEV_VIRTIO BOOTENV_DEV_BLKDEV +#define BOOTENV_DEV_NAME_VIRTIO BOOTENV_DEV_NAME_BLKDEV +#else +#define BOOTENV_SHARED_VIRTIO +#define BOOTENV_DEV_VIRTIO \ + BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO +#define BOOTENV_DEV_NAME_VIRTIO \ + BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO +#endif + #if defined(CONFIG_CMD_DHCP) #if defined(CONFIG_EFI_LOADER) /* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */ @@ -257,10 +269,10 @@ #elif defined(__i386__) #define BOOTENV_EFI_PXE_ARCH "0x6" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32)) +#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32)) #define BOOTENV_EFI_PXE_ARCH "0x19" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64)) +#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64)) #define BOOTENV_EFI_PXE_ARCH "0x1b" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000" #elif defined(CONFIG_SANDBOX) @@ -350,20 +362,22 @@ BOOTENV_SHARED_IDE \ BOOTENV_SHARED_UBIFS \ BOOTENV_SHARED_EFI \ + BOOTENV_SHARED_VIRTIO \ "boot_prefixes=/ /boot/\0" \ "boot_scripts=boot.scr.uimg boot.scr\0" \ "boot_script_dhcp=boot.scr.uimg\0" \ BOOTENV_BOOT_TARGETS \ \ + "boot_syslinux_conf=extlinux/extlinux.conf\0" \ "boot_extlinux=" \ "sysboot ${devtype} ${devnum}:${distro_bootpart} any " \ - "${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \ + "${scriptaddr} ${prefix}${boot_syslinux_conf}\0" \ \ "scan_dev_for_extlinux=" \ "if test -e ${devtype} " \ "${devnum}:${distro_bootpart} " \ - "${prefix}extlinux/extlinux.conf; then " \ - "echo Found ${prefix}extlinux/extlinux.conf; " \ + "${prefix}${boot_syslinux_conf}; then " \ + "echo Found ${prefix}${boot_syslinux_conf}; " \ "run boot_extlinux; " \ "echo SCRIPT FAILED: continuing...; " \ "fi\0" \ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index f758ea7dbe..252e1272c3 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -276,7 +276,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 11cb3955da..83d774527a 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -102,7 +102,6 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI -#define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI # define CONFIG_SYS_DSPI_CS2 diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index f08896ef0a..4b8ef38c0b 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -151,7 +151,6 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI #define CONFIG_SERIAL_FLASH -#define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 16becbdbed..87cdbae1db 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -116,7 +116,6 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI #define CONFIG_SERIAL_FLASH -#define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 99b60d5d82..d41b7c4492 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -142,7 +142,6 @@ /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI -#define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 524a10fc95..86a1233e32 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -370,11 +370,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI - #if defined(CONFIG_SPI_FLASH) #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index c9ed70ca4c..eeb19a9fa6 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -386,12 +386,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 -/* - * eSPI - Enhanced SPI - */ - -#define CONFIG_HARD_SPI - #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 42bfd07f58..f3b0fe0144 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -290,7 +290,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d90797b08..2d5c96f335 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -215,7 +215,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 833a0608bf..1dcf2779d7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -266,7 +266,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 34b3b056ec..06939015d0 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -191,7 +191,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index f5eed0923f..42252c7c42 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -460,7 +460,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 423ecd71c2..1bbe9d9b37 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -287,11 +287,6 @@ #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C #define CONFIG_SYS_I2C_IDT6V49205B 0x69 -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI - #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/alt.h b/include/configs/alt.h index cc6a7bf638..3f7f379e06 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -39,8 +39,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5d5b09bbd1..3bd96b921b 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -253,7 +253,6 @@ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC #undef CONFIG_TIMER -#undef CONFIG_DM_USB #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 0463e42048..eb50012ff7 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -12,16 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #include #undef CONFIG_DM_I2C_COMPAT @@ -98,7 +88,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ + "console=ttyS2,115200n8\0" \ "fdtfile=am3517-evm.dtb\0" \ "fdtaddr=0x82C00000\0" \ "vram=16M\0" \ @@ -176,8 +166,6 @@ /* Physical Memory Map */ #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 /* FLASH and environment organization */ @@ -203,10 +191,6 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 -#undef CONFIG_SPL_BSS_START_ADDR -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 9d0d342478..ed71f4ce56 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -27,8 +27,10 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Power */ +#ifndef CONFIG_DM_I2C #define CONFIG_POWER #define CONFIG_POWER_I2C +#endif #define CONFIG_POWER_TPS65218 #define CONFIG_POWER_TPS62362 diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 65015df131..31749c6d06 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -21,9 +21,17 @@ /* SPL Loader Configuration */ #ifdef CONFIG_TARGET_AM654_A53_EVM #define CONFIG_SPL_TEXT_BASE 0x80080000 +#else +#define CONFIG_SPL_TEXT_BASE 0x41c00000 #endif +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#ifndef CONFIG_CPU_V7R #define CONFIG_SKIP_LOWLEVEL_INIT +#endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 006b049d09..ccbdc0a335 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -34,15 +34,8 @@ /* FIT support */ #define CONFIG_SYS_BOOTM_LEN SZ_64M -/* UBI Support */ - -/* I2C configuration */ - #ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000 -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif + #define NANDARGS \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ @@ -264,10 +257,6 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_OTG -/* Network. */ -#define CONFIG_PHY_SMSC -#define CONFIG_PHY_ATHEROS - /* NAND support */ #ifdef CONFIG_NAND #define GPMC_NAND_ECC_LP_x8_LAYOUT 1 diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 39ca2e0bf3..788f4af70d 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -6,6 +6,10 @@ #ifndef __CONFIG_BMIPS_COMMON_H #define __CONFIG_BMIPS_COMMON_H +/* ETH */ +#define CONFIG_PHY_RESET_DELAY 20 +#define CONFIG_SYS_RX_ETH_BUFFER 6 + /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } @@ -16,7 +20,7 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h new file mode 100644 index 0000000000..1c0945e140 --- /dev/null +++ b/include/configs/broadcom_bcm968580xref.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* + * 6858 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * 968580xref + */ + +#define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/ci20.h b/include/configs/ci20.h new file mode 100644 index 0000000000..9a3621329d --- /dev/null +++ b/include/configs/ci20.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * CI20 configuration + * + * Copyright (c) 2013 Imagination Technologies + * Author: Paul Burton + */ + +#ifndef __CONFIG_CI20_H__ +#define __CONFIG_CI20_H__ + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Ingenic JZ4780 clock configuration. */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 1200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Memory configuration */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x88000000 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* NS16550-ish UARTs */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Ethernet: davicom DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0xb6000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + +/* Environment */ +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE (32 << 10) +#define CONFIG_ENV_OFFSET ((14 + 512) << 10) +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ + +/* Miscellaneous configuration options */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +/* SPL */ +#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ + +#define CONFIG_SPL_TEXT_BASE 0xf4000a00 +#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) + +#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ + +#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */ + +#endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 4adcd956ef..1908d35bcc 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -182,10 +182,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #ifndef CONFIG_TRAILBLAZER -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index ba878eb13b..14a3046f19 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -124,8 +124,9 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #endif +#define CONFIG_ENV_SPI_MAX_HZ 0 +#define CONFIG_ENV_SPI_MODE 0 #ifdef CONFIG_USE_SPIFLASH #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 2f1ffa2754..e68246cc0f 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -10,11 +10,6 @@ * High Level Configuration Options (easy to change) */ -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index f2aa21a43e..3900cbed2d 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -10,11 +10,6 @@ * High Level Configuration Options (easy to change) */ -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 1c94bf9fa1..f4d717213c 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -35,7 +35,6 @@ #endif #ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index c06f0058de..2c7928e88c 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -38,7 +38,6 @@ #endif #ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ diff --git a/include/configs/edison.h b/include/configs/edison.h index 86c584d73d..a6155ba5a8 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -8,13 +8,6 @@ #include -/* ACPI */ - -/* Boot */ -#define CONFIG_BOOTCOMMAND "run bootcmd" - -/* DISK Partition support */ - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 2048 @@ -43,9 +36,6 @@ #define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) #define CONFIG_SUPPORT_EMMC_BOOT -/* PCI */ -#define CONFIG_CMD_PCI - /* RTC */ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 89aa11c0ed..645fc3ffb8 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -29,7 +29,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ #define CONFIG_88F5182 1 /* SOC Name */ diff --git a/include/configs/elgin_rv1108.h b/include/configs/elgin_rv1108.h new file mode 100644 index 0000000000..aa6c4b09e2 --- /dev/null +++ b/include/configs/elgin_rv1108.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 71217f07e2..7e7de4dae6 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -109,6 +109,19 @@ #include "mx6_common.h" +#ifdef CONFIG_SPL +#include "imx6_spl.h" +/* RiOTboard */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb" + +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */ + +#endif + /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 385d59e338..9a205edc7c 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CONFIG_SYS_SDRAM_SIZE SZ_16M #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h index 34739c7474..b742d98706 100644 --- a/include/configs/evb_rv1108.h +++ b/include/configs/evb_rv1108.h @@ -11,11 +11,14 @@ /* * Default environment settings */ +#undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ipaddr=172.16.12.50\0" \ "serverip=172.16.12.69\0" \ "" + +#undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND \ "sf probe;" \ "sf read 0x62000000 0x140800 0x500000;" \ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 0184147068..b10857a757 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -30,7 +30,7 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 @@ -38,7 +38,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Environment settings */ -#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_OFFSET 0xa0000 #define CONFIG_ENV_SIZE (64 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/gose.h b/include/configs/gose.h index 36ac88a20d..8f0e378488 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/helios4.h b/include/configs/helios4.h index ce912ea324..4e98f19a40 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_HELIOS4_H #define _CONFIG_HELIOS4_H +#include + /* * High Level Configuration Options (easy to change) */ @@ -23,6 +25,9 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 104000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 /* * SDIO/MMC Card Configuration @@ -43,28 +48,33 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI +/* + * SPI Flash configuration for the environment access + */ +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_SECT_SIZE SZ_64K +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_OFFSET SZ_1M +#endif + +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC /* Environment in MMC */ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SECT_SIZE 0x200 -#define CONFIG_ENV_SIZE 0x10000 -/* - * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC - * boot image starts @ LBA-0. - * As result in MMC/eMMC case it will be a 1 sector gap between u-boot - * image and environment - */ -#define CONFIG_ENV_OFFSET 0xf0000 +#define CONFIG_ENV_SIZE 0x2000 +/* stay within first 1M */ +#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET +#endif #define CONFIG_PHY_MARVELL /* there is a marvell phy */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_MVEBU -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ @@ -80,7 +90,13 @@ */ #define SPL_BOOT_SPI_NOR_FLASH 1 #define SPL_BOOT_SDIO_MMC_CARD 2 + +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI +#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH +#endif +#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD +#endif /* Defines for SPL */ #define CONFIG_SPL_SIZE (140 << 10) @@ -99,12 +115,16 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD /* SPL related MMC defines */ +#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 28124dd4b1..7e4c497fe0 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -159,7 +159,6 @@ */ #define CONFIG_TSEC1 #define CONFIG_TSEC2 -#define CONFIG_HARD_SPI /* * NOR FLASH setup @@ -273,15 +272,6 @@ #define CONFIG_RTC_PCF8563 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 -/* - * SPI setup - */ -#ifdef CONFIG_HARD_SPI -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0x00000001 -#define CONFIG_SYS_GPIO1_DAT 0x00000001 -#endif - /* * Ethernet setup */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h new file mode 100644 index 0000000000..35f81152f2 --- /dev/null +++ b/include/configs/imx8mq_evk.h @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_EVK_H +#define __IMX8M_EVK_H + +#include +#include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h deleted file mode 100644 index 6615f7711d..0000000000 --- a/include/configs/khadas-vim.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Khadas VIM - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/khadas-vim2.h b/include/configs/khadas-vim2.h deleted file mode 100644 index 7ef8f42bd2..0000000000 --- a/include/configs/khadas-vim2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Khadas VIM2 - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MISC_INIT_R - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxm-khadas-vim2.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index e2585171af..0de83f6723 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -22,7 +22,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index ef26a144a9..33c8bd4149 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/lager.h b/include/configs/lager.h index 08498c6d81..89c5d01d3c 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -36,8 +36,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h deleted file mode 100644 index a0856f98da..0000000000 --- a/include/configs/libretech-cc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for LibreTech CC - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 78efa23279..3bae92d0ee 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -38,7 +38,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Environment settings */ -#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_OFFSET 0x80000 #define CONFIG_ENV_SIZE (16 << 10) #define CONFIG_ENV_SECT_SIZE (64 << 10) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 71e4a8b427..cb329385d9 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -93,10 +93,16 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" #endif +#endif #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 787adbc382..324dba2b7e 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -16,7 +16,11 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 @@ -34,7 +38,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) /*SPI device */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_ENV_SPI_BUS 0 @@ -58,7 +62,11 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ +#ifdef CONFIG_TFABOOT +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#else #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ +#endif #define CONFIG_ENV_SECT_SIZE 0x40000 #endif @@ -106,9 +114,15 @@ "kernel_size=0x2800000\0" \ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ + "$kernel_start $kernel_size && "\ + "bootm $kernel_load" +#else #define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 7affabfdba..8c7d4e558d 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -65,7 +65,12 @@ "$kernel_addr $kernel_size && bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#else #define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" +#endif #define CONFIG_CMD_MEMINFO #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index e450002e83..ebb1df41c7 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -119,8 +119,14 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ "env exists secureboot && esbc_halt;" +#endif #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index c5bdea6798..c76bfdc8f8 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -117,4 +117,5 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#include #endif /* __LS1012AQDS_H__ */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 17554ea955..f149a604cf 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -112,8 +112,14 @@ "bootm $load_addr#$board\0" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ "env exists secureboot && esbc_halt;" +#endif #include diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4279d53549..27350dfa00 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -33,7 +33,11 @@ #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -119,7 +123,8 @@ /* IFC */ #ifndef SPL_NO_IFC -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -182,6 +187,16 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 + +#else #ifdef CONFIG_NAND_BOOT /* Store Fman ucode at offeset 0x900000(72 blocks). */ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -208,6 +223,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -300,6 +316,14 @@ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -311,6 +335,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 68f202f97a..ed07d9f28e 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -196,7 +196,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -251,6 +252,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -318,6 +353,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif /* * I2C bus multiplexer @@ -349,7 +385,8 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212 /* QSPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -381,6 +418,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -397,6 +442,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif #define CONFIG_CMDLINE_TAG diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 54e6eef417..a0d39878b8 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -162,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -199,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -227,6 +247,14 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -239,6 +267,7 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif /* FMan */ #ifndef SPL_NO_FMAN diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index cdb73f644a..6e36c9339b 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -33,7 +33,11 @@ #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -165,6 +169,13 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #ifdef CONFIG_SD_BOOT /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is @@ -187,6 +198,7 @@ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 9ae0953940..886fe723ba 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -50,7 +50,8 @@ unsigned long get_board_ddr_clk(void); #endif /* QSPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -227,7 +228,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT #endif @@ -282,6 +284,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -349,6 +385,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif /* * I2C bus multiplexer @@ -399,6 +436,14 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -415,10 +460,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif #define CONFIG_CMDLINE_TAG #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \ + "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" @@ -426,6 +480,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #endif +#endif #include diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index dcb5854046..77b50dbdad 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -160,6 +160,13 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) @@ -169,6 +176,7 @@ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #endif +#endif #define AQR105_IRQ_MASK 0x80000000 /* FMan */ @@ -206,6 +214,12 @@ #ifndef SPL_NO_MISC #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;;" @@ -214,6 +228,7 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif #include diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 822fd76cc5..743d0cf30f 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP */ #ifndef __LS1088_COMMON_H @@ -27,6 +27,7 @@ #include #include +#define LS1088ARDB_PB_BOARD 0x4A /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index f4e350d207..829c5390cf 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -324,7 +324,6 @@ unsigned long get_board_ddr_clk(void); /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 14731c5337..5269bcd243 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -275,7 +275,6 @@ #ifndef SPL_NO_QSPI /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 #endif diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 94214b135d..3fca28da6b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -110,7 +110,6 @@ * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif diff --git a/include/configs/meson-gx-common.h b/include/configs/meson64.h similarity index 51% rename from include/configs/meson-gx-common.h rename to include/configs/meson64.h index c46522ef7e..40ac079dfc 100644 --- a/include/configs/meson-gx-common.h +++ b/include/configs/meson64.h @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Configuration for Amlogic Meson GX SoCs + * Configuration for Amlogic Meson 64bits SoCs * (C) Copyright 2016 Beniamino Galvani */ -#ifndef __MESON_GX_COMMON_CONFIG_H -#define __MESON_GX_COMMON_CONFIG_H +#ifndef __MESON64_CONFIG_H +#define __MESON64_CONFIG_H + +/* Generic Interrupt Controller Definitions */ +#if defined(CONFIG_MESON_AXG) +#define GICD_BASE 0xffc01000 +#define GICC_BASE 0xffc02000 +#else /* MESON GXL and GXBB */ +#define GICD_BASE 0xc4301000 +#define GICC_BASE 0xc4302000 +#endif #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF @@ -17,10 +26,19 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xc4301000 -#define GICC_BASE 0xc4302000 +/* ROM USB boot support, auto-execute boot.scr at scriptaddr */ +#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ + "bootcmd_romusb=" \ + "if test \"${boot_source}\" = \"usb\" && " \ + "test -n \"${scriptaddr}\"; then " \ + "echo '(ROM USB boot)'; " \ + "source ${scriptaddr}; " \ + "fi\0" + +#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \ + "romusb " #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) @@ -28,25 +46,28 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ + func(ROMUSB, romusb, na) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#endif + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x08008000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x08080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + BOOTENV +#endif #include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r=0x01000000\0" \ - "scriptaddr=0x1f000000\0" \ - "kernel_addr_r=0x01080000\0" \ - "pxefile_addr_r=0x01080000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - MESON_FDTFILE_SETTING \ - BOOTENV - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ - -#endif /* __MESON_GX_COMMON_CONFIG_H */ +#endif /* __MESON64_CONFIG_H */ diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h new file mode 100644 index 0000000000..ba763501cf --- /dev/null +++ b/include/configs/mt7623.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7623 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#ifndef __MT7623_H +#define __MT7623_H + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +/* Environment */ +#define CONFIG_ENV_SIZE SZ_4K +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Preloader -> Uboot */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* UBoot -> Kernel */ +#define CONFIG_LOADADDR 0x84000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* MMC */ +#define MMC_SUPPORTS_TUNING +#define CONFIG_SUPPORT_EMMC_BOOT + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* This is needed for kernel booting */ +#define FDT_HIGH "fdt_high=0xac000000\0" + +/* Extra environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + FDT_HIGH + +#endif diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h new file mode 100644 index 0000000000..a665a5eb7f --- /dev/null +++ b/include/configs/mt7629.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee + */ + +#ifndef __MT7629_H +#define __MT7629_H + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +/* Environment */ +#define CONFIG_ENV_SIZE SZ_4K +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Defines for SPL */ +#define CONFIG_SPL_STACK 0x106000 +#define CONFIG_SPL_TEXT_BASE 0x201000 +#define CONFIG_SPL_MAX_SIZE SZ_64K +#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K +#define CONFIG_SPL_PAD_TO 0x10000 + +#define CONFIG_SPI_ADDR 0x30000000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) + +/* SPL -> Uboot */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* UBoot -> Kernel */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 +#define CONFIG_LOADADDR 0x42007f1c +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +#endif diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 5eeb5a1624..a803093163 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -19,7 +19,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_MARVELL 1 /* * Custom CONFIG_SYS_TEXT_BASE can be done in .h diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 7d84d160b4..4765764f83 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -43,7 +43,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_HARD_SPI #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 9e59e7a4dc..4bb3621a42 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -143,7 +143,6 @@ /* SPI */ #ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI #define CONFIG_SPI_HALF_DUPLEX #endif diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h deleted file mode 100644 index ef53f20c0f..0000000000 --- a/include/configs/nanopi-k2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for NANOPI-K2 - * (C) Copyright 2018 Thomas McKahan - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-nanopi-k2.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h deleted file mode 100644 index d117b183aa..0000000000 --- a/include/configs/odroid-c2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for ODROID-C2 - * (C) Copyright 2016 Beniamino Galvani - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index ad77242e38..c3520bb15f 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -40,7 +40,7 @@ /* Console configuration */ #define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" -#define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -157,7 +157,7 @@ "elif test -e mmc 0 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ "mmcbootdev=0\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index f683ee46e3..0337c26475 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -30,7 +30,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) -#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" /* USB */ #define CONFIG_USB_EHCI_EXYNOS @@ -61,6 +61,7 @@ "exynos5422-odroidxu3.dtb fat 0 1;" \ "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ "exynos5422-odroidxu4.dtb fat 0 1;" \ + "exynos5422-odroidhc1.dtb fat 0 1;" \ "boot part 0 1;" \ "root part 0 2\0" @@ -99,7 +100,7 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0"\ + "console=" CONFIG_DEFAULT_CONSOLE \ "fdtfile=exynos5422-odroidxu3.dtb\0" \ "boardname=odroidxu3\0" \ "mmcbootdev=0\0" \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index b9d6569752..775374cf28 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -20,10 +20,6 @@ #define CONFIG_REVISION_TAG 1 -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ - /* TPS65950 */ #define PBIASLITEVMODE1 (1 << 8) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9465fb4702..459ecf328f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -576,11 +576,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI - #if defined(CONFIG_SPI_FLASH) #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index d018c22afd..4f48370648 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -214,11 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* - * eSPI - Enhanced SPI - */ -#define CONFIG_HARD_SPI - #if defined(CONFIG_PCI) /* * General PCI diff --git a/include/configs/p212.h b/include/configs/p212.h deleted file mode 100644 index 2aa9f5d143..0000000000 --- a/include/configs/p212.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Amlogic P212 - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Serial setup */ - -#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0" - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 9997795434..e125a38e7d 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_I2C_MXC /* RTC (actually an RV-4162 but M41T62-compatible) */ -#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_RTC_BUS_NUM 2 diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 49048c163f..b9bc08b388 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -55,6 +55,7 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT #endif /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 7b809e2329..e4c2872fe9 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -12,12 +12,6 @@ #include -/* No more need for I2C legacy compatibility for this board. - * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there - * for the right moment to delete the following line. - */ -#undef CONFIG_DM_I2C_COMPAT - /* Using 32K of volatile storage for environment */ #define CONFIG_ENV_SIZE 0x4000 diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 2bc42a04a0..1884c5844d 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -134,7 +134,19 @@ /* FLASH and environment organization */ #define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +/* Environment starts at 768k = 768 * 1024 = 786432 */ +#define CONFIG_ENV_OFFSET 786432 +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 715776 + #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 0b240e7ebc..c2882e6daf 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -57,10 +57,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_HW_WATCHDOG - /* * Command line configuration. */ diff --git a/include/configs/porter.h b/include/configs/porter.h index e56dc3f1ec..9950f80afd 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -40,8 +40,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index fedc4662fa..0431a7982d 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -21,10 +21,12 @@ #define CONFIG_SYS_HZ 1000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_64K +#define CONFIG_ENV_ADDR 0x4000000 +#define CONFIG_ENV_SIZE SZ_256K #define BOOT_TARGET_DEVICES(func) \ func(SCSI, scsi, 0) \ + func(VIRTIO, virtio, 0) \ func(DHCP, dhcp, na) #include @@ -42,4 +44,9 @@ #define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE 0x0 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ + #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d279c233b2..b29d155d09 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -15,7 +15,35 @@ #define CONFIG_SYS_MALLOC_LEN SZ_8M +#define CONFIG_SYS_BOOTM_LEN SZ_16M + /* Environment options */ #define CONFIG_ENV_SIZE SZ_4K +#define BOOT_TARGET_DEVICES(func) \ + func(QEMU, qemu, na) \ + func(VIRTIO, virtio, 0) \ + func(DHCP, dhcp, na) + +#include + +#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \ + "bootcmd_qemu=" \ + "if env exists kernel_start; then " \ + "bootm ${kernel_start} - ${fdtcontroladdr};" \ + "fi;\0" + +#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \ + "qemu " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "scriptaddr=0x82100000\0" \ + "pxefile_addr_r=0x82200000\0" \ + "ramdisk_addr_r=0x82300000\0" \ + BOOTENV + #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 435d108628..6c2fa6a63c 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -59,8 +59,7 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" + "bootm_size=0x10000000\0" #define CONFIG_BOOTCOMMAND \ "tftp 0x48080000 Image; " \ diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h new file mode 100644 index 0000000000..746d24cbff --- /dev/null +++ b/include/configs/rock960_rk3399.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#ifndef __ROCK960_RK3399_H +#define __ROCK960_RK3399_H + +#include + +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 37be6dbeeb..9ce41767a9 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -148,6 +148,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 2ab3b85e0c..16d4e2e355 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -17,6 +17,9 @@ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) @@ -25,3 +28,18 @@ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #endif + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + BOOTENV +#endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 87ddc20a52..ff634d91dd 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -87,7 +87,7 @@ #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ " ${console} ${meminfo}" @@ -134,7 +134,7 @@ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "verify=n\0" \ "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0"\ + "console=" CONFIG_DEFAULT_CONSOLE \ "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ "mmcdev=0\0" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 999bdd1676..832032da18 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -27,7 +27,7 @@ /* Console configuration */ #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -108,7 +108,7 @@ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ "verify=n\0" \ "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ diff --git a/include/configs/silk.h b/include/configs/silk.h index a94928bd16..112806c342 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -40,8 +40,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 114b87e1b3..28af575bf2 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -112,13 +112,6 @@ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ "dhcp" -/* Enable the watchdog */ -#define CONFIG_AT91SAM9_WATCHDOG -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_HW_WATCHDOG -#endif -#define CONFIG_AT91_HW_WDT_TIMEOUT 15 - #if !defined(CONFIG_SPL_BUILD) /* USB configuration */ #define CONFIG_USB_ATMEL diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index c408db865e..33ddc67bf4 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -66,7 +66,6 @@ #define CONFIG_CF_DSPI #define CONFIG_SF_DEFAULT_SPEED 50000000 #define CONFIG_SERIAL_FLASH -#define CONFIG_HARD_SPI #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 1 diff --git a/include/configs/stout.h b/include/configs/stout.h index b72b565c33..93d980569c 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -44,8 +44,7 @@ #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" + "bootm_size=0x10000000\0" /* SPL support */ #define CONFIG_SPL_TEXT_BASE 0xe6300000 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 4fdb0dd962..f283ab7fca 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -85,13 +85,6 @@ #define CONFIG_RMII #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_AT91SAM9_WATCHDOG -#define CONFIG_AT91_HW_WDT_TIMEOUT 15 -#if !defined(CONFIG_SPL_BUILD) -/* Enable the watchdog */ -#define CONFIG_HW_WATCHDOG -#endif - /* USB */ #if defined(CONFIG_BOARD_TAURUS) #define CONFIG_USB_ATMEL diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 55b9b45eec..1e2a62dd6f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -74,24 +74,10 @@ /* Timer information. */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -/* - * Disable DM_* for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_I2C -#endif - -/* I2C IP block */ +/* If DM_I2C, enable non-DM I2C support */ +#if !defined(CONFIG_DM_I2C) #define CONFIG_I2C -#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#else -/* - * Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client - * devices are adopted to DM - */ -#define CONFIG_DM_I2C_COMPAT #endif /* @@ -165,7 +151,9 @@ /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif #ifdef CONFIG_SPL_OS_BOOT /* FAT */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cc823c5146..0c7d664868 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -128,7 +128,6 @@ #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE /* Keystone net */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE @@ -170,12 +169,16 @@ #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -/* USB Configuration */ -#define CONFIG_USB_XHCI_KEYSTONE -#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE -#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE -#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE -#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE +#define DFU_ALT_INFO_MMC \ + "dfu_alt_info_mmc=" \ + "MLO fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1\0" + +/* DFU settings */ +#define DFUARGS \ + "dfu_bufsiz=0x10000\0" \ + DFU_ALT_INFO_MMC \ /* U-Boot general configuration */ #define CONFIG_MX_CYCLIC @@ -215,6 +218,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + DFUARGS \ "bootdir=/boot\0" \ "tftp_root=/\0" \ "nfs_root=/export\0" \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 223fce49a7..af8e8ce3b6 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -36,7 +36,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TRATS #define CONFIG_BOOTCOMMAND "run autoboot" -#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -120,7 +120,7 @@ "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ "verify=n\0" \ "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ "bootblock=" CONFIG_BOOTBLOCK "\0" \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index f1e4cbad30..9c6b2bbc8d 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -34,7 +34,7 @@ /* Console configuration */ #define CONFIG_BOOTCOMMAND "run autoboot" -#define CONFIG_DEFAULT_CONSOLE "ttySAC2,115200n8" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) @@ -103,7 +103,7 @@ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "verify=n\0" \ "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE "\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ "kernelname=uImage\0" \ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ "${kernelname}\0" \ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index 956f7795f1..4e274bd414 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -42,11 +42,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -/* - * SPI Configs - * */ -#define CONFIG_HARD_SPI /* puts SPI: ready */ - /* * MMC Configs * */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 70f8712b60..95d6452553 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -124,6 +124,8 @@ "third_image=u-boot.bin\0" #endif +#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run ${bootdev}preboot" + #define CONFIG_ROOTPATH "/nfs/root/path" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs $bootargs root=/dev/nfs rw " \ @@ -169,8 +171,32 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "initrd_high=0xffffffffffffffff\0" \ + "script=boot.scr\0" \ "scriptaddr=0x85000000\0" \ "nor_base=0x42000000\0" \ + "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \ + "nandboot=run bootcmd_ubifs0\0" \ + "norboot=run tftpboot\0" \ + "usbboot=run bootcmd_usb0\0" \ + "emmcscript=setenv devtype mmc && " \ + "mmcsetn && " \ + "setenv devnum ${mmc_first_dev} && " \ + "run loadscript_fat\0" \ + "nandscript=echo Running ${script} from ubi ... && " \ + "ubi part UBI && " \ + "ubifsmount ubi0:boot && " \ + "ubifsload ${loadaddr} ${script} && " \ + "source\0" \ + "norscript=echo Running ${script} from tftp ... && " \ + "tftpboot ${script} &&" \ + "source\0" \ + "usbscript=usb start && " \ + "setenv devtype usb && " \ + "setenv devnum 0 && " \ + "run loadscript_fat\0" \ + "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \ + "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \ + "source\0" \ "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ "tftpboot $tmp_addr $second_image && " \ "setexpr tmp_addr $nor_base + 0x70000 && " \ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h new file mode 100644 index 0000000000..df89cdaebf --- /dev/null +++ b/include/configs/vcoreiii.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __VCOREIII_H +#define __VCOREIII_H + +#include + +/* Onboard devices */ + +#define CONFIG_SYS_MALLOC_LEN 0x100000 +#define CONFIG_SYS_LOAD_ADDR 0x00100000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */ +#ifdef CONFIG_SOC_LUTON +#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333 +#else +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#endif +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_SIZE (256 * 1024) +#define CONFIG_ENV_SECT_SIZE (256 * 1024) + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */ +#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */ +#endif + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) +#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) +#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#else +#error Unknown DDR size - please add! +#endif + +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_BOARD_EARLY_INIT_R +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) +#define VCOREIII_DEFAULT_MTD_ENV \ + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ + "mtdids="CONFIG_MTDIDS_DEFAULT"\0" +#else +#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ +#endif + +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + VCOREIII_DEFAULT_MTD_ENV \ + "loadaddr=0x81000000\0" \ + "spi_image_off=0x00100000\0" \ + "console=ttyS0,115200\0" \ + "setup=setenv bootargs console=${console} ${mtdparts}" \ + "${bootargs_extra}\0" \ + "spiboot=run setup; sf probe; sf read ${loadaddr}" \ + "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \ + "ubootfile=u-boot.bin\0" \ + "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \ + "sf erase UBoot 0x100000;" \ + "sf write ${loadaddr} UBoot ${filesize}\0" \ + "bootcmd=run spiboot\0" \ + "" +#endif /* __VCOREIII_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 267b230fda..47ea89df66 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -120,7 +120,7 @@ #define CONFIG_INITRD_TAG 1 /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) diff --git a/include/configs/x600.h b/include/configs/x600.h index a6835ebbd5..639da8012c 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 -#define CONFIG_RTC_M41T62 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* FPGA config options */ diff --git a/include/cpu.h b/include/cpu.h index 367c5f46a0..28dd48feb8 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -14,6 +14,8 @@ * @device_id: Driver-defined device identifier * @family: DMTF CPU Family identifier * @id: DMTF CPU Processor identifier + * @timebase_freq: the current frequency at which the cpu timer timebase + * registers are updated (in Hz) * * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU * device. @@ -24,6 +26,7 @@ struct cpu_platdata { ulong device_id; u16 family; u32 id[2]; + u32 timebase_freq; }; /* CPU features - mostly just a placeholder for now */ diff --git a/include/crc.h b/include/crc.h deleted file mode 100644 index 2a00af5be4..0000000000 --- a/include/crc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: eCos-2.0 */ -/* - *========================================================================== - * - * crc.h - * - * Interface for the CRC algorithms. - * - *========================================================================== - *========================================================================== - *#####DESCRIPTIONBEGIN#### - * - * Author(s): Andrew Lunn - * Contributors: Andrew Lunn - * Date: 2002-08-06 - * Purpose: - * Description: - * - * This code is part of eCos (tm). - * - *####DESCRIPTIONEND#### - * - *========================================================================== - */ - -#ifndef _SERVICES_CRC_CRC_H_ -#define _SERVICES_CRC_CRC_H_ - -#include - -#ifndef __externC -# ifdef __cplusplus -# define __externC extern "C" -# else -# define __externC extern -# endif -#endif - -/* 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */ - -uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *s, int len); - -#endif /* _SERVICES_CRC_CRC_H_ */ diff --git a/include/cros_ec.h b/include/cros_ec.h index 4771e6b7d1..f4b9b7a5c2 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -187,6 +187,14 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, uint32_t set_flags, struct ec_response_flash_protect *resp); +/** + * Notify EC of current boot mode + * + * @param dev CROS-EC device + * @param vboot_mode Verified boot mode + * @return 0 if ok, <0 on error + */ +int cros_ec_entering_mode(struct udevice *dev, int mode); /** * Run internal tests on the cros_ec interface. @@ -397,4 +405,85 @@ struct i2c_msg; int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg, int nmsgs); +/** + * cros_ec_get_events_b() - Get event mask B + * + * @return value of event mask, default value of 0 if it could not be read + */ +uint64_t cros_ec_get_events_b(struct udevice *dev); + +/** + * cros_ec_clear_events_b() - Clear even mask B + * + * Any pending events in the B range are cleared + * + * @return 0 if OK, -ve on error + */ +int cros_ec_clear_events_b(struct udevice *dev, uint64_t mask); + +/** + * cros_ec_efs_verify() - tell the EC to verify one of its images + * + * @param dev CROS-EC device + * @param region Flash region to query + * @return 0 if OK, -ve on error + */ +int cros_ec_efs_verify(struct udevice *dev, enum ec_flash_region region); + +/** + * cros_ec_battery_cutoff() - Request that the battery be cut off + * + * This tells the battery to stop supplying power. This is used before shipping + * a device to ensure that the battery remains charged while the device is + * shipped or sitting on the shelf waiting to be purchased. + * + * @param dev CROS-EC device + * @param flags Flags to use (EC_BATTERY_CUTOFF_FLAG_...) + * @return 0 if OK, -ve on error + */ +int cros_ec_battery_cutoff(struct udevice *dev, uint8_t flags); + +/** + * cros_ec_read_limit_power() - Check if power is limited by batter/charger + * + * Sometimes the battery is low and / or the device is connected to a charger + * that cannot supply much power. + * + * @param dev CROS-EC device + * @param limit_powerp Returns whether power is limited (0 or 1) + * @return 0 if OK, -ENOSYS if the EC does not support this comment, -EINVAL + * if the EC returned an invalid response + */ +int cros_ec_read_limit_power(struct udevice *dev, int *limit_powerp); + +/** + * cros_ec_config_powerbtn() - Configure the behaviour of the power button + * + * @param dev CROS-EC device + * @param flags Flags to use (EC_POWER_BUTTON_...) + * @return 0 if OK, -ve on error + */ +int cros_ec_config_powerbtn(struct udevice *dev, uint32_t flags); + +/** + * cros_ec_get_lid_shutdown_mask() - Set the lid shutdown mask + * + * Determines whether a lid close event is reported + * + * @param dev CROS-EC device + * @return shufdown mas if OK, -ve on error + */ +int cros_ec_get_lid_shutdown_mask(struct udevice *dev); + +/** + * cros_ec_set_lid_shutdown_mask() - Set the lid shutdown mask + * + * Set whether a lid close event is reported + * + * @param dev CROS-EC device + * @param enable true to enable reporting, false to disable + * @return shufdown mas if OK, -ve on error + */ +int cros_ec_set_lid_shutdown_mask(struct udevice *dev, int enable); + #endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 02ac4c7952..ee2b24a62a 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -74,8 +74,8 @@ int device_bind_with_driver_data(struct udevice *parent, * tree. * * @parent: Pointer to device's parent - * @pre_reloc_only: If true, bind the driver only if its DM_INIT_F flag is set. - * If false bind the driver always. + * @pre_reloc_only: If true, bind the driver only if its DM_FLAG_PRE_RELOC flag + * is set. If false bind the driver always. * @info: Name and platdata for this device * @devp: if non-NULL, returns a pointer to the bound device * @return 0 if OK, -ve on error diff --git a/include/dm/device.h b/include/dm/device.h index 847934425b..27a6d7b9fd 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -525,6 +525,8 @@ int device_find_next_child(struct udevice **devp); * This is used to locate an existing child of a device which is of a given * uclass. * + * The device is NOT probed + * * @parent: Parent device to search * @uclass_id: Uclass to look for * @devp: Returns device found, if any @@ -534,6 +536,29 @@ int device_find_first_inactive_child(struct udevice *parent, enum uclass_id uclass_id, struct udevice **devp); +/** + * device_find_first_child_by_uclass() - Find the first child of a device in uc + * + * @parent: Parent device to search + * @uclass_id: Uclass to look for + * @devp: Returns first child device in that uclass, if any + * @return 0 if found, else -ENODEV + */ +int device_find_first_child_by_uclass(struct udevice *parent, + enum uclass_id uclass_id, + struct udevice **devp); + +/** + * device_find_child_by_name() - Find a child by device name + * + * @parent: Parent device to search + * @name: Name to look for + * @devp: Returns device found, if any + * @return 0 if found, else -ENODEV + */ +int device_find_child_by_name(struct udevice *parent, const char *name, + struct udevice **devp); + /** * device_has_children() - check if a device has any children * diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h index 49a6ffd5f8..c171d9bc2f 100644 --- a/include/dm/fdtaddr.h +++ b/include/dm/fdtaddr.h @@ -55,6 +55,19 @@ void *devfdt_remap_addr(struct udevice *dev); */ void *devfdt_remap_addr_index(struct udevice *dev, int index); +/** + * devfdt_remap_addr_name() - Get the reg property of a device, indexed by + * name, as a memory-mapped I/O pointer + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @dev: Pointer to a device + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_remap_addr_name(struct udevice *dev, const char *name); + /** * devfdt_map_physmem() - Read device address from reg property of the * device node and map the address into CPU address diff --git a/include/dm/lists.h b/include/dm/lists.h index 13d1516a12..810e244d9e 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -39,8 +39,8 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id); * each one. The devices will have @parent as their parent. * * @parent: parent device (root) - * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false - * bind all drivers. + * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag. + * If false bind all drivers. */ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); @@ -53,10 +53,13 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); * @parent: parent device (root) * @node: device tree node to bind * @devp: if non-NULL, returns a pointer to the bound device + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. * @return 0 if device was bound, -EINVAL if the device tree is invalid, * other -ve value on error */ -int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp); +int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, + bool pre_reloc_only); /** * device_bind_driver() - bind a device to a driver diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 2fc9fa39a3..d206ee2caa 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -236,6 +236,16 @@ int ofnode_read_u32_default(ofnode ref, const char *propname, u32 def); */ int ofnode_read_s32_default(ofnode node, const char *propname, s32 def); +/** + * ofnode_read_u64() - Read a 64-bit integer from a property + * + * @node: valid node reference to read property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int ofnode_read_u64(ofnode node, const char *propname, u64 *outp); + /** * ofnode_read_u64_default() - Read a 64-bit integer from a property * @@ -323,7 +333,7 @@ ofnode ofnode_get_parent(ofnode node); * ofnode_get_name() - get the name of a node * * @node: valid node to look up - * @return name or node + * @return name of node */ const char *ofnode_get_name(ofnode node); diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index 80de3f3fed..ff2b82e7c2 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -6,6 +6,9 @@ #ifndef __PINCTRL_H #define __PINCTRL_H +#define PINNAME_SIZE 10 +#define PINMUX_SIZE 40 + /** * struct pinconf_param - pin config parameters * @@ -66,6 +69,7 @@ struct pinconf_param { * pointing a config node. (necessary for pinctrl_full) * @set_state_simple: do needed pinctrl operations for a peripherl @periph. * (necessary for pinctrl_simple) + * @get_pin_muxing: display the muxing of a given pin. */ struct pinctrl_ops { int (*get_pins_count)(struct udevice *dev); @@ -129,6 +133,24 @@ struct pinctrl_ops { * @return mux value (SoC-specific, e.g. 0 for input, 1 for output) */ int (*get_gpio_mux)(struct udevice *dev, int banknum, int index); + + /** + * get_pin_muxing() - show pin muxing + * + * This allows to display the muxing of a given pin. It's useful for + * debug purpose to know if a pin is configured as GPIO or as an + * alternate function and which one. + * Typically it is used by a PINCTRL driver with knowledge of the SoC + * pinctrl setup. + * + * @dev: Pinctrl device to use + * @selector: Pin selector + * @buf Pin's muxing description + * @size Pin's muxing description length + * return 0 if OK, -ve on error + */ + int (*get_pin_muxing)(struct udevice *dev, unsigned int selector, + char *buf, int size); }; #define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops) @@ -332,6 +354,18 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph); */ int pinctrl_decode_pin_config(const void *blob, int node); +/** + * pinctrl_decode_pin_config_dm() - decode pin configuration flags + * + * This decodes some of the PIN_CONFIG values into flags, with each value + * being (1 << pin_cfg). This does not support things with values like the + * slew rate. + * + * @pinconfig: Pinconfig udevice + * @return decoded flag value, or -ve on error + */ +int pinctrl_decode_pin_config_dm(struct udevice *dev); + /** * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO * @@ -348,4 +382,41 @@ int pinctrl_decode_pin_config(const void *blob, int node); */ int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index); +/** + * pinctrl_get_pin_muxing() - Returns the muxing description + * + * This allows to display the muxing description of the given pin for + * debug purpose + * + * @dev: Pinctrl device to use + * @selector Pin index within pin-controller + * @buf Pin's muxing description + * @size Pin's muxing description length + * @return 0 if OK, -ve on error + */ +int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf, + int size); + +/** + * pinctrl_get_pins_count() - display pin-controller pins number + * + * This allows to know the number of pins owned by a given pin-controller + * + * @dev: Pinctrl device to use + * @return pins number if OK, -ve on error + */ +int pinctrl_get_pins_count(struct udevice *dev); + +/** + * pinctrl_get_pin_name() - Returns the pin's name + * + * This allows to display the pin's name for debug purpose + * + * @dev: Pinctrl device to use + * @selector Pin index within pin-controller + * @buf Pin's name + * @return 0 if OK, -ve on error + */ +int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf, + int size); #endif /* __PINCTRL_H */ diff --git a/include/dm/platform_data/pl022_spi.h b/include/dm/platform_data/spi_pl022.h similarity index 64% rename from include/dm/platform_data/pl022_spi.h rename to include/dm/platform_data/spi_pl022.h index 77fe6da3cb..63a58ee453 100644 --- a/include/dm/platform_data/pl022_spi.h +++ b/include/dm/platform_data/spi_pl022.h @@ -7,22 +7,15 @@ * in ofdata_to_platdata. */ -#ifndef __PL022_SPI_H__ -#define __PL022_SPI_H__ +#ifndef __spi_pl022_h +#define __spi_pl022_h -#if !CONFIG_IS_ENABLED(OF_PLATDATA) -#include -#endif #include struct pl022_spi_pdata { fdt_addr_t addr; fdt_size_t size; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct clk clk; -#else unsigned int freq; -#endif }; -#endif +#endif /* __spi_pl022_h */ diff --git a/include/dm/read.h b/include/dm/read.h index a27b8554fb..389e30e7fb 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -64,6 +64,38 @@ int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp); */ int dev_read_u32_default(struct udevice *dev, const char *propname, int def); +/** + * dev_read_s32() - read a signed 32-bit integer from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_s32(struct udevice *dev, const char *propname, s32 *outp); + +/** + * dev_read_s32_default() - read a signed 32-bit int from a device's DT property + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @def: default value to return if the property has no value + * @return property value, or @def if not found + */ +int dev_read_s32_default(struct udevice *dev, const char *propname, int def); + +/** + * dev_read_u32u() - read a 32-bit integer from a device's DT property + * + * This version uses a standard uint type. + * + * @dev: device to read DT property from + * @propname: name of the property to read from + * @outp: place to put value (if found) + * @return 0 if OK, -ve on error + */ +int dev_read_u32u(struct udevice *dev, const char *propname, uint *outp); + /** * dev_read_string() - Read a string from a device's DT property * @@ -124,6 +156,31 @@ fdt_addr_t dev_read_addr_index(struct udevice *dev, int index); */ void *dev_remap_addr_index(struct udevice *dev, int index); +/** + * dev_read_addr_name() - Get the reg property of a device, indexed by name + * + * @dev: Device to read from + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @return address or FDT_ADDR_T_NONE if not found + */ +fdt_addr_t dev_read_addr_name(struct udevice *dev, const char* name); + +/** + * dev_remap_addr_name() - Get the reg property of a device, indexed by name, + * as a memory-mapped I/O pointer + * + * @dev: Device to read from + * @name: the 'reg' property can hold a list of pairs, with the + * 'reg-names' property providing named-based identification. @index + * indicates the value to search for in 'reg-names'. + * + * @return pointer or NULL if not found + */ +void *dev_remap_addr_name(struct udevice *dev, const char* name); + /** * dev_read_addr() - Get the reg property of a device * @@ -467,6 +524,32 @@ static inline int dev_read_u32_default(struct udevice *dev, return ofnode_read_u32_default(dev_ofnode(dev), propname, def); } +static inline int dev_read_s32(struct udevice *dev, + const char *propname, s32 *outp) +{ + return ofnode_read_s32(dev_ofnode(dev), propname, outp); +} + +static inline int dev_read_s32_default(struct udevice *dev, + const char *propname, int def) +{ + return ofnode_read_s32_default(dev_ofnode(dev), propname, def); +} + +static inline int dev_read_u32u(struct udevice *dev, + const char *propname, uint *outp) +{ + u32 val; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), propname, &val); + if (ret) + return ret; + *outp = val; + + return 0; +} + static inline const char *dev_read_string(struct udevice *dev, const char *propname) { @@ -494,6 +577,12 @@ static inline fdt_addr_t dev_read_addr_index(struct udevice *dev, int index) return devfdt_get_addr_index(dev, index); } +static inline fdt_addr_t dev_read_addr_name(struct udevice *dev, + const char *name) +{ + return devfdt_get_addr_name(dev, name); +} + static inline fdt_addr_t dev_read_addr(struct udevice *dev) { return devfdt_get_addr(dev); @@ -514,6 +603,11 @@ static inline void *dev_remap_addr_index(struct udevice *dev, int index) return devfdt_remap_addr_index(dev, index); } +static inline void *dev_remap_addr_name(struct udevice *dev, const char *name) +{ + return devfdt_remap_addr_name(dev, name); +} + static inline fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *propname, fdt_size_t *sizep) diff --git a/include/dm/root.h b/include/dm/root.h index 2b9c6da416..c8d629ba9b 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -48,8 +48,8 @@ int dm_scan_platdata(bool pre_reloc_only); * the top-level subnodes are examined. * * @blob: Pointer to device tree blob - * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC - * flag. If false bind all drivers. + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. * @return 0 if OK, -ve on error */ int dm_scan_fdt(const void *blob, bool pre_reloc_only); @@ -62,8 +62,8 @@ int dm_scan_fdt(const void *blob, bool pre_reloc_only); * of "clocks" node. * * @blob: Pointer to device tree blob - * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC - * flag. If false bind all drivers. + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. * @return 0 if OK, -ve on error */ int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only); @@ -76,8 +76,9 @@ int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only); * programmaticaly. They should do this by calling device_bind() on each * device. * - * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC - * flag. If false bind all drivers. + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. + * @return 0 if OK, -ve on error */ int dm_scan_other(bool pre_reloc_only); @@ -88,8 +89,8 @@ int dm_scan_other(bool pre_reloc_only); * then scans and binds available devices from platform data and the FDT. * This calls dm_init() to set up Driver Model structures. * - * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC - * flag. If false bind all drivers. + * @pre_reloc_only: If true, bind only nodes with special devicetree properties, + * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. * @return 0 if OK, -ve on error */ int dm_init_and_scan(bool pre_reloc_only); diff --git a/include/dm/test.h b/include/dm/test.h index 83418eb482..07385cd531 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -69,6 +69,7 @@ struct dm_test_priv { int op_count[DM_TEST_OP_COUNT]; int uclass_flag; int uclass_total; + int uclass_postp; }; /** diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 269a2c6e72..f3bafb3c63 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -21,16 +21,19 @@ enum uclass_id { UCLASS_TEST_DUMMY, UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ + UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */ UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ UCLASS_AXI_EMUL, /* sandbox AXI bus device emulator */ - UCLASS_SIMPLE_BUS, /* bus with child devices */ /* U-Boot uclasses start here - in alphabetical order */ UCLASS_ADC, /* Analog-to-digital converter */ UCLASS_AHCI, /* SATA disk controller */ + UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ + UCLASS_AXI, /* AXI bus */ UCLASS_BLK, /* Block device */ UCLASS_BOARD, /* Device information from hardware */ + UCLASS_BOOTCOUNT, /* Bootcount backing store */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ @@ -38,15 +41,16 @@ enum uclass_id { UCLASS_DMA, /* Direct Memory Access */ UCLASS_EFI, /* EFI managed devices */ UCLASS_ETH, /* Ethernet device */ + UCLASS_FIRMWARE, /* Firmware */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ - UCLASS_FIRMWARE, /* Firmware */ + UCLASS_HWSPINLOCK, /* Hardware semaphores */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_MUX, /* I2C multiplexer */ + UCLASS_I2S, /* I2S bus */ UCLASS_IDE, /* IDE device */ - UCLASS_AXI, /* AXI bus */ UCLASS_IRQ, /* Interrupt controller */ UCLASS_KEYBOARD, /* Keyboard input device */ UCLASS_LED, /* Light-emitting diode (LED) */ @@ -68,8 +72,8 @@ enum uclass_id { UCLASS_PINCONFIG, /* Pin configuration node device */ UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PMIC, /* PMIC I/O device */ - UCLASS_PWM, /* Pulse-width modulator */ UCLASS_POWER_DOMAIN, /* (SoC) Power domains */ + UCLASS_PWM, /* Pulse-width modulator */ UCLASS_PWRSEQ, /* Power sequence device */ UCLASS_RAM, /* RAM controller */ UCLASS_REGULATOR, /* Regulator device */ @@ -78,11 +82,13 @@ enum uclass_id { UCLASS_RTC, /* Real time clock device */ UCLASS_SCSI, /* SCSI device */ UCLASS_SERIAL, /* Serial UART */ + UCLASS_SIMPLE_BUS, /* Bus with child devices */ UCLASS_SMEM, /* Shared memory interface */ + UCLASS_SOUND, /* Playing simple sounds */ UCLASS_SPI, /* SPI bus */ - UCLASS_SPMI, /* System Power Management Interface bus */ UCLASS_SPI_FLASH, /* SPI flash */ UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPMI, /* System Power Management Interface bus */ UCLASS_SYSCON, /* System configuration device */ UCLASS_SYSRESET, /* System reset device */ UCLASS_TEE, /* Trusted Execution Environment device */ @@ -92,10 +98,12 @@ enum uclass_id { UCLASS_USB, /* USB bus */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ UCLASS_USB_HUB, /* USB hub */ + UCLASS_USB_GADGET_GENERIC, /* USB generic device */ UCLASS_VIDEO, /* Video or LCD device */ UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */ UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */ UCLASS_VIDEO_OSD, /* On-screen display */ + UCLASS_VIRTIO, /* VirtIO transport device */ UCLASS_W1, /* Dallas 1-Wire bus */ UCLASS_W1_EEPROM, /* one-wire EEPROMs */ UCLASS_WDT, /* Watchdot Timer driver */ diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index 30d5a4fb9b..6977995246 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -11,6 +11,19 @@ #include +/** + * uclass_find_next_free_req_seq() - Get the next free req_seq number + * + * This returns the next free req_seq number. This is useful only if + * OF_CONTROL is not used. The next free req_seq number is simply the + * maximum req_seq of the uclass + 1. + * This allows assiging req_seq number in the binding order. + * + * @id: Id number of the uclass + * @return The next free req_seq number + */ +int uclass_find_next_free_req_seq(enum uclass_id id); + /** * uclass_get_device_tail() - handle the end of a get_device call * @@ -142,6 +155,23 @@ int uclass_find_device_by_of_offset(enum uclass_id id, int node, int uclass_find_device_by_ofnode(enum uclass_id id, ofnode node, struct udevice **devp); +/** + * uclass_find_device_by_phandle() - Find a uclass device by phandle + * + * This searches the devices in the uclass for one with the given phandle. + * + * The device is NOT probed, it is merely returned. + * + * @id: ID to look up + * @parent: Parent device containing the phandle pointer + * @name: Name of property in the parent device node + * @devp: Returns pointer to device (there is only one for each node) + * @return 0 if OK, -ENOENT if there is no @name present in the node, other + * -ve on error + */ +int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, + const char *name, struct udevice **devp); + /** * uclass_bind_device() - Associate device with a uclass * diff --git a/include/dm/uclass.h b/include/dm/uclass.h index eebf2d5614..1bc62d523e 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -61,7 +61,8 @@ struct udevice; * @post_probe: Called after a new device is probed * @pre_remove: Called before a device is removed * @child_post_bind: Called after a child is bound to a device in this uclass - * @child_pre_probe: Called before a child is probed in this uclass + * @child_pre_probe: Called before a child in this uclass is probed + * @child_post_probe: Called after a child in this uclass is probed * @init: Called to set up the uclass * @destroy: Called to destroy the uclass * @priv_auto_alloc_size: If non-zero this is the size of the private data @@ -94,6 +95,7 @@ struct uclass_driver { int (*pre_remove)(struct udevice *dev); int (*child_post_bind)(struct udevice *dev); int (*child_pre_probe)(struct udevice *dev); + int (*child_post_probe)(struct udevice *dev); int (*init)(struct uclass *class); int (*destroy)(struct uclass *class); int priv_auto_alloc_size; @@ -305,6 +307,18 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp); */ int uclass_next_device(struct udevice **devp); +/** + * uclass_next_device_err() - Get the next device in a uclass + * + * The device returned is probed if necessary, and ready for use + * + * @devp: On entry, pointer to device to lookup. On exit, returns pointer + * to the next device in the uclass if no error occurred, or -ENODEV if + * there is no next device. + * @return 0 if found, -ENODEV if not found, other -ve on error + */ +int uclass_next_device_err(struct udevice **devp); + /** * uclass_first_device_check() - Get the first device in a uclass * @@ -379,4 +393,20 @@ int uclass_resolve_seq(struct udevice *dev); #define uclass_foreach_dev_safe(pos, next, uc) \ list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node) +/** + * uclass_foreach_dev_probe() - Helper function to iteration through devices + * of given uclass + * + * This creates a for() loop which works through the available devices in + * a uclass in order from start to end. Devices are probed if necessary, + * and ready for use. + * + * @id: Uclass ID + * @dev: struct udevice * to hold the current device. Set to NULL when there + * are no more devices. + */ +#define uclass_foreach_dev_probe(id, dev) \ + for (int _ret = uclass_first_device_err(id, &dev); !_ret && dev; \ + _ret = uclass_next_device_err(&dev)) + #endif diff --git a/include/dm/util.h b/include/dm/util.h index 898822e445..9ff6531d1b 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -55,7 +55,7 @@ static inline void dm_dump_devres(void) * There are 3 settings currently in use * - * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL - * Existing platforms only use it to indicate nodes needee in + * Existing platforms only use it to indicate nodes needed in * SPL. Should probably be replaced by u-boot,dm-spl for * existing platforms. * @blob: devicetree @@ -65,4 +65,29 @@ static inline void dm_dump_devres(void) */ bool dm_fdt_pre_reloc(const void *blob, int offset); +/** + * Check if an of node should be or was bound before relocation. + * + * Devicetree nodes can be marked as needed to be bound + * in the loader stages via special devicetree properties. + * + * Before relocation this function can be used to check if nodes + * are required in either SPL or TPL stages. + * + * After relocation and jumping into the real U-Boot binary + * it is possible to determine if a node was bound in one of + * SPL/TPL stages. + * + * There are 3 settings currently in use + * - + * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL + * Existing platforms only use it to indicate nodes needed in + * SPL. Should probably be replaced by u-boot,dm-spl for + * existing platforms. + * @node: of node + * + * Returns true if node is needed in SPL/TL, false otherwise. + */ +bool dm_ofnode_pre_reloc(ofnode node); + #endif diff --git a/include/dma-uclass.h b/include/dma-uclass.h new file mode 100644 index 0000000000..31b43fb4b9 --- /dev/null +++ b/include/dma-uclass.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 - 2018 Texas Instruments Incorporated + * Written by Mugunthan V N + * + */ + +#ifndef _DMA_UCLASS_H +#define _DMA_UCLASS_H + +/* See dma.h for background documentation. */ + +#include + +struct ofnode_phandle_args; + +/* + * struct dma_ops - Driver model DMA operations + * + * The uclass interface is implemented by all DMA devices which use + * driver model. + */ +struct dma_ops { +#ifdef CONFIG_DMA_CHANNELS + /** + * of_xlate - Translate a client's device-tree (OF) DMA specifier. + * + * The DMA core calls this function as the first step in implementing + * a client's dma_get_by_*() call. + * + * If this function pointer is set to NULL, the DMA core will use a + * default implementation, which assumes #dma-cells = <1>, and that + * the DT cell contains a simple integer DMA Channel. + * + * At present, the DMA API solely supports device-tree. If this + * changes, other xxx_xlate() functions may be added to support those + * other mechanisms. + * + * @dma: The dma struct to hold the translation result. + * @args: The dma specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct dma *dma, + struct ofnode_phandle_args *args); + /** + * request - Request a translated DMA. + * + * The DMA core calls this function as the second step in + * implementing a client's dma_get_by_*() call, following a successful + * xxx_xlate() call, or as the only step in implementing a client's + * dma_request() call. + * + * @dma: The DMA struct to request; this has been filled in by + * a previoux xxx_xlate() function call, or by the caller of + * dma_request(). + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct dma *dma); + /** + * free - Free a previously requested dma. + * + * This is the implementation of the client dma_free() API. + * + * @dma: The DMA to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct dma *dma); + /** + * enable() - Enable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*enable)(struct dma *dma); + /** + * disable() - Disable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*disable)(struct dma *dma); + /** + * prepare_rcv_buf() - Prepare/Add receive DMA buffer. + * + * @dma: The DMA Channel to manipulate. + * @dst: The receive buffer pointer. + * @size: The receive buffer size + * @return zero on success, or -ve error code. + */ + int (*prepare_rcv_buf)(struct dma *dma, void *dst, size_t size); + /** + * receive() - Receive a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @dst: The destination pointer. + * @metadata: DMA driver's specific data + * @return zero on success, or -ve error code. + */ + int (*receive)(struct dma *dma, void **dst, void *metadata); + /** + * send() - Send a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @metadata: DMA driver's specific data + * @return zero on success, or -ve error code. + */ + int (*send)(struct dma *dma, void *src, size_t len, void *metadata); +#endif /* CONFIG_DMA_CHANNELS */ + /** + * transfer() - Issue a DMA transfer. The implementation must + * wait until the transfer is done. + * + * @dev: The DMA device + * @direction: direction of data transfer (should be one from + * enum dma_direction) + * @dst: The destination pointer. + * @src: The source pointer. + * @len: Length of the data to be copied (number of bytes). + * @return zero on success, or -ve error code. + */ + int (*transfer)(struct udevice *dev, int direction, void *dst, + void *src, size_t len); +}; + +#endif /* _DMA_UCLASS_H */ diff --git a/include/dma.h b/include/dma.h index 50e965241c..d1c3d0df7d 100644 --- a/include/dma.h +++ b/include/dma.h @@ -1,12 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2015 - * Texas Instruments Incorporated, + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 - 2018 Texas Instruments Incorporated + * Written by Mugunthan V N + * */ #ifndef _DMA_H_ #define _DMA_H_ +#include +#include + /* * enum dma_direction - dma transfer direction indicator * @DMA_MEM_TO_MEM: Memcpy mode @@ -26,28 +31,6 @@ enum dma_direction { #define DMA_SUPPORTS_DEV_TO_MEM BIT(2) #define DMA_SUPPORTS_DEV_TO_DEV BIT(3) -/* - * struct dma_ops - Driver model DMA operations - * - * The uclass interface is implemented by all DMA devices which use - * driver model. - */ -struct dma_ops { - /* - * Get the current timer count - * - * @dev: The DMA device - * @direction: direction of data transfer should be one from - enum dma_direction - * @dst: Destination pointer - * @src: Source pointer - * @len: Length of the data to be copied. - * @return: 0 if OK, -ve on error - */ - int (*transfer)(struct udevice *dev, int direction, void *dst, - void *src, size_t len); -}; - /* * struct dma_dev_priv - information about a device used by the uclass * @@ -58,6 +41,257 @@ struct dma_dev_priv { u32 supported; }; +#ifdef CONFIG_DMA_CHANNELS +/** + * A DMA is a feature of computer systems that allows certain hardware + * subsystems to access main system memory, independent of the CPU. + * DMA channels are typically generated externally to the HW module + * consuming them, by an entity this API calls a DMA provider. This API + * provides a standard means for drivers to enable and disable DMAs, and to + * copy, send and receive data using DMA. + * + * A driver that implements UCLASS_DMA is a DMA provider. A provider will + * often implement multiple separate DMAs, since the hardware it manages + * often has this capability. dma_uclass.h describes the interface which + * DMA providers must implement. + * + * DMA consumers/clients are the HW modules driven by the DMA channels. This + * header file describes the API used by drivers for those HW modules. + * + * DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking). + * Note. dma_send() is sync operation always - it'll start transfer and will + * poll for it to complete: + * - get/request dma channel + * struct dma dma_tx; + * ret = dma_get_by_name(common->dev, "tx0", &dma_tx); + * if (ret) ... + * + * - enable dma channel + * ret = dma_enable(&dma_tx); + * if (ret) ... + * + * - dma transmit DMA_MEM_TO_DEV. + * struct ti_drv_packet_data packet_data; + * + * packet_data.opt1 = val1; + * packet_data.opt2 = val2; + * ret = dma_send(&dma_tx, packet, length, &packet_data); + * if (ret) .. + * + * DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking). + * Note. dma_receive() is sync operation always - it'll start transfer + * (if required) and will poll for it to complete (or for any previously + * configured dev2mem transfer to complete): + * - get/request dma channel + * struct dma dma_rx; + * ret = dma_get_by_name(common->dev, "rx0", &dma_rx); + * if (ret) ... + * + * - enable dma channel + * ret = dma_enable(&dma_rx); + * if (ret) ... + * + * - dma receive DMA_DEV_TO_MEM. + * struct ti_drv_packet_data packet_data; + * + * len = dma_receive(&dma_rx, (void **)packet, &packet_data); + * if (ret < 0) ... + * + * DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on + * networking). Networking subsystem allows to configure and use few receive + * buffers (dev2mem), as Networking RX DMA channels usually implemented + * as streaming interface + * - get/request dma channel + * struct dma dma_rx; + * ret = dma_get_by_name(common->dev, "rx0", &dma_rx); + * if (ret) ... + * + * for (i = 0; i < RX_DESC_NUM; i++) { + * ret = dma_prepare_rcv_buf(&dma_rx, + * net_rx_packets[i], + * RX_BUF_SIZE); + * if (ret) ... + * } + * + * - enable dma channel + * ret = dma_enable(&dma_rx); + * if (ret) ... + * + * - dma receive DMA_DEV_TO_MEM. + * struct ti_drv_packet_data packet_data; + * + * len = dma_receive(&dma_rx, (void **)packet, &packet_data); + * if (ret < 0) .. + * + * -- process packet -- + * + * - return buffer back to DAM channel + * ret = dma_prepare_rcv_buf(&dma_rx, + * net_rx_packets[rx_next], + * RX_BUF_SIZE); + */ + +struct udevice; + +/** + * struct dma - A handle to (allowing control of) a single DMA. + * + * Clients provide storage for DMA handles. The content of the structure is + * managed solely by the DMA API and DMA drivers. A DMA struct is + * initialized by "get"ing the DMA struct. The DMA struct is passed to all + * other DMA APIs to identify which DMA channel to operate upon. + * + * @dev: The device which implements the DMA channel. + * @id: The DMA channel ID within the provider. + * + * Currently, the DMA API assumes that a single integer ID is enough to + * identify and configure any DMA channel for any DMA provider. If this + * assumption becomes invalid in the future, the struct could be expanded to + * either (a) add more fields to allow DMA providers to store additional + * information, or (b) replace the id field with an opaque pointer, which the + * provider would dynamically allocated during its .of_xlate op, and process + * during is .request op. This may require the addition of an extra op to clean + * up the allocation. + */ +struct dma { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA) +/** + * dma_get_by_index - Get/request a DMA by integer index. + * + * This looks up and requests a DMA. The index is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA indices to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @index: The index of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma); + +/** + * dma_get_by_name - Get/request a DMA by name. + * + * This looks up and requests a DMA. The name is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA names to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @name: The name of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma); +# else +static inline int dma_get_by_index(struct udevice *dev, int index, + struct dma *dma) +{ + return -ENOSYS; +} + +static inline int dma_get_by_name(struct udevice *dev, const char *name, + struct dma *dma) +{ + return -ENOSYS; +} +# endif + +/** + * dma_request - Request a DMA by provider-specific ID. + * + * This requests a DMA using a provider-specific ID. Generally, this function + * should not be used, since dma_get_by_index/name() provide an interface that + * better separates clients from intimate knowledge of DMA providers. + * However, this function may be useful in core SoC-specific code. + * + * @dev: The DMA provider device. + * @dma: A pointer to a DMA struct to initialize. The caller must + * have already initialized any field in this struct which the + * DMA provider uses to identify the DMA channel. + * @return 0 if OK, or a negative error code. + */ +int dma_request(struct udevice *dev, struct dma *dma); + +/** + * dma_free - Free a previously requested DMA. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int dma_free(struct dma *dma); + +/** + * dma_enable() - Enable (turn on) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_enable(struct dma *dma); + +/** + * dma_disable() - Disable (turn off) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_disable(struct dma *dma); + +/** + * dma_prepare_rcv_buf() - Prepare/add receive DMA buffer. + * + * It allows to implement zero-copy async DMA_DEV_TO_MEM (receive) transactions + * if supported by DMA providers. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @dst: The receive buffer pointer. + * @size: The receive buffer size + * @return zero on success, or -ve error code. + */ +int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size); + +/** + * dma_receive() - Receive a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @dst: The destination pointer. + * @metadata: DMA driver's channel specific data + * @return length of received data on success, or zero - no data, + * or -ve error code. + */ +int dma_receive(struct dma *dma, void **dst, void *metadata); + +/** + * dma_send() - Send a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @metadata: DMA driver's channel specific data + * @return zero on success, or -ve error code. + */ +int dma_send(struct dma *dma, void *src, size_t len, void *metadata); +#endif /* CONFIG_DMA_CHANNELS */ + /* * dma_get_device - get a DMA device which supports transfer * type of transfer_type diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h new file mode 100644 index 0000000000..86a8806e21 --- /dev/null +++ b/include/dt-bindings/clock/am3.h @@ -0,0 +1,227 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_AM3_H +#define __DT_BINDINGS_CLK_AM3_H + +#define AM3_CLKCTRL_OFFSET 0x0 +#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) + +/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ + +/* l4_per clocks */ +#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 +#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) +#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) +#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) +#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) +#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) +#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) +#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) +#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) +#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) +#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) +#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) +#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) +#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) +#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) +#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) +#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) +#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) +#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) +#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) +#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) +#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) +#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) +#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) +#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) +#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) +#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) +#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) +#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) +#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) +#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) +#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) +#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) +#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) +#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) +#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) +#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) +#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) +#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) +#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) +#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) +#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) +#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) +#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) +#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) +#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) +#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) +#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) +#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) +#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) +#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) +#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) +#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 +#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) +#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) +#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) +#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) +#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) +#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) +#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) +#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) +#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) +#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) +#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) +#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) + +/* mpu clocks */ +#define AM3_MPU_CLKCTRL_OFFSET 0x4 +#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) +#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 +#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) +#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 +#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) +#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) + +/* XXX: Compatibility part end */ + +/* l4ls clocks */ +#define AM3_L4LS_CLKCTRL_OFFSET 0x38 +#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) +#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) +#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) +#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) +#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) +#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) +#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) +#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) +#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) +#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) +#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) +#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) +#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) +#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) +#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) +#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) +#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) +#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) +#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) +#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) +#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) +#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) +#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) +#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) +#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) +#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) +#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) +#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) +#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) +#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) +#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) +#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) + +/* l3s clocks */ +#define AM3_L3S_CLKCTRL_OFFSET 0x1c +#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) +#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) +#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) +#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) +#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) +#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) + +/* l3 clocks */ +#define AM3_L3_CLKCTRL_OFFSET 0x24 +#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) +#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) +#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) +#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) +#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) +#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) +#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) +#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) +#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) +#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) +#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) + +/* l4hs clocks */ +#define AM3_L4HS_CLKCTRL_OFFSET 0x120 +#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) +#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) + +/* pruss_ocp clocks */ +#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 +#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) +#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) + +/* cpsw_125mhz clocks */ +#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) + +/* lcdc clocks */ +#define AM3_LCDC_CLKCTRL_OFFSET 0x18 +#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) +#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) + +/* clk_24mhz clocks */ +#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c +#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) +#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) +#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) +#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) +#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) +#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) +#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) +#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) +#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) + +/* l3_aon clocks */ +#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 +#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) +#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) + +/* l4_wkup_aon clocks */ +#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 +#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) +#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) + +/* mpu clocks */ +#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) + +#endif diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h new file mode 100644 index 0000000000..61955016a5 --- /dev/null +++ b/include/dt-bindings/clock/axg-aoclkc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK + +#define CLKID_AO_REMOTE 0 +#define CLKID_AO_I2C_MASTER 1 +#define CLKID_AO_I2C_SLAVE 2 +#define CLKID_AO_UART1 3 +#define CLKID_AO_UART2 4 +#define CLKID_AO_IR_BLASTER 5 +#define CLKID_AO_SAR_ADC 6 +#define CLKID_AO_CLK81 7 +#define CLKID_AO_SAR_ADC_SEL 8 +#define CLKID_AO_SAR_ADC_DIV 9 +#define CLKID_AO_SAR_ADC_CLK 10 +#define CLKID_AO_ALT_XTAL 11 + +#endif diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h new file mode 100644 index 0000000000..fd9c362099 --- /dev/null +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h new file mode 100644 index 0000000000..fd1f938c38 --- /dev/null +++ b/include/dt-bindings/clock/axg-clkc.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson-AXG clock tree IDs + * + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AXG_CLKC_H +#define __AXG_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_AUDIO_LOCKER 16 +#define CLKID_MIPI_DSI_HOST 17 +#define CLKID_ISA 18 +#define CLKID_PL301 19 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC0 21 +#define CLKID_I2C 22 +#define CLKID_RNG0 23 +#define CLKID_UART0 24 +#define CLKID_MIPI_DSI_PHY 25 +#define CLKID_SPICC1 26 +#define CLKID_PCIE_A 27 +#define CLKID_PCIE_B 28 +#define CLKID_HIU_IFACE 29 +#define CLKID_ASSIST_MISC 30 +#define CLKID_SD_EMMC_B 31 +#define CLKID_SD_EMMC_C 32 +#define CLKID_DMA 33 +#define CLKID_SPI 34 +#define CLKID_AUDIO 35 +#define CLKID_ETH 36 +#define CLKID_UART1 37 +#define CLKID_G2D 38 +#define CLKID_USB0 39 +#define CLKID_USB1 40 +#define CLKID_RESET 41 +#define CLKID_USB 42 +#define CLKID_AHB_ARB0 43 +#define CLKID_EFUSE 44 +#define CLKID_BOOT_ROM 45 +#define CLKID_AHB_DATA_BUS 46 +#define CLKID_AHB_CTRL_BUS 47 +#define CLKID_USB1_DDR_BRIDGE 48 +#define CLKID_USB0_DDR_BRIDGE 49 +#define CLKID_MMC_PCLK 50 +#define CLKID_VPU_INTR 51 +#define CLKID_SEC_AHB_AHB3_BRIDGE 52 +#define CLKID_GIC 53 +#define CLKID_AO_MEDIA_CPU 54 +#define CLKID_AO_AHB_SRAM 55 +#define CLKID_AO_AHB_BUS 56 +#define CLKID_AO_IFACE 57 +#define CLKID_AO_I2C 58 +#define CLKID_SD_EMMC_B_CLK0 59 +#define CLKID_SD_EMMC_C_CLK0 60 +#define CLKID_HIFI_PLL 69 +#define CLKID_PCIE_CML_EN0 79 +#define CLKID_PCIE_CML_EN1 80 +#define CLKID_MIPI_ENABLE 81 +#define CLKID_GEN_CLK 84 + +#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h index d5e13c5c2d..3f10448cef 100644 --- a/include/dt-bindings/clock/bcm6318-clock.h +++ b/include/dt-bindings/clock/bcm6318-clock.h @@ -33,4 +33,15 @@ #define BCM6318_CLK_AFE 29 #define BCM6318_CLK_QPROC 30 +#define BCM6318_UCLK_ADSL 0 +#define BCM6318_UCLK_ARB 1 +#define BCM6318_UCLK_MIPS 2 +#define BCM6318_UCLK_PCIE 3 +#define BCM6318_UCLK_PERIPH 4 +#define BCM6318_UCLK_PHYMIPS 5 +#define BCM6318_UCLK_ROBOSW 6 +#define BCM6318_UCLK_SAR 7 +#define BCM6318_UCLK_SDR 8 +#define BCM6318_UCLK_USB 9 + #endif /* __DT_BINDINGS_CLOCK_BCM6318_H */ diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 0000000000..73214c52c0 --- /dev/null +++ b/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h new file mode 100644 index 0000000000..71ced1593a --- /dev/null +++ b/include/dt-bindings/clock/mt7623-clk.h @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT2701_H +#define _DT_BINDINGS_CLK_MT2701_H + +/* TOPCKGEN */ +#define CLK_TOP_FCLKS_OFF 0 + +#define CLK_TOP_DPI 0 +#define CLK_TOP_DMPLL 1 +#define CLK_TOP_VENCPLL 2 +#define CLK_TOP_HDMI_0_PIX340M 3 +#define CLK_TOP_HDMI_0_DEEP340M 4 +#define CLK_TOP_HDMI_0_PLL340M 5 +#define CLK_TOP_HADDS2_FB 6 +#define CLK_TOP_WBG_DIG_416M 7 +#define CLK_TOP_DSI0_LNTC_DSI 8 +#define CLK_TOP_HDMI_SCL_RX 9 +#define CLK_TOP_32K_EXTERNAL 10 +#define CLK_TOP_HDMITX_CLKDIG_CTS 11 +#define CLK_TOP_AUD_EXT1 12 +#define CLK_TOP_AUD_EXT2 13 +#define CLK_TOP_NFI1X_PAD 14 + +#define CLK_TOP_SYSPLL 15 +#define CLK_TOP_SYSPLL_D2 16 +#define CLK_TOP_SYSPLL_D3 17 +#define CLK_TOP_SYSPLL_D5 18 +#define CLK_TOP_SYSPLL_D7 19 +#define CLK_TOP_SYSPLL1_D2 20 +#define CLK_TOP_SYSPLL1_D4 21 +#define CLK_TOP_SYSPLL1_D8 22 +#define CLK_TOP_SYSPLL1_D16 23 +#define CLK_TOP_SYSPLL2_D2 24 +#define CLK_TOP_SYSPLL2_D4 25 +#define CLK_TOP_SYSPLL2_D8 26 +#define CLK_TOP_SYSPLL3_D2 27 +#define CLK_TOP_SYSPLL3_D4 28 +#define CLK_TOP_SYSPLL4_D2 29 +#define CLK_TOP_SYSPLL4_D4 30 +#define CLK_TOP_UNIVPLL 31 +#define CLK_TOP_UNIVPLL_D2 32 +#define CLK_TOP_UNIVPLL_D3 33 +#define CLK_TOP_UNIVPLL_D5 34 +#define CLK_TOP_UNIVPLL_D7 35 +#define CLK_TOP_UNIVPLL_D26 36 +#define CLK_TOP_UNIVPLL_D52 37 +#define CLK_TOP_UNIVPLL_D108 38 +#define CLK_TOP_USB_PHY48M 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL1_D8 42 +#define CLK_TOP_UNIVPLL2_D2 43 +#define CLK_TOP_UNIVPLL2_D4 44 +#define CLK_TOP_UNIVPLL2_D8 45 +#define CLK_TOP_UNIVPLL2_D16 46 +#define CLK_TOP_UNIVPLL2_D32 47 +#define CLK_TOP_UNIVPLL3_D2 48 +#define CLK_TOP_UNIVPLL3_D4 49 +#define CLK_TOP_UNIVPLL3_D8 50 +#define CLK_TOP_MSDCPLL 51 +#define CLK_TOP_MSDCPLL_D2 52 +#define CLK_TOP_MSDCPLL_D4 53 +#define CLK_TOP_MSDCPLL_D8 54 +#define CLK_TOP_MMPLL 55 +#define CLK_TOP_MMPLL_D2 56 +#define CLK_TOP_DMPLL_D2 57 +#define CLK_TOP_DMPLL_D4 58 +#define CLK_TOP_DMPLL_X2 59 +#define CLK_TOP_TVDPLL 60 +#define CLK_TOP_TVDPLL_D2 61 +#define CLK_TOP_TVDPLL_D4 62 +#define CLK_TOP_VDECPLL 63 +#define CLK_TOP_TVD2PLL 64 +#define CLK_TOP_TVD2PLL_D2 65 +#define CLK_TOP_MIPIPLL 66 +#define CLK_TOP_MIPIPLL_D2 67 +#define CLK_TOP_MIPIPLL_D4 68 +#define CLK_TOP_HDMIPLL 69 +#define CLK_TOP_HDMIPLL_D2 70 +#define CLK_TOP_HDMIPLL_D3 71 +#define CLK_TOP_ARMPLL_1P3G 72 +#define CLK_TOP_AUDPLL 73 +#define CLK_TOP_AUDPLL_D4 74 +#define CLK_TOP_AUDPLL_D8 75 +#define CLK_TOP_AUDPLL_D16 76 +#define CLK_TOP_AUDPLL_D24 77 +#define CLK_TOP_AUD1PLL_98M 78 +#define CLK_TOP_AUD2PLL_90M 79 +#define CLK_TOP_HADDS2PLL_98M 80 +#define CLK_TOP_HADDS2PLL_294M 81 +#define CLK_TOP_ETHPLL_500M 82 +#define CLK_TOP_CLK26M_D8 83 +#define CLK_TOP_32K_INTERNAL 84 +#define CLK_TOP_AXISEL_D4 85 +#define CLK_TOP_8BDAC 86 + +#define CLK_TOP_AXI_SEL 87 +#define CLK_TOP_MEM_SEL 88 +#define CLK_TOP_DDRPHYCFG_SEL 89 +#define CLK_TOP_MM_SEL 90 +#define CLK_TOP_PWM_SEL 91 +#define CLK_TOP_VDEC_SEL 92 +#define CLK_TOP_MFG_SEL 93 +#define CLK_TOP_CAMTG_SEL 94 +#define CLK_TOP_UART_SEL 95 +#define CLK_TOP_SPI0_SEL 96 +#define CLK_TOP_USB20_SEL 97 +#define CLK_TOP_MSDC30_0_SEL 98 +#define CLK_TOP_MSDC30_1_SEL 99 +#define CLK_TOP_MSDC30_2_SEL 100 +#define CLK_TOP_AUDIO_SEL 101 +#define CLK_TOP_AUDINTBUS_SEL 102 +#define CLK_TOP_PMICSPI_SEL 103 +#define CLK_TOP_SCP_SEL 104 +#define CLK_TOP_DPI0_SEL 105 +#define CLK_TOP_DPI1_SEL 106 +#define CLK_TOP_TVE_SEL 107 +#define CLK_TOP_HDMI_SEL 108 +#define CLK_TOP_APLL_SEL 109 +#define CLK_TOP_RTC_SEL 110 +#define CLK_TOP_NFI2X_SEL 111 +#define CLK_TOP_EMMC_HCLK_SEL 112 +#define CLK_TOP_FLASH_SEL 113 +#define CLK_TOP_DI_SEL 114 +#define CLK_TOP_NR_SEL 115 +#define CLK_TOP_OSD_SEL 116 +#define CLK_TOP_HDMIRX_BIST_SEL 117 +#define CLK_TOP_INTDIR_SEL 118 +#define CLK_TOP_ASM_I_SEL 119 +#define CLK_TOP_ASM_M_SEL 120 +#define CLK_TOP_ASM_H_SEL 121 +#define CLK_TOP_MS_CARD_SEL 122 +#define CLK_TOP_ETHIF_SEL 123 +#define CLK_TOP_HDMIRX26_24_SEL 124 +#define CLK_TOP_MSDC30_3_SEL 125 +#define CLK_TOP_CMSYS_SEL 126 +#define CLK_TOP_SPI1_SEL 127 +#define CLK_TOP_SPI2_SEL 128 +#define CLK_TOP_8BDAC_SEL 129 +#define CLK_TOP_AUD2DVD_SEL 130 +#define CLK_TOP_PADMCLK_SEL 131 +#define CLK_TOP_AUD_MUX1_SEL 132 +#define CLK_TOP_AUD_MUX2_SEL 133 +#define CLK_TOP_AUDPLL_MUX_SEL 134 +#define CLK_TOP_AUD_K1_SRC_SEL 135 +#define CLK_TOP_AUD_K2_SRC_SEL 136 +#define CLK_TOP_AUD_K3_SRC_SEL 137 +#define CLK_TOP_AUD_K4_SRC_SEL 138 +#define CLK_TOP_AUD_K5_SRC_SEL 139 +#define CLK_TOP_AUD_K6_SRC_SEL 140 + +#define CLK_TOP_AUD_EXTCK1_DIV 141 +#define CLK_TOP_AUD_EXTCK2_DIV 142 +#define CLK_TOP_AUD_MUX1_DIV 143 +#define CLK_TOP_AUD_MUX2_DIV 144 +#define CLK_TOP_AUD_K1_SRC_DIV 145 +#define CLK_TOP_AUD_K2_SRC_DIV 146 +#define CLK_TOP_AUD_K3_SRC_DIV 147 +#define CLK_TOP_AUD_K4_SRC_DIV 148 +#define CLK_TOP_AUD_K5_SRC_DIV 149 +#define CLK_TOP_AUD_K6_SRC_DIV 150 +#define CLK_TOP_AUD_48K_TIMING 151 +#define CLK_TOP_AUD_44K_TIMING 152 +#define CLK_TOP_AUD_I2S1_MCLK 153 +#define CLK_TOP_AUD_I2S2_MCLK 154 +#define CLK_TOP_AUD_I2S3_MCLK 155 +#define CLK_TOP_AUD_I2S4_MCLK 156 +#define CLK_TOP_AUD_I2S5_MCLK 157 +#define CLK_TOP_AUD_I2S6_MCLK 158 +#define CLK_TOP_NR 159 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_TVDPLL 5 +#define CLK_APMIXED_AUD1PLL 6 +#define CLK_APMIXED_TRGPLL 7 +#define CLK_APMIXED_ETHPLL 8 +#define CLK_APMIXED_VDECPLL 9 +#define CLK_APMIXED_HADDS2PLL 10 +#define CLK_APMIXED_AUD2PLL 11 +#define CLK_APMIXED_TVD2PLL 12 +#define CLK_APMIXED_NR 13 + +/* INFRACFG */ +#define CLK_INFRA_DBG 0 +#define CLK_INFRA_SMI 1 +#define CLK_INFRA_QAXI_CM4 2 +#define CLK_INFRA_AUD_SPLIN_B 3 +#define CLK_INFRA_AUDIO 4 +#define CLK_INFRA_EFUSE 5 +#define CLK_INFRA_L2C_SRAM 6 +#define CLK_INFRA_M4U 7 +#define CLK_INFRA_CONNMCU 8 +#define CLK_INFRA_TRNG 9 +#define CLK_INFRA_RAMBUFIF 10 +#define CLK_INFRA_CPUM 11 +#define CLK_INFRA_KP 12 +#define CLK_INFRA_CEC 13 +#define CLK_INFRA_IRRX 14 +#define CLK_INFRA_PMICSPI 15 +#define CLK_INFRA_PMICWRAP 16 +#define CLK_INFRA_DDCCI 17 +#define CLK_INFRA_CPUSEL 18 +#define CLK_INFRA_NR 19 + +/* PERICFG */ +#define CLK_PERI_NFI 0 +#define CLK_PERI_THERM 1 +#define CLK_PERI_PWM1 2 +#define CLK_PERI_PWM2 3 +#define CLK_PERI_PWM3 4 +#define CLK_PERI_PWM4 5 +#define CLK_PERI_PWM5 6 +#define CLK_PERI_PWM6 7 +#define CLK_PERI_PWM7 8 +#define CLK_PERI_PWM 9 +#define CLK_PERI_USB0 10 +#define CLK_PERI_USB1 11 +#define CLK_PERI_AP_DMA 12 +#define CLK_PERI_MSDC30_0 13 +#define CLK_PERI_MSDC30_1 14 +#define CLK_PERI_MSDC30_2 15 +#define CLK_PERI_MSDC30_3 16 +#define CLK_PERI_MSDC50_3 17 +#define CLK_PERI_NLI 18 +#define CLK_PERI_UART0 19 +#define CLK_PERI_UART1 20 +#define CLK_PERI_UART2 21 +#define CLK_PERI_UART3 22 +#define CLK_PERI_BTIF 23 +#define CLK_PERI_I2C0 24 +#define CLK_PERI_I2C1 25 +#define CLK_PERI_I2C2 26 +#define CLK_PERI_I2C3 27 +#define CLK_PERI_AUXADC 28 +#define CLK_PERI_SPI0 39 +#define CLK_PERI_ETH 30 +#define CLK_PERI_USB0_MCU 31 + +#define CLK_PERI_USB1_MCU 32 +#define CLK_PERI_USB_SLV 33 +#define CLK_PERI_GCPU 34 +#define CLK_PERI_NFI_ECC 35 +#define CLK_PERI_NFI_PAD 36 +#define CLK_PERI_FLASH 37 +#define CLK_PERI_HOST89_INT 38 +#define CLK_PERI_HOST89_SPI 39 +#define CLK_PERI_HOST89_DVD 40 +#define CLK_PERI_SPI1 41 +#define CLK_PERI_SPI2 42 +#define CLK_PERI_FCI 43 +#define CLK_PERI_NR 44 + +/* AUDIO */ +#define CLK_AUD_AFE 0 +#define CLK_AUD_LRCK_DETECT 1 +#define CLK_AUD_I2S 2 +#define CLK_AUD_APLL_TUNER 3 +#define CLK_AUD_HDMI 4 +#define CLK_AUD_SPDF 5 +#define CLK_AUD_SPDF2 6 +#define CLK_AUD_APLL 7 +#define CLK_AUD_TML 8 +#define CLK_AUD_AHB_IDLE_EXT 9 +#define CLK_AUD_AHB_IDLE_INT 10 + +#define CLK_AUD_I2SIN1 11 +#define CLK_AUD_I2SIN2 12 +#define CLK_AUD_I2SIN3 13 +#define CLK_AUD_I2SIN4 14 +#define CLK_AUD_I2SIN5 15 +#define CLK_AUD_I2SIN6 16 +#define CLK_AUD_I2SO1 17 +#define CLK_AUD_I2SO2 18 +#define CLK_AUD_I2SO3 19 +#define CLK_AUD_I2SO4 20 +#define CLK_AUD_I2SO5 21 +#define CLK_AUD_I2SO6 22 +#define CLK_AUD_ASRCI1 23 +#define CLK_AUD_ASRCI2 24 +#define CLK_AUD_ASRCO1 25 +#define CLK_AUD_ASRCO2 26 +#define CLK_AUD_ASRC11 27 +#define CLK_AUD_ASRC12 28 +#define CLK_AUD_HDMIRX 29 +#define CLK_AUD_INTDIR 30 +#define CLK_AUD_A1SYS 31 +#define CLK_AUD_A2SYS 32 +#define CLK_AUD_AFE_CONN 33 +#define CLK_AUD_AFE_PCMIF 34 +#define CLK_AUD_AFE_MRGIF 35 + +#define CLK_AUD_MMIF_UL1 36 +#define CLK_AUD_MMIF_UL2 37 +#define CLK_AUD_MMIF_UL3 38 +#define CLK_AUD_MMIF_UL4 39 +#define CLK_AUD_MMIF_UL5 40 +#define CLK_AUD_MMIF_UL6 41 +#define CLK_AUD_MMIF_DL1 42 +#define CLK_AUD_MMIF_DL2 43 +#define CLK_AUD_MMIF_DL3 44 +#define CLK_AUD_MMIF_DL4 45 +#define CLK_AUD_MMIF_DL5 46 +#define CLK_AUD_MMIF_DL6 47 +#define CLK_AUD_MMIF_DLMCH 48 +#define CLK_AUD_MMIF_ARB1 49 +#define CLK_AUD_MMIF_AWB1 50 +#define CLK_AUD_MMIF_AWB2 51 +#define CLK_AUD_MMIF_DAI 52 + +#define CLK_AUD_DMIC1 53 +#define CLK_AUD_DMIC2 54 +#define CLK_AUD_ASRCI3 55 +#define CLK_AUD_ASRCI4 56 +#define CLK_AUD_ASRCI5 57 +#define CLK_AUD_ASRCI6 58 +#define CLK_AUD_ASRCO3 59 +#define CLK_AUD_ASRCO4 60 +#define CLK_AUD_ASRCO5 61 +#define CLK_AUD_ASRCO6 62 +#define CLK_AUD_MEM_ASRC1 63 +#define CLK_AUD_MEM_ASRC2 64 +#define CLK_AUD_MEM_ASRC3 65 +#define CLK_AUD_MEM_ASRC4 66 +#define CLK_AUD_MEM_ASRC5 67 +#define CLK_AUD_DSD_ENC 68 +#define CLK_AUD_ASRC_BRG 60 +#define CLK_AUD_NR 70 + +/* MMSYS */ +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CMDQ 2 +#define CLK_MM_MUTEX 3 +#define CLK_MM_DISP_COLOR 4 +#define CLK_MM_DISP_BLS 5 +#define CLK_MM_DISP_WDMA 6 +#define CLK_MM_DISP_RDMA 7 +#define CLK_MM_DISP_OVL 8 +#define CLK_MM_MDP_TDSHP 9 +#define CLK_MM_MDP_WROT 10 +#define CLK_MM_MDP_WDMA 11 +#define CLK_MM_MDP_RSZ1 12 +#define CLK_MM_MDP_RSZ0 13 +#define CLK_MM_MDP_RDMA 14 +#define CLK_MM_MDP_BLS_26M 15 +#define CLK_MM_CAM_MDP 16 +#define CLK_MM_FAKE_ENG 17 +#define CLK_MM_MUTEX_32K 18 +#define CLK_MM_DISP_RDMA1 19 +#define CLK_MM_DISP_UFOE 20 + +#define CLK_MM_DSI_ENGINE 21 +#define CLK_MM_DSI_DIG 22 +#define CLK_MM_DPI_DIGL 23 +#define CLK_MM_DPI_ENGINE 24 +#define CLK_MM_DPI1_DIGL 25 +#define CLK_MM_DPI1_ENGINE 26 +#define CLK_MM_TVE_OUTPUT 27 +#define CLK_MM_TVE_INPUT 28 +#define CLK_MM_HDMI_PIXEL 29 +#define CLK_MM_HDMI_PLL 30 +#define CLK_MM_HDMI_AUDIO 31 +#define CLK_MM_HDMI_SPDIF 32 +#define CLK_MM_TVE_FMM 33 +#define CLK_MM_NR 34 + +/* IMGSYS */ +#define CLK_IMG_SMI_COMM 0 +#define CLK_IMG_RESZ 1 +#define CLK_IMG_JPGDEC_SMI 2 +#define CLK_IMG_JPGDEC 3 +#define CLK_IMG_VENC_LT 4 +#define CLK_IMG_VENC 5 +#define CLK_IMG_NR 6 + +/* VDEC */ +#define CLK_VDEC_CKGEN 0 +#define CLK_VDEC_LARB 1 +#define CLK_VDEC_NR 2 + +/* HIFSYS */ +#define CLK_HIFSYS_USB0PHY 0 +#define CLK_HIFSYS_USB1PHY 1 +#define CLK_HIFSYS_PCIE0 2 +#define CLK_HIFSYS_PCIE1 3 +#define CLK_HIFSYS_PCIE2 4 +#define CLK_HIFSYS_NR 5 + +/* ETHSYS */ +#define CLK_ETHSYS_HSDMA 0 +#define CLK_ETHSYS_ESW 1 +#define CLK_ETHSYS_GP2 2 +#define CLK_ETHSYS_GP1 3 +#define CLK_ETHSYS_PCM 4 +#define CLK_ETHSYS_GDMA 5 +#define CLK_ETHSYS_I2S 6 +#define CLK_ETHSYS_CRYPTO 7 +#define CLK_ETHSYS_NR 8 + +/* G3DSYS */ +#define CLK_G3DSYS_CORE 0 +#define CLK_G3DSYS_NR 1 + +#endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h new file mode 100644 index 0000000000..0bbfbfa744 --- /dev/null +++ b/include/dt-bindings/clock/mt7629-clk.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT7629_H +#define _DT_BINDINGS_CLK_MT7629_H + +/* TOPCKGEN */ +#define CLK_TOP_FCLKS_OFF 0 + +#define CLK_TOP_TO_U2_PHY 0 +#define CLK_TOP_TO_U2_PHY_1P 1 +#define CLK_TOP_PCIE0_PIPE_EN 2 +#define CLK_TOP_PCIE1_PIPE_EN 3 +#define CLK_TOP_SSUSB_TX250M 4 +#define CLK_TOP_SSUSB_EQ_RX250M 5 +#define CLK_TOP_SSUSB_CDR_REF 6 +#define CLK_TOP_SSUSB_CDR_FB 7 +#define CLK_TOP_SATA_ASIC 8 +#define CLK_TOP_SATA_RBC 9 + +#define CLK_TOP_TO_USB3_SYS 10 +#define CLK_TOP_P1_1MHZ 11 +#define CLK_TOP_4MHZ 12 +#define CLK_TOP_P0_1MHZ 13 +#define CLK_TOP_ETH_500M 14 +#define CLK_TOP_TXCLK_SRC_PRE 15 +#define CLK_TOP_RTC 16 +#define CLK_TOP_PWM_QTR_26M 17 +#define CLK_TOP_CPUM_TCK_IN 18 +#define CLK_TOP_TO_USB3_DA_TOP 19 +#define CLK_TOP_MEMPLL 20 +#define CLK_TOP_DMPLL 21 +#define CLK_TOP_DMPLL_D4 22 +#define CLK_TOP_DMPLL_D8 23 +#define CLK_TOP_SYSPLL_D2 24 +#define CLK_TOP_SYSPLL1_D2 25 +#define CLK_TOP_SYSPLL1_D4 26 +#define CLK_TOP_SYSPLL1_D8 27 +#define CLK_TOP_SYSPLL1_D16 28 +#define CLK_TOP_SYSPLL2_D2 29 +#define CLK_TOP_SYSPLL2_D4 30 +#define CLK_TOP_SYSPLL2_D8 31 +#define CLK_TOP_SYSPLL_D5 32 +#define CLK_TOP_SYSPLL3_D2 33 +#define CLK_TOP_SYSPLL3_D4 34 +#define CLK_TOP_SYSPLL_D7 35 +#define CLK_TOP_SYSPLL4_D2 36 +#define CLK_TOP_SYSPLL4_D4 37 +#define CLK_TOP_SYSPLL4_D16 38 +#define CLK_TOP_UNIVPLL 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL1_D8 42 +#define CLK_TOP_UNIVPLL_D3 43 +#define CLK_TOP_UNIVPLL2_D2 44 +#define CLK_TOP_UNIVPLL2_D4 45 +#define CLK_TOP_UNIVPLL2_D8 46 +#define CLK_TOP_UNIVPLL2_D16 47 +#define CLK_TOP_UNIVPLL_D5 48 +#define CLK_TOP_UNIVPLL3_D2 49 +#define CLK_TOP_UNIVPLL3_D4 50 +#define CLK_TOP_UNIVPLL3_D16 51 +#define CLK_TOP_UNIVPLL_D7 52 +#define CLK_TOP_UNIVPLL_D80_D4 53 +#define CLK_TOP_UNIV48M 54 +#define CLK_TOP_SGMIIPLL_D2 55 +#define CLK_TOP_CLKXTAL_D4 56 +#define CLK_TOP_HD_FAXI 57 +#define CLK_TOP_FAXI 58 +#define CLK_TOP_F_FAUD_INTBUS 59 +#define CLK_TOP_AP2WBHIF_HCLK 60 +#define CLK_TOP_10M_INFRAO 61 +#define CLK_TOP_MSDC30_1 62 +#define CLK_TOP_SPI 63 +#define CLK_TOP_SF 64 +#define CLK_TOP_FLASH 65 +#define CLK_TOP_TO_USB3_REF 66 +#define CLK_TOP_TO_USB3_MCU 67 +#define CLK_TOP_TO_USB3_DMA 68 +#define CLK_TOP_FROM_TOP_AHB 69 +#define CLK_TOP_FROM_TOP_AXI 70 +#define CLK_TOP_PCIE1_MAC_EN 71 +#define CLK_TOP_PCIE0_MAC_EN 72 + +#define CLK_TOP_AXI_SEL 73 +#define CLK_TOP_MEM_SEL 74 +#define CLK_TOP_DDRPHYCFG_SEL 75 +#define CLK_TOP_ETH_SEL 76 +#define CLK_TOP_PWM_SEL 77 +#define CLK_TOP_F10M_REF_SEL 78 +#define CLK_TOP_NFI_INFRA_SEL 79 +#define CLK_TOP_FLASH_SEL 80 +#define CLK_TOP_UART_SEL 81 +#define CLK_TOP_SPI0_SEL 82 +#define CLK_TOP_SPI1_SEL 83 +#define CLK_TOP_MSDC50_0_SEL 84 +#define CLK_TOP_MSDC30_0_SEL 85 +#define CLK_TOP_MSDC30_1_SEL 86 +#define CLK_TOP_AP2WBMCU_SEL 87 +#define CLK_TOP_AP2WBHIF_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_AUD_INTBUS_SEL 90 +#define CLK_TOP_PMICSPI_SEL 91 +#define CLK_TOP_SCP_SEL 92 +#define CLK_TOP_ATB_SEL 93 +#define CLK_TOP_HIF_SEL 94 +#define CLK_TOP_SATA_SEL 95 +#define CLK_TOP_U2_SEL 96 +#define CLK_TOP_AUD1_SEL 97 +#define CLK_TOP_AUD2_SEL 98 +#define CLK_TOP_IRRX_SEL 99 +#define CLK_TOP_IRTX_SEL 100 +#define CLK_TOP_SATA_MCU_SEL 101 +#define CLK_TOP_PCIE0_MCU_SEL 102 +#define CLK_TOP_PCIE1_MCU_SEL 103 +#define CLK_TOP_SSUSB_MCU_SEL 104 +#define CLK_TOP_CRYPTO_SEL 105 +#define CLK_TOP_SGMII_REF_1_SEL 106 +#define CLK_TOP_10M_SEL 107 +#define CLK_TOP_NR_CLK 108 + +/* INFRACFG */ +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_TRNG_PD 2 +#define CLK_INFRA_DEVAPC_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_SEJ_PD 5 +#define CLK_INFRA_NR_CLK 6 + +/* PERICFG */ +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_PWM1_PD 1 +#define CLK_PERI_PWM2_PD 2 +#define CLK_PERI_PWM3_PD 3 +#define CLK_PERI_PWM4_PD 4 +#define CLK_PERI_PWM5_PD 5 +#define CLK_PERI_PWM6_PD 6 +#define CLK_PERI_PWM7_PD 7 +#define CLK_PERI_PWM_PD 8 +#define CLK_PERI_AP_DMA_PD 9 +#define CLK_PERI_MSDC30_1_PD 10 +#define CLK_PERI_UART0_PD 11 +#define CLK_PERI_UART1_PD 12 +#define CLK_PERI_UART2_PD 13 +#define CLK_PERI_UART3_PD 14 +#define CLK_PERI_BTIF_PD 15 +#define CLK_PERI_I2C0_PD 16 +#define CLK_PERI_SPI0_PD 17 +#define CLK_PERI_SNFI_PD 18 +#define CLK_PERI_NFI_PD 19 +#define CLK_PERI_NFIECC_PD 20 +#define CLK_PERI_FLASH_PD 21 +#define CLK_PERI_NR_CLK 22 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIV2PLL 2 +#define CLK_APMIXED_ETH1PLL 3 +#define CLK_APMIXED_ETH2PLL 4 +#define CLK_APMIXED_SGMIPLL 5 +#define CLK_APMIXED_NR_CLK 6 + +/* SSUSBSYS */ +#define CLK_SSUSB_U2_PHY_1P_EN 0 +#define CLK_SSUSB_U2_PHY_EN 1 +#define CLK_SSUSB_REF_EN 2 +#define CLK_SSUSB_SYS_EN 3 +#define CLK_SSUSB_MCU_EN 4 +#define CLK_SSUSB_DMA_EN 5 +#define CLK_SSUSB_NR_CLK 6 + +/* PCIESYS */ +#define CLK_PCIE_P1_AUX_EN 0 +#define CLK_PCIE_P1_OBFF_EN 1 +#define CLK_PCIE_P1_AHB_EN 2 +#define CLK_PCIE_P1_AXI_EN 3 +#define CLK_PCIE_P1_MAC_EN 4 +#define CLK_PCIE_P1_PIPE_EN 5 +#define CLK_PCIE_P0_AUX_EN 6 +#define CLK_PCIE_P0_OBFF_EN 7 +#define CLK_PCIE_P0_AHB_EN 8 +#define CLK_PCIE_P0_AXI_EN 9 +#define CLK_PCIE_P0_MAC_EN 10 +#define CLK_PCIE_P0_PIPE_EN 11 +#define CLK_PCIE_NR_CLK 12 + +/* ETHSYS */ +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_GP0_EN 3 +#define CLK_ETH_ESW_EN 4 +#define CLK_ETH_NR_CLK 5 + +/* SGMIISYS */ +#define CLK_SGMII_TX_EN 0 +#define CLK_SGMII_RX_EN 1 +#define CLK_SGMII_CDR_REF 2 +#define CLK_SGMII_CDR_FB 3 +#define CLK_SGMII_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7629_H */ diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h new file mode 100644 index 0000000000..6d3b5a9a60 --- /dev/null +++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ + +#include + +/* r8a77965 CPG Core Clocks */ +#define R8A77965_CLK_Z 0 +#define R8A77965_CLK_ZR 1 +#define R8A77965_CLK_ZG 2 +#define R8A77965_CLK_ZTR 3 +#define R8A77965_CLK_ZTRD2 4 +#define R8A77965_CLK_ZT 5 +#define R8A77965_CLK_ZX 6 +#define R8A77965_CLK_S0D1 7 +#define R8A77965_CLK_S0D2 8 +#define R8A77965_CLK_S0D3 9 +#define R8A77965_CLK_S0D4 10 +#define R8A77965_CLK_S0D6 11 +#define R8A77965_CLK_S0D8 12 +#define R8A77965_CLK_S0D12 13 +#define R8A77965_CLK_S1D1 14 +#define R8A77965_CLK_S1D2 15 +#define R8A77965_CLK_S1D4 16 +#define R8A77965_CLK_S2D1 17 +#define R8A77965_CLK_S2D2 18 +#define R8A77965_CLK_S2D4 19 +#define R8A77965_CLK_S3D1 20 +#define R8A77965_CLK_S3D2 21 +#define R8A77965_CLK_S3D4 22 +#define R8A77965_CLK_LB 23 +#define R8A77965_CLK_CL 24 +#define R8A77965_CLK_ZB3 25 +#define R8A77965_CLK_ZB3D2 26 +#define R8A77965_CLK_CR 27 +#define R8A77965_CLK_CRD2 28 +#define R8A77965_CLK_SD0H 29 +#define R8A77965_CLK_SD0 30 +#define R8A77965_CLK_SD1H 31 +#define R8A77965_CLK_SD1 32 +#define R8A77965_CLK_SD2H 33 +#define R8A77965_CLK_SD2 34 +#define R8A77965_CLK_SD3H 35 +#define R8A77965_CLK_SD3 36 +#define R8A77965_CLK_SSP2 37 +#define R8A77965_CLK_SSP1 38 +#define R8A77965_CLK_SSPRS 39 +#define R8A77965_CLK_RPC 40 +#define R8A77965_CLK_RPCD2 41 +#define R8A77965_CLK_MSO 42 +#define R8A77965_CLK_CANFD 43 +#define R8A77965_CLK_HDMI 44 +#define R8A77965_CLK_CSI0 45 +#define R8A77965_CLK_CP 46 +#define R8A77965_CLK_CPEX 47 +#define R8A77965_CLK_R 48 +#define R8A77965_CLK_OSC 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h index c806fce449..a596a482f3 100644 --- a/include/dt-bindings/clock/r8a77990-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h @@ -56,8 +56,7 @@ #define R8A77990_CLK_LV0 45 #define R8A77990_CLK_LV1 46 #define R8A77990_CLK_CSI0 47 -#define R8A77990_CLK_POST3 48 -#define R8A77990_CLK_CP 49 -#define R8A77990_CLK_CPEX 50 +#define R8A77990_CLK_CP 48 +#define R8A77990_CLK_CPEX 49 #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index 9219a50a24..10ed9d140f 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -14,7 +14,6 @@ #define ARMCLK 3 /* sclk gates (special clocks) */ -#define SCLK_MAC 64 #define SCLK_SPI0 65 #define SCLK_NANDC 67 #define SCLK_SDMMC 68 @@ -35,20 +34,77 @@ #define SCLK_SDMMC_SAMPLE 84 #define SCLK_SDIO_SAMPLE 85 #define SCLK_EMMC_SAMPLE 86 -#define SCLK_MAC_RX 87 -#define SCLK_MAC_TX 88 -#define SCLK_MACREF 89 -#define SCLK_MACREF_OUT 90 -#define SCLK_SARADC 91 +#define SCLK_VENC_CORE 87 +#define SCLK_HEVC_CORE 88 +#define SCLK_HEVC_CABAC 89 +#define SCLK_PWM0_PMU 90 +#define SCLK_I2C0_PMU 91 +#define SCLK_WIFI 92 +#define SCLK_CIFOUT 93 +#define SCLK_MIPI_CSI_OUT 94 +#define SCLK_CIF0 95 +#define SCLK_CIF1 96 +#define SCLK_CIF2 97 +#define SCLK_CIF3 98 +#define SCLK_DSP 99 +#define SCLK_DSP_IOP 100 +#define SCLK_DSP_EPP 101 +#define SCLK_DSP_EDP 102 +#define SCLK_DSP_EDAP 103 +#define SCLK_CVBS_HOST 104 +#define SCLK_HDMI_SFR 105 +#define SCLK_HDMI_CEC 106 +#define SCLK_CRYPTO 107 +#define SCLK_SPI 108 +#define SCLK_SARADC 109 +#define SCLK_TSADC 110 +#define SCLK_MAC_PRE 111 +#define SCLK_MAC 112 +#define SCLK_MAC_RX 113 +#define SCLK_MAC_REF 114 +#define SCLK_MAC_REFOUT 115 +#define SCLK_DSP_PFM 116 +#define SCLK_RGA 117 +#define SCLK_I2C1 118 +#define SCLK_I2C2 119 +#define SCLK_I2C3 120 +#define SCLK_PWM 121 +#define SCLK_ISP 122 +#define SCLK_USBPHY 123 +#define SCLK_I2S0_SRC 124 +#define SCLK_I2S1_SRC 125 +#define SCLK_I2S2_SRC 126 +#define SCLK_UART0_SRC 127 +#define SCLK_UART1_SRC 128 +#define SCLK_UART2_SRC 129 +#define SCLK_MAC_TX 130 +#define SCLK_MACREF 131 +#define SCLK_MACREF_OUT 132 +#define DCLK_VOP_SRC 185 +#define DCLK_HDMIPHY 186 +#define DCLK_VOP 187 /* aclk gates */ #define ACLK_DMAC 192 #define ACLK_PRE 193 #define ACLK_CORE 194 #define ACLK_ENMCORE 195 -#define ACLK_GMAC 196 - +#define ACLK_RKVENC 196 +#define ACLK_RKVDEC 197 +#define ACLK_VPU 198 +#define ACLK_CIF0 199 +#define ACLK_VIO0 200 +#define ACLK_VIO1 201 +#define ACLK_VOP 202 +#define ACLK_IEP 203 +#define ACLK_RGA 204 +#define ACLK_ISP 205 +#define ACLK_CIF1 206 +#define ACLK_CIF2 207 +#define ACLK_CIF3 208 +#define ACLK_PERI 209 +#define ACLK_GMAC 210 /* pclk gates */ #define PCLK_GPIO1 256 @@ -67,12 +123,24 @@ #define PCLK_PWM 269 #define PCLK_TIMER 270 #define PCLK_PERI 271 -#define PCLK_GMAC 272 -#define PCLK_SARADC 273 +#define PCLK_GPIO0_PMU 272 +#define PCLK_I2C0_PMU 273 +#define PCLK_PWM0_PMU 274 +#define PCLK_ISP 275 +#define PCLK_VIO 276 +#define PCLK_MIPI_DSI 277 +#define PCLK_HDMI_CTRL 278 +#define PCLK_SARADC 279 +#define PCLK_DSP_CFG 280 +#define PCLK_BUS 281 +#define PCLK_EFUSE0 282 +#define PCLK_EFUSE1 283 +#define PCLK_WDT 284 +#define PCLK_GMAC 285 /* hclk gates */ #define HCLK_I2S0_8CH 320 -#define HCLK_I2S1_8CH 321 +#define HCLK_I2S1_2CH 321 #define HCLK_I2S2_2CH 322 #define HCLK_NANDC 323 #define HCLK_SDMMC 324 @@ -80,20 +148,37 @@ #define HCLK_EMMC 326 #define HCLK_PERI 327 #define HCLK_SFC 328 +#define HCLK_RKVENC 329 +#define HCLK_RKVDEC 330 +#define HCLK_CIF0 331 +#define HCLK_VIO 332 +#define HCLK_VOP 333 +#define HCLK_IEP 334 +#define HCLK_RGA 335 +#define HCLK_ISP 336 +#define HCLK_CRYPTO_MST 337 +#define HCLK_CRYPTO_SLV 338 +#define HCLK_HOST0 339 +#define HCLK_OTG 340 +#define HCLK_CIF1 341 +#define HCLK_CIF2 342 +#define HCLK_CIF3 343 +#define HCLK_BUS 344 +#define HCLK_VPU 345 -#define CLK_NR_CLKS (HCLK_SFC + 1) +#define CLK_NR_CLKS (HCLK_VPU + 1) /* reset id */ -#define SRST_CORE_PO_AD 0 +#define SRST_CORE_PO_AD 0 #define SRST_CORE_AD 1 #define SRST_L2_AD 2 -#define SRST_CPU_NIU_AD 3 +#define SRST_CPU_NIU_AD 3 #define SRST_CORE_PO 4 #define SRST_CORE 5 -#define SRST_L2 6 +#define SRST_L2 6 #define SRST_CORE_DBG 8 #define PRST_DBG 9 -#define RST_DAP 10 +#define RST_DAP 10 #define PRST_DBG_NIU 11 #define ARST_STRC_SYS_AD 15 @@ -160,9 +245,9 @@ #define HRST_SYSBUS 75 #define PRST_USBGRF 76 -#define ARST_PERIPH_NIU 80 -#define HRST_PERIPH_NIU 81 -#define PRST_PERIPH_NIU 82 +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 #define HRST_PERIPH 83 #define HRST_SDMMC 84 #define HRST_SDIO 85 @@ -180,7 +265,7 @@ #define HRST_HOST0_AUX 96 #define HRST_HOST0_ARB 97 #define SRST_HOST0_EHCIPHY 98 -#define SRST_HOST0_UTMI 99 +#define SRST_HOST0_UTMI 99 #define SRST_USBPOR 100 #define SRST_UTMI0 101 #define SRST_UTMI1 102 @@ -227,21 +312,21 @@ #define HRST_VPU_NIU 141 #define ARST_VPU 142 #define HRST_VPU 143 -#define ARST_RKVDEC_NIU 144 -#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 #define ARST_RKVDEC 146 #define HRST_RKVDEC 147 #define SRST_RKVDEC_CABAC 148 #define SRST_RKVDEC_CORE 149 -#define ARST_RKVENC_NIU 150 -#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 #define ARST_RKVENC 152 #define HRST_RKVENC 153 #define SRST_RKVENC_CORE 154 #define SRST_DSP_CORE 156 #define SRST_DSP_SYS 157 -#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_GLOBAL 158 #define SRST_DSP_OECM 159 #define PRST_DSP_IOP_NIU 160 #define ARST_DSP_EPP_NIU 161 @@ -259,7 +344,7 @@ #define SRST_PMU_I2C0 173 #define PRST_PMU_I2C0 174 #define PRST_PMU_GPIO0 175 -#define PRST_PMU_INTMEM 176 +#define PRST_PMU_INTMEM 176 #define PRST_PMU_PWM0 177 #define SRST_PMU_PWM0 178 #define PRST_PMU_GRF 179 diff --git a/include/dt-bindings/dma/bcm6318-dma.h b/include/dt-bindings/dma/bcm6318-dma.h new file mode 100644 index 0000000000..ad7c5ac2df --- /dev/null +++ b/include/dt-bindings/dma/bcm6318-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6318_H +#define __DT_BINDINGS_DMA_BCM6318_H + +#define BCM6318_DMA_ENETSW_RX 0 +#define BCM6318_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6318_H */ diff --git a/include/dt-bindings/dma/bcm63268-dma.h b/include/dt-bindings/dma/bcm63268-dma.h new file mode 100644 index 0000000000..7d027119e6 --- /dev/null +++ b/include/dt-bindings/dma/bcm63268-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM63268_H +#define __DT_BINDINGS_DMA_BCM63268_H + +#define BCM63268_DMA_ENETSW_RX 0 +#define BCM63268_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM63268_H */ diff --git a/include/dt-bindings/dma/bcm6328-dma.h b/include/dt-bindings/dma/bcm6328-dma.h new file mode 100644 index 0000000000..7494df2feb --- /dev/null +++ b/include/dt-bindings/dma/bcm6328-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6328_H +#define __DT_BINDINGS_DMA_BCM6328_H + +#define BCM6328_DMA_ENETSW_RX 0 +#define BCM6328_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6328_H */ diff --git a/include/dt-bindings/dma/bcm6338-dma.h b/include/dt-bindings/dma/bcm6338-dma.h new file mode 100644 index 0000000000..f2e0b20444 --- /dev/null +++ b/include/dt-bindings/dma/bcm6338-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6338_H +#define __DT_BINDINGS_DMA_BCM6338_H + +#define BCM6338_DMA_ENET_RX 0 +#define BCM6338_DMA_ENET_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6338_H */ diff --git a/include/dt-bindings/dma/bcm6348-dma.h b/include/dt-bindings/dma/bcm6348-dma.h new file mode 100644 index 0000000000..36c2ffd412 --- /dev/null +++ b/include/dt-bindings/dma/bcm6348-dma.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6348_H +#define __DT_BINDINGS_DMA_BCM6348_H + +#define BCM6348_DMA_ENET0_RX 0 +#define BCM6348_DMA_ENET0_TX 1 +#define BCM6348_DMA_ENET1_RX 2 +#define BCM6348_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6348_H */ diff --git a/include/dt-bindings/dma/bcm6358-dma.h b/include/dt-bindings/dma/bcm6358-dma.h new file mode 100644 index 0000000000..3118b9da0a --- /dev/null +++ b/include/dt-bindings/dma/bcm6358-dma.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6358_H +#define __DT_BINDINGS_DMA_BCM6358_H + +#define BCM6358_DMA_ENET0_RX 0 +#define BCM6358_DMA_ENET0_TX 1 +#define BCM6358_DMA_ENET1_RX 2 +#define BCM6358_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6358_H */ diff --git a/include/dt-bindings/dma/bcm6362-dma.h b/include/dt-bindings/dma/bcm6362-dma.h new file mode 100644 index 0000000000..1e62236daa --- /dev/null +++ b/include/dt-bindings/dma/bcm6362-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6362_H +#define __DT_BINDINGS_DMA_BCM6362_H + +#define BCM6362_DMA_ENETSW_RX 0 +#define BCM6362_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6362_H */ diff --git a/include/dt-bindings/dma/bcm6368-dma.h b/include/dt-bindings/dma/bcm6368-dma.h new file mode 100644 index 0000000000..36c6caa0e1 --- /dev/null +++ b/include/dt-bindings/dma/bcm6368-dma.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + */ + +#ifndef __DT_BINDINGS_DMA_BCM6368_H +#define __DT_BINDINGS_DMA_BCM6368_H + +#define BCM6368_DMA_ENETSW_RX 0 +#define BCM6368_DMA_ENETSW_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6368_H */ diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h new file mode 100644 index 0000000000..25bb1fffa9 --- /dev/null +++ b/include/dt-bindings/gpio/meson-axg-gpio.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H +#define _DT_BINDINGS_MESON_AXG_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_TEST_N 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define BOOT_0 11 +#define BOOT_1 12 +#define BOOT_2 13 +#define BOOT_3 14 +#define BOOT_4 15 +#define BOOT_5 16 +#define BOOT_6 17 +#define BOOT_7 18 +#define BOOT_8 19 +#define BOOT_9 20 +#define BOOT_10 21 +#define BOOT_11 22 +#define BOOT_12 23 +#define BOOT_13 24 +#define BOOT_14 25 +#define GPIOA_0 26 +#define GPIOA_1 27 +#define GPIOA_2 28 +#define GPIOA_3 29 +#define GPIOA_4 30 +#define GPIOA_5 31 +#define GPIOA_6 32 +#define GPIOA_7 33 +#define GPIOA_8 34 +#define GPIOA_9 35 +#define GPIOA_10 36 +#define GPIOA_11 37 +#define GPIOA_12 38 +#define GPIOA_13 39 +#define GPIOA_14 40 +#define GPIOA_15 41 +#define GPIOA_16 42 +#define GPIOA_17 43 +#define GPIOA_18 44 +#define GPIOA_19 45 +#define GPIOA_20 46 +#define GPIOX_0 47 +#define GPIOX_1 48 +#define GPIOX_2 49 +#define GPIOX_3 50 +#define GPIOX_4 51 +#define GPIOX_5 52 +#define GPIOX_6 53 +#define GPIOX_7 54 +#define GPIOX_8 55 +#define GPIOX_9 56 +#define GPIOX_10 57 +#define GPIOX_11 58 +#define GPIOX_12 59 +#define GPIOX_13 60 +#define GPIOX_14 61 +#define GPIOX_15 62 +#define GPIOX_16 63 +#define GPIOX_17 64 +#define GPIOX_18 65 +#define GPIOX_19 66 +#define GPIOX_20 67 +#define GPIOX_21 68 +#define GPIOX_22 69 +#define GPIOY_0 70 +#define GPIOY_1 71 +#define GPIOY_2 72 +#define GPIOY_3 73 +#define GPIOY_4 74 +#define GPIOY_5 75 +#define GPIOY_6 76 +#define GPIOY_7 77 +#define GPIOY_8 78 +#define GPIOY_9 79 +#define GPIOY_10 80 +#define GPIOY_11 81 +#define GPIOY_12 82 +#define GPIOY_13 83 +#define GPIOY_14 84 +#define GPIOY_15 85 + +#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/power/mt7623-power.h b/include/dt-bindings/power/mt7623-power.h new file mode 100644 index 0000000000..0e73bb43a5 --- /dev/null +++ b/include/dt-bindings/power/mt7623-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MT7623_POWER_H +#define _DT_BINDINGS_MT7623_POWER_H + +#define MT7623_POWER_DOMAIN_CONN 0 +#define MT7623_POWER_DOMAIN_DISP 1 +#define MT7623_POWER_DOMAIN_MFG 2 +#define MT7623_POWER_DOMAIN_VDEC 3 +#define MT7623_POWER_DOMAIN_ISP 4 +#define MT7623_POWER_DOMAIN_BDP 5 +#define MT7623_POWER_DOMAIN_ETH 6 +#define MT7623_POWER_DOMAIN_HIF 7 +#define MT7623_POWER_DOMAIN_IFR_MSC 8 + +#endif /* _DT_BINDINGS_MT7623_POWER_H */ diff --git a/include/dt-bindings/power/mt7629-power.h b/include/dt-bindings/power/mt7629-power.h new file mode 100644 index 0000000000..c7e6130503 --- /dev/null +++ b/include/dt-bindings/power/mt7629-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MT7629_POWER_H +#define _DT_BINDINGS_MT7629_POWER_H + +#define MT7629_POWER_DOMAIN_ETHSYS 0 +#define MT7629_POWER_DOMAIN_HIF0 1 +#define MT7629_POWER_DOMAIN_HIF1 2 + +#endif /* _DT_BINDINGS_MT7629_POWER_H */ diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h index 1409c73a57..944d85beec 100644 --- a/include/dt-bindings/power/r8a77990-sysc.h +++ b/include/dt-bindings/power/r8a77990-sysc.h @@ -11,8 +11,14 @@ * (e.g. SYSCISR, Interrupt Status Register) */ -#define R8A77990_PD_CA53_CPU0 5 +#define R8A77990_PD_CA53_CPU0 5 +#define R8A77990_PD_CA53_CPU1 6 +#define R8A77990_PD_CR7 13 +#define R8A77990_PD_A3VC 14 +#define R8A77990_PD_3DG_A 17 +#define R8A77990_PD_3DG_B 18 #define R8A77990_PD_CA53_SCU 21 +#define R8A77990_PD_A2VC1 26 /* Always-on power area */ #define R8A77990_PD_ALWAYS_ON 32 diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h new file mode 100644 index 0000000000..05c3636787 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) + * + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H + +#define AXG_ARB_TODDR_A 0 +#define AXG_ARB_TODDR_B 1 +#define AXG_ARB_TODDR_C 2 +#define AXG_ARB_FRDDR_A 3 +#define AXG_ARB_FRDDR_B 4 +#define AXG_ARB_FRDDR_C 5 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h new file mode 100644 index 0000000000..ad6f55dabd --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h @@ -0,0 +1,124 @@ +/* + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong + * + * Copyright (c) 2017 Amlogic, inc. + * Author: Yixun Lan + * + * SPDX-License-Identifier: (GPL-2.0+ OR BSD) + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +#define RESET_PCIE_A 1 +#define RESET_PCIE_B 2 +#define RESET_DDR_TOP 3 +/* 4 */ +#define RESET_VIU 5 +#define RESET_PCIE_PHY 6 +#define RESET_PCIE_APB 7 +/* 8 */ +/* 9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +/* 12 */ +#define RESET_VCBUS 13 +/* 14 */ +/* 15 */ +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18-21 */ +#define RESET_SYS_CPU_CAPB3 22 +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +#define RESET_MMC 27 +/* 28-31 */ +/* RESET1 */ +/* 32 */ +/* 33 */ +#define RESET_USB_OTG 34 +#define RESET_DDR 35 +#define RESET_AO_RESET 36 +/* 37 */ +#define RESET_AHB_SRAM 38 +/* 39 */ +/* 40 */ +#define RESET_DMA 41 +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +/* 44 */ +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +#define RESET_ROM_BOOT 47 +#define RESET_SYS_CPU_0 48 +#define RESET_SYS_CPU_1 49 +#define RESET_SYS_CPU_2 50 +#define RESET_SYS_CPU_3 51 +#define RESET_SYS_CPU_CORE_0 52 +#define RESET_SYS_CPU_CORE_1 53 +#define RESET_SYS_CPU_CORE_2 54 +#define RESET_SYS_CPU_CORE_3 55 +#define RESET_SYS_PLL_DIV 56 +#define RESET_SYS_CPU_AXI 57 +#define RESET_SYS_CPU_L2 58 +#define RESET_SYS_CPU_P 59 +#define RESET_SYS_CPU_MBIST 60 +/* 61-63 */ +/* RESET2 */ +/* 64 */ +/* 65 */ +#define RESET_AUDIO 66 +/* 67 */ +#define RESET_MIPI_HOST 68 +#define RESET_AUDIO_LOCKER 69 +#define RESET_GE2D 70 +/* 71-76 */ +#define RESET_AO_CPU_RESET 77 +/* 78-95 */ +/* RESET3 */ +#define RESET_RING_OSCILLATOR 96 +/* 97-127 */ +/* RESET4 */ +/* 128 */ +/* 129 */ +#define RESET_MIPI_PHY 130 +/* 131-140 */ +#define RESET_VENCL 141 +#define RESET_I2C_MASTER_2 142 +#define RESET_I2C_MASTER_1 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_PERIPHS_GENERAL 192 +#define RESET_PERIPHS_SPICC 193 +/* 194 */ +/* 195 */ +#define RESET_PERIPHS_I2C_MASTER_0 196 +/* 197-200 */ +#define RESET_PERIPHS_UART_0 201 +#define RESET_PERIPHS_UART_1 202 +/* 203-204 */ +#define RESET_PERIPHS_SPI_0 205 +#define RESET_PERIPHS_I2C_MASTER_3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +/* 228 */ +#define RESET_DEVICE_MMC_ARB 229 +/* 230 */ +#define RESET_VID_LOCK 231 +#define RESET_A9_DMC_PIPEL 232 +#define RESET_DMC_VPU_PIPEL 233 +/* 234-255 */ + +#endif diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h new file mode 100644 index 0000000000..d342c0b6b2 --- /dev/null +++ b/include/dt-bindings/reset/axg-aoclkc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK + +#define RESET_AO_REMOTE 0 +#define RESET_AO_I2C_MASTER 1 +#define RESET_AO_I2C_SLAVE 2 +#define RESET_AO_UART1 3 +#define RESET_AO_UART2 4 +#define RESET_AO_IR_BLASTER 5 + +#endif diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 228ab3b102..9941cc37a3 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -38,4 +38,23 @@ struct dwc3_device { int dwc3_uboot_init(struct dwc3_device *dev); void dwc3_uboot_exit(int index); void dwc3_uboot_handle_interrupt(int index); + +struct phy; +#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB) +int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys); +int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys); +#else +static inline int dwc3_setup_phy(struct udevice *dev, struct phy **array, + int *num_phys) +{ + return -ENOTSUPP; +} + +static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, + int num_phys) +{ + return -ENOTSUPP; +} +#endif + #endif /* __DWC3_UBOOT_H_ */ diff --git a/include/efi.h b/include/efi.h index b1deb609b4..b5e2c64f38 100644 --- a/include/efi.h +++ b/include/efi.h @@ -96,7 +96,7 @@ typedef struct { typedef unsigned long efi_status_t; typedef u64 efi_physical_addr_t; typedef u64 efi_virtual_addr_t; -typedef void *efi_handle_t; +typedef struct efi_object *efi_handle_t; #define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \ diff --git a/include/efi_api.h b/include/efi_api.h index e850b951eb..aef77b6319 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -85,10 +85,10 @@ struct efi_boot_services { efi_status_t (EFIAPI *check_event)(struct efi_event *event); #define EFI_NATIVE_INTERFACE 0x00000000 efi_status_t (EFIAPI *install_protocol_interface)( - void **handle, const efi_guid_t *protocol, + efi_handle_t *handle, const efi_guid_t *protocol, int protocol_interface_type, void *protocol_interface); efi_status_t (EFIAPI *reinstall_protocol_interface)( - void *handle, const efi_guid_t *protocol, + efi_handle_t handle, const efi_guid_t *protocol, void *old_interface, void *new_interface); efi_status_t (EFIAPI *uninstall_protocol_interface)( efi_handle_t handle, const efi_guid_t *protocol, @@ -164,9 +164,9 @@ struct efi_boot_services { efi_status_t (EFIAPI *locate_protocol)(const efi_guid_t *protocol, void *registration, void **protocol_interface); efi_status_t (EFIAPI *install_multiple_protocol_interfaces)( - void **handle, ...); + efi_handle_t *handle, ...); efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)( - void *handle, ...); + efi_handle_t handle, ...); efi_status_t (EFIAPI *calculate_crc32)(const void *data, efi_uintn_t data_size, u32 *crc32); @@ -241,8 +241,8 @@ struct efi_runtime_services { efi_status_t (EFIAPI *query_capsule_caps)( struct efi_capsule_header **capsule_header_array, efi_uintn_t capsule_count, - u64 maximum_capsule_size, - u32 reset_type); + u64 *maximum_capsule_size, + u32 *reset_type); efi_status_t (EFIAPI *query_variable_info)( u32 attributes, u64 *maximum_variable_storage_size, @@ -965,7 +965,7 @@ struct efi_file_info { struct efi_time last_access_time; struct efi_time modification_time; u64 attribute; - s16 file_name[0]; + u16 file_name[0]; }; struct efi_file_system_info { diff --git a/include/efi_loader.h b/include/efi_loader.h index 1417c3588f..53f08161ab 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -167,28 +167,41 @@ struct efi_handler { struct list_head open_infos; }; -/* - * UEFI has a poor man's OO model where one "object" can be polymorphic and have - * multiple different protocols (classes) attached to it. +/** + * struct efi_object - dereferenced EFI handle * - * This struct is the parent struct for all of our actual implementation objects - * that can include it to make themselves an EFI object + * @link: pointers to put the handle into a linked list + * @protocols: linked list with the protocol interfaces installed on this + * handle + * + * UEFI offers a flexible and expandable object model. The objects in the UEFI + * API are devices, drivers, and loaded images. struct efi_object is our storage + * structure for these objects. + * + * When including this structure into a larger structure always put it first so + * that when deleting a handle the whole encompassing structure can be freed. + * + * A pointer to this structure is referred to as a handle. Typedef efi_handle_t + * has been created for such pointers. */ struct efi_object { /* Every UEFI object is part of a global object list */ struct list_head link; /* The list of protocols */ struct list_head protocols; - /* The object spawner can either use this for data or as identifier */ - void *handle; }; /** * struct efi_loaded_image_obj - handle of a loaded image + * + * @header: EFI object header + * @reloc_base: base address for the relocated image + * @reloc_size: size of the relocated image + * @exit_jmp: long jump buffer for returning form started image + * @entry: entry address of the relocated image */ struct efi_loaded_image_obj { - /* Generic EFI object parent class data */ - struct efi_object parent; + struct efi_object header; void *reloc_base; aligned_u64 reloc_size; efi_status_t exit_status; @@ -290,11 +303,11 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map); /* Call this to set the current device name */ void efi_set_bootdev(const char *dev, const char *devnr, const char *path); /* Add a new object to the object list. */ -void efi_add_handle(struct efi_object *obj); +void efi_add_handle(efi_handle_t obj); /* Create handle */ efi_status_t efi_create_handle(efi_handle_t *handle); /* Delete handle */ -void efi_delete_handle(struct efi_object *obj); +void efi_delete_handle(efi_handle_t obj); /* Call this to validate a handle and find the EFI object for it */ struct efi_object *efi_search_obj(const efi_handle_t handle); /* Find a protocol on a handle */ @@ -331,7 +344,16 @@ struct efi_simple_file_system_protocol *efi_simple_file_system( /* open file from device-path: */ struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp); - +/** + * efi_size_in_pages() - convert size in bytes to size in pages + * + * This macro returns the number of EFI memory pages required to hold 'size' + * bytes. + * + * @size: size in bytes + * Return: size in pages + */ +#define efi_size_in_pages(size) ((size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) /* Generic EFI memory allocator, call this to get memory */ void *efi_alloc(uint64_t len, int memory_type); /* More specific EFI memory allocator, called by EFI payloads */ @@ -419,6 +441,10 @@ const struct efi_device_path *efi_dp_last_node( efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path, struct efi_device_path **device_path, struct efi_device_path **file_path); +efi_status_t efi_dp_from_name(const char *dev, const char *devnr, + const char *path, + struct efi_device_path **device, + struct efi_device_path **file); #define EFI_DP_TYPE(_dp, _type, _subtype) \ (((_dp)->type == DEVICE_PATH_TYPE_##_type) && \ @@ -492,6 +518,29 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name, efi_guid_t *vendor, u32 attributes, efi_uintn_t data_size, void *data); +/* + * See section 3.1.3 in the v2.7 UEFI spec for more details on + * the layout of EFI_LOAD_OPTION. In short it is: + * + * typedef struct _EFI_LOAD_OPTION { + * UINT32 Attributes; + * UINT16 FilePathListLength; + * // CHAR16 Description[]; <-- variable length, NULL terminated + * // EFI_DEVICE_PATH_PROTOCOL FilePathList[]; + * <-- FilePathListLength bytes + * // UINT8 OptionalData[]; + * } EFI_LOAD_OPTION; + */ +struct efi_load_option { + u32 attributes; + u16 file_path_length; + u16 *label; + struct efi_device_path *file_path; + u8 *optional_data; +}; + +void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data); +unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data); void *efi_bootmgr_load(struct efi_device_path **device_path, struct efi_device_path **file_path); diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 56beac305e..49d3d6d0b4 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -129,7 +129,6 @@ u16 efi_st_get_key(void); * @setup: set up the unit test * @teardown: tear down the unit test * @execute: execute the unit test - * @setup_ok: setup was successful (set at runtime) * @on_request: test is only executed on request */ struct efi_unit_test { @@ -139,7 +138,6 @@ struct efi_unit_test { const struct efi_system_table *systable); int (*execute)(void); int (*teardown)(void); - int setup_ok; bool on_request; }; diff --git a/include/environment.h b/include/environment.h index 5e90f157e8..7da1291d5b 100644 --- a/include/environment.h +++ b/include/environment.h @@ -157,7 +157,6 @@ extern env_t environment; #endif /* ENV_IS_EMBEDDED */ extern const unsigned char default_environment[]; -extern env_t *env_ptr; #if defined(CONFIG_NEEDS_MANUAL_RELOC) extern void env_reloc(void); diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 3c9c87f21b..86ff6d3ea7 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -34,14 +34,14 @@ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ + "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \ + "name=reserved,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ - "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ "name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \ "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ - "name=system,size=768M,uuid=${uuid_gpt_system};" \ + "name=system,size=1024M,uuid=${uuid_gpt_system};" \ "name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ diff --git a/include/fdtdec.h b/include/fdtdec.h index c26df50543..f1bcbf837f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -951,11 +951,33 @@ int fdtdec_setup_memory_banksize(void); */ int fdtdec_setup(void); +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) +/** + * fdtdec_resetup() - Set up the device tree again + * + * The main difference with fdtdec_setup() is that it returns if the fdt has + * changed because a better match has been found. + * This is typically used for boards that rely on a DM driver to detect the + * board type. This function sould be called by the board code after the stuff + * needed by board_fit_config_name_match() to operate porperly is available. + * If this functions signals that a rescan is necessary, the board code must + * unbind all the drivers using dm_uninit() and then rescan the DT with + * dm_init_and_scan(). + * + * @param rescan Returns a flag indicating that fdt has changed and rescanning + * the fdt is required + * + * @return 0 if OK, -ve on error + */ +int fdtdec_resetup(int *rescan); +#endif + /** * Board-specific FDT initialization. Returns the address to a device tree blob. * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined * and the board implements it. */ +void *board_fdt_blob_setup(void); /* * Decode the size of memory diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0de8..3edcc39f4e 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 @@ -164,7 +164,7 @@ /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK 0x0F000000 #define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT 0x00080000 /* GPCM External Access Termination mode for write access */ @@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes { */ #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) /* * NAND_AUTOBOOT_TRGR @@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes { /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK 0x000F0000 #define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) /* * GPCM Machine specific registers @@ -1031,6 +1031,23 @@ struct fsl_ifc { struct fsl_ifc_runtime *rregs; }; +struct ifc_regs { + const char *name; + u32 pr; + u32 pr_ext; + u32 amask; + u32 or; + u32 ftim[4]; + u32 or_ext; + u32 pr_final; + u32 amask_final; +}; + +struct ifc_regs_info { + struct ifc_regs *regs; + u32 cs_size; +}; + #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #undef CSPR_MSEL_NOR #define CSPR_MSEL_NOR CSPR_MSEL_GPCM diff --git a/include/handoff.h b/include/handoff.h new file mode 100644 index 0000000000..aacb0f5ebf --- /dev/null +++ b/include/handoff.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Passing basic information from SPL to U-Boot proper + * + * Copyright 2018 Google, Inc + */ + +#ifndef __HANDOFF_H +#define __HANDOFF_H + +#if CONFIG_IS_ENABLED(HANDOFF) + +#include + +/** + * struct spl_handoff - information passed from SPL to U-Boot proper + * + * @ram_size: Value to use for gd->ram_size + */ +struct spl_handoff { + struct arch_spl_handoff arch; + u64 ram_size; +#ifdef CONFIG_NR_DRAM_BANKS + struct { + u64 start; + u64 size; + } ram_bank[CONFIG_NR_DRAM_BANKS]; +#endif +}; + +void handoff_save_dram(struct spl_handoff *ho); +void handoff_load_dram_size(struct spl_handoff *ho); +void handoff_load_dram_banks(struct spl_handoff *ho); +#endif + +#endif diff --git a/include/hwspinlock.h b/include/hwspinlock.h new file mode 100644 index 0000000000..99389c13c2 --- /dev/null +++ b/include/hwspinlock.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _HWSPINLOCK_H_ +#define _HWSPINLOCK_H_ + +/** + * Implement a hwspinlock uclass. + * Hardware spinlocks are used to perform hardware protection of + * critical sections and synchronisation between multiprocessors. + */ + +struct udevice; + +/** + * struct hwspinlock - A handle to (allowing control of) a single hardware + * spinlock. + * + * @dev: The device which implements the hardware spinlock. + * @id: The hardware spinlock ID within the provider. + */ +struct hwspinlock { + struct udevice *dev; + unsigned long id; +}; + +#if CONFIG_IS_ENABLED(DM_HWSPINLOCK) + +/** + * hwspinlock_get_by_index - Get a hardware spinlock by integer index + * + * This looks up and request a hardware spinlock. The index is relative to the + * client device; each device is assumed to have n hardware spinlock associated + * with it somehow, and this function finds and requests one of them. + * + * @dev: The client device. + * @index: The index of the hardware spinlock to request, within the + * client's list of hardware spinlock. + * @hws: A pointer to a hardware spinlock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int hwspinlock_get_by_index(struct udevice *dev, + int index, struct hwspinlock *hws); + +/** + * Lock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @timeout: Timeout value in msecs + * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors + */ +int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout); + +/** + * Unlock the hardware spinlock + * + * @hws: A hardware spinlock struct that previously requested by + * hwspinlock_get_by_index + * @return: 0 if OK, -ve on error + */ +int hwspinlock_unlock(struct hwspinlock *hws); + +#else + +static inline int hwspinlock_get_by_index(struct udevice *dev, + int index, + struct hwspinlock *hws) +{ + return -ENOSYS; +} + +static inline int hwspinlock_lock_timeout(struct hwspinlock *hws, + int timeout) +{ + return -ENOSYS; +} + +static inline int hwspinlock_unlock(struct hwspinlock *hws) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_HWSPINLOCK */ + +struct ofnode_phandle_args; + +/** + * struct hwspinlock_ops - Driver model hwspinlock operations + * + * The uclass interface is implemented by all hwspinlock devices which use + * driver model. + */ +struct hwspinlock_ops { + /** + * of_xlate - Translate a client's device-tree (OF) hardware specifier. + * + * The hardware core calls this function as the first step in + * implementing a client's hwspinlock_get_by_*() call. + * + * @hws: The hardware spinlock struct to hold the translation + * result. + * @args: The hardware spinlock specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct hwspinlock *hws, + struct ofnode_phandle_args *args); + + /** + * Lock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be used + * @return 0 if OK, -ve on error + */ + int (*lock)(struct udevice *dev, int index); + + /** + * Unlock the hardware spinlock + * + * @dev: hwspinlock Device + * @index: index of the lock to be unlocked + * @return 0 if OK, -ve on error + */ + int (*unlock)(struct udevice *dev, int index); + + /** + * Relax - optional + * Platform-specific relax method, called by hwspinlock core + * while spinning on a lock, between two successive call to + * lock + * + * @dev: hwspinlock Device + */ + void (*relax)(struct udevice *dev); +}; + +#endif /* _HWSPINLOCK_H_ */ diff --git a/include/i2c.h b/include/i2c.h index d33f827500..ccffc19552 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -536,6 +536,27 @@ int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip); */ void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); +/** + * i2c_emul_find() - Find an emulator for an i2c sandbox device + * + * This looks at the device's 'emul' phandle + * + * @dev: Device to find an emulator for + * @emulp: Returns the associated emulator, if found * + * @return 0 if OK, -ENOENT or -ENODEV if not found + */ +int i2c_emul_find(struct udevice *dev, struct udevice **emulp); + +/** + * i2c_emul_get_device() - Find the device being emulated + * + * Given an emulator this returns the associated device + * + * @emul: Emulator for the device + * @return device that @emul is emulating + */ +struct udevice *i2c_emul_get_device(struct udevice *emul); + #ifndef CONFIG_DM_I2C /* diff --git a/include/i2s.h b/include/i2s.h index e6d45ec26d..28f6184811 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -76,7 +76,7 @@ struct i2s_reg { }; /* This structure stores the i2s related information */ -struct i2stx_info { +struct i2s_uc_priv { unsigned int rfs; /* LR clock frame size */ unsigned int bfs; /* Bit slock frame size */ unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ @@ -87,17 +87,41 @@ struct i2stx_info { unsigned int id; /* I2S controller id */ }; +/* Operations for i2s devices */ +struct i2s_ops { + /** + * tx_data() - Transmit audio data + * + * @dev: I2C device + * @data: Data buffer to play + * @data_size: Size of data buffer in bytes + * @return 0 if OK, -ve on error + */ + int (*tx_data)(struct udevice *dev, void *data, uint data_size); +}; + +#define i2s_get_ops(dev) ((struct i2s_ops *)(dev)->driver->ops) + +/** + * i2s_tx_data() - Transmit audio data + * + * @dev: I2C device + * @data: Data buffer to play + * @data_size: Size of data buffer in bytes + * @return 0 if OK, -ve on error + */ +int i2s_tx_data(struct udevice *dev, void *data, uint data_size); + /* * Sends the given data through i2s tx * * @param pi2s_tx pointer of i2s transmitter parameter structure. * @param data address of the data buffer - * @param data_size array size of the int buffer (total size / size of int) - * + * @param data_size size of the data (in bytes) * @return int value 0 for success, -1 in case of error */ -int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data, - unsigned long data_size); +int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, + uint data_size); /* * Initialise i2s transmiter @@ -106,6 +130,6 @@ int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data, * * @return int value 0 for success, -1 in case of error */ -int i2s_tx_init(struct i2stx_info *pi2s_tx); +int i2s_tx_init(struct i2s_uc_priv *pi2s_tx); #endif /* __I2S_H__ */ diff --git a/include/i8042.h b/include/i8042.h index 2b9e5c4d37..8d69fa13bc 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -72,19 +72,4 @@ #define BRK 0x0100 /* make break flag for keyboard */ #define ALT 0x0200 /* right alt */ -/* exports */ - -/** - * Flush all buffer from keyboard controller to host. - */ -void i8042_flush(void); - -/** - * Disables the keyboard so that key strokes no longer generate scancodes to - * the host. - * - * @return 0 if ok, -1 if keyboard input was found while disabling - */ -int i8042_disable(void); - #endif /* _I8042_H_ */ diff --git a/include/image.h b/include/image.h index 031c355b48..765ffecee0 100644 --- a/include/image.h +++ b/include/image.h @@ -30,6 +30,7 @@ struct fdt_region; #define IMAGE_ENABLE_FIT 1 #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1 #define CONFIG_FIT_ENABLE_SHA256_SUPPORT #define CONFIG_SHA1 #define CONFIG_SHA256 @@ -125,7 +126,8 @@ enum ih_category { * Operating System Codes * * The following are exposed to uImage header. - * Do not change values for backward compatibility. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. */ enum { IH_OS_INVALID = 0, /* Invalid OS */ @@ -163,7 +165,8 @@ enum { * CPU Architecture Codes (supported by Linux) * * The following are exposed to uImage header. - * Do not change values for backward compatibility. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. */ enum { IH_ARCH_INVALID = 0, /* Invalid CPU */ @@ -236,7 +239,8 @@ enum { * as command interpreter (=> Shell Scripts). * * The following are exposed to uImage header. - * Do not change values for backward compatibility. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. */ enum { @@ -251,7 +255,6 @@ enum { IH_TYPE_FLATDT, /* Binary Flat Device Tree Blob */ IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ - IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ @@ -278,6 +281,9 @@ enum { IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */ IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */ IH_TYPE_SOCFPGAIMAGE_V1, /* Altera SOCFPGA A10 Preloader */ + IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */ + IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ + IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ IH_TYPE_COUNT, /* Number of image types */ }; @@ -286,7 +292,8 @@ enum { * Compression Types * * The following are exposed to uImage header. - * Do not change values for backward compatibility. + * New IDs *MUST* be appended at the end of the list and *NEVER* + * inserted for backward compatibility. */ enum { IH_COMP_NONE = 0, /* No Compression Used */ @@ -1100,6 +1107,7 @@ struct image_sign_info { int node_offset; /* Offset of signature node */ const char *name; /* Algorithm name */ struct checksum_algo *checksum; /* Checksum algorithm information */ + struct padding_algo *padding; /* Padding algorithm information */ struct crypto_algo *crypto; /* Crypto algorithm information */ const void *fdt_blob; /* FDT containing public keys */ int required_keynode; /* Node offset of key to use: -1=any */ @@ -1185,6 +1193,13 @@ struct crypto_algo { uint8_t *sig, uint sig_len); }; +struct padding_algo { + const char *name; + int (*verify)(struct image_sign_info *info, + uint8_t *pad, int pad_len, + const uint8_t *hash, int hash_len); +}; + /** * image_get_checksum_algo() - Look up a checksum algorithm * @@ -1201,6 +1216,14 @@ struct checksum_algo *image_get_checksum_algo(const char *full_name); */ struct crypto_algo *image_get_crypto_algo(const char *full_name); +/** + * image_get_padding_algo() - Look up a padding algorithm + * + * @param name Name of padding algorithm + * @return pointer to algorithm information, or NULL if not found + */ +struct padding_algo *image_get_padding_algo(const char *name); + /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' * diff --git a/include/imximage.h b/include/imximage.h index 6f7ca7f5e3..544babb53a 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -33,6 +33,7 @@ #define FLASH_OFFSET_NOR 0x1000 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD #define FLASH_OFFSET_QSPI 0x1000 +#define FLASH_OFFSET_FLEXSPI 0x1000 /* Initial Load Region Size */ #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF @@ -48,6 +49,7 @@ /* Command tags and parameters */ #define IVT_HEADER_TAG 0xD1 #define IVT_VERSION 0x40 +#define IVT_VERSION_V3 0x41 #define DCD_HEADER_TAG 0xD2 #define DCD_VERSION 0x40 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC @@ -71,6 +73,12 @@ enum imximage_cmd { CMD_CHECK_BITS_CLR, CMD_CSF, CMD_PLUGIN, + /* Follwoing on i.MX8MQ/MM */ + CMD_FIT, + CMD_SIGNED_HDMI, + CMD_LOADER, + CMD_SECOND_LOADER, + CMD_DDR_FW, }; enum imximage_fld_types { @@ -84,7 +92,8 @@ enum imximage_fld_types { enum imximage_version { IMXIMAGE_VER_INVALID = -1, IMXIMAGE_V1 = 1, - IMXIMAGE_V2 + IMXIMAGE_V2, + IMXIMAGE_V3 }; typedef struct { @@ -177,6 +186,12 @@ typedef struct { } data; } imx_header_v2_t; +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + uint32_t padding[5]; +} imx_header_v3_t; + /* The header must be aligned to 4k on MX53 for NAND boot */ struct imx_header { union { diff --git a/include/init.h b/include/init.h index a58d7a6917..afc953d51e 100644 --- a/include/init.h +++ b/include/init.h @@ -109,7 +109,14 @@ int arch_reserve_stacks(void); */ int init_cache_f_r(void); +#if !CONFIG_IS_ENABLED(CPU) +/** + * print_cpuinfo() - Display information about the CPU + * + * Return: 0 if OK, -ve on error + */ int print_cpuinfo(void); +#endif int timer_init(void); int reserve_mmu(void); int misc_init_f(void); diff --git a/include/inttypes.h b/include/inttypes.h new file mode 100644 index 0000000000..dcb6785228 --- /dev/null +++ b/include/inttypes.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc. + * + * This file is taken from the GNU C Library v2.15, with the unimplemented + * functions removed and a few style fixes. + */ + +/* + * ISO C99: 7.8 Format conversion of integer types + */ + +#ifndef _INTTYPES_H +#define _INTTYPES_H 1 + +#include + +/* Get a definition for wchar_t. But we must not define wchar_t itself. */ +#ifndef ____gwchar_t_defined +# ifdef __cplusplus +# define __gwchar_t wchar_t +# elif defined __WCHAR_TYPE__ +typedef __WCHAR_TYPE__ __gwchar_t; +# else +# define __need_wchar_t +# include +typedef wchar_t __gwchar_t; +# endif +# define ____gwchar_t_defined 1 +#endif + +/* + * The ISO C99 standard specifies that these macros must only be defined if + * explicitly requested + */ +#if !defined __cplusplus || defined __STDC_FORMAT_MACROS + +/* linux/types.h always uses long long for 64-bit and long for uintptr_t */ +# define __PRI64_PREFIX "ll" +# define __PRIPTR_PREFIX "l" + +/* Macros for printing format specifiers. */ + +/* Decimal notation. */ +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 __PRI64_PREFIX "d" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 __PRI64_PREFIX "d" + +# define PRIdFAST8 "d" +# define PRIdFAST16 __PRIPTR_PREFIX "d" +# define PRIdFAST32 __PRIPTR_PREFIX "d" +# define PRIdFAST64 __PRI64_PREFIX "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 __PRI64_PREFIX "i" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 __PRI64_PREFIX "i" + +# define PRIiFAST8 "i" +# define PRIiFAST16 __PRIPTR_PREFIX "i" +# define PRIiFAST32 __PRIPTR_PREFIX "i" +# define PRIiFAST64 __PRI64_PREFIX "i" + +/* Octal notation. */ +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 __PRI64_PREFIX "o" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 __PRI64_PREFIX "o" + +# define PRIoFAST8 "o" +# define PRIoFAST16 __PRIPTR_PREFIX "o" +# define PRIoFAST32 __PRIPTR_PREFIX "o" +# define PRIoFAST64 __PRI64_PREFIX "o" + +/* Unsigned integers. */ +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 __PRI64_PREFIX "u" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 __PRI64_PREFIX "u" + +# define PRIuFAST8 "u" +# define PRIuFAST16 __PRIPTR_PREFIX "u" +# define PRIuFAST32 __PRIPTR_PREFIX "u" +# define PRIuFAST64 __PRI64_PREFIX "u" + +/* lowercase hexadecimal notation. */ +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 __PRI64_PREFIX "x" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 __PRI64_PREFIX "x" + +# define PRIxFAST8 "x" +# define PRIxFAST16 __PRIPTR_PREFIX "x" +# define PRIxFAST32 __PRIPTR_PREFIX "x" +# define PRIxFAST64 __PRI64_PREFIX "x" + +/* UPPERCASE hexadecimal notation. */ +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 __PRI64_PREFIX "X" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 __PRI64_PREFIX "X" + +# define PRIXFAST8 "X" +# define PRIXFAST16 __PRIPTR_PREFIX "X" +# define PRIXFAST32 __PRIPTR_PREFIX "X" +# define PRIXFAST64 __PRI64_PREFIX "X" + +/* Macros for printing `intmax_t' and `uintmax_t'. */ +# define PRIdMAX __PRI64_PREFIX "d" +# define PRIiMAX __PRI64_PREFIX "i" +# define PRIoMAX __PRI64_PREFIX "o" +# define PRIuMAX __PRI64_PREFIX "u" +# define PRIxMAX __PRI64_PREFIX "x" +# define PRIXMAX __PRI64_PREFIX "X" + +/* Macros for printing `intptr_t' and `uintptr_t'. */ +# define PRIdPTR __PRIPTR_PREFIX "d" +# define PRIiPTR __PRIPTR_PREFIX "i" +# define PRIoPTR __PRIPTR_PREFIX "o" +# define PRIuPTR __PRIPTR_PREFIX "u" +# define PRIxPTR __PRIPTR_PREFIX "x" +# define PRIXPTR __PRIPTR_PREFIX "X" + +/* Macros for scanning format specifiers. */ + +/* Signed decimal notation. */ +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 __PRI64_PREFIX "d" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 __PRI64_PREFIX "d" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 __PRIPTR_PREFIX "d" +# define SCNdFAST32 __PRIPTR_PREFIX "d" +# define SCNdFAST64 __PRI64_PREFIX "d" + +/* Signed decimal notation. */ +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 __PRI64_PREFIX "i" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 __PRI64_PREFIX "i" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 __PRIPTR_PREFIX "i" +# define SCNiFAST32 __PRIPTR_PREFIX "i" +# define SCNiFAST64 __PRI64_PREFIX "i" + +/* Unsigned decimal notation. */ +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 __PRI64_PREFIX "u" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 __PRI64_PREFIX "u" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 __PRIPTR_PREFIX "u" +# define SCNuFAST32 __PRIPTR_PREFIX "u" +# define SCNuFAST64 __PRI64_PREFIX "u" + +/* Octal notation. */ +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 __PRI64_PREFIX "o" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 __PRI64_PREFIX "o" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 __PRIPTR_PREFIX "o" +# define SCNoFAST32 __PRIPTR_PREFIX "o" +# define SCNoFAST64 __PRI64_PREFIX "o" + +/* Hexadecimal notation. */ +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 __PRI64_PREFIX "x" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 __PRI64_PREFIX "x" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 __PRIPTR_PREFIX "x" +# define SCNxFAST32 __PRIPTR_PREFIX "x" +# define SCNxFAST64 __PRI64_PREFIX "x" + +/* Macros for scanning `intmax_t' and `uintmax_t'. */ +# define SCNdMAX __PRI64_PREFIX "d" +# define SCNiMAX __PRI64_PREFIX "i" +# define SCNoMAX __PRI64_PREFIX "o" +# define SCNuMAX __PRI64_PREFIX "u" +# define SCNxMAX __PRI64_PREFIX "x" + +/* Macros for scanning `intptr_t' and `uintptr_t'. */ +# define SCNdPTR __PRIPTR_PREFIX "d" +# define SCNiPTR __PRIPTR_PREFIX "i" +# define SCNoPTR __PRIPTR_PREFIX "o" +# define SCNuPTR __PRIPTR_PREFIX "u" +# define SCNxPTR __PRIPTR_PREFIX "x" + +#endif /* C++ && format macros */ + +#if __WORDSIZE == 64 + +/* We have to define the `uintmax_t' type using `ldiv_t'. */ +typedef struct { + long int quot; /* Quotient. */ + long int rem; /* Remainder. */ +} imaxdiv_t; + +#else + +/* We have to define the `uintmax_t' type using `lldiv_t'. */ +typedef struct { + long long int quot; /* Quotient. */ + long long int rem; /* Remainder. */ +} imaxdiv_t; + +#endif + +#endif /* inttypes.h */ diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h new file mode 100644 index 0000000000..4a54ae0509 --- /dev/null +++ b/include/linux/bitmap.h @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +#ifndef __LINUX_BITMAP_H +#define __LINUX_BITMAP_H + +#include +#include +#include + +#define small_const_nbits(nbits) \ + (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG) + +static inline void bitmap_zero(unsigned long *dst, int nbits) +{ + if (small_const_nbits(nbits)) { + *dst = 0UL; + } else { + int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); + + memset(dst, 0, len); + } +} + +#endif /* __LINUX_BITMAP_H */ diff --git a/arch/mips/include/asm/const.h b/include/linux/const.h similarity index 52% rename from arch/mips/include/asm/const.h rename to include/linux/const.h index ed43b5d534..379c889232 100644 --- a/arch/mips/include/asm/const.h +++ b/include/linux/const.h @@ -1,11 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * const.h: Macros for dealing with constants. - */ - +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ #ifndef _LINUX_CONST_H #define _LINUX_CONST_H +/* const.h: Macros for dealing with constants. */ + /* Some constant macros are used in both assembler and * C code. Therefore we cannot annotate them always with * 'UL' and other type specifiers unilaterally. We @@ -16,12 +14,21 @@ */ #ifdef __ASSEMBLY__ +#define _AC(X,Y) X #define _AT(T,X) X #else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) #define _AT(T,X) ((T)(X)) #endif -#define _BITUL(x) (_AC(1,UL) << (x)) -#define _BITULL(x) (_AC(1,ULL) << (x)) +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) -#endif /* !(_LINUX_CONST_H) */ +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#endif /* _LINUX_CONST_H */ diff --git a/include/linux/delay.h b/include/linux/delay.h index 193603451a..71a38e15fb 100644 --- a/include/linux/delay.h +++ b/include/linux/delay.h @@ -10,8 +10,7 @@ void udelay(unsigned long usec); static inline void mdelay(unsigned long msec) { - while (msec--) - udelay(1000); + udelay(1000 * msec); } static inline void ndelay(unsigned long nsec) diff --git a/include/linux/io.h b/include/linux/io.h index d1b3efed9d..9badab49b0 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -7,6 +7,7 @@ #include #include +#ifndef CONFIG_HAVE_ARCH_IOMAP static inline u8 ioread8(const volatile void __iomem *addr) { return readb(addr); @@ -21,6 +22,7 @@ static inline u32 ioread32(const volatile void __iomem *addr) { return readl(addr); } +#endif /* !CONFIG_HAVE_ARCH_IOMAP */ #ifdef CONFIG_64BIT static inline u64 ioread64(const volatile void __iomem *addr) @@ -29,6 +31,7 @@ static inline u64 ioread64(const volatile void __iomem *addr) } #endif /* CONFIG_64BIT */ +#ifndef CONFIG_HAVE_ARCH_IOMAP static inline void iowrite8(u8 value, volatile void __iomem *addr) { writeb(value, addr); @@ -43,6 +46,7 @@ static inline void iowrite32(u32 value, volatile void __iomem *addr) { writel(value, addr); } +#endif /* !CONFIG_HAVE_ARCH_IOMAP */ #ifdef CONFIG_64BIT static inline void iowrite64(u64 value, volatile void __iomem *addr) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 04a09eb4f6..a85c15d8dc 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -33,6 +33,10 @@ #define S64_MAX ((s64)(U64_MAX>>1)) #define S64_MIN ((s64)(-S64_MAX - 1)) +/* Aliases defined by stdint.h */ +#define UINT32_MAX U32_MAX +#define UINT64_MAX U64_MAX + #define STACK_MAGIC 0xdeadbeef #define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) @@ -98,6 +102,18 @@ (((__x) - ((__d) / 2)) / (__d)); \ } \ ) +/* + * Same as above but for u64 dividends. divisor must be a 32-bit + * number. + */ +#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ +{ \ + typeof(divisor) __d = divisor; \ + unsigned long long _tmp = (x) + (__d) / 2; \ + do_div(_tmp, __d); \ + _tmp; \ +} \ +) /* * Multiplies an integer by a fraction, while avoiding unnecessary diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 68e5915324..cd1f557a2f 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -366,6 +366,8 @@ static inline bool mtd_has_partitions(const struct mtd_info *mtd) return !list_empty(&mtd->partitions); } +bool mtd_partitions_used(struct mtd_info *master); + int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobecc); int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, @@ -562,8 +564,23 @@ unsigned mtd_mmap_capabilities(struct mtd_info *mtd); /* drivers/mtd/mtdcore.h */ int add_mtd_device(struct mtd_info *mtd); int del_mtd_device(struct mtd_info *mtd); + +#ifdef CONFIG_MTD_PARTITIONS int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); int del_mtd_partitions(struct mtd_info *); +#else +static inline int add_mtd_partitions(struct mtd_info *mtd, + const struct mtd_partition *parts, + int nparts) +{ + return 0; +} + +static inline int del_mtd_partitions(struct mtd_info *mtd) +{ + return 0; +} +#endif struct mtd_info *__mtd_next_device(int i); #define mtd_for_each_device(mtd) \ @@ -581,6 +598,7 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, const uint64_t length, uint64_t *len_incl_bad, int *truncated); +bool mtd_dev_list_updated(void); /* drivers/mtd/mtd_uboot.c */ int mtd_search_alternate_name(const char *mtdname, char *altname, diff --git a/include/linux/psci.h b/include/linux/psci.h index 8d13bd2702..9433df836b 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -88,10 +88,8 @@ #define PSCI_RET_DISABLED -8 #ifdef CONFIG_ARM_PSCI_FW -typedef unsigned long (psci_fn)(unsigned long, unsigned long, - unsigned long, unsigned long); - -extern psci_fn *invoke_psci_fn; +unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3); #else unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3) diff --git a/include/linux/sizes.h b/include/linux/sizes.h index ce3e8150c1..fbde0bc7e8 100644 --- a/include/linux/sizes.h +++ b/include/linux/sizes.h @@ -8,6 +8,8 @@ #ifndef __LINUX_SIZES_H__ #define __LINUX_SIZES_H__ +#include + #define SZ_1 0x00000001 #define SZ_2 0x00000002 #define SZ_4 0x00000004 @@ -44,4 +46,6 @@ #define SZ_1G 0x40000000 #define SZ_2G 0x80000000 +#define SZ_4G _AC(0x100000000, ULL) + #endif /* __LINUX_SIZES_H__ */ diff --git a/include/linux/types.h b/include/linux/types.h index 1f3cd63b8f..cc6f7cb39e 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -158,4 +158,7 @@ struct ustat { char f_fpack[6]; }; +#define DECLARE_BITMAP(name, bits) \ + unsigned long name[BITS_TO_LONGS(bits)] + #endif /* _LINUX_TYPES_H */ diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h index 30c464ce39..a49a66f2f8 100644 --- a/include/linux/usb/composite.h +++ b/include/linux/usb/composite.h @@ -24,7 +24,7 @@ #include #include #include -#include +#include /* * USB function drivers should return USB_GADGET_DELAYED_STATUS if they diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index b824f13477..497798a32a 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -19,6 +19,7 @@ #define __LINUX_USB_GADGET_H #include +#include #include #include @@ -926,4 +927,21 @@ extern void usb_ep_autoconfig_reset(struct usb_gadget *); extern int usb_gadget_handle_interrupts(int index); +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +int usb_gadget_initialize(int index); +int usb_gadget_release(int index); +int dm_usb_gadget_handle_interrupts(struct udevice *dev); +#else +#include +static inline int usb_gadget_initialize(int index) +{ + return board_usb_init(index, USB_INIT_DEVICE); +} + +static inline int usb_gadget_release(int index) +{ + return board_usb_cleanup(index, USB_INIT_DEVICE); +} +#endif + #endif /* __LINUX_USB_GADGET_H */ diff --git a/include/log.h b/include/log.h index a872fc6ef5..0f2bc19477 100644 --- a/include/log.h +++ b/include/log.h @@ -47,6 +47,8 @@ enum log_category_t { LOGC_DT, /* Device-tree */ LOGC_EFI, /* EFI implementation */ LOGC_ALLOC, /* Memory allocation */ + LOGC_SANDBOX, /* Related to the sandbox board */ + LOGC_BLOBLIST, /* Bloblist */ LOGC_COUNT, /* Number of log categories */ LOGC_END, /* Sentinel value for a list of log categories */ @@ -107,14 +109,19 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file, #define log_io(_fmt...) #endif +#if CONFIG_IS_ENABLED(LOG) + /* Emit a log record if the level is less that the maximum */ #define log(_cat, _level, _fmt, _args...) ({ \ int _l = _level; \ - if (_l <= _LOG_MAX_LEVEL) \ + if (CONFIG_IS_ENABLED(LOG) && _l <= _LOG_MAX_LEVEL) \ _log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \ __func__, \ pr_fmt(_fmt), ##_args); \ }) +#else +#define log(_cat, _level, _fmt, _args...) +#endif #ifdef DEBUG #define _DEBUG 1 @@ -174,7 +181,16 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, ({ if (!(x) && _DEBUG) \ __assert_fail(#x, __FILE__, __LINE__, __func__); }) -#ifdef CONFIG_LOG_ERROR_RETURN +#if CONFIG_IS_ENABLED(LOG) && defined(CONFIG_LOG_ERROR_RETURN) +/* + * Log an error return value, possibly with a message. Usage: + * + * return log_ret(fred_call()); + * + * or: + * + * return log_msg_ret("fred failed", fred_call()); + */ #define log_ret(_ret) ({ \ int __ret = (_ret); \ if (__ret < 0) \ @@ -189,8 +205,9 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, __ret; \ }) #else +/* Non-logging versions of the above which just return the error code */ #define log_ret(_ret) (_ret) -#define log_msg_ret(_msg, _ret) (_ret) +#define log_msg_ret(_msg, _ret) ((void)(_msg), _ret) #endif /** diff --git a/include/malloc.h b/include/malloc.h index 8175c75920..b714fedf45 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -880,6 +880,7 @@ static inline void free(void *ptr) {} void *calloc(size_t nmemb, size_t size); void *memalign_simple(size_t alignment, size_t bytes); void *realloc_simple(void *ptr, size_t size); +void malloc_simple_info(void); #else # ifdef USE_DL_PREFIX diff --git a/include/misc.h b/include/misc.h index 50515852b2..12d1325ee2 100644 --- a/include/misc.h +++ b/include/misc.h @@ -13,7 +13,7 @@ * @buf: pointer to data buffer * @size: data size in bytes to read the device * - * Return: 0 if OK, -ve on error + * Return: number of bytes read if OK (may be 0 if EOF), -ve on error */ int misc_read(struct udevice *dev, int offset, void *buf, int size); @@ -24,7 +24,7 @@ int misc_read(struct udevice *dev, int offset, void *buf, int size); * @buf: pointer to data buffer * @size: data size in bytes to write the device * - * Return: 0 if OK, -ve on error + * Return: number of bytes written if OK (may be < @size), -ve on error */ int misc_write(struct udevice *dev, int offset, void *buf, int size); @@ -90,7 +90,7 @@ struct misc_ops { * @buf: pointer to data buffer * @size: data size in bytes to read the device * - * Return: 0 if OK, -ve on error + * Return: number of bytes read if OK (may be 0 if EOF), -ve on error */ int (*read)(struct udevice *dev, int offset, void *buf, int size); @@ -101,7 +101,7 @@ struct misc_ops { * @buf: pointer to data buffer * @size: data size in bytes to write the device * - * Return: 0 if OK, -ve on error + * Return: number of bytes written if OK (may be < @size), -ve on error */ int (*write)(struct udevice *dev, int offset, const void *buf, int size); diff --git a/include/netdev.h b/include/netdev.h index 55001625fb..0a1a3a2d8d 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr); int fec_initialize (bd_t *bis); int fecmxc_initialize(bd_t *bis); int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr); -int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); void gt6426x_eth_initialize(bd_t *bis); diff --git a/include/ns16550.h b/include/ns16550.h index 5fcbcd2e74..22b89e4d6d 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -49,14 +49,16 @@ * struct ns16550_platdata - information about a NS16550 port * * @base: Base register address + * @reg_width: IO accesses size of registers (in bytes) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) * @clock: UART base clock speed in Hz */ struct ns16550_platdata { unsigned long base; + int reg_width; int reg_shift; - int clock; int reg_offset; + int clock; u32 fcr; }; diff --git a/include/os.h b/include/os.h index 28eb625284..6f33b08cf0 100644 --- a/include/os.h +++ b/include/os.h @@ -350,4 +350,18 @@ int os_mprotect_allow(void *start, size_t len); */ int os_write_file(const char *name, const void *buf, int size); +/** + * os_read_file() - Read a file from the host filesystem + * + * This can be useful when reading test data into sandbox for use by test + * routines. The data is allocated using os_malloc() and should be freed by + * the caller. + * + * @name: File path to read from + * @bufp: Returns buffer containing data read + * @sizep: Returns size of data + * @return 0 if OK, -ve on error + */ +int os_read_file(const char *name, void **bufp, int *sizep); + #endif diff --git a/include/palmas.h b/include/palmas.h index 229de53715..20c7e489c1 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -117,6 +117,7 @@ #define BB_VSEL_VBAT (3 << 1) #define BB_CHRG_EN (1 << 0) +#ifndef CONFIG_DM_I2C /* * Functions to read and write from TPS659038/TWL6035/TWL6037 * or other Palmas family of TI PMICs @@ -130,6 +131,10 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) { return i2c_read(chip_no, reg, 1, val, 1); } +#else +int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val); +int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +#endif void palmas_init_settings(void); int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage); diff --git a/include/pci.h b/include/pci.h index 938a8390cb..785d7d28b7 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1312,6 +1312,29 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, */ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); +/** + * dm_pci_find_next_capability() - find a capability starting from an offset + * + * Tell if a device supports a given PCI capability. Returns the + * address of the requested capability structure within the device's + * PCI configuration space or 0 in case the device does not support it. + * + * Possible values for @cap: + * + * %PCI_CAP_ID_MSI Message Signalled Interrupts + * %PCI_CAP_ID_PCIX PCI-X + * %PCI_CAP_ID_EXP PCI Express + * %PCI_CAP_ID_MSIX MSI-X + * + * See PCI_CAP_ID_xxx for the complete capability ID codes. + * + * @dev: PCI device to query + * @start: offset to start from + * @cap: capability code + * @return: capability address or 0 if not supported + */ +int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); + /** * dm_pci_find_capability() - find a capability * @@ -1334,6 +1357,31 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); */ int dm_pci_find_capability(struct udevice *dev, int cap); +/** + * dm_pci_find_next_ext_capability() - find an extended capability + * starting from an offset + * + * Tell if a device supports a given PCI express extended capability. + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 in case the device + * does not support it. + * + * Possible values for @cap: + * + * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting + * %PCI_EXT_CAP_ID_VC Virtual Channel + * %PCI_EXT_CAP_ID_DSN Device Serial Number + * %PCI_EXT_CAP_ID_PWR Power Budgeting + * + * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. + * + * @dev: PCI device to query + * @start: offset to start from + * @cap: extended capability code + * @return: extended capability address or 0 if not supported + */ +int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); + /** * dm_pci_find_ext_capability() - find an extended capability * diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 00fbab80cb..669a94a6c8 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -80,6 +80,8 @@ enum { #define TPS65217_PWR_SRC_USB_BITMASK 0x4 #define TPS65217_PWR_SRC_AC_BITMASK 0x8 +int power_tps65217_init(unsigned char bus); + int tps65217_reg_read(uchar src_reg, uchar *src_val); int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, uchar mask); diff --git a/include/power/tps65910.h b/include/power/tps65910.h index 48e0b2c5ab..21b2a21ee0 100644 --- a/include/power/tps65910.h +++ b/include/power/tps65910.h @@ -72,6 +72,7 @@ enum { #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) +int power_tps65910_init(unsigned char bus); int tps65910_set_i2c_control(void); int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); #endif /* __POWER_TPS65910_H__ */ diff --git a/include/regmap.h b/include/regmap.h index 6a574eaa41..a3afb72df5 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -7,6 +7,61 @@ #ifndef __REGMAP_H #define __REGMAP_H +/** + * DOC: Overview + * + * Regmaps are an abstraction mechanism that allows device drivers to access + * register maps irrespective of the underlying bus architecture. This entails + * that for devices that support multiple busses (e.g. I2C and SPI for a GPIO + * expander chip) only one driver has to be written. This driver will + * instantiate a regmap with a backend depending on the bus the device is + * attached to, and use the regmap API to access the register map through that + * bus transparently. + * + * Read and write functions are supplied, which can read/write data of + * arbitrary length from/to the regmap. + * + * The endianness of regmap accesses is selectable for each map through device + * tree settings via the boolean "little-endian", "big-endian", and + * "native-endian" properties. + * + * Furthermore, the register map described by a regmap can be split into + * multiple disjoint areas called ranges. In this way, register maps with + * "holes", i.e. areas of addressable memory that are not part of the register + * map, can be accessed in a concise manner. + * + * Currently, only a bare "mem" backend for regmaps is supported, which + * accesses the register map as regular IO-mapped memory. + */ + +/** + * enum regmap_size_t - Access sizes for regmap reads and writes + * + * @REGMAP_SIZE_8: 8-bit read/write access size + * @REGMAP_SIZE_16: 16-bit read/write access size + * @REGMAP_SIZE_32: 32-bit read/write access size + * @REGMAP_SIZE_64: 64-bit read/write access size + */ +enum regmap_size_t { + REGMAP_SIZE_8 = 1, + REGMAP_SIZE_16 = 2, + REGMAP_SIZE_32 = 4, + REGMAP_SIZE_64 = 8, +}; + +/** + * enum regmap_endianness_t - Endianness for regmap reads and writes + * + * @REGMAP_NATIVE_ENDIAN: Native endian read/write accesses + * @REGMAP_LITTLE_ENDIAN: Little endian read/write accesses + * @REGMAP_BIG_ENDIAN: Big endian read/write accesses + */ +enum regmap_endianness_t { + REGMAP_NATIVE_ENDIAN, + REGMAP_LITTLE_ENDIAN, + REGMAP_BIG_ENDIAN, +}; + /** * struct regmap_range - a register map range * @@ -21,10 +76,11 @@ struct regmap_range { /** * struct regmap - a way of accessing hardware/bus registers * - * @range_count: Number of ranges available within the map - * @ranges: Array of ranges + * @range_count: Number of ranges available within the map + * @ranges: Array of ranges */ struct regmap { + enum regmap_endianness_t endianness; int range_count; struct regmap_range ranges[0]; }; @@ -33,14 +89,193 @@ struct regmap { * Interface to provide access to registers either through a direct memory * bus or through a peripheral bus like I2C, SPI. */ + +/** + * regmap_write() - Write a 32-bit value to a regmap + * + * @map: Regmap to write to + * @offset: Offset in the regmap to write to + * @val: Data to write to the regmap at the specified offset + * + * Note that this function will only write values of 32 bit width to the + * regmap; if the size of data to be read is different, the regmap_raw_write + * function can be used. + * + * Return: 0 if OK, -ve on error + */ int regmap_write(struct regmap *map, uint offset, uint val); + +/** + * regmap_read() - Read a 32-bit value from a regmap + * + * @map: Regmap to read from + * @offset: Offset in the regmap to read from + * @valp: Pointer to the buffer to receive the data read from the regmap + * at the specified offset + * + * Note that this function will only read values of 32 bit width from the + * regmap; if the size of data to be read is different, the regmap_raw_read + * function can be used. + * + * Return: 0 if OK, -ve on error + */ int regmap_read(struct regmap *map, uint offset, uint *valp); -#define regmap_write32(map, ptr, member, val) \ - regmap_write(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), val) +/** + * regmap_raw_write() - Write a value of specified length to a regmap + * + * @map: Regmap to write to + * @offset: Offset in the regmap to write to + * @val: Value to write to the regmap at the specified offset + * @val_len: Length of the data to be written to the regmap + * + * Note that this function will, as opposed to regmap_write, write data of + * arbitrary length to the regmap, and not just 32-bit values, and is thus a + * generalized version of regmap_write. + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_write(struct regmap *map, uint offset, const void *val, + size_t val_len); -#define regmap_read32(map, ptr, member, valp) \ - regmap_read(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), valp) +/** + * regmap_raw_read() - Read a value of specified length from a regmap + * + * @map: Regmap to read from + * @offset: Offset in the regmap to read from + * @valp: Pointer to the buffer to receive the data read from the regmap + * at the specified offset + * @val_len: Length of the data to be read from the regmap + * + * Note that this function will, as opposed to regmap_read, read data of + * arbitrary length from the regmap, and not just 32-bit values, and is thus a + * generalized version of regmap_read. + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_read(struct regmap *map, uint offset, void *valp, + size_t val_len); + +/** + * regmap_raw_write_range() - Write a value of specified length to a range of a + * regmap + * + * @map: Regmap to write to + * @range_num: Number of the range in the regmap to write to + * @offset: Offset in the regmap to write to + * @val: Value to write to the regmap at the specified offset + * @val_len: Length of the data to be written to the regmap + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, + const void *val, size_t val_len); + +/** + * regmap_raw_read_range() - Read a value of specified length from a range of a + * regmap + * + * @map: Regmap to read from + * @range_num: Number of the range in the regmap to write to + * @offset: Offset in the regmap to read from + * @valp: Pointer to the buffer to receive the data read from the regmap + * at the specified offset + * @val_len: Length of the data to be read from the regmap + * + * Return: 0 if OK, -ve on error + */ +int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, + void *valp, size_t val_len); + +/** + * regmap_range_set() - Set a value in a regmap range described by a struct + * @map: Regmap in which a value should be set + * @range: Range of the regmap in which a value should be set + * @type: Structure type that describes the memory layout of the regmap range + * @member: Member of the describing structure that should be set in the regmap + * range + * @val: Value which should be written to the regmap range + */ +#define regmap_range_set(map, range, type, member, val) \ + do { \ + typeof(((type *)0)->member) __tmp = val; \ + regmap_raw_write_range(map, range, offsetof(type, member), \ + &__tmp, sizeof(((type *)0)->member)); \ + } while (0) + +/** + * regmap_set() - Set a value in a regmap described by a struct + * @map: Regmap in which a value should be set + * @type: Structure type that describes the memory layout of the regmap + * @member: Member of the describing structure that should be set in the regmap + * @val: Value which should be written to the regmap + */ +#define regmap_set(map, type, member, val) \ + regmap_range_set(map, 0, type, member, val) + +/** + * regmap_range_get() - Get a value from a regmap range described by a struct + * @map: Regmap from which a value should be read + * @range: Range of the regmap from which a value should be read + * @type: Structure type that describes the memory layout of the regmap + * range + * @member: Member of the describing structure that should be read in the + * regmap range + * @valp: Variable that receives the value read from the regmap range + */ +#define regmap_range_get(map, range, type, member, valp) \ + regmap_raw_read_range(map, range, offsetof(type, member), \ + (void *)valp, sizeof(((type *)0)->member)) + +/** + * regmap_get() - Get a value from a regmap described by a struct + * @map: Regmap from which a value should be read + * @type: Structure type that describes the memory layout of the regmap + * range + * @member: Member of the describing structure that should be read in the + * regmap + * @valp: Variable that receives the value read from the regmap + */ +#define regmap_get(map, type, member, valp) \ + regmap_range_get(map, 0, type, member, valp) + +/** + * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs + * + * @map: Regmap to read from + * @addr: Offset to poll + * @val: Unsigned integer variable to read the value into + * @cond: Break condition (usually involving @val) + * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). + * @timeout_ms: Timeout in ms, 0 means never timeout + * + * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read + * error return value in case of a error read. In the two former cases, + * the last read value at @addr is stored in @val. Must not be called + * from atomic context if sleep_us or timeout_us are used. + * + * This is modelled after the regmap_read_poll_timeout macros in linux but + * with millisecond timeout. + */ +#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_ms) \ +({ \ + unsigned long __start = get_timer(0); \ + int __ret; \ + for (;;) { \ + __ret = regmap_read((map), (addr), &(val)); \ + if (__ret) \ + break; \ + if (cond) \ + break; \ + if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \ + __ret = regmap_read((map), (addr), &(val)); \ + break; \ + } \ + if ((sleep_us)) \ + udelay((sleep_us)); \ + } \ + __ret ?: ((cond) ? 0 : -ETIMEDOUT); \ +}) /** * regmap_update_bits() - Perform a read/modify/write using a mask @@ -49,31 +284,36 @@ int regmap_read(struct regmap *map, uint offset, uint *valp); * @offset: Offset of the memory * @mask: Mask to apply to the read value * @val: Value to apply to the value to write + * Return: 0 if OK, -ve on error */ int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val); /** * regmap_init_mem() - Set up a new register map that uses memory access * - * Use regmap_uninit() to free it. - * * @node: Device node that uses this map * @mapp: Returns allocated map + * Return: 0 if OK, -ve on error + * + * Use regmap_uninit() to free it. */ int regmap_init_mem(ofnode node, struct regmap **mapp); /** - * regmap_init_mem_platdata() - Set up a new memory register map for of-platdata + * regmap_init_mem_platdata() - Set up a new memory register map for + * of-platdata + * + * @dev: Device that uses this map + * @reg: List of address, size pairs + * @count: Number of pairs (e.g. 1 if the regmap has a single entry) + * @mapp: Returns allocated map + * Return: 0 if OK, -ve on error * * This creates a new regmap with a list of regions passed in, rather than * using the device tree. It only supports 32-bit machines. * * Use regmap_uninit() to free it. * - * @dev: Device that uses this map - * @reg: List of address, size pairs - * @count: Number of pairs (e.g. 1 if the regmap has a single entry) - * @mapp: Returns allocated map */ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, struct regmap **mapp); @@ -83,11 +323,15 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, * * @map: Regmap to query * @range_num: Range to look up + * Return: Pointer to the range in question if OK, NULL on error */ void *regmap_get_range(struct regmap *map, unsigned int range_num); /** * regmap_uninit() - free a previously inited regmap + * + * @map: Regmap to free + * Return: 0 if OK, -ve on error */ int regmap_uninit(struct regmap *map); diff --git a/include/rtc.h b/include/rtc.h index 0d964d56d5..2c3a5743e3 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -86,7 +86,7 @@ struct rtc_ops { int dm_rtc_get(struct udevice *dev, struct rtc_time *time); /** - * dm_rtc_put() - Write a time to an RTC + * dm_rtc_set() - Write a time to an RTC * * @dev: Device to read from * @time: Time to write into the RTC diff --git a/include/serial.h b/include/serial.h index 020cd392e8..c1a9fee250 100644 --- a/include/serial.h +++ b/include/serial.h @@ -75,6 +75,8 @@ enum serial_par { #define SERIAL_PAR_SHIFT 0 #define SERIAL_PAR_MASK (0x03 << SERIAL_PAR_SHIFT) +#define SERIAL_SET_PARITY(parity) \ + ((parity << SERIAL_PAR_SHIFT) & SERIAL_PAR_MASK) #define SERIAL_GET_PARITY(config) \ ((config & SERIAL_PAR_MASK) >> SERIAL_PAR_SHIFT) @@ -87,6 +89,8 @@ enum serial_bits { #define SERIAL_BITS_SHIFT 2 #define SERIAL_BITS_MASK (0x3 << SERIAL_BITS_SHIFT) +#define SERIAL_SET_BITS(bits) \ + ((bits << SERIAL_BITS_SHIFT) & SERIAL_BITS_MASK) #define SERIAL_GET_BITS(config) \ ((config & SERIAL_BITS_MASK) >> SERIAL_BITS_SHIFT) @@ -99,6 +103,8 @@ enum serial_stop { #define SERIAL_STOP_SHIFT 4 #define SERIAL_STOP_MASK (0x3 << SERIAL_STOP_SHIFT) +#define SERIAL_SET_STOP(stop) \ + ((stop << SERIAL_STOP_SHIFT) & SERIAL_STOP_MASK) #define SERIAL_GET_STOP(config) \ ((config & SERIAL_STOP_MASK) >> SERIAL_STOP_SHIFT) @@ -107,9 +113,43 @@ enum serial_stop { bits << SERIAL_BITS_SHIFT | \ stop << SERIAL_STOP_SHIFT) -#define SERIAL_DEFAULT_CONFIG SERIAL_PAR_NONE << SERIAL_PAR_SHIFT | \ - SERIAL_8_BITS << SERIAL_BITS_SHIFT | \ - SERIAL_ONE_STOP << SERIAL_STOP_SHIFT +#define SERIAL_DEFAULT_CONFIG \ + (SERIAL_PAR_NONE << SERIAL_PAR_SHIFT | \ + SERIAL_8_BITS << SERIAL_BITS_SHIFT | \ + SERIAL_ONE_STOP << SERIAL_STOP_SHIFT) + +enum serial_chip_type { + SERIAL_CHIP_UNKNOWN = -1, + SERIAL_CHIP_16550_COMPATIBLE, +}; + +enum adr_space_type { + SERIAL_ADDRESS_SPACE_MEMORY = 0, + SERIAL_ADDRESS_SPACE_IO, +}; + +/** + * struct serial_device_info - structure to hold serial device info + * + * @type: type of the UART chip + * @addr_space: address space to access the registers + * @addr: physical address of the registers + * @reg_width: size (in bytes) of the IO accesses to the registers + * @reg_offset: offset to apply to the @addr from the start of the registers + * @reg_shift: quantity to shift the register offsets by + * @baudrate: baud rate + */ +struct serial_device_info { + enum serial_chip_type type; + enum adr_space_type addr_space; + ulong addr; + u8 reg_width; + u8 reg_offset; + u8 reg_shift; + unsigned int baudrate; +}; + +#define SERIAL_DEFAULT_ADDRESS 0xBADACCE5 /** * struct struct dm_serial_ops - Driver model serial operations @@ -189,10 +229,10 @@ struct dm_serial_ops { #endif /** - * setconfig() - Set up the uart configuration + * getconfig() - Get the uart configuration * (parity, 5/6/7/8 bits word length, stop bits) * - * Set up a new config for this device. + * Get a current config for this device. * * @dev: Device pointer * @parity: parity to use @@ -200,7 +240,25 @@ struct dm_serial_ops { * @stop: stop bits number to use * @return 0 if OK, -ve on error */ + int (*getconfig)(struct udevice *dev, uint *serial_config); + /** + * setconfig() - Set up the uart configuration + * (parity, 5/6/7/8 bits word length, stop bits) + * + * Set up a new config for this device. + * + * @dev: Device pointer + * @serial_config: number of bits, parity and number of stopbits to use + * @return 0 if OK, -ve on error + */ int (*setconfig)(struct udevice *dev, uint serial_config); + /** + * getinfo() - Get serial device information + * + * @dev: Device pointer + * @info: struct serial_device_info to fill + */ + int (*getinfo)(struct udevice *dev, struct serial_device_info *info); }; /** @@ -226,7 +284,6 @@ struct serial_dev_priv { void atmel_serial_initialize(void); void mcf_serial_initialize(void); void mpc85xx_serial_initialize(void); -void mpc8xx_serial_initialize(void); void mxc_serial_initialize(void); void ns16550_serial_initialize(void); void pl01x_serial_initialize(void); diff --git a/include/sound.h b/include/sound.h index 3269f2371c..b7959cc260 100644 --- a/include/sound.h +++ b/include/sound.h @@ -7,14 +7,6 @@ #ifndef __SOUND_H__ #define __SOUND_H__ -/* sound codec enum */ -enum en_sound_codec { - CODEC_WM_8994, - CODEC_WM_8995, - CODEC_MAX_98095, - CODEC_MAX -}; - /* sound codec enum */ enum sound_compat { AUDIO_COMPAT_SPI, @@ -25,31 +17,81 @@ enum sound_compat { struct sound_codec_info { int i2c_bus; int i2c_dev_addr; - enum en_sound_codec codec_type; }; -/* +/** + * struct sound_uc_priv - private uclass information about each sound device + * + * This is used to line the codec and i2s together + * + * @codec: Codec that is used for this sound device + * @i2s: I2S bus that is used for this sound device + * @setup_done: true if setup() has been called + */ +struct sound_uc_priv { + struct udevice *codec; + struct udevice *i2s; + int setup_done; +}; + +/** * Generates square wave sound data for 1 second * - * @param data data buffer pointer - * @param size size of the buffer - * @param freq frequency of the wave + * @sample_rate: Sample rate in Hz + * @data: data buffer pointer + * @size: size of the buffer in bytes + * @freq: frequency of the wave + * @channels: Number of channels to use */ -void sound_create_square_wave(unsigned short *data, int size, uint32_t freq); +void sound_create_square_wave(uint sample_rate, unsigned short *data, int size, + uint freq, uint channels); /* - * Initialises audio sub system - * @param blob Pointer of device tree node or NULL if none. - * @return int value 0 for success, -1 for error + * The sound uclass brings together a data transport (currently only I2C) and a + * codec (currently connected over I2C). */ -int sound_init(const void *blob); -/* - * plays the pcm data buffer in pcm_data.h through i2s1 to make the - * sine wave sound +/* Operations for sound */ +struct sound_ops { + /** + * setup() - Set up to play a sound + */ + int (*setup)(struct udevice *dev); + + /** + * play() - Play a beep + * + * @dev: Sound device + * @data: Data buffer to play + * @data_size: Size of data buffer in bytes + * @return 0 if OK, -ve on error + */ + int (*play)(struct udevice *dev, void *data, uint data_size); +}; + +#define sound_get_ops(dev) ((struct sound_ops *)(dev)->driver->ops) + +/** + * setup() - Set up to play a sound + */ +int sound_setup(struct udevice *dev); + +/** + * play() - Play a beep * - * @return int 0 for success, -1 for error + * @dev: Sound device + * @msecs: Duration of beep in milliseconds + * @frequency_hz: Frequency of the beep in Hertz + * @return 0 if OK, -ve on error */ -int sound_play(uint32_t msec, uint32_t frequency); +int sound_beep(struct udevice *dev, int msecs, int frequency_hz); + +/** + * sound_find_codec_i2s() - Called by sound drivers to locate codec and i2s + * + * This finds the audio codec and i2s devices and puts them in the uclass's + * private data for this device. + */ +int sound_find_codec_i2s(struct udevice *dev); #endif /* __SOUND__H__ */ diff --git a/include/spi.h b/include/spi.h index 96873cfd85..2b74930429 100644 --- a/include/spi.h +++ b/include/spi.h @@ -148,13 +148,6 @@ struct spi_slave { #define SPI_XFER_U_PAGE BIT(4) }; -/** - * Initialization, must be called once on start up. - * - * TODO: I don't think we really need this. - */ -void spi_init(void); - /** * spi_do_alloc_slave - Allocate a new SPI slave (internal) * diff --git a/include/spi_flash.h b/include/spi_flash.h index d28b9d15f1..feea9a9062 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -115,6 +115,19 @@ struct dm_spi_flash_ops { int (*write)(struct udevice *dev, u32 offset, size_t len, const void *buf); int (*erase)(struct udevice *dev, u32 offset, size_t len); + /** + * get_sw_write_prot() - Check state of software write-protect feature + * + * SPI flash chips can lock a region of the flash defined by a + * 'protected area'. This function checks if this protected area is + * defined. + * + * @dev: SPI flash device + * @return 0 if no region is write-protected, 1 if a region is + * write-protected, -ENOSYS if the driver does not implement this, + * other -ve value on error + */ + int (*get_sw_write_prot)(struct udevice *dev); }; /* Access the serial operations for a device */ @@ -156,6 +169,20 @@ int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len, */ int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len); +/** + * spl_flash_get_sw_write_prot() - Check state of software write-protect feature + * + * SPI flash chips can lock a region of the flash defined by a + * 'protected area'. This function checks if this protected area is + * defined. + * + * @dev: SPI flash device + * @return 0 if no region is write-protected, 1 if a region is + * write-protected, -ENOSYS if the driver does not implement this, + * other -ve value on error + */ +int spl_flash_get_sw_write_prot(struct udevice *dev); + int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode, struct udevice **devp); diff --git a/include/spl.h b/include/spl.h index 9a439f468b..c82f2fd033 100644 --- a/include/spl.h +++ b/include/spl.h @@ -11,6 +11,7 @@ /* Platform-specific defines */ #include #include +#include /* Value in r0 indicates we booted from U-Boot */ #define UBOOT_NOT_LOADED_FROM_SPL 0x13578642 @@ -21,6 +22,46 @@ #define MMCSD_MODE_FS 2 #define MMCSD_MODE_EMMCBOOT 3 +/* + * u_boot_first_phase() - check if this is the first U-Boot phase + * + * U-Boot has up to three phases: TPL, SPL and U-Boot proper. Depending on the + * build flags we can determine whether the current build is for the first + * phase of U-Boot or not. If there is no SPL, then this is U-Boot proper. If + * there is SPL but no TPL, the the first phase is SPL. If there is TPL, then + * it is the first phase. + * + * @returns true if this is the first phase of U-Boot + * + */ +static inline bool u_boot_first_phase(void) +{ + if (IS_ENABLED(CONFIG_TPL)) { + if (IS_ENABLED(CONFIG_TPL_BUILD)) + return true; + } else if (IS_ENABLED(CONFIG_SPL)) { + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return true; + } else { + return true; + } + + return false; +} + +/* A string name for SPL or TPL */ +#ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_TPL_BUILD +# define SPL_TPL_NAME "TPL" +# else +# define SPL_TPL_NAME "SPL" +# endif +# define SPL_TPL_PROMPT SPL_TPL_NAME ": " +#else +# define SPL_TPL_NAME "" +# define SPL_TPL_PROMPT "" +#endif + struct spl_image_info { const char *name; u8 os; @@ -77,6 +118,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 +#define SPL_FIT_FOUND 2 /* SPL common functions */ void preloader_console_init(void); @@ -311,6 +353,18 @@ void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); */ void board_return_to_bootrom(void); +/** + * board_spl_fit_post_load - allow process images after loading finished + * + */ +void board_spl_fit_post_load(ulong load_addr, size_t length); + +/** + * board_spl_fit_size_align - specific size align before processing payload + * + */ +ulong board_spl_fit_size_align(ulong size); + /** * spl_perform_fixups() - arch/board-specific callback before processing * the boot-payload diff --git a/include/syscon.h b/include/syscon.h index 2aa73e520a..3df96e3276 100644 --- a/include/syscon.h +++ b/include/syscon.h @@ -73,6 +73,19 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp); */ struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data); +/** + * syscon_regmap_lookup_by_phandle() - Look up a controller by a phandle + * + * This operates by looking up the given name in the device (device + * tree property) of the device using the system controller. + * + * @dev: Device using the system controller + * @name: Name of property referring to the system controller + * @return A pointer to the regmap if found, ERR_PTR(-ve) on error + */ +struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev, + const char *name); + /** * syscon_get_first_range() - get the first memory range from a syscon regmap * diff --git a/include/tee.h b/include/tee.h index 98b1c9cc69..edd9f9b0c9 100644 --- a/include/tee.h +++ b/include/tee.h @@ -34,6 +34,7 @@ * struct tee_version_data::gen_caps */ #define TEE_SUCCESS 0x00000000 +#define TEE_ERROR_STORAGE_NOT_AVAILABLE 0xf0100003 #define TEE_ERROR_GENERIC 0xffff0000 #define TEE_ERROR_BAD_PARAMETERS 0xffff0006 #define TEE_ERROR_ITEM_NOT_FOUND 0xffff0008 diff --git a/include/test/suites.h b/include/test/suites.h index abb3a4b816..77d863b4a6 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -23,6 +23,7 @@ struct unit_test; int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents, int argc, char * const argv[]); +int do_ut_bloblist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/include/tpm-common.h b/include/tpm-common.h index 5f8bc6bc52..f9c2ca2053 100644 --- a/include/tpm-common.h +++ b/include/tpm-common.h @@ -26,6 +26,8 @@ enum tpm_duration { /* Max buffer size supported by our tpm */ #define TPM_DEV_BUFSIZE 1260 +#define TPM_PCR_MINIMUM_DIGEST_SIZE 20 + /** * enum tpm_version - The version of the TPM stack to be used * @TPM_V1: Use TPM v1.x stack @@ -174,11 +176,47 @@ struct tpm_ops { int do_##cmd(cmd_tbl_t *cmdtp, int flag, \ int argc, char * const argv[]) \ { \ + struct udevice *dev; \ + int rc; \ + \ + rc = get_tpm(&dev); \ + if (rc) \ + return rc; \ if (argc != 1) \ return CMD_RET_USAGE; \ - return report_return_code(cmd()); \ + return report_return_code(cmd(dev)); \ } +/** + * tpm_open() - Request access to locality 0 for the caller + * + * After all commands have been completed the caller is supposed to + * call tpm_close(). + * + * @dev - TPM device + * Returns 0 on success, -ve on failure. + */ +int tpm_open(struct udevice *dev); + +/** + * tpm_close() - Close the current session + * + * Releasing the locked locality. Returns 0 on success, -ve 1 on + * failure (in case lock removal did not succeed). + * + * @dev - TPM device + * Returns 0 on success, -ve on failure. + */ +int tpm_close(struct udevice *dev); + +/** + * tpm_clear_and_reenable() - Force clear the TPM and reenable it + * + * @dev: TPM device + * @return 0 on success, -ve on failure + */ +u32 tpm_clear_and_reenable(struct udevice *dev); + /** * tpm_get_desc() - Get a text description of the TPM * @@ -202,6 +240,7 @@ int tpm_get_desc(struct udevice *dev, char *buf, int size); * Note that the outgoing data is inspected to determine command type * (ordinal) and a timeout is used for that command type. * + * @dev - TPM device * @sendbuf - buffer of the data to send * @send_size size of the data to send * @recvbuf - memory to save the response to @@ -216,9 +255,10 @@ int tpm_xfer(struct udevice *dev, const u8 *sendbuf, size_t send_size, /** * Initialize TPM device. It must be called before any TPM commands. * + * @dev - TPM device * @return 0 on success, non-0 on error. */ -int tpm_init(void); +int tpm_init(struct udevice *dev); /** * Retrieve the array containing all the v1 (resp. v2) commands. @@ -242,4 +282,15 @@ static inline cmd_tbl_t *get_tpm2_commands(unsigned int *size) } #endif +/** + * tpm_get_version() - Find the version of a TPM + * + * This checks the uclass data for a TPM device and returns the version number + * it supports. + * + * @dev: TPM device + * @return version number (TPM_V1 or TPMV2) + */ +enum tpm_version tpm_get_version(struct udevice *dev); + #endif /* __TPM_COMMON_H */ diff --git a/include/tpm-v1.h b/include/tpm-v1.h index be2eca946f..45b7a4831d 100644 --- a/include/tpm-v1.h +++ b/include/tpm-v1.h @@ -282,64 +282,72 @@ struct __packed tpm_nv_data_public { /** * Issue a TPM_Startup command. * + * @param dev TPM device * @param mode TPM startup mode * @return return code of the operation */ -u32 tpm_startup(enum tpm_startup_type mode); +u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode); /** * Issue a TPM_SelfTestFull command. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_self_test_full(void); +u32 tpm_self_test_full(struct udevice *dev); /** * Issue a TPM_ContinueSelfTest command. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_continue_self_test(void); +u32 tpm_continue_self_test(struct udevice *dev); /** * Issue a TPM_NV_DefineSpace command. The implementation is limited * to specify TPM_NV_ATTRIBUTES and size of the area. The area index * could be one of the special value listed in enum tpm_nv_index. * + * @param dev TPM device * @param index index of the area * @param perm TPM_NV_ATTRIBUTES of the area * @param size size of the area * @return return code of the operation */ -u32 tpm_nv_define_space(u32 index, u32 perm, u32 size); +u32 tpm_nv_define_space(struct udevice *dev, u32 index, u32 perm, u32 size); /** * Issue a TPM_NV_ReadValue command. This implementation is limited * to read the area from offset 0. The area index could be one of * the special value listed in enum tpm_nv_index. * + * @param dev TPM device * @param index index of the area * @param data output buffer of the area contents * @param count size of output buffer * @return return code of the operation */ -u32 tpm_nv_read_value(u32 index, void *data, u32 count); +u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count); /** * Issue a TPM_NV_WriteValue command. This implementation is limited * to write the area from offset 0. The area index could be one of * the special value listed in enum tpm_nv_index. * + * @param dev TPM device * @param index index of the area * @param data input buffer to be wrote to the area * @param length length of data bytes of input buffer * @return return code of the operation */ -u32 tpm_nv_write_value(u32 index, const void *data, u32 length); +u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data, + u32 length); /** * Issue a TPM_Extend command. * + * @param dev TPM device * @param index index of the PCR * @param in_digest 160-bit value representing the event to be * recorded @@ -347,69 +355,78 @@ u32 tpm_nv_write_value(u32 index, const void *data, u32 length); * command * @return return code of the operation */ -u32 tpm_extend(u32 index, const void *in_digest, void *out_digest); +u32 tpm_extend(struct udevice *dev, u32 index, const void *in_digest, + void *out_digest); /** * Issue a TPM_PCRRead command. * + * @param dev TPM device * @param index index of the PCR * @param data output buffer for contents of the named PCR * @param count size of output buffer * @return return code of the operation */ -u32 tpm_pcr_read(u32 index, void *data, size_t count); +u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count); /** * Issue a TSC_PhysicalPresence command. TPM physical presence flag * is bit-wise OR'ed of flags listed in enum tpm_physical_presence. * + * @param dev TPM device * @param presence TPM physical presence flag * @return return code of the operation */ -u32 tpm_tsc_physical_presence(u16 presence); +u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence); /** * Issue a TPM_ReadPubek command. * + * @param dev TPM device * @param data output buffer for the public endorsement key * @param count size of output buffer * @return return code of the operation */ -u32 tpm_read_pubek(void *data, size_t count); +u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count); /** * Issue a TPM_ForceClear command. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_force_clear(void); +u32 tpm_force_clear(struct udevice *dev); /** * Issue a TPM_PhysicalEnable command. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_physical_enable(void); +u32 tpm_physical_enable(struct udevice *dev); /** * Issue a TPM_PhysicalDisable command. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_physical_disable(void); +u32 tpm_physical_disable(struct udevice *dev); /** * Issue a TPM_PhysicalSetDeactivated command. * + * @param dev TPM device * @param state boolean state of the deactivated flag * @return return code of the operation */ -u32 tpm_physical_set_deactivated(u8 state); +u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state); /** * Issue a TPM_GetCapability command. This implementation is limited * to query sub_cap index that is 4-byte wide. * + * @param dev TPM device * @param cap_area partition of capabilities * @param sub_cap further definition of capability, which is * limited to be 4-byte wide @@ -417,15 +434,17 @@ u32 tpm_physical_set_deactivated(u8 state); * @param count size of output buffer * @return return code of the operation */ -u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count); +u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap, + void *cap, size_t count); /** * Issue a TPM_FlushSpecific command for a AUTH resource. * + * @param dev TPM device * @param auth_handle handle of the auth session * @return return code of the operation */ -u32 tpm_terminate_auth_session(u32 auth_handle); +u32 tpm_terminate_auth_session(struct udevice *dev, u32 auth_handle); /** * Issue a TPM_OIAP command to setup an object independent authorization @@ -434,22 +453,25 @@ u32 tpm_terminate_auth_session(u32 auth_handle); * If there was already an OIAP session active it is terminated and a new * session is set up. * + * @param dev TPM device * @param auth_handle pointer to the (new) auth handle or NULL. * @return return code of the operation */ -u32 tpm_oiap(u32 *auth_handle); +u32 tpm_oiap(struct udevice *dev, u32 *auth_handle); /** * Ends an active OIAP session. * + * @param dev TPM device * @return return code of the operation */ -u32 tpm_end_oiap(void); +u32 tpm_end_oiap(struct udevice *dev); /** * Issue a TPM_LoadKey2 (Auth1) command using an OIAP session for authenticating * the usage of the parent key. * + * @param dev TPM device * @param parent_handle handle of the parent key. * @param key pointer to the key structure (TPM_KEY or TPM_KEY12). * @param key_length size of the key structure @@ -457,13 +479,15 @@ u32 tpm_end_oiap(void); * @param key_handle pointer to the key handle * @return return code of the operation */ -u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, - const void *parent_key_usage_auth, u32 *key_handle); +u32 tpm_load_key2_oiap(struct udevice *dev, u32 parent_handle, const void *key, + size_t key_length, const void *parent_key_usage_auth, + u32 *key_handle); /** * Issue a TPM_GetPubKey (Auth1) command using an OIAP session for * authenticating the usage of the key. * + * @param dev TPM device * @param key_handle handle of the key * @param usage_auth usage auth for the key * @param pubkey pointer to the pub key buffer; may be NULL if the pubkey @@ -473,45 +497,51 @@ u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, * of the stored TPM_PUBKEY structure (iff pubkey != NULL). * @return return code of the operation */ -u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey, +u32 tpm_get_pub_key_oiap(struct udevice *dev, u32 key_handle, + const void *usage_auth, void *pubkey, size_t *pubkey_len); /** * Get the TPM permanent flags value * + * @param dev TPM device * @param pflags Place to put permanent flags * @return return code of the operation */ -u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags); +u32 tpm_get_permanent_flags(struct udevice *dev, + struct tpm_permanent_flags *pflags); /** * Get the TPM permissions * + * @param dev TPM device * @param perm Returns permissions value * @return return code of the operation */ -u32 tpm_get_permissions(u32 index, u32 *perm); +u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm); /** * Flush a resource with a given handle and type from the TPM * + * @param dev TPM device * @param key_handle handle of the resource * @param resource_type type of the resource * @return return code of the operation */ -u32 tpm_flush_specific(u32 key_handle, u32 resource_type); +u32 tpm_flush_specific(struct udevice *dev, u32 key_handle, u32 resource_type); #ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1 /** * Search for a key by usage AuthData and the hash of the parent's pub key. * + * @param dev TPM device * @param auth Usage auth of the key to search for * @param pubkey_digest SHA1 hash of the pub key structure of the key * @param[out] handle The handle of the key (Non-null iff found) * @return 0 if key was found in TPM; != 0 if not. */ -u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20], - u32 *handle); +u32 tpm_find_key_sha1(struct udevice *dev, const u8 auth[20], + const u8 pubkey_digest[20], u32 *handle); #endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */ /** @@ -519,38 +549,43 @@ u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20], * that the TPM may legally return fewer bytes than requested by retrying * until @p count bytes have been received. * + * @param dev TPM device * @param data output buffer for the random bytes * @param count size of output buffer * @return return code of the operation */ -u32 tpm_get_random(void *data, u32 count); +u32 tpm_get_random(struct udevice *dev, void *data, u32 count); /** * tpm_finalise_physical_presence() - Finalise physical presence * + * @param dev TPM device * @return return code of the operation (0 = success) */ -u32 tpm_finalise_physical_presence(void); +u32 tpm_finalise_physical_presence(struct udevice *dev); /** * tpm_nv_set_locked() - lock the non-volatile space * + * @param dev TPM device * @return return code of the operation (0 = success) */ -u32 tpm_nv_set_locked(void); +u32 tpm_nv_set_locked(struct udevice *dev); /** * tpm_set_global_lock() - set the global lock * + * @param dev TPM device * @return return code of the operation (0 = success) */ -u32 tpm_set_global_lock(void); +u32 tpm_set_global_lock(struct udevice *dev); /** * tpm_resume() - start up the TPM from resume (after suspend) * + * @param dev TPM device * @return return code of the operation (0 = success) */ -u32 tpm_resume(void); +u32 tpm_resume(struct udevice *dev); #endif /* __TPM_V1_H */ diff --git a/include/tpm-v2.h b/include/tpm-v2.h index c77b416182..ae00803f6d 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -128,48 +128,87 @@ enum tpm2_algorithms { TPM2_ALG_NULL = 0x10, }; +/* NV index attributes */ +enum tpm_index_attrs { + TPMA_NV_PPWRITE = 1UL << 0, + TPMA_NV_OWNERWRITE = 1UL << 1, + TPMA_NV_AUTHWRITE = 1UL << 2, + TPMA_NV_POLICYWRITE = 1UL << 3, + TPMA_NV_COUNTER = 1UL << 4, + TPMA_NV_BITS = 1UL << 5, + TPMA_NV_EXTEND = 1UL << 6, + TPMA_NV_POLICY_DELETE = 1UL << 10, + TPMA_NV_WRITELOCKED = 1UL << 11, + TPMA_NV_WRITEALL = 1UL << 12, + TPMA_NV_WRITEDEFINE = 1UL << 13, + TPMA_NV_WRITE_STCLEAR = 1UL << 14, + TPMA_NV_GLOBALLOCK = 1UL << 15, + TPMA_NV_PPREAD = 1UL << 16, + TPMA_NV_OWNERREAD = 1UL << 17, + TPMA_NV_AUTHREAD = 1UL << 18, + TPMA_NV_POLICYREAD = 1UL << 19, + TPMA_NV_NO_DA = 1UL << 25, + TPMA_NV_ORDERLY = 1UL << 26, + TPMA_NV_CLEAR_STCLEAR = 1UL << 27, + TPMA_NV_READLOCKED = 1UL << 28, + TPMA_NV_WRITTEN = 1UL << 29, + TPMA_NV_PLATFORMCREATE = 1UL << 30, + TPMA_NV_READ_STCLEAR = 1UL << 31, + + TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD | + TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD, + TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE | + TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE, +}; + /** * Issue a TPM2_Startup command. * + * @dev TPM device * @mode TPM startup mode * * @return code of the operation */ -u32 tpm2_startup(enum tpm2_startup_types mode); +u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode); /** * Issue a TPM2_SelfTest command. * + * @dev TPM device * @full_test Asking to perform all tests or only the untested ones * * @return code of the operation */ -u32 tpm2_self_test(enum tpm2_yes_no full_test); +u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test); /** * Issue a TPM2_Clear command. * + * @dev TPM device * @handle Handle * @pw Password * @pw_sz Length of the password * * @return code of the operation */ -u32 tpm2_clear(u32 handle, const char *pw, const ssize_t pw_sz); +u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, + const ssize_t pw_sz); /** * Issue a TPM2_PCR_Extend command. * + * @dev TPM device * @index Index of the PCR * @digest Value representing the event to be recorded * * @return code of the operation */ -u32 tpm2_pcr_extend(u32 index, const uint8_t *digest); +u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest); /** * Issue a TPM2_PCR_Read command. * + * @dev TPM device * @idx Index of the PCR * @idx_min_sz Minimum size in bytes of the pcrSelect array * @data Output buffer for contents of the named PCR @@ -177,13 +216,14 @@ u32 tpm2_pcr_extend(u32 index, const uint8_t *digest); * * @return code of the operation */ -u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data, - unsigned int *updates); +u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, + void *data, unsigned int *updates); /** * Issue a TPM2_GetCapability command. This implementation is limited * to query property index that is 4-byte wide. * + * @dev TPM device * @capability Partition of capabilities * @property Further definition of capability, limited to be 4 bytes wide * @buf Output buffer for capability information @@ -191,22 +231,24 @@ u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data, * * @return code of the operation */ -u32 tpm2_get_capability(u32 capability, u32 property, void *buf, - size_t prop_count); +u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, + void *buf, size_t prop_count); /** * Issue a TPM2_DictionaryAttackLockReset command. * + * @dev TPM device * @pw Password * @pw_sz Length of the password * * @return code of the operation */ -u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz); +u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz); /** * Issue a TPM2_DictionaryAttackParameters command. * + * @dev TPM device * @pw Password * @pw_sz Length of the password * @max_tries Count of authorizations before lockout @@ -215,13 +257,15 @@ u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz); * * @return code of the operation */ -u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz, - unsigned int max_tries, unsigned int recovery_time, +u32 tpm2_dam_parameters(struct udevice *dev, const char *pw, + const ssize_t pw_sz, unsigned int max_tries, + unsigned int recovery_time, unsigned int lockout_recovery); /** * Issue a TPM2_HierarchyChangeAuth command. * + * @dev TPM device * @handle Handle * @newpw New password * @newpw_sz Length of the new password @@ -230,12 +274,14 @@ u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz, * * @return code of the operation */ -int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz, - const char *oldpw, const ssize_t oldpw_sz); +int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw, + const ssize_t newpw_sz, const char *oldpw, + const ssize_t oldpw_sz); /** * Issue a TPM_PCR_SetAuthPolicy command. * + * @dev TPM device * @pw Platform password * @pw_sz Length of the password * @index Index of the PCR @@ -243,12 +289,13 @@ int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz, * * @return code of the operation */ -u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index, - const char *key); +u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw, + const ssize_t pw_sz, u32 index, const char *key); /** * Issue a TPM_PCR_SetAuthValue command. * + * @dev TPM device * @pw Platform password * @pw_sz Length of the password * @index Index of the PCR @@ -257,7 +304,8 @@ u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index, * * @return code of the operation */ -u32 tpm2_pcr_setauthvalue(const char *pw, const ssize_t pw_sz, u32 index, - const char *key, const ssize_t key_sz); +u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw, + const ssize_t pw_sz, u32 index, const char *key, + const ssize_t key_sz); #endif /* __TPM_V2_H */ diff --git a/include/twl4030.h b/include/twl4030.h index 46a9306246..c27ad615ee 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -648,6 +648,7 @@ * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and * TWL4030_LED_LEDEN. */ +#ifndef CONFIG_DM_I2C static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) { return i2c_write(chip_no, reg, 1, &val, 1); @@ -657,7 +658,10 @@ static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) { return i2c_read(chip_no, reg, 1, val, 1); } - +#else +int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val); +int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +#endif /* * Power */ diff --git a/include/twl6030.h b/include/twl6030.h index 66853439ed..41f17de3ab 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -186,6 +186,7 @@ struct twl6030_data{ }; /* Functions to read and write from TWL6030 */ +#ifndef CONFIG_DM_I2C static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) { return i2c_write(chip_no, reg, 1, &val, 1); @@ -195,6 +196,10 @@ static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) { return i2c_read(chip_no, reg, 1, val, 1); } +#else +int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val); +int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +#endif /* * Power diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index e98cb46c90..788ef29a17 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -11,6 +11,20 @@ /* lib/crc8.c */ unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len); +/* lib/crc16.c - 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */ +uint16_t crc16_ccitt(uint16_t crc_start, const unsigned char *s, int len); +/** + * crc16_ccitt_wd_buf - Perform CRC16-CCIT on an input buffer and return the + * 16-bit result (network byte-order) in an output buffer + * + * @in: input buffer + * @len: input buffer length + * @out: output buffer (at least 2 bytes) + * @chunk_sz: ignored + */ +void crc16_ccitt_wd_buf(const uint8_t *in, uint len, + uint8_t *out, uint chunk_sz); + /* lib/crc32.c */ uint32_t crc32 (uint32_t, const unsigned char *, uint); uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h index 68bcb14c74..2d3024d8b7 100644 --- a/include/u-boot/rsa.h +++ b/include/u-boot/rsa.h @@ -97,6 +97,16 @@ static inline int rsa_add_verify_data(struct image_sign_info *info, int rsa_verify(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t *sig, uint sig_len); + +int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len); + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len); +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ #else static inline int rsa_verify(struct image_sign_info *info, const struct image_region region[], int region_count, @@ -104,8 +114,26 @@ static inline int rsa_verify(struct image_sign_info *info, { return -ENXIO; } + +static inline int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + return -ENXIO; +} + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +static inline int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + return -ENXIO; +} +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ #endif +#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5" + #define RSA2048_BYTES (2048 / 8) #define RSA4096_BYTES (4096 / 8) diff --git a/include/usb.h b/include/usb.h index b6b48a8c60..420a30e49f 100644 --- a/include/usb.h +++ b/include/usb.h @@ -140,7 +140,7 @@ struct usb_device { int act_len; /* transferred bytes */ int maxchild; /* Number of ports if hub */ int portnr; /* Port number, 1=first */ -#ifndef CONFIG_DM_USB +#if !CONFIG_IS_ENABLED(DM_USB) /* parent hub, or NULL if this is the root hub */ struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; @@ -148,7 +148,7 @@ struct usb_device { #endif /* slot_id - for xHCI enabled devices */ unsigned int slot_id; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; /* Pointer to associated device */ struct udevice *controller_dev; /* Pointer to associated controller */ #endif @@ -173,7 +173,7 @@ enum usb_init_type { int usb_lowlevel_init(int index, enum usb_init_type init, void **controller); int usb_lowlevel_stop(int index); -#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_DM_USB) +#if defined(CONFIG_USB_MUSB_HOST) || CONFIG_IS_ENABLED(DM_USB) int usb_reset_root_port(struct usb_device *dev); #else #define usb_reset_root_port(dev) @@ -187,7 +187,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); #if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_MUSB_HOST \ - || defined(CONFIG_DM_USB) + || CONFIG_IS_ENABLED(DM_USB) struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, int elementsize, void *buffer, int interval); int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); @@ -588,7 +588,7 @@ struct usb_hub_device { struct usb_tt tt; /* Transaction Translator */ }; -#ifdef CONFIG_DM_USB +#if CONFIG_IS_ENABLED(DM_USB) /** * struct usb_platdata - Platform data about a USB controller * @@ -912,7 +912,7 @@ int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp); */ void usb_stor_reset(void); -#else /* !CONFIG_DM_USB */ +#else /* !CONFIG_IS_ENABLED(DM_USB) */ struct usb_device *usb_get_dev_index(int index); diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 62e32365e2..4068de045d 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -14,7 +14,7 @@ struct dwc2_plat_otg_data { void *priv; int phy_of_node; int (*phy_control)(int on); - unsigned int regs_phy; + uintptr_t regs_phy; uintptr_t regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; diff --git a/include/usb/lin_gadget_compat.h b/include/usb/lin_gadget_compat.h deleted file mode 100644 index e5dba473b7..0000000000 --- a/include/usb/lin_gadget_compat.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 Samsung Electronics - * Lukasz Majewski - * - * This is a Linux kernel compatibility layer for USB Gadget - */ - -#ifndef __LIN_COMPAT_H__ -#define __LIN_COMPAT_H__ - -#include -#include - -/* common */ -#define DECLARE_BITMAP(name, bits) \ - unsigned long name[BITS_TO_LONGS(bits)] - -#define small_const_nbits(nbits) \ - (__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG) - -static inline void bitmap_zero(unsigned long *dst, int nbits) -{ - if (small_const_nbits(nbits)) - *dst = 0UL; - else { - int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long); - memset(dst, 0, len); - } -} - -#define dma_cache_maint(addr, size, mode) cache_flush() -void cache_flush(void); - -#endif /* __LIN_COMPAT_H__ */ diff --git a/include/video.h b/include/video.h index 75200f0e45..1d57b48b17 100644 --- a/include/video.h +++ b/include/video.h @@ -61,7 +61,9 @@ enum video_log2_bpp { * @font_size: Font size in pixels (0 to use a default value) * @fb: Frame buffer * @fb_size: Frame buffer size - * @line_length: Length of each frame buffer line, in bytes + * @line_length: Length of each frame buffer line, in bytes. This can be + * set by the driver, but if not, the uclass will set it after + * probing * @colour_fg: Foreground colour (pixel value) * @colour_bg: Background colour (pixel value) * @flush_dcache: true to enable flushing of the data cache after @@ -191,9 +193,10 @@ void video_set_flush_dcache(struct udevice *dev, bool flush); /** * Set default colors and attributes * - * @priv device information + * @dev: video device + * @invert true to invert colours */ -void video_set_default_colors(struct video_priv *priv); +void video_set_default_colors(struct udevice *dev, bool invert); #endif /* CONFIG_DM_VIDEO */ diff --git a/include/virtio.h b/include/virtio.h new file mode 100644 index 0000000000..654fdf154b --- /dev/null +++ b/include/virtio.h @@ -0,0 +1,707 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * VirtIO is a virtualization standard for network and disk device drivers + * where just the guest's device driver "knows" it is running in a virtual + * environment, and cooperates with the hypervisor. This enables guests to + * get high performance network and disk operations, and gives most of the + * performance benefits of paravirtualization. In the U-Boot case, the guest + * is U-Boot itself, while the virtual environment are normally QEMU targets + * like ARM, RISC-V and x86. + * + * See http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf for + * the VirtIO specification v1.0. + * + * This file is largely based on Linux kernel virtio_*.h files + */ + +#ifndef __VIRTIO_H__ +#define __VIRTIO_H__ + +#define VIRTIO_ID_NET 1 /* virtio net */ +#define VIRTIO_ID_BLOCK 2 /* virtio block */ +#define VIRTIO_ID_MAX_NUM 3 + +#define VIRTIO_NET_DRV_NAME "virtio-net" +#define VIRTIO_BLK_DRV_NAME "virtio-blk" + +/* Status byte for guest to report progress, and synchronize features */ + +/* We have seen device and processed generic fields (VIRTIO_CONFIG_F_VIRTIO) */ +#define VIRTIO_CONFIG_S_ACKNOWLEDGE 1 +/* We have found a driver for the device */ +#define VIRTIO_CONFIG_S_DRIVER 2 +/* Driver has used its parts of the config, and is happy */ +#define VIRTIO_CONFIG_S_DRIVER_OK 4 +/* Driver has finished configuring features */ +#define VIRTIO_CONFIG_S_FEATURES_OK 8 +/* Device entered invalid state, driver must reset it */ +#define VIRTIO_CONFIG_S_NEEDS_RESET 0x40 +/* We've given up on this device */ +#define VIRTIO_CONFIG_S_FAILED 0x80 + +/* + * Virtio feature bits VIRTIO_TRANSPORT_F_START through VIRTIO_TRANSPORT_F_END + * are reserved for the transport being used (eg: virtio_ring, virtio_pci etc.), + * the rest are per-device feature bits. + */ +#define VIRTIO_TRANSPORT_F_START 28 +#define VIRTIO_TRANSPORT_F_END 38 + +#ifndef VIRTIO_CONFIG_NO_LEGACY +/* + * Do we get callbacks when the ring is completely used, + * even if we've suppressed them? + */ +#define VIRTIO_F_NOTIFY_ON_EMPTY 24 + +/* Can the device handle any descriptor layout? */ +#define VIRTIO_F_ANY_LAYOUT 27 +#endif /* VIRTIO_CONFIG_NO_LEGACY */ + +/* v1.0 compliant */ +#define VIRTIO_F_VERSION_1 32 + +/* + * If clear - device has the IOMMU bypass quirk feature. + * If set - use platform tools to detect the IOMMU. + * + * Note the reverse polarity (compared to most other features), + * this is for compatibility with legacy systems. + */ +#define VIRTIO_F_IOMMU_PLATFORM 33 + +/* Does the device support Single Root I/O Virtualization? */ +#define VIRTIO_F_SR_IOV 37 + +/** + * virtio scatter-gather struct + * + * @addr: sg buffer address + * @lengh: sg buffer length + */ +struct virtio_sg { + void *addr; + size_t length; +}; + +struct virtqueue; + +/* virtio bus operations */ +struct dm_virtio_ops { + /** + * get_config() - read the value of a configuration field + * + * @vdev: the real virtio device + * @offset: the offset of the configuration field + * @buf: the buffer to write the field value into + * @len: the length of the buffer + * @return 0 if OK, -ve on error + */ + int (*get_config)(struct udevice *vdev, unsigned int offset, + void *buf, unsigned int len); + /** + * set_config() - write the value of a configuration field + * + * @vdev: the real virtio device + * @offset: the offset of the configuration field + * @buf: the buffer to read the field value from + * @len: the length of the buffer + * @return 0 if OK, -ve on error + */ + int (*set_config)(struct udevice *vdev, unsigned int offset, + const void *buf, unsigned int len); + /** + * generation() - config generation counter + * + * @vdev: the real virtio device + * @counter: the returned config generation counter + * @return 0 if OK, -ve on error + */ + int (*generation)(struct udevice *vdev, u32 *counter); + /** + * get_status() - read the status byte + * + * @vdev: the real virtio device + * @status: the returned status byte + * @return 0 if OK, -ve on error + */ + int (*get_status)(struct udevice *vdev, u8 *status); + /** + * set_status() - write the status byte + * + * @vdev: the real virtio device + * @status: the new status byte + * @return 0 if OK, -ve on error + */ + int (*set_status)(struct udevice *vdev, u8 status); + /** + * reset() - reset the device + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ + int (*reset)(struct udevice *vdev); + /** + * get_features() - get the array of feature bits for this device + * + * @vdev: the real virtio device + * @features: the first 32 feature bits (all we currently need) + * @return 0 if OK, -ve on error + */ + int (*get_features)(struct udevice *vdev, u64 *features); + /** + * set_features() - confirm what device features we'll be using + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ + int (*set_features)(struct udevice *vdev); + /** + * find_vqs() - find virtqueues and instantiate them + * + * @vdev: the real virtio device + * @nvqs: the number of virtqueues to find + * @vqs: on success, includes new virtqueues + * @return 0 if OK, -ve on error + */ + int (*find_vqs)(struct udevice *vdev, unsigned int nvqs, + struct virtqueue *vqs[]); + /** + * del_vqs() - free virtqueues found by find_vqs() + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ + int (*del_vqs)(struct udevice *vdev); + /** + * notify() - notify the device to process the queue + * + * @vdev: the real virtio device + * @vq: virtqueue to process + * @return 0 if OK, -ve on error + */ + int (*notify)(struct udevice *vdev, struct virtqueue *vq); +}; + +/* Get access to a virtio bus' operations */ +#define virtio_get_ops(dev) ((struct dm_virtio_ops *)(dev)->driver->ops) + +/** + * virtio uclass per device private data + * + * @vqs: virtualqueue for the virtio device + * @vdev: the real virtio device underneath + * @legacy: is it a legacy device? + * @device: virtio device ID + * @vendor: virtio vendor ID + * @features: negotiated supported features + * @feature_table: an array of feature supported by the driver + * @feature_table_size: number of entries in the feature table array + * @feature_table_legacy: same as feature_table but working in legacy mode + * @feature_table_size_legacy: number of entries in feature table legacy array + */ +struct virtio_dev_priv { + struct list_head vqs; + struct udevice *vdev; + bool legacy; + u32 device; + u32 vendor; + u64 features; + const u32 *feature_table; + u32 feature_table_size; + const u32 *feature_table_legacy; + u32 feature_table_size_legacy; +}; + +/** + * virtio_get_config() - read the value of a configuration field + * + * @vdev: the real virtio device + * @offset: the offset of the configuration field + * @buf: the buffer to write the field value into + * @len: the length of the buffer + * @return 0 if OK, -ve on error + */ +int virtio_get_config(struct udevice *vdev, unsigned int offset, + void *buf, unsigned int len); + +/** + * virtio_set_config() - write the value of a configuration field + * + * @vdev: the real virtio device + * @offset: the offset of the configuration field + * @buf: the buffer to read the field value from + * @len: the length of the buffer + * @return 0 if OK, -ve on error + */ +int virtio_set_config(struct udevice *vdev, unsigned int offset, + void *buf, unsigned int len); + +/** + * virtio_generation() - config generation counter + * + * @vdev: the real virtio device + * @counter: the returned config generation counter + * @return 0 if OK, -ve on error + */ +int virtio_generation(struct udevice *vdev, u32 *counter); + +/** + * virtio_get_status() - read the status byte + * + * @vdev: the real virtio device + * @status: the returned status byte + * @return 0 if OK, -ve on error + */ +int virtio_get_status(struct udevice *vdev, u8 *status); + +/** + * virtio_set_status() - write the status byte + * + * @vdev: the real virtio device + * @status: the new status byte + * @return 0 if OK, -ve on error + */ +int virtio_set_status(struct udevice *vdev, u8 status); + +/** + * virtio_reset() - reset the device + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ +int virtio_reset(struct udevice *vdev); + +/** + * virtio_get_features() - get the array of feature bits for this device + * + * @vdev: the real virtio device + * @features: the first 32 feature bits (all we currently need) + * @return 0 if OK, -ve on error + */ +int virtio_get_features(struct udevice *vdev, u64 *features); + +/** + * virtio_set_features() - confirm what device features we'll be using + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ +int virtio_set_features(struct udevice *vdev); + +/** + * virtio_find_vqs() - find virtqueues and instantiate them + * + * @vdev: the real virtio device + * @nvqs: the number of virtqueues to find + * @vqs: on success, includes new virtqueues + * @return 0 if OK, -ve on error + */ +int virtio_find_vqs(struct udevice *vdev, unsigned int nvqs, + struct virtqueue *vqs[]); + +/** + * virtio_del_vqs() - free virtqueues found by find_vqs() + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ +int virtio_del_vqs(struct udevice *vdev); + +/** + * virtio_notify() - notify the device to process the queue + * + * @vdev: the real virtio device + * @vq: virtqueue to process + * @return 0 if OK, -ve on error + */ +int virtio_notify(struct udevice *vdev, struct virtqueue *vq); + +/** + * virtio_add_status() - helper to set a new status code to the device + * + * @vdev: the real virtio device + * @status: new status code to be added + */ +void virtio_add_status(struct udevice *vdev, u8 status); + +/** + * virtio_finalize_features() - helper to finalize features + * + * @vdev: the real virtio device + * @return 0 if OK, -ve on error + */ +int virtio_finalize_features(struct udevice *vdev); + +/** + * virtio_driver_features_init() - initialize driver supported features + * + * This fills in the virtio device parent per child private data with the given + * information, which contains driver supported features and legacy features. + * + * This API should be called in the virtio device driver's bind method, so that + * later virtio transport uclass driver can utilize the driver supplied features + * to negotiate with the device on the final supported features. + * + * @priv: virtio uclass per device private data + * @feature: an array of feature supported by the driver + * @feature_size: number of entries in the feature table array + * @feature_legacy: same as feature_table but working in legacy mode + * @feature_legacy_size:number of entries in feature table legacy array + */ +void virtio_driver_features_init(struct virtio_dev_priv *priv, + const u32 *feature, + u32 feature_size, + const u32 *feature_legacy, + u32 feature_legacy_size); + +/** + * virtio_init() - helper to enumerate all known virtio devices + * + * @return 0 if OK, -ve on error + */ +int virtio_init(void); + +static inline u16 __virtio16_to_cpu(bool little_endian, __virtio16 val) +{ + if (little_endian) + return le16_to_cpu((__force __le16)val); + else + return be16_to_cpu((__force __be16)val); +} + +static inline __virtio16 __cpu_to_virtio16(bool little_endian, u16 val) +{ + if (little_endian) + return (__force __virtio16)cpu_to_le16(val); + else + return (__force __virtio16)cpu_to_be16(val); +} + +static inline u32 __virtio32_to_cpu(bool little_endian, __virtio32 val) +{ + if (little_endian) + return le32_to_cpu((__force __le32)val); + else + return be32_to_cpu((__force __be32)val); +} + +static inline __virtio32 __cpu_to_virtio32(bool little_endian, u32 val) +{ + if (little_endian) + return (__force __virtio32)cpu_to_le32(val); + else + return (__force __virtio32)cpu_to_be32(val); +} + +static inline u64 __virtio64_to_cpu(bool little_endian, __virtio64 val) +{ + if (little_endian) + return le64_to_cpu((__force __le64)val); + else + return be64_to_cpu((__force __be64)val); +} + +static inline __virtio64 __cpu_to_virtio64(bool little_endian, u64 val) +{ + if (little_endian) + return (__force __virtio64)cpu_to_le64(val); + else + return (__force __virtio64)cpu_to_be64(val); +} + +/** + * __virtio_test_bit - helper to test feature bits + * + * For use by transports. Devices should normally use virtio_has_feature, + * which includes more checks. + * + * @udev: the transport device + * @fbit: the feature bit + */ +static inline bool __virtio_test_bit(struct udevice *udev, unsigned int fbit) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* Did you forget to fix assumptions on max features? */ + if (__builtin_constant_p(fbit)) + BUILD_BUG_ON(fbit >= 64); + else + WARN_ON(fbit >= 64); + + return uc_priv->features & BIT_ULL(fbit); +} + +/** + * __virtio_set_bit - helper to set feature bits + * + * For use by transports. + * + * @udev: the transport device + * @fbit: the feature bit + */ +static inline void __virtio_set_bit(struct udevice *udev, unsigned int fbit) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* Did you forget to fix assumptions on max features? */ + if (__builtin_constant_p(fbit)) + BUILD_BUG_ON(fbit >= 64); + else + WARN_ON(fbit >= 64); + + uc_priv->features |= BIT_ULL(fbit); +} + +/** + * __virtio_clear_bit - helper to clear feature bits + * + * For use by transports. + * + * @vdev: the transport device + * @fbit: the feature bit + */ +static inline void __virtio_clear_bit(struct udevice *udev, unsigned int fbit) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); + + /* Did you forget to fix assumptions on max features? */ + if (__builtin_constant_p(fbit)) + BUILD_BUG_ON(fbit >= 64); + else + WARN_ON(fbit >= 64); + + uc_priv->features &= ~BIT_ULL(fbit); +} + +/** + * virtio_has_feature - helper to determine if this device has this feature + * + * Note this API is only usable after the virtio device driver's bind phase, + * as the feature has been negotiated between the device and the driver. + * + * @vdev: the virtio device + * @fbit: the feature bit + */ +static inline bool virtio_has_feature(struct udevice *vdev, unsigned int fbit) +{ + if (!(vdev->flags & DM_FLAG_BOUND)) + WARN_ON(true); + + return __virtio_test_bit(vdev->parent, fbit); +} + +static inline bool virtio_legacy_is_little_endian(void) +{ +#ifdef __LITTLE_ENDIAN + return true; +#else + return false; +#endif +} + +static inline bool virtio_is_little_endian(struct udevice *vdev) +{ + struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(vdev->parent); + + return !uc_priv->legacy || virtio_legacy_is_little_endian(); +} + +/* Memory accessors */ +static inline u16 virtio16_to_cpu(struct udevice *vdev, __virtio16 val) +{ + return __virtio16_to_cpu(virtio_is_little_endian(vdev), val); +} + +static inline __virtio16 cpu_to_virtio16(struct udevice *vdev, u16 val) +{ + return __cpu_to_virtio16(virtio_is_little_endian(vdev), val); +} + +static inline u32 virtio32_to_cpu(struct udevice *vdev, __virtio32 val) +{ + return __virtio32_to_cpu(virtio_is_little_endian(vdev), val); +} + +static inline __virtio32 cpu_to_virtio32(struct udevice *vdev, u32 val) +{ + return __cpu_to_virtio32(virtio_is_little_endian(vdev), val); +} + +static inline u64 virtio64_to_cpu(struct udevice *vdev, __virtio64 val) +{ + return __virtio64_to_cpu(virtio_is_little_endian(vdev), val); +} + +static inline __virtio64 cpu_to_virtio64(struct udevice *vdev, u64 val) +{ + return __cpu_to_virtio64(virtio_is_little_endian(vdev), val); +} + +/* Read @count fields, @bytes each */ +static inline void __virtio_cread_many(struct udevice *vdev, + unsigned int offset, + void *buf, size_t count, size_t bytes) +{ + u32 old, gen; + int i; + + /* no need to check return value as generation can be optional */ + virtio_generation(vdev, &gen); + do { + old = gen; + + for (i = 0; i < count; i++) + virtio_get_config(vdev, offset + bytes * i, + buf + i * bytes, bytes); + + virtio_generation(vdev, &gen); + } while (gen != old); +} + +static inline void virtio_cread_bytes(struct udevice *vdev, + unsigned int offset, + void *buf, size_t len) +{ + __virtio_cread_many(vdev, offset, buf, len, 1); +} + +static inline u8 virtio_cread8(struct udevice *vdev, unsigned int offset) +{ + u8 ret; + + virtio_get_config(vdev, offset, &ret, sizeof(ret)); + return ret; +} + +static inline void virtio_cwrite8(struct udevice *vdev, + unsigned int offset, u8 val) +{ + virtio_set_config(vdev, offset, &val, sizeof(val)); +} + +static inline u16 virtio_cread16(struct udevice *vdev, + unsigned int offset) +{ + u16 ret; + + virtio_get_config(vdev, offset, &ret, sizeof(ret)); + return virtio16_to_cpu(vdev, (__force __virtio16)ret); +} + +static inline void virtio_cwrite16(struct udevice *vdev, + unsigned int offset, u16 val) +{ + val = (__force u16)cpu_to_virtio16(vdev, val); + virtio_set_config(vdev, offset, &val, sizeof(val)); +} + +static inline u32 virtio_cread32(struct udevice *vdev, + unsigned int offset) +{ + u32 ret; + + virtio_get_config(vdev, offset, &ret, sizeof(ret)); + return virtio32_to_cpu(vdev, (__force __virtio32)ret); +} + +static inline void virtio_cwrite32(struct udevice *vdev, + unsigned int offset, u32 val) +{ + val = (__force u32)cpu_to_virtio32(vdev, val); + virtio_set_config(vdev, offset, &val, sizeof(val)); +} + +static inline u64 virtio_cread64(struct udevice *vdev, + unsigned int offset) +{ + u64 ret; + + __virtio_cread_many(vdev, offset, &ret, 1, sizeof(ret)); + return virtio64_to_cpu(vdev, (__force __virtio64)ret); +} + +static inline void virtio_cwrite64(struct udevice *vdev, + unsigned int offset, u64 val) +{ + val = (__force u64)cpu_to_virtio64(vdev, val); + virtio_set_config(vdev, offset, &val, sizeof(val)); +} + +/* Config space read accessor */ +#define virtio_cread(vdev, structname, member, ptr) \ + do { \ + /* Must match the member's type, and be integer */ \ + if (!typecheck(typeof((((structname *)0)->member)), *(ptr))) \ + (*ptr) = 1; \ + \ + switch (sizeof(*ptr)) { \ + case 1: \ + *(ptr) = virtio_cread8(vdev, \ + offsetof(structname, member)); \ + break; \ + case 2: \ + *(ptr) = virtio_cread16(vdev, \ + offsetof(structname, member)); \ + break; \ + case 4: \ + *(ptr) = virtio_cread32(vdev, \ + offsetof(structname, member)); \ + break; \ + case 8: \ + *(ptr) = virtio_cread64(vdev, \ + offsetof(structname, member)); \ + break; \ + default: \ + WARN_ON(true); \ + } \ + } while (0) + +/* Config space write accessor */ +#define virtio_cwrite(vdev, structname, member, ptr) \ + do { \ + /* Must match the member's type, and be integer */ \ + if (!typecheck(typeof((((structname *)0)->member)), *(ptr))) \ + WARN_ON((*ptr) == 1); \ + \ + switch (sizeof(*ptr)) { \ + case 1: \ + virtio_cwrite8(vdev, \ + offsetof(structname, member), \ + *(ptr)); \ + break; \ + case 2: \ + virtio_cwrite16(vdev, \ + offsetof(structname, member), \ + *(ptr)); \ + break; \ + case 4: \ + virtio_cwrite32(vdev, \ + offsetof(structname, member), \ + *(ptr)); \ + break; \ + case 8: \ + virtio_cwrite64(vdev, \ + offsetof(structname, member), \ + *(ptr)); \ + break; \ + default: \ + WARN_ON(true); \ + } \ + } while (0) + +/* Conditional config space accessors */ +#define virtio_cread_feature(vdev, fbit, structname, member, ptr) \ + ({ \ + int _r = 0; \ + if (!virtio_has_feature(vdev, fbit)) \ + _r = -ENOENT; \ + else \ + virtio_cread(vdev, structname, member, ptr); \ + _r; \ + }) + +#endif /* __VIRTIO_H__ */ diff --git a/include/virtio_ring.h b/include/virtio_ring.h new file mode 100644 index 0000000000..6fc0593b14 --- /dev/null +++ b/include/virtio_ring.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_ring.h + */ + +#ifndef _LINUX_VIRTIO_RING_H +#define _LINUX_VIRTIO_RING_H + +#include + +/* This marks a buffer as continuing via the next field */ +#define VRING_DESC_F_NEXT 1 +/* This marks a buffer as write-only (otherwise read-only) */ +#define VRING_DESC_F_WRITE 2 +/* This means the buffer contains a list of buffer descriptors */ +#define VRING_DESC_F_INDIRECT 4 + +/* + * The Host uses this in used->flags to advise the Guest: don't kick me when + * you add a buffer. It's unreliable, so it's simply an optimization. Guest + * will still kick if it's out of buffers. + */ +#define VRING_USED_F_NO_NOTIFY 1 + +/* + * The Guest uses this in avail->flags to advise the Host: don't interrupt me + * when you consume a buffer. It's unreliable, so it's simply an optimization. + */ +#define VRING_AVAIL_F_NO_INTERRUPT 1 + +/* We support indirect buffer descriptors */ +#define VIRTIO_RING_F_INDIRECT_DESC 28 + +/* + * The Guest publishes the used index for which it expects an interrupt + * at the end of the avail ring. Host should ignore the avail->flags field. + * + * The Host publishes the avail index for which it expects a kick + * at the end of the used ring. Guest should ignore the used->flags field. + */ +#define VIRTIO_RING_F_EVENT_IDX 29 + +/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */ +struct vring_desc { + /* Address (guest-physical) */ + __virtio64 addr; + /* Length */ + __virtio32 len; + /* The flags as indicated above */ + __virtio16 flags; + /* We chain unused descriptors via this, too */ + __virtio16 next; +}; + +struct vring_avail { + __virtio16 flags; + __virtio16 idx; + __virtio16 ring[]; +}; + +struct vring_used_elem { + /* Index of start of used descriptor chain */ + __virtio32 id; + /* Total length of the descriptor chain which was used (written to) */ + __virtio32 len; +}; + +struct vring_used { + __virtio16 flags; + __virtio16 idx; + struct vring_used_elem ring[]; +}; + +struct vring { + unsigned int num; + struct vring_desc *desc; + struct vring_avail *avail; + struct vring_used *used; +}; + +/** + * virtqueue - a queue to register buffers for sending or receiving. + * + * @list: the chain of virtqueues for this device + * @vdev: the virtio device this queue was created for + * @index: the zero-based ordinal number for this queue + * @num_free: number of elements we expect to be able to fit + * @vring: actual memory layout for this queue + * @event: host publishes avail event idx + * @free_head: head of free buffer list + * @num_added: number we've added since last sync + * @last_used_idx: last used index we've seen + * @avail_flags_shadow: last written value to avail->flags + * @avail_idx_shadow: last written value to avail->idx in guest byte order + */ +struct virtqueue { + struct list_head list; + struct udevice *vdev; + unsigned int index; + unsigned int num_free; + struct vring vring; + bool event; + unsigned int free_head; + unsigned int num_added; + u16 last_used_idx; + u16 avail_flags_shadow; + u16 avail_idx_shadow; +}; + +/* + * Alignment requirements for vring elements. + * When using pre-virtio 1.0 layout, these fall out naturally. + */ +#define VRING_AVAIL_ALIGN_SIZE 2 +#define VRING_USED_ALIGN_SIZE 4 +#define VRING_DESC_ALIGN_SIZE 16 + +/* + * We publish the used event index at the end of the available ring, + * and vice versa. They are at the end for backwards compatibility. + */ +#define vring_used_event(vr) ((vr)->avail->ring[(vr)->num]) +#define vring_avail_event(vr) (*(__virtio16 *)&(vr)->used->ring[(vr)->num]) + +static inline void vring_init(struct vring *vr, unsigned int num, void *p, + unsigned long align) +{ + vr->num = num; + vr->desc = p; + vr->avail = p + num * sizeof(struct vring_desc); + vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] + + sizeof(__virtio16) + align - 1) & ~(align - 1)); +} + +static inline unsigned int vring_size(unsigned int num, unsigned long align) +{ + return ((sizeof(struct vring_desc) * num + + sizeof(__virtio16) * (3 + num) + align - 1) & ~(align - 1)) + + sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num; +} + +/* + * The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX. + * Assuming a given event_idx value from the other side, if we have just + * incremented index from old to new_idx, should we trigger an event? + */ +static inline int vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old) +{ + /* + * Note: Xen has similar logic for notification hold-off + * in include/xen/interface/io/ring.h with req_event and req_prod + * corresponding to event_idx + 1 and new_idx respectively. + * Note also that req_event and req_prod in Xen start at 1, + * event indexes in virtio start at 0. + */ + return (__u16)(new_idx - event_idx - 1) < (__u16)(new_idx - old); +} + +struct virtio_sg; + +/** + * virtqueue_add - expose buffers to other end + * + * @vq: the struct virtqueue we're talking about + * @sgs: array of terminated scatterlists + * @out_sgs: the number of scatterlists readable by other side + * @in_sgs: the number of scatterlists which are writable + * (after readable ones) + * + * Caller must ensure we don't call this with other virtqueue operations + * at the same time (except where noted). + * + * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO). + */ +int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[], + unsigned int out_sgs, unsigned int in_sgs); + +/** + * virtqueue_kick - update after add_buf + * + * @vq: the struct virtqueue + * + * After one or more virtqueue_add() calls, invoke this to kick + * the other side. + * + * Caller must ensure we don't call this with other virtqueue + * operations at the same time (except where noted). + */ +void virtqueue_kick(struct virtqueue *vq); + +/** + * virtqueue_get_buf - get the next used buffer + * + * @vq: the struct virtqueue we're talking about + * @len: the length written into the buffer + * + * If the device wrote data into the buffer, @len will be set to the + * amount written. This means you don't need to clear the buffer + * beforehand to ensure there's no data leakage in the case of short + * writes. + * + * Caller must ensure we don't call this with other virtqueue + * operations at the same time (except where noted). + * + * Returns NULL if there are no used buffers, or the memory buffer + * handed to virtqueue_add_*(). + */ +void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len); + +/** + * vring_create_virtqueue - create a virtqueue for a virtio device + * + * @index: the index of the queue + * @num: number of elements of the queue + * @vring_align:the alignment requirement of the descriptor ring + * @udev: the virtio transport udevice + * @return: the virtqueue pointer or NULL if failed + * + * This creates a virtqueue and allocates the descriptor ring for a virtio + * device. The caller should query virtqueue_get_ring_size() to learn the + * actual size of the ring. + * + * This API is supposed to be called by the virtio transport driver in the + * virtio find_vqs() uclass method. + */ +struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, + unsigned int vring_align, + struct udevice *udev); + +/** + * vring_del_virtqueue - destroy a virtqueue + * + * @vq: the struct virtqueue we're talking about + * + * This destroys a virtqueue. If created with vring_create_virtqueue(), + * this also frees the descriptor ring. + * + * This API is supposed to be called by the virtio transport driver in the + * virtio del_vqs() uclass method. + */ +void vring_del_virtqueue(struct virtqueue *vq); + +/** + * virtqueue_get_vring_size - get the size of the virtqueue's vring + * + * @vq: the struct virtqueue containing the vring of interest + * @return: the size of the vring in a virtqueue. + */ +unsigned int virtqueue_get_vring_size(struct virtqueue *vq); + +/** + * virtqueue_get_desc_addr - get the vring descriptor table address + * + * @vq: the struct virtqueue containing the vring of interest + * @return: the descriptor table address of the vring in a virtqueue. + */ +ulong virtqueue_get_desc_addr(struct virtqueue *vq); + +/** + * virtqueue_get_avail_addr - get the vring available ring address + * + * @vq: the struct virtqueue containing the vring of interest + * @return: the available ring address of the vring in a virtqueue. + */ +ulong virtqueue_get_avail_addr(struct virtqueue *vq); + +/** + * virtqueue_get_used_addr - get the vring used ring address + * + * @vq: the struct virtqueue containing the vring of interest + * @return: the used ring address of the vring in a virtqueue. + */ +ulong virtqueue_get_used_addr(struct virtqueue *vq); + +/** + * virtqueue_poll - query pending used buffers + * + * @vq: the struct virtqueue we're talking about + * @last_used_idx: virtqueue last used index + * + * Returns "true" if there are pending used buffers in the queue. + */ +bool virtqueue_poll(struct virtqueue *vq, u16 last_used_idx); + +/** + * virtqueue_dump - dump the virtqueue for debugging + * + * @vq: the struct virtqueue we're talking about + * + * Caller must ensure we don't call this with other virtqueue operations + * at the same time (except where noted). + */ +void virtqueue_dump(struct virtqueue *vq); + +/* + * Barriers in virtio are tricky. Since we are not in a hyperviosr/guest + * scenario, having these as nops is enough to work as expected. + */ + +static inline void virtio_mb(void) +{ +} + +static inline void virtio_rmb(void) +{ +} + +static inline void virtio_wmb(void) +{ +} + +static inline void virtio_store_mb(__virtio16 *p, __virtio16 v) +{ + WRITE_ONCE(*p, v); +} + +#endif /* _LINUX_VIRTIO_RING_H */ diff --git a/include/virtio_types.h b/include/virtio_types.h new file mode 100644 index 0000000000..d700d1936d --- /dev/null +++ b/include/virtio_types.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2018, Tuomas Tynkkynen + * Copyright (C) 2018, Bin Meng + * + * From Linux kernel include/uapi/linux/virtio_types.h + */ + +#ifndef _LINUX_VIRTIO_TYPES_H +#define _LINUX_VIRTIO_TYPES_H + +#include + +/* + * __virtio{16,32,64} have the following meaning: + * - __u{16,32,64} for virtio devices in legacy mode, accessed in native endian + * - __le{16,32,64} for standard-compliant virtio devices + */ + +typedef __u16 __bitwise __virtio16; +typedef __u32 __bitwise __virtio32; +typedef __u64 __bitwise __virtio64; + +#endif /* _LINUX_VIRTIO_TYPES_H */ diff --git a/include/vxworks.h b/include/vxworks.h index 60c0efaf6e..1a29509460 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -83,6 +83,5 @@ struct efi_gop_info { int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); void boot_prep_vxworks(bootm_headers_t *images); void boot_jump_vxworks(bootm_headers_t *images); -void do_bootvx_fdt(bootm_headers_t *images); #endif diff --git a/include/w1.h b/include/w1.h index 399177a12e..b958b1c92c 100644 --- a/include/w1.h +++ b/include/w1.h @@ -12,6 +12,7 @@ #define W1_FAMILY_DS24B33 0x23 #define W1_FAMILY_DS2431 0x2d +#define W1_FAMILY_DS2502 0x09 #define W1_FAMILY_EEP_SANDBOX 0xfe struct w1_device { diff --git a/lib/Kconfig b/lib/Kconfig index ccab426e12..0333ab172f 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -21,6 +21,12 @@ config DYNAMIC_CRC_TABLE Enable this option to calculate entries for CRC tables at runtime. This can be helpful when reducing the size of the build image +config HAVE_ARCH_IOMAP + bool + help + Enable this option if architecture provides io{read,write}{8,16,32} + I/O accessor functions. + config HAVE_PRIVATE_LIBGCC bool @@ -295,6 +301,14 @@ config LZO help This enables support for LZO compression algorithm.r +config SPL_LZ4 + bool "Enable LZ4 decompression support in SPL" + help + This enables support for tge LZ4 decompression algorithm in SPL. LZ4 + is a lossless data compression algorithm that is focused on + fast compression and decompression speed. It belongs to the LZ77 + family of byte-oriented compression schemes. + config SPL_LZO bool "Enable LZO decompression support in SPL" help diff --git a/lib/Makefile b/lib/Makefile index fb6944128a..a6dd928a92 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -8,7 +8,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI_LOADER) += efi_driver/ obj-$(CONFIG_EFI_LOADER) += efi_loader/ -obj-$(CONFIG_EFI_LOADER) += efi_selftest/ +obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_BZIP2) += bzip2/ obj-$(CONFIG_TIZEN) += tizen/ @@ -38,7 +38,6 @@ obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o obj-y += initcall.o obj-$(CONFIG_LMB) += lmb.o obj-y += ldiv.o -obj-$(CONFIG_LZ4) += lz4_wrapper.o obj-$(CONFIG_MD5) += md5.o obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o @@ -64,6 +63,7 @@ obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o obj-$(CONFIG_$(SPL_)LZO) += lzo/ +obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o obj-$(CONFIG_LIBAVB) += libavb/ @@ -76,6 +76,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o endif obj-$(CONFIG_ADDR_MAP) += addr_map.o diff --git a/lib/crc16.c b/lib/crc16.c index 763ae33f34..f46ba727c9 100644 --- a/lib/crc16.c +++ b/lib/crc16.c @@ -22,7 +22,12 @@ *========================================================================== */ -#include "crc.h" +#ifdef USE_HOSTCC +#include +#else +#include +#endif +#include /* Table of CRC constants - implements x^16+x^12+x^5+1 */ static const uint16_t crc16_tab[] = { @@ -60,14 +65,20 @@ static const uint16_t crc16_tab[] = { 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, }; -uint16_t crc16_ccitt(uint16_t crc_start, unsigned char *buf, int len) +uint16_t crc16_ccitt(uint16_t cksum, const unsigned char *buf, int len) { - int i; - uint16_t cksum; - - cksum = crc_start; - for (i = 0; i < len; i++) + for (int i = 0; i < len; i++) cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xff] ^ (cksum << 8); return cksum; } + +void crc16_ccitt_wd_buf(const uint8_t *in, uint len, + uint8_t *out, uint chunk_sz) +{ + uint16_t crc; + + crc = crc16_ccitt(0, in, len); + crc = htons(crc); + memcpy(out, &crc, sizeof(crc)); +} diff --git a/lib/crc32.c b/lib/crc32.c index 71e27df78e..eee21f8d73 100644 --- a/lib/crc32.c +++ b/lib/crc32.c @@ -65,7 +65,8 @@ static void __efi_runtime make_crc_table(void) int n, k; uLong poly; /* polynomial exclusive-or pattern */ /* terms of polynomial defining this crc (except x^32): */ - static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + static Byte __efi_runtime_data p[] = { + 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26}; /* make exclusive-or pattern from polynomial (0xedb88320L) */ poly = 0L; diff --git a/lib/efi/efi.c b/lib/efi/efi.c index c6639f96cc..2c6a50824f 100644 --- a/lib/efi/efi.c +++ b/lib/efi/efi.c @@ -69,7 +69,7 @@ int efi_init(struct efi_priv *priv, const char *banner, efi_handle_t image, efi_putc(priv, ' '); ret = boot->open_protocol(priv->parent_image, &loaded_image_guid, - (void **)&loaded_image, &priv->parent_image, + (void **)&loaded_image, priv->parent_image, NULL, EFI_OPEN_PROTOCOL_GET_PROTOCOL); if (ret) { efi_puts(priv, "Failed to get loaded image protocol\n"); diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index 5879d40386..0047998ee0 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -161,5 +161,4 @@ U_BOOT_DRIVER(efi_sysreset) = { .id = UCLASS_SYSRESET, .of_match = efi_sysreset_ids, .ops = &efi_sysreset_ops, - .flags = DM_FLAG_PRE_RELOC, }; diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index 5b9c139f38..3f147cf608 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -38,7 +38,7 @@ * handle handle of the controller on which this driver is installed * io block io protocol proxied by this driver */ -struct efi_blk_priv { +struct efi_blk_platdata { efi_handle_t handle; struct efi_block_io *io; }; @@ -55,8 +55,8 @@ struct efi_blk_priv { static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) { - struct efi_blk_priv *priv = dev->priv; - struct efi_block_io *io = priv->io; + struct efi_blk_platdata *platdata = dev_get_platdata(dev); + struct efi_block_io *io = platdata->io; efi_status_t ret; EFI_PRINT("%s: read '%s', from block " LBAFU ", " LBAFU " blocks\n", @@ -84,8 +84,8 @@ static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, const void *buffer) { - struct efi_blk_priv *priv = dev->priv; - struct efi_block_io *io = priv->io; + struct efi_blk_platdata *platdata = dev_get_platdata(dev); + struct efi_block_io *io = platdata->io; efi_status_t ret; EFI_PRINT("%s: write '%s', from block " LBAFU ", " LBAFU " blocks\n", @@ -135,7 +135,7 @@ static int efi_bl_bind(efi_handle_t handle, void *interface) struct efi_object *obj = efi_search_obj(handle); struct efi_block_io *io = interface; int disks; - struct efi_blk_priv *priv; + struct efi_blk_platdata *platdata; EFI_PRINT("%s: handle %p, interface %p\n", __func__, handle, io); @@ -163,18 +163,16 @@ static int efi_bl_bind(efi_handle_t handle, void *interface) return -ENOENT; /* Set the DM_FLAG_NAME_ALLOCED flag to avoid a memory leak */ device_set_name_alloced(bdev); - /* Allocate priv */ + + platdata = dev_get_platdata(bdev); + platdata->handle = handle; + platdata->io = interface; + ret = device_probe(bdev); if (ret) return ret; EFI_PRINT("%s: block device '%s' created\n", __func__, bdev->name); - priv = bdev->priv; - priv->handle = handle; - priv->io = interface; - - ret = blk_prepare_device(bdev); - /* Create handles for the partions of the block device */ disks = efi_bl_bind_partitions(handle, bdev); EFI_PRINT("Found %d partitions\n", disks); @@ -193,7 +191,7 @@ U_BOOT_DRIVER(efi_blk) = { .name = "efi_blk", .id = UCLASS_BLK, .ops = &efi_blk_ops, - .priv_auto_alloc_size = sizeof(struct efi_blk_priv), + .platdata_auto_alloc_size = sizeof(struct efi_blk_platdata), }; /* EFI driver operators */ diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 0c5764db12..a095df3f54 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * EFI utils + * EFI boot manager * * Copyright (c) 2017 Rob Clark */ @@ -9,6 +9,7 @@ #include #include #include +#include static const struct efi_boot_services *bs; static const struct efi_runtime_services *rs; @@ -30,42 +31,68 @@ static const struct efi_runtime_services *rs; */ -/* - * See section 3.1.3 in the v2.7 UEFI spec for more details on - * the layout of EFI_LOAD_OPTION. In short it is: - * - * typedef struct _EFI_LOAD_OPTION { - * UINT32 Attributes; - * UINT16 FilePathListLength; - * // CHAR16 Description[]; <-- variable length, NULL terminated - * // EFI_DEVICE_PATH_PROTOCOL FilePathList[]; <-- FilePathListLength bytes - * // UINT8 OptionalData[]; - * } EFI_LOAD_OPTION; - */ -struct load_option { - u32 attributes; - u16 file_path_length; - u16 *label; - struct efi_device_path *file_path; - u8 *optional_data; -}; - -/* parse an EFI_LOAD_OPTION, as described above */ -static void parse_load_option(struct load_option *lo, void *ptr) +/* Parse serialized data and transform it into efi_load_option structure */ +void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data) { - lo->attributes = *(u32 *)ptr; - ptr += sizeof(u32); + lo->attributes = get_unaligned_le32(data); + data += sizeof(u32); - lo->file_path_length = *(u16 *)ptr; - ptr += sizeof(u16); + lo->file_path_length = get_unaligned_le16(data); + data += sizeof(u16); - lo->label = ptr; - ptr += (u16_strlen(lo->label) + 1) * 2; + /* FIXME */ + lo->label = (u16 *)data; + data += (u16_strlen(lo->label) + 1) * sizeof(u16); - lo->file_path = ptr; - ptr += lo->file_path_length; + /* FIXME */ + lo->file_path = (struct efi_device_path *)data; + data += lo->file_path_length; - lo->optional_data = ptr; + lo->optional_data = data; +} + +/* + * Serialize efi_load_option structure into byte stream for BootXXXX. + * Return a size of allocated data. + */ +unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data) +{ + unsigned long label_len, option_len; + unsigned long size; + u8 *p; + + label_len = (u16_strlen(lo->label) + 1) * sizeof(u16); + option_len = strlen((char *)lo->optional_data); + + /* total size */ + size = sizeof(lo->attributes); + size += sizeof(lo->file_path_length); + size += label_len; + size += lo->file_path_length; + size += option_len + 1; + p = malloc(size); + if (!p) + return 0; + + /* copy data */ + *data = p; + memcpy(p, &lo->attributes, sizeof(lo->attributes)); + p += sizeof(lo->attributes); + + memcpy(p, &lo->file_path_length, sizeof(lo->file_path_length)); + p += sizeof(lo->file_path_length); + + memcpy(p, lo->label, label_len); + p += label_len; + + memcpy(p, lo->file_path, lo->file_path_length); + p += lo->file_path_length; + + memcpy(p, lo->optional_data, option_len); + p += option_len; + *(char *)p = '\0'; + + return size; } /* free() the result */ @@ -100,7 +127,7 @@ static void *get_var(u16 *name, const efi_guid_t *vendor, static void *try_load_entry(uint16_t n, struct efi_device_path **device_path, struct efi_device_path **file_path) { - struct load_option lo; + struct efi_load_option lo; u16 varname[] = L"Boot0000"; u16 hexmap[] = L"0123456789ABCDEF"; void *load_option, *image = NULL; @@ -115,7 +142,7 @@ static void *try_load_entry(uint16_t n, struct efi_device_path **device_path, if (!load_option) return NULL; - parse_load_option(&lo, load_option); + efi_deserialize_load_option(&lo, load_option); if (lo.attributes & LOAD_OPTION_ACTIVE) { efi_status_t ret; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index da978d2b34..cc9efbb0cb 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -26,6 +26,14 @@ LIST_HEAD(efi_obj_list); /* List of all events */ LIST_HEAD(efi_events); +/* + * If we're running on nasty systems (32bit ARM booting into non-EFI Linux) + * we need to do trickery with caches. Since we don't want to break the EFI + * aware boot path, only apply hacks when loading exiting directly (breaking + * direct Linux EFI booting along the way - oh well). + */ +static bool efi_is_direct_boot = true; + #ifdef CONFIG_ARM /* * The "gd" pointer lives in a register on ARM and AArch64 that we declare @@ -416,13 +424,12 @@ static efi_status_t EFIAPI efi_free_pool_ext(void *buffer) * * The protocols list is initialized. The object handle is set. */ -void efi_add_handle(struct efi_object *obj) +void efi_add_handle(efi_handle_t handle) { - if (!obj) + if (!handle) return; - INIT_LIST_HEAD(&obj->protocols); - obj->handle = obj; - list_add_tail(&obj->link, &efi_obj_list); + INIT_LIST_HEAD(&handle->protocols); + list_add_tail(&handle->link, &efi_obj_list); } /** @@ -440,7 +447,7 @@ efi_status_t efi_create_handle(efi_handle_t *handle) return EFI_OUT_OF_RESOURCES; efi_add_handle(obj); - *handle = obj->handle; + *handle = obj; return EFI_SUCCESS; } @@ -536,13 +543,13 @@ efi_status_t efi_remove_all_protocols(const efi_handle_t handle) * * @obj: handle to delete */ -void efi_delete_handle(struct efi_object *obj) +void efi_delete_handle(efi_handle_t handle) { - if (!obj) + if (!handle) return; - efi_remove_all_protocols(obj->handle); - list_del(&obj->link); - free(obj); + efi_remove_all_protocols(handle); + list_del(&handle->link); + free(handle); } /** @@ -927,7 +934,7 @@ struct efi_object *efi_search_obj(const efi_handle_t handle) struct efi_object *efiobj; list_for_each_entry(efiobj, &efi_obj_list, link) { - if (efiobj->handle == handle) + if (efiobj == handle) return efiobj; } @@ -1019,7 +1026,7 @@ efi_status_t efi_add_protocol(const efi_handle_t handle, * Return: status code */ static efi_status_t EFIAPI efi_install_protocol_interface( - void **handle, const efi_guid_t *protocol, + efi_handle_t *handle, const efi_guid_t *protocol, int protocol_interface_type, void *protocol_interface) { efi_status_t r; @@ -1052,7 +1059,7 @@ out: /** * efi_get_drivers() - get all drivers associated to a controller - * @efiobj: handle of the controller + * @handle: handle of the controller * @protocol: protocol GUID (optional) * @number_of_drivers: number of child controllers * @driver_handle_buffer: handles of the the drivers @@ -1061,7 +1068,7 @@ out: * * Return: status code */ -static efi_status_t efi_get_drivers(struct efi_object *efiobj, +static efi_status_t efi_get_drivers(efi_handle_t handle, const efi_guid_t *protocol, efi_uintn_t *number_of_drivers, efi_handle_t **driver_handle_buffer) @@ -1072,7 +1079,7 @@ static efi_status_t efi_get_drivers(struct efi_object *efiobj, bool duplicate; /* Count all driver associations */ - list_for_each_entry(handler, &efiobj->protocols, link) { + list_for_each_entry(handler, &handle->protocols, link) { if (protocol && guidcmp(handler->guid, protocol)) continue; list_for_each_entry(item, &handler->open_infos, link) { @@ -1090,7 +1097,7 @@ static efi_status_t efi_get_drivers(struct efi_object *efiobj, if (!*driver_handle_buffer) return EFI_OUT_OF_RESOURCES; /* Collect unique driver handles */ - list_for_each_entry(handler, &efiobj->protocols, link) { + list_for_each_entry(handler, &handle->protocols, link) { if (protocol && guidcmp(handler->guid, protocol)) continue; list_for_each_entry(item, &handler->open_infos, link) { @@ -1117,7 +1124,7 @@ static efi_status_t efi_get_drivers(struct efi_object *efiobj, /** * efi_disconnect_all_drivers() - disconnect all drivers from a controller - * @efiobj: handle of the controller + * @handle: handle of the controller * @protocol: protocol GUID (optional) * @child_handle: handle of the child to destroy * @@ -1128,16 +1135,16 @@ static efi_status_t efi_get_drivers(struct efi_object *efiobj, * * Return: status code */ -static efi_status_t efi_disconnect_all_drivers( - struct efi_object *efiobj, - const efi_guid_t *protocol, - efi_handle_t child_handle) +static efi_status_t efi_disconnect_all_drivers + (efi_handle_t handle, + const efi_guid_t *protocol, + efi_handle_t child_handle) { efi_uintn_t number_of_drivers; efi_handle_t *driver_handle_buffer; efi_status_t r, ret; - ret = efi_get_drivers(efiobj, protocol, &number_of_drivers, + ret = efi_get_drivers(handle, protocol, &number_of_drivers, &driver_handle_buffer); if (ret != EFI_SUCCESS) return ret; @@ -1145,7 +1152,7 @@ static efi_status_t efi_disconnect_all_drivers( ret = EFI_NOT_FOUND; while (number_of_drivers) { r = EFI_CALL(efi_disconnect_controller( - efiobj->handle, + handle, driver_handle_buffer[--number_of_drivers], child_handle)); if (r == EFI_SUCCESS) @@ -1156,21 +1163,19 @@ static efi_status_t efi_disconnect_all_drivers( } /** - * efi_uninstall_protocol_interface() - uninstall protocol interface + * efi_uninstall_protocol() - uninstall protocol interface + * * @handle: handle from which the protocol shall be removed * @protocol: GUID of the protocol to be removed * @protocol_interface: interface to be removed * - * This function implements the UninstallProtocolInterface service. - * - * See the Unified Extensible Firmware Interface (UEFI) specification for - * details. + * This function DOES NOT delete a handle without installed protocol. * * Return: status code */ -static efi_status_t EFIAPI efi_uninstall_protocol_interface( - efi_handle_t handle, const efi_guid_t *protocol, - void *protocol_interface) +static efi_status_t efi_uninstall_protocol + (efi_handle_t handle, const efi_guid_t *protocol, + void *protocol_interface) { struct efi_object *efiobj; struct efi_handler *handler; @@ -1178,8 +1183,6 @@ static efi_status_t EFIAPI efi_uninstall_protocol_interface( struct efi_open_protocol_info_item *pos; efi_status_t r; - EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface); - /* Check handle */ efiobj = efi_search_obj(handle); if (!efiobj) { @@ -1210,7 +1213,41 @@ static efi_status_t EFIAPI efi_uninstall_protocol_interface( } r = efi_remove_protocol(handle, protocol, protocol_interface); out: - return EFI_EXIT(r); + return r; +} + +/** + * efi_uninstall_protocol_interface() - uninstall protocol interface + * @handle: handle from which the protocol shall be removed + * @protocol: GUID of the protocol to be removed + * @protocol_interface: interface to be removed + * + * This function implements the UninstallProtocolInterface service. + * + * See the Unified Extensible Firmware Interface (UEFI) specification for + * details. + * + * Return: status code + */ +static efi_status_t EFIAPI efi_uninstall_protocol_interface + (efi_handle_t handle, const efi_guid_t *protocol, + void *protocol_interface) +{ + efi_status_t ret; + + EFI_ENTRY("%p, %pUl, %p", handle, protocol, protocol_interface); + + ret = efi_uninstall_protocol(handle, protocol, protocol_interface); + if (ret != EFI_SUCCESS) + goto out; + + /* If the last protocol has been removed, delete the handle. */ + if (list_empty(&handle->protocols)) { + list_del(&handle->link); + free(handle); + } +out: + return EFI_EXIT(ret); } /** @@ -1240,7 +1277,7 @@ static efi_status_t EFIAPI efi_register_protocol_notify( * @search_type: selection criterion * @protocol: GUID of the protocol * @search_key: registration key - * @efiobj: handle + * @handle: handle * * See the documentation of the LocateHandle service in the UEFI specification. * @@ -1248,7 +1285,7 @@ static efi_status_t EFIAPI efi_register_protocol_notify( */ static int efi_search(enum efi_locate_search_type search_type, const efi_guid_t *protocol, void *search_key, - struct efi_object *efiobj) + efi_handle_t handle) { efi_status_t ret; @@ -1259,7 +1296,7 @@ static int efi_search(enum efi_locate_search_type search_type, /* TODO: RegisterProtocolNotify is not implemented yet */ return -1; case BY_PROTOCOL: - ret = efi_search_protocol(efiobj->handle, protocol, NULL); + ret = efi_search_protocol(handle, protocol, NULL); return (ret != EFI_SUCCESS); default: /* Invalid search type */ @@ -1331,7 +1368,7 @@ static efi_status_t efi_locate_handle( /* Then fill the array */ list_for_each_entry(efiobj, &efi_obj_list, link) { if (!efi_search(search_type, protocol, search_key, efiobj)) - *buffer++ = efiobj->handle; + *buffer++ = efiobj; } return EFI_SUCCESS; @@ -1489,7 +1526,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, } /* Add internal object to object list */ - efi_add_handle(&obj->parent); + efi_add_handle(&obj->header); if (info_ptr) *info_ptr = info; @@ -1506,7 +1543,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, * When asking for the device path interface, return * bootefi_device_path */ - ret = efi_add_protocol(obj->parent.handle, + ret = efi_add_protocol(&obj->header, &efi_guid_device_path, device_path); if (ret != EFI_SUCCESS) goto failure; @@ -1516,7 +1553,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, * When asking for the loaded_image interface, just * return handle which points to loaded_image_info */ - ret = efi_add_protocol(obj->parent.handle, + ret = efi_add_protocol(&obj->header, &efi_guid_loaded_image, info); if (ret != EFI_SUCCESS) goto failure; @@ -1678,6 +1715,8 @@ static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data); + efi_is_direct_boot = false; + /* call the image! */ if (setjmp(&image_obj->exit_jmp)) { /* @@ -1785,6 +1824,21 @@ static efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle) return EFI_EXIT(EFI_SUCCESS); } +/** + * efi_exit_caches() - fix up caches for EFI payloads if necessary + */ +static void efi_exit_caches(void) +{ +#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) + /* + * Grub on 32bit ARM needs to have caches disabled before jumping into + * a zImage, but does not know of all cache layers. Give it a hand. + */ + if (efi_is_direct_boot) + cleanup_before_linux(); +#endif +} + /** * efi_exit_boot_services() - stop all boot services * @image_handle: handle of the loaded image @@ -1838,6 +1892,9 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, board_quiesce_devices(); + /* Fix up caches for EFI payloads if necessary */ + efi_exit_caches(); + /* This stops all lingering devices */ bootm_disable_interrupts(); @@ -2176,7 +2233,7 @@ static efi_status_t EFIAPI efi_locate_protocol(const efi_guid_t *protocol, efiobj = list_entry(lhandle, struct efi_object, link); - ret = efi_search_protocol(efiobj->handle, protocol, &handler); + ret = efi_search_protocol(efiobj, protocol, &handler); if (ret == EFI_SUCCESS) { *protocol_interface = handler->protocol_interface; return EFI_EXIT(EFI_SUCCESS); @@ -2279,8 +2336,8 @@ out: * * Return: status code */ -static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces( - void **handle, ...) +static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces + (efi_handle_t *handle, ...) { EFI_ENTRY("%p", handle); @@ -2316,7 +2373,7 @@ static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces( for (; i; --i) { protocol = efi_va_arg(argptr, efi_guid_t*); protocol_interface = efi_va_arg(argptr, void*); - EFI_CALL(efi_uninstall_protocol_interface(handle, protocol, + EFI_CALL(efi_uninstall_protocol_interface(*handle, protocol, protocol_interface)); } efi_va_end(argptr); @@ -2339,7 +2396,7 @@ static efi_status_t EFIAPI efi_install_multiple_protocol_interfaces( * Return: status code */ static efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces( - void *handle, ...) + efi_handle_t handle, ...) { EFI_ENTRY("%p", handle); @@ -2358,16 +2415,21 @@ static efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces( if (!protocol) break; protocol_interface = efi_va_arg(argptr, void*); - r = EFI_CALL(efi_uninstall_protocol_interface( - handle, protocol, - protocol_interface)); + r = efi_uninstall_protocol(handle, protocol, + protocol_interface); if (r != EFI_SUCCESS) break; i++; } efi_va_end(argptr); - if (r == EFI_SUCCESS) + if (r == EFI_SUCCESS) { + /* If the last protocol has been removed, delete the handle. */ + if (list_empty(&handle->protocols)) { + list_del(&handle->link); + free(handle); + } return EFI_EXIT(r); + } /* If an error occurred undo all changes. */ efi_va_start(argptr, handle); @@ -2380,7 +2442,8 @@ static efi_status_t EFIAPI efi_uninstall_multiple_protocol_interfaces( } efi_va_end(argptr); - return EFI_EXIT(r); + /* In case of an error always return EFI_INVALID_PARAMETER */ + return EFI_EXIT(EFI_INVALID_PARAMETER); } /** @@ -2553,10 +2616,10 @@ out: * * Return: status code */ -static efi_status_t EFIAPI efi_open_protocol( - void *handle, const efi_guid_t *protocol, - void **protocol_interface, void *agent_handle, - void *controller_handle, uint32_t attributes) +static efi_status_t EFIAPI efi_open_protocol + (efi_handle_t handle, const efi_guid_t *protocol, + void **protocol_interface, efi_handle_t agent_handle, + efi_handle_t controller_handle, uint32_t attributes) { struct efi_handler *handler; efi_status_t r = EFI_INVALID_PARAMETER; @@ -2828,13 +2891,19 @@ static efi_status_t EFIAPI efi_reinstall_protocol_interface( EFI_ENTRY("%p, %pUl, %p, %p", handle, protocol, old_interface, new_interface); - ret = EFI_CALL(efi_uninstall_protocol_interface(handle, protocol, - old_interface)); + + /* Uninstall protocol but do not delete handle */ + ret = efi_uninstall_protocol(handle, protocol, old_interface); if (ret != EFI_SUCCESS) goto out; - ret = EFI_CALL(efi_install_protocol_interface(&handle, protocol, - EFI_NATIVE_INTERFACE, - new_interface)); + + /* Install the new protocol */ + ret = efi_add_protocol(handle, protocol, new_interface); + /* + * The UEFI spec does not specify what should happen to the handle + * if in case of an error no protocol interface remains on the handle. + * So let's do nothing here. + */ if (ret != EFI_SUCCESS) goto out; /* diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 0225222a61..66c33a551d 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -205,7 +205,7 @@ static int query_console_serial(int *rows, int *cols) /* * Not all terminals understand CSI [18t for querying the console size. * We should adhere to escape sequences documented in the console_codes - * manpage and the ECMA-48 standard. + * man page and the ECMA-48 standard. * * So here we follow a different approach. We position the cursor to the * bottom right and query its position. Before leaving the function we @@ -480,7 +480,7 @@ void set_shift_mask(int mod, struct efi_key_state *key_state) * * This gets called when we have already parsed CSI. * - * @modifiers: bitmask (shift, alt, ctrl) + * @modifiers: bit mask (shift, alt, ctrl) * @return: the unmodified code */ static int analyze_modifiers(struct efi_key_state *key_state) @@ -1051,34 +1051,34 @@ static void EFIAPI efi_key_notify(struct efi_event *event, void *context) efi_status_t efi_console_register(void) { efi_status_t r; - struct efi_object *efi_console_output_obj; - struct efi_object *efi_console_input_obj; + efi_handle_t console_output_handle; + efi_handle_t console_input_handle; /* Set up mode information */ query_console_size(); /* Create handles */ - r = efi_create_handle((efi_handle_t *)&efi_console_output_obj); + r = efi_create_handle(&console_output_handle); if (r != EFI_SUCCESS) goto out_of_memory; - r = efi_add_protocol(efi_console_output_obj->handle, + r = efi_add_protocol(console_output_handle, &efi_guid_text_output_protocol, &efi_con_out); if (r != EFI_SUCCESS) goto out_of_memory; - systab.con_out_handle = efi_console_output_obj->handle; - systab.stderr_handle = efi_console_output_obj->handle; + systab.con_out_handle = console_output_handle; + systab.stderr_handle = console_output_handle; - r = efi_create_handle((efi_handle_t *)&efi_console_input_obj); + r = efi_create_handle(&console_input_handle); if (r != EFI_SUCCESS) goto out_of_memory; - r = efi_add_protocol(efi_console_input_obj->handle, + r = efi_add_protocol(console_input_handle, &efi_guid_text_input_protocol, &efi_con_in); if (r != EFI_SUCCESS) goto out_of_memory; - systab.con_in_handle = efi_console_input_obj->handle; - r = efi_add_protocol(efi_console_input_obj->handle, + systab.con_in_handle = console_input_handle; + r = efi_add_protocol(console_input_handle, &efi_guid_text_input_ex_protocol, &efi_con_in_ex); if (r != EFI_SUCCESS) goto out_of_memory; diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 46a24f7882..d94982314a 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -82,7 +82,7 @@ struct efi_device_path *efi_dp_next(const struct efi_device_path *dp) /* * Compare two device-paths, stopping when the shorter of the two hits - * an End* node. This is useful to, for example, compare a device-path + * an End* node. This is useful to, for example, compare a device-path * representing a device with one representing a file on the device, or * a device with a parent device. */ @@ -109,16 +109,17 @@ int efi_dp_match(const struct efi_device_path *a, } /* - * See UEFI spec (section 3.1.2, about short-form device-paths.. - * tl;dr: we can have a device-path that starts with a USB WWID - * or USB Class node, and a few other cases which don't encode - * the full device path with bus hierarchy: + * We can have device paths that start with a USB WWID or a USB Class node, + * and a few other cases which don't encode the full device path with bus + * hierarchy: * * - MESSAGING:USB_WWID * - MESSAGING:USB_CLASS * - MEDIA:FILE_PATH * - MEDIA:HARD_DRIVE * - MESSAGING:URI + * + * See UEFI spec (section 3.1.2, about short-form device-paths) */ static struct efi_device_path *shorten_path(struct efi_device_path *dp) { @@ -150,7 +151,7 @@ static struct efi_object *find_obj(struct efi_device_path *dp, bool short_path, struct efi_device_path *obj_dp; efi_status_t ret; - ret = efi_search_protocol(efiobj->handle, + ret = efi_search_protocol(efiobj, &efi_guid_device_path, &handler); if (ret != EFI_SUCCESS) continue; @@ -644,7 +645,7 @@ static unsigned dp_part_size(struct blk_desc *desc, int part) /* * Create a device node for a block device partition. * - * @buf buffer to which the device path is wirtten + * @buf buffer to which the device path is written * @desc block device descriptor * @part partition number, 0 identifies a block device */ @@ -709,7 +710,7 @@ static void *dp_part_node(void *buf, struct blk_desc *desc, int part) /* * Create a device path for a block device or one of its partitions. * - * @buf buffer to which the device path is wirtten + * @buf buffer to which the device path is written * @desc block device descriptor * @part partition number, 0 identifies a block device */ @@ -728,7 +729,7 @@ static void *dp_part_fill(void *buf, struct blk_desc *desc, int part) /* * We *could* make a more accurate path, by looking at if_type * and handling all the different cases like we do for non- - * legacy (ie CONFIG_BLK=y) case. But most important thing + * legacy (i.e. CONFIG_BLK=y) case. But most important thing * is just to have a unique device-path for if_type+devnum. * So map things to a fictitious USB device. */ @@ -752,7 +753,7 @@ static void *dp_part_fill(void *buf, struct blk_desc *desc, int part) return dp_part_node(buf, desc, part); } -/* Construct a device-path from a partition on a blk device: */ +/* Construct a device-path from a partition on a block device: */ struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part) { void *buf, *start; @@ -771,7 +772,7 @@ struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part) /* * Create a device node for a block device partition. * - * @buf buffer to which the device path is wirtten + * @buf buffer to which the device path is written * @desc block device descriptor * @part partition number, 0 identifies a block device */ @@ -791,7 +792,7 @@ struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part) return buf; } -/* convert path to an UEFI style path (ie. DOS style backslashes and utf16) */ +/* convert path to an UEFI style path (i.e. DOS style backslashes and UTF-16) */ static void path_to_uefi(u16 *uefi, const char *path) { while (*path) { @@ -941,3 +942,53 @@ efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path, *file_path = fp; return EFI_SUCCESS; } + +efi_status_t efi_dp_from_name(const char *dev, const char *devnr, + const char *path, + struct efi_device_path **device, + struct efi_device_path **file) +{ + int is_net; + struct blk_desc *desc = NULL; + disk_partition_t fs_partition; + int part = 0; + char filename[32] = { 0 }; /* dp->str is u16[32] long */ + char *s; + + if (path && !file) + return EFI_INVALID_PARAMETER; + + is_net = !strcmp(dev, "Net"); + if (!is_net) { + part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, + 1); + if (part < 0) + return EFI_INVALID_PARAMETER; + + if (device) + *device = efi_dp_from_part(desc, part); + } else { +#ifdef CONFIG_NET + if (device) + *device = efi_dp_from_eth(); +#endif + } + + if (!path) + return EFI_SUCCESS; + + if (!is_net) { + /* Add leading / to fs paths, because they're absolute */ + snprintf(filename, sizeof(filename), "/%s", path); + } else { + snprintf(filename, sizeof(filename), "%s", path); + } + /* DOS style file path: */ + s = filename; + while ((s = strchr(s, '/'))) + *s++ = '\\'; + *file = efi_dp_from_file(((!is_net && device) ? desc : NULL), + part, filename); + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c index 0082236359..e219f84b28 100644 --- a/lib/efi_loader/efi_device_path_to_text.c +++ b/lib/efi_loader/efi_device_path_to_text.c @@ -269,9 +269,9 @@ static char *efi_convert_single_device_node_to_text( * for details. * * device_node device node to be converted - * display_only true if the shorter text represenation shall be used + * display_only true if the shorter text representation shall be used * allow_shortcuts true if shortcut forms may be used - * @return text represenation of the device path + * @return text representation of the device path * NULL if out of memory of device_path is NULL */ static uint16_t EFIAPI *efi_convert_device_node_to_text( @@ -302,9 +302,9 @@ out: * for details. * * device_path device path to be converted - * display_only true if the shorter text represenation shall be used + * display_only true if the shorter text representation shall be used * allow_shortcuts true if shortcut forms may be used - * @return text represenation of the device path + * @return text representation of the device path * NULL if out of memory of device_path is NULL */ static uint16_t EFIAPI *efi_convert_device_path_to_text( diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 13fcc1b471..c037526ad2 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -14,26 +14,30 @@ const efi_guid_t efi_block_io_guid = BLOCK_IO_GUID; +/** + * struct efi_disk_obj - EFI disk object + * + * @header: EFI object header + * @ops: EFI disk I/O protocol interface + * @ifname: interface name for block device + * @dev_index: device index of block device + * @media: block I/O media information + * @dp: device path to the block device + * @part: partition + * @volume: simple file system protocol of the partition + * @offset: offset into disk for simple partition + * @desc: internal block device descriptor + */ struct efi_disk_obj { - /* Generic EFI object parent class data */ - struct efi_object parent; - /* EFI Interface callback struct for block I/O */ + struct efi_object header; struct efi_block_io ops; - /* U-Boot ifname for block device */ const char *ifname; - /* U-Boot dev_index for block device */ int dev_index; - /* EFI Interface Media descriptor struct, referenced by ops */ struct efi_block_io_media media; - /* EFI device path to this block device */ struct efi_device_path *dp; - /* partition # */ unsigned int part; - /* handle to filesys proto (for partition objects) */ struct efi_simple_file_system_protocol *volume; - /* Offset into disk for simple partitions */ lbaint_t offset; - /* Internal block device */ struct blk_desc *desc; }; @@ -246,7 +250,7 @@ static efi_status_t efi_disk_add_dev( return EFI_OUT_OF_RESOURCES; /* Hook up to the device list */ - efi_add_handle(&diskobj->parent); + efi_add_handle(&diskobj->header); /* Fill in object data */ if (part) { @@ -258,18 +262,18 @@ static efi_status_t efi_disk_add_dev( diskobj->dp = efi_dp_from_part(desc, part); } diskobj->part = part; - ret = efi_add_protocol(diskobj->parent.handle, &efi_block_io_guid, + ret = efi_add_protocol(&diskobj->header, &efi_block_io_guid, &diskobj->ops); if (ret != EFI_SUCCESS) return ret; - ret = efi_add_protocol(diskobj->parent.handle, &efi_guid_device_path, + ret = efi_add_protocol(&diskobj->header, &efi_guid_device_path, diskobj->dp); if (ret != EFI_SUCCESS) return ret; if (part >= 1) { diskobj->volume = efi_simple_file_system(desc, part, diskobj->dp); - ret = efi_add_protocol(diskobj->parent.handle, + ret = efi_add_protocol(&diskobj->header, &efi_simple_file_system_protocol_guid, diskobj->volume); if (ret != EFI_SUCCESS) @@ -381,7 +385,7 @@ efi_status_t efi_disk_register(void) /* Partitions show up as block devices in EFI */ disks += efi_disk_create_partitions( - disk->parent.handle, desc, if_typename, + &disk->header, desc, if_typename, desc->devnum, dev->name); } #else @@ -426,9 +430,9 @@ efi_status_t efi_disk_register(void) disks++; /* Partitions show up as block devices in EFI */ - disks += efi_disk_create_partitions( - disk->parent.handle, desc, - if_typename, i, devname); + disks += efi_disk_create_partitions + (&disk->header, desc, + if_typename, i, devname); } } #endif diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index beb4fba917..128cb0a627 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -563,7 +563,7 @@ static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file, if (fh->isdir) info->attribute |= EFI_FILE_DIRECTORY; - ascii2unicode((u16 *)info->file_name, filename); + ascii2unicode(info->file_name, filename); } else if (!guidcmp(info_type, &efi_file_system_info_guid)) { struct efi_file_system_info *info = buffer; disk_partition_t part; diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index a4aa9bcf61..d62ce45912 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -16,15 +16,22 @@ DECLARE_GLOBAL_DATA_PTR; static const efi_guid_t efi_gop_guid = EFI_GOP_GUID; +/** + * struct efi_gop_obj - graphical output protocol object + * + * @header: EFI object header + * @ops: graphical output protocol interface + * @info: graphical output mode information + * @mode: graphical output mode + * @bpix: bits per pixel + * @fb: frame buffer + */ struct efi_gop_obj { - /* Generic EFI object parent class data */ - struct efi_object parent; - /* EFI Interface callback struct for gop */ + struct efi_object header; struct efi_gop ops; - /* The only mode we support */ struct efi_gop_mode_info info; struct efi_gop_mode mode; - /* Fields we only have acces to during init */ + /* Fields we only have access to during init */ u32 bpix; void *fb; }; @@ -236,12 +243,12 @@ static efi_uintn_t gop_get_bpp(struct efi_gop *this) } /* - * Gcc can't optimize our BLT function well, but we need to make sure that + * GCC can't optimize our BLT function well, but we need to make sure that * our 2-dimensional loop gets executed very quickly, otherwise the system * will feel slow. * * By manually putting all obvious branch targets into functions which call - * our generic blt function with constants, the compiler can successfully + * our generic BLT function with constants, the compiler can successfully * optimize for speed. */ static efi_status_t gop_blt_video_fill(struct efi_gop *this, @@ -439,13 +446,13 @@ efi_status_t efi_gop_register(void) } /* Hook up to the device list */ - efi_add_handle(&gopobj->parent); + efi_add_handle(&gopobj->header); /* Fill in object data */ - ret = efi_add_protocol(gopobj->parent.handle, &efi_gop_guid, + ret = efi_add_protocol(&gopobj->header, &efi_gop_guid, &gopobj->ops); if (ret != EFI_SUCCESS) { - printf("ERROR: Failure adding gop protocol\n"); + printf("ERROR: Failure adding GOP protocol\n"); return ret; } gopobj->ops.query_mode = gop_query_mode; @@ -463,7 +470,10 @@ efi_status_t efi_gop_register(void) if (bpix == LCD_COLOR32) #endif { - /* With 32bit color space we can directly expose the fb */ + /* + * With 32bit color space we can directly expose the frame + * buffer + */ gopobj->mode.fb_base = fb_base; gopobj->mode.fb_size = fb_size; } diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 5bd4f4d7fc..4bb517473e 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -294,6 +295,12 @@ static uint64_t efi_find_free_memory(uint64_t len, uint64_t max_addr) { struct list_head *lhandle; + /* + * Prealign input max address, so we simplify our matching + * logic below and can just reuse it as return pointer. + */ + max_addr &= ~EFI_PAGE_MASK; + list_for_each(lhandle, &efi_mem) { struct efi_mem_list *lmem = list_entry(lhandle, struct efi_mem_list, link); @@ -378,7 +385,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type, /* Reserve that map in our memory maps */ ret = efi_add_memory_map(addr, pages, memory_type, true); if (ret == addr) { - *memory = (uintptr_t)map_sysmem(addr, len); + *memory = addr; } else { /* Map would overlap, bail out */ r = EFI_OUT_OF_RESOURCES; @@ -391,7 +398,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type, void *efi_alloc(uint64_t len, int memory_type) { uint64_t ret = 0; - uint64_t pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + uint64_t pages = efi_size_in_pages(len); efi_status_t r; r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, memory_type, pages, @@ -412,12 +419,11 @@ void *efi_alloc(uint64_t len, int memory_type) efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) { uint64_t r = 0; - uint64_t addr = map_to_sysmem((void *)(uintptr_t)memory); - r = efi_add_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY, false); + r = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false); /* Merging of adjacent free regions is missing */ - if (r == addr) + if (r == memory) return EFI_SUCCESS; return EFI_NOT_FOUND; @@ -435,8 +441,8 @@ efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer) { efi_status_t r; struct efi_pool_allocation *alloc; - u64 num_pages = (size + sizeof(struct efi_pool_allocation) + - EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + u64 num_pages = efi_size_in_pages(size + + sizeof(struct efi_pool_allocation)); if (!buffer) return EFI_INVALID_PARAMETER; @@ -545,17 +551,51 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, __weak void efi_add_known_memory(void) { + u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK; int i; + /* Fix for 32bit targets with ram_top at 4G */ + if (!ram_top) + ram_top = 0x100000000ULL; + /* Add RAM */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - u64 ram_start = gd->bd->bi_dram[i].start; - u64 ram_size = gd->bd->bi_dram[i].size; - u64 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; - u64 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + u64 ram_end, ram_start, pages; - efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, - false); + ram_start = (uintptr_t)map_sysmem(gd->bd->bi_dram[i].start, 0); + ram_end = ram_start + gd->bd->bi_dram[i].size; + + /* Remove partial pages */ + ram_end &= ~EFI_PAGE_MASK; + ram_start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + + if (ram_end <= ram_start) { + /* Invalid mapping, keep going. */ + continue; + } + + pages = (ram_end - ram_start) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(ram_start, pages, + EFI_CONVENTIONAL_MEMORY, false); + + /* + * Boards may indicate to the U-Boot memory core that they + * can not support memory above ram_top. Let's honor this + * in the efi_loader subsystem too by declaring any memory + * above ram_top as "already occupied by firmware". + */ + if (ram_top < ram_start) { + /* ram_top is before this region, reserve all */ + efi_add_memory_map(ram_start, pages, + EFI_BOOT_SERVICES_DATA, true); + } else if ((ram_top >= ram_start) && (ram_top < ram_end)) { + /* ram_top is inside this region, reserve parts */ + pages = (ram_end - ram_top) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(ram_top, pages, + EFI_BOOT_SERVICES_DATA, true); + } } } @@ -563,6 +603,7 @@ __weak void efi_add_known_memory(void) static void add_u_boot_and_runtime(void) { unsigned long runtime_start, runtime_end, runtime_pages; + unsigned long runtime_mask = EFI_PAGE_MASK; unsigned long uboot_start, uboot_pages; unsigned long uboot_stack_size = 16 * 1024 * 1024; @@ -571,10 +612,22 @@ static void add_u_boot_and_runtime(void) uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT; efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA, false); - /* Add Runtime Services */ - runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK; +#if defined(__aarch64__) + /* + * Runtime Services must be 64KiB aligned according to the + * "AArch64 Platforms" section in the UEFI spec (2.7+). + */ + + runtime_mask = SZ_64K - 1; +#endif + + /* + * Add Runtime Services. We mark surrounding boottime code as runtime as + * well to fulfill the runtime alignment constraints but avoid padding. + */ + runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask; runtime_end = (ulong)&__efi_runtime_stop; - runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + runtime_end = (runtime_end + runtime_mask) & ~runtime_mask; runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT; efi_add_memory_map(runtime_start, runtime_pages, EFI_RUNTIME_SERVICES_CODE, false); diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 4e8b2d597d..c7d9da8521 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -14,6 +14,8 @@ static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID; static struct efi_pxe_packet *dhcp_ack; static bool new_rx_packet; static void *new_tx_packet; +static void *transmit_buffer; + /* * The notification function of this event is called in every timer cycle * to check if a new network packet has been received. @@ -24,33 +26,85 @@ static struct efi_event *network_timer_event; */ static struct efi_event *wait_for_packet; +/** + * struct efi_net_obj - EFI object representing a network interface + * + * @header: EFI object header + * @net: simple network protocol interface + * @net_mode: status of the network interface + * @pxe: PXE base code protocol interface + * @pxe_mode: status of the PXE base code protocol + */ struct efi_net_obj { - /* Generic EFI object parent class data */ - struct efi_object parent; - /* EFI Interface callback struct for network */ + struct efi_object header; struct efi_simple_network net; struct efi_simple_network_mode net_mode; - /* PXE struct to transmit dhcp data */ struct efi_pxe pxe; struct efi_pxe_mode pxe_mode; }; +/* + * efi_net_start() - start the network interface + * + * This function implements the Start service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * Return: status code + */ static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this) { + efi_status_t ret = EFI_SUCCESS; + EFI_ENTRY("%p", this); - return EFI_EXIT(EFI_SUCCESS); -} + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } -static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this) -{ - EFI_ENTRY("%p", this); - - return EFI_EXIT(EFI_SUCCESS); + if (this->mode->state != EFI_NETWORK_STOPPED) + ret = EFI_ALREADY_STARTED; + else + this->mode->state = EFI_NETWORK_STARTED; +out: + return EFI_EXIT(ret); } /* - * Initialize network adapter and allocate transmit and receive buffers. + * efi_net_stop() - stop the network interface + * + * This function implements the Stop service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * Return: status code + */ +static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this) +{ + efi_status_t ret = EFI_SUCCESS; + + EFI_ENTRY("%p", this); + + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + if (this->mode->state == EFI_NETWORK_STOPPED) + ret = EFI_NOT_STARTED; + else + this->mode->state = EFI_NETWORK_STOPPED; +out: + return EFI_EXIT(ret); +} + +/* + * efi_net_initialize() - initialize the network interface * * This function implements the Initialize service of the * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface @@ -59,7 +113,7 @@ static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this) * @this: pointer to the protocol instance * @extra_rx: extra receive buffer to be allocated * @extra_tx: extra transmit buffer to be allocated - * @return: status code + * Return: status code */ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this, ulong extra_rx, ulong extra_tx) @@ -69,9 +123,10 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this, EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx); + /* Check parameters */ if (!this) { r = EFI_INVALID_PARAMETER; - goto error; + goto out; } /* Setup packet buffers */ @@ -84,32 +139,83 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this, ret = eth_init(); if (ret < 0) { eth_halt(); + this->mode->state = EFI_NETWORK_STOPPED; r = EFI_DEVICE_ERROR; + goto out; + } else { + this->mode->state = EFI_NETWORK_INITIALIZED; } - -error: +out: return EFI_EXIT(r); } +/* + * efi_net_reset() - reinitialize the network interface + * + * This function implements the Reset service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @extended_verification: execute exhaustive verification + * Return: status code + */ static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this, int extended_verification) { EFI_ENTRY("%p, %x", this, extended_verification); - return EFI_EXIT(EFI_SUCCESS); + return EFI_EXIT(EFI_CALL(efi_net_initialize(this, 0, 0))); } +/* + * efi_net_shutdown() - shut down the network interface + * + * This function implements the Shutdown service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * Return: status code + */ static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this) { + efi_status_t ret = EFI_SUCCESS; + EFI_ENTRY("%p", this); - return EFI_EXIT(EFI_SUCCESS); + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + eth_halt(); + this->mode->state = EFI_NETWORK_STOPPED; + +out: + return EFI_EXIT(ret); } -static efi_status_t EFIAPI efi_net_receive_filters( - struct efi_simple_network *this, u32 enable, u32 disable, - int reset_mcast_filter, ulong mcast_filter_count, - struct efi_mac_address *mcast_filter) +/* + * efi_net_receive_filters() - mange multicast receive filters + * + * This function implements the ReceiveFilters service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @enable: bit mask of receive filters to enable + * @disable: bit mask of receive filters to disable + * @reset_mcast_filter: true resets contents of the filters + * @mcast_filter_count: number of hardware MAC addresses in the new filters list + * @mcast_filter: list of new filters + * Return: status code + */ +static efi_status_t EFIAPI efi_net_receive_filters + (struct efi_simple_network *this, u32 enable, u32 disable, + int reset_mcast_filter, ulong mcast_filter_count, + struct efi_mac_address *mcast_filter) { EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable, reset_mcast_filter, mcast_filter_count, mcast_filter); @@ -117,15 +223,40 @@ static efi_status_t EFIAPI efi_net_receive_filters( return EFI_EXIT(EFI_UNSUPPORTED); } -static efi_status_t EFIAPI efi_net_station_address( - struct efi_simple_network *this, int reset, - struct efi_mac_address *new_mac) +/* + * efi_net_station_address() - set the hardware MAC address + * + * This function implements the StationAddress service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @reset: if true reset the address to default + * @new_mac: new MAC address + * Return: status code + */ +static efi_status_t EFIAPI efi_net_station_address + (struct efi_simple_network *this, int reset, + struct efi_mac_address *new_mac) { EFI_ENTRY("%p, %x, %p", this, reset, new_mac); return EFI_EXIT(EFI_UNSUPPORTED); } +/* + * efi_net_statistics() - reset or collect statistics of the network interface + * + * This function implements the Statistics service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @reset: if true, the statistics are reset + * @stat_size: size of the statistics table + * @stat_table: table to receive the statistics + * Return: status code + */ static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this, int reset, ulong *stat_size, void *stat_table) @@ -135,6 +266,19 @@ static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this, return EFI_EXIT(EFI_UNSUPPORTED); } +/* + * efi_net_mcastiptomac() - translate multicast IP address to MAC address + * + * This function implements the Statistics service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @ipv6: true if the IP address is an IPv6 address + * @ip: IP address + * @mac: MAC address + * Return: status code + */ static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this, int ipv6, struct efi_ip_address *ip, @@ -145,6 +289,19 @@ static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this, return EFI_EXIT(EFI_INVALID_PARAMETER); } +/** + * efi_net_nvdata() - read or write NVRAM + * + * This function implements the GetStatus service of the Simple Network + * Protocol. See the UEFI spec for details. + * + * @this: the instance of the Simple Network Protocol + * @readwrite: true for read, false for write + * @offset: offset in NVRAM + * @buffer_size: size of buffer + * @buffer: buffer + * Return: status code + */ static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this, int read_write, ulong offset, ulong buffer_size, char *buffer) @@ -155,13 +312,42 @@ static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this, return EFI_EXIT(EFI_UNSUPPORTED); } +/** + * efi_net_get_status() - get interrupt status + * + * This function implements the GetStatus service of the Simple Network + * Protocol. See the UEFI spec for details. + * + * @this: the instance of the Simple Network Protocol + * @int_status: interface status + * @txbuf: transmission buffer + */ static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this, u32 *int_status, void **txbuf) { + efi_status_t ret = EFI_SUCCESS; + EFI_ENTRY("%p, %p, %p", this, int_status, txbuf); efi_timer_check(); + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + switch (this->mode->state) { + case EFI_NETWORK_STOPPED: + ret = EFI_NOT_STARTED; + goto out; + case EFI_NETWORK_STARTED: + ret = EFI_DEVICE_ERROR; + goto out; + default: + break; + } + if (int_status) { /* We send packets synchronously, so nothing is outstanding */ *int_status = EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT; @@ -172,65 +358,103 @@ static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this, *txbuf = new_tx_packet; new_tx_packet = NULL; - - return EFI_EXIT(EFI_SUCCESS); +out: + return EFI_EXIT(ret); } -static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this, - size_t header_size, size_t buffer_size, void *buffer, - struct efi_mac_address *src_addr, - struct efi_mac_address *dest_addr, u16 *protocol) +/** + * efi_net_transmit() - transmit a packet + * + * This function implements the Transmit service of the Simple Network Protocol. + * See the UEFI spec for details. + * + * @this: the instance of the Simple Network Protocol + * @header_size: size of the media header + * @buffer_size: size of the buffer to receive the packet + * @buffer: buffer to receive the packet + * @src_addr: source hardware MAC address + * @dest_addr: destination hardware MAC address + * @protocol: type of header to build + * Return: status code + */ +static efi_status_t EFIAPI efi_net_transmit + (struct efi_simple_network *this, size_t header_size, + size_t buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol) { + efi_status_t ret = EFI_SUCCESS; + EFI_ENTRY("%p, %lu, %lu, %p, %p, %p, %p", this, (unsigned long)header_size, (unsigned long)buffer_size, buffer, src_addr, dest_addr, protocol); efi_timer_check(); - if (header_size) { - /* We would need to create the header if header_size != 0 */ - return EFI_EXIT(EFI_INVALID_PARAMETER); + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + /* We do not support jumbo packets */ + if (buffer_size > PKTSIZE_ALIGN) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + if (header_size) { + /* + * TODO: We would need to create the header + * if header_size != 0 + */ + ret = EFI_INVALID_PARAMETER; + goto out; + } + + switch (this->mode->state) { + case EFI_NETWORK_STOPPED: + ret = EFI_NOT_STARTED; + goto out; + case EFI_NETWORK_STARTED: + ret = EFI_DEVICE_ERROR; + goto out; + default: + break; } -#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER /* Ethernet packets always fit, just bounce */ - memcpy(efi_bounce_buffer, buffer, buffer_size); - net_send_packet(efi_bounce_buffer, buffer_size); -#else - net_send_packet(buffer, buffer_size); -#endif + memcpy(transmit_buffer, buffer, buffer_size); + net_send_packet(transmit_buffer, buffer_size); new_tx_packet = buffer; - return EFI_EXIT(EFI_SUCCESS); +out: + return EFI_EXIT(ret); } -static void efi_net_push(void *pkt, int len) -{ - new_rx_packet = true; - wait_for_packet->is_signaled = true; -} - -/* - * Receive a packet from a network interface. +/** + * efi_net_receive() - receive a packet from a network interface * * This function implements the Receive service of the Simple Network Protocol. * See the UEFI spec for details. * - * @this the instance of the Simple Network Protocol - * @header_size size of the media header - * @buffer_size size of the buffer to receive the packet - * @buffer buffer to receive the packet - * @src_addr source MAC address - * @dest_addr destination MAC address - * @protocol protocol - * @return status code + * @this: the instance of the Simple Network Protocol + * @header_size: size of the media header + * @buffer_size: size of the buffer to receive the packet + * @buffer: buffer to receive the packet + * @src_addr: source MAC address + * @dest_addr: destination MAC address + * @protocol: protocol + * Return: status code */ -static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this, - size_t *header_size, size_t *buffer_size, void *buffer, - struct efi_mac_address *src_addr, - struct efi_mac_address *dest_addr, u16 *protocol) +static efi_status_t EFIAPI efi_net_receive + (struct efi_simple_network *this, size_t *header_size, + size_t *buffer_size, void *buffer, + struct efi_mac_address *src_addr, + struct efi_mac_address *dest_addr, u16 *protocol) { + efi_status_t ret = EFI_SUCCESS; struct ethernet_hdr *eth_hdr; size_t hdr_size = sizeof(struct ethernet_hdr); u16 protlen; @@ -238,14 +462,35 @@ static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this, EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size, buffer_size, buffer, src_addr, dest_addr, protocol); + /* Execute events */ efi_timer_check(); - if (!new_rx_packet) - return EFI_EXIT(EFI_NOT_READY); + /* Check parameters */ + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + switch (this->mode->state) { + case EFI_NETWORK_STOPPED: + ret = EFI_NOT_STARTED; + goto out; + case EFI_NETWORK_STARTED: + ret = EFI_DEVICE_ERROR; + goto out; + default: + break; + } + + if (!new_rx_packet) { + ret = EFI_NOT_READY; + goto out; + } /* Check that we at least received an Ethernet header */ if (net_rx_packet_len < sizeof(struct ethernet_hdr)) { new_rx_packet = false; - return EFI_EXIT(EFI_NOT_READY); + ret = EFI_NOT_READY; + goto out; } /* Fill export parameters */ eth_hdr = (struct ethernet_hdr *)net_rx_packet; @@ -263,18 +508,24 @@ static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this, if (protocol) *protocol = protlen; if (*buffer_size < net_rx_packet_len) { - /* Packet doesn't fit, try again with bigger buf */ + /* Packet doesn't fit, try again with bigger buffer */ *buffer_size = net_rx_packet_len; - return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + ret = EFI_BUFFER_TOO_SMALL; + goto out; } /* Copy packet */ memcpy(buffer, net_rx_packet, net_rx_packet_len); *buffer_size = net_rx_packet_len; new_rx_packet = false; - - return EFI_EXIT(EFI_SUCCESS); +out: + return EFI_EXIT(ret); } +/** + * efi_net_set_dhcp_ack() - take note of a selected DHCP IP address + * + * This function is called by dhcp_handler(). + */ void efi_net_set_dhcp_ack(void *pkt, int len) { int maxsize = sizeof(*dhcp_ack); @@ -285,8 +536,22 @@ void efi_net_set_dhcp_ack(void *pkt, int len) memcpy(dhcp_ack, pkt, min(len, maxsize)); } -/* - * Check if a new network packet has been received. +/** + * efi_net_push() - callback for received network packet + * + * This function is called when a network packet is received by eth_rx(). + * + * @pkt: network packet + * @len: length + */ +static void efi_net_push(void *pkt, int len) +{ + new_rx_packet = true; + wait_for_packet->is_signaled = true; +} + +/** + * efi_network_timer_notify() - check if a new network packet has been received * * This notification function is called in every timer cycle. * @@ -296,47 +561,65 @@ void efi_net_set_dhcp_ack(void *pkt, int len) static void EFIAPI efi_network_timer_notify(struct efi_event *event, void *context) { + struct efi_simple_network *this = (struct efi_simple_network *)context; + EFI_ENTRY("%p, %p", event, context); + /* + * Some network drivers do not support calling eth_rx() before + * initialization. + */ + if (!this || this->mode->state != EFI_NETWORK_INITIALIZED) + goto out; + if (!new_rx_packet) { push_packet = efi_net_push; eth_rx(); push_packet = NULL; } +out: EFI_EXIT(EFI_SUCCESS); } -/* This gets called from do_bootefi_exec(). */ +/** + * efi_net_register() - register the simple network protocol + * + * This gets called from do_bootefi_exec(). + */ efi_status_t efi_net_register(void) { - struct efi_net_obj *netobj; + struct efi_net_obj *netobj = NULL; efi_status_t r; if (!eth_get_dev()) { - /* No eth device active, don't expose any */ + /* No network device active, don't expose any */ return EFI_SUCCESS; } - /* We only expose the "active" eth device, so one is enough */ + /* We only expose the "active" network device, so one is enough */ netobj = calloc(1, sizeof(*netobj)); - if (!netobj) { - printf("ERROR: Out of memory\n"); - return EFI_OUT_OF_RESOURCES; - } + if (!netobj) + goto out_of_resources; + + /* Allocate an aligned transmit buffer */ + transmit_buffer = calloc(1, PKTSIZE_ALIGN + PKTALIGN); + if (!transmit_buffer) + goto out_of_resources; + transmit_buffer = (void *)ALIGN((uintptr_t)transmit_buffer, PKTALIGN); /* Hook net up to the device list */ - efi_add_handle(&netobj->parent); + efi_add_handle(&netobj->header); /* Fill in object data */ - r = efi_add_protocol(netobj->parent.handle, &efi_net_guid, + r = efi_add_protocol(&netobj->header, &efi_net_guid, &netobj->net); if (r != EFI_SUCCESS) goto failure_to_add_protocol; - r = efi_add_protocol(netobj->parent.handle, &efi_guid_device_path, + r = efi_add_protocol(&netobj->header, &efi_guid_device_path, efi_dp_from_eth()); if (r != EFI_SUCCESS) goto failure_to_add_protocol; - r = efi_add_protocol(netobj->parent.handle, &efi_pxe_guid, + r = efi_add_protocol(&netobj->header, &efi_pxe_guid, &netobj->pxe); if (r != EFI_SUCCESS) goto failure_to_add_protocol; @@ -385,13 +668,13 @@ efi_status_t efi_net_register(void) * iPXE is running at TPL_CALLBACK most of the time. Use a higher TPL. */ r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY, - efi_network_timer_notify, NULL, NULL, + efi_network_timer_notify, &netobj->net, NULL, &network_timer_event); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register network event\n"); return r; } - /* Network is time critical, create event in every timer cyle */ + /* Network is time critical, create event in every timer cycle */ r = efi_set_timer(network_timer_event, EFI_TIMER_PERIODIC, 0); if (r != EFI_SUCCESS) { printf("ERROR: Failed to set network timer\n"); @@ -402,4 +685,9 @@ efi_status_t efi_net_register(void) failure_to_add_protocol: printf("ERROR: Failure to add protocol\n"); return r; +out_of_resources: + free(netobj); + /* free(transmit_buffer) not needed yet */ + printf("ERROR: Out of memory\n"); + return EFI_OUT_OF_RESOURCES; } diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index f059dc97fd..fff93f0960 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -141,7 +141,9 @@ static void EFIAPI efi_reset_system_boottime( do_reset(NULL, 0, 0, NULL); break; case EFI_RESET_SHUTDOWN: - /* We don't have anything to map this to */ +#ifdef CONFIG_CMD_POWEROFF + do_poweroff(NULL, 0, 0, NULL); +#endif break; } @@ -282,7 +284,7 @@ static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = { }, { /* invalidate_*cache_all are gone */ .ptr = &efi_runtime_services.set_virtual_address_map, - .patchto = &efi_invalid_parameter, + .patchto = &efi_unimplemented, }, { /* RTC accessors are gone */ .ptr = &efi_runtime_services.get_time, @@ -378,6 +380,9 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) ulong symidx = rel->info >> SYM_INDEX; extern struct dyn_sym __dyn_sym_start[]; newaddr = __dyn_sym_start[symidx].addr + offset; +#ifdef IS_RELA + newaddr -= CONFIG_SYS_TEXT_BASE; +#endif break; } #endif @@ -431,14 +436,42 @@ static efi_status_t EFIAPI efi_set_virtual_address_map( uint32_t descriptor_version, struct efi_mem_desc *virtmap) { - ulong runtime_start = (ulong)&__efi_runtime_start & - ~(ulong)EFI_PAGE_MASK; int n = memory_map_size / descriptor_size; int i; + int rt_code_sections = 0; EFI_ENTRY("%lx %lx %x %p", memory_map_size, descriptor_size, descriptor_version, virtmap); + /* + * TODO: + * Further down we are cheating. While really we should implement + * SetVirtualAddressMap() events and ConvertPointer() to allow + * dynamically loaded drivers to expose runtime services, we don't + * today. + * + * So let's ensure we see exactly one single runtime section, as + * that is the built-in one. If we see more (or less), someone must + * have tried adding or removing to that which we don't support yet. + * In that case, let's better fail rather than expose broken runtime + * services. + */ + for (i = 0; i < n; i++) { + struct efi_mem_desc *map = (void*)virtmap + + (descriptor_size * i); + + if (map->type == EFI_RUNTIME_SERVICES_CODE) + rt_code_sections++; + } + + if (rt_code_sections != 1) { + /* + * We expose exactly one single runtime code section, so + * something is definitely going wrong. + */ + return EFI_EXIT(EFI_INVALID_PARAMETER); + } + /* Rebind mmio pointers */ for (i = 0; i < n; i++) { struct efi_mem_desc *map = (void*)virtmap + @@ -478,7 +511,7 @@ static efi_status_t EFIAPI efi_set_virtual_address_map( map = (void*)virtmap + (descriptor_size * i); if (map->type == EFI_RUNTIME_SERVICES_CODE) { ulong new_offset = map->virtual_start - - (runtime_start - gd->relocaddr); + map->physical_start + gd->relocaddr; efi_runtime_relocate(new_offset, map); /* Once we're virtual, we can no longer handle @@ -623,8 +656,8 @@ efi_status_t __efi_runtime EFIAPI efi_update_capsule( efi_status_t __efi_runtime EFIAPI efi_query_capsule_caps( struct efi_capsule_header **capsule_header_array, efi_uintn_t capsule_count, - u64 maximum_capsule_size, - u32 reset_type) + u64 *maximum_capsule_size, + u32 *reset_type) { return EFI_UNSUPPORTED; } diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c index 38e42fa243..a81488495e 100644 --- a/lib/efi_loader/efi_smbios.c +++ b/lib/efi_loader/efi_smbios.c @@ -7,6 +7,7 @@ #include #include +#include #include static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID; @@ -19,17 +20,19 @@ static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID; efi_status_t efi_smbios_register(void) { /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */ - u64 dmi = U32_MAX; + u64 dmi_addr = U32_MAX; efi_status_t ret; + void *dmi; /* Reserve 4kiB page for SMBIOS */ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, - EFI_RUNTIME_SERVICES_DATA, 1, &dmi); + EFI_RUNTIME_SERVICES_DATA, 1, &dmi_addr); if (ret != EFI_SUCCESS) { /* Could not find space in lowmem, use highmem instead */ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, - EFI_RUNTIME_SERVICES_DATA, 1, &dmi); + EFI_RUNTIME_SERVICES_DATA, 1, + &dmi_addr); if (ret != EFI_SUCCESS) return ret; @@ -39,11 +42,14 @@ efi_status_t efi_smbios_register(void) * Generate SMBIOS tables - we know that efi_allocate_pages() returns * a 4k-aligned address, so it is safe to assume that * write_smbios_table() will write the table at that address. + * + * Note that on sandbox, efi_allocate_pages() unfortunately returns a + * pointer even though it uses a uint64_t type. Convert it. */ - assert(!(dmi & 0xf)); - write_smbios_table(dmi); + assert(!(dmi_addr & 0xf)); + dmi = (void *)(uintptr_t)dmi_addr; + write_smbios_table(map_to_sysmem(dmi)); /* And expose them to our EFI payload */ - return efi_install_configuration_table(&smbios_guid, - (void *)(uintptr_t)dmi); + return efi_install_configuration_table(&smbios_guid, dmi); } diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c index 3b8de5b4ea..2905479e65 100644 --- a/lib/efi_loader/helloworld.c +++ b/lib/efi_loader/helloworld.c @@ -17,6 +17,16 @@ static const efi_guid_t fdt_guid = EFI_FDT_GUID; static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID; static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID; +/** + * hw_memcmp() - compare memory areas + * + * @buf1: pointer to first area + * @buf2: pointer to second area + * @length: number of bytes to compare + * Return: 0 if both memory areas are the same, otherwise the sign of the + * result value is the same as the sign of ghe difference between + * the first differing pair of bytes taken as u8. + */ static int hw_memcmp(const void *buf1, const void *buf2, size_t length) { const u8 *pos1 = buf1; @@ -31,12 +41,12 @@ static int hw_memcmp(const void *buf1, const void *buf2, size_t length) return 0; } -/* - * Entry point of the EFI application. +/** + * efi_main() - entry point of the EFI application. * - * @handle handle of the loaded image - * @systable system table - * @return status code + * @handle: handle of the loaded image + * @systable: system table + * @return: status code */ efi_status_t EFIAPI efi_main(efi_handle_t handle, struct efi_system_table *systable) @@ -48,7 +58,8 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, efi_uintn_t i; u16 rev[] = L"0.0.0"; - con_out->output_string(con_out, L"Hello, world!\n"); + /* UEFI requires CR LF */ + con_out->output_string(con_out, L"Hello, world!\r\n"); /* Print the revision number */ rev[0] = (systable->hdr.revision >> 16) + '0'; @@ -65,27 +76,30 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, con_out->output_string(con_out, L"Running on UEFI "); con_out->output_string(con_out, rev); - con_out->output_string(con_out, L"\n"); + con_out->output_string(con_out, L"\r\n"); /* Get the loaded image protocol */ ret = boottime->handle_protocol(handle, &loaded_image_guid, (void **)&loaded_image); if (ret != EFI_SUCCESS) { - con_out->output_string(con_out, - L"Cannot open loaded image protocol\n"); + con_out->output_string + (con_out, L"Cannot open loaded image protocol\r\n"); goto out; } /* Find configuration tables */ for (i = 0; i < systable->nr_tables; ++i) { if (!hw_memcmp(&systable->tables[i].guid, &fdt_guid, sizeof(efi_guid_t))) - con_out->output_string(con_out, L"Have device tree\n"); + con_out->output_string + (con_out, L"Have device tree\r\n"); if (!hw_memcmp(&systable->tables[i].guid, &acpi_guid, sizeof(efi_guid_t))) - con_out->output_string(con_out, L"Have ACPI 2.0 table\n"); + con_out->output_string + (con_out, L"Have ACPI 2.0 table\r\n"); if (!hw_memcmp(&systable->tables[i].guid, &smbios_guid, sizeof(efi_guid_t))) - con_out->output_string(con_out, L"Have SMBIOS table\n"); + con_out->output_string + (con_out, L"Have SMBIOS table\r\n"); } /* Output the load options */ con_out->output_string(con_out, L"Load options: "); @@ -94,7 +108,7 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, (u16 *)loaded_image->load_options); else con_out->output_string(con_out, L""); - con_out->output_string(con_out, L"\n"); + con_out->output_string(con_out, L"\r\n"); out: boottime->exit(handle, ret, 0, NULL); diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig index b52696778d..59f9f36801 100644 --- a/lib/efi_selftest/Kconfig +++ b/lib/efi_selftest/Kconfig @@ -1,6 +1,6 @@ config CMD_BOOTEFI_SELFTEST bool "Allow booting an EFI efi_selftest" - depends on CMD_BOOTEFI && !SANDBOX + depends on CMD_BOOTEFI imply FAT imply FAT_WRITE help diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 2f55d9d66f..743b482044 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -10,7 +10,7 @@ CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI) -Os CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding CFLAGS_REMOVE_efi_selftest_miniapp_return.o := $(CFLAGS_NON_EFI) -Os -obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \ +obj-y += \ efi_selftest.o \ efi_selftest_bitblt.o \ efi_selftest_config_table.o \ @@ -21,11 +21,13 @@ efi_selftest_devicepath.o \ efi_selftest_devicepath_util.o \ efi_selftest_events.o \ efi_selftest_event_groups.o \ +efi_selftest_exception.o \ efi_selftest_exitbootservices.o \ efi_selftest_fdt.o \ efi_selftest_gop.o \ efi_selftest_loaded_image.o \ efi_selftest_manageprotocols.o \ +efi_selftest_memory.o \ efi_selftest_rtc.o \ efi_selftest_snp.o \ efi_selftest_textinput.o \ @@ -37,20 +39,16 @@ efi_selftest_util.o \ efi_selftest_variables.o \ efi_selftest_watchdog.o -ifeq ($(CONFIG_CMD_BOOTEFI_SELFTEST),y) obj-$(CONFIG_CPU_V7) += efi_selftest_unaligned.o -endif ifeq ($(CONFIG_BLK)$(CONFIG_PARTITIONS),yy) -obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest_block_device.o +obj-y += efi_selftest_block_device.o endif # TODO: As of v2018.01 the relocation code for the EFI application cannot # be built on x86_64. ifeq ($(CONFIG_X86_64)$(CONFIG_SANDBOX),) -ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST),) - obj-y += \ efi_selftest_startimage_exit.o \ efi_selftest_startimage_return.o @@ -74,5 +72,3 @@ $(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h $(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h endif - -endif diff --git a/lib/efi_selftest/efi_selftest.c b/lib/efi_selftest/efi_selftest.c index dd338db687..5b01610eca 100644 --- a/lib/efi_selftest/efi_selftest.c +++ b/lib/efi_selftest/efi_selftest.c @@ -18,6 +18,7 @@ static const struct efi_boot_services *boottime; static const struct efi_runtime_services *runtime; static efi_handle_t handle; static u16 reset_message[] = L"Selftest completed"; +static int *setup_status; /* * Exit the boot services. @@ -74,20 +75,20 @@ void efi_st_exit_boot_services(void) */ static int setup(struct efi_unit_test *test, unsigned int *failures) { - if (!test->setup) { - test->setup_ok = EFI_ST_SUCCESS; + int ret; + + if (!test->setup) return EFI_ST_SUCCESS; - } efi_st_printc(EFI_LIGHTBLUE, "\nSetting up '%s'\n", test->name); - test->setup_ok = test->setup(handle, systable); - if (test->setup_ok != EFI_ST_SUCCESS) { + ret = test->setup(handle, systable); + if (ret != EFI_ST_SUCCESS) { efi_st_error("Setting up '%s' failed\n", test->name); ++*failures; } else { efi_st_printc(EFI_LIGHTGREEN, "Setting up '%s' succeeded\n", test->name); } - return test->setup_ok; + return ret; } /* @@ -186,18 +187,20 @@ static void list_all_tests(void) void efi_st_do_tests(const u16 *testname, unsigned int phase, unsigned int steps, unsigned int *failures) { + int i = 0; struct efi_unit_test *test; for (test = ll_entry_start(struct efi_unit_test, efi_unit_test); - test < ll_entry_end(struct efi_unit_test, efi_unit_test); ++test) { + test < ll_entry_end(struct efi_unit_test, efi_unit_test); + ++test, ++i) { if (testname ? efi_st_strcmp_16_8(testname, test->name) : test->on_request) continue; if (test->phase != phase) continue; if (steps & EFI_ST_SETUP) - setup(test, failures); - if (steps & EFI_ST_EXECUTE && test->setup_ok == EFI_ST_SUCCESS) + setup_status[i] = setup(test, failures); + if (steps & EFI_ST_EXECUTE && setup_status[i] == EFI_ST_SUCCESS) execute(test, failures); if (steps & EFI_ST_TEARDOWN) teardown(test, failures); @@ -271,6 +274,16 @@ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, ll_entry_count(struct efi_unit_test, efi_unit_test)); + /* Allocate buffer for setup results */ + ret = boottime->allocate_pool(EFI_RUNTIME_SERVICES_DATA, sizeof(int) * + ll_entry_count(struct efi_unit_test, + efi_unit_test), + (void **)&setup_status); + if (ret != EFI_SUCCESS) { + efi_st_error("Allocate pool failed\n"); + return ret; + } + /* Execute boottime tests */ efi_st_do_tests(testname, EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, EFI_ST_SETUP | EFI_ST_EXECUTE | EFI_ST_TEARDOWN, diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c index d4e4fac1c7..f038da9f19 100644 --- a/lib/efi_selftest/efi_selftest_block_device.c +++ b/lib/efi_selftest/efi_selftest_block_device.c @@ -445,11 +445,6 @@ static int execute(void) efi_st_error("Failed to write file\n"); return EFI_ST_FAILURE; } - ret = file->close(file); - if (ret != EFI_SUCCESS) { - efi_st_error("Failed to close file\n"); - return EFI_ST_FAILURE; - } ret = file->getpos(file, &pos); if (ret != EFI_SUCCESS) { efi_st_error("GetPosition failed\n"); @@ -460,6 +455,11 @@ static int execute(void) (unsigned int)pos); return EFI_ST_FAILURE; } + ret = file->close(file); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to close file\n"); + return EFI_ST_FAILURE; + } /* Verify file */ boottime->set_mem(buf, sizeof(buf), 0); diff --git a/lib/efi_selftest/efi_selftest_config_table.c b/lib/efi_selftest/efi_selftest_config_table.c index 2aa3fc7284..0bc5da6b0c 100644 --- a/lib/efi_selftest/efi_selftest_config_table.c +++ b/lib/efi_selftest/efi_selftest_config_table.c @@ -18,7 +18,7 @@ static efi_guid_t table_guid = 0x17, 0x2e, 0x51, 0x6b, 0x49, 0x75); /* - * Notification function, increments the notfication count if parameter + * Notification function, increments the notification count if parameter * context is provided. * * @event notified event @@ -33,23 +33,23 @@ static void EFIAPI notify(struct efi_event *event, void *context) } /* - * Check crc32 of a table. + * Check CRC32 of a table. */ static int check_table(const void *table) { efi_status_t ret; u32 crc32, res; - /* Casting from const to not const */ + /* Casting from constant to not constant */ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table; crc32 = hdr->crc32; /* - * Setting the crc32 of the 'const' table to zero is easier than + * Setting the CRC32 of the 'const' table to zero is easier than * copying */ hdr->crc32 = 0; ret = boottime->calculate_crc32(table, hdr->headersize, &res); - /* Reset table crc32 so it stays constant */ + /* Reset table CRC32 so it stays constant */ hdr->crc32 = crc32; if (ret != EFI_ST_SUCCESS) { efi_st_error("CalculateCrc32 failed\n"); @@ -203,7 +203,7 @@ static int execute(void) return EFI_ST_FAILURE; } if (tabcnt > 1) { - efi_st_error("Duplicate table guid\n"); + efi_st_error("Duplicate table GUID\n"); return EFI_ST_FAILURE; } if (table != &tables[1]) { diff --git a/lib/efi_selftest/efi_selftest_controllers.c b/lib/efi_selftest/efi_selftest_controllers.c index d08c377c72..38720bb63d 100644 --- a/lib/efi_selftest/efi_selftest_controllers.c +++ b/lib/efi_selftest/efi_selftest_controllers.c @@ -33,7 +33,7 @@ static efi_handle_t handle_driver; * Count child controllers * * @handle handle on which child controllers are installed - * @protocol protocol for which the child controlles where installed + * @protocol protocol for which the child controllers were installed * @count number of child controllers * @return status code */ diff --git a/lib/efi_selftest/efi_selftest_crc32.c b/lib/efi_selftest/efi_selftest_crc32.c index 8555b8f114..4881e8ac6f 100644 --- a/lib/efi_selftest/efi_selftest_crc32.c +++ b/lib/efi_selftest/efi_selftest_crc32.c @@ -5,7 +5,7 @@ * Copyright (c) 2018 Heinrich Schuchardt * * This unit test checks the CalculateCrc32 bootservice and checks the - * headers of the system table, the boot services tablle, and the runtime + * headers of the system table, the boot services table, and the runtime * services table before and after ExitBootServices(). */ @@ -19,7 +19,7 @@ static int check_table(const void *table) { efi_status_t ret; u32 crc32, res; - /* Casting from const to not const */ + /* Casting from constant to not constant */ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table; if (!hdr->signature) { diff --git a/lib/efi_selftest/efi_selftest_devicepath.c b/lib/efi_selftest/efi_selftest_devicepath.c index adcf531e90..105ce2c92b 100644 --- a/lib/efi_selftest/efi_selftest_devicepath.c +++ b/lib/efi_selftest/efi_selftest_devicepath.c @@ -257,7 +257,7 @@ static int teardown(void) static int execute(void) { struct efi_device_path *remaining_dp; - void *handle; + efi_handle_t handle; /* * This device path node ends with the letter 't' of 'u-boot'. * The following '.bin' does not belong to the node but is diff --git a/lib/efi_selftest/efi_selftest_event_groups.c b/lib/efi_selftest/efi_selftest_event_groups.c index 9b3c5132ef..5a7980c5d0 100644 --- a/lib/efi_selftest/efi_selftest_event_groups.c +++ b/lib/efi_selftest/efi_selftest_event_groups.c @@ -19,7 +19,7 @@ static efi_guid_t event_group = 0x0e, 0x5b, 0x45, 0xc0, 0x56, 0x91); /* - * Notification function, increments the notfication count if parameter + * Notification function, increments the notification count if parameter * context is provided. * * @event notified event @@ -114,7 +114,7 @@ static int execute(void) (unsigned int)i, (unsigned int)j, (unsigned int)counter[j]); efi_st_error( - "Nofification function not called\n"); + "Notification function not called\n"); return EFI_ST_FAILURE; } } diff --git a/lib/efi_selftest/efi_selftest_events.c b/lib/efi_selftest/efi_selftest_events.c index 47f9f99318..ed99a53804 100644 --- a/lib/efi_selftest/efi_selftest_events.c +++ b/lib/efi_selftest/efi_selftest_events.c @@ -17,7 +17,7 @@ static unsigned int timer_ticks; static struct efi_boot_services *boottime; /* - * Notification function, increments the notfication count if parameter + * Notification function, increments the notification count if parameter * context is provided. * * @event notified event diff --git a/lib/efi_selftest/efi_selftest_exception.c b/lib/efi_selftest/efi_selftest_exception.c new file mode 100644 index 0000000000..76cfb88d7c --- /dev/null +++ b/lib/efi_selftest/efi_selftest_exception.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * efi_selftest_exception + * + * Copyright (c) 2018 Heinrich Schuchardt + * + * Test the handling of exceptions by trying to execute an undefined + * instruction. + */ + +#include + +/** + * undefined_instruction() - try to executed an undefined instruction + */ +static void undefined_instruction(void) +{ +#if defined(CONFIG_ARM) + /* + * 0xe7f...f. is undefined in ARM mode + * 0xde.. is undefined in Thumb mode + */ + asm volatile (".word 0xe7f7defb\n"); +#elif defined(CONFIG_RISCV) + asm volatile (".word 0xffffffff\n"); +#elif defined(CONFIG_X86) + asm volatile (".word 0xffff\n"); +#endif +} + +/** + * execute() - execute unit test + * + * Return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + undefined_instruction(); + + efi_st_error("An undefined instruction exception was not raised\n"); + + return EFI_ST_FAILURE; +} + +EFI_UNIT_TEST(exception) = { + .name = "exception", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .execute = execute, + .on_request = true, +}; diff --git a/lib/efi_selftest/efi_selftest_fdt.c b/lib/efi_selftest/efi_selftest_fdt.c index c7bc242b5c..d545d51812 100644 --- a/lib/efi_selftest/efi_selftest_fdt.c +++ b/lib/efi_selftest/efi_selftest_fdt.c @@ -16,7 +16,7 @@ static struct efi_boot_services *boottime; static const char *fdt; -/* This should be sufficent for */ +/* This should be sufficient for */ #define BUFFERSIZE 0x100000 static efi_guid_t fdt_guid = EFI_FDT_GUID; diff --git a/lib/efi_selftest/efi_selftest_loaded_image.c b/lib/efi_selftest/efi_selftest_loaded_image.c index f9b54ae263..ea2b380a77 100644 --- a/lib/efi_selftest/efi_selftest_loaded_image.c +++ b/lib/efi_selftest/efi_selftest_loaded_image.c @@ -53,7 +53,7 @@ static int execute(void) efi_st_error("ProtocolsPerHandle failed\n"); return EFI_ST_FAILURE; } - if (!protocol_buffer_count | !protocol_buffer) { + if (!protocol_buffer_count || !protocol_buffer) { efi_st_error("ProtocolsPerHandle returned no protocol\n"); return EFI_ST_FAILURE; } diff --git a/lib/efi_selftest/efi_selftest_manageprotocols.c b/lib/efi_selftest/efi_selftest_manageprotocols.c index b09e4cdcfa..0ff35cec8a 100644 --- a/lib/efi_selftest/efi_selftest_manageprotocols.c +++ b/lib/efi_selftest/efi_selftest_manageprotocols.c @@ -189,7 +189,14 @@ static int execute(void) /* * Test error handling in UninstallMultipleProtocols * - * Try to uninstall more protocols than there are installed. + * These are the installed protocol interfaces on handle 2: + * + * guid1 interface4 + * guid2 interface2 + * + * Try to uninstall more protocols than there are installed. This + * should return an error EFI_INVALID_PARAMETER. All deleted protocols + * should be reinstalled. */ ret = boottime->uninstall_multiple_protocol_interfaces( handle2, @@ -197,13 +204,18 @@ static int execute(void) &guid2, &interface2, &guid3, &interface3, NULL); - if (ret == EFI_SUCCESS) { + if (ret != EFI_INVALID_PARAMETER) { + printf("%lx", ret); efi_st_error("UninstallMultipleProtocolInterfaces did not catch error\n"); return EFI_ST_FAILURE; } /* * Test LocateHandleBuffer with ByProtocol + * + * These are the handles with a guid1 protocol interface installed: + * + * handle1, handle2 */ count = buffer_size; ret = boottime->locate_handle_buffer(BY_PROTOCOL, &guid1, NULL, @@ -213,7 +225,7 @@ static int execute(void) return EFI_ST_FAILURE; } if (count != 2) { - efi_st_error("LocateHandleBuffer failed to locate new handles\n"); + efi_st_error("UninstallMultipleProtocolInterfaces deleted handle\n"); return EFI_ST_FAILURE; } ret = find_in_buffer(handle1, count, buffer); diff --git a/lib/efi_selftest/efi_selftest_memory.c b/lib/efi_selftest/efi_selftest_memory.c new file mode 100644 index 0000000000..24b4438ce4 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_memory.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * efi_selftest_memory + * + * Copyright (c) 2018 Heinrich Schuchardt + * + * This unit test checks the following runtime services: + * AllocatePages, FreePages, GetMemoryMap + * + * The memory type used for the device tree is checked. + */ + +#include + +#define EFI_ST_NUM_PAGES 8 + +static const efi_guid_t fdt_guid = EFI_FDT_GUID; +static struct efi_boot_services *boottime; +static u64 fdt_addr; + +/** + * setup() - setup unit test + * + * @handle: handle of the loaded image + * @systable: system table + * Return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + size_t i; + + boottime = systable->boottime; + + for (i = 0; i < systable->nr_tables; ++i) { + if (!efi_st_memcmp(&systable->tables[i].guid, &fdt_guid, + sizeof(efi_guid_t))) { + if (fdt_addr) { + efi_st_error("Duplicate device tree\n"); + return EFI_ST_FAILURE; + } + fdt_addr = (uintptr_t)systable->tables[i].table; + } + } + return EFI_ST_SUCCESS; +} + +/** + * find_in_memory_map() - check matching memory map entry exists + * + * @memory_map: memory map + * @desc_size: number of memory map entries + * @addr: physical address to find in the map + * @type: expected memory type + * Return: EFI_ST_SUCCESS for success + */ +static int find_in_memory_map(efi_uintn_t map_size, + struct efi_mem_desc *memory_map, + efi_uintn_t desc_size, + u64 addr, int memory_type) +{ + efi_uintn_t i; + bool found = false; + + for (i = 0; map_size; ++i, map_size -= desc_size) { + struct efi_mem_desc *entry = &memory_map[i]; + + if (addr >= entry->physical_start && + addr < entry->physical_start + + (entry->num_pages << EFI_PAGE_SHIFT)) { + if (found) { + efi_st_error("Duplicate memory map entry\n"); + return EFI_ST_FAILURE; + } + found = true; + if (memory_type != entry->type) { + efi_st_error + ("Wrong memory type %d, expected %d\n", + entry->type, memory_type); + return EFI_ST_FAILURE; + } + } + } + if (!found) { + efi_st_error("Missing memory map entry\n"); + return EFI_ST_FAILURE; + } + return EFI_ST_SUCCESS; +} + +/* + * execute() - execute unit test + * + * Return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + u64 p1; + u64 p2; + efi_uintn_t map_size = 0; + efi_uintn_t map_key; + efi_uintn_t desc_size; + u32 desc_version; + struct efi_mem_desc *memory_map; + efi_status_t ret; + + /* Allocate two page ranges with different memory type */ + ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES, + EFI_RUNTIME_SERVICES_CODE, + EFI_ST_NUM_PAGES, &p1); + if (ret != EFI_SUCCESS) { + efi_st_error("AllocatePages did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + ret = boottime->allocate_pages(EFI_ALLOCATE_ANY_PAGES, + EFI_RUNTIME_SERVICES_DATA, + EFI_ST_NUM_PAGES, &p2); + if (ret != EFI_SUCCESS) { + efi_st_error("AllocatePages did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + + /* Load memory map */ + ret = boottime->get_memory_map(&map_size, NULL, &map_key, &desc_size, + &desc_version); + if (ret != EFI_BUFFER_TOO_SMALL) { + efi_st_error + ("GetMemoryMap did not return EFI_BUFFER_TOO_SMALL\n"); + return EFI_ST_FAILURE; + } + /* Allocate extra space for newly allocated memory */ + map_size += sizeof(struct efi_mem_desc); + ret = boottime->allocate_pool(EFI_BOOT_SERVICES_DATA, map_size, + (void **)&memory_map); + if (ret != EFI_SUCCESS) { + efi_st_error("AllocatePool did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + ret = boottime->get_memory_map(&map_size, memory_map, &map_key, + &desc_size, &desc_version); + if (ret != EFI_SUCCESS) { + efi_st_error("GetMemoryMap did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + + /* Check memory map entries */ + if (find_in_memory_map(map_size, memory_map, desc_size, p1, + EFI_RUNTIME_SERVICES_CODE) != EFI_ST_SUCCESS) + return EFI_ST_FAILURE; + if (find_in_memory_map(map_size, memory_map, desc_size, p2, + EFI_RUNTIME_SERVICES_DATA) != EFI_ST_SUCCESS) + return EFI_ST_FAILURE; + + /* Free memory */ + ret = boottime->free_pages(p1, EFI_ST_NUM_PAGES); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePages did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pages(p2, EFI_ST_NUM_PAGES); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePages did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(memory_map); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool did not return EFI_SUCCESS\n"); + return EFI_ST_FAILURE; + } + + /* Check memory reservation for the device tree */ + if (fdt_addr && + find_in_memory_map(map_size, memory_map, desc_size, fdt_addr, + EFI_RUNTIME_SERVICES_DATA) != EFI_ST_SUCCESS) { + efi_st_error + ("Device tree not marked as runtime services data\n"); + return EFI_ST_FAILURE; + } + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(memory) = { + .name = "memory", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, +}; diff --git a/lib/efi_selftest/efi_selftest_snp.c b/lib/efi_selftest/efi_selftest_snp.c index 09bd53da82..e10a34ba64 100644 --- a/lib/efi_selftest/efi_selftest_snp.c +++ b/lib/efi_selftest/efi_selftest_snp.c @@ -103,7 +103,7 @@ static efi_status_t send_dhcp_discover(void) struct dhcp p = {}; /* - * Fill ethernet header + * Fill Ethernet header */ boottime->copy_mem(p.eth_hdr.et_dest, (void *)BROADCAST_MAC, ARP_HLEN); boottime->copy_mem(p.eth_hdr.et_src, &net->mode->current_address, @@ -228,6 +228,14 @@ static int setup(const efi_handle_t handle, efi_st_error("WaitForPacket event missing\n"); return EFI_ST_FAILURE; } + /* + * Start network adapter. + */ + ret = net->start(net); + if (ret != EFI_SUCCESS && ret != EFI_ALREADY_STARTED) { + efi_st_error("Failed to start network adapter\n"); + return EFI_ST_FAILURE; + } /* * Initialize network adapter. */ @@ -236,14 +244,6 @@ static int setup(const efi_handle_t handle, efi_st_error("Failed to initialize network adapter\n"); return EFI_ST_FAILURE; } - /* - * Start network adapter. - */ - ret = net->start(net); - if (ret != EFI_SUCCESS) { - efi_st_error("Failed to start network adapter\n"); - return EFI_ST_FAILURE; - } return EFI_ST_SUCCESS; } diff --git a/lib/efi_selftest/efi_selftest_textinput.c b/lib/efi_selftest/efi_selftest_textinput.c index 164fbffe6c..b90671cdd2 100644 --- a/lib/efi_selftest/efi_selftest_textinput.c +++ b/lib/efi_selftest/efi_selftest_textinput.c @@ -5,7 +5,7 @@ * Copyright (c) 2018 Heinrich Schuchardt * * Provides a unit test for the EFI_SIMPLE_TEXT_INPUT_PROTOCOL. - * The unicode character and the scan code are printed for text + * The Unicode character and the scan code are printed for text * input. To run the test: * * setenv efi_selftest text input diff --git a/lib/efi_selftest/efi_selftest_tpl.c b/lib/efi_selftest/efi_selftest_tpl.c index 61ae46b797..97d256abe4 100644 --- a/lib/efi_selftest/efi_selftest_tpl.c +++ b/lib/efi_selftest/efi_selftest_tpl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * efi_selftest_events + * efi_selftest_tpl * * Copyright (c) 2017 Heinrich Schuchardt * diff --git a/lib/efi_selftest/efi_selftest_unicode_collation.c b/lib/efi_selftest/efi_selftest_unicode_collation.c index 9765bd3e44..75294307d9 100644 --- a/lib/efi_selftest/efi_selftest_unicode_collation.c +++ b/lib/efi_selftest/efi_selftest_unicode_collation.c @@ -52,7 +52,7 @@ static int test_stri_coll(void) c1, c2); if (ret) { efi_st_error( - "stri_coll(\"%ps\", \"%ps\") = %zu\n", c1, c2, ret); + "stri_coll(\"%ps\", \"%ps\") = %d\n", c1, c2, (int)ret); return EFI_ST_FAILURE; } @@ -60,7 +60,7 @@ static int test_stri_coll(void) c1, c3); if (ret >= 0) { efi_st_error( - "stri_coll(\"%ps\", \"%ps\") = %zu\n", c1, c3, ret); + "stri_coll(\"%ps\", \"%ps\") = %d\n", c1, c3, (int)ret); return EFI_ST_FAILURE; } @@ -68,7 +68,7 @@ static int test_stri_coll(void) c3, c1); if (ret <= 0) { efi_st_error( - "stri_coll(\"%ps\", \"%ps\") = %zu\n", c3, c1, ret); + "stri_coll(\"%ps\", \"%ps\") = %d\n", c3, c1, (int)ret); return EFI_ST_FAILURE; } diff --git a/lib/efi_selftest/efi_selftest_variables.c b/lib/efi_selftest/efi_selftest_variables.c index 146378fb9a..e4c389a872 100644 --- a/lib/efi_selftest/efi_selftest_variables.c +++ b/lib/efi_selftest/efi_selftest_variables.c @@ -4,10 +4,8 @@ * * Copyright (c) 2018 Heinrich Schuchardt * - * This unit test checks the following protocol services: - * ConnectController, DisconnectController, - * InstallProtocol, ReinstallProtocol, UninstallProtocol, - * OpenProtocol, CloseProtcol, OpenProtocolInformation + * This unit test checks the runtime services for variables: + * GetVariable, GetNextVariableName, SetVariable, QueryVariableInfo. */ #include diff --git a/lib/efi_selftest/efi_selftest_watchdog.c b/lib/efi_selftest/efi_selftest_watchdog.c index bff2330918..cbc6761721 100644 --- a/lib/efi_selftest/efi_selftest_watchdog.c +++ b/lib/efi_selftest/efi_selftest_watchdog.c @@ -35,7 +35,7 @@ static struct notify_context notification_context; static bool watchdog_reset; /* - * Notification function, increments the notfication count if parameter + * Notification function, increments the notification count if parameter * context is provided. * * @event notified event diff --git a/lib/fdtdec.c b/lib/fdtdec.c index a420ba1885..6f8ec0dbed 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -199,7 +200,7 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name) return fdtdec_get_addr_size(blob, node, prop_name, NULL); } -#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI) +#if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI) int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, const char *prop_name, struct fdt_pci_addr *addr) { @@ -1198,7 +1199,8 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp) # else static int uncompress_blob(const void *src, ulong sz_src, void **dstp) { - return -ENOTSUPP; + *dstp = (void *)src; + return 0; } # endif #endif @@ -1252,8 +1254,9 @@ int fdtdec_setup(void) # if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) gd->fdt_blob = (void *)prior_stage_fdt_address; # else - gd->fdt_blob = (void *)env_get_ulong("fdtcontroladdr", 16, - (uintptr_t)gd->fdt_blob); + gd->fdt_blob = map_sysmem + (env_get_ulong("fdtcontroladdr", 16, + (unsigned long)map_to_sysmem(gd->fdt_blob)), 0); # endif # endif @@ -1272,14 +1275,55 @@ int fdtdec_setup(void) * If so, pick the most relevant */ fdt_blob = locate_dtb_in_fit(gd->fdt_blob); - if (fdt_blob) + if (fdt_blob) { + gd->multi_dtb_fit = gd->fdt_blob; gd->fdt_blob = fdt_blob; + } + # endif #endif return fdtdec_prepare_fdt(); } +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) +int fdtdec_resetup(int *rescan) +{ + void *fdt_blob; + + /* + * If the current DTB is part of a compressed FIT image, + * try to locate the best match from the uncompressed + * FIT image stillpresent there. Save the time and space + * required to uncompress it again. + */ + if (gd->multi_dtb_fit) { + fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit); + + if (fdt_blob == gd->fdt_blob) { + /* + * The best match did not change. no need to tear down + * the DM and rescan the fdt. + */ + *rescan = 0; + return 0; + } + + *rescan = 1; + gd->fdt_blob = fdt_blob; + return fdtdec_prepare_fdt(); + } + + /* + * If multi_dtb_fit is NULL, it means that blob appended to u-boot is + * not a FIT image containings DTB, but a single DTB. There is no need + * to teard down DM and rescan the DT in this case. + */ + *rescan = 0; + return 0; +} +#endif + #ifdef CONFIG_NR_DRAM_BANKS int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id, phys_addr_t *basep, phys_size_t *sizep, bd_t *bd) diff --git a/lib/hashtable.c b/lib/hashtable.c index 1c48692b69..93028ed83b 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -662,7 +662,7 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag, return (-1); } } else { - size = totlen; + size = totlen + 1; } /* Check if the user provided a buffer */ diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c index d3b9a60e99..7e9fa9272e 100644 --- a/lib/libfdt/fdt_region.c +++ b/lib/libfdt/fdt_region.c @@ -96,6 +96,9 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, break; case FDT_END_NODE: + /* Depth must never go below -1 */ + if (depth < 0) + return -FDT_ERR_BADSTRUCTURE; include = want; want = stack[depth--]; while (end > path && *--end != '/') diff --git a/lib/physmem.c b/lib/physmem.c index f21ac243ed..84b191dae3 100644 --- a/lib/physmem.c +++ b/lib/physmem.c @@ -9,14 +9,16 @@ */ #include +#include #include #include phys_addr_t __weak arch_phys_memset(phys_addr_t s, int c, phys_size_t n) { - void *s_ptr = (void *)(uintptr_t)s; + void *s_ptr = map_sysmem(s, n); assert(((phys_addr_t)(uintptr_t)s) == s); assert(((phys_addr_t)(uintptr_t)(s + n)) == s + n); + return (phys_addr_t)(uintptr_t)memset(s_ptr, c, n); } diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 05ac67b822..fb5e07b56d 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -387,13 +387,16 @@ static void rsa_engine_remove(ENGINE *e) } } -static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, +static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, + struct checksum_algo *checksum_algo, const struct image_region region[], int region_count, uint8_t **sigp, uint *sig_size) { EVP_PKEY *key; + EVP_PKEY_CTX *ckey; EVP_MD_CTX *context; - int size, ret = 0; + int ret = 0; + size_t size; uint8_t *sig; int i; @@ -409,7 +412,7 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, size = EVP_PKEY_size(key); sig = malloc(size); if (!sig) { - fprintf(stderr, "Out of memory for signature (%d bytes)\n", + fprintf(stderr, "Out of memory for signature (%zu bytes)\n", size); ret = -ENOMEM; goto err_alloc; @@ -421,22 +424,43 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, goto err_create; } EVP_MD_CTX_init(context); - if (!EVP_SignInit(context, checksum_algo->calculate_sign())) { + + ckey = EVP_PKEY_CTX_new(key, NULL); + if (!ckey) { + ret = rsa_err("EVP key context creation failed"); + goto err_create; + } + + if (EVP_DigestSignInit(context, &ckey, + checksum_algo->calculate_sign(), + NULL, key) <= 0) { ret = rsa_err("Signer setup failed"); goto err_sign; } +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT + if (padding_algo && !strcmp(padding_algo->name, "pss")) { + if (EVP_PKEY_CTX_set_rsa_padding(ckey, + RSA_PKCS1_PSS_PADDING) <= 0) { + ret = rsa_err("Signer padding setup failed"); + goto err_sign; + } + } +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ + for (i = 0; i < region_count; i++) { - if (!EVP_SignUpdate(context, region[i].data, region[i].size)) { + if (!EVP_DigestSignUpdate(context, region[i].data, + region[i].size)) { ret = rsa_err("Signing data failed"); goto err_sign; } } - if (!EVP_SignFinal(context, sig, sig_size, key)) { + if (!EVP_DigestSignFinal(context, sig, &size)) { ret = rsa_err("Could not obtain signature"); goto err_sign; } + #if OPENSSL_VERSION_NUMBER < 0x10100000L || \ (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) EVP_MD_CTX_cleanup(context); @@ -446,7 +470,7 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, EVP_MD_CTX_destroy(context); EVP_PKEY_free(key); - debug("Got signature: %d bytes, expected %d\n", *sig_size, size); + debug("Got signature: %d bytes, expected %zu\n", *sig_size, size); *sigp = sig; *sig_size = size; @@ -483,7 +507,7 @@ int rsa_sign(struct image_sign_info *info, ret = rsa_get_priv_key(info->keydir, info->keyname, e, &rsa); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, info->checksum, region, + ret = rsa_sign_with_key(rsa, info->padding, info->checksum, region, region_count, sigp, sig_len); if (ret) goto err_sign; diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index bc83354378..9734f6d3bd 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -57,31 +57,247 @@ static int rsa_verify_padding(const uint8_t *msg, const int pad_len, return ret; } +int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + struct checksum_algo *checksum = info->checksum; + int ret, pad_len = msg_len - checksum->checksum_len; + + /* Check pkcs1.5 padding bytes. */ + ret = rsa_verify_padding(msg, pad_len, checksum); + if (ret) { + debug("In RSAVerify(): Padding check failed!\n"); + return -EINVAL; + } + + /* Check hash. */ + if (memcmp((uint8_t *)msg + pad_len, hash, msg_len - pad_len)) { + debug("In RSAVerify(): Hash check failed!\n"); + return -EACCES; + } + + return 0; +} + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +static void u32_i2osp(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)((val >> 24) & 0xff); + buf[1] = (uint8_t)((val >> 16) & 0xff); + buf[2] = (uint8_t)((val >> 8) & 0xff); + buf[3] = (uint8_t)((val >> 0) & 0xff); +} + +/** + * mask_generation_function1() - generate an octet string + * + * Generate an octet string used to check rsa signature. + * It use an input octet string and a hash function. + * + * @checksum: A Hash function + * @seed: Specifies an input variable octet string + * @seed_len: Size of the input octet string + * @output: Specifies the output octet string + * @output_len: Size of the output octet string + * @return 0 if the octet string was correctly generated, others on error + */ +static int mask_generation_function1(struct checksum_algo *checksum, + uint8_t *seed, int seed_len, + uint8_t *output, int output_len) +{ + struct image_region region[2]; + int ret = 0, i, i_output = 0, region_count = 2; + uint32_t counter = 0; + uint8_t buf_counter[4], *tmp; + int hash_len = checksum->checksum_len; + + memset(output, 0, output_len); + + region[0].data = seed; + region[0].size = seed_len; + region[1].data = &buf_counter[0]; + region[1].size = 4; + + tmp = malloc(hash_len); + if (!tmp) { + debug("%s: can't allocate array tmp\n", __func__); + ret = -ENOMEM; + goto out; + } + + while (i_output < output_len) { + u32_i2osp(counter, &buf_counter[0]); + + ret = checksum->calculate(checksum->name, + region, region_count, + tmp); + if (ret < 0) { + debug("%s: Error in checksum calculation\n", __func__); + goto out; + } + + i = 0; + while ((i_output < output_len) && (i < hash_len)) { + output[i_output] = tmp[i]; + i_output++; + i++; + } + + counter++; + } + +out: + free(tmp); + + return ret; +} + +static int compute_hash_prime(struct checksum_algo *checksum, + uint8_t *pad, int pad_len, + uint8_t *hash, int hash_len, + uint8_t *salt, int salt_len, + uint8_t *hprime) +{ + struct image_region region[3]; + int ret, region_count = 3; + + region[0].data = pad; + region[0].size = pad_len; + region[1].data = hash; + region[1].size = hash_len; + region[2].data = salt; + region[2].size = salt_len; + + ret = checksum->calculate(checksum->name, region, region_count, hprime); + if (ret < 0) { + debug("%s: Error in checksum calculation\n", __func__); + goto out; + } + +out: + return ret; +} + +int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + uint8_t *masked_db = NULL; + int masked_db_len = msg_len - hash_len - 1; + uint8_t *h = NULL, *hprime = NULL; + int h_len = hash_len; + uint8_t *db_mask = NULL; + int db_mask_len = masked_db_len; + uint8_t *db = NULL, *salt = NULL; + int db_len = masked_db_len, salt_len = msg_len - hash_len - 2; + uint8_t pad_zero[8] = { 0 }; + int ret, i, leftmost_bits = 1; + uint8_t leftmost_mask; + struct checksum_algo *checksum = info->checksum; + + /* first, allocate everything */ + masked_db = malloc(masked_db_len); + h = malloc(h_len); + db_mask = malloc(db_mask_len); + db = malloc(db_len); + salt = malloc(salt_len); + hprime = malloc(hash_len); + if (!masked_db || !h || !db_mask || !db || !salt || !hprime) { + printf("%s: can't allocate some buffer\n", __func__); + ret = -ENOMEM; + goto out; + } + + /* step 4: check if the last byte is 0xbc */ + if (msg[msg_len - 1] != 0xbc) { + printf("%s: invalid pss padding (0xbc is missing)\n", __func__); + ret = -EINVAL; + goto out; + } + + /* step 5 */ + memcpy(masked_db, msg, masked_db_len); + memcpy(h, msg + masked_db_len, h_len); + + /* step 6 */ + leftmost_mask = (0xff >> (8 - leftmost_bits)) << (8 - leftmost_bits); + if (masked_db[0] & leftmost_mask) { + printf("%s: invalid pss padding ", __func__); + printf("(leftmost bit of maskedDB not zero)\n"); + ret = -EINVAL; + goto out; + } + + /* step 7 */ + mask_generation_function1(checksum, h, h_len, db_mask, db_mask_len); + + /* step 8 */ + for (i = 0; i < db_len; i++) + db[i] = masked_db[i] ^ db_mask[i]; + + /* step 9 */ + db[0] &= 0xff >> leftmost_bits; + + /* step 10 */ + if (db[0] != 0x01) { + printf("%s: invalid pss padding ", __func__); + printf("(leftmost byte of db isn't 0x01)\n"); + ret = EINVAL; + goto out; + } + + /* step 11 */ + memcpy(salt, &db[1], salt_len); + + /* step 12 & 13 */ + compute_hash_prime(checksum, pad_zero, 8, + (uint8_t *)hash, hash_len, + salt, salt_len, hprime); + + /* step 14 */ + ret = memcmp(h, hprime, hash_len); + +out: + free(hprime); + free(salt); + free(db); + free(db_mask); + free(h); + free(masked_db); + + return ret; +} +#endif + /** * rsa_verify_key() - Verify a signature against some data using RSA Key * * Verify a RSA PKCS1.5 signature against an expected hash using * the RSA Key properties in prop structure. * + * @info: Specifies key and FIT information * @prop: Specifies key * @sig: Signature * @sig_len: Number of bytes in signature * @hash: Pointer to the expected hash * @key_len: Number of bytes in rsa key - * @algo: Checksum algo structure having information on DER encoding etc. * @return 0 if verified, -ve on error */ -static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, +static int rsa_verify_key(struct image_sign_info *info, + struct key_prop *prop, const uint8_t *sig, const uint32_t sig_len, const uint8_t *hash, - const uint32_t key_len, struct checksum_algo *algo) + const uint32_t key_len) { - int pad_len; int ret; #if !defined(USE_HOSTCC) struct udevice *mod_exp_dev; #endif + struct checksum_algo *checksum = info->checksum; + struct padding_algo *padding = info->padding; + int hash_len = checksum->checksum_len; - if (!prop || !sig || !hash || !algo) + if (!prop || !sig || !hash || !checksum) return -EIO; if (sig_len != (prop->num_bits / 8)) { @@ -89,7 +305,7 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return -EINVAL; } - debug("Checksum algorithm: %s", algo->name); + debug("Checksum algorithm: %s", checksum->name); /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { @@ -116,19 +332,10 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return ret; } - pad_len = key_len - algo->checksum_len; - - /* Check pkcs1.5 padding bytes. */ - ret = rsa_verify_padding(buf, pad_len, algo); + ret = padding->verify(info, buf, key_len, hash, hash_len); if (ret) { - debug("In RSAVerify(): Padding check failed!\n"); - return -EINVAL; - } - - /* Check hash. */ - if (memcmp((uint8_t *)buf + pad_len, hash, sig_len - pad_len)) { - debug("In RSAVerify(): Hash check failed!\n"); - return -EACCES; + debug("In RSAVerify(): padding check failed!\n"); + return ret; } return 0; @@ -182,8 +389,8 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, return -EFAULT; } - ret = rsa_verify_key(&prop, sig, sig_len, hash, - info->crypto->key_len, info->checksum); + ret = rsa_verify_key(info, &prop, sig, sig_len, hash, + info->crypto->key_len); return ret; } diff --git a/lib/smbios.c b/lib/smbios.c index 326eb00230..e8ee55c4ae 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -72,9 +73,10 @@ static int smbios_string_table_len(char *start) static int smbios_write_type0(ulong *current, int handle) { - struct smbios_type0 *t = (struct smbios_type0 *)*current; + struct smbios_type0 *t; int len = sizeof(struct smbios_type0); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type0)); fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle); t->vendor = smbios_add_string(t->eos, "U-Boot"); @@ -101,16 +103,18 @@ static int smbios_write_type0(ulong *current, int handle) len = t->length + smbios_string_table_len(t->eos); *current += len; + unmap_sysmem(t); return len; } static int smbios_write_type1(ulong *current, int handle) { - struct smbios_type1 *t = (struct smbios_type1 *)*current; + struct smbios_type1 *t; int len = sizeof(struct smbios_type1); char *serial_str = env_get("serial#"); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type1)); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); @@ -122,15 +126,17 @@ static int smbios_write_type1(ulong *current, int handle) len = t->length + smbios_string_table_len(t->eos); *current += len; + unmap_sysmem(t); return len; } static int smbios_write_type2(ulong *current, int handle) { - struct smbios_type2 *t = (struct smbios_type2 *)*current; + struct smbios_type2 *t; int len = sizeof(struct smbios_type2); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type2)); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); @@ -140,15 +146,17 @@ static int smbios_write_type2(ulong *current, int handle) len = t->length + smbios_string_table_len(t->eos); *current += len; + unmap_sysmem(t); return len; } static int smbios_write_type3(ulong *current, int handle) { - struct smbios_type3 *t = (struct smbios_type3 *)*current; + struct smbios_type3 *t; int len = sizeof(struct smbios_type3); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type3)); fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); @@ -160,6 +168,7 @@ static int smbios_write_type3(ulong *current, int handle) len = t->length + smbios_string_table_len(t->eos); *current += len; + unmap_sysmem(t); return len; } @@ -198,9 +207,10 @@ static void smbios_write_type4_dm(struct smbios_type4 *t) static int smbios_write_type4(ulong *current, int handle) { - struct smbios_type4 *t = (struct smbios_type4 *)*current; + struct smbios_type4 *t; int len = sizeof(struct smbios_type4); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type4)); fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle); t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL; @@ -214,32 +224,37 @@ static int smbios_write_type4(ulong *current, int handle) len = t->length + smbios_string_table_len(t->eos); *current += len; + unmap_sysmem(t); return len; } static int smbios_write_type32(ulong *current, int handle) { - struct smbios_type32 *t = (struct smbios_type32 *)*current; + struct smbios_type32 *t; int len = sizeof(struct smbios_type32); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type32)); fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle); *current += len; + unmap_sysmem(t); return len; } static int smbios_write_type127(ulong *current, int handle) { - struct smbios_type127 *t = (struct smbios_type127 *)*current; + struct smbios_type127 *t; int len = sizeof(struct smbios_type127); + t = map_sysmem(*current, len); memset(t, 0, sizeof(struct smbios_type127)); fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle); *current += len; + unmap_sysmem(t); return len; } @@ -257,6 +272,7 @@ static smbios_write_type smbios_write_funcs[] = { ulong write_smbios_table(ulong addr) { struct smbios_entry *se; + ulong table_addr; ulong tables; int len = 0; int max_struct_size = 0; @@ -268,7 +284,7 @@ ulong write_smbios_table(ulong addr) /* 16 byte align the table address */ addr = ALIGN(addr, 16); - se = (struct smbios_entry *)(uintptr_t)addr; + se = map_sysmem(addr, sizeof(struct smbios_entry)); memset(se, 0, sizeof(struct smbios_entry)); addr += sizeof(struct smbios_entry); @@ -290,7 +306,24 @@ ulong write_smbios_table(ulong addr) se->max_struct_size = max_struct_size; memcpy(se->intermediate_anchor, "_DMI_", 5); se->struct_table_length = len; - se->struct_table_address = tables; + + /* + * We must use a pointer here so things work correctly on sandbox. The + * user of this table is not aware of the mapping of addresses to + * sandbox's DRAM buffer. + */ + table_addr = (ulong)map_sysmem(tables, 0); + if (sizeof(table_addr) > sizeof(u32) && table_addr > (ulong)UINT_MAX) { + /* + * We need to put this >32-bit pointer into the table but the + * field is only 32 bits wide. + */ + printf("WARNING: SMBIOS table_address overflow %llx\n", + (unsigned long long)table_addr); + table_addr = 0; + } + se->struct_table_address = table_addr; + se->struct_count = handle; /* calculate checksums */ @@ -298,6 +331,7 @@ ulong write_smbios_table(ulong addr) isize = sizeof(struct smbios_entry) - SMBIOS_INTERMEDIATE_OFFSET; se->intermediate_checksum = table_compute_checksum(istart, isize); se->checksum = table_compute_checksum(se, sizeof(struct smbios_entry)); + unmap_sysmem(se); return addr; } diff --git a/lib/string.c b/lib/string.c index c4ca944bb4..af17c16f61 100644 --- a/lib/string.c +++ b/lib/string.c @@ -15,6 +15,7 @@ * reentrant and should be faster). Use only strsep() in new code, please. */ +#include #include #include #include diff --git a/lib/tpm-common.c b/lib/tpm-common.c index a440639cec..86b4f413c2 100644 --- a/lib/tpm-common.c +++ b/lib/tpm-common.c @@ -12,6 +12,13 @@ #include #include "tpm-utils.h" +enum tpm_version tpm_get_version(struct udevice *dev) +{ + struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); + + return priv->version; +} + int pack_byte_string(u8 *str, size_t size, const char *format, ...) { va_list args; @@ -112,7 +119,7 @@ int unpack_byte_string(const u8 *str, size_t size, const char *format, ...) if (offset + length > size) { va_end(args); - log_err("Failed to read: size=%d, offset=%x, len=%x\n", + log_err("Failed to read: size=%zd, offset=%zx, len=%zx\n", size, offset, length); return -1; } @@ -151,9 +158,9 @@ u32 tpm_return_code(const void *response) return get_unaligned_be32(response + return_code_offset); } -u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr) +u32 tpm_sendrecv_command(struct udevice *dev, const void *command, + void *response, size_t *size_ptr) { - struct udevice *dev; int err, ret; u8 response_buffer[COMMAND_BUFFER_SIZE]; size_t response_length; @@ -166,9 +173,6 @@ u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr) response_length = sizeof(response_buffer); } - ret = uclass_first_device_err(UCLASS_TPM, &dev); - if (ret) - return ret; err = tpm_xfer(dev, command, tpm_command_size(command), response, &response_length); @@ -188,14 +192,7 @@ u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr) return ret; } -int tpm_init(void) +int tpm_init(struct udevice *dev) { - struct udevice *dev; - int err; - - err = uclass_first_device_err(UCLASS_TPM, &dev); - if (err) - return err; - return tpm_open(dev); } diff --git a/lib/tpm-utils.h b/lib/tpm-utils.h index a9cb7dc7ee..d680d14088 100644 --- a/lib/tpm-utils.h +++ b/lib/tpm-utils.h @@ -18,24 +18,6 @@ #define tpm_u16(x) __MSB(x), __LSB(x) #define tpm_u32(x) tpm_u16((x) >> 16), tpm_u16((x) & 0xFFFF) -/** - * tpm_open() - Request access to locality 0 for the caller - * - * After all commands have been completed the caller is supposed to - * call tpm_close(). - * - * Returns 0 on success, -ve on failure. - */ -int tpm_open(struct udevice *dev); - -/** - * tpm_close() - Close the current session - * - * Releasing the locked locality. Returns 0 on success, -ve 1 on - * failure (in case lock removal did not succeed). - */ -int tpm_close(struct udevice *dev); - /** * Pack data into a byte string. The data types are specified in * the format string: 'b' means unsigned byte, 'w' unsigned word, @@ -96,6 +78,7 @@ u32 tpm_return_code(const void *response); * is a bidirectional * @return return code of the TPM response */ -u32 tpm_sendrecv_command(const void *command, void *response, size_t *size_ptr); +u32 tpm_sendrecv_command(struct udevice *dev, const void *command, + void *response, size_t *size_ptr); #endif /* __TPM_UTILS_H */ diff --git a/lib/tpm-v1.c b/lib/tpm-v1.c index 9d45c3d3bf..3e89f84544 100644 --- a/lib/tpm-v1.c +++ b/lib/tpm-v1.c @@ -31,7 +31,7 @@ static struct session_data oiap_session = {0, }; #endif /* CONFIG_TPM_AUTH_SESSIONS */ -u32 tpm_startup(enum tpm_startup_type mode) +u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode) { const u8 command[12] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x0, @@ -44,59 +44,59 @@ u32 tpm_startup(enum tpm_startup_type mode) mode_offset, mode)) return TPM_LIB_ERROR; - return tpm_sendrecv_command(buf, NULL, NULL); + return tpm_sendrecv_command(dev, buf, NULL, NULL); } -u32 tpm_resume(void) +u32 tpm_resume(struct udevice *dev) { - return tpm_startup(TPM_ST_STATE); + return tpm_startup(dev, TPM_ST_STATE); } -u32 tpm_self_test_full(void) +u32 tpm_self_test_full(struct udevice *dev) { const u8 command[10] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_continue_self_test(void) +u32 tpm_continue_self_test(struct udevice *dev) { const u8 command[10] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_clear_and_reenable(void) +u32 tpm_clear_and_reenable(struct udevice *dev) { u32 ret; log_info("TPM: Clear and re-enable\n"); - ret = tpm_force_clear(); + ret = tpm_force_clear(dev); if (ret != TPM_SUCCESS) { log_err("Can't initiate a force clear\n"); return ret; } -#if IS_ENABLED(CONFIG_TPM_V1) - ret = tpm_physical_enable(); - if (ret != TPM_SUCCESS) { - log_err("TPM: Can't set enabled state\n"); - return ret; - } + if (tpm_get_version(dev) == TPM_V1) { + ret = tpm_physical_enable(dev); + if (ret != TPM_SUCCESS) { + log_err("TPM: Can't set enabled state\n"); + return ret; + } - ret = tpm_physical_set_deactivated(0); - if (ret != TPM_SUCCESS) { - log_err("TPM: Can't set deactivated state\n"); - return ret; + ret = tpm_physical_set_deactivated(dev, 0); + if (ret != TPM_SUCCESS) { + log_err("TPM: Can't set deactivated state\n"); + return ret; + } } -#endif return TPM_SUCCESS; } -u32 tpm_nv_define_space(u32 index, u32 perm, u32 size) +u32 tpm_nv_define_space(struct udevice *dev, u32 index, u32 perm, u32 size) { const u8 command[101] = { 0x0, 0xc1, /* TPM_TAG */ @@ -136,15 +136,15 @@ u32 tpm_nv_define_space(u32 index, u32 perm, u32 size) size_offset, size)) return TPM_LIB_ERROR; - return tpm_sendrecv_command(buf, NULL, NULL); + return tpm_sendrecv_command(dev, buf, NULL, NULL); } -u32 tpm_nv_set_locked(void) +u32 tpm_nv_set_locked(struct udevice *dev) { - return tpm_nv_define_space(TPM_NV_INDEX_LOCK, 0, 0); + return tpm_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0); } -u32 tpm_nv_read_value(u32 index, void *data, u32 count) +u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count) { const u8 command[22] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, @@ -163,7 +163,7 @@ u32 tpm_nv_read_value(u32 index, void *data, u32 count) index_offset, index, length_offset, count)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", @@ -178,7 +178,8 @@ u32 tpm_nv_read_value(u32 index, void *data, u32 count) return 0; } -u32 tpm_nv_write_value(u32 index, const void *data, u32 length) +u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data, + u32 length) { const u8 command[256] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, @@ -201,21 +202,22 @@ u32 tpm_nv_write_value(u32 index, const void *data, u32 length) length_offset, length, data_offset, data, length)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; return 0; } -uint32_t tpm_set_global_lock(void) +uint32_t tpm_set_global_lock(struct udevice *dev) { u32 x; - return tpm_nv_write_value(TPM_NV_INDEX_0, (uint8_t *)&x, 0); + return tpm_nv_write_value(dev, TPM_NV_INDEX_0, (uint8_t *)&x, 0); } -u32 tpm_extend(u32 index, const void *in_digest, void *out_digest) +u32 tpm_extend(struct udevice *dev, u32 index, const void *in_digest, + void *out_digest) { const u8 command[34] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, @@ -234,7 +236,7 @@ u32 tpm_extend(u32 index, const void *in_digest, void *out_digest) in_digest_offset, in_digest, PCR_DIGEST_LENGTH)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; @@ -246,7 +248,7 @@ u32 tpm_extend(u32 index, const void *in_digest, void *out_digest) return 0; } -u32 tpm_pcr_read(u32 index, void *data, size_t count) +u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count) { const u8 command[14] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, @@ -264,7 +266,7 @@ u32 tpm_pcr_read(u32 index, void *data, size_t count) 0, command, sizeof(command), index_offset, index)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "s", @@ -274,7 +276,7 @@ u32 tpm_pcr_read(u32 index, void *data, size_t count) return 0; } -u32 tpm_tsc_physical_presence(u16 presence) +u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence) { const u8 command[12] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x0, @@ -287,19 +289,19 @@ u32 tpm_tsc_physical_presence(u16 presence) presence_offset, presence)) return TPM_LIB_ERROR; - return tpm_sendrecv_command(buf, NULL, NULL); + return tpm_sendrecv_command(dev, buf, NULL, NULL); } -u32 tpm_finalise_physical_presence(void) +u32 tpm_finalise_physical_presence(struct udevice *dev) { const u8 command[12] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_read_pubek(void *data, size_t count) +u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count) { const u8 command[30] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, @@ -312,7 +314,7 @@ u32 tpm_read_pubek(void *data, size_t count) u32 data_size; u32 err; - err = tpm_sendrecv_command(command, response, &response_length); + err = tpm_sendrecv_command(dev, command, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", @@ -330,34 +332,34 @@ u32 tpm_read_pubek(void *data, size_t count) return 0; } -u32 tpm_force_clear(void) +u32 tpm_force_clear(struct udevice *dev) { const u8 command[10] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_physical_enable(void) +u32 tpm_physical_enable(struct udevice *dev) { const u8 command[10] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_physical_disable(void) +u32 tpm_physical_disable(struct udevice *dev) { const u8 command[10] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, }; - return tpm_sendrecv_command(command, NULL, NULL); + return tpm_sendrecv_command(dev, command, NULL, NULL); } -u32 tpm_physical_set_deactivated(u8 state) +u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state) { const u8 command[11] = { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, @@ -370,10 +372,11 @@ u32 tpm_physical_set_deactivated(u8 state) state_offset, state)) return TPM_LIB_ERROR; - return tpm_sendrecv_command(buf, NULL, NULL); + return tpm_sendrecv_command(dev, buf, NULL, NULL); } -u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count) +u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap, + void *cap, size_t count) { const u8 command[22] = { 0x0, 0xc1, /* TPM_TAG */ @@ -397,7 +400,7 @@ u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count) cap_area_offset, cap_area, sub_cap_offset, sub_cap)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", @@ -412,7 +415,8 @@ u32 tpm_get_capability(u32 cap_area, u32 sub_cap, void *cap, size_t count) return 0; } -u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags) +u32 tpm_get_permanent_flags(struct udevice *dev, + struct tpm_permanent_flags *pflags) { const u8 command[22] = { 0x0, 0xc1, /* TPM_TAG */ @@ -429,7 +433,7 @@ u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags) u32 err; u32 data_size; - err = tpm_sendrecv_command(command, response, &response_length); + err = tpm_sendrecv_command(dev, command, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", @@ -450,7 +454,7 @@ u32 tpm_get_permanent_flags(struct tpm_permanent_flags *pflags) return 0; } -u32 tpm_get_permissions(u32 index, u32 *perm) +u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm) { const u8 command[22] = { 0x0, 0xc1, /* TPM_TAG */ @@ -468,7 +472,7 @@ u32 tpm_get_permissions(u32 index, u32 *perm) if (pack_byte_string(buf, sizeof(buf), "d", 0, command, sizeof(command), index_offset, index)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", @@ -479,7 +483,7 @@ u32 tpm_get_permissions(u32 index, u32 *perm) } #ifdef CONFIG_TPM_FLUSH_RESOURCES -u32 tpm_flush_specific(u32 key_handle, u32 resource_type) +u32 tpm_flush_specific(struct udevice *dev, u32 key_handle, u32 resource_type) { const u8 command[18] = { 0x00, 0xc1, /* TPM_TAG */ @@ -500,7 +504,7 @@ u32 tpm_flush_specific(u32 key_handle, u32 resource_type) resource_type_offset, resource_type)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, &response_length); if (err) return err; return 0; @@ -638,7 +642,7 @@ static u32 verify_response_auth(u32 command_code, const void *response, return TPM_SUCCESS; } -u32 tpm_terminate_auth_session(u32 auth_handle) +u32 tpm_terminate_auth_session(struct udevice *dev, u32 auth_handle) { const u8 command[18] = { 0x00, 0xc1, /* TPM_TAG */ @@ -657,19 +661,19 @@ u32 tpm_terminate_auth_session(u32 auth_handle) if (oiap_session.valid && oiap_session.handle == auth_handle) oiap_session.valid = 0; - return tpm_sendrecv_command(request, NULL, NULL); + return tpm_sendrecv_command(dev, request, NULL, NULL); } -u32 tpm_end_oiap(void) +u32 tpm_end_oiap(struct udevice *dev) { u32 err = TPM_SUCCESS; if (oiap_session.valid) - err = tpm_terminate_auth_session(oiap_session.handle); + err = tpm_terminate_auth_session(dev, oiap_session.handle); return err; } -u32 tpm_oiap(u32 *auth_handle) +u32 tpm_oiap(struct udevice *dev, u32 *auth_handle) { const u8 command[10] = { 0x00, 0xc1, /* TPM_TAG */ @@ -683,9 +687,9 @@ u32 tpm_oiap(u32 *auth_handle) u32 err; if (oiap_session.valid) - tpm_terminate_auth_session(oiap_session.handle); + tpm_terminate_auth_session(dev, oiap_session.handle); - err = tpm_sendrecv_command(command, response, &response_length); + err = tpm_sendrecv_command(dev, command, response, &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "ds", @@ -699,8 +703,9 @@ u32 tpm_oiap(u32 *auth_handle) return 0; } -u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, - const void *parent_key_usage_auth, u32 *key_handle) +u32 tpm_load_key2_oiap(struct udevice *dev, u32 parent_handle, const void *key, + size_t key_length, const void *parent_key_usage_auth, + u32 *key_handle) { const u8 command[14] = { 0x00, 0xc2, /* TPM_TAG */ @@ -719,7 +724,7 @@ u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, u32 err; if (!oiap_session.valid) { - err = tpm_oiap(NULL); + err = tpm_oiap(dev, NULL); if (err) return err; } @@ -739,7 +744,7 @@ u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, parent_key_usage_auth); if (err) return err; - err = tpm_sendrecv_command(request, response, &response_length); + err = tpm_sendrecv_command(dev, request, response, &response_length); if (err) { if (err == TPM_AUTHFAIL) oiap_session.valid = 0; @@ -764,7 +769,8 @@ u32 tpm_load_key2_oiap(u32 parent_handle, const void *key, size_t key_length, return 0; } -u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey, +u32 tpm_get_pub_key_oiap(struct udevice *dev, u32 key_handle, + const void *usage_auth, void *pubkey, size_t *pubkey_len) { const u8 command[14] = { @@ -783,7 +789,7 @@ u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey, u32 err; if (!oiap_session.valid) { - err = tpm_oiap(NULL); + err = tpm_oiap(dev, NULL); if (err) return err; } @@ -799,7 +805,7 @@ u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey, request + sizeof(command), usage_auth); if (err) return err; - err = tpm_sendrecv_command(request, response, &response_length); + err = tpm_sendrecv_command(dev, request, response, &response_length); if (err) { if (err == TPM_AUTHFAIL) oiap_session.valid = 0; @@ -829,8 +835,8 @@ u32 tpm_get_pub_key_oiap(u32 key_handle, const void *usage_auth, void *pubkey, } #ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1 -u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20], - u32 *handle) +u32 tpm_find_key_sha1(struct udevice *dev, const u8 auth[20], + const u8 pubkey_digest[20], u32 *handle) { u16 key_count; u32 key_handles[10]; @@ -842,7 +848,8 @@ u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20], unsigned int i; /* fetch list of already loaded keys in the TPM */ - err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf)); + err = tpm_get_capability(dev, TPM_CAP_HANDLE, TPM_RT_KEY, buf, + sizeof(buf)); if (err) return -1; key_count = get_unaligned_be16(buf); @@ -870,7 +877,7 @@ u32 tpm_find_key_sha1(const u8 auth[20], const u8 pubkey_digest[20], #endif /* CONFIG_TPM_AUTH_SESSIONS */ -u32 tpm_get_random(void *data, u32 count) +u32 tpm_get_random(struct udevice *dev, void *data, u32 count) { const u8 command[14] = { 0x0, 0xc1, /* TPM_TAG */ @@ -894,7 +901,8 @@ u32 tpm_get_random(void *data, u32 count) 0, command, sizeof(command), length_offset, this_bytes)) return TPM_LIB_ERROR; - err = tpm_sendrecv_command(buf, response, &response_length); + err = tpm_sendrecv_command(dev, buf, response, + &response_length); if (err) return err; if (unpack_byte_string(response, response_length, "d", diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index f1bbca8e7a..f89592d6e2 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -10,7 +10,7 @@ #include #include "tpm-utils.h" -u32 tpm2_startup(enum tpm2_startup_types mode) +u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) { const u8 command_v2[12] = { tpm_u16(TPM2_ST_NO_SESSIONS), @@ -24,14 +24,14 @@ u32 tpm2_startup(enum tpm2_startup_types mode) * Note TPM2_Startup command will return RC_SUCCESS the first time, * but will return RC_INITIALIZE otherwise. */ - ret = tpm_sendrecv_command(command_v2, NULL, NULL); + ret = tpm_sendrecv_command(dev, command_v2, NULL, NULL); if (ret && ret != TPM2_RC_INITIALIZE) return ret; return 0; } -u32 tpm2_self_test(enum tpm2_yes_no full_test) +u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test) { const u8 command_v2[12] = { tpm_u16(TPM2_ST_NO_SESSIONS), @@ -40,10 +40,11 @@ u32 tpm2_self_test(enum tpm2_yes_no full_test) full_test, }; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_clear(u32 handle, const char *pw, const ssize_t pw_sz) +u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, + const ssize_t pw_sz) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_SESSIONS), /* TAG */ @@ -75,10 +76,10 @@ u32 tpm2_clear(u32 handle, const char *pw, const ssize_t pw_sz) if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_pcr_extend(u32 index, const uint8_t *digest) +u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_SESSIONS), /* TAG */ @@ -113,11 +114,11 @@ u32 tpm2_pcr_extend(u32 index, const uint8_t *digest) if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data, - unsigned int *updates) +u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, + void *data, unsigned int *updates) { u8 idx_array_sz = max(idx_min_sz, DIV_ROUND_UP(idx, 8)); u8 command_v2[COMMAND_BUFFER_SIZE] = { @@ -142,7 +143,7 @@ u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data, 17 + pcr_sel_idx, pcr_sel_bit)) return TPM_LIB_ERROR; - ret = tpm_sendrecv_command(command_v2, response, &response_len); + ret = tpm_sendrecv_command(dev, command_v2, response, &response_len); if (ret) return ret; @@ -158,8 +159,8 @@ u32 tpm2_pcr_read(u32 idx, unsigned int idx_min_sz, void *data, return 0; } -u32 tpm2_get_capability(u32 capability, u32 property, void *buf, - size_t prop_count) +u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, + void *buf, size_t prop_count) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_NO_SESSIONS), /* TAG */ @@ -175,7 +176,7 @@ u32 tpm2_get_capability(u32 capability, u32 property, void *buf, unsigned int properties_off; int ret; - ret = tpm_sendrecv_command(command_v2, response, &response_len); + ret = tpm_sendrecv_command(dev, command_v2, response, &response_len); if (ret) return ret; @@ -191,7 +192,7 @@ u32 tpm2_get_capability(u32 capability, u32 property, void *buf, return 0; } -u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz) +u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_SESSIONS), /* TAG */ @@ -223,11 +224,12 @@ u32 tpm2_dam_reset(const char *pw, const ssize_t pw_sz) if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz, - unsigned int max_tries, unsigned int recovery_time, +u32 tpm2_dam_parameters(struct udevice *dev, const char *pw, + const ssize_t pw_sz, unsigned int max_tries, + unsigned int recovery_time, unsigned int lockout_recovery) { u8 command_v2[COMMAND_BUFFER_SIZE] = { @@ -271,11 +273,12 @@ u32 tpm2_dam_parameters(const char *pw, const ssize_t pw_sz, if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz, - const char *oldpw, const ssize_t oldpw_sz) +int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw, + const ssize_t newpw_sz, const char *oldpw, + const ssize_t oldpw_sz) { unsigned int offset = 27; u8 command_v2[COMMAND_BUFFER_SIZE] = { @@ -315,11 +318,11 @@ int tpm2_change_auth(u32 handle, const char *newpw, const ssize_t newpw_sz, if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index, - const char *key) +u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw, + const ssize_t pw_sz, u32 index, const char *key) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_SESSIONS), /* TAG */ @@ -370,11 +373,12 @@ u32 tpm2_pcr_setauthpolicy(const char *pw, const ssize_t pw_sz, u32 index, if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } -u32 tpm2_pcr_setauthvalue(const char *pw, const ssize_t pw_sz, u32 index, - const char *key, const ssize_t key_sz) +u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw, + const ssize_t pw_sz, u32 index, const char *key, + const ssize_t key_sz) { u8 command_v2[COMMAND_BUFFER_SIZE] = { tpm_u16(TPM2_ST_SESSIONS), /* TAG */ @@ -415,5 +419,5 @@ u32 tpm2_pcr_setauthvalue(const char *pw, const ssize_t pw_sz, u32 index, if (ret) return TPM_LIB_ERROR; - return tpm_sendrecv_command(command_v2, NULL, NULL); + return tpm_sendrecv_command(dev, command_v2, NULL, NULL); } diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 9b64a63419..70bd0b334b 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -381,7 +381,7 @@ $(obj)/%.efi: $(obj)/%_efi.so quiet_cmd_efi_ld = LD $@ cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \ - -Bsymbolic $^ -o $@ + -Bsymbolic -s $^ -o $@ EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 7416abec62..2ef19bf005 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -81,9 +81,11 @@ libs-$(CONFIG_TPL_LIBGENERIC_SUPPORT) += lib/ else libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/ env/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ +ifdef CONFIG_SPL_FRAMEWORK +libs-$(CONFIG_PARTITIONS) += disk/ +endif endif -libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ libs-y += drivers/ libs-$(CONFIG_SPL_USB_GADGET_SUPPORT) += drivers/usb/dwc3/ libs-y += dts/ @@ -219,6 +221,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin +ALL-$(CONFIG_ARCH_MEDIATEK) += $(obj)/u-boot-spl-mtk.bin + all: $(ALL-y) quiet_cmd_cat = CAT $@ @@ -349,6 +353,15 @@ cmd_sunxi_spl_image_builder = $(objtree)/tools/sunxi-spl-image-builder \ $(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin $(call if_changed,sunxi_spl_image_builder) + +# MediaTek's specific SPL build +MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtk_image \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \ + -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))" + +$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + # Rule to link u-boot-spl # May be overridden by arch/$(ARCH)/config.mk quiet_cmd_u-boot-spl ?= LD $@ diff --git a/scripts/check-config.sh b/scripts/check-config.sh index 4848ca6e25..583f7d0963 100755 --- a/scripts/check-config.sh +++ b/scripts/check-config.sh @@ -17,6 +17,15 @@ set -e set -u +PROG_NAME="${0##*/}" + +usage() { + echo "$PROG_NAME " + exit 1 +} + +[ $# -ge 3 ] || usage + path="$1" whitelist="$2" srctree="$3" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0627024e71..527050de97 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -82,11 +82,9 @@ CONFIG_AT91SAM9G20EK_2MMC CONFIG_AT91SAM9G45EKES CONFIG_AT91SAM9G45_LCD_BASE CONFIG_AT91SAM9M10G45EK -CONFIG_AT91SAM9_WATCHDOG CONFIG_AT91_CAN CONFIG_AT91_EFLASH CONFIG_AT91_GPIO_PULLUP -CONFIG_AT91_HW_WDT_TIMEOUT CONFIG_AT91_LED CONFIG_AT91_WANTS_COMMON_PHY CONFIG_ATAPI @@ -355,7 +353,6 @@ CONFIG_DESIGNWARE_ETH CONFIG_DESIGNWARE_WATCHDOG CONFIG_DEVELOP CONFIG_DEVICE_TREE_LIST -CONFIG_DEV_USB_PHY_BASE CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC CONFIG_DFU_ALT_BOOT_SD @@ -399,13 +396,11 @@ CONFIG_DRIVER_NE2000_VAL CONFIG_DRIVER_SMC911X_BASE CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE CONFIG_DRIVER_TI_EMAC_USE_RMII -CONFIG_DRIVER_TI_KEYSTONE_NET CONFIG_DRIVE_MMC CONFIG_DRIVE_SATA CONFIG_DRIVE_TYPES CONFIG_DSP_CLUSTER_START CONFIG_DUOVERO -CONFIG_DV_USBPHY_CTL CONFIG_DWC2_DFLT_SPEED_FULL CONFIG_DWC2_DMA_BURST_SIZE CONFIG_DWC2_DMA_ENABLE @@ -695,7 +690,6 @@ CONFIG_FTAPBBRG020S_01_BASE CONFIG_FTCFC010_BASE CONFIG_FTDMAC020_BASE CONFIG_FTGMAC100_BASE -CONFIG_FTGMAC100_EGIGA CONFIG_FTGPIO010_BASE CONFIG_FTIDE020S_BASE CONFIG_FTIIC010_BASE @@ -751,7 +745,6 @@ CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_H264_FREQ CONFIG_H8300 -CONFIG_HARD_SPI CONFIG_HAS_ETH0 CONFIG_HAS_ETH1 CONFIG_HAS_ETH2 @@ -962,7 +955,6 @@ CONFIG_IMX_OTP CONFIG_IMX_VIDEO_SKIP CONFIG_INETSPACE_V2 CONFIG_INITRD_TAG -CONFIG_INIT_CRITICAL CONFIG_INIT_IGNORE_ERROR CONFIG_INI_ALLOW_MULTILINE CONFIG_INI_CASE_INSENSITIVE @@ -1201,7 +1193,6 @@ CONFIG_MALLOC_F_ADDR CONFIG_MALTA CONFIG_MARCO_MEMSET CONFIG_MARUBUN_PCCARD -CONFIG_MARVELL CONFIG_MARVELL_GPIO CONFIG_MARVELL_MFP CONFIG_MASK_AER_AO @@ -1489,7 +1480,6 @@ CONFIG_PHY_ID CONFIG_PHY_INTERFACE_MODE CONFIG_PHY_IRAM_BASE CONFIG_PHY_M88E1111 -CONFIG_PHY_MAX_ADDR CONFIG_PHY_MODE_NEED_CHANGE CONFIG_PHY_RESET CONFIG_PHY_RESET_DELAY @@ -1664,7 +1654,6 @@ CONFIG_RTC_DS3231 CONFIG_RTC_FTRTC010 CONFIG_RTC_IMXDI CONFIG_RTC_M41T11 -CONFIG_RTC_M41T62 CONFIG_RTC_MC13XXX CONFIG_RTC_MCFRRTC CONFIG_RTC_MCP79411 @@ -4057,7 +4046,6 @@ CONFIG_SYS_RTC_CNT CONFIG_SYS_RTC_OSCILLATOR CONFIG_SYS_RTC_REG_BASE_ADDR CONFIG_SYS_RTC_SETUP -CONFIG_SYS_RV3029_TCR CONFIG_SYS_RX_ETH_BUFFER CONFIG_SYS_SATA CONFIG_SYS_SATA1 @@ -4583,7 +4571,6 @@ CONFIG_USB_GADGET_PXA27X CONFIG_USB_GADGET_PXA2XX CONFIG_USB_GADGET_SA1100 CONFIG_USB_GADGET_SUPERH -CONFIG_USB_HOST_XHCI_BASE CONFIG_USB_INVENTRA_DMA CONFIG_USB_ISP1301_I2C_ADDR CONFIG_USB_MAX_CONTROLLER_COUNT @@ -4596,18 +4583,15 @@ CONFIG_USB_OHCI_NEW CONFIG_USB_OHCI_SUNXI CONFIG_USB_OTG CONFIG_USB_OTG_BLACKLIST_HUB -CONFIG_USB_PHY_CFG_BASE CONFIG_USB_PHY_TYPE CONFIG_USB_PXA25X_SMALL CONFIG_USB_R8A66597_HCD CONFIG_USB_SERIALNO -CONFIG_USB_SS_BASE CONFIG_USB_TI_CPPI_DMA CONFIG_USB_TTY CONFIG_USB_TUSB_OMAP_DMA CONFIG_USB_ULPI_TIMEOUT CONFIG_USB_XHCI_EXYNOS -CONFIG_USB_XHCI_KEYSTONE CONFIG_USB_XHCI_OMAP CONFIG_USER_LOWLEVEL_INIT CONFIG_USE_INTERRUPT diff --git a/test/Makefile b/test/Makefile index 1e434730b6..2fe41f489c 100644 --- a/test/Makefile +++ b/test/Makefile @@ -2,6 +2,7 @@ # # (C) Copyright 2012 The Chromium Authors +obj-$(CONFIG_SANDBOX) += bloblist.o obj-$(CONFIG_UNIT_TEST) += cmd_ut.o obj-$(CONFIG_UNIT_TEST) += ut.o obj-$(CONFIG_SANDBOX) += command_ut.o diff --git a/test/README b/test/README index 873a4e1931..4bc9ca3a6a 100644 --- a/test/README +++ b/test/README @@ -10,11 +10,15 @@ Running tests To run most tests on sandbox, type this: - test/run + make check in the U-Boot directory. Note that only the pytest suite is run using this command. +Some tests take ages to run. To run just the quick ones, type this: + + make qcheck + Sandbox ------- diff --git a/test/bloblist.c b/test/bloblist.c new file mode 100644 index 0000000000..89bdb012e3 --- /dev/null +++ b/test/bloblist.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018, Google Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Declare a new compression test */ +#define BLOBLIST_TEST(_name, _flags) \ + UNIT_TEST(_name, _flags, bloblist_test) + +enum { + TEST_TAG = 1, + TEST_TAG2 = 2, + TEST_TAG_MISSING = 3, + + TEST_SIZE = 10, + TEST_SIZE2 = 20, + + TEST_ADDR = CONFIG_BLOBLIST_ADDR, + TEST_BLOBLIST_SIZE = 0x100, +}; + +static struct bloblist_hdr *clear_bloblist(void) +{ + struct bloblist_hdr *hdr; + + /* Clear out any existing bloblist so we have a clean slate */ + hdr = map_sysmem(CONFIG_BLOBLIST_ADDR, TEST_BLOBLIST_SIZE); + memset(hdr, '\0', TEST_BLOBLIST_SIZE); + + return hdr; +} + +static int bloblist_test_init(struct unit_test_state *uts) +{ + struct bloblist_hdr *hdr; + + hdr = clear_bloblist(); + ut_asserteq(-ENOENT, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0)); + hdr->version++; + ut_asserteq(-EPROTONOSUPPORT, bloblist_check(TEST_ADDR, + TEST_BLOBLIST_SIZE)); + + ut_asserteq(-ENOSPC, bloblist_new(TEST_ADDR, 0x10, 0)); + ut_asserteq(-EFAULT, bloblist_new(1, TEST_BLOBLIST_SIZE, 0)); + ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0)); + + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + ut_assertok(bloblist_finish()); + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + hdr->flags++; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + + return 1; +} +BLOBLIST_TEST(bloblist_test_init, 0); + +static int bloblist_test_blob(struct unit_test_state *uts) +{ + struct bloblist_hdr *hdr; + struct bloblist_rec *rec, *rec2; + char *data; + + /* At the start there should be no records */ + hdr = clear_bloblist(); + ut_assertnull(bloblist_find(TEST_TAG, TEST_BLOBLIST_SIZE)); + ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0)); + + /* Add a record and check that we can find it */ + data = bloblist_add(TEST_TAG, TEST_SIZE); + rec = (void *)(hdr + 1); + ut_asserteq_ptr(rec + 1, data); + data = bloblist_find(TEST_TAG, TEST_SIZE); + ut_asserteq_ptr(rec + 1, data); + + /* Check the 'ensure' method */ + ut_asserteq_ptr(data, bloblist_ensure(TEST_TAG, TEST_SIZE)); + ut_assertnull(bloblist_ensure(TEST_TAG, TEST_SIZE2)); + rec2 = (struct bloblist_rec *)(data + ALIGN(TEST_SIZE, BLOBLIST_ALIGN)); + + /* Check for a non-existent record */ + ut_asserteq_ptr(data, bloblist_ensure(TEST_TAG, TEST_SIZE)); + ut_asserteq_ptr(rec2 + 1, bloblist_ensure(TEST_TAG2, TEST_SIZE2)); + ut_assertnull(bloblist_find(TEST_TAG_MISSING, 0)); + + return 0; +} +BLOBLIST_TEST(bloblist_test_blob, 0); + +static int bloblist_test_bad_blob(struct unit_test_state *uts) +{ + struct bloblist_hdr *hdr; + void *data; + + hdr = clear_bloblist(); + ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0)); + data = hdr + 1; + data += sizeof(struct bloblist_rec); + ut_asserteq_ptr(data, bloblist_ensure(TEST_TAG, TEST_SIZE)); + ut_asserteq_ptr(data, bloblist_ensure(TEST_TAG, TEST_SIZE)); + + return 0; +} +BLOBLIST_TEST(bloblist_test_bad_blob, 0); + +static int bloblist_test_checksum(struct unit_test_state *uts) +{ + struct bloblist_hdr *hdr; + char *data, *data2; + + hdr = clear_bloblist(); + ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0)); + ut_assertok(bloblist_finish()); + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + + /* + * Now change things amd make sure that the checksum notices. We cannot + * change the size or alloced fields, since that will crash the code. + * It has to rely on these being correct. + */ + hdr->flags--; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + hdr->flags++; + + hdr->size--; + ut_asserteq(-EFBIG, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + hdr->size++; + + hdr->spare++; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + hdr->spare--; + + hdr->chksum++; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + hdr->chksum--; + + /* Make sure the checksum changes when we add blobs */ + data = bloblist_add(TEST_TAG, TEST_SIZE); + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + + data2 = bloblist_add(TEST_TAG2, TEST_SIZE2); + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + ut_assertok(bloblist_finish()); + + /* It should also change if we change the data */ + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + *data += 1; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + *data -= 1; + + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + *data2 += 1; + ut_asserteq(-EIO, bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + *data2 -= 1; + + /* + * Changing data outside the range of valid data should not affect + * the checksum. + */ + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + data[TEST_SIZE]++; + data2[TEST_SIZE2]++; + ut_assertok(bloblist_check(TEST_ADDR, TEST_BLOBLIST_SIZE)); + + return 0; +} + +BLOBLIST_TEST(bloblist_test_checksum, 0); + +int do_ut_bloblist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = ll_entry_start(struct unit_test, + bloblist_test); + const int n_ents = ll_entry_count(struct unit_test, bloblist_test); + + return cmd_ut_category("bloblist", tests, n_ents, argc, argv); +} diff --git a/test/cmd_ut.c b/test/cmd_ut.c index b7e01a4847..56924a5272 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -55,6 +55,8 @@ static cmd_tbl_t cmd_ut_sub[] = { #ifdef CONFIG_SANDBOX U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression, "", ""), + U_BOOT_CMD_MKENT(bloblist, CONFIG_SYS_MAXARGS, 1, do_ut_bloblist, + "", ""), #endif }; @@ -97,6 +99,7 @@ static int do_ut(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static char ut_help_text[] = "all - execute all enabled tests\n" #ifdef CONFIG_SANDBOX + "ut bloblist - Test bloblist implementation\n" "ut compression - Test compressors and bootm decompression\n" #endif #ifdef CONFIG_UT_DM diff --git a/test/dm/Makefile b/test/dm/Makefile index b490cf2862..7dc80be25e 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -2,7 +2,6 @@ # # Copyright (c) 2013 Google, Inc -obj-$(CONFIG_CMD_DM) += cmd_dm.o obj-$(CONFIG_UT_DM) += bus.o obj-$(CONFIG_UT_DM) += test-driver.o obj-$(CONFIG_UT_DM) += test-fdt.o @@ -13,13 +12,16 @@ obj-$(CONFIG_UT_DM) += test-uclass.o # subsystem you must add sandbox tests here. obj-$(CONFIG_UT_DM) += core.o ifneq ($(CONFIG_SANDBOX),) +obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_BLK) += blk.o obj-$(CONFIG_BOARD) += board.o obj-$(CONFIG_CLK) += clk.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_FIRMWARE) += firmware.o obj-$(CONFIG_DM_GPIO) += gpio.o +obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o +obj-$(CONFIG_SOUND) += i2s.o obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o @@ -52,5 +54,8 @@ obj-$(CONFIG_AXI) += axi.o obj-$(CONFIG_MISC) += misc.o obj-$(CONFIG_DM_SERIAL) += serial.o obj-$(CONFIG_CPU) += cpu.o +obj-$(CONFIG_SOUND) += sound.o obj-$(CONFIG_TEE) += tee.o +obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o +obj-$(CONFIG_DMA) += dma.o endif diff --git a/test/dm/adc.c b/test/dm/adc.c index 13eda3bd23..1f82304f41 100644 --- a/test/dm/adc.c +++ b/test/dm/adc.c @@ -22,10 +22,14 @@ static int dm_test_adc_bind(struct unit_test_state *uts) { struct udevice *dev; + unsigned int channel_mask; ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); ut_asserteq_str(SANDBOX_ADC_DEVNAME, dev->name); + ut_assertok(adc_channel_mask(dev, &channel_mask)); + ut_asserteq((1 << SANDBOX_ADC_CHANNELS) - 1, channel_mask); + return 0; } DM_TEST(dm_test_adc_bind, DM_TESTF_SCAN_FDT); @@ -160,3 +164,34 @@ static int dm_test_adc_multi_channel_shot(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_adc_multi_channel_shot, DM_TESTF_SCAN_FDT); + +static const int dm_test_adc_uV_data[SANDBOX_ADC_CHANNELS] = { + ((u64)SANDBOX_ADC_CHANNEL0_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) / + SANDBOX_ADC_DATA_MASK, + ((u64)SANDBOX_ADC_CHANNEL1_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) / + SANDBOX_ADC_DATA_MASK, + ((u64)SANDBOX_ADC_CHANNEL2_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) / + SANDBOX_ADC_DATA_MASK, + ((u64)SANDBOX_ADC_CHANNEL3_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) / + SANDBOX_ADC_DATA_MASK, +}; + +static int dm_test_adc_raw_to_uV(struct unit_test_state *uts) +{ + struct adc_channel *tdata = adc_channel_test_data; + unsigned int i, data; + struct udevice *dev; + int uV; + + ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev)); + /* Test each ADC channel's value in microvolts */ + for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) { + ut_assertok(adc_start_channel(dev, tdata->id)); + ut_assertok(adc_channel_data(dev, tdata->id, &data)); + ut_assertok(adc_raw_to_uV(dev, data, &uV)); + ut_asserteq(dm_test_adc_uV_data[i], uV); + } + + return 0; +} +DM_TEST(dm_test_adc_raw_to_uV, DM_TESTF_SCAN_FDT); diff --git a/test/dm/audio.c b/test/dm/audio.c new file mode 100644 index 0000000000..77c3a3625b --- /dev/null +++ b/test/dm/audio.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +/* Basic test of the audio codec uclass */ +static int dm_test_audio(struct unit_test_state *uts) +{ + int interface, rate, mclk_freq, bits_per_sample; + struct udevice *dev; + uint channels; + + /* check probe success */ + ut_assertok(uclass_first_device_err(UCLASS_AUDIO_CODEC, &dev)); + ut_assertok(audio_codec_set_params(dev, 1, 2, 3, 4, 5)); + sandbox_get_codec_params(dev, &interface, &rate, &mclk_freq, + &bits_per_sample, &channels); + ut_asserteq(1, interface); + ut_asserteq(2, rate); + ut_asserteq(3, mclk_freq); + ut_asserteq(4, bits_per_sample); + ut_asserteq(5, channels); + + return 0; +} +DM_TEST(dm_test_audio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/blk.c b/test/dm/blk.c index 4de477bafa..9c71adc69d 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -15,34 +15,29 @@ DECLARE_GLOBAL_DATA_PTR; /* Test that block devices can be created */ static int dm_test_blk_base(struct unit_test_state *uts) { - struct udevice *blk, *usb_blk, *dev; + struct udevice *blk1, *blk3, *dev; /* Make sure there are no block devices */ - ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_BLK, 0, &blk)); + ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_BLK, 0, &dev)); /* Create two, one the parent of the other */ ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test", - IF_TYPE_HOST, 1, 512, 2, &blk)); - ut_assertok(blk_create_device(blk, "usb_storage_blk", "test", - IF_TYPE_USB, 3, 512, 2, &usb_blk)); + IF_TYPE_HOST, 1, 512, 2, &blk1)); + ut_assertok(blk_create_device(blk1, "sandbox_host_blk", "test", + IF_TYPE_HOST, 3, 512, 2, &blk3)); /* Check we can find them */ ut_asserteq(-ENODEV, blk_get_device(IF_TYPE_HOST, 0, &dev)); ut_assertok(blk_get_device(IF_TYPE_HOST, 1, &dev)); - ut_asserteq_ptr(blk, dev); - - ut_asserteq(-ENODEV, blk_get_device(IF_TYPE_USB, 0, &dev)); - ut_assertok(blk_get_device(IF_TYPE_USB, 3, &dev)); - ut_asserteq_ptr(usb_blk, dev); + ut_asserteq_ptr(blk1, dev); + ut_assertok(blk_get_device(IF_TYPE_HOST, 3, &dev)); + ut_asserteq_ptr(blk3, dev); /* Check we can iterate */ ut_assertok(blk_first_device(IF_TYPE_HOST, &dev)); - ut_asserteq_ptr(blk, dev); - ut_asserteq(-ENODEV, blk_next_device(&dev)); - - ut_assertok(blk_first_device(IF_TYPE_USB, &dev)); - ut_asserteq_ptr(usb_blk, dev); - ut_asserteq(-ENODEV, blk_next_device(&dev)); + ut_asserteq_ptr(blk1, dev); + ut_assertok(blk_next_device(&dev)); + ut_asserteq_ptr(blk3, dev); return 0; } diff --git a/test/dm/bus.c b/test/dm/bus.c index 08137a2216..93f3acd430 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -63,6 +63,15 @@ static int testbus_child_pre_probe_uclass(struct udevice *dev) return 0; } +static int testbus_child_post_probe_uclass(struct udevice *dev) +{ + struct dm_test_priv *priv = dev_get_priv(dev); + + priv->uclass_postp++; + + return 0; +} + static int testbus_child_post_remove(struct udevice *dev) { struct dm_test_parent_data *parent_data = dev_get_parent_priv(dev); @@ -102,12 +111,13 @@ UCLASS_DRIVER(testbus) = { .id = UCLASS_TEST_BUS, .flags = DM_UC_FLAG_SEQ_ALIAS, .child_pre_probe = testbus_child_pre_probe_uclass, + .child_post_probe = testbus_child_post_probe_uclass, }; /* Test that we can probe for children */ static int dm_test_bus_children(struct unit_test_state *uts) { - int num_devices = 7; + int num_devices = 8; struct udevice *bus; struct uclass *uc; @@ -547,3 +557,38 @@ static int dm_test_bus_child_pre_probe_uclass(struct unit_test_state *uts) } DM_TEST(dm_test_bus_child_pre_probe_uclass, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* + * Test that the bus' uclass' child_post_probe() is called after the + * device's probe() method + */ +static int dm_test_bus_child_post_probe_uclass(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + int child_count; + + /* + * See testfdt_drv_probe() which effectively initializes that + * the uclass postp flag is set to a value + */ + ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus)); + for (device_find_first_child(bus, &dev), child_count = 0; + dev; + device_find_next_child(&dev)) { + struct dm_test_priv *priv = dev_get_priv(dev); + + /* Check that things happened in the right order */ + ut_asserteq_ptr(NULL, priv); + ut_assertok(device_probe(dev)); + + priv = dev_get_priv(dev); + ut_assert(priv != NULL); + ut_asserteq(0, priv->uclass_postp); + child_count++; + } + ut_asserteq(3, child_count); + + return 0; +} +DM_TEST(dm_test_bus_child_post_probe_uclass, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/dma.c b/test/dm/dma.c new file mode 100644 index 0000000000..b56d17731d --- /dev/null +++ b/test/dm/dma.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Direct Memory Access U-Class tests + * + * Copyright (C) 2018 Texas Instruments Incorporated + * Grygorii Strashko + */ + +#include +#include +#include +#include +#include + +static int dm_test_dma_m2m(struct unit_test_state *uts) +{ + struct udevice *dev; + struct dma dma_m2m; + u8 src_buf[512]; + u8 dst_buf[512]; + size_t len = 512; + int i; + + ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev)); + ut_assertok(dma_get_by_name(dev, "m2m", &dma_m2m)); + + memset(dst_buf, 0, len); + for (i = 0; i < len; i++) + src_buf[i] = i; + + ut_assertok(dma_memcpy(dst_buf, src_buf, len)); + + ut_assertok(memcmp(src_buf, dst_buf, len)); + return 0; +} +DM_TEST(dm_test_dma_m2m, DM_TESTF_SCAN_FDT); + +static int dm_test_dma(struct unit_test_state *uts) +{ + struct udevice *dev; + struct dma dma_tx, dma_rx; + u8 src_buf[512]; + u8 dst_buf[512]; + void *dst_ptr; + size_t len = 512; + u32 meta1, meta2; + int i; + + ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev)); + + ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx)); + ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx)); + + ut_assertok(dma_enable(&dma_tx)); + ut_assertok(dma_enable(&dma_rx)); + + memset(dst_buf, 0, len); + for (i = 0; i < len; i++) + src_buf[i] = i; + meta1 = 0xADADDEAD; + meta2 = 0; + dst_ptr = &dst_buf; + + ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1)); + + ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2)); + ut_asserteq(0xADADDEAD, meta2); + + ut_assertok(dma_disable(&dma_tx)); + ut_assertok(dma_disable(&dma_rx)); + + ut_assertok(dma_free(&dma_tx)); + ut_assertok(dma_free(&dma_rx)); + ut_assertok(memcmp(src_buf, dst_buf, len)); + + return 0; +} +DM_TEST(dm_test_dma, DM_TESTF_SCAN_FDT); + +static int dm_test_dma_rx(struct unit_test_state *uts) +{ + struct udevice *dev; + struct dma dma_tx, dma_rx; + u8 src_buf[512]; + u8 dst_buf[512]; + void *dst_ptr; + size_t len = 512; + u32 meta1, meta2; + int i; + + ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev)); + + ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx)); + ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx)); + + ut_assertok(dma_enable(&dma_tx)); + ut_assertok(dma_enable(&dma_rx)); + + memset(dst_buf, 0, len); + for (i = 0; i < len; i++) + src_buf[i] = i; + meta1 = 0xADADDEAD; + meta2 = 0; + dst_ptr = NULL; + + ut_assertok(dma_prepare_rcv_buf(&dma_tx, dst_buf, len)); + + ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1)); + + ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2)); + ut_asserteq(0xADADDEAD, meta2); + ut_asserteq_ptr(dst_buf, dst_ptr); + + ut_assertok(dma_disable(&dma_tx)); + ut_assertok(dma_disable(&dma_rx)); + + ut_assertok(dma_free(&dma_tx)); + ut_assertok(dma_free(&dma_rx)); + ut_assertok(memcmp(src_buf, dst_buf, len)); + + return 0; +} +DM_TEST(dm_test_dma_rx, DM_TESTF_SCAN_FDT); diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c new file mode 100644 index 0000000000..09ec38b4f3 --- /dev/null +++ b/test/dm/hwspinlock.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Test that hwspinlock driver functions are called */ +static int dm_test_hwspinlock_base(struct unit_test_state *uts) +{ + struct sandbox_state *state = state_get_current(); + struct hwspinlock hws; + + ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev)); + ut_assertnonnull(hws.dev); + ut_asserteq(false, state->hwspinlock); + + hws.id = 0; + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_asserteq(true, state->hwspinlock); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_asserteq(false, state->hwspinlock); + + ut_assertok(hwspinlock_lock_timeout(&hws, 1)); + ut_assertok(!hwspinlock_lock_timeout(&hws, 1)); + + ut_assertok(hwspinlock_unlock(&hws)); + ut_assertok(!hwspinlock_unlock(&hws)); + + return 0; +} + +DM_TEST(dm_test_hwspinlock_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/i2c.c b/test/dm/i2c.c index 772f62b265..cbbd4aa29a 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -35,7 +35,7 @@ static int dm_test_i2c_find(struct unit_test_state *uts) */ ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); ut_assertok(dm_i2c_probe(bus, chip, 0, &dev)); - ut_asserteq(-ENODEV, dm_i2c_probe(bus, no_chip, 0, &dev)); + ut_asserteq(-ENOENT, dm_i2c_probe(bus, no_chip, 0, &dev)); ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)); return 0; diff --git a/test/dm/i2s.c b/test/dm/i2s.c new file mode 100644 index 0000000000..49ebc3523c --- /dev/null +++ b/test/dm/i2s.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +/* Basic test of the i2s codec uclass */ +static int dm_test_i2s(struct unit_test_state *uts) +{ + struct udevice *dev; + u8 data[3]; + + /* check probe success */ + ut_assertok(uclass_first_device_err(UCLASS_I2S, &dev)); + data[0] = 1; + data[1] = 4; + data[2] = 6; + ut_assertok(i2s_tx_data(dev, data, ARRAY_SIZE(data))); + ut_asserteq(11, sandbox_get_i2s_sum(dev)); + ut_assertok(i2s_tx_data(dev, data, 1)); + ut_asserteq(12, sandbox_get_i2s_sum(dev)); + + return 0; +} +DM_TEST(dm_test_i2s, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/misc.c b/test/dm/misc.c index 61279665ef..4d4232adf1 100644 --- a/test/dm/misc.c +++ b/test/dm/misc.c @@ -21,9 +21,9 @@ static int dm_test_misc(struct unit_test_state *uts) ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "misc-test", &dev)); /* Read / write tests */ - ut_assertok(misc_write(dev, 0, "TEST", 4)); - ut_assertok(misc_write(dev, 4, "WRITE", 5)); - ut_assertok(misc_read(dev, 0, buf, 9)); + ut_asserteq(4, misc_write(dev, 0, "TEST", 4)); + ut_asserteq(5, misc_write(dev, 4, "WRITE", 5)); + ut_asserteq(9, misc_read(dev, 0, buf, 9)); ut_assertok(memcmp(buf, "TESTWRITE", 9)); diff --git a/test/dm/pci.c b/test/dm/pci.c index a1dedd84a7..a1febd54b7 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -211,6 +211,16 @@ static int dm_test_pci_cap(struct unit_test_state *uts) cap = dm_pci_find_capability(swap, PCI_CAP_ID_PCIX); ut_asserteq(0, cap); + /* look up PCI_CAP_ID_MSIX starting from PCI_CAP_ID_PM_OFFSET */ + cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_PM_OFFSET, + PCI_CAP_ID_MSIX); + ut_asserteq(PCI_CAP_ID_MSIX_OFFSET, cap); + + /* look up PCI_CAP_ID_VNDR starting from PCI_CAP_ID_EXP_OFFSET */ + cap = dm_pci_find_next_capability(swap, PCI_CAP_ID_EXP_OFFSET, + PCI_CAP_ID_VNDR); + ut_asserteq(0, cap); + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); @@ -222,6 +232,16 @@ static int dm_test_pci_cap(struct unit_test_state *uts) cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_SRIOV); ut_asserteq(0, cap); + /* look up PCI_EXT_CAP_ID_DSN starting from PCI_EXT_CAP_ID_ERR_OFFSET */ + cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_ERR_OFFSET, + PCI_EXT_CAP_ID_DSN); + ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap); + + /* look up PCI_EXT_CAP_ID_RCRB starting from PCI_EXT_CAP_ID_VC_OFFSET */ + cap = dm_pci_find_next_ext_capability(swap, PCI_EXT_CAP_ID_VC_OFFSET, + PCI_EXT_CAP_ID_RCRB); + ut_asserteq(0, cap); + return 0; } DM_TEST(dm_test_pci_cap, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/regmap.c b/test/dm/regmap.c index d4b86b3b03..9a70c159dd 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -25,7 +25,7 @@ static int dm_test_regmap_base(struct unit_test_state *uts) ut_assertok_ptr(map); ut_asserteq(1, map->range_count); ut_asserteq(0x10, map->ranges[0].start); - ut_asserteq(4, map->ranges[0].size); + ut_asserteq(16, map->ranges[0].size); ut_asserteq(0x10, map_to_sysmem(regmap_get_range(map, 0))); ut_assertok(uclass_get_device(UCLASS_SYSCON, 1, &dev)); @@ -116,3 +116,57 @@ static int dm_test_regmap_rw(struct unit_test_state *uts) } DM_TEST(dm_test_regmap_rw, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Get/Set test */ +static int dm_test_regmap_getset(struct unit_test_state *uts) +{ + struct udevice *dev; + struct regmap *map; + uint reg; + struct layout { + u32 val0; + u32 val1; + u32 val2; + u32 val3; + }; + + ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev)); + map = syscon_get_regmap(dev); + ut_assertok_ptr(map); + + regmap_set(map, struct layout, val0, 0xcacafafa); + regmap_set(map, struct layout, val3, 0x55aa2211); + + ut_assertok(regmap_get(map, struct layout, val0, ®)); + ut_assertok(regmap_get(map, struct layout, val3, ®)); + + return 0; +} + +DM_TEST(dm_test_regmap_getset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Read polling test */ +static int dm_test_regmap_poll(struct unit_test_state *uts) +{ + struct udevice *dev; + struct regmap *map; + uint reg; + unsigned long start; + + ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev)); + map = syscon_get_regmap(dev); + ut_assertok_ptr(map); + + start = get_timer(0); + + ut_asserteq(-ETIMEDOUT, + regmap_read_poll_timeout(map, 0, reg, + (reg == 0xcacafafa), + 1, 5 * CONFIG_SYS_HZ)); + + ut_assert(get_timer(start) > (5 * CONFIG_SYS_HZ)); + + return 0; +} + +DM_TEST(dm_test_regmap_poll, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/rtc.c b/test/dm/rtc.c index e2bc648fdc..7188742764 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -60,7 +61,7 @@ static int dm_test_rtc_set_get(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); ut_assertok(dm_rtc_get(dev, &now)); - ut_assertok(device_find_first_child(dev, &emul)); + ut_assertok(i2c_emul_find(dev, &emul)); ut_assert(emul != NULL); /* Tell the RTC to go into manual mode */ @@ -125,7 +126,7 @@ static int dm_test_rtc_reset(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_RTC, 0, &dev)); ut_assertok(dm_rtc_get(dev, &now)); - ut_assertok(device_find_first_child(dev, &emul)); + ut_assertok(i2c_emul_find(dev, &emul)); ut_assert(emul != NULL); old_base_time = sandbox_i2c_rtc_get_set_base_time(emul, 0); @@ -154,9 +155,9 @@ static int dm_test_rtc_dual(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_RTC, 1, &dev2)); ut_assertok(dm_rtc_get(dev2, &now2)); - ut_assertok(device_find_first_child(dev1, &emul1)); + ut_assertok(i2c_emul_find(dev1, &emul1)); ut_assert(emul1 != NULL); - ut_assertok(device_find_first_child(dev2, &emul2)); + ut_assertok(i2c_emul_find(dev2, &emul2)); ut_assert(emul2 != NULL); offset = sandbox_i2c_rtc_set_offset(emul1, false, -1); diff --git a/test/dm/serial.c b/test/dm/serial.c index 5c603e1f42..19a15d5d95 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -11,7 +11,9 @@ static int dm_test_serial(struct unit_test_state *uts) { + struct serial_device_info info_serial = {0}; struct udevice *dev_serial; + uint value_serial; ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial", &dev_serial)); @@ -22,6 +24,16 @@ static int dm_test_serial(struct unit_test_state *uts) * sandbox_serial driver */ ut_assertok(serial_setconfig(SERIAL_DEFAULT_CONFIG)); + ut_assertok(serial_getconfig(&value_serial)); + ut_assert(value_serial == SERIAL_DEFAULT_CONFIG); + ut_assertok(serial_getinfo(&info_serial)); + ut_assert(info_serial.type == SERIAL_CHIP_UNKNOWN); + ut_assert(info_serial.addr == SERIAL_DEFAULT_ADDRESS); + /* + * test with a parameter which is NULL pointer + */ + ut_asserteq(-EINVAL, serial_getconfig(NULL)); + ut_asserteq(-EINVAL, serial_getinfo(NULL)); /* * test with a serial config which is not supported by * sandbox_serial driver: test with wrong parity diff --git a/test/dm/sf.c b/test/dm/sf.c index 35241b9f57..3788d59052 100644 --- a/test/dm/sf.c +++ b/test/dm/sf.c @@ -6,15 +6,66 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include -/* Test that sandbox SPI flash works correctly */ +/* Simple test of sandbox SPI flash */ static int dm_test_spi_flash(struct unit_test_state *uts) +{ + struct udevice *dev, *emul; + int full_size = 0x200000; + int size = 0x10000; + u8 *src, *dst; + int i; + + src = map_sysmem(0x20000, full_size); + ut_assertok(os_write_file("spi.bin", src, full_size)); + ut_assertok(uclass_first_device_err(UCLASS_SPI_FLASH, &dev)); + + dst = map_sysmem(0x20000 + full_size, full_size); + ut_assertok(spi_flash_read_dm(dev, 0, size, dst)); + ut_assertok(memcmp(src, dst, size)); + + /* Erase */ + ut_assertok(spi_flash_erase_dm(dev, 0, size)); + ut_assertok(spi_flash_read_dm(dev, 0, size, dst)); + for (i = 0; i < size; i++) + ut_asserteq(dst[i], 0xff); + + /* Write some new data */ + for (i = 0; i < size; i++) + src[i] = i; + ut_assertok(spi_flash_write_dm(dev, 0, size, src)); + ut_assertok(spi_flash_read_dm(dev, 0, size, dst)); + ut_assertok(memcmp(src, dst, size)); + + /* Try the write-protect stuff */ + ut_assertok(uclass_first_device_err(UCLASS_SPI_EMUL, &emul)); + ut_asserteq(0, spl_flash_get_sw_write_prot(dev)); + sandbox_sf_set_block_protect(emul, 1); + ut_asserteq(1, spl_flash_get_sw_write_prot(dev)); + sandbox_sf_set_block_protect(emul, 0); + ut_asserteq(0, spl_flash_get_sw_write_prot(dev)); + + /* + * Since we are about to destroy all devices, we must tell sandbox + * to forget the emulation device + */ + sandbox_sf_unbind_emul(state_get_current(), 0, 0); + + return 0; +} +DM_TEST(dm_test_spi_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Functional test that sandbox SPI flash works correctly */ +static int dm_test_spi_flash_func(struct unit_test_state *uts) { /* * Create an empty test file and run the SPI flash tests. This is a @@ -28,7 +79,7 @@ static int dm_test_spi_flash(struct unit_test_state *uts) * benefit is worth the extra complexity. */ ut_asserteq(0, run_command_list( - "sb save hostfs - 0 spi.bin 200000;" + "host save hostfs - 0 spi.bin 200000;" "sf probe;" "sf test 0 10000", -1, 0)); /* @@ -39,4 +90,4 @@ static int dm_test_spi_flash(struct unit_test_state *uts) return 0; } -DM_TEST(dm_test_spi_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +DM_TEST(dm_test_spi_flash_func, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/sound.c b/test/dm/sound.c new file mode 100644 index 0000000000..7d0b36e7a5 --- /dev/null +++ b/test/dm/sound.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +/* Basic test of the sound codec uclass */ +static int dm_test_sound(struct unit_test_state *uts) +{ + struct sound_uc_priv *uc_priv; + struct udevice *dev; + + /* check probe success */ + ut_assertok(uclass_first_device_err(UCLASS_SOUND, &dev)); + uc_priv = dev_get_uclass_priv(dev); + ut_asserteq_str("audio-codec", uc_priv->codec->name); + ut_asserteq_str("i2s", uc_priv->i2s->name); + ut_asserteq(0, sandbox_get_setup_called(dev)); + + ut_assertok(sound_beep(dev, 1, 100)); + ut_asserteq(4560, sandbox_get_sound_sum(dev)); + ut_assertok(sound_beep(dev, 1, 100)); + ut_asserteq(9120, sandbox_get_sound_sum(dev)); + + return 0; +} +DM_TEST(dm_test_sound, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/syscon.c b/test/dm/syscon.c index 77c79285d9..a294dda02e 100644 --- a/test/dm/syscon.c +++ b/test/dm/syscon.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -43,3 +44,31 @@ static int dm_test_syscon_by_driver_data(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_syscon_by_driver_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test system controller by phandle */ +static int dm_test_syscon_by_phandle(struct unit_test_state *uts) +{ + struct udevice *dev; + struct regmap *map; + + ut_assertok(uclass_get_device_by_name(UCLASS_TEST_PROBE, "test4", + &dev)); + + ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev, "first-syscon")); + map = syscon_regmap_lookup_by_phandle(dev, "first-syscon"); + ut_assert(map); + ut_assert(!IS_ERR(map)); + ut_asserteq(1, map->range_count); + + ut_assertok_ptr(syscon_regmap_lookup_by_phandle(dev, + "second-sys-ctrl")); + map = syscon_regmap_lookup_by_phandle(dev, "second-sys-ctrl"); + ut_assert(map); + ut_assert(!IS_ERR(map)); + ut_asserteq(4, map->range_count); + + ut_assert(IS_ERR(syscon_regmap_lookup_by_phandle(dev, "not-present"))); + + return 0; +} +DM_TEST(dm_test_syscon_by_phandle, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index e1b7bf5277..5b2358ef67 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -102,10 +102,10 @@ static int dm_test_sysreset_get_last(struct unit_test_state *uts) /* Device 2 is the cold sysreset device */ ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev)); - ut_asserteq(SYSRESET_COLD, sysreset_get_last(dev)); + ut_asserteq(SYSRESET_POWER, sysreset_get_last(dev)); /* This is device 0, the non-DT one */ - ut_asserteq(SYSRESET_COLD, sysreset_get_last_walk()); + ut_asserteq(SYSRESET_POWER, sysreset_get_last_walk()); return 0; } diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 79b1f1de45..984b80c02c 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -55,10 +55,13 @@ static int testfdt_drv_probe(struct udevice *dev) /* * If this device is on a bus, the uclass_flag will be set before - * calling this function. This is used by - * dm_test_bus_child_pre_probe_uclass(). + * calling this function. In the meantime the uclass_postp is + * initlized to a value -1. These are used respectively by + * dm_test_bus_child_pre_probe_uclass() and + * dm_test_bus_child_post_probe_uclass(). */ priv->uclass_total += priv->uclass_flag; + priv->uclass_postp = -1; return 0; } @@ -84,6 +87,25 @@ U_BOOT_DRIVER(testfdt_drv) = { .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), }; +static const struct udevice_id testfdt1_ids[] = { + { + .compatible = "denx,u-boot-fdt-test1", + .data = DM_TEST_TYPE_FIRST }, + { } +}; + +U_BOOT_DRIVER(testfdt1_drv) = { + .name = "testfdt1_drv", + .of_match = testfdt1_ids, + .id = UCLASS_TEST_FDT, + .ofdata_to_platdata = testfdt_ofdata_to_platdata, + .probe = testfdt_drv_probe, + .ops = &test_ops, + .priv_auto_alloc_size = sizeof(struct dm_test_priv), + .platdata_auto_alloc_size = sizeof(struct dm_test_pdata), + .flags = DM_FLAG_PRE_RELOC, +}; + /* From here is the testfdt uclass code */ int testfdt_ping(struct udevice *dev, int pingval, int *pingret) { @@ -168,7 +190,7 @@ int dm_check_devices(struct unit_test_state *uts, int num_devices) /* Test that FDT-based binding works correctly */ static int dm_test_fdt(struct unit_test_state *uts) { - const int num_devices = 7; + const int num_devices = 8; struct udevice *dev; struct uclass *uc; int ret; @@ -208,8 +230,12 @@ static int dm_test_fdt_pre_reloc(struct unit_test_state *uts) ret = uclass_get(UCLASS_TEST_FDT, &uc); ut_assert(!ret); - /* These is only one pre-reloc device */ - ut_asserteq(1, list_count_items(&uc->dev_head)); + /* + * These are 2 pre-reloc devices: + * one with "u-boot,dm-pre-reloc" property (a-test node), and the other + * one whose driver marked with DM_FLAG_PRE_RELOC flag (h-test node). + */ + ut_asserteq(2, list_count_items(&uc->dev_head)); return 0; } @@ -464,7 +490,6 @@ static int dm_test_fdt_translation(struct unit_test_state *uts) } DM_TEST(dm_test_fdt_translation, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -/* Test devfdt_remap_addr_index() */ static int dm_test_fdt_remap_addr_flat(struct unit_test_state *uts) { struct udevice *dev; @@ -485,7 +510,46 @@ static int dm_test_fdt_remap_addr_flat(struct unit_test_state *uts) DM_TEST(dm_test_fdt_remap_addr_flat, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT | DM_TESTF_FLAT_TREE); -/* Test dev_remap_addr_index() */ +static int dm_test_fdt_remap_addr_index_flat(struct unit_test_state *uts) +{ + struct udevice *dev; + fdt_addr_t addr; + void *paddr; + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev)); + + addr = devfdt_get_addr_index(dev, 0); + ut_asserteq(0x8000, addr); + + paddr = map_physmem(addr, 0, MAP_NOCACHE); + ut_assertnonnull(paddr); + ut_asserteq_ptr(paddr, devfdt_remap_addr_index(dev, 0)); + + return 0; +} +DM_TEST(dm_test_fdt_remap_addr_index_flat, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT | DM_TESTF_FLAT_TREE); + +static int dm_test_fdt_remap_addr_name_flat(struct unit_test_state *uts) +{ + struct udevice *dev; + fdt_addr_t addr; + void *paddr; + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev)); + + addr = devfdt_get_addr_name(dev, "sandbox-dummy-0"); + ut_asserteq(0x8000, addr); + + paddr = map_physmem(addr, 0, MAP_NOCACHE); + ut_assertnonnull(paddr); + ut_asserteq_ptr(paddr, devfdt_remap_addr_name(dev, "sandbox-dummy-0")); + + return 0; +} +DM_TEST(dm_test_fdt_remap_addr_name_flat, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT | DM_TESTF_FLAT_TREE); + static int dm_test_fdt_remap_addr_live(struct unit_test_state *uts) { struct udevice *dev; @@ -506,6 +570,46 @@ static int dm_test_fdt_remap_addr_live(struct unit_test_state *uts) DM_TEST(dm_test_fdt_remap_addr_live, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +static int dm_test_fdt_remap_addr_index_live(struct unit_test_state *uts) +{ + struct udevice *dev; + fdt_addr_t addr; + void *paddr; + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev)); + + addr = dev_read_addr_index(dev, 0); + ut_asserteq(0x8000, addr); + + paddr = map_physmem(addr, 0, MAP_NOCACHE); + ut_assertnonnull(paddr); + ut_asserteq_ptr(paddr, dev_remap_addr_index(dev, 0)); + + return 0; +} +DM_TEST(dm_test_fdt_remap_addr_index_live, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +static int dm_test_fdt_remap_addr_name_live(struct unit_test_state *uts) +{ + struct udevice *dev; + fdt_addr_t addr; + void *paddr; + + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, true, &dev)); + + addr = dev_read_addr_name(dev, "sandbox-dummy-0"); + ut_asserteq(0x8000, addr); + + paddr = map_physmem(addr, 0, MAP_NOCACHE); + ut_assertnonnull(paddr); + ut_asserteq_ptr(paddr, dev_remap_addr_name(dev, "sandbox-dummy-0")); + + return 0; +} +DM_TEST(dm_test_fdt_remap_addr_name_live, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + static int dm_test_fdt_livetree_writing(struct unit_test_state *uts) { struct udevice *dev; @@ -585,3 +689,85 @@ static int dm_test_fdt_disable_enable_by_path(struct unit_test_state *uts) } DM_TEST(dm_test_fdt_disable_enable_by_path, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test a few uclass phandle functions */ +static int dm_test_fdt_phandle(struct unit_test_state *uts) +{ + struct udevice *back, *dev, *dev2; + + ut_assertok(uclass_find_first_device(UCLASS_PANEL_BACKLIGHT, &back)); + ut_asserteq(-ENOENT, uclass_find_device_by_phandle(UCLASS_REGULATOR, + back, "missing", &dev)); + ut_assertok(uclass_find_device_by_phandle(UCLASS_REGULATOR, back, + "power-supply", &dev)); + ut_asserteq(0, device_active(dev)); + ut_asserteq_str("ldo1", dev->name); + ut_assertok(uclass_get_device_by_phandle(UCLASS_REGULATOR, back, + "power-supply", &dev2)); + ut_asserteq_ptr(dev, dev2); + + return 0; +} +DM_TEST(dm_test_fdt_phandle, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test device_find_first_child_by_uclass() */ +static int dm_test_first_child(struct unit_test_state *uts) +{ + struct udevice *i2c, *dev, *dev2; + + ut_assertok(uclass_first_device_err(UCLASS_I2C, &i2c)); + ut_assertok(device_find_first_child_by_uclass(i2c, UCLASS_RTC, &dev)); + ut_asserteq_str("rtc@43", dev->name); + ut_assertok(device_find_child_by_name(i2c, "rtc@43", &dev2)); + ut_asserteq_ptr(dev, dev2); + ut_assertok(device_find_child_by_name(i2c, "rtc@61", &dev2)); + ut_asserteq_str("rtc@61", dev2->name); + + ut_assertok(device_find_first_child_by_uclass(i2c, UCLASS_I2C_EEPROM, + &dev)); + ut_asserteq_str("eeprom@2c", dev->name); + ut_assertok(device_find_child_by_name(i2c, "eeprom@2c", &dev2)); + ut_asserteq_ptr(dev, dev2); + + ut_asserteq(-ENODEV, device_find_first_child_by_uclass(i2c, + UCLASS_VIDEO, &dev)); + ut_asserteq(-ENODEV, device_find_child_by_name(i2c, "missing", &dev)); + + return 0; +} +DM_TEST(dm_test_first_child, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test integer functions in dm_read_...() */ +static int dm_test_read_int(struct unit_test_state *uts) +{ + struct udevice *dev; + u32 val32; + s32 sval; + uint val; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_FDT, &dev)); + ut_asserteq_str("a-test", dev->name); + ut_assertok(dev_read_u32(dev, "int-value", &val32)); + ut_asserteq(1234, val32); + + ut_asserteq(-EINVAL, dev_read_u32(dev, "missing", &val32)); + ut_asserteq(6, dev_read_u32_default(dev, "missing", 6)); + + ut_asserteq(1234, dev_read_u32_default(dev, "int-value", 6)); + ut_asserteq(1234, val32); + + ut_asserteq(-EINVAL, dev_read_s32(dev, "missing", &sval)); + ut_asserteq(6, dev_read_s32_default(dev, "missing", 6)); + + ut_asserteq(-1234, dev_read_s32_default(dev, "uint-value", 6)); + ut_assertok(dev_read_s32(dev, "uint-value", &sval)); + ut_asserteq(-1234, sval); + + val = 0; + ut_asserteq(-EINVAL, dev_read_u32u(dev, "missing", &val)); + ut_assertok(dev_read_u32u(dev, "uint-value", &val)); + ut_asserteq(-1234, val); + + return 0; +} +DM_TEST(dm_test_read_int, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/dm/video.c b/test/dm/video.c index 7def338058..6be5defc53 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -178,12 +178,12 @@ static int dm_test_video_ansi(struct unit_test_state *uts) /* test set-cursor: [%d;%df */ vidconsole_put_string(con, "abc"ANSI_ESC"[2;2fab"ANSI_ESC"[4;4fcd"); - ut_asserteq(142, compress_frame_buffer(dev)); + ut_asserteq(143, compress_frame_buffer(dev)); /* test colors (30-37 fg color, 40-47 bg color) */ vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */ vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */ - ut_asserteq(265, compress_frame_buffer(dev)); + ut_asserteq(272, compress_frame_buffer(dev)); return 0; } @@ -335,7 +335,7 @@ static int dm_test_video_truetype(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(12619, compress_frame_buffer(dev)); + ut_asserteq(12237, compress_frame_buffer(dev)); return 0; } @@ -356,7 +356,7 @@ static int dm_test_video_truetype_scroll(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(33849, compress_frame_buffer(dev)); + ut_asserteq(35030, compress_frame_buffer(dev)); return 0; } @@ -377,7 +377,7 @@ static int dm_test_video_truetype_bs(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); vidconsole_put_string(con, test_string); - ut_asserteq(34871, compress_frame_buffer(dev)); + ut_asserteq(29018, compress_frame_buffer(dev)); return 0; } diff --git a/test/dm/virtio.c b/test/dm/virtio.c new file mode 100644 index 0000000000..4b317d2ec3 --- /dev/null +++ b/test/dm/virtio.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Basic test of the virtio uclass */ +static int dm_test_virtio_base(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + u8 status; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + + /* check the child virtio-blk device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + ut_assertok(strcmp(dev->name, "virtio-blk#0")); + + /* check driver status */ + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(VIRTIO_CONFIG_S_ACKNOWLEDGE, status); + + return 0; +} +DM_TEST(dm_test_virtio_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test all of the virtio uclass ops */ +static int dm_test_virtio_all_ops(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + struct virtio_dev_priv *uc_priv; + uint offset = 0, len = 0, nvqs = 1; + void *buffer = NULL; + u8 status; + u32 counter; + u64 features; + struct virtqueue *vqs[2]; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + + /* check the child virtio-blk device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + + /* + * fake the virtio device probe by filling in uc_priv->vdev + * which is used by virtio_find_vqs/virtio_del_vqs. + */ + uc_priv = dev_get_uclass_priv(bus); + uc_priv->vdev = dev; + + /* test virtio_xxx APIs */ + ut_assertok(virtio_get_config(dev, offset, buffer, len)); + ut_assertok(virtio_set_config(dev, offset, buffer, len)); + ut_asserteq(-ENOSYS, virtio_generation(dev, &counter)); + ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(VIRTIO_CONFIG_S_DRIVER_OK, status); + ut_assertok(virtio_reset(dev)); + ut_assertok(virtio_get_status(dev, &status)); + ut_asserteq(0, status); + ut_assertok(virtio_get_features(dev, &features)); + ut_asserteq(VIRTIO_F_VERSION_1, features); + ut_assertok(virtio_set_features(dev)); + ut_assertok(virtio_find_vqs(dev, nvqs, vqs)); + ut_assertok(virtio_del_vqs(dev)); + ut_assertok(virtio_notify(dev, vqs[0])); + + return 0; +} +DM_TEST(dm_test_virtio_all_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test of the virtio driver that does not have required driver ops */ +static int dm_test_virtio_missing_ops(struct unit_test_state *uts) +{ + struct udevice *bus; + + /* find the virtio device */ + ut_assertok(uclass_find_device(UCLASS_VIRTIO, 1, &bus)); + + /* + * Probe the device should fail with error -ENOENT. + * See ops check in virtio_uclass_pre_probe(). + */ + ut_asserteq(-ENOENT, device_probe(bus)); + + return 0; +} +DM_TEST(dm_test_virtio_missing_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test removal of virtio device driver */ +static int dm_test_virtio_remove(struct unit_test_state *uts) +{ + struct udevice *bus, *dev; + + /* check probe success */ + ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus)); + + /* check the child virtio-blk device is bound */ + ut_assertok(device_find_first_child(bus, &dev)); + + /* set driver status to VIRTIO_CONFIG_S_DRIVER_OK */ + ut_assertok(virtio_set_status(dev, VIRTIO_CONFIG_S_DRIVER_OK)); + + /* check the device can be successfully removed */ + dev->flags |= DM_FLAG_ACTIVATED; + ut_assertok(device_remove(bus, DM_REMOVE_ACTIVE_ALL)); + + return 0; +} +DM_TEST(dm_test_virtio_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh index 86308cfe2d..721af71d44 100755 --- a/test/fs/fs-test.sh +++ b/test/fs/fs-test.sh @@ -194,7 +194,7 @@ function test_image() { ;; sb) - PREFIX="sb " + PREFIX="host " WRITE="save" SUFFIX="fs -" ;; @@ -217,11 +217,11 @@ function test_image() { # In u-boot commands, stands for host or hostfs # hostfs maps to the host fs. - # host maps to the "sb bind" that we do + # host maps to the "host bind" that we do $UBOOT << EOF sb=$5 -setenv bind 'if test "\$sb" != sb; then sb bind 0 "$1"; fi' +setenv bind 'if test "\$sb" != sb; then host bind 0 "$1"; fi' run bind # Test Case 1 - ls ${PREFIX}ls host${SUFFIX} $6 @@ -229,7 +229,7 @@ ${PREFIX}ls host${SUFFIX} $6 ${PREFIX}ls host${SUFFIX} invalid_d # # We want ${PREFIX}size host 0:0 $3 for host commands and -# sb size hostfs - $3 for hostfs commands. +# host size hostfs - $3 for hostfs commands. # 1MB is 0x0010 0000 # Test Case 2a - size of small file ${PREFIX}size host${SUFFIX} ${FPATH}$FILE_SMALL @@ -575,7 +575,7 @@ TOTAL_PASS=0 # In each loop, for a given file system image, we test both the # fs command, like load/size/write, the file system specific command -# like: ext4load/ext4size/ext4write and the sb load/ls/save commands. +# like: ext4load/ext4size/ext4write and the host load/ls/save commands. for fs in ext4 fat16 fat32; do echo "Creating $fs image if not already present." @@ -583,11 +583,11 @@ for fs in ext4 fat16 fat32; do MD5_FILE_FS="${MD5_FILE}.${fs}" create_image $IMAGE $fs - # sb commands test + # host commands test echo "Creating files in $fs image if not already present." create_files $IMAGE $MD5_FILE_FS - # Lets mount the image and test sb hostfs commands + # Lets mount the image and test host hostfs commands mkdir -p "$MOUNT_DIR" case "$fs" in fat*) diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c index e8b3e566e0..567b57686a 100644 --- a/test/lib/hexdump.c +++ b/test/lib/hexdump.c @@ -11,8 +11,6 @@ static int lib_test_hex_to_bin(struct unit_test_state *uts) { - return 0; - ut_asserteq(0x0, hex_to_bin('0')); ut_asserteq(0x1, hex_to_bin('1')); ut_asserteq(0x2, hex_to_bin('2')); @@ -30,6 +28,8 @@ static int lib_test_hex_to_bin(struct unit_test_state *uts) ut_asserteq(0xe, hex_to_bin('e')); ut_asserteq(0xf, hex_to_bin('f')); ut_asserteq(-1, hex_to_bin('g')); + + return 0; } DM_TEST(lib_test_hex_to_bin, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig index 13c85428cb..a4f154415d 100644 --- a/test/overlay/Kconfig +++ b/test/overlay/Kconfig @@ -1,11 +1,10 @@ config UT_OVERLAY bool "Enable Device Tree Overlays Unit Tests" - depends on OF_LIBFDT_OVERLAY - depends on UNIT_TEST + depends on UNIT_TEST && OF_CONTROL + default y + select OF_LIBFDT_OVERLAY help This enables the 'ut overlay' command which runs a series of unit tests on the fdt overlay code. If all is well then all tests pass although there will be a few messages printed along the way. - Be warned that it requires an out-of-tree dtc compiler with patches - to support the DT overlays, otherwise it will fail. diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c index 3d34c8ab53..fc2491d0b4 100644 --- a/test/overlay/cmd_ut_overlay.c +++ b/test/overlay/cmd_ut_overlay.c @@ -23,6 +23,8 @@ extern u32 __dtb_test_fdt_base_begin; extern u32 __dtb_test_fdt_overlay_begin; extern u32 __dtb_test_fdt_overlay_stacked_begin; +static void *fdt; + static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path, const char *name, int index, u32 *out) @@ -67,7 +69,6 @@ static int fdt_getprop_str(void *fdt, const char *path, const char *name, static int fdt_overlay_change_int_property(struct unit_test_state *uts) { - void *fdt = uts->priv; u32 val = 0; ut_assertok(ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property", @@ -80,7 +81,6 @@ OVERLAY_TEST(fdt_overlay_change_int_property, 0); static int fdt_overlay_change_str_property(struct unit_test_state *uts) { - void *fdt = uts->priv; const char *val = NULL; ut_assertok(fdt_getprop_str(fdt, "/test-node", "test-str-property", @@ -93,7 +93,6 @@ OVERLAY_TEST(fdt_overlay_change_str_property, 0); static int fdt_overlay_add_str_property(struct unit_test_state *uts) { - void *fdt = uts->priv; const char *val = NULL; ut_assertok(fdt_getprop_str(fdt, "/test-node", "test-str-property-2", @@ -106,7 +105,6 @@ OVERLAY_TEST(fdt_overlay_add_str_property, 0); static int fdt_overlay_add_node_by_phandle(struct unit_test_state *uts) { - void *fdt = uts->priv; int off; off = fdt_path_offset(fdt, "/test-node/new-node"); @@ -120,7 +118,6 @@ OVERLAY_TEST(fdt_overlay_add_node_by_phandle, 0); static int fdt_overlay_add_node_by_path(struct unit_test_state *uts) { - void *fdt = uts->priv; int off; off = fdt_path_offset(fdt, "/new-node"); @@ -134,7 +131,6 @@ OVERLAY_TEST(fdt_overlay_add_node_by_path, 0); static int fdt_overlay_add_subnode_property(struct unit_test_state *uts) { - void *fdt = uts->priv; int off; off = fdt_path_offset(fdt, "/test-node/sub-test-node"); @@ -150,7 +146,6 @@ OVERLAY_TEST(fdt_overlay_add_subnode_property, 0); static int fdt_overlay_local_phandle(struct unit_test_state *uts) { uint32_t local_phandle; - void *fdt = uts->priv; u32 val = 0; int off; @@ -175,7 +170,6 @@ OVERLAY_TEST(fdt_overlay_local_phandle, 0); static int fdt_overlay_local_phandles(struct unit_test_state *uts) { uint32_t local_phandle, test_phandle; - void *fdt = uts->priv; u32 val = 0; int off; @@ -205,7 +199,6 @@ OVERLAY_TEST(fdt_overlay_local_phandles, 0); static int fdt_overlay_stacked(struct unit_test_state *uts) { - void *fdt = uts->priv; u32 val = 0; ut_assertok(ut_fdt_getprop_u32(fdt, "/new-local-node", @@ -225,7 +218,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) void *fdt_base = &__dtb_test_fdt_base_begin; void *fdt_overlay = &__dtb_test_fdt_overlay_begin; void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin; - void *fdt_base_copy, *fdt_overlay_copy, *fdt_overlay_stacked_copy; + void *fdt_overlay_copy, *fdt_overlay_stacked_copy; int ret = -ENOMEM; uts = calloc(1, sizeof(*uts)); @@ -235,10 +228,9 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ut_assertok(fdt_check_header(fdt_base)); ut_assertok(fdt_check_header(fdt_overlay)); - fdt_base_copy = malloc(FDT_COPY_SIZE); - if (!fdt_base_copy) + fdt = malloc(FDT_COPY_SIZE); + if (!fdt) goto err1; - uts->priv = fdt_base_copy; fdt_overlay_copy = malloc(FDT_COPY_SIZE); if (!fdt_overlay_copy) @@ -254,7 +246,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * (and relocate it since the memory might be mapped * read-only) */ - ut_assertok(fdt_open_into(fdt_base, fdt_base_copy, FDT_COPY_SIZE)); + ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); /* * Resize the overlay to 4k so that we have room to operate on @@ -275,10 +267,10 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FDT_COPY_SIZE)); /* Apply the overlay */ - ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_copy)); + ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_copy)); /* Apply the stacked overlay */ - ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_stacked_copy)); + ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_stacked_copy)); ret = cmd_ut_category("overlay", tests, n_ents, argc, argv); @@ -286,9 +278,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) err3: free(fdt_overlay_copy); err2: - free(fdt_base_copy); + free(fdt); err1: - free(uts); - return ret; } diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py index f21b7059ea..dee3fee566 100644 --- a/test/py/tests/test_bind.py +++ b/test/py/tests/test_bind.py @@ -13,7 +13,7 @@ def in_tree(response, name, uclass, drv, depth, last_child): else: leaf = leaf + '`' leaf = leaf + '-- ' + name - line = ' *{:10.10} [0-9]* \[ [ +] \] {:10.10} {}$'.format(uclass, drv,leaf) + line = ' *{:10.10} [0-9]* \[ [ +] \] {:20.20} {}$'.format(uclass, drv, leaf) prog = re.compile(line) for l in lines: if prog.match(l): @@ -28,31 +28,31 @@ def test_bind_unbind_with_node(u_boot_console): response = u_boot_console.run_command("bind /bind-test generic_simple_bus") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False) - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) #Unbind child #1. No error expected and all devices should be there except for bind-test-child1 response = u_boot_console.run_command("unbind /bind-test/bind-test-child1") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert "bind-test-child1" not in tree - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) #bind child #1. No error expected and all devices should be there response = u_boot_console.run_command("bind /bind-test/bind-test-child1 phy_sandbox") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True) - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, False) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, False) #Unbind child #2. No error expected and all devices should be there except for bind-test-child2 response = u_boot_console.run_command("unbind /bind-test/bind-test-child2") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, True) assert "bind-test-child2" not in tree @@ -61,9 +61,9 @@ def test_bind_unbind_with_node(u_boot_console): response = u_boot_console.run_command("bind /bind-test/bind-test-child2 generic_simple_bus") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False) - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) #Unbind parent. No error expected. All devices should be removed and unbound response = u_boot_console.run_command("unbind /bind-test") @@ -89,9 +89,9 @@ def test_bind_unbind_with_node(u_boot_console): response = u_boot_console.run_command("bind /bind-test generic_simple_bus") assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test", "simple_bus", "generic_simple", 0, True) + assert in_tree(tree, "bind-test", "simple_bus", "generic_simple_bus", 0, True) assert in_tree(tree, "bind-test-child1", "phy", "phy_sandbox", 1, False) - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) response = u_boot_console.run_command("unbind /bind-test") assert response == '' @@ -138,7 +138,7 @@ def test_bind_unbind_with_uclass(u_boot_console): response = u_boot_console.run_command("unbind simple_bus {}".format(child_of_child2_index)) assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) assert not in_tree(tree, "generic_simple_bus", "simple_bus", "generic_simple_bus", 2, True) child_of_child2_line = get_next_line(tree, "bind-test-child2") assert child_of_child2_line == "" @@ -161,7 +161,7 @@ def test_bind_unbind_with_uclass(u_boot_console): assert response == '' tree = u_boot_console.run_command("dm tree") - assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple", 1, True) + assert in_tree(tree, "bind-test-child2", "simple_bus", "generic_simple_bus", 1, True) child_of_child2_line = get_next_line(tree, "bind-test-child2") assert child_of_child2_line == "" diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py index e0833ffe22..36b35ee536 100644 --- a/test/py/tests/test_efi_selftest.py +++ b/test/py/tests/test_efi_selftest.py @@ -8,12 +8,14 @@ import u_boot_utils @pytest.mark.buildconfigspec('cmd_bootefi_selftest') def test_efi_selftest(u_boot_console): - """ - Run bootefi selftest - """ + """Test the UEFI implementation + :param u_boot_console: U-Boot console + + This function executes all selftests that are not marked as on request. + """ u_boot_console.run_command(cmd='setenv efi_selftest') - u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False) + u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False) m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']) if m != 0: raise Exception('Failures occurred during the EFI selftest') diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index 34696e9767..49d6fea571 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -99,15 +99,15 @@ base_fdt = ''' # then run the 'bootm' command, then save out memory from the places where # we expect 'bootm' to write things. Then quit. base_script = ''' -sb load hostfs 0 %(fit_addr)x %(fit)s +host load hostfs 0 %(fit_addr)x %(fit)s fdt addr %(fit_addr)x bootm start %(fit_addr)x bootm loados -sb save hostfs 0 %(kernel_addr)x %(kernel_out)s %(kernel_size)x -sb save hostfs 0 %(fdt_addr)x %(fdt_out)s %(fdt_size)x -sb save hostfs 0 %(ramdisk_addr)x %(ramdisk_out)s %(ramdisk_size)x -sb save hostfs 0 %(loadables1_addr)x %(loadables1_out)s %(loadables1_size)x -sb save hostfs 0 %(loadables2_addr)x %(loadables2_out)s %(loadables2_size)x +host save hostfs 0 %(kernel_addr)x %(kernel_out)s %(kernel_size)x +host save hostfs 0 %(fdt_addr)x %(fdt_out)s %(fdt_size)x +host save hostfs 0 %(ramdisk_addr)x %(ramdisk_out)s %(ramdisk_size)x +host save hostfs 0 %(loadables1_addr)x %(loadables1_out)s %(loadables1_size)x +host save hostfs 0 %(loadables2_addr)x %(loadables2_out)s %(loadables2_size)x ''' @pytest.mark.boardspec('sandbox') diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py index c067cc9ba3..140ca29ac7 100644 --- a/test/py/tests/test_fs/test_basic.py +++ b/test/py/tests/test_fs/test_basic.py @@ -13,6 +13,7 @@ import re from fstest_defs import * @pytest.mark.boardspec('sandbox') +@pytest.mark.slow class TestFsBasic(object): def test_fs1(self, u_boot_console, fs_obj_basic): """ diff --git a/test/py/tests/test_fs/test_ext.py b/test/py/tests/test_fs/test_ext.py index 38217d08bf..06cad5516d 100644 --- a/test/py/tests/test_fs/test_ext.py +++ b/test/py/tests/test_fs/test_ext.py @@ -13,6 +13,7 @@ import re from fstest_defs import * @pytest.mark.boardspec('sandbox') +@pytest.mark.slow class TestFsExt(object): def test_fs_ext1(self, u_boot_console, fs_obj_ext): """ diff --git a/test/py/tests/test_fs/test_mkdir.py b/test/py/tests/test_fs/test_mkdir.py index d9da97b56b..b3fe11cf3b 100644 --- a/test/py/tests/test_fs/test_mkdir.py +++ b/test/py/tests/test_fs/test_mkdir.py @@ -11,6 +11,7 @@ This test verifies mkdir operation on file system. import pytest @pytest.mark.boardspec('sandbox') +@pytest.mark.slow class TestMkdir(object): def test_mkdir1(self, u_boot_console, fs_obj_mkdir): """ diff --git a/test/py/tests/test_fs/test_unlink.py b/test/py/tests/test_fs/test_unlink.py index 69c1a6e078..2b817468ed 100644 --- a/test/py/tests/test_fs/test_unlink.py +++ b/test/py/tests/test_fs/test_unlink.py @@ -12,6 +12,7 @@ on file system. import pytest @pytest.mark.boardspec('sandbox') +@pytest.mark.slow class TestUnlink(object): def test_unlink1(self, u_boot_console, fs_obj_unlink): """ diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py new file mode 100644 index 0000000000..0ee972298c --- /dev/null +++ b/test/py/tests/test_handoff.py @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2016 Google, Inc + +import pytest + +# Magic number to check that SPL handoff is working +TEST_HANDOFF_MAGIC = 0x14f93c7b + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('spl') +def test_handoff(u_boot_console): + """Test that of-platdata can be generated and used in sandbox""" + cons = u_boot_console + response = cons.run_command('sb handoff') + assert ('SPL handoff magic %x' % TEST_HANDOFF_MAGIC) in response diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py index dd8a09f032..98103ee71a 100644 --- a/test/py/tests/test_ofplatdata.py +++ b/test/py/tests/test_ofplatdata.py @@ -3,11 +3,40 @@ import pytest -OF_PLATDATA_OUTPUT = '' +OF_PLATDATA_OUTPUT = ''' +of-platdata probe: +bool 1 +byte 05 +bytearray 06 00 00 +int 1 +intarray 2 3 4 0 +longbytearray 09 0a 0b 0c 0d 0e 0f 10 11 +string message +stringarray "multi-word" "message" "" +of-platdata probe: +bool 0 +byte 08 +bytearray 01 23 34 +int 3 +intarray 5 0 0 0 +longbytearray 09 00 00 00 00 00 00 00 00 +string message2 +stringarray "another" "multi-word" "message" +of-platdata probe: +bool 0 +byte 00 +bytearray 00 00 00 +int 0 +intarray 0 0 0 0 +longbytearray 00 00 00 00 00 00 00 00 00 +string +stringarray "one" "" "" +''' @pytest.mark.buildconfigspec('spl_of_platdata') def test_ofplatdata(u_boot_console): """Test that of-platdata can be generated and used in sandbox""" cons = u_boot_console + cons.restart_uboot_with_flags(['--show_of_platdata']) output = cons.get_spawn_output().replace('\r', '') assert OF_PLATDATA_OUTPUT in output diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py new file mode 100644 index 0000000000..25394f1faf --- /dev/null +++ b/test/py/tests/test_pinmux.py @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0 + +import pytest +import u_boot_utils + +@pytest.mark.buildconfigspec('cmd_pinmux') +def test_pinmux_usage_1(u_boot_console): + """Test that 'pinmux' command without parameters displays + pinmux usage.""" + output = u_boot_console.run_command('pinmux') + assert 'Usage:' in output + +@pytest.mark.buildconfigspec('cmd_pinmux') +def test_pinmux_usage_2(u_boot_console): + """Test that 'pinmux status' executed without previous "pinmux dev" + command displays pinmux usage.""" + output = u_boot_console.run_command('pinmux status') + assert 'Usage:' in output + +@pytest.mark.buildconfigspec('cmd_pinmux') +@pytest.mark.boardspec('sandbox') +def test_pinmux_status_all(u_boot_console): + """Test that 'pinmux status -a' displays pin's muxing.""" + output = u_boot_console.run_command('pinmux status -a') + assert ('SCL : I2C SCL' in output) + assert ('SDA : I2C SDA' in output) + assert ('TX : Uart TX' in output) + assert ('RX : Uart RX' in output) + assert ('W1 : 1-wire gpio' in output) + +@pytest.mark.buildconfigspec('cmd_pinmux') +@pytest.mark.boardspec('sandbox') +def test_pinmux_list(u_boot_console): + """Test that 'pinmux list' returns the pin-controller list.""" + output = u_boot_console.run_command('pinmux list') + assert 'sandbox_pinctrl' in output + +@pytest.mark.buildconfigspec('cmd_pinmux') +def test_pinmux_dev_bad(u_boot_console): + """Test that 'pinmux dev' returns an error when trying to select a + wrong pin controller.""" + pincontroller = 'bad_pin_controller_name' + output = u_boot_console.run_command('pinmux dev ' + pincontroller) + expected_output = 'Can\'t get the pin-controller: ' + pincontroller + '!' + assert (expected_output in output) + +@pytest.mark.buildconfigspec('cmd_pinmux') +@pytest.mark.boardspec('sandbox') +def test_pinmux_dev(u_boot_console): + """Test that 'pinmux dev' select the wanted pin controller.""" + pincontroller = 'pinctrl' + output = u_boot_console.run_command('pinmux dev ' + pincontroller) + expected_output = 'dev: ' + pincontroller + assert (expected_output in output) + +@pytest.mark.buildconfigspec('cmd_pinmux') +@pytest.mark.boardspec('sandbox') +def test_pinmux_status(u_boot_console): + """Test that 'pinmux status' displays selected pincontroller's pin + muxing descriptions.""" + output = u_boot_console.run_command('pinmux status') + assert ('SCL : I2C SCL' in output) + assert ('SDA : I2C SDA' in output) + assert ('TX : Uart TX' in output) + assert ('RX : Uart RX' in output) + assert ('W1 : 1-wire gpio' in output) diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index e9cbd57fba..4627ceb026 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -74,7 +74,7 @@ def test_vboot(u_boot_console): cons.restart_uboot() with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)): output = cons.run_command_list( - ['sb load hostfs - 100 %stest.fit' % tmpdir, + ['host load hostfs - 100 %stest.fit' % tmpdir, 'fdt addr 100', 'bootm 100']) assert(expect_string in ''.join(output)) @@ -126,7 +126,7 @@ def test_vboot(u_boot_console): handle.write(struct.pack(">I", size)) return struct.unpack(">I", total_size)[0] - def test_with_algo(sha_algo): + def test_with_algo(sha_algo, padding): """Test verified boot with the given hash algorithm. This is the main part of the test code. The same procedure is followed @@ -144,7 +144,7 @@ def test_vboot(u_boot_console): # Build the FIT, but don't sign anything yet cons.log.action('%s: Test FIT with signed images' % sha_algo) - make_fit('sign-images-%s.its' % sha_algo) + make_fit('sign-images-%s%s.its' % (sha_algo , padding)) run_bootm(sha_algo, 'unsigned images', 'dev-', True) # Sign images with our dev keys @@ -155,7 +155,7 @@ def test_vboot(u_boot_console): dtc('sandbox-u-boot.dts') cons.log.action('%s: Test FIT with signed configuration' % sha_algo) - make_fit('sign-configs-%s.its' % sha_algo) + make_fit('sign-configs-%s%s.its' % (sha_algo , padding)) run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True) # Sign images with our dev keys @@ -204,7 +204,7 @@ def test_vboot(u_boot_console): fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign' dtc_args = '-I dts -O dtb -i %s' % tmpdir dtb = '%ssandbox-u-boot.dtb' % tmpdir - sig_node = '/configurations/conf@1/signature@1' + sig_node = '/configurations/conf-1/signature' # Create an RSA key pair public_exponent = 65537 @@ -226,8 +226,10 @@ def test_vboot(u_boot_console): # afterwards. old_dtb = cons.config.dtb cons.config.dtb = dtb - test_with_algo('sha1') - test_with_algo('sha256') + test_with_algo('sha1','') + test_with_algo('sha1','-pss') + test_with_algo('sha256','') + test_with_algo('sha256','-pss') finally: # Go back to the original U-Boot with the correct dtb. cons.config.dtb = old_dtb diff --git a/test/py/tests/vboot/sign-configs-sha1-pss.its b/test/py/tests/vboot/sign-configs-sha1-pss.its new file mode 100644 index 0000000000..72a5637e3a --- /dev/null +++ b/test/py/tests/vboot/sign-configs-sha1-pss.its @@ -0,0 +1,46 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + hash-1 { + algo = "sha1"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + hash-1 { + algo = "sha1"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-configs-sha1.its b/test/py/tests/vboot/sign-configs-sha1.its index db2ed79355..d8bc1fa091 100644 --- a/test/py/tests/vboot/sign-configs-sha1.its +++ b/test/py/tests/vboot/sign-configs-sha1.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,28 +14,28 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - hash@1 { + hash-1 { algo = "sha1"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - hash@1 { + hash-1 { algo = "sha1"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; - signature@1 { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; diff --git a/test/py/tests/vboot/sign-configs-sha256-pss.its b/test/py/tests/vboot/sign-configs-sha256-pss.its new file mode 100644 index 0000000000..7bdcc7e286 --- /dev/null +++ b/test/py/tests/vboot/sign-configs-sha256-pss.its @@ -0,0 +1,46 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + hash-1 { + algo = "sha256"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + hash-1 { + algo = "sha256"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-configs-sha256.its b/test/py/tests/vboot/sign-configs-sha256.its index 1b3432ec14..f5591aad30 100644 --- a/test/py/tests/vboot/sign-configs-sha256.its +++ b/test/py/tests/vboot/sign-configs-sha256.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,28 +14,28 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - hash@1 { + hash-1 { algo = "sha256"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - hash@1 { + hash-1 { algo = "sha256"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; - signature@1 { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; diff --git a/test/py/tests/vboot/sign-images-sha1-pss.its b/test/py/tests/vboot/sign-images-sha1-pss.its new file mode 100644 index 0000000000..ded7ae4f55 --- /dev/null +++ b/test/py/tests/vboot/sign-images-sha1-pss.its @@ -0,0 +1,44 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-images-sha1.its b/test/py/tests/vboot/sign-images-sha1.its index f69326a39b..18c759e9e6 100644 --- a/test/py/tests/vboot/sign-images-sha1.its +++ b/test/py/tests/vboot/sign-images-sha1.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,29 +14,29 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - signature@1 { + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - signature@1 { + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; }; }; }; diff --git a/test/py/tests/vboot/sign-images-sha256-pss.its b/test/py/tests/vboot/sign-images-sha256-pss.its new file mode 100644 index 0000000000..34850cc6c5 --- /dev/null +++ b/test/py/tests/vboot/sign-images-sha256-pss.its @@ -0,0 +1,44 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-images-sha256.its b/test/py/tests/vboot/sign-images-sha256.its index e6aa9fc409..bb0f8ee8a6 100644 --- a/test/py/tests/vboot/sign-images-sha256.its +++ b/test/py/tests/vboot/sign-images-sha256.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,29 +14,29 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - signature@1 { + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - signature@1 { + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; }; }; }; diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py index 778f6d0983..836f5a9e2b 100644 --- a/test/py/u_boot_console_sandbox.py +++ b/test/py/u_boot_console_sandbox.py @@ -24,6 +24,7 @@ class ConsoleSandbox(ConsoleBase): """ super(ConsoleSandbox, self).__init__(log, config, max_fifo_fill=1024) + self.sandbox_flags = [] def get_spawn(self): """Connect to a fresh U-Boot instance. @@ -51,8 +52,25 @@ class ConsoleSandbox(ConsoleBase): '-d', self.config.dtb ] + cmd += self.sandbox_flags return Spawn(cmd, cwd=self.config.source_dir) + def restart_uboot_with_flags(self, flags): + """Run U-Boot with the given command-line flags + + Args: + flags: List of flags to pass, each a string + + Returns: + A u_boot_spawn.Spawn object that is attached to U-Boot. + """ + + try: + self.sandbox_flags = flags + return self.restart_uboot() + finally: + self.sandbox_flags = [] + def kill(self, sig): """Send a specific Unix signal to the sandbox process. diff --git a/test/run b/test/run index fb8ff5da0c..55a6649a9c 100755 --- a/test/run +++ b/test/run @@ -1,6 +1,7 @@ #!/bin/bash # Script to run all U-Boot tests that use sandbox. +# $1: tests to run (empty for all, 'quick' for quick ones only) # Runs a test and checks the exit code to decide if it passed # $1: Test name @@ -12,14 +13,17 @@ run_test() { [ $? -ne 0 ] && failures=$((failures+1)) } +# SKip slow tests if requested +[ "$1" == "quick" ] && mark_expr="not slow" + failures=0 # Run all tests that the standard sandbox build can support -run_test "sandbox" ./test/py/test.py --bd sandbox --build +run_test "sandbox" ./test/py/test.py --bd sandbox --build -m "${mark_expr}" # Run tests which require sandbox_spl run_test "sandbox_spl" ./test/py/test.py --bd sandbox_spl --build \ - -k test_ofplatdata.py + -k 'test_ofplatdata or test_handoff' # Run tests for the flat-device-tree version of sandbox. This is a special # build which does not enable CONFIG_OF_LIVE for the live device tree, so we can @@ -36,7 +40,9 @@ export DTC=${DTC_DIR}/dtc run_test "binman" ./tools/binman/binman -t run_test "patman" ./tools/patman/patman --test -run_test "buildman" ./tools/buildman/buildman -t + +[ "$1" == "quick" ] && skip=--skip-net-tests +run_test "buildman" ./tools/buildman/buildman -t ${skip} run_test "fdt" ./tools/dtoc/test_fdt -t run_test "dtoc" ./tools/dtoc/dtoc -t diff --git a/tools/.gitignore b/tools/.gitignore index c8cdaef90c..e5ede22842 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -24,6 +24,7 @@ /mksunxiboot /mxsboot /ncb +/prelink-riscv /proftool /relocate-rela /sunxi-spl-image-builder diff --git a/tools/Makefile b/tools/Makefile index 3c0521f655..081383d7a7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \ imagetool.o \ imximage.o \ imx8image.o \ + imx8mimage.o \ kwbimage.o \ lib/md5.o \ lpc32xximage.o \ @@ -106,6 +107,7 @@ dumpimage-mkimage-objs := aisimage.o \ stm32image.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ + lib/crc16.o \ lib/sha1.o \ lib/sha256.o \ common/hash.o \ @@ -116,6 +118,7 @@ dumpimage-mkimage-objs := aisimage.o \ $(LIBFDT_OBJS) \ gpimage.o \ gpimage-common.o \ + mtk_image.o \ $(RSA_OBJS-y) dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o @@ -124,7 +127,7 @@ fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o file2include-objs := file2include.o -ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) +ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS diff --git a/tools/binman/README b/tools/binman/README index b64dedf2eb..04ed2b799c 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -723,6 +723,12 @@ If you need to specify a particular device-tree compiler to use, you can define the DTC environment variable. This can be useful when the system dtc is too old. +To enable a full backtrace and other debugging features in binman, pass +BINMAN_DEBUG=1 to your build: + + make sandbox_defconfig + make BINMAN_DEBUG=1 + History / Credits ----------------- diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py index 642a0e482a..ae80bbee53 100644 --- a/tools/binman/etype/blob.py +++ b/tools/binman/etype/blob.py @@ -60,7 +60,7 @@ class Entry_blob(Entry): except AttributeError: data = lz4.compress(data) ''' - data = tools.Run('lz4', '-c', self._pathname, ) + data = tools.Run('lz4', '-c', self._pathname) self.SetContents(data) return True diff --git a/tools/binman/etype/u_boot_elf.py b/tools/binman/etype/u_boot_elf.py index 134b6cc15b..f83860dc0a 100644 --- a/tools/binman/etype/u_boot_elf.py +++ b/tools/binman/etype/u_boot_elf.py @@ -30,9 +30,8 @@ class Entry_u_boot_elf(Entry_blob): out_fname = tools.GetOutputFilename('%s.stripped' % uniq) tools.WriteFile(out_fname, tools.ReadFile(self._pathname)) tools.Run('strip', out_fname) - self.SetContents(tools.ReadFile(out_fname)) - else: - self.SetContents(tools.ReadFile(self._pathname)) + self._pathname = out_fname + Entry_blob.ReadBlobContents(self) return True def GetDefaultFilename(self): diff --git a/tools/buildman/README b/tools/buildman/README index 76601902cb..5a709c6ff9 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -114,6 +114,10 @@ a few commits or boards, it will be pretty slow. As a tip, if you don't plan to use your machine for anything else, you can use -T to increase the number of threads beyond the default. + +Selecting which boards to build +=============================== + Buildman lets you build all boards, or a subset. Specify the subset by passing command-line arguments that list the desired board name, architecture name, SOC name, or anything else in the boards.cfg file. Multiple arguments are @@ -138,11 +142,17 @@ You can also use -x to specifically exclude some boards. For example: means to build all arm boards except nvidia, freescale and anything ending with 'ball'. +For building specific boards you can use the --boards option, which takes a +comma-separated list of board target names and be used multiple times on +the command line: + + buidman --boards sandbox,snow --boards + It is convenient to use the -n option to see what will be built based on the subset given. Use -v as well to get an actual list of boards. Buildman does not store intermediate object files. It optionally copies -the binary output into a directory when a build is successful. Size +the binary output into a directory when a build is successful (-k). Size information is always recorded. It needs a fair bit of disk space to work, typically 250MB per thread. diff --git a/tools/buildman/board.py b/tools/buildman/board.py index 272bac0c21..2a1d021574 100644 --- a/tools/buildman/board.py +++ b/tools/buildman/board.py @@ -237,20 +237,30 @@ class Boards: terms.append(term) return terms - def SelectBoards(self, args, exclude=[]): + def SelectBoards(self, args, exclude=[], boards=None): """Mark boards selected based on args + Normally either boards (an explicit list of boards) or args (a list of + terms to match against) is used. It is possible to specify both, in + which case they are additive. + + If boards and args are both empty, all boards are selected. + Args: args: List of strings specifying boards to include, either named, or by their target, architecture, cpu, vendor or soc. If empty, all boards are selected. exclude: List of boards to exclude, regardless of 'args' + boards: List of boards to build Returns: - Dictionary which holds the list of boards which were selected - due to each argument, arranged by argument. + Tuple + Dictionary which holds the list of boards which were selected + due to each argument, arranged by argument. + List of errors found """ result = {} + warnings = [] terms = self._BuildTerms(args) result['all'] = [] @@ -261,6 +271,7 @@ class Boards: for expr in exclude: exclude_list.append(Expr(expr)) + found = [] for board in self._boards: matching_term = None build_it = False @@ -271,6 +282,10 @@ class Boards: matching_term = str(term) build_it = True break + elif boards: + if board.target in boards: + build_it = True + found.append(board.target) else: build_it = True @@ -286,4 +301,9 @@ class Boards: result[matching_term].append(board.target) result['all'].append(board.target) - return result + if boards: + remaining = set(boards) - set(found) + if remaining: + warnings.append('Boards not found: %s\n' % ', '.join(remaining)) + + return result, warnings diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 05f8299541..6a6c83bf33 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -290,6 +290,7 @@ class Builder: self._re_function = re.compile('(.*): In function.*') self._re_files = re.compile('In file included from.*') self._re_warning = re.compile('(.*):(\d*):(\d*): warning: .*') + self._re_dtb_warning = re.compile('(.*): Warning .*') self._re_note = re.compile('(.*):(\d*):(\d*): note: this is the location of the previous.*') self.queue = Queue.Queue() @@ -788,7 +789,8 @@ class Builder: self._re_files.match(line)): last_func = line else: - is_warning = self._re_warning.match(line) + is_warning = (self._re_warning.match(line) or + self._re_dtb_warning.match(line)) is_note = self._re_note.match(line) if is_warning or (last_was_warning and is_note): if last_func: @@ -1194,10 +1196,11 @@ class Builder: Print(' ' + line, newline=True, colour=col) - better = [] # List of boards fixed since last commit - worse = [] # List of new broken boards since last commit - new = [] # List of boards that didn't exist last time - unknown = [] # List of boards that were not built + ok_boards = [] # List of boards fixed since last commit + warn_boards = [] # List of boards with warnings since last commit + err_boards = [] # List of new broken boards since last commit + new_boards = [] # List of boards that didn't exist last time + unknown_boards = [] # List of boards that were not built for target in board_dict: if target not in board_selected: @@ -1208,13 +1211,19 @@ class Builder: base_outcome = self._base_board_dict[target].rc outcome = board_dict[target] if outcome.rc == OUTCOME_UNKNOWN: - unknown.append(target) + unknown_boards.append(target) elif outcome.rc < base_outcome: - better.append(target) + if outcome.rc == OUTCOME_WARNING: + warn_boards.append(target) + else: + ok_boards.append(target) elif outcome.rc > base_outcome: - worse.append(target) + if outcome.rc == OUTCOME_WARNING: + warn_boards.append(target) + else: + err_boards.append(target) else: - new.append(target) + new_boards.append(target) # Get a list of errors that have appeared, and disappeared better_err, worse_err = _CalcErrorDelta(self._base_err_lines, @@ -1223,16 +1232,18 @@ class Builder: self._base_warn_line_boards, warn_lines, warn_line_boards, 'w') # Display results by arch - if (better or worse or unknown or new or worse_err or better_err - or worse_warn or better_warn): + if any((ok_boards, warn_boards, err_boards, unknown_boards, new_boards, + worse_err, better_err, worse_warn, better_warn)): arch_list = {} - self.AddOutcome(board_selected, arch_list, better, '', + self.AddOutcome(board_selected, arch_list, ok_boards, '', self.col.GREEN) - self.AddOutcome(board_selected, arch_list, worse, '+', + self.AddOutcome(board_selected, arch_list, warn_boards, 'w+', + self.col.YELLOW) + self.AddOutcome(board_selected, arch_list, err_boards, '+', self.col.RED) - self.AddOutcome(board_selected, arch_list, new, '*', self.col.BLUE) + self.AddOutcome(board_selected, arch_list, new_boards, '*', self.col.BLUE) if self._show_unknown: - self.AddOutcome(board_selected, arch_list, unknown, '?', + self.AddOutcome(board_selected, arch_list, unknown_boards, '?', self.col.MAGENTA) for arch, target_list in arch_list.iteritems(): Print('%10s: %s' % (arch, target_list)) diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py index e493b1ac4a..93d09ca08d 100644 --- a/tools/buildman/cmdline.py +++ b/tools/buildman/cmdline.py @@ -18,6 +18,8 @@ def ParseArgs(): parser.add_option('-B', '--bloat', dest='show_bloat', action='store_true', default=False, help='Show changes in function code size for each board') + parser.add_option('--boards', type='string', action='append', + help='List of board names to build separated by comma') parser.add_option('-c', '--count', dest='count', type='int', default=-1, help='Run build on the top n commits') parser.add_option('-C', '--force-reconfig', dest='force_reconfig', @@ -64,7 +66,7 @@ def ParseArgs(): parser.add_option('-l', '--list-error-boards', action='store_true', default=False, help='Show a list of boards next to each error/warning') parser.add_option('--list-tool-chains', action='store_true', default=False, - help='List available tool chains') + help='List available tool chains (use -v to see probing detail)') parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (describe actions, but do nothing)") parser.add_option('-N', '--no-subdirs', action='store_true', dest='no_subdirs', @@ -102,7 +104,7 @@ def ParseArgs(): type='string', action='append', help='Specify a list of boards to exclude, separated by comma') - parser.usage += """ + parser.usage += """ [list of target/arch/cpu/board/vendor/soc to build] Build U-Boot for all commits in a branch. Use -n to do a dry run""" diff --git a/tools/buildman/control.py b/tools/buildman/control.py index bc0819784f..c900211510 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -41,7 +41,8 @@ def GetActionSummary(is_summary, commits, selected, options): GetPlural(options.threads), options.jobs, GetPlural(options.jobs)) return str -def ShowActions(series, why_selected, boards_selected, builder, options): +def ShowActions(series, why_selected, boards_selected, builder, options, + board_warnings): """Display a list of actions that we would take, if not a dry run. Args: @@ -55,6 +56,7 @@ def ShowActions(series, why_selected, boards_selected, builder, options): value is Board object builder: The builder that will be used to build the commits options: Command line options object + board_warnings: List of warnings obtained from board selected """ col = terminal.Color() print 'Dry run, so not doing much. But I would do this:' @@ -79,6 +81,9 @@ def ShowActions(series, why_selected, boards_selected, builder, options): print ' %s' % ' '.join(why_selected[arg]) print ('Total boards to build for each commit: %d\n' % len(why_selected['all'])) + if board_warnings: + for warning in board_warnings: + print col.Color(col.YELLOW, warning) def CheckOutputDir(output_dir): """Make sure that the output directory is not within the current directory @@ -159,7 +164,7 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, if no_toolchains: toolchains.GetSettings() - toolchains.Scan(options.list_tool_chains) + toolchains.Scan(options.list_tool_chains and options.verbose) if options.list_tool_chains: toolchains.List() print @@ -210,7 +215,15 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, for arg in options.exclude: exclude += arg.split(',') - why_selected = boards.SelectBoards(args, exclude) + + if options.boards: + requested_boards = [] + for b in options.boards: + requested_boards += b.split(',') + else: + requested_boards = None + why_selected, board_warnings = boards.SelectBoards(args, exclude, + requested_boards) selected = boards.GetSelected() if not len(selected): sys.exit(col.Color(col.RED, 'No matching boards found')) @@ -292,7 +305,8 @@ def DoBuildman(options, args, toolchains=None, make_func=None, boards=None, # For a dry run, just show our actions as a sanity check if options.dry_run: - ShowActions(series, why_selected, selected, builder, options) + ShowActions(series, why_selected, selected, builder, options, + board_warnings) else: builder.force_build = options.force_build builder.force_build_failures = options.force_build_failures diff --git a/tools/buildman/test.py b/tools/buildman/test.py index e0c9d6da6a..de02f61be6 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -46,8 +46,9 @@ make[1]: *** [main.o] Error 1 make: *** [common/libcommon.o] Error 2 Make failed ''', - '''main.c: In function 'main_loop3': -main.c:280:6: warning: unused variable 'mary' [-Wunused-variable] + '''arch/arm/dts/socfpga_arria10_socdk_sdmmc.dtb: Warning \ +(avoid_unnecessary_addr_size): /clocks: unnecessary #address-cells/#size-cells \ +without "ranges" or child "reg" property ''', '''powerpc-linux-ld: warning: dot moved backwards before `.bss' powerpc-linux-ld: warning: dot moved backwards before `.bss' @@ -96,6 +97,8 @@ boards = [ BASE_DIR = 'base' +OUTCOME_OK, OUTCOME_WARN, OUTCOME_ERR = range(3) + class Options: """Class that holds build options""" pass @@ -165,9 +168,10 @@ class TestBuild(unittest.TestCase): result.combined = result.stdout + result.stderr return result - def assertSummary(self, text, arch, plus, boards, ok=False): + def assertSummary(self, text, arch, plus, boards, outcome=OUTCOME_ERR): col = self._col - expected_colour = col.GREEN if ok else col.RED + expected_colour = (col.GREEN if outcome == OUTCOME_OK else + col.YELLOW if outcome == OUTCOME_WARN else col.RED) expect = '%10s: ' % arch # TODO(sjg@chromium.org): If plus is '', we shouldn't need this expect += ' ' + col.Color(expected_colour, plus) @@ -191,6 +195,8 @@ class TestBuild(unittest.TestCase): build.do_make = self.Make board_selected = self.boards.GetSelectedDict() + # Build the boards for the pre-defined commits and warnings/errors + # associated with each. This calls our Make() to inject the fake output. build.BuildBoards(self.commits, board_selected, keep_outputs=False, verbose=False) lines = terminal.GetPrintTestLines() @@ -206,33 +212,49 @@ class TestBuild(unittest.TestCase): build.ShowSummary(self.commits, board_selected) #terminal.EchoPrintTestLines() lines = terminal.GetPrintTestLines() + + # Upstream commit: no errors self.assertEqual(lines[0].text, '01: %s' % commits[0][1]) + + # Second commit: all archs should fail with warnings self.assertEqual(lines[1].text, '02: %s' % commits[1][1]) - # We expect all archs to fail col = terminal.Color() - self.assertSummary(lines[2].text, 'sandbox', '+', ['board4']) - self.assertSummary(lines[3].text, 'arm', '+', ['board1']) - self.assertSummary(lines[4].text, 'powerpc', '+', ['board2', 'board3']) + self.assertSummary(lines[2].text, 'sandbox', 'w+', ['board4'], + outcome=OUTCOME_WARN) + self.assertSummary(lines[3].text, 'arm', 'w+', ['board1'], + outcome=OUTCOME_WARN) + self.assertSummary(lines[4].text, 'powerpc', 'w+', ['board2', 'board3'], + outcome=OUTCOME_WARN) - # Now we should have the compiler warning + # Second commit: The warnings should be listed self.assertEqual(lines[5].text, 'w+%s' % errors[0].rstrip().replace('\n', '\nw+')) self.assertEqual(lines[5].colour, col.MAGENTA) + # Third commit: Still fails self.assertEqual(lines[6].text, '03: %s' % commits[2][1]) self.assertSummary(lines[7].text, 'sandbox', '+', ['board4']) - self.assertSummary(lines[8].text, 'arm', '', ['board1'], ok=True) + self.assertSummary(lines[8].text, 'arm', '', ['board1'], + outcome=OUTCOME_OK) self.assertSummary(lines[9].text, 'powerpc', '+', ['board2', 'board3']) - # Compiler error + # Expect a compiler error self.assertEqual(lines[10].text, '+%s' % errors[1].rstrip().replace('\n', '\n+')) + # Fourth commit: Compile errors are fixed, just have warning for board3 self.assertEqual(lines[11].text, '04: %s' % commits[3][1]) - self.assertSummary(lines[12].text, 'sandbox', '', ['board4'], ok=True) - self.assertSummary(lines[13].text, 'powerpc', '', ['board2', 'board3'], - ok=True) + self.assertSummary(lines[12].text, 'sandbox', 'w+', ['board4'], + outcome=OUTCOME_WARN) + expect = '%10s: ' % 'powerpc' + expect += ' ' + col.Color(col.GREEN, '') + expect += ' ' + expect += col.Color(col.GREEN, ' %s' % 'board2') + expect += ' ' + col.Color(col.YELLOW, 'w+') + expect += ' ' + expect += col.Color(col.YELLOW, ' %s' % 'board3') + self.assertEqual(lines[13].text, expect) # Compile error fixed self.assertEqual(lines[14].text, '-%s' % @@ -243,9 +265,11 @@ class TestBuild(unittest.TestCase): errors[2].rstrip().replace('\n', '\nw+')) self.assertEqual(lines[15].colour, col.MAGENTA) + # Fifth commit self.assertEqual(lines[16].text, '05: %s' % commits[4][1]) self.assertSummary(lines[17].text, 'sandbox', '+', ['board4']) - self.assertSummary(lines[18].text, 'powerpc', '', ['board3'], ok=True) + self.assertSummary(lines[18].text, 'powerpc', '', ['board3'], + outcome=OUTCOME_OK) # The second line of errors[3] is a duplicate, so buildman will drop it expect = errors[3].rstrip().split('\n') @@ -256,8 +280,10 @@ class TestBuild(unittest.TestCase): self.assertEqual(lines[20].text, 'w-%s' % errors[2].rstrip().replace('\n', '\nw-')) + # Sixth commit self.assertEqual(lines[21].text, '06: %s' % commits[5][1]) - self.assertSummary(lines[22].text, 'sandbox', '', ['board4'], ok=True) + self.assertSummary(lines[22].text, 'sandbox', '', ['board4'], + outcome=OUTCOME_OK) # The second line of errors[3] is a duplicate, so buildman will drop it expect = errors[3].rstrip().split('\n') @@ -268,6 +294,7 @@ class TestBuild(unittest.TestCase): self.assertEqual(lines[24].text, 'w-%s' % errors[0].rstrip().replace('\n', '\nw-')) + # Seventh commit self.assertEqual(lines[25].text, '07: %s' % commits[6][1]) self.assertSummary(lines[26].text, 'sandbox', '+', ['board4']) @@ -313,60 +340,63 @@ class TestBuild(unittest.TestCase): def testBoardSingle(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['sandbox']), - {'all': ['board4'], 'sandbox': ['board4']}) + ({'all': ['board4'], 'sandbox': ['board4']}, [])) def testBoardArch(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['arm']), - {'all': ['board0', 'board1'], - 'arm': ['board0', 'board1']}) + ({'all': ['board0', 'board1'], + 'arm': ['board0', 'board1']}, [])) def testBoardArchSingle(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['arm sandbox']), - {'sandbox': ['board4'], + ({'sandbox': ['board4'], 'all': ['board0', 'board1', 'board4'], - 'arm': ['board0', 'board1']}) + 'arm': ['board0', 'board1']}, [])) def testBoardArchSingleMultiWord(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['arm', 'sandbox']), - {'sandbox': ['board4'], 'all': ['board0', 'board1', 'board4'], 'arm': ['board0', 'board1']}) + ({'sandbox': ['board4'], + 'all': ['board0', 'board1', 'board4'], + 'arm': ['board0', 'board1']}, [])) def testBoardSingleAnd(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['Tester & arm']), - {'Tester&arm': ['board0', 'board1'], 'all': ['board0', 'board1']}) + ({'Tester&arm': ['board0', 'board1'], + 'all': ['board0', 'board1']}, [])) def testBoardTwoAnd(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['Tester', '&', 'arm', 'Tester' '&', 'powerpc', 'sandbox']), - {'sandbox': ['board4'], + ({'sandbox': ['board4'], 'all': ['board0', 'board1', 'board2', 'board3', 'board4'], 'Tester&powerpc': ['board2', 'board3'], - 'Tester&arm': ['board0', 'board1']}) + 'Tester&arm': ['board0', 'board1']}, [])) def testBoardAll(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards([]), - {'all': ['board0', 'board1', 'board2', 'board3', - 'board4']}) + ({'all': ['board0', 'board1', 'board2', 'board3', + 'board4']}, [])) def testBoardRegularExpression(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['T.*r&^Po']), - {'all': ['board2', 'board3'], - 'T.*r&^Po': ['board2', 'board3']}) + ({'all': ['board2', 'board3'], + 'T.*r&^Po': ['board2', 'board3']}, [])) def testBoardDuplicate(self): """Test single board selection""" self.assertEqual(self.boards.SelectBoards(['sandbox sandbox', 'sandbox']), - {'all': ['board4'], 'sandbox': ['board4']}) + ({'all': ['board4'], 'sandbox': ['board4']}, [])) def CheckDirs(self, build, dirname): self.assertEqual('base%s' % dirname, build._GetOutputDir(1)) self.assertEqual('base%s/fred' % dirname, diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 4b35f400e9..c62ce136fa 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -502,7 +502,8 @@ class Toolchains: trailing / """ stdout = command.Output('tar', 'xvfJ', fname, '-C', dest) - return stdout.splitlines()[0][:-1] + dirs = stdout.splitlines()[1].split('/')[:2] + return '/'.join(dirs) def TestSettingsHasPath(self, path): """Check if buildman will find this toolchain @@ -516,13 +517,14 @@ class Toolchains: def ListArchs(self): """List architectures with available toolchains to download""" host_arch, archives = self.LocateArchUrl('list') - re_arch = re.compile('[-a-z0-9.]*_([^-]*)-.*') + re_arch = re.compile('[-a-z0-9.]*[-_]([^-]*)-.*') arch_set = set() for archive in archives: # Remove the host architecture from the start arch = re_arch.match(archive[len(host_arch):]) if arch: - arch_set.add(arch.group(1)) + if arch.group(1) != '2.0' and arch.group(1) != '64': + arch_set.add(arch.group(1)) return sorted(arch_set) def FetchAndInstall(self, arch): diff --git a/tools/file2include.c b/tools/file2include.c index b98af30a72..775440cba9 100644 --- a/tools/file2include.c +++ b/tools/file2include.c @@ -18,7 +18,6 @@ #include #include #include -#include /* Size of the blocks written to the compressed file */ #define BLOCK_SIZE 8 diff --git a/tools/image-host.c b/tools/image-host.c index 09e4f47e5a..88b329502c 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -157,6 +157,7 @@ static int fit_image_setup_sig(struct image_sign_info *info, { const char *node_name; char *algo_name; + const char *padding_name; node_name = fit_get_name(fit, noffset, NULL); if (fit_image_hash_get_algo(fit, noffset, &algo_name)) { @@ -165,6 +166,8 @@ static int fit_image_setup_sig(struct image_sign_info *info, return -1; } + padding_name = fdt_getprop(fit, noffset, "padding", NULL); + memset(info, '\0', sizeof(*info)); info->keydir = keydir; info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); @@ -173,6 +176,7 @@ static int fit_image_setup_sig(struct image_sign_info *info, info->name = strdup(algo_name); info->checksum = image_get_checksum_algo(algo_name); info->crypto = image_get_crypto_algo(algo_name); + info->padding = image_get_padding_algo(padding_name); info->require_keys = require_keys; info->engine_id = engine_id; if (!info->checksum || !info->crypto) { diff --git a/tools/imagetool.h b/tools/imagetool.h index 3fcfb4468d..71471420f9 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -233,6 +233,7 @@ time_t imagetool_get_source_date( void pbl_load_uboot(int fd, struct image_tool_params *mparams); int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); int imx8image_copy_image(int fd, struct image_tool_params *mparams); +int imx8mimage_copy_image(int fd, struct image_tool_params *mparams); #define ___cat(a, b) a ## b #define __cat(a, b) ___cat(a, b) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh new file mode 100755 index 0000000000..6346fb64d8 --- /dev/null +++ b/tools/imx8m_image.sh @@ -0,0 +1,43 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to check whether the file exists in imximage.cfg for i.MX8M +# + +file=$1 + +post_process=$2 + +blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {print $2} /^DDR_FW/ {print $2}' $file` +for f in $blobs; do + tmp=$srctree/$f + + if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then + continue + fi + + if [ -f $f ]; then + continue + fi + + if [ ! -f $tmp ]; then + echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2 + exit 1 + fi + + sed -in "s;$f;$tmp;" $file +done + +if [ $post_process == 1 ]; then + if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin + objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin + cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin + cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin + cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin + rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin + fi +fi + +exit 0 diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c new file mode 100644 index 0000000000..50a256cbac --- /dev/null +++ b/tools/imx8mimage.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Peng Fan + */ + + +#include "imagetool.h" +#include +#include "imximage.h" +#include "compiler.h" + +static uint32_t ap_start_addr, sld_start_addr, sld_src_off; +static char *ap_img, *sld_img, *signed_hdmi; +static imx_header_v3_t imx_header[2]; /* At most there are 3 IVT headers */ +static uint32_t rom_image_offset; +static uint32_t sector_size = 0x200; +static uint32_t image_off; +static uint32_t sld_header_off; +static uint32_t ivt_offset; +static uint32_t using_fit; + +#define CSF_SIZE 0x2000 +#define HDMI_IVT_ID 0 +#define IMAGE_IVT_ID 1 + +#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */ +#define ALIGN_SIZE 0x1000 +#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a) +#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2)) + +static uint32_t get_cfg_value(char *token, char *name, int linenr) +{ + char *endptr; + uint32_t value; + + errno = 0; + value = strtoul(token, &endptr, 16); + if (errno || token == endptr) { + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", + name, linenr, token); + exit(EXIT_FAILURE); + } + return value; +} + +int imx8mimage_check_params(struct image_tool_params *params) +{ + return 0; +} + +static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ +} + +static void imx8mimage_print_header(const void *ptr) +{ +} + +static int imx8mimage_check_image_types(uint8_t type) +{ + return (type == IH_TYPE_IMX8MIMAGE) ? EXIT_SUCCESS : EXIT_FAILURE; +} + +static table_entry_t imx8mimage_cmds[] = { + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, + {CMD_FIT, "FIT", "fit image", }, + {CMD_SIGNED_HDMI, "SIGNED_HDMI", "signed hdmi image", }, + {CMD_LOADER, "LOADER", "loader image", }, + {CMD_SECOND_LOADER, "SECOND_LOADER", "2nd loader image", }, + {CMD_DDR_FW, "DDR_FW", "ddr firmware", }, + {-1, "", "", }, +}; + +static table_entry_t imx8mimage_ivt_offset[] = { + {0x400, "sd", "sd/emmc",}, + {0x400, "emmc_fastboot", "emmc fastboot",}, + {0x1000, "fspi", "flexspi", }, + {-1, "", "Invalid", }, +}; + +static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int lineno) +{ + switch (cmd) { + case CMD_BOOT_FROM: + ivt_offset = get_table_entry_id(imx8mimage_ivt_offset, + "imx8mimage ivt offset", + token); + if (!strncmp(token, "sd", 2)) + rom_image_offset = 0x8000; + break; + case CMD_LOADER: + ap_img = token; + break; + case CMD_SECOND_LOADER: + sld_img = token; + break; + case CMD_SIGNED_HDMI: + signed_hdmi = token; + case CMD_FIT: + using_fit = 1; + break; + case CMD_DDR_FW: + /* Do nothing */ + break; + } +} + +static void parse_cfg_fld(int32_t *cmd, char *token, + char *name, int lineno, int fld) +{ + switch (fld) { + case CFG_COMMAND: + *cmd = get_table_entry_id(imx8mimage_cmds, + "imx8mimage commands", token); + if (*cmd < 0) { + fprintf(stderr, "Error: %s[%d] - Invalid command" "(%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + break; + case CFG_REG_SIZE: + parse_cfg_cmd(*cmd, token, name, lineno); + break; + case CFG_REG_ADDRESS: + switch (*cmd) { + case CMD_LOADER: + ap_start_addr = get_cfg_value(token, name, lineno); + break; + case CMD_SECOND_LOADER: + sld_start_addr = get_cfg_value(token, name, lineno); + break; + } + break; + case CFG_REG_VALUE: + switch (*cmd) { + case CMD_SECOND_LOADER: + sld_src_off = get_cfg_value(token, name, lineno); + break; + } + default: + break; + } +} + +static uint32_t parse_cfg_file(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + int lineno = 0; + int fld; + size_t len; + int32_t cmd; + + fd = fopen(name, "r"); + if (fd == 0) { + fprintf(stderr, "Error: %s - Can't open cfg file\n", name); + exit(EXIT_FAILURE); + } + + /* + * Very simple parsing, line starting with # are comments + * and are dropped + */ + while ((getline(&line, &len, fd)) > 0) { + lineno++; + + token = strtok_r(line, "\r\n", &saveptr1); + if (!token) + continue; + + /* Check inside the single line */ + for (fld = CFG_COMMAND, cmd = CFG_INVALID, + line = token; ; line = NULL, fld++) { + token = strtok_r(line, " \t", &saveptr2); + if (!token) + break; + + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + parse_cfg_fld(&cmd, token, name, lineno, fld); + } + } + + return 0; +} + +static void fill_zero(int ifd, int size, int offset) +{ + int fill_size; + uint8_t zeros[4096]; + int ret; + + memset(zeros, 0, sizeof(zeros)); + + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "%s seek: %s\n", __func__, strerror(errno)); + exit(EXIT_FAILURE); + } + + while (size) { + if (size > 4096) + fill_size = 4096; + else + fill_size = size; + + if (write(ifd, (char *)&zeros, fill_size) != fill_size) { + fprintf(stderr, "Write error: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + size -= fill_size; + }; +} + +static void copy_file(int ifd, const char *datafile, int pad, int offset, + int datafile_offset) +{ + int dfd; + struct stat sbuf; + unsigned char *ptr; + int tail; + int zero = 0; + uint8_t zeros[4096]; + int size, ret; + + memset(zeros, 0, sizeof(zeros)); + + dfd = open(datafile, O_RDONLY | O_BINARY); + if (dfd < 0) { + fprintf(stderr, "Can't open %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(dfd, &sbuf) < 0) { + fprintf(stderr, "Can't stat %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == MAP_FAILED) { + fprintf(stderr, "Can't read %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + size = sbuf.st_size - datafile_offset; + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ifd fail\n"); + exit(EXIT_FAILURE); + } + + if (write(ifd, ptr + datafile_offset, size) != size) { + fprintf(stderr, "Write error %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + tail = size % 4; + pad = pad - size; + if (pad == 1 && tail != 0) { + if (write(ifd, (char *)&zero, 4 - tail) != 4 - tail) { + fprintf(stderr, "Write error on %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + } else if (pad > 1) { + while (pad > 0) { + int todo = sizeof(zeros); + + if (todo > pad) + todo = pad; + if (write(ifd, (char *)&zeros, todo) != todo) { + fprintf(stderr, "Write error: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + pad -= todo; + } + } + + munmap((void *)ptr, sbuf.st_size); + close(dfd); +} + +/* Return this IVT offset in the final output file */ +static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep, + uint32_t *fit_load_addr) +{ + image_header_t image_header; + int ret; + + uint32_t fit_size, load_addr; + int align_len = 64 - 1; /* 64 is cacheline size */ + + ret = lseek(fd, fit_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek fd fail for fit\n"); + exit(EXIT_FAILURE); + } + + if (read(fd, (char *)&image_header, sizeof(image_header_t)) != + sizeof(image_header_t)) { + fprintf(stderr, "generate_ivt_for_fit read failed: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + if (be32_to_cpu(image_header.ih_magic) != FDT_MAGIC) { + fprintf(stderr, "%s error: not a FIT file\n", __func__); + exit(EXIT_FAILURE); + } + + fit_size = fdt_totalsize(&image_header); + fit_size = (fit_size + 3) & ~3; + + fit_size = ALIGN(fit_size, ALIGN_SIZE); + + ret = lseek(fd, fit_offset + fit_size, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek fd fail for fit\n"); + exit(EXIT_FAILURE); + } + + /* + * ep is the u-boot entry. SPL loads the FIT before the u-boot + * address. 0x2000 is for CSF_SIZE + */ + load_addr = (ep - (fit_size + CSF_SIZE) - 512 - align_len) & + ~align_len; + + flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 }, + load_addr, 0, 0, 0, + (load_addr + fit_size), + (load_addr + fit_size + 0x20), + 0 }; + + if (write(fd, &ivt_header, sizeof(flash_header_v2_t)) != + sizeof(flash_header_v2_t)) { + fprintf(stderr, "IVT writing error on fit image\n"); + exit(EXIT_FAILURE); + } + + *fit_load_addr = load_addr; + + return fit_offset + fit_size; +} + +static void dump_header_v2(imx_header_v3_t *imx_header, int index) +{ + const char *ivt_name[2] = {"HDMI FW", "LOADER IMAGE"}; + + fprintf(stdout, "========= IVT HEADER [%s] =========\n", + ivt_name[index]); + fprintf(stdout, "header.tag: \t\t0x%x\n", + imx_header[index].fhdr.header.tag); + fprintf(stdout, "header.length: \t\t0x%x\n", + imx_header[index].fhdr.header.length); + fprintf(stdout, "header.version: \t0x%x\n", + imx_header[index].fhdr.header.version); + fprintf(stdout, "entry: \t\t\t0x%x\n", + imx_header[index].fhdr.entry); + fprintf(stdout, "reserved1: \t\t0x%x\n", + imx_header[index].fhdr.reserved1); + fprintf(stdout, "dcd_ptr: \t\t0x%x\n", + imx_header[index].fhdr.dcd_ptr); + fprintf(stdout, "boot_data_ptr: \t\t0x%x\n", + imx_header[index].fhdr.boot_data_ptr); + fprintf(stdout, "self: \t\t\t0x%x\n", + imx_header[index].fhdr.self); + fprintf(stdout, "csf: \t\t\t0x%x\n", + imx_header[index].fhdr.csf); + fprintf(stdout, "reserved2: \t\t0x%x\n", + imx_header[index].fhdr.reserved2); + + fprintf(stdout, "boot_data.start: \t0x%x\n", + imx_header[index].boot_data.start); + fprintf(stdout, "boot_data.size: \t0x%x\n", + imx_header[index].boot_data.size); + fprintf(stdout, "boot_data.plugin: \t0x%x\n", + imx_header[index].boot_data.plugin); +} + +void build_image(int ofd) +{ + int file_off, header_hdmi_off = 0, header_image_off; + int hdmi_fd, ap_fd, sld_fd; + uint32_t sld_load_addr = 0; + uint32_t csf_off, sld_csf_off = 0; + int ret; + struct stat sbuf; + + if (!ap_img) { + fprintf(stderr, "No LOADER image specificed\n"); + exit(EXIT_FAILURE); + } + + file_off = 0; + + if (signed_hdmi) { + header_hdmi_off = file_off + ivt_offset; + + hdmi_fd = open(signed_hdmi, O_RDONLY | O_BINARY); + if (hdmi_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + signed_hdmi, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(hdmi_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + signed_hdmi, strerror(errno)); + exit(EXIT_FAILURE); + } + close(hdmi_fd); + + /* + * Aligned to 104KB = 92KB FW image + 0x8000 + * (IVT and alignment) + 0x4000 (second IVT + CSF) + */ + file_off += ALIGN(sbuf.st_size, + HDMI_FW_SIZE + 0x2000 + 0x1000); + } + + header_image_off = file_off + ivt_offset; + + ap_fd = open(ap_img, O_RDONLY | O_BINARY); + if (ap_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + ap_img, strerror(errno)); + exit(EXIT_FAILURE); + } + if (fstat(ap_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + ap_img, strerror(errno)); + exit(EXIT_FAILURE); + } + close(ap_fd); + + imx_header[IMAGE_IVT_ID].fhdr.header.tag = IVT_HEADER_TAG; /* 0xD1 */ + imx_header[IMAGE_IVT_ID].fhdr.header.length = + cpu_to_be16(sizeof(flash_header_v2_t)); + imx_header[IMAGE_IVT_ID].fhdr.header.version = IVT_VERSION_V3; /* 0x41 */ + imx_header[IMAGE_IVT_ID].fhdr.entry = ap_start_addr; + imx_header[IMAGE_IVT_ID].fhdr.self = ap_start_addr - + sizeof(imx_header_v3_t); + imx_header[IMAGE_IVT_ID].fhdr.dcd_ptr = 0; + imx_header[IMAGE_IVT_ID].fhdr.boot_data_ptr = + imx_header[IMAGE_IVT_ID].fhdr.self + + offsetof(imx_header_v3_t, boot_data); + imx_header[IMAGE_IVT_ID].boot_data.start = + imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset; + imx_header[IMAGE_IVT_ID].boot_data.size = + ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset, + sector_size); + + image_off = header_image_off + sizeof(imx_header_v3_t); + file_off += imx_header[IMAGE_IVT_ID].boot_data.size; + + imx_header[IMAGE_IVT_ID].boot_data.plugin = 0; + imx_header[IMAGE_IVT_ID].fhdr.csf = + imx_header[IMAGE_IVT_ID].boot_data.start + + imx_header[IMAGE_IVT_ID].boot_data.size; + + imx_header[IMAGE_IVT_ID].boot_data.size += CSF_SIZE; /* 8K region dummy CSF */ + + csf_off = file_off; + file_off += CSF_SIZE; + + /* Second boot loader image */ + if (sld_img) { + if (!using_fit) { + fprintf(stderr, "Not support no fit\n"); + exit(EXIT_FAILURE); + } else { + sld_header_off = sld_src_off - rom_image_offset; + /* + * Record the second bootloader relative offset in + * image's IVT reserved1 + */ + imx_header[IMAGE_IVT_ID].fhdr.reserved1 = + sld_header_off - header_image_off; + sld_fd = open(sld_img, O_RDONLY | O_BINARY); + if (sld_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + sld_img, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(sld_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + sld_img, strerror(errno)); + exit(EXIT_FAILURE); + } + + close(sld_fd); + + file_off = sld_header_off; + file_off += sbuf.st_size + sizeof(image_header_t); + } + } + + if (signed_hdmi) { + header_hdmi_off -= ivt_offset; + ret = lseek(ofd, header_hdmi_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail for hdmi\n"); + exit(EXIT_FAILURE); + } + + /* The signed HDMI FW has 0x400 IVT offset, need remove it */ + copy_file(ofd, signed_hdmi, 0, header_hdmi_off, 0x400); + } + + /* Main Image */ + header_image_off -= ivt_offset; + image_off -= ivt_offset; + ret = lseek(ofd, header_image_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail\n"); + exit(EXIT_FAILURE); + } + + /* Write image header */ + if (write(ofd, &imx_header[IMAGE_IVT_ID], sizeof(imx_header_v3_t)) != + sizeof(imx_header_v3_t)) { + fprintf(stderr, "error writing image hdr\n"); + exit(1); + } + + copy_file(ofd, ap_img, 0, image_off, 0); + + csf_off -= ivt_offset; + fill_zero(ofd, CSF_SIZE, csf_off); + + if (sld_img) { + sld_header_off -= ivt_offset; + ret = lseek(ofd, sld_header_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail for sld_img\n"); + exit(EXIT_FAILURE); + } + + /* Write image header */ + if (!using_fit) { + /* TODO */ + } else { + copy_file(ofd, sld_img, 0, sld_header_off, 0); + sld_csf_off = + generate_ivt_for_fit(ofd, sld_header_off, + sld_start_addr, + &sld_load_addr) + 0x20; + } + } + + if (!signed_hdmi) + dump_header_v2(imx_header, 0); + dump_header_v2(imx_header, 1); + + fprintf(stdout, "========= OFFSET dump ========="); + if (signed_hdmi) { + fprintf(stdout, "\nSIGNED HDMI FW:\n"); + fprintf(stdout, " header_hdmi_off \t0x%x\n", + header_hdmi_off); + } + + fprintf(stdout, "\nLoader IMAGE:\n"); + fprintf(stdout, " header_image_off \t0x%x\n image_off \t\t0x%x\n csf_off \t\t0x%x\n", + header_image_off, image_off, csf_off); + fprintf(stdout, " spl hab block: \t0x%x 0x%x 0x%x\n", + imx_header[IMAGE_IVT_ID].fhdr.self, header_image_off, + csf_off - header_image_off); + + fprintf(stdout, "\nSecond Loader IMAGE:\n"); + fprintf(stdout, " sld_header_off \t0x%x\n", + sld_header_off); + fprintf(stdout, " sld_csf_off \t\t0x%x\n", + sld_csf_off); + fprintf(stdout, " sld hab block: \t0x%x 0x%x 0x%x\n", + sld_load_addr, sld_header_off, sld_csf_off - sld_header_off); +} + +int imx8mimage_copy_image(int outfd, struct image_tool_params *mparams) +{ + /* + * SECO FW is a container image, this is to calculate the + * 2nd container offset. + */ + fprintf(stdout, "parsing %s\n", mparams->imagename); + parse_cfg_file(mparams->imagename); + + build_image(outfd); + + return 0; +} + +/* + * imx8mimage parameters + */ +U_BOOT_IMAGE_TYPE( + imx8mimage, + "NXP i.MX8M Boot Image support", + 0, + NULL, + imx8mimage_check_params, + NULL, + imx8mimage_print_header, + imx8mimage_set_header, + NULL, + imx8mimage_check_image_types, + NULL, + NULL +); diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh index 4c629e8694..972b95ccbe 100755 --- a/tools/imx_cntr_image.sh +++ b/tools/imx_cntr_image.sh @@ -10,7 +10,7 @@ file=$1 blobs=`awk '/^APPEND/ {print $2} /^IMAGE/ || /^DATA/ {print $3}' $file` for f in $blobs; do tmp=$srctree/$f - if [ $f == "u-boot-dtb.bin" ]; then + if [ $f = "u-boot-dtb.bin" ]; then continue fi diff --git a/tools/k3_x509template.txt b/tools/k3_x509template.txt new file mode 100644 index 0000000000..bd3a9ab056 --- /dev/null +++ b/tools/k3_x509template.txt @@ -0,0 +1,48 @@ + [ req ] + distinguished_name = req_distinguished_name + x509_extensions = v3_ca + prompt = no + dirstring_type = nobmp + + [ req_distinguished_name ] + C = US + ST = TX + L = Dallas + O = Texas Instruments Incorporated + OU = Processors + CN = TI Support + emailAddress = support@ti.com + + [ v3_ca ] + basicConstraints = CA:true + 1.3.6.1.4.1.294.1.1 = ASN1:SEQUENCE:boot_seq + 1.3.6.1.4.1.294.1.2 = ASN1:SEQUENCE:image_integrity + 1.3.6.1.4.1.294.1.3 = ASN1:SEQUENCE:swrv +# 1.3.6.1.4.1.294.1.4 = ASN1:SEQUENCE:encryption + 1.3.6.1.4.1.294.1.8 = ASN1:SEQUENCE:debug + + [ boot_seq ] + certType = INTEGER:TEST_CERT_TYPE + bootCore = INTEGER:TEST_BOOT_CORE + bootCoreOpts = INTEGER:TEST_BOOT_ARCH_WIDTH + destAddr = FORMAT:HEX,OCT:TEST_BOOT_ADDR + imageSize = INTEGER:TEST_IMAGE_LENGTH + + [ image_integrity ] + shaType = OID:2.16.840.1.101.3.4.2.3 + shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL + + [ swrv ] + swrv = INTEGER:0 + +# [ encryption ] +# initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV +# randomString = FORMAT:HEX,OCT:TEST_IMAGE_ENC_RS +# iterationCnt = INTEGER:TEST_IMAGE_KEY_DERIVE_INDEX +# salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT + + [ debug ] + debugType = INTEGER:4 + coreDbgEn = INTEGER:0 + coreDbgSecEn = INTEGER:0 + debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 diff --git a/tools/mkimage.c b/tools/mkimage.c index 38805f0c92..ea5ed542ab 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -530,6 +530,13 @@ int main(int argc, char **argv) ret = imx8image_copy_image(ifd, ¶ms); if (ret) return ret; + } else if (params.type == IH_TYPE_IMX8MIMAGE) { + /* i.MX8M has special Image format */ + int ret; + + ret = imx8mimage_copy_image(ifd, ¶ms); + if (ret) + return ret; } else { copy_file(ifd, params.datafile, pad_len); } diff --git a/tools/mtk_image.c b/tools/mtk_image.c new file mode 100644 index 0000000000..2ca519483d --- /dev/null +++ b/tools/mtk_image.c @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generate MediaTek BootROM header for SPL/U-Boot images + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include "imagetool.h" +#include "mtk_image.h" + +/* NAND header for SPI-NAND with 2KB page + 64B spare */ +static const union nand_boot_header snand_hdr_2k_64_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, + 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, + 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, + 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, + 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 + } +}; + +/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ +static const union nand_boot_header snand_hdr_2k_128_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, + 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, + 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, + 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, + 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 + } +}; + +/* NAND header for SPI-NAND with 4KB page + 256B spare */ +static const union nand_boot_header snand_hdr_4k_256_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, + 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, + 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, + 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, + 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 + } +}; + +/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ +static const union nand_boot_header nand_hdr_1gb_2k_64_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, + 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, + 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, + 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, + 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 + } +}; + +/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ +static const union nand_boot_header nand_hdr_2gb_2k_64_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, + 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, + 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, + 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, + 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 + } +}; + +/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ +static const union nand_boot_header nand_hdr_4gb_2k_64_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, + 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, + 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, + 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, + 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 + } +}; + +/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ +static const union nand_boot_header nand_hdr_2gb_2k_128_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, + 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, + 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, + 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, + 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 + } +}; + +/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ +static const union nand_boot_header nand_hdr_4gb_2k_128_data = { + .data = { + 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, + 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, + 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, + 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, + 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, + 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, + 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, + 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 + } +}; + +static const struct nand_header_type { + const char *name; + const union nand_boot_header *data; +} nand_headers[] = { + { + .name = "2k+64", + .data = &snand_hdr_2k_64_data + }, { + .name = "2k+120", + .data = &snand_hdr_2k_128_data + }, { + .name = "2k+128", + .data = &snand_hdr_2k_128_data + }, { + .name = "4k+256", + .data = &snand_hdr_4k_256_data + }, { + .name = "1g:2k+64", + .data = &nand_hdr_1gb_2k_64_data + }, { + .name = "2g:2k+64", + .data = &nand_hdr_2gb_2k_64_data + }, { + .name = "4g:2k+64", + .data = &nand_hdr_4gb_2k_64_data + }, { + .name = "2g:2k+128", + .data = &nand_hdr_2gb_2k_128_data + }, { + .name = "4g:2k+128", + .data = &nand_hdr_4gb_2k_128_data + } +}; + +static const struct brom_img_type { + const char *name; + enum brlyt_img_type type; +} brom_images[] = { + { + .name = "nand", + .type = BRLYT_TYPE_NAND + }, { + .name = "emmc", + .type = BRLYT_TYPE_EMMC + }, { + .name = "nor", + .type = BRLYT_TYPE_NOR + }, { + .name = "sdmmc", + .type = BRLYT_TYPE_SDMMC + }, { + .name = "snand", + .type = BRLYT_TYPE_SNAND + } +}; + +/* Image type selected by user */ +static enum brlyt_img_type hdr_media; +static int use_lk_hdr; + +/* LK image name */ +static char lk_name[32] = "U-Boot"; + +/* NAND header selected by user */ +static const union nand_boot_header *hdr_nand; + +/* GFH header + 2 * 4KB pages of NAND */ +static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; + +static int mtk_image_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_MTKIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int mtk_brom_parse_imagename(const char *imagename) +{ +#define is_blank_char(c) \ + ((c) == '\t' || (c) == '\n' || (c) == '\r' || (c) == ' ') + + char *buf = strdup(imagename), *key, *val, *end, *next; + int i; + + /* User passed arguments from image name */ + static const char *media = ""; + static const char *nandinfo = ""; + static const char *lk = ""; + + key = buf; + while (key) { + next = strchr(key, ';'); + if (next) + *next = 0; + + val = strchr(key, '='); + if (val) { + *val++ = 0; + + /* Trim key */ + while (is_blank_char(*key)) + key++; + + end = key + strlen(key) - 1; + while ((end >= key) && is_blank_char(*end)) + end--; + end++; + + if (is_blank_char(*end)) + *end = 0; + + /* Trim value */ + while (is_blank_char(*val)) + val++; + + end = val + strlen(val) - 1; + while ((end >= val) && is_blank_char(*end)) + end--; + end++; + + if (is_blank_char(*end)) + *end = 0; + + /* record user passed arguments */ + if (!strcmp(key, "media")) + media = val; + + if (!strcmp(key, "nandinfo")) + nandinfo = val; + + if (!strcmp(key, "lk")) + lk = val; + + if (!strcmp(key, "lkname")) + snprintf(lk_name, sizeof(lk_name), "%s", val); + } + + if (next) + key = next + 1; + else + break; + } + + /* if user specified LK image header, skip following checks */ + if (lk && lk[0] == '1') { + use_lk_hdr = 1; + free(buf); + return 0; + } + + /* parse media type */ + for (i = 0; i < ARRAY_SIZE(brom_images); i++) { + if (!strcmp(brom_images[i].name, media)) { + hdr_media = brom_images[i].type; + break; + } + } + + /* parse nand header type */ + for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { + if (!strcmp(nand_headers[i].name, nandinfo)) { + hdr_nand = nand_headers[i].data; + break; + } + } + + free(buf); + + if (hdr_media == BRLYT_TYPE_INVALID) { + fprintf(stderr, "Error: media type is invalid or missing.\n"); + fprintf(stderr, " Please specify -n \"media=\"\n"); + return -EINVAL; + } + + if ((hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) && + !hdr_nand) { + fprintf(stderr, "Error: nand info is invalid or missing.\n"); + fprintf(stderr, " Please specify -n \"media=%s;" + "nandinfo=\"\n", media); + return -EINVAL; + } + + return 0; +} + +static int mtk_image_check_params(struct image_tool_params *params) +{ + if (!params->addr) { + fprintf(stderr, "Error: Load Address must be set.\n"); + return -EINVAL; + } + + if (!params->imagename) { + fprintf(stderr, "Error: Image Name must be set.\n"); + return -EINVAL; + } + + return mtk_brom_parse_imagename(params->imagename); +} + +static int mtk_image_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + if (use_lk_hdr) { + tparams->header_size = sizeof(union lk_hdr); + tparams->hdr = &hdr_tmp; + memset(&hdr_tmp, 0xff, tparams->header_size); + return 0; + } + + if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) + tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); + else + tparams->header_size = sizeof(struct gen_device_header); + + tparams->header_size += sizeof(struct gfh_header); + tparams->hdr = &hdr_tmp; + + memset(&hdr_tmp, 0xff, tparams->header_size); + + return SHA256_SUM_LEN; +} + +static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) +{ + union gen_boot_header *gbh = (union gen_boot_header *)ptr; + struct brom_layout_header *bh; + struct gfh_header *gfh; + const char *bootmedia; + + if (!strcmp(gbh->name, SF_BOOT_NAME)) + bootmedia = "Serial NOR"; + else if (!strcmp(gbh->name, EMMC_BOOT_NAME)) + bootmedia = "eMMC"; + else if (!strcmp(gbh->name, SDMMC_BOOT_NAME)) + bootmedia = "SD/MMC"; + else + return -1; + + if (print) + printf("Boot Media: %s\n", bootmedia); + + if (le32_to_cpu(gbh->version) != 1 || + le32_to_cpu(gbh->size) != sizeof(union gen_boot_header)) + return -1; + + bh = (struct brom_layout_header *)(ptr + le32_to_cpu(gbh->size)); + + if (strcmp(bh->name, BRLYT_NAME)) + return -1; + + if (le32_to_cpu(bh->magic) != BRLYT_MAGIC || + (le32_to_cpu(bh->type) != BRLYT_TYPE_NOR && + le32_to_cpu(bh->type) != BRLYT_TYPE_EMMC && + le32_to_cpu(bh->type) != BRLYT_TYPE_SDMMC)) + return -1; + + gfh = (struct gfh_header *)(ptr + le32_to_cpu(bh->header_size)); + + if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) + return -1; + + if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) + return -1; + + if (print) + printf("Load Address: %08x\n", + le32_to_cpu(gfh->file_info.load_addr) + + le32_to_cpu(gfh->file_info.jump_offset)); + + return 0; +} + +static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) +{ + union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *bh; + struct gfh_header *gfh; + const char *bootmedia; + + if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || + strcmp(nh->id, NAND_BOOT_ID)) + return -1; + + bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); + + if (strcmp(bh->name, BRLYT_NAME)) + return -1; + + if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { + return -1; + } else { + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) + bootmedia = "Parallel NAND"; + else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) + bootmedia = "Serial NAND"; + else + return -1; + } + + if (print) { + printf("Boot Media: %s\n", bootmedia); + + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { + uint64_t capacity = + (uint64_t)le16_to_cpu(nh->numblocks) * + (uint64_t)le16_to_cpu(nh->pages_of_block) * + (uint64_t)le16_to_cpu(nh->pagesize) * 8; + printf("Capacity: %dGb\n", + (uint32_t)(capacity >> 30)); + } + + if (le16_to_cpu(nh->pagesize) >= 1024) + printf("Page Size: %dKB\n", + le16_to_cpu(nh->pagesize) >> 10); + else + printf("Page Size: %dB\n", + le16_to_cpu(nh->pagesize)); + + printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); + } + + gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); + + if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) + return -1; + + if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) + return -1; + + if (print) + printf("Load Address: %08x\n", + le32_to_cpu(gfh->file_info.load_addr) + + le32_to_cpu(gfh->file_info.jump_offset)); + + return 0; +} + +static int mtk_image_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + union lk_hdr *lk = (union lk_hdr *)ptr; + + /* nothing to verify for LK image header */ + if (le32_to_cpu(lk->magic) == LK_PART_MAGIC) + return 0; + + if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + return mtk_image_verify_nand_header(ptr, 0); + else + return mtk_image_verify_gen_header(ptr, 0); + + return -1; +} + +static void mtk_image_print_header(const void *ptr) +{ + union lk_hdr *lk = (union lk_hdr *)ptr; + + if (le32_to_cpu(lk->magic) == LK_PART_MAGIC) { + printf("Image Type: MediaTek LK Image\n"); + printf("Load Address: %08x\n", le32_to_cpu(lk->loadaddr)); + return; + } + + printf("Image Type: MediaTek BootROM Loadable Image\n"); + + if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + mtk_image_verify_nand_header(ptr, 1); + else + mtk_image_verify_gen_header(ptr, 1); +} + +static void put_brom_layout_header(struct brom_layout_header *hdr, int type) +{ + strncpy(hdr->name, BRLYT_NAME, sizeof(hdr->name)); + hdr->version = cpu_to_le32(1); + hdr->magic = cpu_to_le32(BRLYT_MAGIC); + hdr->type = cpu_to_le32(type); +} + +static void put_ghf_common_header(struct gfh_common_header *gfh, int size, + int type, int ver) +{ + memcpy(gfh->magic, GFH_HEADER_MAGIC, sizeof(gfh->magic)); + gfh->version = ver; + gfh->size = cpu_to_le16(size); + gfh->type = cpu_to_le16(type); +} + +static void put_ghf_header(struct gfh_header *gfh, int file_size, + int dev_hdr_size, int load_addr, int flash_type) +{ + memset(gfh, 0, sizeof(struct gfh_header)); + + /* GFH_FILE_INFO header */ + put_ghf_common_header(&gfh->file_info.gfh, sizeof(gfh->file_info), + GFH_TYPE_FILE_INFO, 1); + strncpy(gfh->file_info.name, GFH_FILE_INFO_NAME, + sizeof(gfh->file_info.name)); + gfh->file_info.unused = cpu_to_le32(1); + gfh->file_info.file_type = cpu_to_le16(1); + gfh->file_info.flash_type = flash_type; + gfh->file_info.sig_type = GFH_SIG_TYPE_SHA256; + gfh->file_info.load_addr = cpu_to_le32(load_addr - sizeof(*gfh)); + gfh->file_info.total_size = cpu_to_le32(file_size - dev_hdr_size); + gfh->file_info.max_size = cpu_to_le32(file_size); + gfh->file_info.hdr_size = sizeof(*gfh); + gfh->file_info.sig_size = SHA256_SUM_LEN; + gfh->file_info.jump_offset = sizeof(*gfh); + gfh->file_info.processed = cpu_to_le32(1); + + /* GFH_BL_INFO header */ + put_ghf_common_header(&gfh->bl_info.gfh, sizeof(gfh->bl_info), + GFH_TYPE_BL_INFO, 1); + gfh->bl_info.attr = cpu_to_le32(1); + + /* GFH_BROM_CFG header */ + put_ghf_common_header(&gfh->brom_cfg.gfh, sizeof(gfh->brom_cfg), + GFH_TYPE_BROM_CFG, 3); + gfh->brom_cfg.cfg_bits = cpu_to_le32( + GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS | + GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN | + GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN); + gfh->brom_cfg.usbdl_by_kcol0_timeout_ms = cpu_to_le32(5000); + + /* GFH_BL_SEC_KEY header */ + put_ghf_common_header(&gfh->bl_sec_key.gfh, sizeof(gfh->bl_sec_key), + GFH_TYPE_BL_SEC_KEY, 1); + + /* GFH_ANTI_CLONE header */ + put_ghf_common_header(&gfh->anti_clone.gfh, sizeof(gfh->anti_clone), + GFH_TYPE_ANTI_CLONE, 1); + gfh->anti_clone.ac_offset = cpu_to_le32(0x10); + gfh->anti_clone.ac_len = cpu_to_le32(0x80); + + /* GFH_BROM_SEC_CFG header */ + put_ghf_common_header(&gfh->brom_sec_cfg.gfh, + sizeof(gfh->brom_sec_cfg), + GFH_TYPE_BROM_SEC_CFG, 1); + gfh->brom_sec_cfg.cfg_bits = + cpu_to_le32(BROM_SEC_CFG_JTAG_EN | BROM_SEC_CFG_UART_EN); +} + +static void put_hash(uint8_t *buff, int size) +{ + sha256_context ctx; + + sha256_starts(&ctx); + sha256_update(&ctx, buff, size); + sha256_finish(&ctx, buff + size); +} + +static void mtk_image_set_gen_header(void *ptr, off_t filesize, + uint32_t loadaddr) +{ + struct gen_device_header *hdr = (struct gen_device_header *)ptr; + struct gfh_header *gfh; + const char *bootname = NULL; + + if (hdr_media == BRLYT_TYPE_NOR) + bootname = SF_BOOT_NAME; + else if (hdr_media == BRLYT_TYPE_EMMC) + bootname = EMMC_BOOT_NAME; + else if (hdr_media == BRLYT_TYPE_SDMMC) + bootname = SDMMC_BOOT_NAME; + + /* Generic device header */ + snprintf(hdr->boot.name, sizeof(hdr->boot.name), "%s", bootname); + hdr->boot.version = cpu_to_le32(1); + hdr->boot.size = cpu_to_le32(sizeof(hdr->boot)); + + /* BRLYT header */ + put_brom_layout_header(&hdr->brlyt, hdr_media); + hdr->brlyt.header_size = cpu_to_le32(sizeof(struct gen_device_header)); + hdr->brlyt.total_size = cpu_to_le32(filesize); + hdr->brlyt.header_size_2 = hdr->brlyt.header_size; + hdr->brlyt.total_size_2 = hdr->brlyt.total_size; + + /* GFH header */ + gfh = (struct gfh_header *)(ptr + sizeof(struct gen_device_header)); + put_ghf_header(gfh, filesize, sizeof(struct gen_device_header), + loadaddr, GFH_FLASH_TYPE_GEN); + + /* Generate SHA256 hash */ + put_hash((uint8_t *)gfh, + filesize - sizeof(struct gen_device_header) - SHA256_SUM_LEN); +} + +static void mtk_image_set_nand_header(void *ptr, off_t filesize, + uint32_t loadaddr) +{ + union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *brlyt; + struct gfh_header *gfh; + uint32_t payload_pages; + int i; + + /* NAND device header, repeat 4 times */ + for (i = 0; i < 4; i++) + memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); + + /* BRLYT header */ + payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / + le16_to_cpu(hdr_nand->pagesize); + brlyt = (struct brom_layout_header *) + (ptr + le16_to_cpu(hdr_nand->pagesize)); + put_brom_layout_header(brlyt, hdr_media); + brlyt->header_size = cpu_to_le32(2); + brlyt->total_size = cpu_to_le32(payload_pages); + brlyt->header_size_2 = brlyt->header_size; + brlyt->total_size_2 = brlyt->total_size; + brlyt->unused = cpu_to_le32(1); + + /* GFH header */ + gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); + put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), + loadaddr, GFH_FLASH_TYPE_NAND); + + /* Generate SHA256 hash */ + put_hash((uint8_t *)gfh, + filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); +} + +static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + union lk_hdr *lk = (union lk_hdr *)ptr; + + if (use_lk_hdr) { + lk->magic = cpu_to_le32(LK_PART_MAGIC); + lk->size = cpu_to_le32(sbuf->st_size - sizeof(union lk_hdr)); + lk->loadaddr = cpu_to_le32(params->addr); + lk->mode = 0xffffffff; /* must be non-zero */ + memset(lk->name, 0, sizeof(lk->name)); + strncpy(lk->name, lk_name, sizeof(lk->name)); + return; + } + + if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) + mtk_image_set_nand_header(ptr, sbuf->st_size, params->addr); + else + mtk_image_set_gen_header(ptr, sbuf->st_size, params->addr); +} + +U_BOOT_IMAGE_TYPE( + mtk_image, + "MediaTek BootROM Loadable Image support", + 0, + NULL, + mtk_image_check_params, + mtk_image_verify_header, + mtk_image_print_header, + mtk_image_set_header, + NULL, + mtk_image_check_image_types, + NULL, + mtk_image_vrec_header +); diff --git a/tools/mtk_image.h b/tools/mtk_image.h new file mode 100644 index 0000000000..0a9eab372b --- /dev/null +++ b/tools/mtk_image.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MediaTek BootROM header definitions + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#ifndef _MTK_IMAGE_H +#define _MTK_IMAGE_H + +/* Device header definitions */ + +/* Header for NOR/SD/eMMC */ +union gen_boot_header { + struct { + char name[12]; + __le32 version; + __le32 size; + }; + + uint8_t pad[0x200]; +}; + +#define EMMC_BOOT_NAME "EMMC_BOOT" +#define SF_BOOT_NAME "SF_BOOT" +#define SDMMC_BOOT_NAME "SDMMC_BOOT" + +/* Header for NAND */ +union nand_boot_header { + struct { + char name[12]; + char version[4]; + char id[8]; + __le16 ioif; + __le16 pagesize; + __le16 addrcycles; + __le16 oobsize; + __le16 pages_of_block; + __le16 numblocks; + __le16 writesize_shift; + __le16 erasesize_shift; + uint8_t dummy[60]; + uint8_t ecc_parity[28]; + }; + + uint8_t data[0x80]; +}; + +#define NAND_BOOT_NAME "BOOTLOADER!" +#define NAND_BOOT_VERSION "V006" +#define NAND_BOOT_ID "NFIINFO" + +/* BootROM layout header */ +struct brom_layout_header { + char name[8]; + __le32 version; + __le32 header_size; + __le32 total_size; + __le32 magic; + __le32 type; + __le32 header_size_2; + __le32 total_size_2; + __le32 unused; +}; + +#define BRLYT_NAME "BRLYT" +#define BRLYT_MAGIC 0x42424242 + +enum brlyt_img_type { + BRLYT_TYPE_INVALID = 0, + BRLYT_TYPE_NAND = 0x10002, + BRLYT_TYPE_EMMC = 0x10005, + BRLYT_TYPE_NOR = 0x10007, + BRLYT_TYPE_SDMMC = 0x10008, + BRLYT_TYPE_SNAND = 0x10009 +}; + +/* Combined device header for NOR/SD/eMMC */ +struct gen_device_header { + union gen_boot_header boot; + + union { + struct brom_layout_header brlyt; + uint8_t brlyt_pad[0x400]; + }; +}; + +/* BootROM header definitions */ +struct gfh_common_header { + uint8_t magic[3]; + uint8_t version; + __le16 size; + __le16 type; +}; + +#define GFH_HEADER_MAGIC "MMM" + +#define GFH_TYPE_FILE_INFO 0 +#define GFH_TYPE_BL_INFO 1 +#define GFH_TYPE_BROM_CFG 7 +#define GFH_TYPE_BL_SEC_KEY 3 +#define GFH_TYPE_ANTI_CLONE 2 +#define GFH_TYPE_BROM_SEC_CFG 8 + +struct gfh_file_info { + struct gfh_common_header gfh; + char name[12]; + __le32 unused; + __le16 file_type; + uint8_t flash_type; + uint8_t sig_type; + __le32 load_addr; + __le32 total_size; + __le32 max_size; + __le32 hdr_size; + __le32 sig_size; + __le32 jump_offset; + __le32 processed; +}; + +#define GFH_FILE_INFO_NAME "FILE_INFO" + +#define GFH_FLASH_TYPE_GEN 5 +#define GFH_FLASH_TYPE_NAND 2 + +#define GFH_SIG_TYPE_NONE 0 +#define GFH_SIG_TYPE_SHA256 1 + +struct gfh_bl_info { + struct gfh_common_header gfh; + __le32 attr; +}; + +struct gfh_brom_cfg { + struct gfh_common_header gfh; + __le32 cfg_bits; + __le32 usbdl_by_auto_detect_timeout_ms; + uint8_t unused[0x48]; + __le32 usbdl_by_kcol0_timeout_ms; + __le32 usbdl_by_flag_timeout_ms; + uint32_t pad; +}; + +#define GFH_BROM_CFG_USBDL_BY_AUTO_DETECT_TIMEOUT_EN 0x02 +#define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10 +#define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80 +#define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100 + +struct gfh_bl_sec_key { + struct gfh_common_header gfh; + uint8_t pad[0x20c]; +}; + +struct gfh_anti_clone { + struct gfh_common_header gfh; + uint8_t ac_b2k; + uint8_t ac_b2c; + uint16_t pad; + __le32 ac_offset; + __le32 ac_len; +}; + +struct gfh_brom_sec_cfg { + struct gfh_common_header gfh; + __le32 cfg_bits; + char customer_name[0x20]; + __le32 pad; +}; + +#define BROM_SEC_CFG_JTAG_EN 1 +#define BROM_SEC_CFG_UART_EN 2 + +struct gfh_header { + struct gfh_file_info file_info; + struct gfh_bl_info bl_info; + struct gfh_brom_cfg brom_cfg; + struct gfh_bl_sec_key bl_sec_key; + struct gfh_anti_clone anti_clone; + struct gfh_brom_sec_cfg brom_sec_cfg; +}; + +/* LK image header */ + +union lk_hdr { + struct { + __le32 magic; + __le32 size; + char name[32]; + __le32 loadaddr; + __le32 mode; + }; + + uint8_t data[512]; +}; + +#define LK_PART_MAGIC 0x58881688 + +#endif /* _MTK_IMAGE_H */