Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts: drivers/serial/serial.c The conflict above was a trivial case of adding one init function in each branch, and manually resolved in merge.
This commit is contained in:
Albert ARIBAUD
6
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
Normal file
6
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
Normal file
@@ -0,0 +1,6 @@
|
||||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x0 spl/u-boot-spl.bin
|
||||
CALL 0x14 0x0
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||||
LOAD 0x40000100 u-boot.bin
|
||||
CALL 0x40000100 0x0
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||||
8
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Normal file
8
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Normal file
@@ -0,0 +1,8 @@
|
||||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x0 spl/u-boot-spl.bin
|
||||
LOAD IVT 0x8000 0x14
|
||||
CALL HAB 0x8000 0x0
|
||||
LOAD 0x40000100 u-boot.bin
|
||||
LOAD IVT 0x8000 0x40000100
|
||||
CALL HAB 0x8000 0x0
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@@ -36,7 +36,7 @@ static void mxs_power_clock2pll(void)
|
||||
CLKCTRL_CLKSEQ_BYPASS_CPU);
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}
|
||||
|
||||
static void mxs_power_clear_auto_restart(void)
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static void mxs_power_set_auto_restart(void)
|
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{
|
||||
struct mxs_rtc_regs *rtc_regs =
|
||||
(struct mxs_rtc_regs *)MXS_RTC_BASE;
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@@ -49,10 +49,7 @@ static void mxs_power_clear_auto_restart(void)
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while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
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||||
;
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|
||||
/*
|
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* Due to the hardware design bug of mx28 EVK-A
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* we need to set the AUTO_RESTART bit.
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*/
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/* Do nothing if flag already set */
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if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
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return;
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|
||||
@@ -911,7 +908,7 @@ void mxs_power_init(void)
|
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mxs_ungate_power();
|
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|
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mxs_power_clock2xtal();
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mxs_power_clear_auto_restart();
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mxs_power_set_auto_restart();
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mxs_power_set_linreg();
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mxs_power_setup_5v_detect();
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|
||||
|
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@@ -11,10 +11,11 @@ include $(TOPDIR)/config.mk
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|
||||
LIB = $(obj)lib$(SOC).o
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|
||||
COBJS = soc.o clock.o
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COBJS-y = soc.o clock.o
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COBJS-$(CONFIG_SECURE_BOOT) += hab.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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|
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all: $(obj).depend $(LIB)
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|
||||
|
||||
104
arch/arm/cpu/armv7/mx6/hab.c
Normal file
104
arch/arm/cpu/armv7/mx6/hab.c
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hab.h>
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|
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/* -------- start of HAB API updates ------------*/
|
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#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
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#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
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#define hab_rvt_authenticate_image \
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
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#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
|
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#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
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#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
|
||||
|
||||
bool is_hab_enabled(void)
|
||||
{
|
||||
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
||||
struct fuse_bank *bank = &ocotp->bank[0];
|
||||
struct fuse_bank0_regs *fuse =
|
||||
(struct fuse_bank0_regs *)bank->fuse_regs;
|
||||
uint32_t reg = readl(&fuse->cfg5);
|
||||
|
||||
return (reg & 0x2) == 0x2;
|
||||
}
|
||||
|
||||
void display_event(uint8_t *event_data, size_t bytes)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
if (!(event_data && bytes > 0))
|
||||
return;
|
||||
|
||||
for (i = 0; i < bytes; i++) {
|
||||
if (i == 0)
|
||||
printf("\t0x%02x", event_data[i]);
|
||||
else if ((i % 8) == 0)
|
||||
printf("\n\t0x%02x", event_data[i]);
|
||||
else
|
||||
printf(" 0x%02x", event_data[i]);
|
||||
}
|
||||
}
|
||||
|
||||
int get_hab_status(void)
|
||||
{
|
||||
uint32_t index = 0; /* Loop index */
|
||||
uint8_t event_data[128]; /* Event data buffer */
|
||||
size_t bytes = sizeof(event_data); /* Event size in bytes */
|
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enum hab_config config = 0;
|
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enum hab_state state = 0;
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|
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if (is_hab_enabled())
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puts("\nSecure boot enabled\n");
|
||||
else
|
||||
puts("\nSecure boot disabled\n");
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|
||||
/* Check HAB status */
|
||||
if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
|
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
|
||||
config, state);
|
||||
|
||||
/* Display HAB Error events */
|
||||
while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
|
||||
&bytes) == HAB_SUCCESS) {
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||||
puts("\n");
|
||||
printf("--------- HAB Event %d -----------------\n",
|
||||
index + 1);
|
||||
puts("event data:\n");
|
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display_event(event_data, bytes);
|
||||
puts("\n");
|
||||
bytes = sizeof(event_data);
|
||||
index++;
|
||||
}
|
||||
}
|
||||
/* Display message if no HAB events are found */
|
||||
else {
|
||||
printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
|
||||
config, state);
|
||||
puts("No HAB Events Found!\n\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
if ((argc != 1)) {
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
get_hab_status();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
|
||||
"display HAB status",
|
||||
""
|
||||
);
|
||||
@@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = {
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
int is_6q = is_cpu_type(MXC_CPU_MX6Q);
|
||||
u32 mask480;
|
||||
u32 mask528;
|
||||
|
||||
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
|
||||
* to make sure PFD is working right, otherwise, PFDs may
|
||||
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
|
||||
* workaround in ROM code, as bus clock need it
|
||||
*/
|
||||
|
||||
mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
|
||||
ANATOP_PFD_CLKGATE_MASK(1) |
|
||||
ANATOP_PFD_CLKGATE_MASK(2) |
|
||||
ANATOP_PFD_CLKGATE_MASK(3);
|
||||
mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
|
||||
ANATOP_PFD_CLKGATE_MASK(1) |
|
||||
ANATOP_PFD_CLKGATE_MASK(3);
|
||||
|
||||
/*
|
||||
* Don't reset PFD2 on DL/S
|
||||
*/
|
||||
if (is_6q)
|
||||
mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
|
||||
writel(mask480, &anatop->pfd_480_set);
|
||||
writel(mask528, &anatop->pfd_528_set);
|
||||
writel(mask480, &anatop->pfd_480_clr);
|
||||
writel(mask528, &anatop->pfd_528_clr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMX_HDMI
|
||||
|
||||
67
arch/arm/include/asm/arch-mx6/hab.h
Normal file
67
arch/arm/include/asm/arch-mx6/hab.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SECURE_MX6Q_H__
|
||||
#define __SECURE_MX6Q_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* -------- start of HAB API updates ------------*/
|
||||
/* The following are taken from HAB4 SIS */
|
||||
|
||||
/* Status definitions */
|
||||
enum hab_status {
|
||||
HAB_STS_ANY = 0x00,
|
||||
HAB_FAILURE = 0x33,
|
||||
HAB_WARNING = 0x69,
|
||||
HAB_SUCCESS = 0xf0
|
||||
};
|
||||
|
||||
/* Security Configuration definitions */
|
||||
enum hab_config {
|
||||
HAB_CFG_RETURN = 0x33, /**< Field Return IC */
|
||||
HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
|
||||
HAB_CFG_CLOSED = 0xcc /**< Secure IC */
|
||||
};
|
||||
|
||||
/* State definitions */
|
||||
enum hab_state {
|
||||
HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
|
||||
HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
|
||||
HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
|
||||
HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
|
||||
HAB_STATE_SECURE = 0xaa, /**< Secure state */
|
||||
HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
|
||||
HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
|
||||
HAB_STATE_NONE = 0xf0, /**< No security state machine */
|
||||
HAB_STATE_MAX
|
||||
};
|
||||
|
||||
/*Function prototype description*/
|
||||
typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
|
||||
uint8_t* , size_t*);
|
||||
typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
|
||||
enum hab_state *);
|
||||
typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
|
||||
typedef enum hab_status hab_rvt_entry_t(void);
|
||||
typedef enum hab_status hab_rvt_exit_t(void);
|
||||
typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
|
||||
void **, size_t *, hab_loader_callback_f_t);
|
||||
typedef void hapi_clock_init_t(void);
|
||||
|
||||
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
|
||||
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
|
||||
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
|
||||
#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
|
||||
#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
|
||||
#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
|
||||
|
||||
#define HAB_CID_ROM 0 /**< ROM Caller ID */
|
||||
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
|
||||
/* ----------- end of HAB API updates ------------*/
|
||||
|
||||
#endif
|
||||
@@ -456,7 +456,13 @@ struct fuse_bank0_regs {
|
||||
u32 uid_low;
|
||||
u32 rsvd1[3];
|
||||
u32 uid_high;
|
||||
u32 rsvd2[0x17];
|
||||
u32 rsvd2[3];
|
||||
u32 rsvd3[4];
|
||||
u32 rsvd4[4];
|
||||
u32 rsvd5[4];
|
||||
u32 cfg5;
|
||||
u32 rsvd6[3];
|
||||
u32 rsvd7[4];
|
||||
};
|
||||
|
||||
struct fuse_bank4_regs {
|
||||
@@ -629,29 +635,12 @@ struct anatop_regs {
|
||||
u32 digprog_sololite; /* 0x280 */
|
||||
};
|
||||
|
||||
#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
|
||||
#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
|
||||
#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
|
||||
#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
|
||||
#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
|
||||
#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
|
||||
#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
|
||||
#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
|
||||
#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
|
||||
#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
|
||||
#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
|
||||
#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
|
||||
#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
|
||||
#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
|
||||
#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
|
||||
#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
|
||||
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
|
||||
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
|
||||
|
||||
struct iomuxc_base_regs {
|
||||
u32 gpr[14]; /* 0x000 */
|
||||
|
||||
@@ -19,6 +19,13 @@
|
||||
|
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/* returns MXC_CPU_ value */
|
||||
#define cpu_type(rev) (((rev) >> 12)&0xff)
|
||||
|
||||
/* use with MXC_CPU_ constants */
|
||||
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
|
||||
|
||||
const char *get_imx_type(u32 imxtype);
|
||||
unsigned imx_ddr_size(void);
|
||||
|
||||
|
||||
220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
Normal file
220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
Normal file
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Freescale MXS UARTAPP Register Definitions
|
||||
*
|
||||
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
|
||||
*
|
||||
* Based on code from LTIB:
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM___MXS_UARTAPP_H
|
||||
#define __ARCH_ARM___MXS_UARTAPP_H
|
||||
|
||||
#include <asm/imx-common/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_uartapp_regs {
|
||||
mxs_reg_32(hw_uartapp_ctrl0)
|
||||
mxs_reg_32(hw_uartapp_ctrl1)
|
||||
mxs_reg_32(hw_uartapp_ctrl2)
|
||||
mxs_reg_32(hw_uartapp_linectrl)
|
||||
mxs_reg_32(hw_uartapp_linectrl2)
|
||||
mxs_reg_32(hw_uartapp_intr)
|
||||
mxs_reg_32(hw_uartapp_data)
|
||||
mxs_reg_32(hw_uartapp_stat)
|
||||
mxs_reg_32(hw_uartapp_debug)
|
||||
mxs_reg_32(hw_uartapp_version)
|
||||
mxs_reg_32(hw_uartapp_autobaud)
|
||||
};
|
||||
#endif
|
||||
|
||||
#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
|
||||
#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
|
||||
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
|
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#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
|
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#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
|
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#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
|
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#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
|
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#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
|
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#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
|
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|
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#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
|
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#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
|
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#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
|
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#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
|
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#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
|
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#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
|
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#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
|
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#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
|
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#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
|
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#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
|
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#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
|
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#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
|
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#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
|
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#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
|
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#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
|
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|
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#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
|
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#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
|
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#define UARTAPP_CTRL2_UARTEN_MASK 0x01
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
|
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#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
|
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#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
|
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|
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
|
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#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
|
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#define UARTAPP_LINECTRL_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
|
||||
#define UARTAPP_LINECTRL_BRK_MASK 1
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
|
||||
|
||||
#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
|
||||
#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
|
||||
#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
|
||||
#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
|
||||
#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
|
||||
#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
|
||||
#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
|
||||
#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
|
||||
#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
|
||||
#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
|
||||
#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
|
||||
#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
|
||||
|
||||
#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
|
||||
#define UARTAPP_INTR_OEIS_MASK (1 << 10)
|
||||
#define UARTAPP_INTR_BEIS_MASK (1 << 9)
|
||||
#define UARTAPP_INTR_PEIS_MASK (1 << 8)
|
||||
#define UARTAPP_INTR_FEIS_MASK (1 << 7)
|
||||
#define UARTAPP_INTR_RTIS_MASK (1 << 6)
|
||||
#define UARTAPP_INTR_TXIS_MASK (1 << 5)
|
||||
#define UARTAPP_INTR_RXIS_MASK (1 << 4)
|
||||
#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
|
||||
#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
|
||||
#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
|
||||
#define UARTAPP_INTR_RIMIS_MASK 0x1
|
||||
|
||||
#define UARTAPP_DATA_DATA_OFFSET 0
|
||||
#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
|
||||
#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
|
||||
|
||||
#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
|
||||
|
||||
#define UARTAPP_STAT_BUSY_MASK (1 << 29)
|
||||
#define UARTAPP_STAT_CTS_MASK (1 << 28)
|
||||
#define UARTAPP_STAT_TXFE_MASK (1 << 27)
|
||||
#define UARTAPP_STAT_RXFF_MASK (1 << 26)
|
||||
#define UARTAPP_STAT_TXFF_MASK (1 << 25)
|
||||
#define UARTAPP_STAT_RXFE_MASK (1 << 24)
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
|
||||
|
||||
#define UARTAPP_STAT_OERR_MASK (1 << 19)
|
||||
#define UARTAPP_STAT_BERR_MASK (1 << 18)
|
||||
#define UARTAPP_STAT_PERR_MASK (1 << 17)
|
||||
#define UARTAPP_STAT_FERR_MASK (1 << 16)
|
||||
#define UARTAPP_STAT_RXCOUNT_OFFSET 0
|
||||
#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
|
||||
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
|
||||
|
||||
#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
|
||||
#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
|
||||
#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
|
||||
#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
|
||||
#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
|
||||
#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
|
||||
|
||||
#define UARTAPP_VERSION_MAJOR_OFFSET 24
|
||||
#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_VERSION_MINOR_OFFSET 16
|
||||
#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_VERSION_STEP_OFFSET 0
|
||||
#define UARTAPP_VERSION_STEP_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
|
||||
#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
|
||||
#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
|
||||
#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
|
||||
#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
|
||||
#endif /* __ARCH_ARM___UARTAPP_H */
|
||||
Reference in New Issue
Block a user