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Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini
2016-01-27 15:05:12 -05:00
parent b20c38a973 f36919a813
commit 19bde0316f
108 changed files with 1191 additions and 1290 deletions
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12
board/avnet/fx12mm/Kconfig
View File

@@ -1,12 +0,0 @@
if TARGET_FX12MM
config SYS_BOARD
default "fx12mm"
config SYS_VENDOR
default "avnet"
config SYS_CONFIG_NAME
default "fx12mm"
endif

7
board/avnet/fx12mm/MAINTAINERS
View File

@@ -1,7 +0,0 @@
FX12MM BOARD
M: Georg Schardt <schardt@team-ctech.de>
S: Maintained
F: board/avnet/fx12mm/
F: include/configs/fx12mm.h
F: configs/fx12mm_defconfig
F: configs/fx12mm_flash_defconfig

11
board/avnet/fx12mm/Makefile
View File

@@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += fx12mm.o
include $(srctree)/board/xilinx/ppc405-generic/Makefile

34
board/avnet/fx12mm/fx12mm.c
View File

@@ -1,34 +0,0 @@
/*
* (C) Copyright 2008
*
* Author: Xilinx Inc.
*
* Modified by:
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
char buf[64];
int i;
int l = getenv_f("serial#", buf, sizeof(buf));
if (l < 0) {
printf("Avnet Virtex4 FX12 with no serial #");
} else {
printf("Avnet Virtex4 FX12 Minimodul # ");
for (i = 0; i < l; ++i) {
if (buf[i] == ' ')
break;
putc(buf[i]);
}
}
putc('\n');
return 0;
}

35
board/avnet/fx12mm/xparameters.h
View File

@@ -1,35 +0,0 @@
/*
* (C) Copyright 2008
*
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* CAUTION: This file is based on the xparameters.h automatically
* generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
*/
#ifndef __XPARAMETER_H__
#define __XPARAMETER_H__
/* RS232 */
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
/* INT_C */
#define XPAR_XPS_INTC_0_DEVICE_ID 0
#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
/* CPU core clock */
#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
/* RAM */
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
/* FLASH */
#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
#endif

12
board/avnet/v5fx30teval/Kconfig
View File

@@ -1,12 +0,0 @@
if TARGET_V5FX30TEVAL
config SYS_BOARD
default "v5fx30teval"
config SYS_VENDOR
default "avnet"
config SYS_CONFIG_NAME
default "v5fx30teval"
endif

7
board/avnet/v5fx30teval/MAINTAINERS
View File

@@ -1,7 +0,0 @@
V5FX30TEVAL BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
S: Maintained
F: board/avnet/v5fx30teval/
F: include/configs/v5fx30teval.h
F: configs/v5fx30teval_defconfig
F: configs/v5fx30teval_flash_defconfig

11
board/avnet/v5fx30teval/Makefile
View File

@@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += v5fx30teval.o
include $(srctree)/board/xilinx/ppc440-generic/Makefile

17
board/avnet/v5fx30teval/v5fx30teval.c
View File

@@ -1,17 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Avnet Virtex 5 FX30 Evaluation Board\n");
return 0;
}

22
board/avnet/v5fx30teval/xparameters.h
View File

@@ -1,22 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters.h by Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

41
board/xilinx/microblaze-generic/microblaze-generic.c
View File

@@ -12,7 +12,6 @@
#include <common.h>
#include <config.h>
#include <fdtdec.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
@@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
static int reset_pin = -1;
#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
ulong ram_base;
void dram_init_banksize(void)
@@ -58,14 +56,6 @@ int dram_init(void)
return 0;
};
#else
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
int gpio_init (void)
static int gpio_init(void)
{
#ifdef CONFIG_XILINX_GPIO
reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
@@ -96,32 +86,9 @@ int gpio_init (void)
return 0;
}
void board_init(void)
int board_late_init(void)
{
gpio_init();
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR)
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
return ret;
return 0;
}

21
board/xilinx/microblaze-generic/xparameters.h
View File

@@ -28,15 +28,6 @@
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is RS232_Uart */
#define XILINX_UARTLITE_BASEADDR 0x40600000
#define XILINX_UARTLITE_BAUDRATE 115200
/* IIC pheriphery is IIC_EEPROM */
#define XILINX_IIC_0_BASEADDR 0x40800000
#define XILINX_IIC_0_FREQ 100000
#define XILINX_IIC_0_BIT 0
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
@@ -44,18 +35,6 @@
#define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is DDR_SDRAM_64Mx32 */
#define XILINX_RAM_START 0x28000000
#define XILINX_RAM_SIZE 0x04000000
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XILINX_EMACLITE_BASEADDR 0x40C00000
/* Watchdog IP is wxi_timebase_wdt_0 */
#define XILINX_WATCHDOG_BASEADDR 0x50000000
#define XILINX_WATCHDOG_IRQ 1

12
board/xilinx/ml507/Kconfig
View File

@@ -1,12 +0,0 @@
if TARGET_ML507
config SYS_BOARD
default "ml507"
config SYS_VENDOR
default "xilinx"
config SYS_CONFIG_NAME
default "ml507"
endif

7
board/xilinx/ml507/MAINTAINERS
View File

@@ -1,7 +0,0 @@
ML507 BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
S: Maintained
F: board/xilinx/ml507/
F: include/configs/ml507.h
F: configs/ml507_defconfig
F: configs/ml507_flash_defconfig

11
board/xilinx/ml507/Makefile
View File

@@ -1,11 +0,0 @@
#
# (C) Copyright 2008
# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
# This work has been supported by: Qtechnology http://qtec.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ml507.o
include $(srctree)/board/xilinx/ppc440-generic/Makefile

17
board/xilinx/ml507/ml507.c
View File

@@ -1,17 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("Xilinx ML507 Board\n");
return 0;
}

23
board/xilinx/ml507/xparameters.h
View File

@@ -1,23 +0,0 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XPARAMETER_H
#define XPARAMETER_H
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#endif

2
board/xilinx/ppc405-generic/MAINTAINERS
View File

@@ -1,5 +1,5 @@
PPC405-GENERIC BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc405-generic/
F: include/configs/xilinx-ppc405-generic.h

4
board/xilinx/ppc405-generic/Makefile
View File

@@ -3,10 +3,10 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
obj-y += xilinx_ppc405_generic.o

31
board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
@@ -10,39 +10,32 @@
#include <common.h>
#include <asm/processor.h>
ulong __get_PCI_freq(void)
ulong get_PCI_freq(void)
{
return 0;
}
ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
int checkboard(void)
{
puts("Xilinx PPC405 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
void get_sys_info(sys_info_t *sys_info)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sys_info->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

7
board/xilinx/ppc405-generic/xparameters.h
View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
@@ -14,12 +14,11 @@
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_SPI_0_BASEADDR 0x83400000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif

2
board/xilinx/ppc440-generic/MAINTAINERS
View File

@@ -1,5 +1,5 @@
PPC440-GENERIC BOARD
M: Ricardo Ribalda <ricardo.ribalda@uam.es>
M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc440-generic/
F: include/configs/xilinx-ppc440-generic.h

6
board/xilinx/ppc440-generic/Makefile
View File

@@ -3,11 +3,11 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
extra-y += ../../xilinx/ppc440-generic/init.o
obj-y += xilinx_ppc440_generic.o
extra-y += init.o

2
board/xilinx/ppc440-generic/init.S
View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+

49
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
@@ -8,34 +8,51 @@
#include <config.h>
#include <common.h>
#include <netdev.h>
#include <asm/processor.h>
int __board_pre_init(void)
{
return 0;
}
int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
int __checkboard(void)
int checkboard(void)
{
puts("Xilinx PPC440 Generic Board\n");
return 0;
}
int checkboard(void) __attribute__((weak, alias("__checkboard")));
phys_size_t __initdram(int board_type)
phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
void __get_sys_info(sys_info_t *sysInfo)
void get_sys_info(sys_info_t *sys_info)
{
sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sysInfo->freqPCI = 0;
sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
sys_info->freqPCI = 0;
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
puts("Init xilinx temac\n");
#ifdef XPAR_LLTEMAC_0_BASEADDR
ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
#endif
#ifdef XPAR_LLTEMAC_1_BASEADDR
ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
#endif
return ret;
}

15
board/xilinx/ppc440-generic/xparameters.h
View File

@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
@@ -12,12 +12,15 @@
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_INTC_0_BASEADDR 0x87000000
#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
#define XPAR_UARTLITE_0_BAUDRATE 9600
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
#define XPAR_LLTEMAC_0_BASEADDR 0x83000000
#define XPAR_LLTEMAC_1_BASEADDR 0x83000040
#endif

26
board/xilinx/zynq/board.c
View File

@@ -8,7 +8,6 @@
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@@ -94,34 +93,11 @@ int board_late_init(void)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board:\tXilinx Zynq\n");
puts("Board: Xilinx Zynq\n");
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
#ifdef CONFIG_XILINX_EMACLITE
u32 txpp = 0;
u32 rxpp = 0;
# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
txpp = 1;
# endif
# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
rxpp = 1;
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
return ret;
}
int dram_init(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)

49
board/xilinx/zynqmp/zynqmp.c
View File

@@ -9,6 +9,7 @@
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
@@ -28,10 +29,18 @@ int board_early_init_r(void)
{
u32 val;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
if (current_el() == 3) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
/* Program freq register in System counter */
writel(zynqmp_get_system_timer_freq(),
&iou_scntr_secure->base_frequency_id_register);
/* And enable system counter */
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
&iou_scntr_secure->counter_control_register);
}
/* Program freq register in System counter and enable system counter */
writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
@@ -48,11 +57,6 @@ int dram_init(void)
return 0;
}
int timer_init(void)
{
return 0;
}
void reset_cpu(ulong addr)
{
}
@@ -73,11 +77,36 @@ int board_late_init(void)
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
puts("Bootmode: ");
switch (bootmode) {
case SD_MODE:
case JTAG_MODE:
puts("JTAG_MODE\n");
setenv("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
setenv("modeboot", "qspiboot");
puts("QSPI_MODE\n");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE:
puts("SD_MODE\n");
setenv("modeboot", "sdboot");
break;
case SD_MODE1:
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
setenv("sdbootdev", "1");
#endif
setenv("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
setenv("modeboot", "nandboot");
break;
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
@@ -88,7 +117,7 @@ int board_late_init(void)
int checkboard(void)
{
puts("Board:\tXilinx ZynqMP\n");
puts("Board: Xilinx ZynqMP\n");
return 0;
}