mtd: spi-nor-core: Add a ->setup() hook
nor->setup() can be used by flashes to configure settings in case they have any peculiarities that can't be easily expressed by the generic spi-nor framework. This includes things like different opcodes, dummy cycles, page size, uniform/non-uniform sector sizes, etc. Move related declarations to avoid forward declarations. Inspired by the Linux kernel's setup() hook. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pratyush Yadav
Jagan Teki
parent
1af0334ab4
commit
18b0de0f3b
@ -1451,71 +1451,6 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
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#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
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#endif /* CONFIG_SPI_FLASH_SPANSION */
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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struct spi_nor_pp_command {
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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SNOR_CMD_READ_1_1_1_DTR,
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/* Dual SPI */
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SNOR_CMD_READ_1_1_2,
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SNOR_CMD_READ_1_2_2,
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SNOR_CMD_READ_2_2_2,
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SNOR_CMD_READ_1_2_2_DTR,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_1_4_4,
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octo SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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SNOR_CMD_READ_1_8_8_DTR,
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SNOR_CMD_READ_MAX
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};
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enum spi_nor_pp_command_index {
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SNOR_CMD_PP,
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/* Quad SPI */
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SNOR_CMD_PP_1_1_4,
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octo SPI */
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SNOR_CMD_PP_1_1_8,
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SNOR_CMD_PP_1_8_8,
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SNOR_CMD_PP_8_8_8,
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SNOR_CMD_PP_MAX
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};
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
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int (*quad_enable)(struct spi_nor *nor);
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};
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static void
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spi_nor_set_read_settings(struct spi_nor_read_command *read,
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u8 num_mode_clocks,
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@ -2377,9 +2312,10 @@ static int spi_nor_select_erase(struct spi_nor *nor,
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return 0;
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}
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static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps)
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static int spi_nor_default_setup(struct spi_nor *nor,
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const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps)
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{
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u32 ignored_mask, shared_mask;
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bool enable_quad_io;
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@ -2438,6 +2374,16 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
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return 0;
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}
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static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps)
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{
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if (!nor->setup)
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return 0;
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return nor->setup(nor, info, params, hwcaps);
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}
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static int spi_nor_init(struct spi_nor *nor)
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{
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int err;
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@ -2504,6 +2450,8 @@ int spi_nor_scan(struct spi_nor *nor)
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nor->read_reg = spi_nor_read_reg;
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nor->write_reg = spi_nor_write_reg;
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nor->setup = spi_nor_default_setup;
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if (spi->mode & SPI_RX_OCTAL) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
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@ -555,28 +555,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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}
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#endif /* CONFIG_SPI_FLASH_SPANSION */
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_MAX
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};
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struct spi_nor_flash_parameter {
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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};
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static void
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spi_nor_set_read_settings(struct spi_nor_read_command *read,
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u8 num_mode_clocks,
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@ -249,6 +249,134 @@ enum spi_nor_option_flags {
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SNOR_F_BROKEN_RESET = BIT(6),
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};
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struct spi_nor;
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/**
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* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
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* supported by the SPI controller (bus master).
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* @mask: the bitmask listing all the supported hw capabilies
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*/
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struct spi_nor_hwcaps {
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u32 mask;
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};
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/*
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*(Fast) Read capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* As a matter of performances, it is relevant to use Octo SPI protocols first,
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* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
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* (Slow) Read.
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*/
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#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
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#define SNOR_HWCAPS_READ BIT(0)
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#define SNOR_HWCAPS_READ_FAST BIT(1)
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#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
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#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
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#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
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#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
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#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
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#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
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#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
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#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
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#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
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#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
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#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
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#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
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#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
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#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
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#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
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#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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/*
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* Page Program capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
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* legacy SPI 1-1-1 protocol.
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* Note that Dual Page Programs are not supported because there is no existing
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* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
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* implements such commands.
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*/
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#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
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#define SNOR_HWCAPS_PP BIT(16)
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#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
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#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
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#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
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#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
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#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
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#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
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#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
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#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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struct spi_nor_pp_command {
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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SNOR_CMD_READ_1_1_1_DTR,
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/* Dual SPI */
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SNOR_CMD_READ_1_1_2,
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SNOR_CMD_READ_1_2_2,
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SNOR_CMD_READ_2_2_2,
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SNOR_CMD_READ_1_2_2_DTR,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_1_4_4,
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octo SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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SNOR_CMD_READ_1_8_8_DTR,
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SNOR_CMD_READ_MAX
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};
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enum spi_nor_pp_command_index {
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SNOR_CMD_PP,
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/* Quad SPI */
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SNOR_CMD_PP_1_1_4,
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octo SPI */
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SNOR_CMD_PP_1_1_8,
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SNOR_CMD_PP_1_8_8,
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SNOR_CMD_PP_8_8_8,
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SNOR_CMD_PP_MAX
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};
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
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int (*quad_enable)(struct spi_nor *nor);
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};
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/**
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* struct flash_info - Forward declaration of a structure used internally by
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* spi_nor_scan()
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@ -330,6 +458,9 @@ struct spi_nor {
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u32 flags;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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int (*setup)(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params,
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const struct spi_nor_hwcaps *hwcaps);
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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@ -368,67 +499,6 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor)
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}
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#endif /* __UBOOT__ */
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/**
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* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
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* supported by the SPI controller (bus master).
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* @mask: the bitmask listing all the supported hw capabilies
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*/
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struct spi_nor_hwcaps {
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u32 mask;
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};
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/*
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*(Fast) Read capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* As a matter of performances, it is relevant to use Octo SPI protocols first,
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* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
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* (Slow) Read.
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*/
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#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
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#define SNOR_HWCAPS_READ BIT(0)
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#define SNOR_HWCAPS_READ_FAST BIT(1)
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#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
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#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
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#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
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#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
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#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
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#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
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#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
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#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
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#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
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#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
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#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
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#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
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#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
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#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
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#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
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#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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/*
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* Page Program capabilities.
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* MUST be ordered by priority: the higher bit position, the higher priority.
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* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
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* legacy SPI 1-1-1 protocol.
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* Note that Dual Page Programs are not supported because there is no existing
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* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
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* implements such commands.
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*/
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#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
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#define SNOR_HWCAPS_PP BIT(16)
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#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
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#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
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#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
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#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
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#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
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#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
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#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
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#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
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/**
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* spi_nor_scan() - scan the SPI NOR
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* @nor: the spi_nor structure
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