Xilinx fixes for v2018.09-rc2

xilinx:
 - Add support for zybo z7 and ultra96
 - Tune zynq and zynqmp mini configurations
 - Move SYS_MALLOC_LEN to Kconfig
 
 fdt
  - make static funcs
 
 gpio:
 - Fix soft gpio driver
 - Fix Zynq gpio driver by using platdata
 
 microblaze:
 - Fix Kconfig entry
 
 spi
 - Move ISSI to Kconfig
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Merge tag 'xilinx-for-v2018.09-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.09-rc2

xilinx:
- Add support for zybo z7 and ultra96
- Tune zynq and zynqmp mini configurations
- Move SYS_MALLOC_LEN to Kconfig

fdt
 - make static funcs

gpio:
- Fix soft gpio driver
- Fix Zynq gpio driver by using platdata

microblaze:
- Fix Kconfig entry

spi
- Move ISSI to Kconfig

Kconfig

@@ -136,6 +136,13 @@ config SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
+config SYS_MALLOC_LEN
+	hex "Define memory for Dynamic allocation"
+	depends on ARCH_ZYNQ
+	help
+	  This defines memory to be allocated for Dynamic allocation
+	  TODO: Use for other architectures
+
 config SPL_SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool in SPL before relocation"
 	depends on SYS_MALLOC_F

MAINTAINERS

@@ -317,6 +317,7 @@ F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
 F:	tools/zynqmp*
+N:	ultra96
 N:	zynqmp
 
 ARM ZYNQMP R5

arch/arm/dts/Makefile

@@ -149,8 +149,10 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zc770-xm013.dtb \
 	zynq-zed.dtb \
 	zynq-zturn.dtb \
-	zynq-zybo.dtb
+	zynq-zybo.dtb \
+	zynq-zybo-z7.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
+	avnet-ultra96-rev1.dtb			\
 	zynqmp-mini-emmc0.dtb			\
 	zynqmp-mini-emmc1.dtb			\
 	zynqmp-mini-nand.dtb			\

arch/arm/dts/avnet-ultra96-rev1.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet Ultra96 rev1
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu100-revC.dts"
+
+/ {
+	model = "Avnet Ultra96 Rev1";
+	compatible = "avnet,ultra96-rev1", "avnet,ultra96",
+		     "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
+		     "xlnx,zynqmp";
+};

arch/arm/dts/zynq-cse-nand.dts

@@ -38,7 +38,7 @@
 		#size-cells = <1>;
 		ranges;
 
-			slcr: slcr@f8000000 {
+		slcr: slcr@f8000000 {
 			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -72,7 +72,6 @@
 			};
 		};
 	};
-
 };
 
 &dcc {

arch/arm/dts/zynq-cse-nor.dts

@@ -56,7 +56,6 @@
 			clkc: clkc@100 {
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
-				fclk-enable = <0xf>;
 				clock-output-names = "armpll", "ddrpll",
 						"iopll", "cpu_6or4x",
 						"cpu_3or2x", "cpu_2x", "cpu_1x",
@@ -80,7 +79,6 @@
 			};
 		};
 	};
-
 };
 
 &dcc {

arch/arm/dts/zynq-zed.dts

@@ -51,6 +51,13 @@
 &qspi {
 	u-boot,dm-pre-reloc;
 	status = "okay";
+	num-cs = <1>;
+	flash@0 {
+		compatible = "spansion,s25fl256s", "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		m25p,fast-read;
+	};
 };
 
 &sdhci0 {

arch/arm/dts/zynq-zybo-z7.dts

@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Digilent Zybo Z7 board";
+	compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "";
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		ld4 {
+			label = "zynq-zybo-z7:green:ld4";
+			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	usb_phy0: phy0 {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+		device_type = "ethernet-phy";
+	};
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

arch/arm/dts/zynqmp-mini-emmc1.dts

@@ -52,7 +52,8 @@
 			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 			status = "disabled";
 			reg = <0x0 0xff170000 0x0 0x1000>;
-			clock-names = "clk_xin", "clk_xin";
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&clk_xin &clk_xin>;
 			xlnx,device_id = <1>;
 		};
 	};

arch/arm/mach-zynq/Kconfig

@@ -57,6 +57,9 @@ config SYS_CONFIG_NAME
 config SYS_MALLOC_F_LEN
 	default 0x600
 
+config SYS_MALLOC_LEN
+	default 0x1400000
+
 config BOOT_INIT_FILE
 	string "boot.bin init register filename"
 	default ""

board/xilinx/microblaze-generic/Kconfig

@@ -36,6 +36,6 @@ config XILINX_MICROBLAZE0_USE_HW_MUL
 
 config XILINX_MICROBLAZE0_HW_VER
 	string "Core version number"
-	default 7.10.d
+	default "7.10.d"
 
 endif

board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c

@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ *   (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ *   - Add "ZYNQ7 Processing System" IP
+ *   - Run "Block Automation" (Check "Apply Board Preset")
+ *   - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ *   - Save diagram changes
+ *   - Go to sources view, select the block diagram,
+ *     and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ *   and the checkpatch.pl script
+ *
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C00U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00028800U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000073U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000BCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000B3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	int ret = -1;
+
+	ret = ps7_config(ps7_post_config_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}

board/xilinx/zynqmp/avnet-ultra96-rev1

@@ -0,0 +1 @@
+zynqmp-zcu100-revC

common/fdt_support.c

@@ -725,7 +725,7 @@ struct reg_cell {
 	unsigned int r1;
 };
 
-int fdt_del_subnodes(const void *blob, int parent_offset)
+static int fdt_del_subnodes(const void *blob, int parent_offset)
 {
 	int off, ndepth;
 	int ret;
@@ -750,7 +750,7 @@ int fdt_del_subnodes(const void *blob, int parent_offset)
 	return 0;
 }
 
-int fdt_del_partitions(void *blob, int parent_offset)
+static int fdt_del_partitions(void *blob, int parent_offset)
 {
 	const void *prop;
 	int ndepth = 0;

configs/avnet_ultra96_rev1_defconfig

@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_MP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQ_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_WDT=y
+CONFIG_WDT_CDNS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/stmark2_defconfig

@@ -23,6 +23,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 # CONFIG_NET is not set
 CONFIG_MTD_DEVICE=y
 CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_SPI=y
 CONFIG_CF_SPI=y

configs/xilinx_zynqmp_zcu100_revC_defconfig

@@ -49,6 +49,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C1=y
 CONFIG_LED=y

configs/xilinx_zynqmp_zcu102_rev1_0_defconfig

@@ -61,6 +61,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y

configs/xilinx_zynqmp_zcu102_revA_defconfig

@@ -60,6 +60,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y

configs/xilinx_zynqmp_zcu102_revB_defconfig

@@ -60,6 +60,7 @@ CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_CMD_PCA953X=y
+CONFIG_XILINX_GPIO=y
 CONFIG_SYS_I2C_ZYNQ=y
 CONFIG_ZYNQ_I2C0=y
 CONFIG_ZYNQ_I2C1=y

configs/zynq_cc108_defconfig

@@ -35,6 +35,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_cse_nand_defconfig

@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x100000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nand"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y

configs/zynq_cse_nor_defconfig

@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0xFFFC0000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SYS_MALLOC_LEN=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
 CONFIG_BOOTDELAY=-1
 # CONFIG_DISPLAY_CPUINFO is not set

configs/zynq_cse_qspi_defconfig

@@ -8,6 +8,7 @@ CONFIG_DEBUG_UART_BASE=0x0
 CONFIG_DEBUG_UART_CLOCK=0
 CONFIG_SPL_STACK_R_ADDR=0x200000
 # CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_SYS_MALLOC_LEN=0x1000
 # CONFIG_CMD_ZYNQ is not set
 CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
 CONFIG_DEBUG_UART=y
@@ -55,6 +56,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_zc702_defconfig

@@ -52,6 +52,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_zc706_defconfig

@@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_zc770_xm010_defconfig

@@ -42,6 +42,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_zc770_xm013_defconfig

@@ -36,6 +36,7 @@ CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/zynq_zybo_z7_defconfig

@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo-z7"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_I2C_ZYNQ=y
+CONFIG_ZYNQ_I2C0=y
+CONFIG_ZYNQ_I2C1=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_REALTEK=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y

drivers/gpio/xilinx_gpio.c

@@ -10,13 +10,9 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
 
-static LIST_HEAD(gpio_list);
+#define XILINX_GPIO_MAX_BANK	2
-
-enum gpio_direction {
-	GPIO_DIRECTION_OUT = 0,
-	GPIO_DIRECTION_IN = 1,
-};
 
 /* Gpio simple map */
 struct gpio_regs {
@@ -24,340 +20,16 @@ struct gpio_regs {
 	u32 gpiodir;
 };
 
-#if !defined(CONFIG_DM_GPIO)
-
-#define GPIO_NAME_SIZE	10
-
-struct gpio_names {
-	char name[GPIO_NAME_SIZE];
-};
-
-/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
-struct xilinx_gpio_priv {
-	struct gpio_regs *regs;
-	u32 gpio_min;
-	u32 gpio_max;
-	u32 gpiodata_store;
-	char name[GPIO_NAME_SIZE];
-	struct list_head list;
-	struct gpio_names *gpio_name;
-};
-
-/* Store number of allocated gpio pins */
-static u32 xilinx_gpio_max;
-
-/* Get associated gpio controller */
-static struct xilinx_gpio_priv *gpio_get_controller(unsigned gpio)
-{
-	struct list_head *entry;
-	struct xilinx_gpio_priv *priv = NULL;
-
-	list_for_each(entry, &gpio_list) {
-		priv = list_entry(entry, struct xilinx_gpio_priv, list);
-		if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) {
-			debug("%s: reg: %x, min-max: %d-%d\n", __func__,
-			      (u32)priv->regs, priv->gpio_min, priv->gpio_max);
-			return priv;
-		}
-	}
-	puts("!!!Can't get gpio controller!!!\n");
-	return NULL;
-}
-
-/* Get gpio pin name if used/setup */
-static char *get_name(unsigned gpio)
-{
-	u32 gpio_priv;
-	struct xilinx_gpio_priv *priv;
-
-	debug("%s\n", __func__);
-
-	priv = gpio_get_controller(gpio);
-	if (priv) {
-		gpio_priv = gpio - priv->gpio_min;
-
-		return *priv->gpio_name[gpio_priv].name ?
-			priv->gpio_name[gpio_priv].name : "UNKNOWN";
-	}
-	return "UNKNOWN";
-}
-
-/* Get output value */
-static int gpio_get_output_value(unsigned gpio)
-{
-	u32 val, gpio_priv;
-	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
-	if (priv) {
-		gpio_priv = gpio - priv->gpio_min;
-		val = !!(priv->gpiodata_store & (1 << gpio_priv));
-		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
-		      (u32)priv->regs, gpio_priv, val);
-
-		return val;
-	}
-	return -1;
-}
-
-/* Get input value */
-static int gpio_get_input_value(unsigned gpio)
-{
-	u32 val, gpio_priv;
-	struct gpio_regs *regs;
-	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
-	if (priv) {
-		regs = priv->regs;
-		gpio_priv = gpio - priv->gpio_min;
-		val = readl(&regs->gpiodata);
-		val = !!(val & (1 << gpio_priv));
-		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
-		      (u32)priv->regs, gpio_priv, val);
-
-		return val;
-	}
-	return -1;
-}
-
-/* Set gpio direction */
-static int gpio_set_direction(unsigned gpio, enum gpio_direction direction)
-{
-	u32 val, gpio_priv;
-	struct gpio_regs *regs;
-	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
-	if (priv) {
-		regs = priv->regs;
-		val = readl(&regs->gpiodir);
-
-		gpio_priv = gpio - priv->gpio_min;
-		if (direction == GPIO_DIRECTION_OUT)
-			val &= ~(1 << gpio_priv);
-		else
-			val |= 1 << gpio_priv;
-
-		writel(val, &regs->gpiodir);
-		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
-		      (u32)priv->regs, gpio_priv, val);
-
-		return 0;
-	}
-
-	return -1;
-}
-
-/* Get gpio direction */
-static int gpio_get_direction(unsigned gpio)
-{
-	u32 val, gpio_priv;
-	struct gpio_regs *regs;
-	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
-	if (priv) {
-		regs = priv->regs;
-		gpio_priv = gpio - priv->gpio_min;
-		val = readl(&regs->gpiodir);
-		val = !!(val & (1 << gpio_priv));
-		debug("%s: reg: %x, gpio_no: %d, dir: %d\n", __func__,
-		      (u32)priv->regs, gpio_priv, val);
-
-		return val;
-	}
-
-	return -1;
-}
-
-/*
- * Get input value
- * for example gpio setup to output only can't get input value
- * which is breaking gpio toggle command
- */
-int gpio_get_value(unsigned gpio)
-{
-	u32 val;
-
-	if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
-		val = gpio_get_output_value(gpio);
-	else
-		val = gpio_get_input_value(gpio);
-
-	return val;
-}
-
-/* Set output value */
-static int gpio_set_output_value(unsigned gpio, int value)
-{
-	u32 val, gpio_priv;
-	struct gpio_regs *regs;
-	struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
-
-	if (priv) {
-		regs = priv->regs;
-		gpio_priv = gpio - priv->gpio_min;
-		val = priv->gpiodata_store;
-		if (value)
-			val |= 1 << gpio_priv;
-		else
-			val &= ~(1 << gpio_priv);
-
-		writel(val, &regs->gpiodata);
-		debug("%s: reg: %x, gpio_no: %d, output_val: %d\n", __func__,
-		      (u32)priv->regs, gpio_priv, val);
-		priv->gpiodata_store = val;
-
-		return 0;
-	}
-
-	return -1;
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
-	if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
-		return gpio_set_output_value(gpio, value);
-
-	return -1;
-}
-
-/* Set GPIO as input */
-int gpio_direction_input(unsigned gpio)
-{
-	debug("%s\n", __func__);
-	return gpio_set_direction(gpio, GPIO_DIRECTION_IN);
-}
-
-/* Setup GPIO as output and set output value */
-int gpio_direction_output(unsigned gpio, int value)
-{
-	int ret = gpio_set_direction(gpio, GPIO_DIRECTION_OUT);
-
-	debug("%s\n", __func__);
-
-	if (ret < 0)
-		return ret;
-
-	return gpio_set_output_value(gpio, value);
-}
-
-/* Show gpio status */
-void gpio_info(void)
-{
-	unsigned gpio;
-
-	struct list_head *entry;
-	struct xilinx_gpio_priv *priv = NULL;
-
-	list_for_each(entry, &gpio_list) {
-		priv = list_entry(entry, struct xilinx_gpio_priv, list);
-		printf("\n%s: %s/%x (%d-%d)\n", __func__, priv->name,
-		       (u32)priv->regs, priv->gpio_min, priv->gpio_max);
-
-		for (gpio = priv->gpio_min; gpio <= priv->gpio_max; gpio++) {
-			printf("GPIO_%d:\t%s is an ", gpio, get_name(gpio));
-			if (gpio_get_direction(gpio) == GPIO_DIRECTION_OUT)
-				printf("OUTPUT value = %d\n",
-				       gpio_get_output_value(gpio));
-			else
-				printf("INPUT value = %d\n",
-				       gpio_get_input_value(gpio));
-		}
-	}
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	u32 gpio_priv;
-	struct xilinx_gpio_priv *priv;
-
-	if (gpio >= xilinx_gpio_max)
-		return -EINVAL;
-
-	priv = gpio_get_controller(gpio);
-	if (priv) {
-		gpio_priv = gpio - priv->gpio_min;
-
-		if (label != NULL) {
-			strncpy(priv->gpio_name[gpio_priv].name, label,
-				GPIO_NAME_SIZE);
-			priv->gpio_name[gpio_priv].name[GPIO_NAME_SIZE - 1] =
-					'\0';
-		}
-		return 0;
-	}
-
-	return -1;
-}
-
-int gpio_free(unsigned gpio)
-{
-	u32 gpio_priv;
-	struct xilinx_gpio_priv *priv;
-
-	if (gpio >= xilinx_gpio_max)
-		return -EINVAL;
-
-	priv = gpio_get_controller(gpio);
-	if (priv) {
-		gpio_priv = gpio - priv->gpio_min;
-		priv->gpio_name[gpio_priv].name[0] = '\0';
-
-		/* Do nothing here */
-		return 0;
-	}
-
-	return -1;
-}
-
-int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
-{
-	struct xilinx_gpio_priv *priv;
-
-	priv = calloc(1, sizeof(struct xilinx_gpio_priv));
-
-	/* Setup gpio name */
-	if (name != NULL) {
-		strncpy(priv->name, name, GPIO_NAME_SIZE);
-		priv->name[GPIO_NAME_SIZE - 1] = '\0';
-	}
-	priv->regs = (struct gpio_regs *)baseaddr;
-
-	priv->gpio_min = xilinx_gpio_max;
-	xilinx_gpio_max = priv->gpio_min + gpio_no;
-	priv->gpio_max = xilinx_gpio_max - 1;
-
-	priv->gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
-
-	INIT_LIST_HEAD(&priv->list);
-	list_add_tail(&priv->list, &gpio_list);
-
-	printf("%s: Add %s (%d-%d)\n", __func__, name,
-	       priv->gpio_min, priv->gpio_max);
-
-	/* Return the first gpio allocated for this device */
-	return priv->gpio_min;
-}
-
-/* Dual channel gpio is one IP with two independent channels */
-int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0, u32 gpio_no1)
-{
-	int ret;
-
-	ret = gpio_alloc(baseaddr, name, gpio_no0);
-	gpio_alloc(baseaddr + 8, strcat((char *)name, "_1"), gpio_no1);
-
-	/* Return the first gpio allocated for this device */
-	return ret;
-}
-#else
-#include <dt-bindings/gpio/gpio.h>
-
-#define XILINX_GPIO_MAX_BANK	2
-
 struct xilinx_gpio_platdata {
 	struct gpio_regs *regs;
 	int bank_max[XILINX_GPIO_MAX_BANK];
 	int bank_input[XILINX_GPIO_MAX_BANK];
 	int bank_output[XILINX_GPIO_MAX_BANK];
+	u32 dout_default[XILINX_GPIO_MAX_BANK];
+};
+
+struct xilinx_gpio_privdata {
+	u32 output_val[XILINX_GPIO_MAX_BANK];
 };
 
 static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
@@ -387,6 +59,7 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
 				 int value)
 {
 	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
 	int val, ret;
 	u32 bank, pin;
 
@@ -394,25 +67,27 @@ static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
 	if (ret)
 		return ret;
 
-	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
+	val = priv->output_val[bank];
-	      __func__, (ulong)platdata->regs, value, offset, bank, pin);
 
-	if (value) {
+	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
-		val = readl(&platdata->regs->gpiodata + bank * 2);
+	      __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
+
+	if (value)
 		val = val | (1 << pin);
-		writel(val, &platdata->regs->gpiodata + bank * 2);
+	else
-	} else {
-		val = readl(&platdata->regs->gpiodata + bank * 2);
 		val = val & ~(1 << pin);
-		writel(val, &platdata->regs->gpiodata + bank * 2);
-	}
 
-	return val;
+	writel(val, &platdata->regs->gpiodata + bank * 2);
+
+	priv->output_val[bank] = val;
+
+	return 0;
 };
 
 static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
 {
 	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
 	int val, ret;
 	u32 bank, pin;
 
@@ -423,7 +98,14 @@ static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
 	debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
 	      (ulong)platdata->regs, offset, bank, pin);
 
-	val = readl(&platdata->regs->gpiodata + bank * 2);
+	if (platdata->bank_output[bank]) {
+		debug("%s: Read saved output value\n", __func__);
+		val = priv->output_val[bank];
+	} else {
+		debug("%s: Read input value from reg\n", __func__);
+		val = readl(&platdata->regs->gpiodata + bank * 2);
+	}
+
 	val = !!(val & (1 << pin));
 
 	return val;
@@ -435,6 +117,10 @@ static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
 	int val, ret;
 	u32 bank, pin;
 
+	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
+	if (ret)
+		return ret;
+
 	/* Check if all pins are inputs */
 	if (platdata->bank_input[bank])
 		return GPIOF_INPUT;
@@ -443,10 +129,6 @@ static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
 	if (platdata->bank_output[bank])
 		return GPIOF_OUTPUT;
 
-	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
-	if (ret)
-		return ret;
-
 	/* FIXME test on dual */
 	val = readl(&platdata->regs->gpiodir + bank * 2);
 	val = !(val & (1 << pin));
@@ -472,14 +154,14 @@ static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
 	if (platdata->bank_input[bank])
 		return -EINVAL;
 
+	xilinx_gpio_set_value(dev, offset, value);
+
 	if (!platdata->bank_output[bank]) {
 		val = readl(&platdata->regs->gpiodir + bank * 2);
 		val = val & ~(1 << pin);
 		writel(val, &platdata->regs->gpiodir + bank * 2);
 	}
 
-	xilinx_gpio_set_value(dev, offset, value);
-
 	return 0;
 }
 
@@ -557,12 +239,26 @@ static const struct dm_gpio_ops xilinx_gpio_ops = {
 static int xilinx_gpio_probe(struct udevice *dev)
 {
 	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
+	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	const void *label_ptr;
 
-	uc_priv->bank_name = dev->name;
+	label_ptr = dev_read_prop(dev, "label", NULL);
+	if (label_ptr) {
+		uc_priv->bank_name = strdup(label_ptr);
+		if (!uc_priv->bank_name)
+			return -ENOMEM;
+	} else {
+		uc_priv->bank_name = dev->name;
+	}
 
 	uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
 
+	priv->output_val[0] = platdata->dout_default[0];
+
+	if (platdata->bank_max[1])
+		priv->output_val[1] = platdata->dout_default[1];
+
 	return 0;
 }
 
@@ -579,6 +275,9 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
 						       "xlnx,all-inputs", 0);
 	platdata->bank_output[0] = dev_read_u32_default(dev,
 							"xlnx,all-outputs", 0);
+	platdata->dout_default[0] = dev_read_u32_default(dev,
+							 "xlnx,dout-default",
+							 0);
 
 	is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
 	if (is_dual) {
@@ -588,6 +287,8 @@ static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
 						"xlnx,all-inputs-2", 0);
 		platdata->bank_output[1] = dev_read_u32_default(dev,
 						"xlnx,all-outputs-2", 0);
+		platdata->dout_default[1] = dev_read_u32_default(dev,
+						"xlnx,dout-default-2", 0);
 	}
 
 	return 0;
@@ -606,5 +307,5 @@ U_BOOT_DRIVER(xilinx_gpio) = {
 	.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
 	.probe = xilinx_gpio_probe,
 	.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
+	.priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
 };
-#endif

drivers/gpio/zynq_gpio.c

@@ -93,7 +93,7 @@
 /* GPIO upper 16 bit mask */
 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
 
-struct zynq_gpio_privdata {
+struct zynq_gpio_platdata {
 	phys_addr_t base;
 	const struct zynq_platform_data *p_data;
 };
@@ -162,20 +162,20 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 					  unsigned int *bank_pin_num,
 					  struct udevice *dev)
 {
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 	u32 bank;
 
-	for (bank = 0; bank < priv->p_data->max_bank; bank++) {
+	for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
-		if ((pin_num >= priv->p_data->bank_min[bank]) &&
+		if (pin_num >= platdata->p_data->bank_min[bank] &&
-		    (pin_num <= priv->p_data->bank_max[bank])) {
+		    pin_num <= platdata->p_data->bank_max[bank]) {
-				*bank_num = bank;
+			*bank_num = bank;
-				*bank_pin_num = pin_num -
+			*bank_pin_num = pin_num -
-						priv->p_data->bank_min[bank];
+					platdata->p_data->bank_min[bank];
-				return;
+			return;
 		}
 	}
 
-	if (bank >= priv->p_data->max_bank) {
+	if (bank >= platdata->p_data->max_bank) {
 		printf("Invalid bank and pin num\n");
 		*bank_num = 0;
 		*bank_pin_num = 0;
@@ -184,9 +184,9 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
 
 static int gpio_is_valid(unsigned gpio, struct udevice *dev)
 {
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
-	return gpio < priv->p_data->ngpio;
+	return gpio < platdata->p_data->ngpio;
 }
 
 static int check_gpio(unsigned gpio, struct udevice *dev)
@@ -202,14 +202,14 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
 {
 	u32 data;
 	unsigned int bank_num, bank_pin_num;
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
 	if (check_gpio(gpio, dev) < 0)
 		return -1;
 
 	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
-	data = readl(priv->base +
+	data = readl(platdata->base +
 			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
 
 	return (data >> bank_pin_num) & 1;
@@ -218,7 +218,7 @@ static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
 static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
 {
 	unsigned int reg_offset, bank_num, bank_pin_num;
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
 	if (check_gpio(gpio, dev) < 0)
 		return -1;
@@ -241,7 +241,7 @@ static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
 	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
 		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
 
-	writel(value, priv->base + reg_offset);
+	writel(value, platdata->base + reg_offset);
 
 	return 0;
 }
@@ -250,7 +250,7 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
 {
 	u32 reg;
 	unsigned int bank_num, bank_pin_num;
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
 	if (check_gpio(gpio, dev) < 0)
 		return -1;
@@ -262,9 +262,9 @@ static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
 		return -1;
 
 	/* clear the bit in direction mode reg to set the pin as input */
-	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 	reg &= ~BIT(bank_pin_num);
-	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 
 	return 0;
 }
@@ -274,7 +274,7 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
 {
 	u32 reg;
 	unsigned int bank_num, bank_pin_num;
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
 	if (check_gpio(gpio, dev) < 0)
 		return -1;
@@ -282,14 +282,14 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
 
 	/* set the GPIO pin as output */
-	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 	reg |= BIT(bank_pin_num);
-	writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 
 	/* configure the output enable reg for the pin */
-	reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+	reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 	reg |= BIT(bank_pin_num);
-	writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+	writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
 
 	/* set the state of the pin */
 	gpio_set_value(gpio, value);
@@ -300,7 +300,7 @@ static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	u32 reg;
 	unsigned int bank_num, bank_pin_num;
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
 	if (check_gpio(offset, dev) < 0)
 		return -1;
@@ -308,7 +308,7 @@ static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
 	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
 
 	/* set the GPIO pin as output */
-	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
 	reg &= BIT(bank_pin_num);
 	if (reg)
 		return GPIOF_OUTPUT;
@@ -334,24 +334,33 @@ static const struct udevice_id zynq_gpio_ids[] = {
 
 static int zynq_gpio_probe(struct udevice *dev)
 {
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	const void *label_ptr;
 
-	uc_priv->bank_name = dev->name;
+	label_ptr = dev_read_prop(dev, "label", NULL);
+	if (label_ptr) {
+		uc_priv->bank_name = strdup(label_ptr);
+		if (!uc_priv->bank_name)
+			return -ENOMEM;
+	} else {
+		uc_priv->bank_name = dev->name;
+	}
 
-	if (priv->p_data)
+	if (platdata->p_data)
-		uc_priv->gpio_count = priv->p_data->ngpio;
+		uc_priv->gpio_count = platdata->p_data->ngpio;
 
 	return 0;
 }
 
 static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
 {
-	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+	struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
 
-	priv->base = (phys_addr_t)dev_read_addr(dev);
+	platdata->base = (phys_addr_t)dev_read_addr(dev);
 
-	priv->p_data = (struct zynq_platform_data *)dev_get_driver_data(dev);
+	platdata->p_data =
+		(struct zynq_platform_data *)dev_get_driver_data(dev);
 
 	return 0;
 }
@@ -363,5 +372,5 @@ U_BOOT_DRIVER(gpio_zynq) = {
 	.of_match = zynq_gpio_ids,
 	.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
 	.probe	= zynq_gpio_probe,
-	.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
+	.platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
 };

drivers/mtd/spi/Kconfig

@@ -66,6 +66,11 @@ config SPI_FLASH_GIGADEVICE
 	help
 	  Add support for various GigaDevice SPI flash chips (GD25xxx)
 
+config SPI_FLASH_ISSI
+	bool "ISSI SPI flash support"
+	help
+	  Add support for various ISSI SPI flash chips (ISxxx)
+
 config SPI_FLASH_MACRONIX
 	bool "Macronix SPI flash support"
 	help

include/configs/stmark2.h

@@ -67,7 +67,6 @@
 #define CONFIG_SF_DEFAULT_SPEED		50000000
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_HARD_SPI
-#define CONFIG_SPI_FLASH_ISSI
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		1
 

include/configs/topic_miami.h

@@ -53,7 +53,6 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
 #undef CONFIG_SPI_FLASH_WINBOND
-#undef CONFIG_SPI_FLASH_ISSI
 
 /* Setup proper boot sequences for Miami boards */
 

include/configs/xilinx_zynqmp_mini.h

@@ -31,5 +31,6 @@
 #undef CONFIG_BOOTP_MAY_FAIL
 
 #undef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS	1
 
 #endif /* __CONFIG_ZYNQMP_MINI_H */

include/configs/xilinx_zynqmp_mini_emmc.h

@@ -13,7 +13,6 @@
 #include <configs/xilinx_zynqmp_mini.h>
 
 #define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS	1
 #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN	0x800000
 

include/configs/xilinx_zynqmp_mini_nand.h

@@ -13,7 +13,6 @@
 #include <configs/xilinx_zynqmp_mini.h>
 
 #define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS	1
 #define CONFIG_SYS_SDRAM_SIZE	0x1000000
 #define CONFIG_SYS_SDRAM_BASE	0x0
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x40000)

include/configs/xilinx_zynqmp_mini_qspi.h

@@ -13,7 +13,6 @@
 #include <configs/xilinx_zynqmp_mini.h>
 
 #define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_NR_DRAM_BANKS	1
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_TEXT_BASE + 0x20000)
 #define CONFIG_SYS_MALLOC_LEN	0x2000
 

include/configs/zynq-common.h

@@ -43,7 +43,6 @@
 /* QSPI */
 #ifdef CONFIG_ZYNQ_QSPI
 # define CONFIG_SF_DEFAULT_SPEED	30000000
-# define CONFIG_SPI_FLASH_ISSI
 #endif
 
 /* NOR */
@@ -235,8 +234,6 @@
 #define CONFIG_SYS_MEMTEST_START	0
 #define CONFIG_SYS_MEMTEST_END		0x1000
 
-#define CONFIG_SYS_MALLOC_LEN		0x1400000
-
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \

include/configs/zynq_cse.h

@@ -36,7 +36,4 @@
 #define CONFIG_SPL_BSS_START_ADDR	0x20000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x8000
 
-#undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_MALLOC_LEN	0x1000
-
 #endif /* __CONFIG_ZYNQ_CSE_H */