blackfin: bf60x: add rsi/sdh support
Add rsi/sdh support for bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
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Sonic Zhang
sonic
parent
320ec9dfb7
commit
187f32fac3
@ -12,18 +12,35 @@
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#define CMD_INT_E 0x100 /* Command Interrupt */
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#define CMD_PEND_E 0x200 /* Command Pending */
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#define CMD_E 0x400 /* Command Enable */
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#ifdef RSI_BLKSZ
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#define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */
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#define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */
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#endif
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/* Bit masks for SDH_PWR_CTL */
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#ifndef RSI_BLKSZ
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#define PWR_ON 0x3 /* Power On */
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#define SD_CMD_OD 0x40 /* Open Drain Output */
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#define ROD_CTL 0x80 /* Rod Control */
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#endif
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/* Bit masks for SDH_CLK_CTL */
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#define CLKDIV 0xff /* MC_CLK Divisor */
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#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
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#define PWR_SV_E 0x200 /* Power Save Enable */
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#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
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#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
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#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
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#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
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#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
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#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
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#ifdef RSI_BLKSZ
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#define CARD_TYPE_MASK 0xe000 /* Card type mask */
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#define CARD_TYPE_OFFSET 13 /* Card type offset */
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#define CARD_TYPE_SDIO 0
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#define CARD_TYPE_eMMC 1
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#define CARD_TYPE_SD 2
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#define CARD_TYPE_CEATA 3
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#endif
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/* Bit masks for SDH_RESP_CMD */
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#define RESP_CMD 0x3f /* Response Command */
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@ -33,7 +50,13 @@
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#define DTX_DIR 0x2 /* Data Transfer Direction */
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#define DTX_MODE 0x4 /* Data Transfer Mode */
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#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
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#ifndef RSI_BLKSZ
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#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
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#else
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/* Bit masks for SDH_BLK_SIZE */
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#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
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#endif
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/* Bit masks for SDH_STATUS */
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#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
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@ -102,10 +125,13 @@
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/* Bit masks for SDH_E_STATUS */
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#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
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#define SD_CARD_DET 0x10 /* SD Card Detect */
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#define SD_CARD_BUSYMODE 0x80000000 /* Card is in Busy mode */
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#define SD_CARD_SLPMODE 0x40000000 /* Card in Sleep Mode */
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#define SD_CARD_READY 0x00020000 /* Card Ready */
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/* Bit masks for SDH_E_MASK */
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#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
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#define SCD_MSK 0x40 /* Mask Card Detect */
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#define SCD_MSK 0x10 /* Mask Card Detect */
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/* Bit masks for SDH_CFG */
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#define CLKS_EN 0x1 /* Clocks Enable */
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@ -114,7 +140,15 @@
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#define SD_RST 0x10 /* SDMMC Reset */
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#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
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#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
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#ifndef RSI_BLKSZ
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#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
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#else
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#define PWR_ON 0x600 /* Power On */
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#define SD_CMD_OD 0x800 /* Open Drain Output */
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#define BOOT_EN 0x1000 /* Boot Enable */
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#define BOOT_MODE 0x2000 /* Alternate Boot Mode */
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#define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */
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#endif
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/* Bit masks for SDH_RD_WAIT_EN */
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#define RWR 0x1 /* Read Wait Request */
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@ -19,9 +19,7 @@
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#include <asm/mach-common/bits/sdh.h>
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#include <asm/mach-common/bits/dma.h>
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#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
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# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
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# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
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#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
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# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
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# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
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# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
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@ -38,10 +36,21 @@
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# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
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# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
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# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
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# if defined(__ADSPBF60x__)
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# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
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# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
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# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
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# else
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# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
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# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
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# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
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# endif
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# define PORTMUX_PINS \
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{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
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#elif defined(__ADSPBF54x__)
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@ -70,6 +79,9 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
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sdh_cmd |= CMD_RSP;
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if (flags & MMC_RSP_136)
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sdh_cmd |= CMD_L_RSP;
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#ifdef RSI_BLKSZ
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sdh_cmd |= CMD_DATA0_BUSY;
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#endif
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bfin_write_SDH_ARGUMENT(arg);
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bfin_write_SDH_COMMAND(sdh_cmd);
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@ -104,6 +116,12 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
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bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
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CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
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#ifdef RSI_BLKSZ
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/* wait till card ready */
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while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
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continue;
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bfin_write_RSI_ESTAT(SD_CARD_READY);
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#endif
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return ret;
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}
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@ -113,16 +131,19 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
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{
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u16 data_ctl = 0;
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u16 dma_cfg = 0;
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int ret = 0;
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unsigned long data_size = data->blocksize * data->blocks;
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/* Don't support write yet. */
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if (data->flags & MMC_DATA_WRITE)
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return UNUSABLE_ERR;
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#ifndef RSI_BLKSZ
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data_ctl |= ((ffs(data_size) - 1) << 4);
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#else
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bfin_write_SDH_BLK_SIZE(data_size);
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#endif
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data_ctl |= DTX_DIR;
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bfin_write_SDH_DATA_CTL(data_ctl);
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dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
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dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
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bfin_write_SDH_DATA_TIMER(-1);
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@ -137,7 +158,7 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
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/* kick off transfer */
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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return ret;
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return 0;
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}
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@ -147,13 +168,23 @@ static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
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u32 status;
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int ret = 0;
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if (data) {
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ret = sdh_setup_data(mmc, data);
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if (ret)
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return ret;
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}
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ret = sdh_send_cmd(mmc, cmd);
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if (ret) {
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bfin_write_SDH_COMMAND(0);
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bfin_write_DMA_CONFIG(0);
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bfin_write_SDH_DATA_CTL(0);
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SSYNC();
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printf("sending CMD%d failed\n", cmd->cmdidx);
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return ret;
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}
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if (data) {
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ret = sdh_setup_data(mmc, data);
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do {
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udelay(1);
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status = bfin_read_SDH_STATUS();
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@ -208,10 +239,12 @@ static void bfin_sdh_set_ios(struct mmc *mmc)
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if (mmc->bus_width == 4) {
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cfg = bfin_read_SDH_CFG();
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cfg &= ~0x80;
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cfg |= 0x40;
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#ifndef RSI_BLKSZ
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cfg &= ~PD_SDDAT3;
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#endif
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cfg |= PUP_SDDAT3;
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bfin_write_SDH_CFG(cfg);
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clk_ctl |= WIDE_BUS;
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clk_ctl |= WIDE_BUS_4;
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}
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bfin_write_SDH_CLK_CTL(clk_ctl);
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sdh_set_clk(mmc->clock);
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@ -220,20 +253,23 @@ static void bfin_sdh_set_ios(struct mmc *mmc)
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static int bfin_sdh_init(struct mmc *mmc)
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{
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const unsigned short pins[] = PORTMUX_PINS;
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u16 pwr_ctl = 0;
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int ret;
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/* Initialize sdh controller */
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peripheral_request_list(pins, "bfin_sdh");
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ret = peripheral_request_list(pins, "bfin_sdh");
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if (ret < 0)
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return ret;
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#if defined(__ADSPBF54x__)
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bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
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#endif
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
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/* Disable card detect pin */
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bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
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pwr_ctl |= ROD_CTL;
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pwr_ctl |= PWR_ON;
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bfin_write_SDH_PWR_CTL(pwr_ctl);
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#ifndef RSI_BLKSZ
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bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
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#else
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
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#endif
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return 0;
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}
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