Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
This commit is contained in:
Stefan Roese
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o
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#OBJS += flash.o
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OBJS += flash.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS)
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File diff suppressed because it is too large
Load Diff
401
board/amcc/bamboo/bamboo.h
Normal file
401
board/amcc/bamboo/bamboo.h
Normal file
@@ -0,0 +1,401 @@
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/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*----------------------------------------------------------------------------+
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| FPGA registers and bit definitions
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+----------------------------------------------------------------------------*/
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/*
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* PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
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* TLB initialization makes it correspond to logical address 0x80001FF0.
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* => Done init_chip.s in bootlib
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*/
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#define FPGA_BASE_ADDR 0x80002000
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/*----------------------------------------------------------------------------+
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| Board Jumpers Setting Register
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| Board Settings provided by jumpers
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+----------------------------------------------------------------------------*/
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#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
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/* Boot from small flash */
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#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
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/* Operational Flash versus SRAM position in Memory Map */
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#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
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#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
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#define FPGA_SET_REG_SRAM_ABOVE 0x00
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/* Boot From NAND Flash */
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#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
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#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
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/* On Board PCI Arbiter Select */
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#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
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#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 1
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
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#define FPGA_SEL_1_REG_PHY_MASK 0xE0
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#define FPGA_SEL_1_REG_MII 0x80
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#define FPGA_SEL_1_REG_RMII 0x40
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#define FPGA_SEL_1_REG_SMII 0x20
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#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
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#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
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#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
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#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
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#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
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#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 2
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
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#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
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#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
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#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
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#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
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#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
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#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
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#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
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/* 1 = TC - output from 440EP */
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#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
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/* 1 = TC (output from 440EP) */
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#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
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#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
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#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 3
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
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#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
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#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
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#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
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#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
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/*----------------------------------------------------------------------------+
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| Soft Reset Register
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+----------------------------------------------------------------------------*/
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#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
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#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
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#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
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#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
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/*----------------------------------------------------------------------------+
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| SDR Configuration registers
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+----------------------------------------------------------------------------*/
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/* Serial Device Strap Reg 0 */
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#define SDR0_SDSTP0 0x0020
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/* Serial Device Strap Reg 1 */
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#define SDR0_SDSTP1 0x0021
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/* Serial Device Strap Reg 2 */
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#define SDR0_SDSTP2 SDR0_STRP2
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/* Serial Device Strap Reg 3 */
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#define SDR0_SDSTP3 SDR0_STRP3
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#define sdr_pstrp0 0x0040
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#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
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#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
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#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
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#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
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#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
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#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
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#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
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#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
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/* Serial Device Enabled - Addr = 0xA8 */
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#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
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/* Serial Device Enabled - Addr = 0xA4 */
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#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
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/* Pin Straps Reg */
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#define SDR0_PSTRP0 0x0040
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#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
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/*----------------------------------------------------------------------------+
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| EBC Configuration Register - EBC0_CFG
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+----------------------------------------------------------------------------*/
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/* External Bus Three-State Control */
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#define EBC0_CFG_EBTC_DRIVEN 0x80000000
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/* Device-Paced Time-out Disable */
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#define EBC0_CFG_PTD_ENABLED 0x00000000
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/* Ready Timeout Count */
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#define EBC0_CFG_RTC_MASK 0x38000000
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#define EBC0_CFG_RTC_16PERCLK 0x00000000
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#define EBC0_CFG_RTC_32PERCLK 0x08000000
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#define EBC0_CFG_RTC_64PERCLK 0x10000000
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#define EBC0_CFG_RTC_128PERCLK 0x18000000
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#define EBC0_CFG_RTC_256PERCLK 0x20000000
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#define EBC0_CFG_RTC_512PERCLK 0x28000000
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#define EBC0_CFG_RTC_1024PERCLK 0x30000000
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#define EBC0_CFG_RTC_2048PERCLK 0x38000000
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/* External Master Priority Low */
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#define EBC0_CFG_EMPL_LOW 0x00000000
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#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
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#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
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#define EBC0_CFG_EMPL_HIGH 0x06000000
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/* External Master Priority High */
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#define EBC0_CFG_EMPH_LOW 0x00000000
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#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
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#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
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#define EBC0_CFG_EMPH_HIGH 0x01800000
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/* Chip Select Three-State Control */
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#define EBC0_CFG_CSTC_DRIVEN 0x00400000
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/* Burst Prefetch */
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#define EBC0_CFG_BPF_ONEDW 0x00000000
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#define EBC0_CFG_BPF_TWODW 0x00100000
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#define EBC0_CFG_BPF_FOURDW 0x00200000
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/* External Master Size */
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#define EBC0_CFG_EMS_8BIT 0x00000000
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/* Power Management Enable */
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#define EBC0_CFG_PME_DISABLED 0x00000000
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#define EBC0_CFG_PME_ENABLED 0x00020000
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/* Power Management Timer */
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#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
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/*----------------------------------------------------------------------------+
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| Peripheral Bank Configuration Register - EBC0_BnCR
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+----------------------------------------------------------------------------*/
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/* BAS - Base Address Select */
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#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
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/* BS - Bank Size */
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#define EBC0_BNCR_BS_MASK 0x000E0000
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#define EBC0_BNCR_BS_1MB 0x00000000
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#define EBC0_BNCR_BS_2MB 0x00020000
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#define EBC0_BNCR_BS_4MB 0x00040000
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#define EBC0_BNCR_BS_8MB 0x00060000
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#define EBC0_BNCR_BS_16MB 0x00080000
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#define EBC0_BNCR_BS_32MB 0x000A0000
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#define EBC0_BNCR_BS_64MB 0x000C0000
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#define EBC0_BNCR_BS_128MB 0x000E0000
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/* BU - Bank Usage */
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#define EBC0_BNCR_BU_MASK 0x00018000
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#define EBC0_BNCR_BU_RO 0x00008000
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#define EBC0_BNCR_BU_WO 0x00010000
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#define EBC0_BNCR_BU_RW 0x00018000
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/* BW - Bus Width */
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#define EBC0_BNCR_BW_MASK 0x00006000
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#define EBC0_BNCR_BW_8BIT 0x00000000
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#define EBC0_BNCR_BW_16BIT 0x00002000
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#define EBC0_BNCR_BW_32BIT 0x00004000
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/*----------------------------------------------------------------------------+
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| Peripheral Bank Access Parameters - EBC0_BnAP
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+----------------------------------------------------------------------------*/
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/* Burst Mode Enable */
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#define EBC0_BNAP_BME_ENABLED 0x80000000
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#define EBC0_BNAP_BME_DISABLED 0x00000000
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/* Transfert Wait */
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#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
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/* Chip Select On Timing */
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#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
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/* Output Enable On Timing */
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#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
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/* Write Back Enable On Timing */
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#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
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/* Write Back Enable Off Timing */
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#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
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/* Transfert Hold */
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#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
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/* PerReady Enable */
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#define EBC0_BNAP_RE_ENABLED 0x00000100
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#define EBC0_BNAP_RE_DISABLED 0x00000000
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/* Sample On Ready */
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#define EBC0_BNAP_SOR_DELAYED 0x00000000
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#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
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/* Byte Enable Mode */
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#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
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#define EBC0_BNAP_BEM_RW 0x00000040
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/* Parity Enable */
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#define EBC0_BNAP_PEN_DISABLED 0x00000000
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#define EBC0_BNAP_PEN_ENABLED 0x00000020
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/*----------------------------------------------------------------------------+
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| Define Boot devices
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+----------------------------------------------------------------------------*/
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/* */
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#define BOOT_FROM_SMALL_FLASH 0x00
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#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
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#define BOOT_FROM_NAND_FLASH0 0x02
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#define BOOT_FROM_PCI 0x03
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#define BOOT_DEVICE_UNKNOWN 0x04
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#define PVR_POWERPC_440EP_PASS1 0x42221850
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#define PVR_POWERPC_440EP_PASS2 0x422218D3
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#define TRUE 1
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#define FALSE 0
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#define GPIO_GROUP_MAX 2
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#define GPIO_MAX 32
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#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
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#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
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#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
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#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
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#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
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/* For the other GPIO number, you must shift */
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#define GPIO0 0
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#define GPIO1 1
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/*#define MAX_SELECTION_NB CORE_NB */
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#define MAX_CORE_SELECT_NB 22
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/*----------------------------------------------------------------------------+
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| PPC440EP GPIOs addresses.
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+----------------------------------------------------------------------------*/
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#define GPIO0_BASE 0xEF600B00
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#define GPIO0_REAL 0xEF600B00
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#define GPIO1_BASE 0xEF600C00
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#define GPIO1_REAL 0xEF600C00
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/* Offsets */
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#define GPIOx_OR 0x00 /* GPIO Output Register */
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#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
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#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
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#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
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#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
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#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
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#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
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#define GPIOx_IR 0x1C /* GPIO Input Register */
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#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
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#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
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#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
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#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
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#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
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#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
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#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
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#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
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#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
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/* GPIO0 */
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#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
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#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
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#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
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#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
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#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
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#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
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/* GPIO1 */
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#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
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#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
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#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
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#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
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#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
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#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
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#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
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#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
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#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
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#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
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#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
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/*----------------------------------------------------------------------------+
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| Declare Configuration values
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+----------------------------------------------------------------------------*/
|
||||
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
|
||||
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
|
||||
|
||||
typedef struct { unsigned long add; /* gpio core base address */
|
||||
gpio_driver_t in_out; /* Driver Setting */
|
||||
gpio_select_t alt_nb; /* Selected Alternate */
|
||||
} gpio_param_s;
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| XX XX
|
||||
|
|
||||
| XXXXXX XXX XX XXX XXX
|
||||
| XX XX X XX XX XX
|
||||
| XX XX X XX XX XX
|
||||
| XX XX XX XX XX
|
||||
| XXXXXX XXX XXX XXXX XXXX
|
||||
+----------------------------------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Defines
|
||||
+----------------------------------------------------------------------------*/
|
||||
typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
|
||||
ZMII_CONFIGURATION_IS_MII,
|
||||
ZMII_CONFIGURATION_IS_RMII,
|
||||
ZMII_CONFIGURATION_IS_SMII
|
||||
} zmii_config_t;
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| Declare Configuration values
|
||||
+----------------------------------------------------------------------------*/
|
||||
typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
|
||||
typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
|
||||
typedef enum config_list { IIC_CORE,
|
||||
SCP_CORE,
|
||||
DMA_CHANNEL_AB,
|
||||
UIC_4_9,
|
||||
USB2_HOST,
|
||||
DMA_CHANNEL_CD,
|
||||
USB2_DEVICE,
|
||||
PACKET_REJ_FUNC_AVAIL,
|
||||
USB1_DEVICE,
|
||||
EBC_MASTER,
|
||||
NAND_FLASH,
|
||||
UART_CORE0,
|
||||
UART_CORE1,
|
||||
UART_CORE2,
|
||||
UART_CORE3,
|
||||
MII_SEL,
|
||||
RMII_SEL,
|
||||
SMII_SEL,
|
||||
PACKET_REJ_FUNC_EN,
|
||||
UIC_0_3,
|
||||
USB1_HOST,
|
||||
PCI_PATCH,
|
||||
CORE_NB
|
||||
} core_list_t;
|
||||
|
||||
typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
|
||||
B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
|
||||
B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
|
||||
B3_V16, B3_VALUE_UNKNOWN
|
||||
} block3_value_t;
|
||||
|
||||
typedef enum config_validity { CONFIG_IS_VALID,
|
||||
CONFIG_IS_INVALID
|
||||
} config_validity_t;
|
||||
@@ -21,17 +21,7 @@
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# esd ADCIOP boards
|
||||
#
|
||||
|
||||
#TEXT_BASE = 0x00001000
|
||||
|
||||
ifeq ($(ramsym),1)
|
||||
TEXT_BASE = 0xFBD00000
|
||||
else
|
||||
TEXT_BASE = 0xFFF80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
|
||||
166
board/amcc/bamboo/flash.c
Normal file
166
board/amcc/bamboo/flash.c
Normal file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* (C) Copyright 2004-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
|
||||
* Add support for Am29F016D and dynamic switch setting.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Modified 4/5/2001
|
||||
* Wait for completion of each sector erase command issued
|
||||
* 4/5/2001
|
||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <ppc440.h>
|
||||
#include "bamboo.h"
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DEBUGF(x...) printf(x)
|
||||
#else
|
||||
#define DEBUGF(x...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
|
||||
*/
|
||||
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
|
||||
{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
|
||||
{0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/
|
||||
{0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
|
||||
};
|
||||
|
||||
/*
|
||||
* include common flash code (for amcc boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
|
||||
static int write_word(flash_info_t * info, ulong dest, ulong data);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long total_b = 0;
|
||||
unsigned long size_b[CFG_MAX_FLASH_BANKS];
|
||||
unsigned short index = 0;
|
||||
int i;
|
||||
unsigned long val;
|
||||
unsigned long ebc_boot_size;
|
||||
unsigned long boot_selection;
|
||||
|
||||
mfsdr(sdr_pstrp0, val);
|
||||
index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
|
||||
|
||||
if ((index == 5) || (index == 7)) {
|
||||
/*
|
||||
* Boot Settings in IIC EEprom address 0xA8 or 0xA4
|
||||
* Read Serial Device Strap Register1 in PPC440EP
|
||||
*/
|
||||
mfsdr(sdr_sdstp1, val);
|
||||
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
|
||||
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
|
||||
|
||||
switch(boot_selection) {
|
||||
case SDR0_SDSTP1_BOOT_SEL_EBC:
|
||||
switch(ebc_boot_size) {
|
||||
case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
|
||||
index = 3;
|
||||
break;
|
||||
case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
|
||||
index = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDR0_SDSTP1_BOOT_SEL_PCI:
|
||||
index = 1;
|
||||
break;
|
||||
|
||||
case SDR0_SDSTP1_BOOT_SEL_NDFC:
|
||||
index = 2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUGF("\n");
|
||||
DEBUGF("FLASH: Index: %d\n", index);
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
|
||||
/* check whether the address is 0 */
|
||||
if (flash_addr_table[index][i] == 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* call flash_get_size() to initialize sector address */
|
||||
size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
|
||||
&flash_info[i]);
|
||||
flash_info[i].size = size_b[i];
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i, size_b[i], size_b[i] << 20);
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
}
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
|
||||
&flash_info[i]);
|
||||
#if defined(CFG_ENV_IS_IN_FLASH)
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[i]);
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[i]);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
total_b += flash_info[i].size;
|
||||
}
|
||||
|
||||
return total_b;
|
||||
}
|
||||
@@ -93,7 +93,7 @@ tlbtab:
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
|
||||
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
@@ -74,7 +74,7 @@ SECTIONS
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
cpu/ppc4xx/405gp_enet.o (.text)
|
||||
cpu/ppc4xx/440gx_enet.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
@@ -150,6 +150,9 @@ SECTIONS
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
||||
@@ -41,6 +41,14 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
* Functions
|
||||
*/
|
||||
static int write_word(flash_info_t * info, ulong dest, ulong data);
|
||||
#ifdef CFG_FLASH_2ND_16BIT_DEV
|
||||
static int write_word_1(flash_info_t * info, ulong dest, ulong data);
|
||||
static int write_word_2(flash_info_t * info, ulong dest, ulong data);
|
||||
static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
|
||||
static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
|
||||
static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
|
||||
static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
|
||||
#endif
|
||||
|
||||
void flash_print_info(flash_info_t * info)
|
||||
{
|
||||
@@ -113,6 +121,9 @@ void flash_print_info(flash_info_t * info)
|
||||
case FLASH_SST160A:
|
||||
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_STMW320DT:
|
||||
printf ("M29W320DT (32 M, top sector)\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Chip Type\n");
|
||||
break;
|
||||
@@ -154,7 +165,21 @@ void flash_print_info(flash_info_t * info)
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
#ifdef CFG_FLASH_2ND_16BIT_DEV
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
|
||||
{
|
||||
/* bit 0 used for big flash marking */
|
||||
if ((ulong)addr & 0x1) {
|
||||
return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
|
||||
} else {
|
||||
return flash_get_size_1(addr, info);
|
||||
}
|
||||
}
|
||||
|
||||
static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
|
||||
#else
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
|
||||
#endif
|
||||
{
|
||||
short i;
|
||||
CFG_FLASH_WORD_SIZE value;
|
||||
@@ -193,7 +218,6 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
|
||||
}
|
||||
|
||||
value = addr2[1]; /* device ID */
|
||||
|
||||
DEBUGF("\nFLASH DEVICEID: %x\n", value);
|
||||
|
||||
switch (value) {
|
||||
@@ -323,7 +347,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int wait_for_DQ7(flash_info_t * info, int sect)
|
||||
static int wait_for_DQ7_1(flash_info_t * info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile CFG_FLASH_WORD_SIZE *addr =
|
||||
@@ -346,7 +370,22 @@ int wait_for_DQ7(flash_info_t * info, int sect)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_2ND_16BIT_DEV
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
|
||||
return flash_erase_2(info, s_first, s_last);
|
||||
} else {
|
||||
return flash_erase_1(info, s_first, s_last);
|
||||
}
|
||||
}
|
||||
|
||||
static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
|
||||
#else
|
||||
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
#endif
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2;
|
||||
@@ -416,7 +455,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7(info, sect);
|
||||
wait_for_DQ7_1(info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -506,12 +545,27 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
#ifdef CFG_FLASH_2ND_16BIT_DEV
|
||||
static int write_word(flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
|
||||
return write_word_2(info, dest, data);
|
||||
} else {
|
||||
return write_word_1(info, dest, data);
|
||||
}
|
||||
}
|
||||
|
||||
static int write_word_1(flash_info_t * info, ulong dest, ulong data)
|
||||
#else
|
||||
static int write_word(flash_info_t * info, ulong dest, ulong data)
|
||||
#endif
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
|
||||
@@ -553,3 +607,311 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef CFG_FLASH_2ND_16BIT_DEV
|
||||
|
||||
#undef CFG_FLASH_WORD_SIZE
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
int n;
|
||||
CFG_FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong) addr;
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
|
||||
|
||||
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
|
||||
udelay(1000);
|
||||
|
||||
value = addr2[0];
|
||||
DEBUGF("FLASH MANUFACT: %x\n", value);
|
||||
|
||||
switch (value) {
|
||||
case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_STM;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[1]; /* device ID */
|
||||
|
||||
DEBUGF("\nFLASH DEVICEID: %x\n", value);
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
|
||||
info->flash_id += FLASH_AM320T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
|
||||
info->flash_id += FLASH_AM320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
|
||||
info->flash_id += FLASH_STMW320DT;
|
||||
info->sector_count = 67;
|
||||
info->size = 0x00400000; break; /* => 4 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00010000);
|
||||
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
|
||||
/* set sector offsets for top boot block type */
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
/* 1 x 16k boot sector */
|
||||
base -= 16 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
/* 2 x 8k boot sectors */
|
||||
for (n=0; n<2; ++n) {
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
/* 1 x 32k boot sector */
|
||||
base -= 32 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
} else {
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[i] =
|
||||
base + (i * 0x00010000) - 0x00030000;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
|
||||
|
||||
/* For AMD29033C flash we need to resend the command of *
|
||||
* reading flash protection for upper 8 Mb of flash */
|
||||
if (i == 32) {
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[2] & 1;
|
||||
}
|
||||
|
||||
/* issue bank reset to return to read mode */
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
static int wait_for_DQ7_2(flash_info_t * info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile CFG_FLASH_WORD_SIZE *addr =
|
||||
(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
start = get_timer(0);
|
||||
last = start;
|
||||
while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(CFG_FLASH_WORD_SIZE) 0x00800080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("- missing\n");
|
||||
} else {
|
||||
printf("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
|
||||
for (i = 0; i < 50; i++)
|
||||
udelay(1000); /* wait 1 ms */
|
||||
} else {
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
|
||||
}
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7_2(info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay(1000);
|
||||
|
||||
/* reset to read mode */
|
||||
addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
|
||||
addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
|
||||
printf(" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_word_2(flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
|
||||
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
|
||||
ulong start;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
|
||||
int flag;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer(0);
|
||||
while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CFG_FLASH_2ND_16BIT_DEV */
|
||||
|
||||
Reference in New Issue
Block a user