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Merge git://git.denx.de/u-boot-fsl-qoriq

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- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
This commit is contained in:
Tom Rini
2019-02-20 12:26:05 -05:00
parent 97f9830849 b0d4a85475
commit 176b32cd4f
99 changed files with 3140 additions and 33 deletions
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29
arch/arm/Kconfig
View File

@@ -1083,6 +1083,32 @@ config TARGET_LS2081ARDB
development platform that supports the QorIQ LS2081A/LS2041A
Layerscape Architecture processor.
config TARGET_LX2160ARDB
bool "Support lx2160ardb"
select ARCH_LX2160A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
help
Support for NXP LX2160ARDB platform.
The lx2160ardb (LX2160A Reference design board (RDB)
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
config TARGET_LX2160AQDS
bool "Support lx2160aqds"
select ARCH_LX2160A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
help
Support for NXP LX2160AQDS platform.
The lx2160aqds (LX2160A QorIQ Development System (QDS)
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
@@ -1237,6 +1263,7 @@ config TARGET_LS1043AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
imply SCSI
imply SCSI_AHCI
help
Support for Freescale LS1043AQDS platform.
@@ -1248,7 +1275,6 @@ config TARGET_LS1043ARDB
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
imply SCSI
help
Support for Freescale LS1043ARDB platform.
@@ -1555,6 +1581,7 @@ source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"

3
arch/arm/cpu/armv8/Kconfig
View File

@@ -106,7 +106,8 @@ config PSCI_RESET
!TARGET_LS1012AFRWY && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through

25
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@@ -2,6 +2,7 @@ config ARCH_LS1012A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -23,6 +24,7 @@ config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -49,13 +51,12 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
imply SCSI
imply SCSI_AHCI
imply CMD_PCI
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -90,6 +91,7 @@ config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -113,6 +115,8 @@ config ARCH_LS1088A
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_400
select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@@ -130,6 +134,7 @@ config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
@@ -145,6 +150,8 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
select FSL_TZASC_400
select FSL_TZPC_BP147
select SYS_FSL_ERRATUM_A008336 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@@ -230,6 +237,9 @@ config FSL_MC_ENET
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
config FSL_LAYERSCAPE
bool
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
@@ -346,6 +356,12 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config EMC2305
bool "Fan controller"
help
Enable the EMC2305 fan controller for configuration of fan
speed.
config SECURE_BOOT
bool "Secure Boot"
help
@@ -404,6 +420,11 @@ config FSL_TZASC_1
config FSL_TZASC_2
bool
config FSL_TZASC_400
bool
config FSL_TZPC_BP147
bool
endmenu
menu "Layerscape clock tree configuration"

22
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@@ -1099,15 +1099,29 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
fsl_rgmii_init();
#endif
config_core_prefetch();
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, xfi, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
* Now if a dpmac is enabled by serdes bits then it takes precedence
* over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
* that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
* then the dpmac is SGMII and not RGMII.
*
* Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
* fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
* or not? if it is (fsl_serdes_init has already enabled the dpmac),
* then don't enable it.
*/
fsl_rgmii_init();
#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif

20
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View File

@@ -548,12 +548,32 @@ void fsl_serdes_init(void)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
#ifdef CONFIG_ARCH_LX2160A
for (i = XFI1, j = 1; i <= XFI14; i++, j++)
xfi_dpmac[i] = j;
for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
sgmii_dpmac[i] = j;
for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
a25gaui_dpmac[i] = j;
for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
xlaui_dpmac[i] = j;
for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
caui2_dpmac[i] = j;
for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
caui4_dpmac[i] = j;
#else
for (i = XFI1, j = 1; i <= XFI8; i++, j++)
xfi_dpmac[i] = j;
for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
sgmii_dpmac[i] = j;
#endif
#endif
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,

4
arch/arm/dts/Makefile
View File

@@ -246,7 +246,9 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb
fsl-ls1088a-qds.dtb \
fsl-lx2160a-rdb.dtb \
fsl-lx2160a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \

17
arch/arm/dts/fsl-lx2160a-qds.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source
*
* Copyright 2018-2019 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

44
arch/arm/dts/fsl-lx2160a-rdb.dts Normal file
View File

@@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160ARDB device tree source
*
* Author: Priyanka Jain <priyanka.jain@nxp.com>
* Sriram Dash <sriram.dash@nxp.com>
*
* Copyright 2018 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "NXP Layerscape LX2160ARDB Board";
compatible = "fsl,lx2160ardb", "fsl,lx2160a";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};

63
arch/arm/dts/fsl-lx2160a.dtsi
View File

@@ -89,7 +89,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 240 0x4>; /* Level high type */
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
@@ -115,4 +115,65 @@
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
};
esdhc0: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
status = "disabled";
};
esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <0 63 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
non-removable;
little-endian;
bus-width = <4>;
status = "disabled";
};
sata0: sata@3200000 {
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 133 4>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
sata1: sata@3210000 {
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3210000 0x0 0x10000>;
interrupts = <0 136 4>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
sata2: sata@3220000 {
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3220000 0x0 0x10000>;
interrupts = <0 97 4>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
sata3: sata@3230000 {
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3230000 0x0 0x10000>;
interrupts = <0 100 4>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
};

3
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@@ -26,7 +26,6 @@
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#define CONFIG_FSL_TZASC_400
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@@ -121,8 +120,6 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4

4
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@@ -42,7 +42,11 @@
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
#ifndef CONFIG_ARCH_LX2160A
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
#else
#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
#endif
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
#ifdef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000

10
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@@ -2,7 +2,7 @@
/*
* LayerScape Internal Memory Map
*
* Copyright 2017-2018 NXP
* Copyright 2017-2019 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
@@ -350,6 +350,14 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#define FSL_CHASSIS3_SRDS3_REGSR 29
#define FSL_CHASSIS3_RCWSR12_REGSR 12
#define FSL_CHASSIS3_RCWSR13_REGSR 13
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_CHASSIS3_EC1_REGSR 26
#define FSL_CHASSIS3_EC2_REGSR 26

1
arch/arm/lib/relocate_64.S
View File

@@ -85,6 +85,7 @@ relocate_done:
isb sy
4: ldp x0, x1, [sp, #16]
bl __asm_flush_dcache_range
bl __asm_flush_l3_dcache
5: ldp x29, x30, [sp],#32
ret
ENDPROC(relocate_code)