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Merge branch 'master' of git://git.denx.de/u-boot-pxa

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This commit is contained in:
Wolfgang Denk 2010-07-15 22:49:12 +02:00
commit 16909f34b7
31 changed files with 2379 additions and 14 deletions
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4
MAKEALL
View File

@ -706,6 +706,7 @@ LIST_at91=" \
LIST_pxa=" \
cerf250 \
colibri_pxa270 \
cradle \
csb226 \
delta \
@ -715,10 +716,13 @@ LIST_pxa=" \
polaris \
pxa255_idp \
trizepsiv \
vpac270_nor \
vpac270_onenand \
wepep250 \
xaeniax \
xm250 \
xsengine \
zipitz2 \
zylonite \
"

9
Makefile
View File

@ -2178,6 +2178,15 @@ trizepsiv_config : unconfig
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
vpac270_nor_config \
vpac270_onenand_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring onenand,$@)" ] ; then \
echo "#define CONFIG_ONENAND_U_BOOT" \
>>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
#########################################################################
## ARM1136 Systems
#########################################################################

76
arch/arm/cpu/pxa/pxafb.c
View File

@ -112,6 +112,39 @@ vidinfo_t panel_info = {
vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_VOIPAC_LCD
# define LCD_BPP LCD_COLOR8
# define LCD_INVERT_COLORS
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x043008f8
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
vl_col: 640,
vl_row: 480,
vl_width: 157,
vl_height: 118,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_HIGH,
vl_hsp: CONFIG_SYS_HIGH,
vl_vsp: CONFIG_SYS_HIGH,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
vl_clor: 1,
vl_tft: 1,
vl_hpw: 32,
vl_blw: 144,
vl_elw: 32,
vl_vpw: 2,
vl_bfw: 13,
vl_efw: 30,
};
#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
@ -146,6 +179,40 @@ vidinfo_t panel_info = {
};
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LMS283GF05
# define LCD_BPP LCD_COLOR8
//# define LCD_INVERT_COLORS
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x043008f8
# define REG_LCCR3 0x03b00009
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_width: 240,
vl_height: 320,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_LOW,
vl_hsp: CONFIG_SYS_LOW,
vl_vsp: CONFIG_SYS_LOW,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
vl_clor: 1,
vl_tft: 1,
vl_hpw: 4,
vl_blw: 4,
vl_elw: 8,
vl_vpw: 4,
vl_bfw: 4,
vl_efw: 8,
};
#endif /* CONFIG_LMS283GF05 */
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
return 0;
}
#ifdef CONFIG_CPU_MONAHANS
static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_1_LCD;
#else
CKEN |= CKEN16_LCD;
#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);

48
arch/arm/cpu/pxa/start.S
View File

@ -34,6 +34,25 @@
.globl _start
_start: b reset
#ifdef CONFIG_PRELOADER
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678 /* now 16*4=64 */
#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@ -49,6 +68,7 @@ _data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@ -117,8 +137,10 @@ reset:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
#ifndef CONFIG_PRELOADER
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
#endif
ldr r2, _armboot_start
ldr r3, _bss_start
@ -135,28 +157,37 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_PRELOADER
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
#endif
ldr pc, _start_armboot
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
#else
_start_armboot: .word start_armboot
#endif
/****************************************************************************/
/* */
@ -296,7 +327,7 @@ setspeed_done:
*/
mov pc, lr
#ifndef CONFIG_PRELOADER
/****************************************************************************/
/* */
/* Interrupt handling */
@ -394,6 +425,7 @@ setspeed_done:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_PRELOADER */
/****************************************************************************/
@ -402,6 +434,12 @@ setspeed_done:
/* */
/****************************************************************************/
#ifdef CONFIG_PRELOADER
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words abort stack */
bl hang /* hang and never return */
#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@ -461,7 +499,7 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_PRELOADER */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/

324
arch/arm/include/asm/arch-pxa/macro.h Normal file
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@ -0,0 +1,324 @@
/*
* arch/arm/include/asm/arch-pxa/macro.h
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_PXA_MACRO_H__
#define __ASM_ARCH_PXA_MACRO_H__
#ifdef __ASSEMBLY__
#include <asm/macro.h>
#include <asm/arch/pxa-regs.h>
/*
* This macro performs a 32bit write to a memory location and makes sure the
* write operation really happened by performing a read back.
*
* Clobbered regs: r4, r5
*/
.macro write32rb addr, data
ldr r4, =\addr
ldr r5, =\data
str r5, [r4]
ldr r5, [r4]
.endm
/*
* This macro waits according to OSCR incrementation
*
* Clobbered regs: r4, r5, r6
*/
.macro pxa_wait_ticks ticks
ldr r4, =OSCR
mov r5, #0
str r5, [r4]
ldr r5, =\ticks
1:
ldr r6, [r4]
cmp r5, r6
bgt 1b
.endm
/*
* This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_gpio_setup
write32 GPSR0, CONFIG_SYS_GPSR0_VAL
write32 GPSR1, CONFIG_SYS_GPSR1_VAL
write32 GPSR2, CONFIG_SYS_GPSR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPSR3, CONFIG_SYS_GPSR3_VAL
#endif
write32 GPCR0, CONFIG_SYS_GPCR0_VAL
write32 GPCR1, CONFIG_SYS_GPCR1_VAL
write32 GPCR2, CONFIG_SYS_GPCR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPCR3, CONFIG_SYS_GPCR3_VAL
#endif
write32 GPDR0, CONFIG_SYS_GPDR0_VAL
write32 GPDR1, CONFIG_SYS_GPDR1_VAL
write32 GPDR2, CONFIG_SYS_GPDR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPDR3, CONFIG_SYS_GPDR3_VAL
#endif
write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
#endif
write32 PSSR, CONFIG_SYS_PSSR_VAL
.endm
/*
* This macro sets up the Memory controller of the PXA2xx CPU
*
* Clobbered regs: r3, r4, r5
*/
.macro pxa_mem_setup
/* This comes handy when setting MDREFR */
ldr r3, =MEMC_BASE
/*
* 1) Initialize Asynchronous static memory controller
*/
/* MSC0: nCS(0,1) */
write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
/* MSC1: nCS(2,3) */
write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
/* MSC2: nCS(4,5) */
write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
/* MCMEM0: Card Interface slot 0 timing */
write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
/* MCMEM1: Card Interface slot 1 timing */
write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
/*
* 3) Configure Fly-By DMA register
*/
write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
ldr r5, [r3, #MDREFR_OFFSET]
bic r5, r5, #0x0ff
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
ldr r4, =CONFIG_SYS_MDREFR_VAL
mov r6, r4
lsl r4, #20
lsr r4, #20 /* Get a valid DRI field */
orr r5, r5, r4 /* MDREFR user config with correct DRI */
orr r5, #MDREFR_K0RUN
orr r5, #MDREFR_SLFRSH
bic r5, #MDREFR_APD
bic r5, #MDREFR_E1PIN
str r5, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
/*
* 6) Initialize SDRAM
*/
bic r6, #MDREFR_SLFRSH
str r6, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
orr r6, #MDREFR_E1PIN
str r6, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
/* Fetch platform value of MDCNFG */
ldr r4, =CONFIG_SYS_MDCNFG_VAL
/* Disable all sdram banks */
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
/* Write initial value of MDCNFG, w/o enabling sdram banks */
str r4, [r3, #MDCNFG_OFFSET]
ldr r4, [r3, #MDCNFG_OFFSET]
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
pxa_wait_ticks 0x300
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
ldr r4, =CONFIG_SYS_DRAM_BASE
.rept 9
str r5, [r4]
.endr
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
ldr r5, =CONFIG_SYS_MDCNFG_VAL
ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
and r5, r5, r4
ldr r4, [r3, #MDCNFG_OFFSET]
orr r4, r4, r5
str r4, [r3, #MDCNFG_OFFSET]
ldr r4, [r3, #MDCNFG_OFFSET]
/*
* 10) Write MDMRS.
*/
ldr r4, =CONFIG_SYS_MDMRS_VAL
str r4, [r3, #MDMRS_OFFSET]
ldr r4, [r3, #MDMRS_OFFSET]
/*
* 11) Enable APD
*/
ldr r4, [r3, #MDREFR_OFFSET]
and r6, r6, #MDREFR_APD
orr r4, r4, r6
str r4, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
.endm
/*
* This macro tests if the CPU woke up from sleep and eventually resumes
*
* Clobbered regs: r4, r5
*/
.macro pxa_wakeup
ldr r4, =RCSR
ldr r5, [r4]
and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
str r5, [r4]
teq r5, #RCSR_SMR
bne pxa_wakeup_exit
ldr r4, =PSSR
mov r5, #PSSR_PH
str r5, [r4]
ldr r4, =PSPR
ldr pc, [r4]
pxa_wakeup_exit:
.endm
/*
* This macro disables all interupts on PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_intr_setup
write32 ICLR, 0
write32 ICMR, 0
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 ICLR2, 0
write32 ICMR2, 0
#endif
.endm
/*
* This macro configures clock on PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_clock_setup
/* Disable the peripheral clocks, and set the core clock frequency */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
write32 CKEN, CONFIG_SYS_CKEN
/* Write CCCR */
write32 CCCR, CONFIG_SYS_CCCR
#ifdef CONFIG_RTC
/* enable the 32Khz oscillator for RTC and PowerManager */
write32 OSCC, #OSCC_OON
ldr r4, =OSCC
/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
2:
ldr r5, [r4]
ands r5, r5, #1
beq 2b
#endif
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_PXA_MACRO_H__ */

10
arch/arm/include/asm/arch-pxa/pxa-regs.h
View File

@ -1132,10 +1132,18 @@ typedef void (*ExcpHndlr) (void) ;
#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
/*
* Interrupt Controller
*/

45
board/colibri_pxa270/Makefile Normal file
View File

@ -0,0 +1,45 @@
#
# Toradex Colibri PXA270 Support
#
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := colibri_pxa270.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

118
board/colibri_pxa270/colibri_pxa270.c Normal file
View File

@ -0,0 +1,118 @@
/*
* Toradex Colibri PXA270 Support
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
struct serial_device *default_serial_console (void)
{
return &serial_ffuart_device;
}
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR);
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH)
PSSR |= PSSR_OTGPH;
UHCRHDA &= ~(0x200);
UHCRHDA |= 0x100;
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
/* enable port 2 */
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
return 0;
}
void usb_board_init_fail(void)
{
return;
}
void usb_board_stop(void)
{
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCCOMS |= 1;
udelay(10);
CKEN &= ~CKEN10_USBHOST;
return;
}
#endif
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif

1
board/colibri_pxa270/config.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0xa1000000

36
board/colibri_pxa270/lowlevel_init.S Normal file
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@ -0,0 +1,36 @@
/*
* Toradex Colibri PXA270 Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
pxa_intr_setup
pxa_clock_setup
mov pc, lr

48
board/vpac270/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := vpac270.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

1
board/vpac270/config.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0xa1000000

40
board/vpac270/lowlevel_init.S Normal file
View File

@ -0,0 +1,40 @@
/*
* Voipac PXA270 Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
pxa_intr_setup
pxa_clock_setup
mov pc, lr

55
board/vpac270/u-boot.lds Normal file
View File

@ -0,0 +1,55 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

127
board/vpac270/vpac270.c Normal file
View File

@ -0,0 +1,127 @@
/*
* (C) Copyright 2004
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
struct serial_device *default_serial_console (void)
{
return &serial_ffuart_device;
}
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR);
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH)
PSSR |= PSSR_OTGPH;
UHCRHDA &= ~(0x200);
UHCRHDA |= 0x100;
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
/* enable port 2 */
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
return 0;
}
void usb_board_init_fail(void)
{
return;
}
void usb_board_stop(void)
{
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCCOMS |= 1;
udelay(10);
CKEN &= ~CKEN10_USBHOST;
return;
}
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif

54
board/zipitz2/Makefile Normal file
View File

@ -0,0 +1,54 @@
#
# Copyright (C) 2009
# Marek Vasut <marek.vasut@gmail.com>
#
# Heavily based on pxa255_idp platform
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := zipitz2.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
board/zipitz2/config.mk Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0xa1000000

40
board/zipitz2/lowlevel_init.S Normal file
View File

@ -0,0 +1,40 @@
/*
* Aeronix Zipit Z2 Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
pxa_intr_setup
pxa_clock_setup
mov pc, lr

56
board/zipitz2/u-boot.lds Normal file
View File

@ -0,0 +1,56 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}

213
board/zipitz2/zipitz2.c Normal file
View File

@ -0,0 +1,213 @@
/*
* Copyright (C) 2009
* Marek Vasut <marek.vasut@gmail.com>
*
* Heavily based on pxa255_idp platform
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <serial.h>
#include <asm/arch/hardware.h>
#include <spi.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_SPI
void lcd_start(void);
#else
inline void lcd_start(void) {};
#endif
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
/* arch number of Lubbock-Board */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
/* Enable LCD */
lcd_start();
return 0;
}
int board_late_init(void)
{
setenv("stdout", "serial");
setenv("stderr", "serial");
return 0;
}
struct serial_device *default_serial_console (void)
{
return &serial_stuart_device;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_CMD_SPI
struct {
unsigned char reg;
unsigned short data;
unsigned char mdelay;
} lcd_data[] = {
{ 0x07, 0x0000, 0 },
{ 0x13, 0x0000, 10 },
{ 0x11, 0x3004, 0 },
{ 0x14, 0x200F, 0 },
{ 0x10, 0x1a20, 0 },
{ 0x13, 0x0040, 50 },
{ 0x13, 0x0060, 0 },
{ 0x13, 0x0070, 200 },
{ 0x01, 0x0127, 0 },
{ 0x02, 0x0700, 0 },
{ 0x03, 0x1030, 0 },
{ 0x08, 0x0208, 0 },
{ 0x0B, 0x0620, 0 },
{ 0x0C, 0x0110, 0 },
{ 0x30, 0x0120, 0 },
{ 0x31, 0x0127, 0 },
{ 0x32, 0x0000, 0 },
{ 0x33, 0x0503, 0 },
{ 0x34, 0x0727, 0 },
{ 0x35, 0x0124, 0 },
{ 0x36, 0x0706, 0 },
{ 0x37, 0x0701, 0 },
{ 0x38, 0x0F00, 0 },
{ 0x39, 0x0F00, 0 },
{ 0x40, 0x0000, 0 },
{ 0x41, 0x0000, 0 },
{ 0x42, 0x013f, 0 },
{ 0x43, 0x0000, 0 },
{ 0x44, 0x013f, 0 },
{ 0x45, 0x0000, 0 },
{ 0x46, 0xef00, 0 },
{ 0x47, 0x013f, 0 },
{ 0x48, 0x0000, 0 },
{ 0x07, 0x0015, 30 },
{ 0x07, 0x0017, 0 },
{ 0x20, 0x0000, 0 },
{ 0x21, 0x0000, 0 },
{ 0x22, 0x0000, 0 },
};
void zipitz2_spi_sda(int set)
{
/* GPIO 13 */
if (set)
GPSR0 = (1 << 13);
else
GPCR0 = (1 << 13);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
GPCR0 = (1 << 22);
else
GPSR0 = (1 << 22);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
return !!(GPLR1 & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Always valid */
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
GPCR2 = (1 << 24);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
GPSR2 = (1 << 24);
}
void lcd_start(void)
{
int i;
unsigned char reg[3] = { 0x74, 0x00, 0 };
unsigned char data[3] = { 0x76, 0, 0 };
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
GAFR0_L |= 0x00800000;
/* Enable clock to all PWM */
CKEN |= 0x3;
/* Configure PWM2 */
PWM_CTRL2 = 0x4f;
PWM_PWDUTY2 = 0x2ff;
PWM_PERVAL2 = 792;
/* Toggle the reset pin to reset the LCD */
GPSR0 = (1 << 19);
udelay(100000);
GPCR0 = (1 << 19);
udelay(20000);
GPSR0 = (1 << 19);
udelay(20000);
/* Program the LCD init sequence */
for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
reg[0] = 0x74;
reg[1] = 0x0;
reg[2] = lcd_data[i].reg;
spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
data[0] = 0x76;
data[1] = lcd_data[i].data >> 8;
data[2] = lcd_data[i].data & 0xff;
spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
if (lcd_data[i].mdelay)
udelay(lcd_data[i].mdelay * 1000);
}
GPSR0 = (1 << 11);
}
#endif

2
boards.cfg
View File

@ -52,6 +52,7 @@ actux3 arm ixp
actux4 arm ixp
ixdp425 arm ixp
cerf250 arm pxa
colibri_pxa270 arm pxa
cradle arm pxa
csb226 arm pxa
delta arm pxa
@ -61,6 +62,7 @@ lubbock arm pxa
pleb2 arm pxa
xaeniax arm pxa
xm250 arm pxa
zipitz2 arm pxa
B2 arm s3c44b0 - dave
assabet arm sa1100
dnp1110 arm sa1100

12
common/lcd.c
View File

@ -41,7 +41,7 @@
#include <lcd.h>
#include <watchdog.h>
#if defined(CONFIG_PXA250)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
#include <asm/byteorder.h>
#endif
@ -503,7 +503,7 @@ void bitmap_plot (int x, int y)
uchar *bmap;
uchar *fb;
ushort *fb16;
#if defined(CONFIG_PXA250)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@ -519,7 +519,7 @@ void bitmap_plot (int x, int y)
if (NBITS(panel_info.vl_bpix) < 12) {
/* Leave room for default color map */
#if defined(CONFIG_PXA250)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
@ -615,7 +615,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
unsigned long pwidth = panel_info.vl_col;
unsigned colors, bpix, bmp_bpix;
unsigned long compression;
#if defined(CONFIG_PXA250)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
#if !defined(CONFIG_MCC200)
/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bmp_bpix == 8) {
#if defined(CONFIG_PXA250)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
@ -745,7 +745,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
if (bpix != 16) {
#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD)
*(fb++) = *(bmap++);
#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
*(fb++) = 255 - *(bmap++);

278
include/configs/colibri_pxa270.h Normal file
View File

@ -0,0 +1,278 @@
/*
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
#undef BOARD_LATE_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Environment settings
*/
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_ENV_OVERWRITE /* override default environment */
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
"bootm 0xa0000000; " \
"fi; " \
"bootm 0x80000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_LZMA /* LZMA compression support */
/*
* Serial Console Configuration
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Bootloader Components Configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#define CONFIG_CMD_FLASH
/*
* Networking Configuration
* chip on the Voipac PXA270 board
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_NET_MULTI 1
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x08000000
#define DM9000_IO (CONFIG_DM9000_BASE)
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#endif
/*
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* HUSH Shell Configuration
*/
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* DRAM Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
/*
* NOR FLASH
*/
#ifdef CONFIG_CMD_FLASH
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_ENV_IS_IN_FLASH 1
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x000000
#define CONFIG_SYS_MONITOR_LEN 0x40000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* GPIO settings
*/
#define CONFIG_SYS_GPSR0_VAL 0x00000000
#define CONFIG_SYS_GPSR1_VAL 0x00020000
#define CONFIG_SYS_GPSR2_VAL 0x0002C000
#define CONFIG_SYS_GPSR3_VAL 0x00000000
#define CONFIG_SYS_GPCR0_VAL 0x00000000
#define CONFIG_SYS_GPCR1_VAL 0x00000000
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0x08000000
#define CONFIG_SYS_GPDR1_VAL 0x0002A981
#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
#define CONFIG_SYS_GPDR3_VAL 0x00000000
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Clock settings
*/
#define CONFIG_SYS_CKEN 0x00500240
#define CONFIG_SYS_CCCR 0x02000290
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x000095f2
#define CONFIG_SYS_MSC1_VAL 0x00007ff4
#define CONFIG_SYS_MSC2_VAL 0x00000000
#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
#define CONFIG_SYS_MDMRS_VAL 0x00320032
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000001
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270"
#define CONFIG_USB_STORAGE
#endif
#endif /* __CONFIG_H */

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/*
* Voipac PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
#undef BOARD_LATE_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Environment settings
*/
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_ENV_OVERWRITE /* override default environment */
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
"fi; " \
"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
"fi; " \
"bootm 0x40000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_LZMA /* LZMA compression support */
/*
* Serial Console Configuration
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Bootloader Components Configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#undef CONFIG_LCD
#define CONFIG_CMD_IDE
#ifdef CONFIG_ONENAND_U_BOOT
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_ONENAND
#else
#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_ONENAND
#endif
/*
* Networking Configuration
* chip on the Voipac PXA270 board
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_NET_MULTI 1
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
#define DM9000_IO (CONFIG_DM9000_BASE)
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#endif
/*
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
/*
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* HUSH Shell Configuration
*/
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* DRAM Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
/*
* NOR FLASH
*/
#if defined(CONFIG_CMD_FLASH) /* NOR */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_ENV_IS_IN_FLASH 1
#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ONENAND_BASE 0x00000000
#define CONFIG_ENV_IS_IN_ONENAND 1
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#endif
#define CONFIG_SYS_MONITOR_BASE 0x000000
#define CONFIG_SYS_MONITOR_LEN 0x40000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* IDE
*/
#ifdef CONFIG_CMD_IDE
#define CONFIG_LBA48
#undef CONFIG_IDE_LED
#undef CONFIG_IDE_RESET
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
#define CONFIG_SYS_ATA_REG_OFFSET 0x120
#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
#define CONFIG_SYS_ATA_STRIDE 2
#endif
/*
* GPIO settings
*/
#define CONFIG_SYS_GPSR0_VAL 0x01308800
#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
#define CONFIG_SYS_GPSR2_VAL 0x922ac000
#define CONFIG_SYS_GPSR3_VAL 0x0161e800
#define CONFIG_SYS_GPCR0_VAL 0x00010000
#define CONFIG_SYS_GPCR1_VAL 0x0
#define CONFIG_SYS_GPCR2_VAL 0x0
#define CONFIG_SYS_GPCR3_VAL 0x0
#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
#define CONFIG_SYS_GPDR2_VAL 0x922affff
#define CONFIG_SYS_GPDR3_VAL 0x0161e904
#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Clock settings
*/
#define CONFIG_SYS_CKEN 0x00500240
#define CONFIG_SYS_CCCR 0x02000290
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
#define CONFIG_SYS_MSC1_VAL 0x02ccf974
#define CONFIG_SYS_MSC2_VAL 0x00000000
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
#define CONFIG_SYS_MEM_BUF_IMP 0x0f
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000001
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
/*
* LCD
*/
#ifdef CONFIG_LCD
#define CONFIG_VOIPAC_LCD
#endif
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
#define CONFIG_USB_STORAGE
#endif
#endif /* __CONFIG_H */

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/*
* Aeronix Zipit Z2 configuration file
*
* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
#undef BOARD_LATE_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Environment settings
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
#define CONFIG_SYS_GBL_DATA_SIZE 512
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
"source 0xa0000000; " \
"else " \
"bootm 0x60000; " \
"fi; "
#define CONFIG_BOOTARGS \
"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_LZMA /* LZMA compression support */
/*
* Serial Console Configuration
* STUART - the lower serial port on Colibri board
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Bootloader Components Configuration
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_SPI
/*
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#endif
/*
* SPI and LCD
*/
#ifdef CONFIG_CMD_SPI
#define CONFIG_SOFT_SPI
#define CONFIG_LCD
#define CONFIG_LMS283GF05
#define CONFIG_VIDEO_LOGO
#define CONFIG_CMD_BMP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
#undef SPI_INIT
#define SPI_DELAY udelay(10)
#define SPI_SDA(val) zipitz2_spi_sda(val)
#define SPI_SCL(val) zipitz2_spi_scl(val)
#define SPI_READ zipitz2_spi_read()
#ifndef __ASSEMBLY__
void zipitz2_spi_sda(int);
void zipitz2_spi_scl(int);
unsigned char zipitz2_spi_read(void);
#endif
#endif
/*
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* HUSH Shell Configuration
*/
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
/*
* Stack sizes
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* DRAM Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
/*
* NOR FLASH
*/
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_PROTECTION
/*
* GPIO settings
*/
#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
#define CONFIG_SYS_GPCR0_VAL 0x00000000
#define CONFIG_SYS_GPCR1_VAL 0x00000020
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff
#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL 0x06080400
#define CONFIG_SYS_GPSR1_VAL 0x007f0000
#define CONFIG_SYS_GPSR2_VAL 0x032a0000
#define CONFIG_SYS_GPSR3_VAL 0x00000180
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Clock settings
*/
#define CONFIG_SYS_CKEN 0x00511220
#define CONFIG_SYS_CCCR 0x00000190
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
#define CONFIG_SYS_MSC2_VAL 0x0000b884
#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000001
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
#endif /* __CONFIG_H */

2
include/lcd.h
View File

@ -87,7 +87,7 @@ typedef struct vidinfo {
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
#elif defined CONFIG_PXA250
#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
/*
* PXA LCD DMA descriptor
*/

83
onenand_ipl/board/vpac270/Makefile Normal file
View File

@ -0,0 +1,83 @@
IPL =onenand_ipl
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS := lowlevel_init.o
SOBJS += start.o
COBJS := vpac270.o
COBJS += onenand_read.o
COBJS += onenand_boot.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
onenandobj := $(OBJTREE)/onenand_ipl/
ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-Map $@.map -o $@
$(onenandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links from common files
# from cpu directory
$(obj)start.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
# from onenand_ipl directory
$(obj)onenand_ipl.h:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
$(obj)onenand_boot.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
$(obj)onenand_read.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)vpac270.c:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
$(obj)lowlevel_init.S:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)$.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

1
onenand_ipl/board/vpac270/config.mk Normal file
View File

@ -0,0 +1 @@
TEXT_BASE = 0x5c03fc00

34
onenand_ipl/board/vpac270/lowlevel_init.S Normal file
View File

@ -0,0 +1,34 @@
/*
* Voipac PXA270 Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
.globl lowlevel_init
lowlevel_init:
pxa_clock_setup
mov pc, lr

51
onenand_ipl/board/vpac270/u-boot.onenand.lds Normal file
View File

@ -0,0 +1,51 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) . = ALIGN(4); }
_end = .;
}

42
onenand_ipl/board/vpac270/vpac270.c Normal file
View File

@ -0,0 +1,42 @@
/*
* (C) Copyright 2004
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
int board_init (void)
{
return 0;
}
int s_init(int skip)
{
return 0;
}