phy: cadence: Sierra: Add support for PHY multilink configurations
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Swapnil Jakhade
Tom Rini
parent
960efc5edc
commit
168fbf79db
@ -29,7 +29,7 @@
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#include <regmap.h>
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#define NUM_SSC_MODE 3
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#define NUM_PHY_TYPE 3
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#define NUM_PHY_TYPE 4
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/* PHY register offsets */
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#define SIERRA_COMMON_CDB_OFFSET 0x0
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@ -183,6 +183,11 @@
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(0xD000 + ((ln) * (0x800 >> (3 - (offset)))))
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#define SIERRA_PHY_ISO_LINK_CTRL 0xB
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/* PHY PMA lane registers */
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#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \
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(0xF000 + ((ln) * (0x800 >> (3 - (offset)))))
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#define SIERRA_PHY_PMA_XCVR_CTRL 0x000
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#define SIERRA_MACRO_ID 0x00007364
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#define SIERRA_MAX_LANES 16
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#define PLL_LOCK_TIME 100
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@ -288,6 +293,8 @@ struct cdns_sierra_data {
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u8 reg_offset_shift;
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struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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[NUM_SSC_MODE];
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struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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[NUM_SSC_MODE];
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struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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[NUM_SSC_MODE];
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struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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@ -306,6 +313,7 @@ struct cdns_sierra_phy {
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struct regmap *regmap_phy_pcs_common_cdb;
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struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
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struct regmap *regmap_phy_pma_common_cdb;
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struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
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struct regmap *regmap_common_cdb;
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struct regmap_field *macro_id_type;
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struct regmap_field *phy_pll_cfg_1;
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@ -361,6 +369,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
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struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
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enum cdns_sierra_phy_type phy_type = ins->phy_type;
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enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
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struct cdns_sierra_vals *phy_pma_ln_vals;
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const struct cdns_reg_pairs *reg_pairs;
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struct cdns_sierra_vals *pcs_cmn_vals;
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struct regmap *regmap = phy->regmap;
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@ -368,7 +377,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
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int i, j;
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/* Initialise the PHY registers, unless auto configured */
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if (phy->autoconf)
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if (phy->autoconf || phy->nsubnodes > 1)
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return 0;
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clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
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@ -384,6 +393,18 @@ static int cdns_sierra_phy_init(struct phy *gphy)
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regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
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}
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/* PHY PMA lane registers configurations */
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phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
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if (phy_pma_ln_vals) {
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reg_pairs = phy_pma_ln_vals->reg_pairs;
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num_regs = phy_pma_ln_vals->num_regs;
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for (i = 0; i < ins->num_lanes; i++) {
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regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
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for (j = 0; j < num_regs; j++)
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regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
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}
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}
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/* PMA common registers configurations */
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pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
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if (pma_cmn_vals) {
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@ -417,10 +438,13 @@ static int cdns_sierra_phy_on(struct phy *gphy)
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u32 val;
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int ret;
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ret = reset_control_deassert(sp->phy_rst);
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if (ret) {
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dev_err(dev, "Failed to take the PHY out of reset\n");
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return ret;
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if (sp->nsubnodes == 1) {
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/* Take the PHY out of reset */
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ret = reset_control_deassert(sp->phy_rst);
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if (ret) {
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dev_err(dev, "Failed to take the PHY out of reset\n");
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return ret;
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}
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}
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/* Take the PHY lane group out of reset */
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@ -776,6 +800,116 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
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}
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sp->regmap_phy_pma_common_cdb = regmap;
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for (i = 0; i < SIERRA_MAX_LANES; i++) {
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block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, reg_offset_shift);
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regmap = cdns_regmap_init(dev, base, block_offset,
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block_offset_shift, reg_offset_shift);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
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return PTR_ERR(regmap);
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}
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sp->regmap_phy_pma_lane_cdb[i] = regmap;
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}
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return 0;
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}
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static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
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{
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const struct cdns_sierra_data *init_data = sp->init_data;
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enum cdns_sierra_phy_type phy_t1, phy_t2, tmp_phy_type;
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struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
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struct cdns_sierra_vals *phy_pma_ln_vals;
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const struct cdns_reg_pairs *reg_pairs;
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struct cdns_sierra_vals *pcs_cmn_vals;
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int i, j, node, mlane, num_lanes, ret;
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enum cdns_sierra_ssc_mode ssc;
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struct regmap *regmap;
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u32 num_regs;
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/* Maximum 2 links (subnodes) are supported */
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if (sp->nsubnodes != 2)
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return -EINVAL;
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clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
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clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
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/* PHY configured to use both PLL LC and LC1 */
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regmap_field_write(sp->phy_pll_cfg_1, 0x1);
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phy_t1 = sp->phys[0]->phy_type;
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phy_t2 = sp->phys[1]->phy_type;
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/*
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* First configure the PHY for first link with phy_t1. Get the array
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* values as [phy_t1][phy_t2][ssc].
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*/
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for (node = 0; node < sp->nsubnodes; node++) {
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if (node == 1) {
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/*
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* If first link with phy_t1 is configured, then
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* configure the PHY for second link with phy_t2.
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* Get the array values as [phy_t2][phy_t1][ssc].
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*/
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tmp_phy_type = phy_t1;
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phy_t1 = phy_t2;
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phy_t2 = tmp_phy_type;
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}
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mlane = sp->phys[node]->mlane;
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ssc = sp->phys[node]->ssc_mode;
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num_lanes = sp->phys[node]->num_lanes;
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/* PHY PCS common registers configurations */
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pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
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if (pcs_cmn_vals) {
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reg_pairs = pcs_cmn_vals->reg_pairs;
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num_regs = pcs_cmn_vals->num_regs;
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regmap = sp->regmap_phy_pcs_common_cdb;
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for (i = 0; i < num_regs; i++)
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regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
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}
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/* PHY PMA lane registers configurations */
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phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
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if (phy_pma_ln_vals) {
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reg_pairs = phy_pma_ln_vals->reg_pairs;
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num_regs = phy_pma_ln_vals->num_regs;
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for (i = 0; i < num_lanes; i++) {
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regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
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for (j = 0; j < num_regs; j++)
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regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
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}
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}
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/* PMA common registers configurations */
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pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
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if (pma_cmn_vals) {
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reg_pairs = pma_cmn_vals->reg_pairs;
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num_regs = pma_cmn_vals->num_regs;
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regmap = sp->regmap_common_cdb;
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for (i = 0; i < num_regs; i++)
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regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
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}
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/* PMA TX lane registers configurations */
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pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
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if (pma_ln_vals) {
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reg_pairs = pma_ln_vals->reg_pairs;
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num_regs = pma_ln_vals->num_regs;
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for (i = 0; i < num_lanes; i++) {
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regmap = sp->regmap_lane_cdb[i + mlane];
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for (j = 0; j < num_regs; j++)
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regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
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}
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}
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}
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/* Take the PHY out of reset */
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ret = reset_control_deassert(sp->phy_rst);
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if (ret)
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return ret;
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return 0;
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}
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@ -896,8 +1030,11 @@ static int cdns_sierra_link_probe(struct udevice *dev)
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sp->num_lanes += inst->num_lanes;
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/* If more than one subnode, configure the PHY as multilink */
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if (!sp->autoconf && sp->nsubnodes > 1)
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regmap_field_write(sp->phy_pll_cfg_1, 0x1);
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if (!sp->autoconf && sp->nsubnodes > 1) {
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ret = cdns_sierra_phy_configure_multilink(sp);
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if (ret)
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return ret;
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}
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return 0;
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}
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