leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source
This commit is contained in:
Wolfgang Denk 2011-05-12 19:26:45 +02:00
commit 162eee4106
16 changed files with 115 additions and 37 deletions
MAKEALL
arch/arm
cpu/arm1136/mx31
generic.c
include/asm
arch-kirkwood
kw88f6281.h
arch-mx31
clock.himx-regs.h
board
Marvell/openrd
Makefilekwbimage.cfgopenrd.copenrd.h
davinci/da8xxevm
da850evm.c
freescale/mx31pdk
mx31pdk.c
boards.cfg
drivers/gpio
mxc_gpio.c
include/configs
mv-common.hmx31pdk.hopenrd.h

2
MAKEALL
View File

@ -361,6 +361,8 @@ LIST_ARM9=" \
omap5912osk \
omap730p2 \
openrd_base \
openrd_client \
openrd_ultimate \
rd6281a \
sbc2410x \
scb9328 \

31
arch/arm/cpu/arm1136/mx31/generic.c
View File

@ -107,18 +107,18 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
}
struct mx3_cpu_type mx31_cpu_type[] = {
{ .srev = 0x00, .v = "1.0" },
{ .srev = 0x10, .v = "1.1" },
{ .srev = 0x11, .v = "1.1" },
{ .srev = 0x12, .v = "1.15" },
{ .srev = 0x13, .v = "1.15" },
{ .srev = 0x14, .v = "1.2" },
{ .srev = 0x15, .v = "1.2" },
{ .srev = 0x28, .v = "2.0" },
{ .srev = 0x29, .v = "2.0" },
{ .srev = 0x00, .v = 0x10 },
{ .srev = 0x10, .v = 0x11 },
{ .srev = 0x11, .v = 0x11 },
{ .srev = 0x12, .v = 0x1F },
{ .srev = 0x13, .v = 0x1F },
{ .srev = 0x14, .v = 0x12 },
{ .srev = 0x15, .v = 0x12 },
{ .srev = 0x28, .v = 0x20 },
{ .srev = 0x29, .v = 0x20 },
};
char *get_cpu_rev(void)
u32 get_cpu_rev(void)
{
u32 i, srev;
@ -129,7 +129,8 @@ char *get_cpu_rev(void)
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
return mx31_cpu_type[i].v;
return "unknown";
return srev | 0x8000;
}
char *get_reset_cause(void)
@ -161,8 +162,12 @@ char *get_reset_cause(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
printf("CPU: Freescale i.MX31 rev %s at %d MHz.",
get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000);
u32 srev = get_cpu_rev();
printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.",
(srev & 0xF0) >> 4, (srev & 0x0F),
((srev & 0x8000) ? " unknown" : ""),
mx31_get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}

8
arch/arm/include/asm/arch-kirkwood/kw88f6281.h
View File

@ -27,11 +27,13 @@
#ifndef _ASM_ARCH_KW88F6281_H
#define _ASM_ARCH_KW88F6281_H
/* SOC specific definations */
/* SOC specific definitions */
#define KW88F6281_REGS_PHYS_BASE 0xf1000000
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock defination*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#endif
#endif /* _ASM_ARCH_KW88F6281_H */

1
arch/arm/include/asm/arch-mx31/clock.h
View File

@ -31,5 +31,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
void mxc_hw_watchdog_enable(void);
#endif /* __ASM_ARCH_CLOCK_H */

2
arch/arm/include/asm/arch-mx31/imx-regs.h
View File

@ -105,7 +105,7 @@ struct iim_regs {
struct mx3_cpu_type {
u8 srev;
char *v;
u32 v;
};
#define IOMUX_PADNUM_MASK 0x1ff

2
board/Marvell/openrd_base/Makefile → board/Marvell/openrd/Makefile
View File

@ -31,7 +31,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := openrd_base.o
COBJS := openrd.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

0
board/Marvell/openrd_base/kwbimage.cfg → board/Marvell/openrd/kwbimage.cfg
View File

33
board/Marvell/openrd_base/openrd_base.c → board/Marvell/openrd/openrd.c
View File

@ -31,7 +31,7 @@
#include <miiphy.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
#include "openrd_base.h"
#include "openrd.h"
DECLARE_GLOBAL_DATA_PTR;
@ -110,7 +110,13 @@ int board_init(void)
/*
* arch number of board
*/
#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
@ -118,12 +124,11 @@ int board_init(void)
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
/* Configure and enable MV88E1116/88E1121 PHY */
void mv_phy_init(char *name)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
@ -148,6 +153,24 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
printf(PHY_NO" Initialized on %s\n", name);
}
void reset_phy(void)
{
mv_phy_init("egiga0");
#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
/* Kirkwood ethernet driver is written with the assumption that in case
* of multiple PHYs, their addresses are consecutive. But unfortunately
* in case of OpenRD-Client, PHY addresses are not consecutive.*/
miiphy_write("egiga1", 0xEE, 0xEE, 24);
#endif
#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
/* configure and initialize both PHY's */
mv_phy_init("egiga1");
#endif
}
#endif /* CONFIG_RESET_PHY_R */

0
board/Marvell/openrd_base/openrd_base.h → board/Marvell/openrd/openrd.h
View File

4
board/davinci/da8xxevm/da850evm.c
View File

@ -179,12 +179,12 @@ int board_init(void)
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(0) |
DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif

16
board/freescale/mx31pdk/mx31pdk.c
View File

@ -28,9 +28,17 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
mxc_hw_watchdog_reset();
}
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@ -68,6 +76,14 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
mxc_hw_watchdog_enable();
#endif
return 0;
}
int checkboard(void)
{
printf("Board: MX31PDK\n");

4
boards.cfg
View File

@ -108,7 +108,9 @@ suen8 arm arm926ejs km_arm keymile
mgcoge2un arm arm926ejs km_arm keymile kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
openrd_base arm arm926ejs - Marvell kirkwood
openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT
openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
rd6281a arm arm926ejs - Marvell kirkwood
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood

5
drivers/gpio/mxc_gpio.c
View File

@ -24,6 +24,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <mxc_gpio.h>
#include <errno.h>
/* GPIO port description */
static unsigned long gpio_ports[] = {
@ -47,7 +48,7 @@ int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction)
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
return 1;
return -EINVAL;
gpio &= 0x1f;
@ -95,7 +96,7 @@ int mxc_gpio_get(unsigned int gpio)
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
return -1;
return -EINVAL;
gpio &= 0x1f;

8
include/configs/mv-common.h
View File

@ -113,6 +113,9 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* ====> Include platform Common Definitions */
#include <asm/arch/config.h>
/*
* DRAM Banks configuration, Custom config can be done in <board>.h
*/
@ -124,10 +127,7 @@
#endif
#endif /* CONFIG_NR_DRAM_BANKS */
/* ====> Include platform Common Definations */
#include <asm/arch/config.h>
/* ====> Include driver Common Definations */
/* ====> Include driver Common Definitions */
/*
* Common NAND configuration
*/

3
include/configs/mx31pdk.h
View File

@ -61,6 +61,7 @@
#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_HW_WATCHDOG
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
@ -98,6 +99,8 @@
*/
#undef CONFIG_CMD_IMLS
#define BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \

33
include/configs/openrd_base.h → include/configs/openrd.h
View File

@ -27,13 +27,25 @@
* MA 02110-1301 USA
*/
#ifndef _CONFIG_OPENRD_BASE_H
#define _CONFIG_OPENRD_BASE_H
#ifndef _CONFIG_OPENRD_H
#define _CONFIG_OPENRD_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nOpenRD_base"
#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
#else
# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
# define CONFIG_IDENT_STRING "\nOpenRD-Client"
# else
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_IDENT_STRING "\nOpenRD-Base"
# else
# error Unknown OpenRD board specified
# endif
# endif
#endif
/*
* High Level Configuration Options (easy to change)
@ -48,6 +60,7 @@
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
@ -105,8 +118,18 @@
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
# else
# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
# endif
# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_PHY_BASE_ADR 0x0
# define PHY_NO "88E1121"
# else
# define CONFIG_PHY_BASE_ADR 0x8
# define PHY_NO "88E1116"
# endif
#endif /* CONFIG_CMD_NET */
/*