leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Browse Source 
Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2017-04-13 10:17:06 -04:00
commit 1622559066
64 changed files with 4935 additions and 245 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -93,10 +93,9 @@ S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/arm926ejs/imx/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/cpu/imx-common/
F: arch/arm/imx-common/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/

4
arch/arm/Kconfig
View File

@ -1242,6 +1242,8 @@ source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/imx-common/Kconfig"
source "board/aries/m28evk/Kconfig"
source "board/aries/m53evk/Kconfig"
source "board/bosch/shc/Kconfig"
source "board/BuR/brxre1/Kconfig"
source "board/BuR/brppt1/Kconfig"
@ -1262,8 +1264,6 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"

16
arch/arm/cpu/armv7/mx6/Kconfig
View File

@ -155,6 +155,19 @@ config TARGET_MX6CUBOXI
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_MX6LOGICPD
bool "Logic PD i.MX6 SOM"
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_PMIC
select DM_REGULATOR
select OF_CONTROL
config TARGET_MX6QARM2
bool "mx6qarm2"
@ -172,6 +185,7 @@ config TARGET_MX6Q_ICORE
config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select DM
@ -253,6 +267,7 @@ config TARGET_MX6UL_GEAM
select SUPPORT_SPL
config TARGET_MX6UL_ISIOT
bool "Support Engicam Is.IoT MX6UL"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM
@ -404,6 +419,7 @@ source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"

8
arch/arm/cpu/armv7/mx7ulp/scg.c
View File

@ -504,7 +504,9 @@ u32 decode_pll(enum pll_clocks pll)
num = readl(&scg1_regs->spllnum);
denom = readl(&scg1_regs->splldenom);
return (infreq / pre_div) * (mult + num / denom);
infreq = infreq / pre_div;
return infreq * mult + infreq * num / denom;
case PLL_A7_APLL:
reg = readl(&scg1_regs->apllcsr);
@ -531,7 +533,9 @@ u32 decode_pll(enum pll_clocks pll)
num = readl(&scg1_regs->apllnum);
denom = readl(&scg1_regs->aplldenom);
return (infreq / pre_div) * (mult + num / denom);
infreq = infreq / pre_div;
return infreq * mult + infreq * num / denom;
case PLL_USB:
reg = readl(&scg1_regs->upllcsr);

2
arch/arm/dts/Makefile
View File

@ -323,11 +323,13 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sl-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
imx6sx-sabreauto.dtb \
imx6ul-geam-kit.dtb \
imx6ul-isiot-emmc.dtb \

190
arch/arm/dts/imx6q-logicpd.dts Normal file
View File

@ -0,0 +1,190 @@
/*
* Copyright 2017 Logic PD, Inc.
* Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6qdl-logicpd.dtsi"
/ {
model = "Logic PD i.MX6QDL SOM";
compatible = "fsl,imx6q";
reg_usb_otg_vbus: regulator-otg-vbus@0 {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_h1_vbus: regulator-usbh1vbus@1 {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
reg_3v3: regulator-3v3@2 {
compatible = "regulator-fixed";
regulator-name = "reg_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbh2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh2>;
phy_type = "hsic";
disable-over-current;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-speed = <10>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */
>;
};
pinctrl_usbh2: usbh2grp {
fsl,pins = <
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};

361
arch/arm/dts/imx6qdl-logicpd.dtsi Normal file
View File

@ -0,0 +1,361 @@
/*
* Copyright 2016 Logic PD
* This file is adapted from imx6qdl-sabresd.dtsi.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6q.dtsi"
/ {
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x10000000 0x80000000>;
};
};
/* Reroute power feeding the CPU to come from the external PMIC */
&reg_arm
{
vin-supply = <&sw1a_reg>;
};
&reg_soc
{
vin-supply = <&sw1c_reg>;
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-name = "vddcore";
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-name = "vddsoc";
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "gen_3v3";
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-name = "sw3a_vddr";
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-name = "sw3b_vddr";
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "gen_rgmii";
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-name = "gen_5v0";
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "gen_vsns";
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "gen_1v5";
};
vgen2_reg: vgen2 {
regulator-name = "vgen2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-name = "gen_vadj_0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
vgen4_reg: vgen4 {
regulator-name = "gen_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-name = "gen_adj_1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-name = "gen_2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
};
};
mfg_eeprom: at24@51 {
compatible = "atmel,24c64";
pagesize = <32>;
read-only;
reg = <0x51>;
};
user_eeprom: at24@52 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x52>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000
MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000
MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000
MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000
MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000
MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000
MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000
MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000
MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000
MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000
MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000
MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&sw2_reg>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1837";
reg = <2>;
interrupt-parent = <&gpio7>;
interrupts = <1 GPIO_ACTIVE_HIGH>;
};
};

641
arch/arm/dts/imx6sl-evk.dts Normal file
View File

@ -0,0 +1,641 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sl.dtsi"
/ {
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user {
label = "debug";
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_aud3v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply-3v15";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-boot-on;
};
reg_aud4v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "wm8962-supply-4v2";
regulator-min-microvolt = <4325000>;
regulator-max-microvolt = <4325000>;
regulator-boot-on;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio4 3 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux3>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
phy-mode = "rmii";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
DCVDD-supply = <&vgen3_reg>;
DBVDD-supply = <&reg_aud3v>;
AVDD-supply = <&vgen3_reg>;
CPVDD-supply = <&vgen3_reg>;
MICVDD-supply = <&reg_aud3v>;
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <&reg_aud4v>;
SPKVDD2-supply = <&reg_aud4v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6sl-evk {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
>;
};
pinctrl_audmux3: audmux3grp {
fsl,pins = <
MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
>;
};
pinctrl_fec_sleep: fecgrp-sleep {
fsl,pins = <
MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
>;
};
pinctrl_pwm1: pwmgrp {
fsl,pins = <
MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
status = "okay";
};

1077
arch/arm/dts/imx6sl-pinfunc.h Normal file
View File

File diff suppressed because it is too large Load Diff

927
arch/arm/dts/imx6sl.dtsi Normal file
View File

@ -0,0 +1,927 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1225000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <4 2 3>;
arm,data-latency = <4 2 3>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
aips1: aips-bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba: spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
compatible = "fsl,imx6sl-spdif",
"fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 14 18 0>,
<&sdma 15 18 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
<&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
status = "disabled";
};
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ECSPI1>,
<&clks IMX6SL_CLK_ECSPI1>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ECSPI2>,
<&clks IMX6SL_CLK_ECSPI2>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ECSPI3>,
<&clks IMX6SL_CLK_ECSPI3>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi4: ecspi@02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ECSPI4>,
<&clks IMX6SL_CLK_ECSPI4>;
clock-names = "ipg", "per";
status = "disabled";
};
uart5: serial@02018000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@02024000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ssi1: ssi@02028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
<&clks IMX6SL_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
ssi2: ssi@0202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
<&clks IMX6SL_CLK_SSI2>;
clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
ssi3: ssi@02030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sl-ssi",
"fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
<&clks IMX6SL_CLK_SSI3>;
clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
uart3: serial@02034000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@02038000 {
compatible = "fsl,imx6sl-uart",
"fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM1>,
<&clks IMX6SL_CLK_PWM1>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM2>,
<&clks IMX6SL_CLK_PWM2>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM3>,
<&clks IMX6SL_CLK_PWM3>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PWM4>,
<&clks IMX6SL_CLK_PWM4>;
clock-names = "ipg", "per";
};
gpt: gpt@02098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_GPT>,
<&clks IMX6SL_CLK_GPT_SERIAL>;
clock-names = "ipg", "per";
};
gpio1: gpio@0209c000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
<0 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
<&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
<&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
<&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
<&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
};
gpio2: gpio@020a0000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
<0 69 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
<&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
<&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
<&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
<&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
<&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
};
gpio3: gpio@020a4000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
<0 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
<&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
<&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
<&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
<&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
<&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
<&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
<&iomuxc 31 102 1>;
};
gpio4: gpio@020a8000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
<0 73 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
<&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
<&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
<&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
<&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
<&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
<&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
<&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
<&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
<&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
<&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
<&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
<&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
<&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
};
gpio5: gpio@020ac000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
<0 75 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
<&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
<&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
<&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
<&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
<&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
<&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
<&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
<&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
<&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
<&iomuxc 21 161 1>;
};
kpp: kpp@020b8000 {
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
status = "disabled";
};
wdog1: wdog@020bc000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
wdog2: wdog@020c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
status = "disabled";
};
clks: ccm@020c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
<0 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
"syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
};
reg_arm: regulator-vddcore {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_pu: regulator-vddpu {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <26>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <28>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
tempmon: tempmon {
compatible = "fsl,imx6q-tempmon";
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
fsl,tempmon-data = <&ocotp>;
clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
};
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBPHY2>;
fsl,anatop = <&anatop>;
};
snvs: snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
<0 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs_poweroff: snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
mask = <0x60>;
status = "disabled";
};
};
epit1: epit@020d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
};
epit2: epit@020d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@020d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
<0 96 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gpc: gpc@020dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
#power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6sl-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
};
csi: csi@020e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
};
spdc: spdc@020e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SDMA>,
<&clks IMX6SL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
/* imx6sl reuses imx6q sdma firmware */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
epdc: epdc@020f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@020f8000 {
compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
<&clks IMX6SL_CLK_LCDIF_AXI>,
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
};
dcp: dcp@020fc000 {
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
<0 100 IRQ_TYPE_LEVEL_HIGH>,
<0 101 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
usbotg1: usb@02184000 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
usbotg2: usb@02184200 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
usbh: usb@02184400 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
};
fec: ethernet@02188000 {
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ENET>,
<&clks IMX6SL_CLK_ENET_REF>;
clock-names = "ipg", "ahb";
status = "disabled";
};
usdhc1: usdhc@02190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USDHC1>,
<&clks IMX6SL_CLK_USDHC1>,
<&clks IMX6SL_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@02194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USDHC2>,
<&clks IMX6SL_CLK_USDHC2>,
<&clks IMX6SL_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@02198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USDHC3>,
<&clks IMX6SL_CLK_USDHC3>,
<&clks IMX6SL_CLK_USDHC3>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc4: usdhc@0219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USDHC4>,
<&clks IMX6SL_CLK_USDHC4>,
<&clks IMX6SL_CLK_USDHC4>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
i2c1: i2c@021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_I2C1>;
status = "disabled";
};
i2c2: i2c@021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_I2C2>;
status = "disabled";
};
i2c3: i2c@021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_I2C3>;
status = "disabled";
};
mmdc: mmdc@021b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
rngb: rngb@021b4000 {
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
};
weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
fsl,weim-cs-gpr = <&gpr>;
status = "disabled";
};
ocotp: ocotp@021bc000 {
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
};
audmux: audmux@021d8000 {
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
};
};
};

60
board/advantech/dms-ba16/dms-ba16.c
View File

@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
/* Reset AR8033 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
udelay(500);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 28), 1);
mdelay(1);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
@ -303,7 +304,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
/* set debug port address: SerDes Test and System Mode Control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
/* enable rgmii tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
/* set the reserved bits to avoid board specific voltage peak issue*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
@ -534,11 +536,61 @@ static const struct boot_mode board_boot_modes[] = {
};
#endif
void pmic_init(void)
{
#define DA9063_ADDR 0x58
#define BCORE2_CONF 0x9D
#define BCORE1_CONF 0x9E
#define BPRO_CONF 0x9F
#define BIO_CONF 0xA0
#define BMEM_CONF 0xA1
#define BPERI_CONF 0xA2
#define MODE_BIT_H 7
#define MODE_BIT_L 6
uchar val;
i2c_set_bus_num(2);
i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
val |= (1 << MODE_BIT_H);
val &= ~(1 << MODE_BIT_L);
i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
}
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/*
* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI
@ -555,11 +607,15 @@ int board_late_init(void)
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
pwm_enable(0);
#endif
#ifdef CONFIG_CMD_SATA
setup_ba16_sata();
#endif
/* board specific pmic init */
pmic_init();
return 0;
}

2
board/denx/m28evk/Kconfig → board/aries/m28evk/Kconfig
View File

@ -4,7 +4,7 @@ config SYS_BOARD
default "m28evk"
config SYS_VENDOR
default "denx"
default "aries"
config SYS_SOC
default "mxs"

2
board/denx/m28evk/MAINTAINERS → board/aries/m28evk/MAINTAINERS
View File

@ -1,6 +1,6 @@
M28EVK BOARD
M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained
F: board/denx/m28evk/
F: board/aries/m28evk/
F: include/configs/m28evk.h
F: configs/m28evk_defconfig

0
board/denx/m28evk/Makefile → board/aries/m28evk/Makefile
View File

6
board/denx/m28evk/README → board/aries/m28evk/README
View File

@ -1,12 +1,12 @@
DENX M28EVK
===========
Aries M28EVK
============
Files of the M28/M28EVK port
----------------------------
arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
board/denx/m28evk/ - M28EVK board specific files
board/aries/m28evk/ - M28EVK board specific files
include/configs/m28evk.h - M28EVK configuration file
Follow the instructions from doc/README.mxs to generate a bootable SD card or to

6
board/denx/m28evk/m28evk.c → board/aries/m28evk/m28evk.c
View File

@ -1,5 +1,5 @@
/*
* DENX M28 module
* Aries M28 module
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -93,7 +93,7 @@ int board_mmc_init(bd_t *bis)
int fecmxc_mii_postcall(int phy)
{
#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
#if defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10)
/* KZ8031 PHY on old boards. */
const uint32_t freq = 0x0080;
#else
@ -123,7 +123,7 @@ int board_eth_init(bd_t *bis)
CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
CLKCTRL_ENET_TIME_SEL_RMII_CLK);
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
/* Reset the new PHY */
gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
udelay(10000);

6
board/denx/m28evk/spl_boot.c → board/aries/m28evk/spl_boot.c
View File

@ -1,5 +1,5 @@
/*
* DENX M28 Boot setup
* ARIES M28 Boot setup
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -56,7 +56,7 @@ const iomux_cfg_t iomux_setup[] = {
MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
/* UART1 */
#ifdef CONFIG_DENX_M28_V10
#ifdef CONFIG_ARIES_M28_V10
MX28_PAD_AUART0_CTS__DUART_RX,
MX28_PAD_AUART0_RTS__DUART_TX,
#else
@ -132,7 +132,7 @@ const iomux_cfg_t iomux_setup[] = {
MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
#endif

2
board/denx/m53evk/Kconfig → board/aries/m53evk/Kconfig
View File

@ -4,7 +4,7 @@ config SYS_BOARD
default "m53evk"
config SYS_VENDOR
default "denx"
default "aries"
config SYS_SOC
default "mx5"

2
board/denx/m53evk/MAINTAINERS → board/aries/m53evk/MAINTAINERS
View File

@ -1,6 +1,6 @@
M53EVK BOARD
M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained
F: board/denx/m53evk/
F: board/aries/m53evk/
F: include/configs/m53evk.h
F: configs/m53evk_defconfig

2
board/denx/m53evk/Makefile → board/aries/m53evk/Makefile
View File

@ -1,5 +1,5 @@
#
# DENX M53EVK
# Aries M53EVK
# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+

2
board/denx/m53evk/imximage.cfg → board/aries/m53evk/imximage.cfg
View File

@ -1,5 +1,5 @@
/*
* DENX M53 DRAM init values
* Aries M53 DRAM init values
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+

4
board/denx/m53evk/m53evk.c → board/aries/m53evk/m53evk.c
View File

@ -1,5 +1,5 @@
/*
* DENX M53 module
* Aries M53 module
*
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
*
@ -381,7 +381,7 @@ int board_init(void)
int checkboard(void)
{
puts("Board: DENX M53EVK\n");
puts("Board: Aries M53EVK\n");
return 0;
}

55
board/freescale/mx6sabresd/README
View File

@ -1,17 +1,19 @@
How to use and build U-Boot on mx6sabresd:
----------------------------------
Currently there are three methods for booting mx6sabresd boards:
Currently there are four methods for booting mx6sabresd boards:
1. Booting via Normal U-Boot (u-boot.imx)
1. Booting from SD card via normal U-Boot (u-boot.imx)
2. Booting via SPL (SPL and u-boot.img)
2. Booting from eMMC via normal U-Boot
3. Booting via Falcon mode (SPL launches the kernel directly)
3. Booting via SPL (SPL and u-boot.img)
4. Booting via Falcon mode (SPL launches the kernel directly)
1. Booting via Normal U-Boot
----------------------------
1. Booting from SD card via normal U-Boot
-----------------------------------------
$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
@ -28,7 +30,44 @@ This will generate the image called u-boot.imx.
$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
2. Booting via SPL
2. Booting from eMMC via normal U-Boot
--------------------------------------
$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
or
$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
$ make
This will generate the image called u-boot.imx.
- Flash the u-boot.imx binary into the eMMC:
Set SW6 to download mode: 00001100
Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader
tool (https://github.com/boundarydevices/imx_usb_loader):
$ sudo ./imx_usb u-boot.imx
In U-boot change the eMMC partition config:
=> mmc partconf 2 1 0 0
Mount the eMMC in the host PC:
=> ums 0 mmc 2
Flash the u-boot.imx binary
$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync
Set SW6 to eMMC 8-bit boot: 11010110
3. Booting via SPL
------------------
Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
@ -48,7 +87,7 @@ $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
3. Booting via Falcon mode
4. Booting via Falcon mode
--------------------------
$ make mx6sabresd_spl_defconfig

258
board/freescale/mx6slevk/mx6slevk.c
View File

@ -47,11 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
@ -155,157 +150,55 @@ static void setup_iomux_fec(void)
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* Power up LAN8720 PHY */
gpio_request(ETH_PHY_POWER, "eth_pwr");
gpio_direction_output(ETH_PHY_POWER , 1);
udelay(15000);
}
#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
};
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
* mmc2 USDHC3
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize "
"mmc dev %d\n", i);
return ret;
}
}
return 0;
#else
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
/* Boot from USDHC */
port = (val >> 11) & 0x3;
switch (port) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.sda = {
.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
.gp = IMX_GPIO_NR(3, 13),
},
.scl = {
.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
.gp = IMX_GPIO_NR(3, 12),
},
};
#ifdef CONFIG_DM_PMIC_PFUZE100
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
int ret;
u32 dev_id, rev_id, i;
u32 switch_num = 6;
u32 offset = PFUZE100_SW1CMODE;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV)
return 0;
return pfuze_mode_init(p, APS_PFM);
if (ret != 0)
return ret;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* set SW1AB staby volatage 0.975V */
pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
/* set SW1C staby volatage 0.975V */
pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
for (i = 0; i < switch_num - 1; i++)
pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
return 0;
}
#endif
@ -374,9 +267,7 @@ int board_ehci_hcd_init(int port)
int board_early_init_f(void)
{
setup_iomux_uart();
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
return 0;
}
@ -385,8 +276,9 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#ifdef CONFIG_MXC_SPI
gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
setup_spi();
#endif
#ifdef CONFIG_FEC_MXC
@ -411,6 +303,76 @@ int checkboard(void)
#include <spl.h>
#include <libfdt.h>
#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
/* Boot from USDHC */
port = (val >> 11) & 0x3;
switch (port) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdqs0 = 0x00003030,
.dram_sdqs1 = 0x00003030,

4
board/gateworks/gw_ventana/MAINTAINERS
View File

@ -3,4 +3,6 @@ M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
F: board/gateworks/gw_ventana/
F: include/configs/gw_ventana.h
F: configs/gwventana_defconfig
F: configs/gwventana_nand_defconfig
F: configs/gwventana_emmc_defconfig
F: configs/gwventana_gw5904_defconfig

488
board/gateworks/gw_ventana/common.c
View File

@ -38,6 +38,44 @@ void setup_iomux_uart(void)
}
/* MMC */
static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* 4-bit microSD on SD2 */
static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* 8-bit eMMC on SD2/NAND */
static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@ -352,6 +390,107 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* VID_EN */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
/* RS485_EN */
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* USBH2_PEN (OTG) */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* 12V0_PWR_EN */
IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
/* BKLT_12VEN */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* EMMY_PDN# */
IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
/* EMMY_CFG1# */
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
/* EMMY_CFG1# */
IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
/* USBH1_PEN (EHCI) */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* USBH2_PEN (OTG) */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* USBDPC_PEN */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* TOUCH_RST */
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
/* AUDIO_RST# */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* UART1_TEN# */
IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* LVDS_BKLEN # */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* RGMII_PDWN# */
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
/* TOUCH_IRQ# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* TOUCH_RST# */
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* UART_RS485 */
IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
/* UART_HALF */
IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
/* SKT1_WDIS# */
IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
/* SKT1_RST# */
IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
/* SKT2_WDIS# */
IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
/* SKT2_RST# */
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* M2_OFF# */
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
/* M2_WDIS# */
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* M2_RST# */
IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
};
/* Digital I/O */
struct dio_cfg gw51xx_dio[] = {
{
@ -566,6 +705,111 @@ struct dio_cfg gw553x_dio[] = {
},
};
struct dio_cfg gw560x_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
};
struct dio_cfg gw5903_dio[] = {
};
struct dio_cfg gw5904_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
IMX_GPIO_NR(2, 0),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
IMX_GPIO_NR(2, 1),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
IMX_GPIO_NR(2, 2),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
IMX_GPIO_NR(2, 3),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
IMX_GPIO_NR(2, 4),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
IMX_GPIO_NR(2, 5),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
IMX_GPIO_NR(2, 6),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
IMX_GPIO_NR(2, 7),
{ 0, 0 },
0
},
};
/*
* Board Specific GPIO
*/
@ -588,6 +832,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW51xx */
@ -631,6 +876,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW53xx */
@ -654,6 +900,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW54xx */
@ -679,6 +926,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW551x */
@ -726,6 +974,58 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW560x */
{
.gpio_pads = gw560x_gpio_pads,
.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
.dio_cfg = gw560x_dio,
.dio_num = ARRAY_SIZE(gw560x_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(4, 31),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.rs232_en = GP_RS232_EN,
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(4, 15),
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW5903 */
{
.gpio_pads = gw5903_gpio_pads,
.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
.dio_cfg = gw5903_dio,
.dio_num = ARRAY_SIZE(gw5903_dio),
.leds = {
IMX_GPIO_NR(6, 14),
},
.otgpwr_en = IMX_GPIO_NR(4, 15),
.mmc_cd = IMX_GPIO_NR(6, 11),
},
/* GW5904 */
{
.gpio_pads = gw5904_gpio_pads,
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
.dio_cfg = gw5904_dio,
.dio_num = ARRAY_SIZE(gw5904_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
};
@ -834,6 +1134,50 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_direction_input(gpio_cfg[board].vsel_pin);
gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
}
/* microSD CD */
if (gpio_cfg[board].mmc_cd) {
gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
gpio_direction_input(gpio_cfg[board].mmc_cd);
}
/* Anything else board specific */
switch(board) {
case GW560x:
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
break;
case GW5903:
gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
gpio_direction_input(IMX_GPIO_NR(4, 6));
gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
break;
case GW5904:
gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
break;
}
}
/* setup GPIO pinmux and default configuration per baseboard and env */
@ -926,6 +1270,8 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
void setup_pmic(void)
{
struct pmic *p;
struct ventana_board_info ventana_info;
int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
u32 reg;
i2c_set_bus_num(CONFIG_I2C_PMIC);
@ -958,23 +1304,40 @@ void setup_pmic(void)
debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
power_ltc3676_init(CONFIG_I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
/*
* set board-specific scalar for max CPU frequency
* per CPU based on the LDO enabled Operating Ranges
* defined in the respective IMX6DQ and IMX6SDL
* datasheets. The voltage resulting from the R1/R2
* feedback inputs on Ventana is 1308mV. Note that this
* is a bit shy of the Vmin of 1350mV in the datasheet
* for LDO enabled mode but is as high as we can go.
*
* We will rely on an OS kernel driver to properly
* regulate these per CPU operating point and use LDO
* bypass mode when using the higher frequency
* operating points to compensate as LDO bypass mode
* allows the rails be 125mV lower.
*/
if (!p || pmic_probe(p))
return;
puts("PMIC: LTC3676\n");
/*
* set board-specific scalar for max CPU frequency
* per CPU based on the LDO enabled Operating Ranges
* defined in the respective IMX6DQ and IMX6SDL
* datasheets. The voltage resulting from the R1/R2
* feedback inputs on Ventana is 1308mV. Note that this
* is a bit shy of the Vmin of 1350mV in the datasheet
* for LDO enabled mode but is as high as we can go.
*/
switch (board) {
case GW560x:
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
break;
case GW5903:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
/* mask PGOOD during SW4 transition */
pmic_reg_write(p, LTC3676_DVB4B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW4 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
break;
default:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
0x1f | LTC3676_PGOOD_MASK);
@ -991,23 +1354,96 @@ void setup_pmic(void)
}
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
static struct fsl_esdhc_cfg usdhc_cfg[2];
int board_mmc_init(bd_t *bis)
{
/* Only one USDHC controller on Ventana */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
struct ventana_board_info ventana_info;
int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
int ret;
return fsl_esdhc_initialize(bis, &usdhc_cfg);
switch (board_type) {
case GW52xx:
case GW53xx:
case GW54xx:
case GW553x:
/* usdhc3: 4bit microSD */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
case GW560x:
/* usdhc2: 8-bit eMMC */
SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].max_bus_width = 8;
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
if (ret)
return ret;
/* usdhc3: 4-bit microSD */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
case GW5903:
/* usdhc3: 8-bit eMMC */
SETUP_IOMUX_PADS(gw5904_emmc_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 8;
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
if (ret)
return ret;
/* usdhc2: 4-bit microSD */
SETUP_IOMUX_PADS(gw5904_mmc_pads);
usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[1].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
case GW5904:
/* usdhc3: 8bit eMMC */
SETUP_IOMUX_PADS(gw5904_emmc_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 8;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
default:
/* doesn't have MMC */
return -1;
}
}
int board_mmc_getcd(struct mmc *mmc)
{
struct ventana_board_info ventana_info;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
int gpio = gpio_cfg[board].mmc_cd;
/* Card Detect */
gpio_request(GP_SD3_CD, "sd_cd");
gpio_direction_input(GP_SD3_CD);
return !gpio_get_value(GP_SD3_CD);
switch (board) {
case GW560x:
/* emmc is always present */
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
return 1;
break;
case GW5903:
case GW5904:
/* emmc is always present */
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
return 1;
break;
}
if (gpio) {
debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
return !gpio_get_value(gpio);
}
return -1;
}
#endif /* CONFIG_FSL_ESDHC */

2
board/gateworks/gw_ventana/common.h
View File

@ -13,7 +13,6 @@
/* GPIO's common to all baseboards */
#define GP_PHY_RST IMX_GPIO_NR(1, 30)
#define GP_SD3_CD IMX_GPIO_NR(7, 0)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
@ -79,6 +78,7 @@ struct ventana {
int rs232_en;
int otgpwr_en;
int vsel_pin;
int mmc_cd;
/* various features */
bool usd_vsel;
};

15
board/gateworks/gw_ventana/eeprom.c
View File

@ -64,6 +64,7 @@ read_eeprom(int bus, struct ventana_board_info *info)
if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
baseboard = '0';
type = GW_UNKNOWN;
switch (baseboard) {
case '0': /* original GW5400-A prototype */
type = GW54proto;
@ -91,10 +92,16 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW553x;
break;
}
/* fall through */
default:
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
type = GW_UNKNOWN;
break;
case '6':
if (info->model[4] == '0')
type = GW560x;
break;
case '9':
if (info->model[4] == '0' && info->model[5] == '3')
type = GW5903;
if (info->model[4] == '0' && info->model[5] == '4')
type = GW5904;
break;
}
return type;

4
board/gateworks/gw_ventana/gsc.c
View File

@ -137,6 +137,10 @@ int gsc_info(int verbose)
break;
case '5': /* GW55xx */
break;
case '6': /* GW560x */
read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
break;
}
return 0;
}

52
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -132,8 +132,9 @@ static void setup_iomux_enet(int gpio)
/* toggle PHY_RST# */
gpio_request(gpio, "phy_rst#");
gpio_direction_output(gpio, 0);
mdelay(2);
mdelay(10);
gpio_set_value(gpio, 1);
mdelay(100);
}
#ifdef CONFIG_USB_EHCI_MX6
@ -226,12 +227,56 @@ int board_phy_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
}
/* TI DP83867 */
else if (phydev->phy_id == 0x2000a231) {
/* configure register 0x170 for ref CLKOUT */
phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
val &= ~0x1f00;
val |= 0x0b00; /* chD tx clock*/
phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
}
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#ifdef CONFIG_MV88E61XX_SWITCH
int mv88e61xx_hw_reset(struct phy_device *phydev)
{
struct mii_dev *bus = phydev->bus;
/* GPIO[0] output, CLK125 */
debug("enabling RGMII_REFCLK\n");
bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
0x1a /*MV_SCRATCH_MISC*/,
(1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
0x1a /*MV_SCRATCH_MISC*/,
(1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
/* RGMII delay - Physical Control register bit[15:14] */
debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
/* forced 1000mbps full-duplex link */
bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
phydev->autoneg = AUTONEG_DISABLE;
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
/* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
bus->write(bus, 0x10, 0, 0x16, 0x8089);
bus->write(bus, 0x11, 0, 0x16, 0x8089);
bus->write(bus, 0x12, 0, 0x16, 0x8089);
bus->write(bus, 0x13, 0, 0x16, 0x8089);
return 0;
}
#endif // CONFIG_MV88E61XX_SWITCH
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FEC_MXC
@ -661,6 +706,8 @@ int checkboard(void)
static const struct boot_mode board_boot_modes[] = {
/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
{ NULL, 0 },
};
#endif
@ -712,7 +759,8 @@ int misc_init_r(void)
setenv("fdt_file1", fdt);
if (board_type != GW551x &&
board_type != GW552x &&
board_type != GW553x)
board_type != GW553x &&
board_type != GW560x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;

56
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -374,6 +374,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
.p1_mpwrdlctl = 0x383A3930,
};
static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001F003F,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x001F004E,
.p1_mpwldectrl1 = 0x0059001F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42220225,
.p0_mpdgctrl1 = 0x0213021F,
.p1_mpdgctrl0 = 0x022C0242,
.p1_mpdgctrl1 = 0x022C0244,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x474A4C4A,
.p1_mprddlctl = 0x48494C45,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x3F3F3F36,
.p1_mpwrdlctl = 0x3F36363F,
};
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
@ -510,10 +529,25 @@ static void spl_dram_init(int width, int size_mb, int board_model)
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
} else if (width == 64 && size_mb == 4096) {
mem = &mt41k512m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_512x64_mmdc_calib;
debug("8gB density\n");
switch(board_model) {
case GW5903:
/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
mem = &mt41k256m16ha_125;
debug("4gB density\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_256x64x2_mmdc_calib;
sysinfo.ncs = 2;
sysinfo.cs_density = 18; /* CS0_END=71 */
sysinfo.cs1_mirror = 1; /* mirror enabled */
}
break;
default:
mem = &mt41k512m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_512x64_mmdc_calib;
debug("8gB density\n");
break;
}
}
if (!(mem && calib)) {
@ -608,6 +642,20 @@ void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
switch (spl_boot_list[0]) {
case BOOT_DEVICE_NAND:
spl_boot_list[1] = BOOT_DEVICE_MMC1;
spl_boot_list[2] = BOOT_DEVICE_UART;
break;
case BOOT_DEVICE_MMC1:
spl_boot_list[1] = BOOT_DEVICE_UART;
break;
}
}
/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)

3
board/gateworks/gw_ventana/ventana_eeprom.h
View File

@ -112,6 +112,9 @@ enum {
GW551x,
GW552x,
GW553x,
GW560x,
GW5903,
GW5904,
GW_UNKNOWN,
GW_BADCRC,
};

12
board/logicpd/imx6/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_MX6LOGICPD
config SYS_BOARD
default "imx6"
config SYS_VENDOR
default "logicpd"
config SYS_CONFIG_NAME
default "imx6_logic"
endif

6
board/logicpd/imx6/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
MX6LOGICPD BOARD
M: Adam Ford <aford173@gmail.com>
S: Maintained
F: board/logicpd/imx6/
F: include/configs/imx6_logic.h
F: configs/imx6q_logic_defconfig

10
board/logicpd/imx6/Makefile Normal file
View File

@ -0,0 +1,10 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := imx6logic.o

37
board/logicpd/imx6/README Normal file
View File

@ -0,0 +1,37 @@
U-Boot for LogicPD i.MX6 Development Kit
----------------------------------------
This file contains information for the port of U-Boot to the Logic PD Development kit.
Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has
an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
For more details about Logic PD i.MX6 Development kit, visit:
https://www.logicpd.com/
Building U-Boot for Logic PD Development Kit
--------------------------------------------
To build U-Boot for the Dual and Quad variants:
make imx6q_logic_defconfig
make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
Flashing U-Boot into the SD card
--------------------------------
See README.imximage for details on booting from SD
Flashing U-Boot into NAND
-------------------------
Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
with:
kobs-ng init -v -x u-boot-dtb.imx
Additional Support Documentation can be found at:
https://support.logicpd.com/

184
board/logicpd/imx6/imx6logic.c Normal file
View File

@ -0,0 +1,184 @@
/*
* Copyright (C) 2017 Logic PD, Inc.
*
* Author: Adam Ford <aford173@gmail.com>
*
* Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
* and updates by Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <miiphy.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void fixup_enet_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct gpio_desc nint;
struct gpio_desc reset;
int ret;
/* Set Ref Clock to 50 MHz */
enable_fec_anatop_clock(0, ENET_50MHZ);
/* Set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
/* Request GPIO Pins to reset Ethernet with new clock */
ret = dm_gpio_lookup_name("GPIO4_7", &nint);
if (ret) {
printf("Unable to lookup GPIO4_7\n");
return;
}
ret = dm_gpio_request(&nint, "eth0_nInt");
if (ret) {
printf("Unable to request eth0_nInt\n");
return;
}
/* Ensure nINT is input or PHY won't startup */
dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
ret = dm_gpio_lookup_name("GPIO4_9", &reset);
if (ret) {
printf("Unable to lookup GPIO4_9\n");
return;
}
ret = dm_gpio_request(&reset, "eth0_reset");
if (ret) {
printf("Unable to request eth0_reset\n");
return;
}
/* Reset LAN8710A PHY */
dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
dm_gpio_set_value(&reset, 0);
udelay(150);
dm_gpio_set_value(&reset, 1);
mdelay(50);
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
};
static void setup_nand_pins(void)
{
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_early_init_f(void)
{
fixup_enet_clock();
setup_iomux_uart();
setup_nand_pins();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
setenv("board_name", "imx6logic");
if (is_mx6dq()) {
setenv("board_rev", "MX6DQ");
setenv("fdt_file", "imx6q-logicpd.dtb");
}
return 0;
}

112
board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg Normal file
View File

@ -0,0 +1,112 @@
/*
* Copyright (C) 2017 Logic PD, Inc.
* Adam Ford <aford173@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#include <asm/imx-common/imximage.cfg>
/* image version */
IMAGE_VERSION 2
BOOT_OFFSET FLASH_OFFSET_STANDARD
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch-mx6/mx6-ddr.h"
#include "asm/arch-mx6/iomux.h"
#include "asm/arch-mx6/crm_regs.h"
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300
DATA 4, CCM_CCGR5, 0x0F0000F3
DATA 4, CCM_CCGR6, 0x00000FFF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 MX6_IOMUXC_GPR6 0x007F007F
DATA 4 MX6_IOMUXC_GPR7 0x007F007F

2
cmd/mmc.c
View File

@ -710,7 +710,7 @@ static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag,
if (argc != 2)
return CMD_RET_USAGE;
val = simple_strtoul(argv[2], NULL, 16);
val = simple_strtoul(argv[1], NULL, 16);
mmc = find_mmc_device(curr_device);
if (!mmc) {

1
configs/gwventana_emmc_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

68
configs/gwventana_gw5904_defconfig Normal file
View File

@ -0,0 +1,68 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_PHYLIB=y
CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_MV88E61XX_PHY_PORTS=0xf
CONFIG_MV88E61XX_FIXED_PORTS=0x0
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Gateworks"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

1
configs/gwventana_nand_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/imx6dl_icore_rqs_mmc_defconfig
View File

@ -38,4 +38,3 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_BOARD_LATE_INIT=y

1
configs/imx6q_icore_rqs_mmc_defconfig
View File

@ -38,4 +38,3 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_BOARD_LATE_INIT=y

38
configs/imx6q_logic_defconfig Normal file
View File

@ -0,0 +1,38 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6LOGICPD=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="i.MX6 Logic # "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_MXS=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR_PFUZE100=y

1
configs/imx6ul_isiot_emmc_defconfig
View File

@ -37,4 +37,3 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

1
configs/imx6ul_isiot_mmc_defconfig
View File

@ -39,4 +39,3 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

1
configs/imx6ul_isiot_nand_defconfig
View File

@ -40,4 +40,3 @@ CONFIG_PINCTRL_IMX6=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

2
configs/m53evk_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aries/m53evk/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

16
configs/mx6slevk_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
@ -23,10 +24,23 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

19
configs/mx6slevk_spinor_defconfig
View File

@ -1,7 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
@ -23,10 +25,23 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

2
configs/mx6slevk_spl_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL,SYS_I2C"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y

2
doc/README.mxs
View File

@ -95,7 +95,7 @@ Next, configure U-Boot for a MXS based board
Examples:
1. For building U-Boot for Denx M28EVK board:
1. For building U-Boot for Aries M28EVK board:
$ make m28evk_config

13
drivers/net/phy/Kconfig
View File

@ -15,6 +15,19 @@ if PHYLIB
config MV88E61XX_SWITCH
bool "Marvel MV88E61xx Ethernet switch PHY support."
if MV88E61XX_SWITCH
config MV88E61XX_CPU_PORT
int "CPU Port"
config MV88E61XX_PHY_PORTS
hex "Bitmask of PHY Ports"
config MV88E61XX_FIXED_PORTS
hex "Bitmask of PHYless serdes Ports"
endif # MV88E61XX_SWITCH
config PHYLIB_10G
bool "Generic 10G PHY support"

2
drivers/video/mxsfb.c
View File

@ -36,7 +36,7 @@ __weak void mxsfb_system_setup(void)
}
/*
* DENX M28EVK:
* ARIES M28EVK:
* setenv videomode
* video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
* le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0

2
include/configs/advantech_dms-ba16.h
View File

@ -261,6 +261,7 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
@ -271,6 +272,7 @@
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000

7
include/configs/gw_ventana.h
View File

@ -100,7 +100,10 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* eMMC Configs */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
/* Filesystem support */
#define CONFIG_CMD_UBIFS
@ -152,7 +155,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_ARP_TIMEOUT 200UL
/* USB Configs */
@ -235,6 +237,7 @@
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
#define CONFIG_ENV_OFFSET (709 * SZ_1K)
#define CONFIG_ENV_SIZE (128 * SZ_1K)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K))

176
include/configs/imx6_logic.h Normal file
View File

@ -0,0 +1,176 @@
/*
* Copyright (C) 2017 Logic PD, Inc.
*
* Configuration settings for the LogicPD i.MX6 SOM.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX6LOGIC_CONFIG_H
#define __IMX6LOGIC_CONFIG_H
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
#include <config_distro_defaults.h>
#include "mx6_common.h"
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_MXC_UART
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
/* Ethernet Configs */
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/* Command definition */
#define CONFIG_CMD_BMODE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x18000000\0" \
"fdt_addr=0x18000000\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"console=" CONSOLE_DEV "\0" \
"mmcdev=1\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console},${baudrate}" \
" root=${mmcroot} ${mtdparts}\0" \
"nandargs=setenv bootargs console=${console},${baudrate}" \
" ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
"ramargs=setenv bootargs console=${console},${baudrate}" \
" root=/dev/ram rw ${mtdparts}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...;" \
" source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
" setenv kernelsize ${filesize}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr}" \
" ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
"mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \
" run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \
"mmcramboot=run ramargs; run loadimage;" \
" run loadfdt; run loadramdisk;" \
" bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
"nandboot=echo Booting from nand ...; " \
" run nandargs;" \
" nand read ${loadaddr} kernel ${kernelsize};" \
" nand read ${fdt_addr} dtb;" \
" bootz ${loadaddr} - ${fdt_addr}\0" \
"nandramboot=echo Booting RAMdisk from nand ...; " \
" nand read ${ramdiskaddr} fs ${ramdisksize};" \
" nand read ${loadaddr} kernel ${kernelsize};" \
" nand read ${fdt_addr} dtb;" \
" run ramargs;" \
" bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs" \
" ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"autoboot=mmc dev ${mmcdev};" \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_BOOTCOMMAND \
"run autoboot"
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x400000
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
/* NAND stuff */
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
/* MTD device */
# define CONFIG_MTD_DEVICE
# define CONFIG_CMD_MTDPARTS
# define CONFIG_MTD_PARTITIONS
# define MTDIDS_DEFAULT "nand0=gpmi-nand"
# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \
"1m(env),16m(kernel),1m(dtb),-(fs)"
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* EEPROM contains serial no, MAC addr and other Logic PD info */
#define CONFIG_I2C_EEPROM
#endif /* __IMX6LOGIC_CONFIG_H */

2
include/configs/m53evk.h
View File

@ -1,5 +1,5 @@
/*
* DENX M53 configuration
* Aries M53 configuration
* Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+

8
include/configs/mccmon6.h
View File

@ -265,6 +265,14 @@
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
"tftp_nor_dtb="\
"echo 'Update mccmon6 NOR DTB via TFTP'; " \
"setenv nor_img_file imx6q-mccmon6.dtb; " \
"setenv nor_img_size 0x20000; " \
"setenv nor_bank_start 0x09980000; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
"run nor_update;" \
"fi\0" \
"tftp_nor_img="\
"echo 'Update mccmon6 NOR image via TFTP'; " \
"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \

2
include/configs/mx6cuboxi.h
View File

@ -84,7 +84,7 @@
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"ip_dyn=yes\0" \
"console=" CONSOLE_DEV "\0" \
"console=" CONSOLE_DEV ",115200\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"update_sd_firmware=" \

9
include/configs/mx6slevk.h
View File

@ -27,19 +27,12 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
@ -143,7 +136,7 @@
/* Environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#if defined CONFIG_SYS_BOOT_SPINOR
#if defined CONFIG_SPI_BOOT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (64 * 1024)

180
include/dt-bindings/clock/imx6sl-clock.h Normal file
View File

@ -0,0 +1,180 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
#define __DT_BINDINGS_CLOCK_IMX6SL_H
#define IMX6SL_CLK_DUMMY 0
#define IMX6SL_CLK_CKIL 1
#define IMX6SL_CLK_OSC 2
#define IMX6SL_CLK_PLL1_SYS 3
#define IMX6SL_CLK_PLL2_BUS 4
#define IMX6SL_CLK_PLL3_USB_OTG 5
#define IMX6SL_CLK_PLL4_AUDIO 6
#define IMX6SL_CLK_PLL5_VIDEO 7
#define IMX6SL_CLK_PLL6_ENET 8
#define IMX6SL_CLK_PLL7_USB_HOST 9
#define IMX6SL_CLK_USBPHY1 10
#define IMX6SL_CLK_USBPHY2 11
#define IMX6SL_CLK_USBPHY1_GATE 12
#define IMX6SL_CLK_USBPHY2_GATE 13
#define IMX6SL_CLK_PLL4_POST_DIV 14
#define IMX6SL_CLK_PLL5_POST_DIV 15
#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
#define IMX6SL_CLK_ENET_REF 17
#define IMX6SL_CLK_PLL2_PFD0 18
#define IMX6SL_CLK_PLL2_PFD1 19
#define IMX6SL_CLK_PLL2_PFD2 20
#define IMX6SL_CLK_PLL3_PFD0 21
#define IMX6SL_CLK_PLL3_PFD1 22
#define IMX6SL_CLK_PLL3_PFD2 23
#define IMX6SL_CLK_PLL3_PFD3 24
#define IMX6SL_CLK_PLL2_198M 25
#define IMX6SL_CLK_PLL3_120M 26
#define IMX6SL_CLK_PLL3_80M 27
#define IMX6SL_CLK_PLL3_60M 28
#define IMX6SL_CLK_STEP 29
#define IMX6SL_CLK_PLL1_SW 30
#define IMX6SL_CLK_OCRAM_ALT_SEL 31
#define IMX6SL_CLK_OCRAM_SEL 32
#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
#define IMX6SL_CLK_PRE_PERIPH_SEL 34
#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
#define IMX6SL_CLK_CSI_SEL 37
#define IMX6SL_CLK_LCDIF_AXI_SEL 38
#define IMX6SL_CLK_USDHC1_SEL 39
#define IMX6SL_CLK_USDHC2_SEL 40
#define IMX6SL_CLK_USDHC3_SEL 41
#define IMX6SL_CLK_USDHC4_SEL 42
#define IMX6SL_CLK_SSI1_SEL 43
#define IMX6SL_CLK_SSI2_SEL 44
#define IMX6SL_CLK_SSI3_SEL 45
#define IMX6SL_CLK_PERCLK_SEL 46
#define IMX6SL_CLK_PXP_AXI_SEL 47
#define IMX6SL_CLK_EPDC_AXI_SEL 48
#define IMX6SL_CLK_GPU2D_OVG_SEL 49
#define IMX6SL_CLK_GPU2D_SEL 50
#define IMX6SL_CLK_LCDIF_PIX_SEL 51
#define IMX6SL_CLK_EPDC_PIX_SEL 52
#define IMX6SL_CLK_SPDIF0_SEL 53
#define IMX6SL_CLK_SPDIF1_SEL 54
#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
#define IMX6SL_CLK_ECSPI_SEL 56
#define IMX6SL_CLK_UART_SEL 57
#define IMX6SL_CLK_PERIPH 58
#define IMX6SL_CLK_PERIPH2 59
#define IMX6SL_CLK_OCRAM_PODF 60
#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
#define IMX6SL_CLK_IPG 63
#define IMX6SL_CLK_CSI_PODF 64
#define IMX6SL_CLK_LCDIF_AXI_PODF 65
#define IMX6SL_CLK_USDHC1_PODF 66
#define IMX6SL_CLK_USDHC2_PODF 67
#define IMX6SL_CLK_USDHC3_PODF 68
#define IMX6SL_CLK_USDHC4_PODF 69
#define IMX6SL_CLK_SSI1_PRED 70
#define IMX6SL_CLK_SSI1_PODF 71
#define IMX6SL_CLK_SSI2_PRED 72
#define IMX6SL_CLK_SSI2_PODF 73
#define IMX6SL_CLK_SSI3_PRED 74
#define IMX6SL_CLK_SSI3_PODF 75
#define IMX6SL_CLK_PERCLK 76
#define IMX6SL_CLK_PXP_AXI_PODF 77
#define IMX6SL_CLK_EPDC_AXI_PODF 78
#define IMX6SL_CLK_GPU2D_OVG_PODF 79
#define IMX6SL_CLK_GPU2D_PODF 80
#define IMX6SL_CLK_LCDIF_PIX_PRED 81
#define IMX6SL_CLK_EPDC_PIX_PRED 82
#define IMX6SL_CLK_LCDIF_PIX_PODF 83
#define IMX6SL_CLK_EPDC_PIX_PODF 84
#define IMX6SL_CLK_SPDIF0_PRED 85
#define IMX6SL_CLK_SPDIF0_PODF 86
#define IMX6SL_CLK_SPDIF1_PRED 87
#define IMX6SL_CLK_SPDIF1_PODF 88
#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
#define IMX6SL_CLK_ECSPI_ROOT 91
#define IMX6SL_CLK_UART_ROOT 92
#define IMX6SL_CLK_AHB 93
#define IMX6SL_CLK_MMDC_ROOT 94
#define IMX6SL_CLK_ARM 95
#define IMX6SL_CLK_ECSPI1 96
#define IMX6SL_CLK_ECSPI2 97
#define IMX6SL_CLK_ECSPI3 98
#define IMX6SL_CLK_ECSPI4 99
#define IMX6SL_CLK_EPIT1 100
#define IMX6SL_CLK_EPIT2 101
#define IMX6SL_CLK_EXTERN_AUDIO 102
#define IMX6SL_CLK_GPT 103
#define IMX6SL_CLK_GPT_SERIAL 104
#define IMX6SL_CLK_GPU2D_OVG 105
#define IMX6SL_CLK_I2C1 106
#define IMX6SL_CLK_I2C2 107
#define IMX6SL_CLK_I2C3 108
#define IMX6SL_CLK_OCOTP 109
#define IMX6SL_CLK_CSI 110
#define IMX6SL_CLK_PXP_AXI 111
#define IMX6SL_CLK_EPDC_AXI 112
#define IMX6SL_CLK_LCDIF_AXI 113
#define IMX6SL_CLK_LCDIF_PIX 114
#define IMX6SL_CLK_EPDC_PIX 115
#define IMX6SL_CLK_OCRAM 116
#define IMX6SL_CLK_PWM1 117
#define IMX6SL_CLK_PWM2 118
#define IMX6SL_CLK_PWM3 119
#define IMX6SL_CLK_PWM4 120
#define IMX6SL_CLK_SDMA 121
#define IMX6SL_CLK_SPDIF 122
#define IMX6SL_CLK_SSI1 123
#define IMX6SL_CLK_SSI2 124
#define IMX6SL_CLK_SSI3 125
#define IMX6SL_CLK_UART 126
#define IMX6SL_CLK_UART_SERIAL 127
#define IMX6SL_CLK_USBOH3 128
#define IMX6SL_CLK_USDHC1 129
#define IMX6SL_CLK_USDHC2 130
#define IMX6SL_CLK_USDHC3 131
#define IMX6SL_CLK_USDHC4 132
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_ENET 135
#define IMX6SL_CLK_LVDS1_SEL 136
#define IMX6SL_CLK_LVDS1_OUT 137
#define IMX6SL_CLK_LVDS1_IN 138
#define IMX6SL_CLK_ANACLK1 139
#define IMX6SL_PLL1_BYPASS_SRC 140
#define IMX6SL_PLL2_BYPASS_SRC 141
#define IMX6SL_PLL3_BYPASS_SRC 142
#define IMX6SL_PLL4_BYPASS_SRC 143
#define IMX6SL_PLL5_BYPASS_SRC 144
#define IMX6SL_PLL6_BYPASS_SRC 145
#define IMX6SL_PLL7_BYPASS_SRC 146
#define IMX6SL_CLK_PLL1 147
#define IMX6SL_CLK_PLL2 148
#define IMX6SL_CLK_PLL3 149
#define IMX6SL_CLK_PLL4 150
#define IMX6SL_CLK_PLL5 151
#define IMX6SL_CLK_PLL6 152
#define IMX6SL_CLK_PLL7 153
#define IMX6SL_PLL1_BYPASS 154
#define IMX6SL_PLL2_BYPASS 155
#define IMX6SL_PLL3_BYPASS 156
#define IMX6SL_PLL4_BYPASS 157
#define IMX6SL_PLL5_BYPASS 158
#define IMX6SL_PLL6_BYPASS 159
#define IMX6SL_PLL7_BYPASS 160
#define IMX6SL_CLK_SSI1_IPG 161
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_SPDIF_GCLK 164
#define IMX6SL_CLK_END 165
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

2
scripts/config_whitelist.txt
View File

@ -125,6 +125,7 @@ CONFIG_ARC_SERIAL
CONFIG_ARC_UART_BASE
CONFIG_ARIA
CONFIG_ARIA_FPGA
CONFIG_ARIES_M28_V10
CONFIG_ARM926EJS
CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
@ -661,7 +662,6 @@ CONFIG_DEFAULT_SPI_CS
CONFIG_DEFAULT_SPI_MODE
CONFIG_DEF_HWCONFIG
CONFIG_DELAY_ENVIRONMENT
CONFIG_DENX_M28_V10
CONFIG_DESIGNWARE_ETH
CONFIG_DESIGNWARE_WATCHDOG
CONFIG_DEVCONCENTER