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davinci: omapl138_lcdk: increase PLL0 frequency

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The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.

Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Bartosz Golaszewski 2016-12-01 12:07:43 +01:00 committed by Tom Rini
parent 88679a2912
commit 1601dd97ed
1 changed files with 1 additions and 1 deletions
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2
include/configs/omapl138_lcdk.h
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@ -75,7 +75,7 @@
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL0_PLLM 37
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*