ARM: vexpress_ca9x4: Reintroduce board in order to use with QEMU.
vexpress_ca9x4 is seemingly the only board except for qemu_arm which
is able to run U-Boot correctly, using the `-M vexpress-a9` option to
QEMU. Building for qemu_arm and running qemu-system-arm with the `-M
virt` argument has a number of downsides, most importantly that it
only supports virtio storage drivers. This significantly reduces its
usefulness in testing memory card and Flash solutions, especially when
the tested images are from a third party source.
So therefore we reintroduce the vexpress_ca9x4 board in this commit,
with the explicit goal of using it with QEMU.
A number of differences to note from the original:
* Since the board was apparently unmaintained, I have now set myself
as the maintainer.
* The board has been converted to use the driver model, which was the
reason it was removed in the first place.
* The vexpress_ca15_tc2 and vexpress_ca5x2 boards, which were removed
in the same commit, are not necessary for the QEMU use case, and
have been omitted.
* An `mmc0` alias was introduced in the dts file. The mmc is not
detected correctly without this, now that it's based on the device
tree instead of the board's init function.
* A couple of other nodes were removed because they were problematic
when trying to run the UEFI bootmgr. Once again, the primary use
case here is QEMU, and these nodes are not needed for that to work.
* Unnecessary board init code has been removed, thanks to driver model
and device tree.
* `CONFIG_OF_EMBED` has been enabled. I know this goes against
recommended practice, but there doesn't seem to be any other way to
pass the dtb to U-Boot in the QEMU scenario. Using the -dtb argument
does not work, I suppose because U-Boot doesn't use the same
mechanics as the kernel when it's booting.
* Load addresses have been changed to fit QEMU use case.
People wanting to get a more detailed, yet somewhat isolated, diff
between this and the original, can run this command:
git diff c6c26a05b89f25a06e7562f8c2071b60fd0c9eac~1 -- \
$( git diff-tree --diff-filter=A -r --name-only HEAD~1 HEAD)
(Make sure to either check out this commit first, or replace HEAD with
the commit ID of this commit)
Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
This commit is contained in:
Kristian Amlie
Tom Rini
parent
6493fa4c3d
commit
15e30106ce
@ -195,6 +195,9 @@ jobs:
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evb_ast2500:
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TEST_PY_BD: "evb-ast2500"
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TEST_PY_ID: "--id qemu"
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vexpress_ca9x4:
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TEST_PY_BD: "vexpress_ca9x4"
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TEST_PY_ID: "--id qemu"
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integratorcp_cm926ejs:
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TEST_PY_BD: "integratorcp_cm926ejs"
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TEST_PY_ID: "--id qemu"
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@ -216,6 +216,12 @@ sandbox_flattree test.py:
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TEST_PY_BD: "sandbox_flattree"
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<<: *buildman_and_testpy_dfn
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vexpress_ca9x4 test.py:
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variables:
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TEST_PY_BD: "vexpress_ca9x4"
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TEST_PY_ID: "--id qemu"
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<<: *buildman_and_testpy_dfn
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integratorcp_cm926ejs test.py:
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variables:
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TEST_PY_BD: "integratorcp_cm926ejs"
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@ -652,6 +652,11 @@ config ARCH_BCMSTB
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This enables support for Broadcom ARM-based set-top box
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chipsets, including the 7445 family of chips.
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config TARGET_VEXPRESS_CA9X4
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bool "Support vexpress_ca9x4"
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select CPU_V7A
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select PL011_SERIAL
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config TARGET_BCMCYGNUS
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bool "Support bcmcygnus"
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select CPU_V7A
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@ -2148,6 +2153,7 @@ source "board/CarMediaLab/flea3/Kconfig"
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source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/octeontx/Kconfig"
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source "board/Marvell/octeontx2/Kconfig"
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source "board/armltd/vexpress/Kconfig"
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source "board/armltd/vexpress64/Kconfig"
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source "board/cortina/presidio-asic/Kconfig"
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source "board/broadcom/bcm963158/Kconfig"
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@ -1120,6 +1120,8 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
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dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
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dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
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dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
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dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
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427
arch/arm/dts/vexpress-v2m.dtsi
Normal file
427
arch/arm/dts/vexpress-v2m.dtsi
Normal file
@ -0,0 +1,427 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
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* V2M-P1
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*
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* HBI-0190D
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*
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* Original memory map ("Legacy memory map" in the board's
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* Technical Reference Manual)
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*
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* WARNING! The hardware described in this file is independent from the
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* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
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* correspondence between the two configurations.
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*
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* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
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* CHANGES TO vexpress-v2m-rs1.dtsi!
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*/
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/ {
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smb@4000000 {
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motherboard {
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model = "V2M-P1";
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arm,hbi = <0x190>;
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arm,vexpress,site = <0>;
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<1 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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psram@2,00000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <2 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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ethernet@3,02000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <3 0x02000000 0x10000>;
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interrupts = <15>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&v2m_fixed_3v3>;
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vddvario-supply = <&v2m_fixed_3v3>;
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};
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usb@3,03000000 {
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compatible = "nxp,usb-isp1761";
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reg = <3 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@7,00000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 7 0 0x20000>;
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v2m_sysreg: sysreg@0 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x1000>;
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v2m_led_gpios: gpio@8 {
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compatible = "arm,vexpress-sysreg,sys_led";
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reg = <0x008 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_mmc_gpios: gpio@48 {
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compatible = "arm,vexpress-sysreg,sys_mci";
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reg = <0x048 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_flash_gpios: gpio@4c {
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compatible = "arm,vexpress-sysreg,sys_flash";
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reg = <0x04c 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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v2m_sysctl: sysctl@1000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x01000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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/* PCI-E I2C bus */
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v2m_i2c_pcie: i2c@2000 {
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compatible = "arm,versatile-i2c";
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reg = <0x02000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie-switch@60 {
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compatible = "idt,89hpes32h8";
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reg = <0x60>;
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};
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};
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aaci@4000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x04000 0x1000>;
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interrupts = <11>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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mmc0: mmci@5000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x05000 0x1000>;
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interrupts = <9>, <10>;
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cd-gpios = <&v2m_mmc_gpios 0 0>;
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wp-gpios = <&v2m_mmc_gpios 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "mclk", "apb_pclk";
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};
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v2m_serial0: uart@9000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x09000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_timer01: timer@11000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x11000 0x1000>;
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interrupts = <2>;
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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v2m_timer23: timer@12000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <3>;
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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/* DVI I2C bus */
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v2m_i2c_dvi: i2c@16000 {
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compatible = "arm,versatile-i2c";
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reg = <0x16000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dvi-transmitter@39 {
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compatible = "sil,sii9022-tpi", "sil,sii9022";
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reg = <0x39>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Both the core tile and the motherboard routes their output
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* pads to this transmitter. The motherboard system controller
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* can select one of them as input using a mux register in
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* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
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* the only platform with this specific set-up.
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*/
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port@0 {
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reg = <0>;
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dvi_bridge_in_ct: endpoint {
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remote-endpoint = <&clcd_pads_ct>;
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};
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};
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port@1 {
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reg = <1>;
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dvi_bridge_in_mb: endpoint {
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remote-endpoint = <&clcd_pads_mb>;
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};
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};
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};
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};
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dvi-transmitter@60 {
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compatible = "sil,sii9022-cpi", "sil,sii9022";
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reg = <0x60>;
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};
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};
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rtc@17000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x17000 0x1000>;
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interrupts = <4>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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compact-flash@1a000 {
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compatible = "arm,vexpress-cf", "ata-generic";
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reg = <0x1a000 0x100
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0x1a100 0xf00>;
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reg-shift = <2>;
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};
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clcd@1f000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f000 0x1000>;
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interrupt-names = "combined";
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interrupts = <14>;
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clocks = <&v2m_oscclk1>, <&smbclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 800x600 16bpp @36MHz works fine */
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max-memory-bandwidth = <54000000>;
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memory-region = <&vram>;
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port {
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clcd_pads_mb: endpoint {
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remote-endpoint = <&dvi_bridge_in_mb>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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};
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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leds {
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compatible = "gpio-leds";
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user1 {
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label = "v2m:green:user1";
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gpios = <&v2m_led_gpios 0 0>;
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linux,default-trigger = "heartbeat";
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};
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user2 {
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label = "v2m:green:user2";
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gpios = <&v2m_led_gpios 1 0>;
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linux,default-trigger = "mmc0";
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};
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user3 {
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label = "v2m:green:user3";
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gpios = <&v2m_led_gpios 2 0>;
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linux,default-trigger = "cpu0";
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};
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user4 {
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label = "v2m:green:user4";
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gpios = <&v2m_led_gpios 3 0>;
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linux,default-trigger = "cpu1";
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};
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user5 {
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label = "v2m:green:user5";
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gpios = <&v2m_led_gpios 4 0>;
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linux,default-trigger = "cpu2";
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};
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user6 {
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label = "v2m:green:user6";
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gpios = <&v2m_led_gpios 5 0>;
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linux,default-trigger = "cpu3";
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};
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user7 {
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label = "v2m:green:user7";
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gpios = <&v2m_led_gpios 6 0>;
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linux,default-trigger = "cpu4";
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};
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user8 {
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label = "v2m:green:user8";
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gpios = <&v2m_led_gpios 7 0>;
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linux,default-trigger = "cpu5";
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||||
};
|
||||
};
|
||||
|
||||
mcc {
|
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compatible = "arm,vexpress,config-bus";
|
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arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
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/* MCC static memory clock */
|
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compatible = "arm,vexpress-osc";
|
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <25000000 60000000>;
|
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#clock-cells = <0>;
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||||
clock-output-names = "v2m:oscclk0";
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||||
};
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|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 65000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: oscclk2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt-vio {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp-mcc {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
369
arch/arm/dts/vexpress-v2p-ca9.dts
Normal file
369
arch/arm/dts/vexpress-v2p-ca9.dts
Normal file
@ -0,0 +1,369 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A9x4
|
||||
* Cortex-A9 MPCore (V2P-CA9)
|
||||
*
|
||||
* HBI-0191B
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA9";
|
||||
arm,hbi = <0x191>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
mmc0 = &mmc0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A9_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 3 is physically at 0x4c000000 */
|
||||
vram: vram@4c000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x4c000000 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&oscclk1>, <&oscclk2>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 1024x768 16bpp @65MHz */
|
||||
max-memory-bandwidth = <95000000>;
|
||||
|
||||
port {
|
||||
clcd_pads_ct: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in_ct>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@100e0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x100e0000 0x1000>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@100e1000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0x100e1000 0x1000>;
|
||||
interrupts = <0 45 4>,
|
||||
<0 46 4>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer@100e4000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x100e4000 0x1000>;
|
||||
interrupts = <0 48 4>,
|
||||
<0 49 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "timclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@100e5000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x100e5000 0x1000>;
|
||||
interrupts = <0 51 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
scu@1e000000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1e000000 0x58>;
|
||||
};
|
||||
|
||||
timer@1e000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1e000600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
watchdog@1e000620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x1e000620 0x20>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1e001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1e001000 0x1000>,
|
||||
<0x1e000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@1e00a000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x1e00a000 0x1000>;
|
||||
interrupts = <0 43 4>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
|
||||
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0: extsaxiclk {
|
||||
/* ACLK clock to the AXI master port on the test chip */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <30000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extsaxiclk";
|
||||
};
|
||||
|
||||
oscclk1: clcdclk {
|
||||
/* Reference clock for the CLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <10000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clcdclk";
|
||||
};
|
||||
|
||||
smbclk: oscclk2: tcrefclk {
|
||||
/* Reference clock for the test chip internal PLLs */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <33000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "tcrefclk";
|
||||
};
|
||||
|
||||
volt-vd10 {
|
||||
/* Test Chip internal logic voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VD10";
|
||||
regulator-always-on;
|
||||
label = "VD10";
|
||||
};
|
||||
|
||||
volt-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "VD10_S2";
|
||||
regulator-always-on;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
volt-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 2>;
|
||||
regulator-name = "VD10_S3";
|
||||
regulator-always-on;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
volt-vcc1v8 {
|
||||
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 3>;
|
||||
regulator-name = "VCC1V8";
|
||||
regulator-always-on;
|
||||
label = "VCC1V8";
|
||||
};
|
||||
|
||||
volt-ddr2vtt {
|
||||
/* DDR2 SDRAM VTT termination voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 4>;
|
||||
regulator-name = "DDR2VTT";
|
||||
regulator-always-on;
|
||||
label = "DDR2VTT";
|
||||
};
|
||||
|
||||
volt-vcc3v3 {
|
||||
/* Local board supply for miscellaneous logic external to the Test Chip */
|
||||
arm,vexpress-sysreg,func = <2 5>;
|
||||
compatible = "arm,vexpress-volt";
|
||||
regulator-name = "VCC3V3";
|
||||
regulator-always-on;
|
||||
label = "VCC3V3";
|
||||
};
|
||||
|
||||
amp-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
amp-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
power-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "PVD10_S2";
|
||||
};
|
||||
|
||||
power-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "PVD10_S3";
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@4000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@e0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xe0000000 0x20000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
12
board/armltd/vexpress/Kconfig
Normal file
12
board/armltd/vexpress/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_VEXPRESS_CA9X4
|
||||
|
||||
config SYS_BOARD
|
||||
default "vexpress"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "armltd"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "vexpress_ca9x4"
|
||||
|
||||
endif
|
||||
6
board/armltd/vexpress/MAINTAINERS
Normal file
6
board/armltd/vexpress/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
VERSATILE EXPRESS BOARDS
|
||||
M: Kristian Amlie <kristian.amlie@northern.tech>
|
||||
S: Maintained
|
||||
F: board/armltd/vexpress/
|
||||
F: include/configs/vexpress_ca9x4.h
|
||||
F: configs/vexpress_ca9x4_defconfig
|
||||
6
board/armltd/vexpress/Makefile
Normal file
6
board/armltd/vexpress/Makefile
Normal file
@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
obj-y := vexpress_common.o
|
||||
167
board/armltd/vexpress/vexpress_common.c
Normal file
167
board/armltd/vexpress/vexpress_common.c
Normal file
@ -0,0 +1,167 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* (C) Copyright 2003
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Kshitij Gupta <Kshitij@ti.com>
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* ARM Ltd.
|
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <bootstage.h>
|
||||
#include <cpu_func.h>
|
||||
#include <init.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/systimer.h>
|
||||
#include <asm/arch/sysctrl.h>
|
||||
#include <asm/arch/wdt.h>
|
||||
|
||||
static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
|
||||
static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
|
||||
|
||||
static void flash__init(void);
|
||||
static void vexpress_timer_init(void);
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
|
||||
void show_boot_progress(int progress)
|
||||
{
|
||||
printf("Boot reached stage %d\n", progress);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void delay(ulong loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b" : "=r" (loops) : "0" (loops));
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
||||
gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
|
||||
|
||||
icache_enable();
|
||||
flash__init();
|
||||
vexpress_timer_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void flash__init(void)
|
||||
{
|
||||
/* Setup the sytem control register to allow writing to flash */
|
||||
writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
|
||||
&sysctrl_base->scflashctrl);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size =
|
||||
get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size =
|
||||
get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size =
|
||||
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Start timer:
|
||||
* Setup a 32 bit timer, running at 1KHz
|
||||
* Versatile Express Motherboard provides 1 MHz timer
|
||||
*/
|
||||
static void vexpress_timer_init(void)
|
||||
{
|
||||
/*
|
||||
* Set clock frequency in system controller:
|
||||
* VEXPRESS_REFCLK is 32KHz
|
||||
* VEXPRESS_TIMCLK is 1MHz
|
||||
*/
|
||||
writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
|
||||
SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
|
||||
readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
|
||||
|
||||
/*
|
||||
* Set Timer0 to be:
|
||||
* Enabled, free running, no interrupt, 32-bit, wrapping
|
||||
*/
|
||||
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
|
||||
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
|
||||
writel(SYSTIMER_EN | SYSTIMER_32BIT |
|
||||
readl(&systimer_base->timer0control),
|
||||
&systimer_base->timer0control);
|
||||
}
|
||||
|
||||
int v2m_cfg_write(u32 devfn, u32 data)
|
||||
{
|
||||
/* Configuration interface broken? */
|
||||
u32 val;
|
||||
|
||||
devfn |= SYS_CFG_START | SYS_CFG_WRITE;
|
||||
|
||||
val = readl(V2M_SYS_CFGSTAT);
|
||||
writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
|
||||
|
||||
writel(data, V2M_SYS_CFGDATA);
|
||||
writel(devfn, V2M_SYS_CFGCTRL);
|
||||
|
||||
do {
|
||||
val = readl(V2M_SYS_CFGSTAT);
|
||||
} while (val == 0);
|
||||
|
||||
return !!(val & SYS_CFG_ERR);
|
||||
}
|
||||
|
||||
/* Use the ARM Watchdog System to cause reset */
|
||||
void reset_cpu(void)
|
||||
{
|
||||
if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
|
||||
printf("Unable to reboot\n");
|
||||
}
|
||||
|
||||
void lowlevel_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
ulong get_board_rev(void){
|
||||
return readl((u32 *)SYS_ID);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARMV7_NONSEC
|
||||
/* Setting the address at which secondary cores start from.
|
||||
* Versatile Express uses one address for all cores, so ignore corenr
|
||||
*/
|
||||
void smp_set_core_boot_addr(unsigned long addr, int corenr)
|
||||
{
|
||||
/* The SYSFLAGS register on VExpress needs to be cleared first
|
||||
* by writing to the next address, since any writes to the address
|
||||
* at offset 0 will only be ORed in
|
||||
*/
|
||||
writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
|
||||
writel(addr, CONFIG_SYSFLAGS_ADDR);
|
||||
}
|
||||
#endif
|
||||
49
configs/vexpress_ca9x4_defconfig
Normal file
49
configs/vexpress_ca9x4_defconfig
Normal file
@ -0,0 +1,49 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_VEXPRESS_CA9X4=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60800000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x40000
|
||||
CONFIG_ENV_SECT_SIZE=0x40000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run distro_bootcmd; run bootflash"
|
||||
CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0x47F80000
|
||||
CONFIG_ARM_PL180_MMCI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMC911X_BASE=0x4e000000
|
||||
CONFIG_SMC911X_32_BIT=y
|
||||
CONFIG_BAUDRATE=38400
|
||||
CONFIG_CONS_INDEX=0
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="vexpress-v2p-ca9"
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_CLK=y
|
||||
16
include/configs/vexpress_ca9x4.h
Normal file
16
include/configs/vexpress_ca9x4.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011 Linaro
|
||||
* Ryan Harkin, <ryan.harkin@linaro.org>
|
||||
*
|
||||
* Configuration for Versatile Express. Parts were derived from other ARM
|
||||
* configurations.
|
||||
*/
|
||||
|
||||
#ifndef __VEXPRESS_CA9X4_H
|
||||
#define __VEXPRESS_CA9X4_H
|
||||
|
||||
#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
|
||||
#include "vexpress_common.h"
|
||||
|
||||
#endif /* VEXPRESS_CA9X4_H */
|
||||
@ -158,29 +158,10 @@
|
||||
func(DHCP, dhcp, na)
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
|
||||
#define CONFIG_PLATFORM_ENV_SETTINGS \
|
||||
"loadaddr=0x80008000\0" \
|
||||
"ramdisk_addr_r=0x61000000\0" \
|
||||
"kernel_addr=0x44100000\0" \
|
||||
"ramdisk_addr=0x44800000\0" \
|
||||
"maxramdisk=0x1800000\0" \
|
||||
"pxefile_addr_r=0x88000000\0" \
|
||||
"scriptaddr=0x88000000\0" \
|
||||
"kernel_addr_r=0x80008000\0"
|
||||
#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
|
||||
#define CONFIG_PLATFORM_ENV_SETTINGS \
|
||||
"loadaddr=0xa0008000\0" \
|
||||
"ramdisk_addr_r=0x81000000\0" \
|
||||
"kernel_addr=0x0c100000\0" \
|
||||
"ramdisk_addr=0x0c800000\0" \
|
||||
"maxramdisk=0x1800000\0" \
|
||||
"pxefile_addr_r=0xa8000000\0" \
|
||||
"scriptaddr=0xa8000000\0" \
|
||||
"kernel_addr_r=0xa0008000\0"
|
||||
#endif
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_PLATFORM_ENV_SETTINGS \
|
||||
"kernel_addr_r=0x60100000\0" \
|
||||
"fdt_addr_r=0x60000000\0" \
|
||||
"bootargs=console=tty0 console=ttyAMA0,38400n8\0" \
|
||||
BOOTENV \
|
||||
"console=ttyAMA0,38400n8\0" \
|
||||
"dram=1024M\0" \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user