leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

armv7: ls102xa: Add workaround for DDR erratum A-008850

Browse Source 
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Alison Wang
2019-03-06 14:49:14 +08:00
committed by Prabhakar Kushwaha
parent ba7eadd8e1
commit 158097052a
10 changed files with 58 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/freescale/ls1021aiot/ls1021aiot.c
View File

@@ -97,6 +97,8 @@ int dram_init(void)
ddrmc_init();
#endif
erratum_a008850_post();
gd->ram_size = DDR_SIZE;
return 0;
}

2
board/freescale/ls1021aqds/ddr.c
View File

@@ -179,6 +179,8 @@ int fsl_initdram(void)
fsl_dp_resume();
#endif
erratum_a008850_post();
gd->ram_size = dram_size;
return 0;

3
board/freescale/ls1021aqds/ddr.h
View File

@@ -5,6 +5,9 @@
#ifndef __DDR_H__
#define __DDR_H__
void erratum_a008850_post(void);
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;

30
board/freescale/ls1021aqds/ls1021aqds.c
View File

@@ -200,10 +200,6 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
@@ -240,10 +236,6 @@ void board_init_f(ulong dummy)
i2c_init_all();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
timer_init();
dram_init();
@@ -420,22 +412,12 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
erratum_a009942_check_cpo();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -456,18 +438,6 @@ int board_init(void)
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif

2
board/freescale/ls1021atwr/ls1021atwr.c
View File

@@ -222,6 +222,8 @@ int dram_init(void)
ddrmc_init();
#endif
erratum_a008850_post();
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)