ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig
Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards. It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -41,6 +41,15 @@ config ARMV7_PSCI
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help
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Say Y here to enable PSCI support.
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config ARMV7_PSCI_NR_CPUS
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int "Maximum supported CPUs for PSCI"
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depends on ARMV7_NONSEC
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default 4
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help
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The maximum number of CPUs supported in the PSCI firmware.
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It is no problem to set a larger value than the number of
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CPUs in the actual hardware implementation.
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config ARMV7_LPAE
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bool "Use LPAE page table format" if EXPERT
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depends on CPU_V7
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@ -45,7 +45,6 @@
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#define CONFIG_S5P_PA_SYSRAM 0x02020000
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#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
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#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
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@ -91,6 +91,5 @@
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/* Misc utility code */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#endif /* __BCM_EP_BOARD_H */
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@ -60,7 +60,6 @@
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#include "tegra-common-usb-gadget.h"
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#include "tegra-common-post.h"
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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/* Reserve top 1M for secure RAM */
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#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
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#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
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@ -10,7 +10,6 @@
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#define CONFIG_LS102XA
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
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#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
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@ -10,7 +10,6 @@
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#define CONFIG_LS102XA
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
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#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
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@ -72,7 +72,6 @@
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#define CONFIG_CMD_FUSE
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#define CONFIG_MXC_OCOTP
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#define CONFIG_ARMV7_SECURE_BASE 0x00900000
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#endif
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@ -22,7 +22,6 @@
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#define CONFIG_SUNXI_USB_PHYS 3
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
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@ -20,7 +20,6 @@
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#define CONFIG_SUNXI_USB_PHYS 3
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
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@ -26,18 +26,6 @@
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#define CONFIG_SUNXI_USB_PHYS 2
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#endif
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#ifndef CONFIG_MACH_SUN8I_A83T
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#if defined(CONFIG_MACH_SUN8I_A23)
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#elif defined(CONFIG_MACH_SUN8I_A33)
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#elif defined(CONFIG_MACH_SUN8I_H3)
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#else
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#error Unsupported sun8i variant
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#endif
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#endif
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/*
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* Include common sunxi configuration where most the settings are
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*/
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@ -12,7 +12,6 @@
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#define __CONFIG_UNIPHIER_COMMON_H__
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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@ -16,6 +16,5 @@
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#define CONFIG_SYSFLAGS_ADDR 0x1c010030
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#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#endif
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