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clk: clk_stm32f7: fix PLL clock division factor

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Fix clock division factor initialization for RCC_PLLCFGR
registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Patrice Chotard 2017-10-26 13:23:19 +02:00 committed by Tom Rini
parent 5829fe2d59
commit 1543bf794f
1 changed files with 9 additions and 7 deletions
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16
drivers/clk/clk_stm32f7.c
View File

@ -136,13 +136,15 @@ static int configure_clocks(struct udevice *dev)
| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
/* Configure the main PLL */ /* Configure the main PLL */
uint32_t pllcfgr = 0; setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
writel(pllcfgr, &regs->pllcfgr); ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
/* Enable the main PLL */ /* Enable the main PLL */
setbits_le32(&regs->cr, RCC_CR_PLLON); setbits_le32(&regs->cr, RCC_CR_PLLON);