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Merge branch '2019-10-24-ti-imports'

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- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
This commit is contained in:
Tom Rini
2019-10-25 17:33:28 -04:00
parent 271103ac0b d0e134b909
commit 15147dc6a9
44 changed files with 39198 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/dts/dra7-evm-u-boot.dtsi
View File

@@ -32,3 +32,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};

17
arch/arm/dts/dra71-evm-u-boot.dtsi
View File

@@ -44,3 +44,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};

17
arch/arm/dts/dra72-evm-revc-u-boot.dtsi
View File

@@ -44,3 +44,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};

23
arch/arm/dts/dra72-evm-u-boot.dtsi Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};

17
arch/arm/dts/dra76-evm-u-boot.dtsi
View File

@@ -24,3 +24,20 @@
&mmc2_iodelay_hs200_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};

4
arch/arm/dts/k3-am65.dtsi
View File

@@ -74,6 +74,8 @@
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
@@ -86,6 +88,8 @@
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */

30
arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi → arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
View File

@@ -1,15 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by the AM65x_DRA80xM EMIF Tool:
* This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
* http://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600
* Data Rate: 1600 MT/s
* ECC Enabled: No
* Data Width: 32
* Data Width: 32 bits
*/
#define DDR_PLL_FREQUENCY 400000000
#define DDRSS_V2H_CTL_REG 0x000073FF
#define DDRCTL_MSTR 0x41040010
#define DDRCTL_RFSHCTL0 0x00210070
#define DDRCTL_ECCCFG0 0x00000000
@@ -32,10 +33,10 @@
#define DDRCTL_DRAMTMG5 0x04040302
#define DDRCTL_DRAMTMG6 0x00000004
#define DDRCTL_DRAMTMG7 0x00000404
#define DDRCTL_DRAMTMG8 0x03030C05
#define DDRCTL_DRAMTMG8 0x03030A05
#define DDRCTL_DRAMTMG9 0x00020208
#define DDRCTL_DRAMTMG10 0x001C180A
#define DDRCTL_DRAMTMG11 0x1106010E
#define DDRCTL_DRAMTMG11 0x0E06010E
#define DDRCTL_DRAMTMG12 0x00020008
#define DDRCTL_DRAMTMG13 0x0B100002
#define DDRCTL_DRAMTMG14 0x00000000
@@ -47,7 +48,7 @@
#define DDRCTL_DFITMG1 0x000A0606
#define DDRCTL_DFITMG2 0x00000604
#define DDRCTL_DFIMISC 0x00000001
#define DDRCTL_ADDRMAP0 0x001F1F1F
#define DDRCTL_ADDRMAP0 0x0000001F
#define DDRCTL_ADDRMAP1 0x003F0808
#define DDRCTL_ADDRMAP2 0x00000000
#define DDRCTL_ADDRMAP3 0x00000000
@@ -83,13 +84,13 @@
#define DDRPHY_DCR 0x0000040C
#define DDRPHY_DTPR0 0x041A0B06
#define DDRPHY_DTPR1 0x28140000
#define DDRPHY_DTPR2 0x0034E300
#define DDRPHY_DTPR3 0x02800800
#define DDRPHY_DTPR2 0x0034E255
#define DDRPHY_DTPR3 0x01D50800
#define DDRPHY_DTPR4 0x31180805
#define DDRPHY_DTPR5 0x00250B06
#define DDRPHY_DTPR6 0x00000505
#define DDRPHY_ZQCR 0x008A2A58
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x000077DD
#define DDRPHY_MR0 0x00000214
#define DDRPHY_MR1 0x00000501
@@ -109,6 +110,8 @@
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
#define DDRPHY_DTCR0 0x8000B1C7
#define DDRPHY_DTCR1 0x00010236
#define DDRPHY_ACIOCR0 0x30070000
#define DDRPHY_ACIOCR3 0x00000001
#define DDRPHY_ACIOCR5 0x04800000
#define DDRPHY_IOVCR0 0x0F0C0C0C
#define DDRPHY_DX0GCR0 0x00000000
@@ -148,9 +151,12 @@
#define DDRPHY_DX3GTR0 0x00020002
#define DDRPHY_DX4GTR0 0x00020002
#define DDRPHY_ODTCR 0x00010000
#define DDRPHY_DX8SL0IOCR 0x04800000
#define DDRPHY_DX8SL1IOCR 0x04800000
#define DDRPHY_DX8SL2IOCR 0x04800000
#define DDRPHY_DX8SL0IOCR 0x74800000
#define DDRPHY_DX8SL1IOCR 0x74800000
#define DDRPHY_DX8SL2IOCR 0x74800000
#define DDRPHY_DX8SL0DXCTL2 0x00141830
#define DDRPHY_DX8SL1DXCTL2 0x00141830
#define DDRPHY_DX8SL2DXCTL2 0x00141830
#define DDRPHY_DX8SL0DQSCTL 0x01264000
#define DDRPHY_DX8SL1DQSCTL 0x01264000
#define DDRPHY_DX8SL2DQSCTL 0x01264000

9
arch/arm/dts/k3-am654-ddr.dtsi
View File

@@ -17,6 +17,10 @@
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;
ti,ss-reg = <
DDRSS_V2H_CTL_REG
>;
ti,ctl-reg = <
DDRCTL_DFIMISC
DDRCTL_DFITMG0
@@ -132,12 +136,15 @@
DDRPHY_DX8SL0DXCTL2
DDRPHY_DX8SL0IOCR
DDRPHY_DX8SL0PLLCR0
DDRPHY_DX8SL0DQSCTL
DDRPHY_DX8SL1DXCTL2
DDRPHY_DX8SL1IOCR
DDRPHY_DX8SL1PLLCR0
DDRPHY_DX8SL1DQSCTL
DDRPHY_DX8SL2DXCTL2
DDRPHY_DX8SL2IOCR
DDRPHY_DX8SL2PLLCR0
DDRPHY_DX8SL2DQSCTL
DDRPHY_DXCCR
DDRPHY_ODTCR
DDRPHY_PGCR0
@@ -168,6 +175,8 @@
>;
ti,phy-ioctl = <
DDRPHY_ACIOCR0
DDRPHY_ACIOCR3
DDRPHY_ACIOCR5
DDRPHY_IOVCR0
>;

2
arch/arm/dts/k3-am654-r5-base-board.dts
View File

@@ -7,7 +7,7 @@
#include "k3-am654.dtsi"
#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {

2195
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

2212
arch/arm/dts/k3-j721e-ddr.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
View File

@@ -6,6 +6,8 @@
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-3733.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
aliases {

1
arch/arm/dts/omap5-u-boot.dtsi
View File

@@ -22,6 +22,7 @@
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp", "simple-bus";
u-boot,dm-spl;
};
ocp2scp@4a090000 {

4
arch/arm/lib/bootm.c
View File

@@ -224,6 +224,8 @@ static void do_nonsec_virt_switch(void)
}
#endif
__weak void board_prep_linux(bootm_headers_t *images) { }
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
@@ -270,6 +272,8 @@ static void boot_prep_linux(bootm_headers_t *images)
printf("FDT and ATAGS support not compiled in - hanging\n");
hang();
}
board_prep_linux(images);
}
__weak bool armv7_boot_nonsec_default(void)

11
arch/arm/mach-k3/common.c
View File

@@ -233,3 +233,14 @@ int print_cpuinfo(void)
return 0;
}
#endif
#ifdef CONFIG_ARM64
void board_prep_linux(bootm_headers_t *images)
{
debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
images->os.start, images->os.end);
__asm_flush_dcache_range(images->os.start,
ROUND(images->os.end,
CONFIG_SYS_CACHELINE_SIZE));
}
#endif

8
arch/arm/mach-k3/j721e_init.c
View File

@@ -73,7 +73,7 @@ static void store_boot_index_from_rom(void)
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
struct udevice *dev;
int ret;
#endif
@@ -117,6 +117,12 @@ void board_init_f(ulong dummy)
/* Prepare console output */
preloader_console_init();
#endif
#if defined(CONFIG_K3_J721E_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
}
u32 spl_boot_mode(const u32 boot_device)