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Prepare v2023.01-rc4

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Merge tag 'v2023.01-rc4' into next

Prepare v2023.01-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-19 09:29:55 -05:00
commit 14f43797d0
267 changed files with 3298 additions and 846 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Kconfig
View File

@ -586,6 +586,7 @@ config SYS_SRAM_SIZE
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
default 786432 if ARCH_SUNXI
default 0
help
Size of memory reserved for monitor code, used to determine

5
MAINTAINERS
View File

@ -568,10 +568,9 @@ F: drivers/spi/stm32_spi.c
F: drivers/video/stm32/stm32_ltdc.c
F: drivers/watchdog/stm32mp_wdt.c
F: include/dt-bindings/clock/stm32fx-clock.h
F: include/dt-bindings/clock/stm32mp1-clks.h
F: include/dt-bindings/clock/stm32mp1-clksrc.h
F: include/dt-bindings/clock/stm32mp*
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
F: include/dt-bindings/reset/stm32mp1-resets.h
F: include/dt-bindings/reset/stm32mp*
F: include/stm32_rcc.h
F: tools/stm32image.c
N: stm

4
Makefile
View File

@ -3,7 +3,7 @@
VERSION = 2023
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@ -1336,7 +1336,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . -m \
$(if $(BINMAN_ALLOW_MISSING),--allow-missing --fake-ext-blobs) \
$(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \

2
arch/Kconfig
View File

@ -111,7 +111,7 @@ config RISCV
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select SPL_SEPARATE_BSS if SPL
imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_EVENT
imply DM_MMC

46
arch/arm/Kconfig
View File

@ -413,52 +413,6 @@ config ARM_SMCCC
This should be enabled if U-Boot needs to communicate with system
firmware (for example, PSCI) according to SMCCC.
config SEMIHOSTING
bool "Support ARM semihosting"
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
on and interpret. This allows U-Boot to read/write files, print to
the console, and execute arbitrary commands on the host system.
Enabling this option will add support for reading and writing files
on the host system. If you don't have a debugger attached then trying
to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
depends on SEMIHOSTING && ARM64
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
attached, then it will panic due to a synchronous abort
exception. This config adds an exception handler which will allow
U-Boot to recover. Say 'y' if unsure.
config SPL_SEMIHOSTING
bool "Support ARM semihosting in SPL"
depends on SPL
help
Semihosting is a method for a target to communicate with a host
debugger. It uses special instructions which the debugger will trap
on and interpret. This allows U-Boot to read/write files, print to
the console, and execute arbitrary commands on the host system.
Enabling this option will add support for reading and writing files
on the host system. If you don't have a debugger attached then trying
to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
depends on SPL_SEMIHOSTING && ARM64
select ARMV8_SPL_EXCEPTION_VECTORS
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
attached, then it will panic due to a synchronous abort
exception. This config adds an exception handler which will allow
U-Boot to recover. Say 'y' if unsure.
config SYS_THUMB_BUILD
bool "Build U-Boot using the Thumb instruction set"
depends on !ARM64

7
arch/arm/dts/rk3128-evb-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3128-u-boot.dtsi"
&emmc {
u-boot,dm-pre-reloc;
};

19
arch/arm/dts/rk3128-evb.dts
View File

@ -15,6 +15,11 @@
stdout-path = &uart2;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
@ -37,6 +42,11 @@
};
};
&emmc {
fifo-mode;
status = "okay";
};
&i2c1 {
status = "okay";
@ -74,21 +84,16 @@
status = "okay";
};
&emmc {
fifo-mode;
status = "okay";
};
&pinctrl {
usb_otg {
otg_vbus_drv: host-vbus-drv {
rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

19
arch/arm/dts/rk3128-u-boot.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rockchip-u-boot.dtsi"
/ {
dmc: dmc@20004000 {
compatible = "rockchip,rk3128-dmc", "syscon";
reg = <0x0 0x20004000 0x0 0x1000>;
u-boot,dm-pre-reloc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};

209
arch/arm/dts/rk3128.dtsi
View File

@ -8,7 +8,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include "skeleton.dtsi"
/ {
compatible = "rockchip,rk3128";
@ -34,11 +33,6 @@
mmc1 = &sdmmc;
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@ -52,10 +46,10 @@
#size-cells = <0>;
enable-method = "rockchip,rk3128-smp";
cpu0:cpu@0x000 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x000>;
reg = <0x0>;
operating-points = <
/* KHz uV */
816000 1000000
@ -65,22 +59,22 @@
clocks = <&cru ARMCLK>;
};
cpu1:cpu@0x001 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x001>;
reg = <0x1>;
};
cpu2:cpu@0x002 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x002>;
reg = <0x2>;
};
cpu3:cpu@0x003 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x003>;
reg = <0x3>;
};
};
@ -165,14 +159,14 @@
interrupt-parent = <&gic>;
ranges;
pdma: pdma@20078000 {
pdma: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
arm,pl330-broken-no-flushp;//2
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC2>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
};
@ -186,7 +180,6 @@
xin12m: xin12m {
compatible = "fixed-clock";
clocks = <&xin24m>;
clock-frequency = <12000000>;
clock-output-names = "xin12m";
#clock-cells = <0>;
@ -207,10 +200,10 @@
rockchip,broadcast = <1>;
};
watchdog: wdt@2004c000 {
compatible = "rockchip,watch dog";
watchdog: watchdog@2004c000 {
compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
reg = <0x2004c000 0x100>;
clock-names = "pclk_wdt";
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
rockchip,irq = <1>;
rockchip,timeout = <60>;
@ -224,29 +217,21 @@
#reset-cells = <1>;
};
nandc: nandc@10500000 {
compatible = "rockchip,rk-nandc";
nandc: nand-controller@10500000 {
compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
nandc_id = <0>;
clocks = <&cru SCLK_NANDC>,
<&cru HCLK_NANDC>,
<&cru SRST_NANDC>;
clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
};
dmc: dmc@20004000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-dmc", "syscon";
reg = <0x0 0x20004000 0x0 0x1000>;
clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
clock-names = "ahb", "nfc";
};
cru: clock-controller@20000000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -254,7 +239,7 @@
assigned-clock-rates = <594000000>;
};
uart0: serial0@20060000 {
uart0: serial@20060000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@ -269,7 +254,7 @@
#dma-cells = <2>;
};
uart1: serial1@20064000 {
uart1: serial@20064000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@ -284,7 +269,7 @@
#dma-cells = <2>;
};
uart2: serial2@20068000 {
uart2: serial@20068000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -311,44 +296,40 @@
status = "disabled";
};
pwm0: pwm0@20050000 {
pwm0: pwm@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
};
pwm1: pwm1@20050010 {
pwm1: pwm@20050010 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
};
pwm2: pwm2@20050020 {
pwm2: pwm@20050020 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
};
pwm3: pwm3@20050030 {
pwm3: pwm@20050030 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
};
sram: sram@10080400 {
@ -377,7 +358,7 @@
interrupts = <GIC_PPI 9 0xf04>;
};
u2phy: usb2-phy {
u2phy: usb2phy {
compatible = "rockchip,rk3128-usb2phy";
reg = <0x017c 0x0c>;
rockchip,grf = <&grf>;
@ -385,7 +366,6 @@
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy";
#phy-cells = <1>;
status = "disabled";
u2phy_otg: otg-port {
@ -407,15 +387,14 @@
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
"snps,dwc2";
compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-use-dma;
hnp-srp-disable;
phys = <&u2phy 0>;
phy-names = "usb";
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
@ -423,7 +402,7 @@
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
phys = <&u2phy 1>;
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
@ -432,19 +411,19 @@
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
phys = <&u2phy 1>;
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@ -452,15 +431,14 @@
status = "disabled";
};
emmc: dwmmc@1021c000 {
u-boot,dm-pre-reloc;
emmc: mmc@1021c000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
max-frequency = <150000000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
@ -472,7 +450,7 @@
status = "disabled";
};
i2c0: i2c0@20072000 {
i2c0: i2c@20072000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@ -484,7 +462,7 @@
pinctrl-0 = <&i2c0_xfer>;
};
i2c1: i2c1@20056000 {
i2c1: i2c@20056000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@ -496,7 +474,7 @@
pinctrl-0 = <&i2c1_xfer>;
};
i2c2: i2c2@2005a000 {
i2c2: i2c@2005a000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@ -508,7 +486,7 @@
pinctrl-0 = <&i2c2_xfer>;
};
i2c3: i2c3@2005e000 {
i2c3: i2c@2005e000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005e000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
@ -521,7 +499,7 @@
};
spi0: spi@20074000 {
compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@ -530,15 +508,14 @@
pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
rockchip,spi-src-clk = <0>;
num-cs = <2>;
clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
clock-names = "spi","pclk_spi0";
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
#dma-cells = <2>;
dma-names = "tx", "rx";
};
grf: syscon@20008000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-grf", "syscon";
reg = <0x20008000 0x1000>;
};
@ -555,7 +532,7 @@
#size-cells = <1>;
ranges;
gpio0: gpio0@2007c000 {
gpio0: gpio@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@ -566,7 +543,7 @@
#interrupt-cells = <2>;
};
gpio1: gpio1@20080000 {
gpio1: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@ -577,7 +554,7 @@
#interrupt-cells = <2>;
};
gpio2: gpio2@20084000 {
gpio2: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@ -588,7 +565,7 @@
#interrupt-cells = <2>;
};
gpio3: gpio2@20088000 {
gpio3: gpio@20088000 {
compatible = "rockchip,gpio-bank";
reg = <0x20088000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
@ -618,85 +595,85 @@
*/
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
emmc_pwren: emmc-pwren {
rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
<1 25 RK_FUNC_2 &pcfg_pull_none>,
<1 26 RK_FUNC_2 &pcfg_pull_none>,
<1 27 RK_FUNC_2 &pcfg_pull_none>,
<1 28 RK_FUNC_2 &pcfg_pull_none>,
<1 29 RK_FUNC_2 &pcfg_pull_none>,
<1 30 RK_FUNC_2 &pcfg_pull_none>,
<1 31 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
<1 RK_PD1 2 &pcfg_pull_none>,
<1 RK_PD2 2 &pcfg_pull_none>,
<1 RK_PD3 2 &pcfg_pull_none>,
<1 RK_PD4 2 &pcfg_pull_none>,
<1 RK_PD5 2 &pcfg_pull_none>,
<1 RK_PD6 2 &pcfg_pull_none>,
<1 RK_PD7 2 &pcfg_pull_none>;
};
};
nandc{
nandc_ale:nandc-ale {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_cle:nandc-cle {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_wrn:nandc-wrn {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_rdn:nandc-rdn {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_rdy:nandc-rdy {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_cs0:nandc-cs0 {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_data: nandc-data {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
<0 17 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
<0 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
<2 23 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
<2 RK_PC7 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
<1 19 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
};
@ -727,75 +704,75 @@
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <0 1 2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <0 27 1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
<0 1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
<0 3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 20 3 &pcfg_pull_none>,
<2 21 3 &pcfg_pull_none>;
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
<2 RK_PC5 3 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
<0 7 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
<0 RK_PA7 1 &pcfg_pull_none>;
};
};
spi0 {
spi0_txd_mux0:spi0-txd-mux0 {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_rxd_mux0:spi0-rxd-mux0 {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_clk_mux0:spi0-clk-mux0 {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_cs0_mux0:spi0-cs0-mux0 {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_cs1_mux0:spi0-cs1-mux0 {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
};

8
arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
View File

@ -20,14 +20,6 @@
rockchip,panel = <&edp_panel>;
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&rk808 {
u-boot,dm-pre-reloc;
};
&sdhci {
max-frequency = <25000000>;
u-boot,dm-pre-reloc;

2
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
View File

@ -15,7 +15,7 @@
/ {
config {
u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
u-boot,boot-led = "module_led";
sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;

2
arch/arm/dts/rockchip-u-boot.dtsi
View File

@ -11,7 +11,7 @@
};
};
#ifdef CONFIG_SPL
#ifdef CONFIG_TPL
&binman {
simple-bin {
filename = "u-boot-rockchip.bin";

2
arch/arm/dts/sama7g5-pinfunc.h
View File

@ -673,7 +673,7 @@
#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0)
#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1)
#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1)
#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2)
#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5)
#define PIN_PD9 105

2
arch/arm/dts/stm32h743.dtsi
View File

@ -339,7 +339,6 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x52007000 0x1000>;
interrupts = <49>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
@ -353,7 +352,6 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x48022400 0x400>;
interrupts = <124>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_CK>;
clock-names = "apb_pclk";
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;

4
arch/arm/dts/stm32mp13-u-boot.dtsi
View File

@ -92,6 +92,10 @@
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};
&scmi {
u-boot,dm-pre-reloc;
};

121
arch/arm/dts/stm32mp131.dtsi
View File

@ -4,6 +4,8 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
/ {
#address-cells = <1>;
@ -52,62 +54,6 @@
};
};
clocks {
clk_axi: clk-axi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <266500000>;
};
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_pclk3: clk-pclk3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104438965>;
};
clk_pclk4: clk-pclk4 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <133250000>;
};
clk_pll4_p: clk-pll4_p {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clk_pll4_r: clk-pll4_r {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <99000000>;
};
clk_rtc_k: clk-rtc-k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
@ -155,7 +101,8 @@
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hsi>;
clocks = <&rcc UART4_K>;
resets = <&rcc UART4_R>;
status = "disabled";
};
@ -170,7 +117,8 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMA1>;
resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@ -187,7 +135,8 @@
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMA2>;
resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@ -196,13 +145,29 @@
dmamux1: dma-router@48002000 {
compatible = "st,stm32h7-dmamux";
reg = <0x48002000 0x40>;
clocks = <&clk_pclk4>;
clocks = <&rcc DMAMUX1>;
resets = <&rcc DMAMUX1_R>;
#dma-cells = <3>;
dma-masters = <&dma1 &dma2>;
dma-requests = <128>;
dma-channels = <16>;
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
interrupt-controller;
@ -213,14 +178,14 @@
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&clk_pclk3>;
clocks = <&rcc SYSCFG>;
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>;
clocks = <&rcc MDMA>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
@ -231,9 +196,9 @@
arm,primecell-periphid = <0x20253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&clk_pll4_p>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@ -245,9 +210,10 @@
arm,primecell-periphid = <0x20253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&clk_pll4_p>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
@ -257,7 +223,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&clk_pclk4>, <&clk_lsi>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
};
@ -266,7 +232,8 @@
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pclk4>, <&clk_rtc_k>;
clocks = <&scmi_clk CK_SCMI_RTCAPB>,
<&scmi_clk CK_SCMI_RTC>;
clock-names = "pclk", "rtc_ck";
status = "disabled";
};
@ -307,7 +274,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
@ -319,7 +286,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
@ -331,7 +298,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
@ -343,7 +310,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
@ -355,7 +322,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
@ -367,7 +334,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
@ -379,7 +346,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
@ -391,7 +358,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
ngpios = <15>;
gpio-ranges = <&pinctrl 0 112 15>;
@ -403,7 +370,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&clk_pclk4>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 128 8>;

4
arch/arm/dts/stm32mp133.dtsi
View File

@ -15,7 +15,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clk_hse>, <&clk_pll4_r>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
@ -28,7 +28,7 @@
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&clk_hse>, <&clk_pll4_r>;
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";

2
arch/arm/dts/stm32mp135f-dk.dts
View File

@ -82,7 +82,7 @@
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;

3
arch/arm/dts/stm32mp13xc.dtsi
View File

@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_axi>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};

3
arch/arm/dts/stm32mp13xf.dtsi
View File

@ -10,7 +10,8 @@
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_axi>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};

3
arch/arm/dts/stm32mp151.dtsi
View File

@ -1102,7 +1102,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC3_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC3_R>;
@ -1435,7 +1434,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
@ -1450,7 +1448,6 @@
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;

1
arch/arm/include/asm/arch-rockchip/misc.h
View File

@ -11,3 +11,4 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
u8 *cpuid);
int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
int rockchip_setup_macaddr(void);
void rockchip_capsule_update_board_setup(void);

181
arch/arm/lib/semihosting.c
View File

@ -5,20 +5,6 @@
*/
#include <common.h>
#include <log.h>
#include <semihosting.h>
#define SYSOPEN 0x01
#define SYSCLOSE 0x02
#define SYSWRITEC 0x03
#define SYSWRITE0 0x04
#define SYSWRITE 0x05
#define SYSREAD 0x06
#define SYSREADC 0x07
#define SYSISERROR 0x08
#define SYSSEEK 0x0A
#define SYSFLEN 0x0C
#define SYSERRNO 0x13
/*
* Macro to force the compiler to *populate* memory (for an array or struct)
@ -39,7 +25,7 @@
/*
* Call the handler
*/
static long smh_trap(unsigned int sysnum, void *addr)
long smh_trap(unsigned int sysnum, void *addr)
{
register long result asm("r0");
register void *_addr asm("r1") = addr;
@ -59,168 +45,3 @@ static long smh_trap(unsigned int sysnum, void *addr)
return result;
}
#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
static bool _semihosting_enabled = true;
static bool try_semihosting = true;
bool semihosting_enabled(void)
{
if (try_semihosting) {
smh_trap(SYSERRNO, NULL);
try_semihosting = false;
}
return _semihosting_enabled;
}
void disable_semihosting(void)
{
_semihosting_enabled = false;
}
#endif
/**
* smh_errno() - Read the host's errno
*
* This gets the value of the host's errno and negates it. The host's errno may
* or may not be set, so only call this function if a previous semihosting call
* has failed.
*
* Return: a negative error value
*/
static int smh_errno(void)
{
long ret = smh_trap(SYSERRNO, NULL);
if (ret > 0 && ret < INT_MAX)
return -ret;
return -EIO;
}
long smh_open(const char *fname, enum smh_open_mode mode)
{
long fd;
struct smh_open_s {
const char *fname;
unsigned long mode;
size_t len;
} open;
debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode);
open.fname = fname;
open.len = strlen(fname);
open.mode = mode;
/* Open the file on the host */
fd = smh_trap(SYSOPEN, &open);
if (fd == -1)
return smh_errno();
return fd;
}
/**
* struct smg_rdwr_s - Arguments for read and write
* @fd: A file descriptor returned from smh_open()
* @memp: Pointer to a buffer of memory of at least @len bytes
* @len: The number of bytes to read or write
*/
struct smh_rdwr_s {
long fd;
void *memp;
size_t len;
};
long smh_read(long fd, void *memp, size_t len)
{
long ret;
struct smh_rdwr_s read;
debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
read.fd = fd;
read.memp = memp;
read.len = len;
ret = smh_trap(SYSREAD, &read);
if (ret < 0)
return smh_errno();
return len - ret;
}
long smh_write(long fd, const void *memp, size_t len, ulong *written)
{
long ret;
struct smh_rdwr_s write;
debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
write.fd = fd;
write.memp = (void *)memp;
write.len = len;
ret = smh_trap(SYSWRITE, &write);
*written = len - ret;
if (ret)
return smh_errno();
return 0;
}
long smh_close(long fd)
{
long ret;
debug("%s: fd %ld\n", __func__, fd);
ret = smh_trap(SYSCLOSE, &fd);
if (ret == -1)
return smh_errno();
return 0;
}
long smh_flen(long fd)
{
long ret;
debug("%s: fd %ld\n", __func__, fd);
ret = smh_trap(SYSFLEN, &fd);
if (ret == -1)
return smh_errno();
return ret;
}
long smh_seek(long fd, long pos)
{
long ret;
struct smh_seek_s {
long fd;
long pos;
} seek;
debug("%s: fd %ld pos %ld\n", __func__, fd, pos);
seek.fd = fd;
seek.pos = pos;
ret = smh_trap(SYSSEEK, &seek);
if (ret)
return smh_errno();
return 0;
}
int smh_getc(void)
{
return smh_trap(SYSREADC, NULL);
}
void smh_putc(char ch)
{
smh_trap(SYSWRITEC, &ch);
}
void smh_puts(const char *s)
{
smh_trap(SYSWRITE0, (char *)s);
}

1
arch/arm/mach-rockchip/Kconfig
View File

@ -246,6 +246,7 @@ config ROCKCHIP_RK3399
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
imply PARTITION_TYPE_GUID
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON

153
arch/arm/mach-rockchip/board.c
View File

@ -6,11 +6,15 @@
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <efi_loader.h>
#include <fastboot.h>
#include <init.h>
#include <log.h>
#include <mmc.h>
#include <part.h>
#include <ram.h>
#include <syscon.h>
#include <uuid.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -22,8 +26,157 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
#define DFU_ALT_BUF_LEN SZ_1K
static struct efi_fw_image *fw_images;
static bool updatable_image(struct disk_partition *info)
{
int i;
bool ret = false;
efi_guid_t image_type_guid;
uuid_str_to_bin(info->type_guid, image_type_guid.b,
UUID_STR_FORMAT_GUID);
for (i = 0; i < num_image_type_guids; i++) {
if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
ret = true;
break;
}
}
return ret;
}
static void set_image_index(struct disk_partition *info, int index)
{
int i;
efi_guid_t image_type_guid;
uuid_str_to_bin(info->type_guid, image_type_guid.b,
UUID_STR_FORMAT_GUID);
for (i = 0; i < num_image_type_guids; i++) {
if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) {
fw_images[i].image_index = index;
break;
}
}
}
static int get_mmc_desc(struct blk_desc **desc)
{
int ret;
struct mmc *mmc;
struct udevice *dev;
/*
* For now the firmware images are assumed to
* be on the SD card
*/
ret = uclass_get_device(UCLASS_MMC, 1, &dev);
if (ret)
return -1;
mmc = mmc_get_mmc_dev(dev);
if (!mmc)
return -ENODEV;
if ((ret = mmc_init(mmc)))
return ret;
*desc = mmc_get_blk_desc(mmc);
if (!*desc)
return -1;
return 0;
}
void set_dfu_alt_info(char *interface, char *devstr)
{
const char *name;
bool first = true;
int p, len, devnum, ret;
char buf[DFU_ALT_BUF_LEN];
struct disk_partition info;
struct blk_desc *desc = NULL;
ret = get_mmc_desc(&desc);
if (ret) {
log_err("Unable to get mmc desc\n");
return;
}
memset(buf, 0, sizeof(buf));
name = blk_get_uclass_name(desc->uclass_id);
devnum = desc->devnum;
len = strlen(buf);
len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
"%s %d=", name, devnum);
for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
if (part_get_info(desc, p, &info))
continue;
/* Add entry to dfu_alt_info only for updatable images */
if (updatable_image(&info)) {
if (!first)
len += snprintf(buf + len,
DFU_ALT_BUF_LEN - len, ";");
len += snprintf(buf + len, DFU_ALT_BUF_LEN - len,
"%s%d_%s part %d %d",
name, devnum, info.name, devnum, p);
first = false;
}
}
log_debug("dfu_alt_info => %s\n", buf);
env_set("dfu_alt_info", buf);
}
static void gpt_capsule_update_setup(void)
{
int p, i, ret;
struct disk_partition info;
struct blk_desc *desc = NULL;
fw_images = update_info.images;
rockchip_capsule_update_board_setup();
ret = get_mmc_desc(&desc);
if (ret) {
log_err("Unable to get mmc desc\n");
return;
}
for (p = 1, i = 1; p <= MAX_SEARCH_PARTITIONS; p++) {
if (part_get_info(desc, p, &info))
continue;
/*
* Since we have a GPT partitioned device, the updatable
* images could be stored in any order. Populate the
* image_index at runtime.
*/
if (updatable_image(&info)) {
set_image_index(&info, i);
i++;
}
}
}
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
__weak int rk_board_late_init(void)
{
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
gpt_capsule_update_setup();
#endif
return 0;
}

8
arch/arm/mach-sunxi/board.c
View File

@ -73,7 +73,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_top;
}
#endif
#endif /* CONFIG_ARM64 */
#ifdef CONFIG_SPL_BUILD
static int gpio_init(void)
@ -196,7 +196,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
return 0;
}
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
#endif
#endif /* CONFIG_SPL_BUILD */
#define SUNXI_INVALID_BOOT_SOURCE -1
@ -457,7 +457,7 @@ void board_init_f(ulong dummy)
#endif
sunxi_board_init();
}
#endif
#endif /* CONFIG_SPL_BUILD */
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
@ -490,7 +490,7 @@ void reset_cpu(void)
while (1) { }
#endif
}
#endif
#endif /* CONFIG_SYSRESET */
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
void enable_caches(void)

4
arch/arm/mach-sunxi/clock_sun6i.c
View File

@ -63,7 +63,7 @@ void clock_init_safe(void)
setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
#endif
}
#endif
#endif /* CONFIG_SPL_BUILD */
void clock_init_sec(void)
{
@ -172,7 +172,7 @@ void clock_set_pll1(unsigned int clk)
&ccm->cpu_axi_cfg);
}
}
#endif
#endif /* CONFIG_SPL_BUILD */
void clock_set_pll3(unsigned int clk)
{

1
arch/riscv/include/asm/spl.h
View File

@ -25,6 +25,7 @@ enum {
BOOT_DEVICE_DFU,
BOOT_DEVICE_XIP,
BOOT_DEVICE_BOOTROM,
BOOT_DEVICE_SMH,
BOOT_DEVICE_NONE
};

2
arch/riscv/lib/Makefile
View File

@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o

25
arch/riscv/lib/interrupts.c
View File

@ -9,6 +9,7 @@
* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
*/
#include <linux/compat.h>
#include <common.h>
#include <efi_loader.h>
#include <hang.h>
@ -17,6 +18,7 @@
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
#include <semihosting.h>
DECLARE_GLOBAL_DATA_PTR;
@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
/* An UEFI application may have changed gd. Restore U-Boot's gd. */
efi_restore_gd();
if (cause == CAUSE_BREAKPOINT &&
CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
ulong pre_addr = epc - 4, post_addr = epc + 4;
/* Check for prior and post addresses to be in same page. */
if ((pre_addr & ~(PAGE_SIZE - 1)) ==
(post_addr & ~(PAGE_SIZE - 1))) {
u32 pre = *(u32 *)pre_addr;
u32 post = *(u32 *)post_addr;
/* Check for semihosting, i.e.:
* slli zero,zero,0x1f
* ebreak
* srai zero,zero,0x7
*/
if (pre == 0x01f01013 && post == 0x40705013) {
disable_semihosting();
epc += 4;
return epc;
}
}
}
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);

24
arch/riscv/lib/semihosting.c Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Ventana Micro Systems Inc.
*/
#include <common.h>
long smh_trap(int sysnum, void *addr)
{
register int ret asm ("a0") = sysnum;
register void *param0 asm ("a1") = addr;
asm volatile (".align 4\n"
".option push\n"
".option norvc\n"
"slli zero, zero, 0x1f\n"
"ebreak\n"
"srai zero, zero, 7\n"
".option pop\n"
: "+r" (ret) : "r" (param0) : "memory");
return ret;
}

11
arch/sandbox/cpu/sdl.c
View File

@ -441,7 +441,6 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len)
{
struct buf_info *buf;
int avail;
bool have_data = false;
int i;
for (i = 0; i < 2; i++) {
@ -453,10 +452,9 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len)
}
if (avail > len)
avail = len;
have_data = true;
SDL_MixAudio(stream, buf->data + buf->pos, avail,
SDL_MIX_MAXVOLUME);
memcpy(stream, buf->data + buf->pos, avail);
stream += avail;
buf->pos += avail;
len -= avail;
@ -466,7 +464,8 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len)
else
break;
}
sdl.stopping = !have_data;
memset(stream, 0, len);
sdl.stopping = !!len;
}
int sandbox_sdl_sound_init(int rate, int channels)
@ -484,7 +483,7 @@ int sandbox_sdl_sound_init(int rate, int channels)
wanted.freq = rate;
wanted.format = AUDIO_S16;
wanted.channels = channels;
wanted.samples = 1024; /* Good low-latency value for callback */
wanted.samples = 960; /* Good low-latency value for callback */
wanted.callback = sandbox_sdl_fill_audio;
wanted.userdata = NULL;

10
arch/sandbox/include/asm/test.h
View File

@ -188,6 +188,16 @@ int sandbox_get_setup_called(struct udevice *dev);
*/
int sandbox_get_sound_active(struct udevice *dev);
/**
* sandbox_get_sound_count() - Read back the count of the sound data so far
*
* This data is provided to the sandbox driver by the sound play() method.
*
* @dev: Device to check
* Return: count of audio data
*/
int sandbox_get_sound_count(struct udevice *dev);
/**
* sandbox_get_sound_sum() - Read back the sum of the sound data so far
*

2
arch/x86/cpu/cpu.c
View File

@ -315,7 +315,7 @@ int reserve_arch(void)
if (IS_ENABLED(CONFIG_HAVE_FSP)) {
/*
* Save stack address to CMOS so that at next S3 boot,
* we can use it as the stack address for fsp_contiue()
* we can use it as the stack address for fsp_continue()
*/
fsp_save_s3_stack();
}

4
arch/x86/include/asm/i8259.h
View File

@ -7,7 +7,7 @@
/* i8259.h i8259 PIC Registers */
#ifndef _ASMI386_I8259_H_
#define _ASMI386_I8959_H_
#define _ASMI386_I8259_H_
/* PIC I/O mapped registers */
#define IRR 0x0 /* Interrupt Request Register */
@ -73,4 +73,4 @@
int i8259_init(void);
#endif /* _ASMI386_I8959_H_ */
#endif /* _ASMI386_I8259_H_ */

20
board/Marvell/mvebu_armada-37xx/board.c
View File

@ -99,9 +99,16 @@ int board_late_init(void)
if (!of_machine_is_compatible("globalscale,espressobin"))
return 0;
/* Find free buffer in default_environment[] for new variables */
while (*ptr != '\0' && *(ptr+1) != '\0') ptr++;
ptr += 2;
/*
* Find free space for new variables in default_environment[] array.
* Free space is after the last variable, each variable is termined
* by nul byte and after the last variable is additional nul byte.
* Move ptr to the position where new variable can be filled.
*/
while (*ptr != '\0') {
do { ptr++; } while (*ptr != '\0');
ptr++;
}
/*
* Ensure that 'env default -a' does not erase permanent MAC addresses
@ -145,6 +152,13 @@ int board_late_init(void)
strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
else
strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
ptr += strlen(ptr) + 1;
/*
* After the last variable (which is nul term string) append another nul
* byte which terminates the list. So everything after ptr is ignored.
*/
*ptr = '\0';
return 0;
}

55
board/rockchip/evb_rk3399/evb-rk3399.c
View File

@ -5,11 +5,25 @@
#include <common.h>
#include <dm.h>
#include <efi_loader.h>
#include <init.h>
#include <log.h>
#include <asm/arch-rockchip/periph.h>
#include <linux/kernel.h>
#include <power/regulator.h>
#define ROCKPI4_UPDATABLE_IMAGES 2
#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0};
struct efi_capsule_update_info update_info = {
.images = fw_images,
};
u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES;
#endif
#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
{
@ -29,4 +43,43 @@ int board_early_init_f(void)
out:
return 0;
}
#endif
#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
static bool board_is_rockpi_4b(void)
{
return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) &&
of_machine_is_compatible("radxa,rockpi4b");
}
static bool board_is_rockpi_4c(void)
{
return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) &&
of_machine_is_compatible("radxa,rockpi4c");
}
void rockchip_capsule_update_board_setup(void)
{
if (board_is_rockpi_4b()) {
efi_guid_t idbldr_image_type_guid =
ROCKPI_4B_IDBLOADER_IMAGE_GUID;
efi_guid_t uboot_image_type_guid = ROCKPI_4B_UBOOT_IMAGE_GUID;
guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid);
guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid);
fw_images[0].fw_name = u"ROCKPI4B-IDBLOADER";
fw_images[1].fw_name = u"ROCKPI4B-UBOOT";
} else if (board_is_rockpi_4c()) {
efi_guid_t idbldr_image_type_guid =
ROCKPI_4C_IDBLOADER_IMAGE_GUID;
efi_guid_t uboot_image_type_guid = ROCKPI_4C_UBOOT_IMAGE_GUID;
guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid);
guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid);
fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER";
fw_images[1].fw_name = u"ROCKPI4C-UBOOT";
}
}
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
#endif /* !CONFIG_SPL_BUILD */

24
board/sunxi/board.c
View File

@ -184,10 +184,6 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_UNKNOWN;
}
#ifdef CONFIG_DM_MMC
static void mmc_pinmux_setup(int sdc);
#endif
/* add board specific code here */
int board_init(void)
{
@ -355,7 +351,7 @@ void board_nand_init(void)
sunxi_nand_init();
#endif
}
#endif
#endif /* CONFIG_NAND_SUNXI */
#ifdef CONFIG_MMC
static void mmc_pinmux_setup(int sdc)
@ -525,9 +521,14 @@ static void mmc_pinmux_setup(int sdc)
int board_mmc_init(struct bd_info *bis)
{
/*
* The BROM always accesses MMC port 0 (typically an SD card), and
* most boards seem to have such a slot. The others haven't reported
* any problem with unconditionally enabling this in the SPL.
*/
if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT))
mmc_pinmux_setup(0);
if (!sunxi_mmc_init(0))
return -1;
}
@ -553,7 +554,7 @@ int mmc_get_env_dev(void)
}
}
#endif
#endif
#endif /* CONFIG_MMC */
#ifdef CONFIG_SPL_BUILD
@ -669,7 +670,7 @@ void sunxi_board_init(void)
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
#endif
#endif /* CONFIG_SPL_BUILD */
#ifdef CONFIG_USB_GADGET
int g_dnl_board_usb_cable_connected(void)
@ -698,7 +699,7 @@ int g_dnl_board_usb_cable_connected(void)
return sun4i_usb_phy_vbus_detect(&phy);
}
#endif
#endif /* CONFIG_USB_GADGET */
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
@ -927,7 +928,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#ifdef CONFIG_SPL_LOAD_FIT
static void set_spl_dt_name(const char *name)
{
struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
@ -995,4 +995,4 @@ int board_fit_config_name_match(const char *name)
return ret;
}
#endif
#endif /* CONFIG_SPL_LOAD_FIT */

8
boot/pxe_utils.c
View File

@ -618,10 +618,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
* Scenario 2: If there is an fdt_addr specified, pass it along to
* bootm, and adjust argc appropriately.
*
* Scenario 3: If there is an fdtcontroladdr specified, pass it along to
* bootm, and adjust argc appropriately.
*
* Scenario 4: fdt blob is not available.
* Scenario 3: fdt blob is not available.
*/
bootm_argv[3] = env_get("fdt_addr_r");
@ -729,9 +726,6 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
if (!bootm_argv[3])
bootm_argv[3] = env_get("fdt_addr");
if (!bootm_argv[3])
bootm_argv[3] = env_get("fdtcontroladdr");
if (bootm_argv[3]) {
if (!bootm_argv[2])
bootm_argv[2] = "-";

28
cmd/mtd.c
View File

@ -434,19 +434,31 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc,
erase_op.mtd = mtd;
erase_op.addr = off;
erase_op.len = mtd->erasesize;
erase_op.scrub = scrub;
while (len) {
ret = mtd_erase(mtd, &erase_op);
if (!scrub) {
ret = mtd_block_isbad(mtd, erase_op.addr);
if (ret < 0) {
printf("Failed to get bad block at 0x%08llx\n",
erase_op.addr);
ret = CMD_RET_FAILURE;
goto out_put_mtd;
}
if (ret) {
/* Abort if its not a bad block error */
if (ret != -EIO)
break;
printf("Skipping bad block at 0x%08llx\n",
erase_op.addr);
if (ret > 0) {
printf("Skipping bad block at 0x%08llx\n",
erase_op.addr);
ret = 0;
len -= mtd->erasesize;
erase_op.addr += mtd->erasesize;
continue;
}
}
ret = mtd_erase(mtd, &erase_op);
if (ret && ret != -EIO)
break;
len -= mtd->erasesize;
erase_op.addr += mtd->erasesize;
}

14
cmd/nand.c
View File

@ -417,12 +417,14 @@ static void nand_print_and_set_info(int idx)
printf("%dx ", chip->numchips);
printf("%s, sector size %u KiB\n",
mtd->name, mtd->erasesize >> 10);
printf(" Page size %8d b\n", mtd->writesize);
printf(" OOB size %8d b\n", mtd->oobsize);
printf(" Erase size %8d b\n", mtd->erasesize);
printf(" subpagesize %8d b\n", chip->subpagesize);
printf(" options 0x%08x\n", chip->options);
printf(" bbt options 0x%08x\n", chip->bbt_options);
printf(" Page size %8d b\n", mtd->writesize);
printf(" OOB size %8d b\n", mtd->oobsize);
printf(" Erase size %8d b\n", mtd->erasesize);
printf(" ecc strength %8d bits\n", mtd->ecc_strength);
printf(" ecc step size %8d b\n", mtd->ecc_step_size);
printf(" subpagesize %8d b\n", chip->subpagesize);
printf(" options 0x%08x\n", chip->options);
printf(" bbt options 0x%08x\n", chip->bbt_options);
/* Set geometry info */
env_set_hex("nand_writesize", mtd->writesize);

2
cmd/sound.c
View File

@ -86,5 +86,5 @@ U_BOOT_CMD(
sound, 4, 1, do_sound,
"sound sub-system",
"init - initialise the sound driver\n"
"sound play [len] [freq] - play a sound for len ms at freq hz\n"
"sound play [len [freq]] - play a sound for len ms at freq Hz\n"
);

2
common/spl/Kconfig
View File

@ -691,7 +691,7 @@ config SPL_FS_FAT
config SPL_FS_LOAD_PAYLOAD_NAME
string "File to load for U-Boot from the filesystem"
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING
default "tispl.bin" if SYS_K3_SPL_ATF
default "u-boot.itb" if SPL_LOAD_FIT
default "u-boot.img"

4
common/spl/spl_legacy.c
View File

@ -106,7 +106,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image,
* is set
*/
if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
dataptr += sizeof(hdr);
dataptr += sizeof(*hdr);
load->read(load, dataptr, spl_image->size,
(void *)(unsigned long)spl_image->load_addr);
@ -116,7 +116,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image,
lzma_len = LZMA_LEN;
/* dataptr points to compressed payload */
dataptr = offset + sizeof(hdr);
dataptr = offset + sizeof(*hdr);
debug("LZMA: Decompressing %08lx to %08lx\n",
dataptr, spl_image->load_addr);

1
configs/A10-OLinuXino-Lime_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

2
configs/A10s-OLinuXino-M_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MMC1_CD_PIN="PG13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
@ -17,6 +16,5 @@ CONFIG_SYS_I2C_SPEED=400000
CONFIG_MII=y
CONFIG_SUN4I_EMAC=y
CONFIG_AXP152_POWER=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

1
configs/A13-OLinuXinoM_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000

1
configs/A13-OLinuXino_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y

1
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y

1
configs/A20-OLinuXino-Lime2_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y

1
configs/A20-OLinuXino-Lime_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A20-OLinuXino_MICRO_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A20-Olimex-SOM-EVB_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A20-Olimex-SOM204-EVB_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/A33-OLinuXino_defconfig
View File

@ -16,6 +16,5 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y

1
configs/Ainol_AW1_defconfig
View File

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Ampe_A76_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Auxtek-T003_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Auxtek-T004_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Bananapi_M2_Ultra_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_USB2_VBUS_PIN="PH23"
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Bananapi_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y

1
configs/Bananapi_m2m_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

1
configs/Bananapro_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y

1
configs/CHIP_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_CHIP_DIP_SCAN=y
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_DFU_RAM=y

1
configs/CHIP_pro_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y

1
configs/CSQ_CS908_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

1
configs/Chuwi_V7_CW0825_defconfig
View File

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Colombus_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PM1"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Cubieboard2_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Cubieboard4_defconfig
View File

@ -12,6 +12,5 @@ CONFIG_USB0_ID_DET="PH16"
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y

1
configs/Cubieboard_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Cubietruck_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y

1
configs/Cubietruck_plus_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_USB2_VBUS_PIN="PL6"
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y

1
configs/Empire_electronix_d709_defconfig
View File

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Empire_electronix_m712_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Hummingbird_A31_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y

1
configs/Hyundai_A7HD_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Itead_Ibox_A20_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Lamobo_R1_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Linksprite_pcDuino3_Nano_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_SATAPWR="PH2"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Linksprite_pcDuino3_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=122
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Linksprite_pcDuino_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/MK808C_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/MSI_Primo73_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/MSI_Primo81_defconfig
View File

@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y

1
configs/Marsboard_A10_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y

1
configs/Mele_A1000G_quad_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

1
configs/Mele_A1000_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Mele_I7_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

1
configs/Mele_M3_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Mele_M5_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Mele_M9_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

1
configs/Merrii_A80_Optimus_defconfig
View File

@ -12,6 +12,5 @@ CONFIG_USB0_ID_DET="PH3"
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y

1
configs/Mini-X_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f

1
configs/Nintendo_NES_Classic_Edition_defconfig
View File

@ -9,7 +9,6 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set

1
configs/Orangepi_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Orangepi_mini_defconfig
View File

@ -14,7 +14,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y

1
configs/Sinlinx_SinA31s_defconfig
View File

@ -10,7 +10,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y

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