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ARM: exynos: fix regression for Origen4210

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The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Thomas Abraham 2015-08-03 17:58:01 +05:30 committed by Minkyu Kang
parent 77b55e8cfc
commit 14a66afead
2 changed files with 2 additions and 4 deletions
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2
arch/arm/mach-exynos/common_setup.h
View File

@ -60,7 +60,7 @@ enum l2_cache_params {
};
#ifndef CONFIG_SYS_L2CACHE_OFF
#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
/*
* Configure L2CTLR to get timings that keep us from hanging/crashing.
*

4
arch/arm/mach-exynos/lowlevel_init.c
View File

@ -175,7 +175,7 @@ int do_lowlevel_init(void)
arch_cpu_init();
#ifndef CONFIG_SYS_L2CACHE_OFF
#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
/*
* Init L2 cache parameters here for use by boot and resume
*
@ -188,9 +188,7 @@ int do_lowlevel_init(void)
configure_l2_actlr();
dsb();
isb();
#endif
#ifdef CONFIG_EXYNOS5420
relocate_wait_code();
/* Reconfigure secondary cores */