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Merge branch 'master' of git://git.denx.de/u-boot-arm

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* 'master' of git://git.denx.de/u-boot-arm:
  tegra2: Optimize out-of-tree build for Ventana.
  tegra: Move boards over to use arch-level board UART function
  tegra: Add support for UART init in cpu board.c
  tegra: Add a function mux feature
  tegra: add clock_ll_start_uart() to enable UART prior to reloc
  tegra: Move clock_early_init() to arch_cpu_init()
  tegra: Move cpu_init_cp15() to arch_cpu_init()
  arm: Tegra: Fix Harmony and Ventana builds in u-boot-tegra/master
  tegra: Fix build error in plutux, medcom
  tegra2: Add Avionic Design Medcom support.
  tegra2: Add Avionic Design Plutux support.
  tegra2: Add common Avionic Design Tamonten support.
  tegra2: Move tegra2_mmc_init() prototype to public header.
  tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000.
  tegra2: Always build with USE_PRIVATE_LIBGCC=yes.
  tegra2: Plumb in SPI/UART switch code
  tegra2: spi: Support SPI / UART switch
  tegra2: Implement SPI / UART GPIO switch
  tegra2: Enable SPI environment on Seaboard
  tegra2: config: Enable SPI flash on Seaboard
  tegra2: spi: Add SPI driver for Tegra2 SOC
  tegra2: Add UARTB support
  tegra2: Tidy UART selection
  arm, davinci: Fix build warnings for cam_enc_4xx
  Devkit8000: Switch over to enable_gpmc_cs_config
  arm, davinci: Add support for generating AIS images to the Makefile
  mkimage: Fix variable length header support
  arm, da850evm: Add an SPL for SPI boot
  arm, davinci: Add SPL support for DA850 SoCs
  sf: Add spi_boot() to allow booting from SPI flash in an SPL
  spl: display_options.o is required for SPI flash support in SPL
  ARM: omap3: add support to Technexion twister board
  ARM: omap3: added common configuration for Technexion TAM3517
  vision2: Fix checkpatch warning
This commit is contained in:
Wolfgang Denk
2012-01-05 16:38:50 +01:00
parent 72ebafbe2b a747cc0a8c
commit 145afab32c
59 changed files with 2687 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@@ -35,6 +35,7 @@
/u-boot.dis /u-boot.dis
/u-boot.lds /u-boot.lds
/u-boot.ubl /u-boot.ubl
/u-boot.ais
/u-boot.dtb /u-boot.dtb
/u-boot.sb /u-boot.sb

6
MAINTAINERS
View File

@@ -572,6 +572,7 @@ Stefano Babic <sbabic@denx.de>
mx51evk i.MX51 mx51evk i.MX51
polaris xscale/pxa polaris xscale/pxa
trizepsiv xscale/pxa trizepsiv xscale/pxa
twister omap3
vision2 i.MX51 vision2 i.MX51
Jason Liu <r64343@freescale.com> Jason Liu <r64343@freescale.com>
@@ -782,6 +783,11 @@ Stelian Pop <stelian@popies.net>
at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
at91sam9rlek ARM926EJS (AT91SAM9RL SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
Thierry Reding <thierry.reding@avionic-design.de>
plutux Tegra2 (ARM7 & A9 Dual Core)
medcom Tegra2 (ARM7 & A9 Dual Core)
Tom Rini <trini@ti.com> Tom Rini <trini@ti.com>
omap3_evm ARM ARMV7 (OMAP3xx SoC) omap3_evm ARM ARMV7 (OMAP3xx SoC)

13
Makefile
View File

@@ -429,6 +429,18 @@ $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
rm $(obj)u-boot-ubl.bin rm $(obj)u-boot-ubl.bin
rm $(obj)spl/u-boot-spl-pad.bin rm $(obj)spl/u-boot-spl-pad.bin
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(obj)tools/mkimage -s -n /dev/null -T aisimage \
-e $(CONFIG_SPL_TEXT_BASE) \
-d $(obj)spl/u-boot-spl.bin \
$(obj)spl/u-boot-spl.ais
$(OBJCOPY) ${OBJCFLAGS} -I binary \
--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
$(obj)u-boot.ais
rm $(obj)spl/u-boot-spl{,-pad}.ais
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb -o $(obj)u-boot.sb
@@ -762,6 +774,7 @@ clobber: tidy
@rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb @rm -f $(obj)u-boot.sb
@rm -f $(obj)tools/inca-swap-bytes @rm -f $(obj)tools/inca-swap-bytes

3
arch/arm/cpu/arm926ejs/davinci/Makefile
View File

@@ -38,7 +38,8 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_BUILD
COBJS-y += spl.o COBJS-y += spl.o
COBJS-y += dm365_lowlevel.o COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif endif
SOBJS = reset.o SOBJS = reset.o

35
arch/arm/cpu/arm926ejs/davinci/spl.c
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@@ -26,6 +26,17 @@
#include <nand.h> #include <nand.h>
#include <asm/arch/dm365_lowlevel.h> #include <asm/arch/dm365_lowlevel.h>
#include <ns16550.h> #include <ns16550.h>
#include <malloc.h>
#include <spi_flash.h>
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
DECLARE_GLOBAL_DATA_PTR;
/* Define global data structure pointer to it*/
static gd_t gdata __attribute__ ((section(".data")));
static bd_t bdata __attribute__ ((section(".data")));
#else
void puts(const char *str) void puts(const char *str)
{ {
@@ -41,6 +52,8 @@ void putc(char c)
NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c); NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
} }
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
inline void hang(void) inline void hang(void)
{ {
puts("### ERROR ### Please RESET the board ###\n"); puts("### ERROR ### Please RESET the board ###\n");
@@ -50,14 +63,34 @@ inline void hang(void)
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0); dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
} }
void board_init_r(gd_t *id, ulong dummy) void board_init_r(gd_t *id, ulong dummy)
{ {
#ifdef CONFIG_SOC_DM365
nand_init(); nand_init();
puts("Nand boot...\n"); puts("Nand boot...\n");
nand_boot(); nand_boot();
#endif
#ifdef CONFIG_SOC_DA8XX
mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
gd = &gdata;
gd->bd = &bdata;
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
gd->have_console = 1;
puts("SPI boot...\n");
spi_boot();
#endif
} }

2
arch/arm/cpu/armv7/tegra2/Makefile
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@@ -33,7 +33,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o SOBJS := lowlevel_init.o
COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

58
arch/arm/cpu/armv7/tegra2/board.c
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@@ -24,12 +24,22 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#include "ap20.h" #include "ap20.h"
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/arch/tegra2.h> #include <asm/arch/tegra2.h>
#include <asm/arch/pmc.h> #include <asm/arch/pmc.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
enum {
/* UARTs which we can enable */
UARTA = 1 << 0,
UARTB = 1 << 1,
UARTD = 1 << 3,
UART_COUNT = 4,
};
/* /*
* Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
* so we are using this value to identify memory size. * so we are using this value to identify memory size.
@@ -80,6 +90,54 @@ int arch_cpu_init(void)
{ {
/* Fire up the Cortex A9 */ /* Fire up the Cortex A9 */
tegra2_start(); tegra2_start();
/* We didn't do this init in start.S, so do it now */
cpu_init_cp15();
/* Initialize essential common plls */
clock_early_init();
return 0; return 0;
} }
#endif #endif
/**
* Set up the specified uarts
*
* @param uarts_ids Mask containing UARTs to init (UARTx)
*/
static void setup_uarts(int uart_ids)
{
static enum periph_id id_for_uart[] = {
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_UART4,
};
size_t i;
for (i = 0; i < UART_COUNT; i++) {
if (uart_ids & (1 << i)) {
enum periph_id id = id_for_uart[i];
funcmux_select(id, 0);
clock_ll_start_uart(id);
}
}
}
void board_init_uart_f(void)
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA2_ENABLE_UARTA
uart_ids |= UARTA;
#endif
#ifdef CONFIG_TEGRA2_ENABLE_UARTB
uart_ids |= UARTB;
#endif
#ifdef CONFIG_TEGRA2_ENABLE_UARTD
uart_ids |= UARTD;
#endif
setup_uarts(uart_ids);
}

14
arch/arm/cpu/armv7/tegra2/clock.c
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@@ -904,6 +904,20 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
return 0; return 0;
} }
void clock_ll_start_uart(enum periph_id periph_id)
{
/* Assert UART reset and enable clock */
reset_set_enable(periph_id, 1);
clock_enable(periph_id);
clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(periph_id, 0);
}
int clock_verify(void) int clock_verify(void)
{ {
struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);

2
arch/arm/cpu/armv7/tegra2/config.mk
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@@ -29,3 +29,5 @@
ifdef CONFIG_TEGRA2 ifdef CONFIG_TEGRA2
CFLAGS_arch/arm/lib/board.o += -march=armv4t CFLAGS_arch/arm/lib/board.o += -march=armv4t
endif endif
USE_PRIVATE_LIBGCC = yes

58
arch/arm/cpu/armv7/tegra2/funcmux.c Normal file
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@@ -0,0 +1,58 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
int funcmux_select(enum periph_id id, int config)
{
if (config != 0) {
debug("%s: invalid config %d for periph_id %d", __func__,
config, id);
return -1;
}
switch (id) {
case PERIPH_ID_UART1:
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
break;
case PERIPH_ID_UART2:
pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
pinmux_tristate_disable(PINGRP_UAD);
break;
case PERIPH_ID_UART4:
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PINGRP_GMC);
break;
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
}
return 0;
}

30
arch/arm/include/asm/arch-tegra2/board.h Normal file
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@@ -0,0 +1,30 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA_BOARD_H_
#define _TEGRA_BOARD_H_
/* Setup UARTs for the board according to the selected config */
void board_init_uart_f(void);
#endif

11
arch/arm/include/asm/arch-tegra2/clock.h
View File

@@ -344,6 +344,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
*/ */
unsigned clock_get_rate(enum clock_id clkid); unsigned clock_get_rate(enum clock_id clkid);
/**
* Start up a UART using low-level calls
*
* Prior to relocation clock_start_periph_pll() cannot be called. This
* function provides a way to set up a UART using low-level calls which
* do not require BSS.
*
* @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
*/
void clock_ll_start_uart(enum periph_id periph_id);
/* /*
* Checks that clocks are valid and prints a warning if not * Checks that clocks are valid and prints a warning if not
* *

41
arch/arm/include/asm/arch-tegra2/funcmux.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 high-level function multiplexing */
#ifndef __FUNCMUX_H
#define __FUNCMUX_H
/**
* Select a config for a particular peripheral.
*
* Each peripheral can operate through a number of configurations,
* which are sets of pins that it uses to bring out its signals.
* The basic config is 0, and higher numbers indicate different
* pinmux settings to bring the peripheral out on other pins,
*
* @param id Peripheral id
* @param config Configuration to use (generally 0)
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
*/
int funcmux_select(enum periph_id id, int config);
#endif

27
arch/arm/include/asm/arch-tegra2/mmc.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (c) 2011, Google Inc. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA2_MMC_H_
#define _TEGRA2_MMC_H_
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
#endif /* TEGRA2_MMC_H_ */

1
arch/arm/include/asm/arch-tegra2/tegra2.h
View File

@@ -38,6 +38,7 @@
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
#define NV_PA_PMC_BASE 0x7000E400 #define NV_PA_PMC_BASE 0x7000E400
#define NV_PA_CSITE_BASE 0x70040000 #define NV_PA_CSITE_BASE 0x70040000

76
arch/arm/include/asm/arch-tegra2/tegra2_spi.h Normal file
View File

@@ -0,0 +1,76 @@
/*
* NVIDIA Tegra2 SPI-FLASH controller
*
* Copyright 2010-2011 NVIDIA Corporation
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA2_SPI_H_
#define _TEGRA2_SPI_H_
#include <asm/types.h>
struct spi_tegra {
u32 command; /* SPI_COMMAND_0 register */
u32 status; /* SPI_STATUS_0 register */
u32 rx_cmp; /* SPI_RX_CMP_0 register */
u32 dma_ctl; /* SPI_DMA_CTL_0 register */
u32 tx_fifo; /* SPI_TX_FIFO_0 register */
u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
u32 rx_fifo; /* SPI_RX_FIFO_0 register */
};
#define SPI_CMD_GO (1 << 30)
#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
#define SPI_CMD_CK_SDA (1 << 21)
#define SPI_CMD_ACTIVE_SDA_SHIFT 18
#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
#define SPI_CMD_CS_POL (1 << 16)
#define SPI_CMD_TXEN (1 << 15)
#define SPI_CMD_RXEN (1 << 14)
#define SPI_CMD_CS_VAL (1 << 13)
#define SPI_CMD_CS_SOFT (1 << 12)
#define SPI_CMD_CS_DELAY (1 << 9)
#define SPI_CMD_CS3_EN (1 << 8)
#define SPI_CMD_CS2_EN (1 << 7)
#define SPI_CMD_CS1_EN (1 << 6)
#define SPI_CMD_CS0_EN (1 << 5)
#define SPI_CMD_BIT_LENGTH (1 << 4)
#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
#define SPI_STAT_BSY (1 << 31)
#define SPI_STAT_RDY (1 << 30)
#define SPI_STAT_RXF_FLUSH (1 << 29)
#define SPI_STAT_TXF_FLUSH (1 << 28)
#define SPI_STAT_RXF_UNR (1 << 27)
#define SPI_STAT_TXF_OVF (1 << 26)
#define SPI_STAT_RXF_EMPTY (1 << 25)
#define SPI_STAT_RXF_FULL (1 << 24)
#define SPI_STAT_TXF_EMPTY (1 << 23)
#define SPI_STAT_TXF_FULL (1 << 22)
#define SPI_STAT_SEL_TXRX_N (1 << 16)
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_TIMEOUT 1000
#define TEGRA2_SPI_MAX_FREQ 52000000
#endif /* _TEGRA2_SPI_H_ */

46
arch/arm/include/asm/arch-tegra2/uart-spi-switch.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _UART_SPI_SWITCH_H
#define _UART_SPI_SWITCH_H
#if defined(CONFIG_SPI_UART_SWITCH)
/*
* Signal that we are about to use the UART. This unfortunate hack is
* required by Seaboard, which cannot use its console and SPI at the same
* time! If the board file provides this, the board config will declare it.
* Let this be a lesson for others.
*/
void pinmux_select_uart(NS16550_t regs);
/*
* Signal that we are about the use the SPI bus.
*/
void pinmux_select_spi(void);
#else /* not CONFIG_SPI_UART_SWITCH */
static inline void pinmux_select_uart(NS16550_t regs) {}
static inline void pinmux_select_spi(void) {}
#endif
#endif

116
board/avionic-design/common/tamonten.c Normal file
View File

@@ -0,0 +1,116 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/board.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart.h>
#include <asm/arch/mmc.h>
#include "tamonten.h"
#ifdef CONFIG_TEGRA2_MMC
#include <mmc.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
const struct tegra2_sysinfo sysinfo = {
CONFIG_TEGRA2_BOARD_STRING
};
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
*/
int timer_init(void)
{
return 0;
}
#ifdef CONFIG_TEGRA2_MMC
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
{
/* SDMMC4: config 3, x8 on 2nd set of pins */
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATB);
pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PINGRP_GME);
}
#endif
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
clock_init();
clock_verify();
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
return 0;
}
#ifdef CONFIG_TEGRA2_MMC
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
gpio_config_mmc();
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
tegra2_mmc_init(0, 4, -1, GPIO_PH2);
return 0;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
/* Initialize selected UARTs */
board_init_uart_f();
return 0;
}
#endif /* EARLY_INIT */

32
board/avionic-design/common/tamonten.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TAMONTEN_H_
#define _TAMONTEN_H_
void tegra2_start(void);
void gpio_config_mmc(void);
#endif /* TAMONTEN_H */

50
board/avionic-design/medcom/Makefile Normal file
View File

@@ -0,0 +1,50 @@
#
# (C) Copyright 2010,2011
# NVIDIA Corporation <www.nvidia.com>
# (C) Copyright 2011
# Avionic Design GmbH <www.avionic-design.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
COBJS += ../common/tamonten.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

45
board/avionic-design/medcom/medcom.c Normal file
View File

@@ -0,0 +1,45 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/tegra2.h>
#ifdef CONFIG_TEGRA2_MMC
#include <mmc.h>
#endif
#ifdef CONFIG_TEGRA2_MMC
/*
* Routine: gpio_config_mmc
* Description: Set GPIOs for SD card
*/
void gpio_config_mmc(void)
{
/* configure pin as input for card detect */
gpio_request(GPIO_PH2, "SD4 CD");
gpio_direction_input(GPIO_PH2);
}
#endif

50
board/avionic-design/plutux/Makefile Normal file
View File

@@ -0,0 +1,50 @@
#
# (C) Copyright 2010,2011
# NVIDIA Corporation <www.nvidia.com>
# (C) Copyright 2011
# Avionic Design GmbH <www.avionic-design.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
COBJS += ../common/tamonten.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

45
board/avionic-design/plutux/plutux.c Normal file
View File

@@ -0,0 +1,45 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/tegra2.h>
#ifdef CONFIG_TEGRA2_MMC
#include <mmc.h>
#endif
#ifdef CONFIG_TEGRA2_MMC
/*
* Routine: gpio_config_mmc
* Description: Set GPIOs for SD card
*/
void gpio_config_mmc(void)
{
/* configure pin as input for card detect */
gpio_request(GPIO_PH2, "SD4 CD");
gpio_direction_input(GPIO_PH2);
}
#endif

4
board/davinci/da8xxevm/da850evm.c
View File

@@ -108,7 +108,7 @@ static const struct pinmux_config gpio_pins[] = {
#endif #endif
}; };
static const struct pinmux_resource pinmuxes[] = { const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_DRIVER_TI_EMAC #ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio), PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
@@ -135,6 +135,8 @@ static const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(gpio_pins), PINMUX_ITEM(gpio_pins),
}; };
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
static const struct lpsc_resource lpsc[] = { static const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */

73
board/davinci/da8xxevm/u-boot-spl.lds Normal file
View File

@@ -0,0 +1,73 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
__start = .;
arch/arm/cpu/arm926ejs/start.o (.text)
*(.text*)
} >.sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
} >.sram
.dynsym : {
__dynsym_start = .;
*(.dynsym)
} >.sram
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end__ = .;
} >.sram
__image_copy_end = .;
_end = .;
}

47
board/nvidia/common/Makefile Normal file
View File

@@ -0,0 +1,47 @@
# Copyright (c) 2011 The Chromium OS Authors.
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
LIB = $(obj)lib$(VENDOR).o
COBJS-y += board.o
COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

73
board/nvidia/common/board.c
View File

@@ -27,10 +27,12 @@
#include <asm/arch/tegra2.h> #include <asm/arch/tegra2.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/arch/board.h>
#include <asm/arch/clk_rst.h> #include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/pinmux.h> #include <asm/arch/pinmux.h>
#include <asm/arch/uart.h> #include <asm/arch/uart.h>
#include <spi.h>
#include "board.h" #include "board.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@@ -48,63 +50,22 @@ int timer_init(void)
return 0; return 0;
} }
static void enable_uart(enum periph_id pid)
{
/* Assert UART reset and enable clock */
reset_set_enable(pid, 1);
clock_enable(pid);
clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(pid, 0);
}
/*
* Routine: clock_init_uart
* Description: init the PLL and clock for the UART(s)
*/
static void clock_init_uart(void)
{
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
enable_uart(PERIPH_ID_UART1);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
enable_uart(PERIPH_ID_UART4);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
/*
* Routine: pin_mux_uart
* Description: setup the pin muxes/tristate values for the UART(s)
*/
static void pin_mux_uart(void)
{
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PINGRP_GMC);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
/* /*
* Routine: board_init * Routine: board_init
* Description: Early hardware init. * Description: Early hardware init.
*/ */
int board_init(void) int board_init(void)
{ {
/* Do clocks and UART first so that printf() works */
clock_init(); clock_init();
clock_verify(); clock_verify();
#ifdef CONFIG_SPI_UART_SWITCH
gpio_config_uart();
#endif
#ifdef CONFIG_TEGRA2_SPI
spi_init();
#endif
/* boot param addr */ /* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -114,20 +75,14 @@ int board_init(void)
#ifdef CONFIG_BOARD_EARLY_INIT_F #ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* We didn't do this init in start.S, so do it now */ board_init_uart_f();
cpu_init_cp15();
/* Initialize essential common plls */
clock_early_init();
/* Initialize UART clocks */
clock_init_uart();
/* Initialize periph pinmuxes */
pin_mux_uart();
/* Initialize periph GPIOs */ /* Initialize periph GPIOs */
#ifdef CONFIG_SPI_UART_SWITCH
gpio_early_init_uart();
#else
gpio_config_uart(); gpio_config_uart();
#endif
return 0; return 0;
} }
#endif /* EARLY_INIT */ #endif /* EARLY_INIT */

2
board/nvidia/common/board.h
View File

@@ -25,6 +25,6 @@
#define _BOARD_H_ #define _BOARD_H_
void gpio_config_uart(void); void gpio_config_uart(void);
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); void gpio_early_init_uart(void);
#endif /* BOARD_H */ #endif /* BOARD_H */

138
board/nvidia/common/uart-spi-switch.c Normal file
View File

@@ -0,0 +1,138 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ns16550.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/tegra2_spi.h>
/* position of the UART/SPI select switch */
enum spi_uart_switch {
SWITCH_UNKNOWN,
SWITCH_SPI,
SWITCH_UART,
SWITCH_BOTH
};
/* Information about the spi/uart switch */
struct spi_uart {
int gpio; /* GPIO to control switch */
NS16550_t regs; /* Address of UART affected */
u32 port; /* Port number of UART affected */
};
static struct spi_uart local;
static enum spi_uart_switch switch_pos; /* Current switch position */
static void get_config(struct spi_uart *config)
{
#if defined CONFIG_SPI_CORRUPTS_UART
config->gpio = CONFIG_UART_DISABLE_GPIO;
config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART;
config->port = CONFIG_SPI_CORRUPTS_UART_NR;
#else
config->gpio = -1;
#endif
}
/*
* Init the UART / SPI switch. This can be called before relocation so we must
* not access BSS.
*/
void gpio_early_init_uart(void)
{
struct spi_uart config;
get_config(&config);
if (config.gpio != -1) {
/* Cannot provide a label prior to relocation */
gpio_request(config.gpio, NULL);
gpio_direction_output(config.gpio, 0);
}
}
/*
* Configure the UART / SPI switch.
*/
void gpio_config_uart(void)
{
get_config(&local);
if (local.gpio != -1) {
gpio_direction_output(local.gpio, 0);
switch_pos = SWITCH_UART;
} else {
/*
* If we're here we don't have a SPI switch; go ahead and
* enable the SPI now. We didn't in spi_init() so we wouldn't
* kill the UART.
*/
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
switch_pos = SWITCH_BOTH;
}
}
static void spi_uart_switch(struct spi_uart *config,
enum spi_uart_switch new_pos)
{
if (switch_pos == SWITCH_BOTH || new_pos == switch_pos)
return;
/* if the UART was selected, allow it to drain */
if (switch_pos == SWITCH_UART)
NS16550_drain(config->regs, config->port);
/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ?
PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD);
/*
* On Seaboard, MOSI/MISO are shared w/UART.
* Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
* Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
*/
gpio_direction_output(config->gpio, new_pos == SWITCH_SPI);
switch_pos = new_pos;
/* if the SPI was selected, clear any junk bytes in the UART */
if (switch_pos == SWITCH_UART) {
/* TODO: What if it is part-way through clocking in junk? */
udelay(100);
NS16550_clear(config->regs, config->port);
}
}
void pinmux_select_uart(NS16550_t regs)
{
/* Also prevents calling spi_uart_switch() before relocation */
if (regs == local.regs)
spi_uart_switch(&local, SWITCH_UART);
}
void pinmux_select_spi(void)
{
spi_uart_switch(&local, SWITCH_SPI);
}

1
board/nvidia/harmony/Makefile
View File

@@ -31,7 +31,6 @@ endif
LIB = $(obj)lib$(BOARD).o LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

2
board/nvidia/harmony/harmony.c
View File

@@ -25,11 +25,11 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/tegra2.h> #include <asm/arch/tegra2.h>
#include <asm/arch/pinmux.h> #include <asm/arch/pinmux.h>
#include <asm/arch/mmc.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#ifdef CONFIG_TEGRA2_MMC #ifdef CONFIG_TEGRA2_MMC
#include <mmc.h> #include <mmc.h>
#endif #endif
#include "../common/board.h"
/* /*
* Routine: gpio_config_uart * Routine: gpio_config_uart

1
board/nvidia/seaboard/Makefile
View File

@@ -31,7 +31,6 @@ endif
LIB = $(obj)lib$(BOARD).o LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o COBJS := $(BOARD).o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

5
board/nvidia/seaboard/seaboard.c
View File

@@ -25,12 +25,14 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/tegra2.h> #include <asm/arch/tegra2.h>
#include <asm/arch/pinmux.h> #include <asm/arch/pinmux.h>
#include <asm/arch/mmc.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#ifdef CONFIG_TEGRA2_MMC #ifdef CONFIG_TEGRA2_MMC
#include <mmc.h> #include <mmc.h>
#endif #endif
#include "../common/board.h"
/* TODO: Remove this code when the SPI switch is working */
#ifndef CONFIG_SPI_UART_SWITCH
/* /*
* Routine: gpio_config_uart_seaboard * Routine: gpio_config_uart_seaboard
* Description: Force GPIO_PI3 low on Seaboard so UART4 works. * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
@@ -48,6 +50,7 @@ void gpio_config_uart(void)
return; return;
gpio_config_uart_seaboard(); gpio_config_uart_seaboard();
} }
#endif
#ifdef CONFIG_TEGRA2_MMC #ifdef CONFIG_TEGRA2_MMC
/* /*

6
board/nvidia/ventana/Makefile
View File

@@ -25,14 +25,12 @@
include $(TOPDIR)/config.mk include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE)) ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../seaboard) $(shell mkdir -p $(obj)../common $(obj)../seaboard)
$(shell mkdir -p $(obj)../common)
endif endif
LIB = $(obj)lib$(BOARD).o LIB = $(obj)lib$(BOARD).o
COBJS += ../seaboard/seaboard.o COBJS = ../seaboard/seaboard.o
COBJS += ../common/board.o
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

38
board/technexion/twister/Makefile Normal file
View File

@@ -0,0 +1,38 @@
#
# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
#
# Based on ti/evm/Makefile
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend

116
board/technexion/twister/twister.c Normal file
View File

@@ -0,0 +1,116 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
#include <asm/gpio.h>
#include "twister.h"
DECLARE_GLOBAL_DATA_PTR;
/* Timing definitions for Ethernet Controller */
static const u32 gpmc_smc911[] = {
NET_GPMC_CONFIG1,
NET_GPMC_CONFIG2,
NET_GPMC_CONFIG3,
NET_GPMC_CONFIG4,
NET_GPMC_CONFIG5,
NET_GPMC_CONFIG6,
};
static const u32 gpmc_XR16L2751[] = {
XR16L2751_GPMC_CONFIG1,
XR16L2751_GPMC_CONFIG2,
XR16L2751_GPMC_CONFIG3,
XR16L2751_GPMC_CONFIG4,
XR16L2751_GPMC_CONFIG5,
XR16L2751_GPMC_CONFIG6,
};
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
/* Chip select 1 and 3 are used for XR16L2751 UART controller */
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
XR16L2751_UART1_BASE, GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
XR16L2751_UART2_BASE, GPMC_SIZE_16M);
gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
return 0;
}
int misc_init_r(void)
{
dieid_num_r();
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_TWISTER();
}
int board_eth_init(bd_t *bis)
{
davinci_emac_initialize();
/* init cs for extern lan */
enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
printf("\nError initializing SMC911x controlleri\n");
return 0;
}
#if defined(CONFIG_OMAP_HSMMC) && \
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0);
}
#endif

411
board/technexion/twister/twister.h Normal file
View File

@@ -0,0 +1,411 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2010 TechNexion Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef _TAM3517_H_
#define _TAM3517_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"TAM3517 TWISTER Board",
"NAND",
};
#define XR16L2751_GPMC_CONFIG1 0x00000000
#define XR16L2751_GPMC_CONFIG2 0x001e1e01
#define XR16L2751_GPMC_CONFIG3 0x00080300
#define XR16L2751_GPMC_CONFIG4 0x1c091c09
#define XR16L2751_GPMC_CONFIG5 0x04181f1f
#define XR16L2751_GPMC_CONFIG6 0x00000FCF
#define XR16L2751_UART1_BASE 0x21000000
#define XR16L2751_UART2_BASE 0x23000000
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_TWISTER() \
/* SDRC */\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SDRC_CKE0), (M0)) \
MUX_VAL(CP(SDRC_CKE1), (M0)) \
MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\
MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\
/* GPMC */\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
/* MMC */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
/* CardDetect */\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
/* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
/* Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
/* - VIO_1V8*/\
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
/* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
/* hsusb1_dir */\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
/* hsusb1_nxt */\
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
#endif

19
board/timll/devkit8000/devkit8000.c
View File

@@ -48,6 +48,16 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
static u32 gpmc_net_config[GPMC_MAX_REG] = {
NET_GPMC_CONFIG1,
NET_GPMC_CONFIG2,
NET_GPMC_CONFIG3,
NET_GPMC_CONFIG4,
NET_GPMC_CONFIG5,
NET_GPMC_CONFIG6,
0
};
/* /*
* Routine: board_init * Routine: board_init
* Description: Early hardware init. * Description: Early hardware init.
@@ -82,13 +92,8 @@ int misc_init_r(void)
#ifdef CONFIG_DRIVER_DM9000 #ifdef CONFIG_DRIVER_DM9000
/* Configure GPMC registers for DM9000 */ /* Configure GPMC registers for DM9000 */
writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1); enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2); CONFIG_DM9000_BASE, GPMC_SIZE_16M);
writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
/* Use OMAP DIE_ID as MAC address */ /* Use OMAP DIE_ID as MAC address */
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {

3
board/ttcontrol/vision2/vision2.c
View File

@@ -428,9 +428,8 @@ static void setup_gpios(void)
gpio_direction_output(4, 1); gpio_direction_output(4, 1);
gpio_direction_output(7, 0); gpio_direction_output(7, 0);
for (i = 65; i < 71; i++) { for (i = 65; i < 71; i++)
gpio_direction_output(i, 0); gpio_direction_output(i, 0);
}
gpio_direction_output(94, 0); gpio_direction_output(94, 0);

3
boards.cfg
View File

@@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti
omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_evm_quick_nand arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3
devkit8000 arm armv7 devkit8000 timll omap3 devkit8000 arm armv7 devkit8000 timll omap3
twister arm armv7 twister technexion omap3
omap4_panda arm armv7 panda ti omap4 omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4
omap5_evm arm armv7 omap5_evm ti omap5 omap5_evm arm armv7 omap5_evm ti omap5
@@ -244,6 +245,8 @@ xaeniax arm pxa
zipitz2 arm pxa zipitz2 arm pxa
colibri_pxa270 arm pxa - toradex colibri_pxa270 arm pxa - toradex
jornada arm sa1100 jornada arm sa1100
plutux arm armv7 plutux avionic-design tegra2
medcom arm armv7 medcom avionic-design tegra2
atngw100 avr32 at32ap - atmel at32ap700x atngw100 avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x

1
doc/README.SPL
View File

@@ -65,3 +65,4 @@ CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)

9
doc/README.davinci
View File

@@ -95,6 +95,15 @@ into the RAM.
The programmers and UBL are always released as part of any standard TI The programmers and UBL are always released as part of any standard TI
software release associated with an SOC. software release associated with an SOC.
Alternative boot method (DA850 EVM only):
For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
is provided to load U-Boot directly from SPI flash. In this case, the
SPL does the low level initialization that is otherwise done by the SPL.
To build U-Boot with this SPL, do
make da850evm_config
make u-boot.ais
and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM.
Environment Variables Environment Variables
===================== =====================

2
drivers/mmc/tegra2_mmc.h
View File

@@ -127,7 +127,5 @@ struct mmc_host {
int cd_gpio; /* Change Detect GPIO */ int cd_gpio; /* Change Detect GPIO */
}; };
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __TEGRA2_MMC_H_ */ #endif /* __TEGRA2_MMC_H_ */

4
drivers/mtd/spi/Makefile
View File

@@ -25,6 +25,10 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libspi_flash.o LIB := $(obj)libspi_flash.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
endif
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o

58
drivers/mtd/spi/spi_spl_load.c Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (C) 2011 OMICRON electronics GmbH
*
* based on drivers/mtd/nand/nand_spl_load.c
*
* Copyright (C) 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi_flash.h>
/*
* The main entry for SPI booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
* from SPI into SDRAM and starts it from there.
*/
void spi_boot(void)
{
struct spi_flash *flash;
void (*uboot)(void) __noreturn;
/*
* Load U-Boot image from SPI flash into RAM
*/
flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
if (!flash) {
puts("failed.\n");
hang();
}
spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
CONFIG_SYS_SPI_U_BOOT_SIZE,
(void *) CONFIG_SYS_TEXT_BASE);
/*
* Jump to U-Boot image
*/
uboot = (void *) CONFIG_SYS_TEXT_BASE;
(*uboot)();
}

1
drivers/spi/Makefile
View File

@@ -43,6 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
COBJS := $(COBJS-y) COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)

279
drivers/spi/tegra2_spi.c Normal file
View File

@@ -0,0 +1,279 @@
/*
* Copyright (c) 2010-2011 NVIDIA Corporation
* With help from the mpc8xxx SPI driver
* With more help from omap3_spi SPI driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <ns16550.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
#include <asm/arch/tegra2_spi.h>
struct tegra_spi_slave {
struct spi_slave slave;
struct spi_tegra *regs;
unsigned int freq;
unsigned int mode;
};
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
{
return container_of(slave, struct tegra_spi_slave, slave);
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
if (bus != 0 || cs != 0)
return 0;
else
return 1;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct tegra_spi_slave *spi;
if (!spi_cs_is_valid(bus, cs)) {
printf("SPI error: unsupported bus %d / chip select %d\n",
bus, cs);
return NULL;
}
if (max_hz > TEGRA2_SPI_MAX_FREQ) {
printf("SPI error: unsupported frequency %d Hz. Max frequency"
" is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
return NULL;
}
spi = malloc(sizeof(struct tegra_spi_slave));
if (!spi) {
printf("SPI error: malloc of SPI structure failed\n");
return NULL;
}
spi->slave.bus = bus;
spi->slave.cs = cs;
spi->freq = max_hz;
spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
spi->mode = mode;
return &spi->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
free(spi);
}
void spi_init(void)
{
/* do nothing */
}
int spi_claim_bus(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
struct spi_tegra *regs = spi->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
writel(reg, &regs->status);
debug("spi_init: STATUS = %08x\n", readl(&regs->status));
/*
* Use sw-controlled CS, so we can clock in data after ReadID, etc.
*/
reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
if (spi->mode & 2)
reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
/*
* SPI pins on Tegra2 are muxed - change pinmux later due to UART
* issue.
*/
pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_tristate_disable(PINGRP_LSPI);
#ifndef CONFIG_SPI_UART_SWITCH
/*
* NOTE:
* Only set PinMux bits 3:2 to SPI here on boards that don't have the
* SPI UART switch or subsequent UART data won't go out! See
* spi_uart_switch().
*/
/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
#endif
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
/*
* We can't release UART_DISABLE and set pinmux to UART4 here since
* some code (e,g, spi_flash_probe) uses printf() while the SPI
* bus is held. That is arguably bad, but it has the advantage of
* already being in the source tree.
*/
}
void spi_cs_activate(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
pinmux_select_spi();
/* CS is negated on Tegra, so drive a 1 to get a 0 */
setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *data_out, void *data_in, unsigned long flags)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
struct spi_tegra *regs = spi->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
int num_bytes;
int ret;
debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
ret = 0;
reg = readl(&regs->status);
writel(reg, &regs->status); /* Clear all SPI events via R/W */
debug("spi_xfer entry: STATUS = %08x\n", reg);
reg = readl(&regs->command);
reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
writel(reg, &regs->command);
debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
int bytes;
int is_read = 0;
int tm, i;
tmpdout = 0;
bytes = (num_bytes > 4) ? 4 : num_bytes;
if (dout != NULL) {
for (i = 0; i < bytes; ++i)
tmpdout = (tmpdout << 8) | dout[i];
}
num_bytes -= bytes;
if (dout)
dout += bytes;
clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
bytes * 8 - 1);
writel(tmpdout, &regs->tx_fifo);
setbits_le32(&regs->command, SPI_CMD_GO);
/*
* Wait for SPI transmit FIFO to empty, or to time out.
* The RX FIFO status will be read and cleared last
*/
for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
u32 status;
status = readl(&regs->status);
/* We can exit when we've had both RX and TX activity */
if (is_read && (status & SPI_STAT_TXF_EMPTY))
break;
if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
SPI_STAT_RDY)
tm++;
else if (!(status & SPI_STAT_RXF_EMPTY)) {
tmpdin = readl(&regs->rx_fifo);
is_read = 1;
/* swap bytes read in */
if (din != NULL) {
for (i = bytes - 1; i >= 0; --i) {
din[i] = tmpdin & 0xff;
tmpdin >>= 8;
}
din += bytes;
}
}
}
if (tm >= SPI_TIMEOUT)
ret = tm;
/* clear ACK RDY, etc. bits */
writel(readl(&regs->status), &regs->status);
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
tmpdin, readl(&regs->status));
if (ret) {
printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
return -1;
}
return 0;
}

87
include/configs/da850evm.h
View File

@@ -65,6 +65,75 @@
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
DAVINCI_SYSCFG_SUSPSRC_EMAC | \
DAVINCI_SYSCFG_SUSPSRC_I2C)
/*
* PLL configuration
*/
#define CONFIG_SYS_DV_CLKMODE 0
#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(0 << DV_DDR_SDTMR1_WTR_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(0 << DV_DDR_SDTMR2_CKE_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
/* /*
* Serial Driver info * Serial Driver info
*/ */
@@ -76,6 +145,7 @@
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
#define CONFIG_SPI #define CONFIG_SPI
#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH
@@ -242,6 +312,23 @@
#undef CONFIG_CMD_ENV #undef CONFIG_CMD_ENV
#endif #endif
/* defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_SIZE 32768
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
/* additions for new relocation code, must added to all boards */ /* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \

3
include/configs/harmony.h
View File

@@ -58,4 +58,7 @@
#define CONFIG_EFI_PARTITION #define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT #define CONFIG_CMD_FAT
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

64
include/configs/medcom.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Medcom) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ENV_IS_NOWHERE
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_FIT
#define CONFIG_BOOTCOMMAND \
"mmc rescan;" \
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#endif /* __CONFIG_H */

64
include/configs/plutux.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
* (C) Copyright 2011
* Avionic Design GmbH <www.avionic-design.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Plutux) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ENV_IS_NOWHERE
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_FIT
#define CONFIG_BOOTCOMMAND \
"mmc rescan;" \
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#endif /* __CONFIG_H */

20
include/configs/seaboard.h
View File

@@ -37,11 +37,23 @@
#define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_TEGRA2_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_F
/* SPI */
#define CONFIG_TEGRA2_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* SD/MMC */ /* SD/MMC */
#define CONFIG_MMC #define CONFIG_MMC
#define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_MMC
@@ -52,4 +64,12 @@
#define CONFIG_EFI_PARTITION #define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT #define CONFIG_CMD_FAT
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

361
include/configs/tam3517-common.h Normal file
View File

@@ -0,0 +1,361 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef __TAM3517_H
#define __TAM3517_H
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
2 * 1024 * 1024)
/*
* DDR related
*/
#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#define CONFIG_SERIAL1 /* UART1 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_STORAGE
/* #define CONFIG_EHCI_DCACHE */
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#define CONFIG_AUTO_COMPLETE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* AM3517 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* ethernet support, EMAC
*
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM 0
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (45 << 10) /* 45 K */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\
56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
"512k(u-boot),128k(env1)," \
"128k(env2),6m(kernel),-(rootfs)"
#define xstr(s) str(s)
#define str(s) #s
#define CONFIG_TAM3517_SETTINGS \
"netdev=eth0\0" \
"nandargs=setenv bootargs root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip_sta=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
"else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttyO0,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=82000000\0" \
"kernel_addr_r=82000000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr}\0" \
"nandboot=run nandargs addip addtty addmtd addmisc;" \
"nand read ${kernel_addr_r} kernel\0" \
"bootm ${kernel_addr_r}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r}\0" \
"net_self=if run net_self_load;then " \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
"updatemlo=nandecc hw;nand erase 0 20000;" \
"nand write ${loadaddr} 0 20000\0" \
"upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \
"else echo Error updating u-boot !;" \
"echo Board without bootloader !!;" \
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
#endif /* __TAM3517_H */

5
include/configs/tegra2-common.h
View File

@@ -51,8 +51,7 @@
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
/* Environment */ /* Environment */
#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */
/* /*
* Size of malloc() pool * Size of malloc() pool
@@ -152,7 +151,7 @@
#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_TEXT_BASE 0x00E08000 #define CONFIG_SYS_TEXT_BASE 0x00108000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE

54
include/configs/twister.h Normal file
View File

@@ -0,0 +1,54 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2009 TechNexion Ltd.
*
* Configuration for the Technexion twister board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tam3517-common.h"
#define MACH_TYPE_TAM3517 2818
#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517
#define CONFIG_TAM3517_SW3_SETTINGS
#define CONFIG_XR16L2751
#define CONFIG_BOOTDELAY 10
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_HOSTNAME twister
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_PROMPT "twister => "
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#define CONFIG_SMC911X_NO_EEPROM
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run nandboot\0"
#endif /* __CONFIG_H */

3
include/configs/ventana.h
View File

@@ -52,4 +52,7 @@
#define CONFIG_EFI_PARTITION #define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT #define CONFIG_CMD_FAT
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

3
include/spi_flash.h
View File

@@ -25,6 +25,7 @@
#include <spi.h> #include <spi.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/compiler.h>
struct spi_flash { struct spi_flash {
struct spi_slave *spi; struct spi_slave *spi;
@@ -68,4 +69,6 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
return flash->erase(flash, offset, len); return flash->erase(flash, offset, len);
} }
void spi_boot(void) __noreturn;
#endif /* _SPI_FLASH_H_ */ #endif /* _SPI_FLASH_H_ */

2
lib/Makefile
View File

@@ -50,6 +50,8 @@ COBJS-$(CONFIG_SHA1) += sha1.o
COBJS-$(CONFIG_SHA256) += sha256.o COBJS-$(CONFIG_SHA256) += sha256.o
COBJS-y += strmhz.o COBJS-y += strmhz.o
COBJS-$(CONFIG_RBTREE) += rbtree.o COBJS-$(CONFIG_RBTREE) += rbtree.o
else
COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o
endif endif
COBJS-y += ctype.o COBJS-y += ctype.o

97
tools/mkimage.c
View File

@@ -383,65 +383,66 @@ NXTARG: ;
exit (EXIT_FAILURE); exit (EXIT_FAILURE);
} }
if (!params.skipcpy && if (!params.skipcpy) {
(params.type == IH_TYPE_MULTI || if (params.type == IH_TYPE_MULTI ||
params.type == IH_TYPE_SCRIPT)) { params.type == IH_TYPE_SCRIPT) {
char *file = params.datafile; char *file = params.datafile;
uint32_t size; uint32_t size;
for (;;) { for (;;) {
char *sep = NULL; char *sep = NULL;
if (file) { if (file) {
if ((sep = strchr(file, ':')) != NULL) { if ((sep = strchr(file, ':')) != NULL) {
*sep = '\0'; *sep = '\0';
}
if (stat (file, &sbuf) < 0) {
fprintf (stderr, "%s: Can't stat %s: %s\n",
params.cmdname, file, strerror(errno));
exit (EXIT_FAILURE);
}
size = cpu_to_uimage (sbuf.st_size);
} else {
size = 0;
} }
if (stat (file, &sbuf) < 0) { if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) {
fprintf (stderr, "%s: Can't stat %s: %s\n", fprintf (stderr, "%s: Write error on %s: %s\n",
params.cmdname, file, strerror(errno)); params.cmdname, params.imagefile,
strerror(errno));
exit (EXIT_FAILURE); exit (EXIT_FAILURE);
} }
size = cpu_to_uimage (sbuf.st_size);
} else { if (!file) {
size = 0; break;
}
if (sep) {
*sep = ':';
file = sep + 1;
} else {
file = NULL;
}
} }
if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { file = params.datafile;
fprintf (stderr, "%s: Write error on %s: %s\n",
params.cmdname, params.imagefile,
strerror(errno));
exit (EXIT_FAILURE);
}
if (!file) { for (;;) {
break; char *sep = strchr(file, ':');
} if (sep) {
*sep = '\0';
if (sep) { copy_file (ifd, file, 1);
*sep = ':'; *sep++ = ':';
file = sep + 1; file = sep;
} else { } else {
file = NULL; copy_file (ifd, file, 0);
break;
}
} }
} else {
copy_file (ifd, params.datafile, 0);
} }
file = params.datafile;
for (;;) {
char *sep = strchr(file, ':');
if (sep) {
*sep = '\0';
copy_file (ifd, file, 1);
*sep++ = ':';
file = sep;
} else {
copy_file (ifd, file, 0);
break;
}
}
} else {
copy_file (ifd, params.datafile, 0);
} }
/* We're a bit of paranoid */ /* We're a bit of paranoid */