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Merge remote-tracking branch 'u-boot/master'

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This commit is contained in:
Albert ARIBAUD 2015-10-14 10:46:36 +02:00
commit 13a3972585
1324 changed files with 29286 additions and 39335 deletions
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2
Kconfig
View File

@ -146,7 +146,7 @@ config FIT
Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
pass the the address of the blob to the "bootm" command.
pass the address of the blob to the "bootm" command.
config FIT_VERBOSE
bool "Display verbose messages on FIT boot"

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*

24
README
View File

@ -681,8 +681,10 @@ The following options need to be configured:
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_761320
CONFIG_ARM_ERRATA_773022
CONFIG_ARM_ERRATA_774769
CONFIG_ARM_ERRATA_794072
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
@ -840,18 +842,6 @@ The following options need to be configured:
define this to a list of base addresses for each (supported)
port. See e.g. include/configs/versatile.h
CONFIG_PL011_SERIAL_RLCR
Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
have separate receive and transmit line control registers. Set
this variable to initialize the extra register.
CONFIG_PL011_SERIAL_FLUSH_ON_INIT
On some platforms (e.g. U8500) U-Boot is loaded by a second stage
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
CONFIG_SERIAL_HW_FLOW_CONTROL
Define this variable to enable hw flow control in serial driver.
@ -2371,16 +2361,20 @@ CBFS (Coreboot Filesystem) support
- drivers/i2c/i2c_mxc.c
- activate this driver with CONFIG_SYS_I2C_MXC
- enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
- enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
- enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
- enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
- define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
- define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
If those defines are not set, default value is 100000
for speed, and 0 for slave.
- enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
- enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- drivers/i2c/rcar_i2c.c:
- activate this driver with CONFIG_SYS_I2C_RCAR

5
api/api_storage.c
View File

@ -112,6 +112,11 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
else
found = 1;
/* provide hint if there are more devices in
* this group to enumerate */
if (1 < specs[type].max_dev)
*more = 1;
} else {
for (i = 0; i < specs[type].max_dev; i++)
if (di->cookie == (void *)get_dev(specs[type].name, i)) {

163
arch/arm/Kconfig
View File

@ -70,7 +70,7 @@ config SYS_L2CACHE_OFF
choice
prompt "Target select"
default ARCH_VERSATILE
default TARGET_HIKEY
config ARCH_AT91
bool "Atmel AT91"
@ -79,10 +79,6 @@ config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
config TARGET_SCB9328
bool "Support scb9328"
select CPU_ARM920T
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@ -138,11 +134,6 @@ config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
config TARGET_TX25
bool "Support tx25"
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_ZMX25
bool "Support zmx25"
select CPU_ARM926EJS
@ -152,14 +143,6 @@ config TARGET_APF27
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_IMX27LITE
bool "Support imx27lite"
select CPU_ARM926EJS
config TARGET_MAGNESIUM
bool "Support magnesium"
select CPU_ARM926EJS
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
select CPU_ARM926EJS
@ -205,10 +188,6 @@ config TARGET_SC_SPS_1
select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
select CPU_ARM926EJS
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
@ -243,18 +222,10 @@ config TARGET_X600
select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
select CPU_ARM926EJS
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
config TARGET_QONG
bool "Support qong"
select CPU_ARM1136
config TARGET_MX31ADS
bool "Support mx31ads"
select CPU_ARM1136
@ -264,14 +235,6 @@ config TARGET_MX31PDK
select CPU_ARM1136
select SUPPORT_SPL
config TARGET_TT01
bool "Support tt01"
select CPU_ARM1136
config TARGET_IMX31_LITEKIT
bool "Support imx31_litekit"
select CPU_ARM1136
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
@ -400,6 +363,13 @@ config TARGET_AM335X_EVM
select DM_SERIAL
select DM_GPIO
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select CPU_V7
@ -472,6 +442,10 @@ config ARCH_KEYSTONE
select CPU_V7
select SUPPORT_SPL
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
@ -485,10 +459,6 @@ config TARGET_M53EVK
select CPU_V7
select SUPPORT_SPL
config TARGET_IMA3_MX53
bool "Support ima3-mx53"
select CPU_V7
config TARGET_MX51EVK
bool "Support mx51evk"
select CPU_V7
@ -509,14 +479,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
config TARGET_MX51_EFIKAMX
bool "Support mx51_efikamx"
select CPU_V7
config TARGET_VISION2
bool "Support vision2"
select CPU_V7
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
@ -564,18 +526,10 @@ config ARCH_SUNXI
select USB_STORAGE
select USB_KEYBOARD
config TARGET_SNOWBALL
bool "Support snowball"
select CPU_V7
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
select CPU_V7
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
@ -584,6 +538,10 @@ config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
@ -609,6 +567,15 @@ config TARGET_VEXPRESS64_BASE_FVP
select ARM64
select SEMIHOSTING
config TARGET_VEXPRESS64_BASE_FVP_DRAM
bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
select ARM64
help
This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
the default config to allow the user to load the images directly into
DRAM using model parameters rather than by using semi-hosting to load
the files from the host filesystem.
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
@ -648,6 +615,9 @@ config TARGET_LS2085ARDB
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
select DM
select DM_GPIO
select DM_SERIAL
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
@ -656,66 +626,19 @@ config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
select SUPPORT_SPL
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
config TARGET_BALLOON3
bool "Support balloon3"
select CPU_PXA
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
config TARGET_PALMLD
bool "Support palmld"
select CPU_PXA
config TARGET_PALMTC
bool "Support palmtc"
select CPU_PXA
config TARGET_PALMTREO680
bool "Support palmtreo680"
select CPU_PXA
select SUPPORT_SPL
config TARGET_PXA255_IDP
bool "Support pxa255_idp"
select CPU_PXA
config TARGET_TRIZEPSIV
bool "Support trizepsiv"
select CPU_PXA
config TARGET_VPAC270
bool "Support vpac270"
select CPU_PXA
select SUPPORT_SPL
config TARGET_XAENIAX
bool "Support xaeniax"
select CPU_PXA
config TARGET_ZIPITZ2
bool "Support zipitz2"
select CPU_PXA
config TARGET_LP8X4X
bool "Support lp8x4x"
select CPU_PXA
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
config TARGET_JORNADA
bool "Support jornada"
select CPU_SA1100
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CPU_V7
@ -761,12 +684,12 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/cpu/armv7/omap3/Kconfig"
source "arch/arm/cpu/armv7/omap4/Kconfig"
@ -787,8 +710,6 @@ source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
@ -809,7 +730,6 @@ source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/balloon3/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
@ -818,10 +738,8 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
@ -839,30 +757,19 @@ source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/palmld/Kconfig"
source "board/palmtc/Kconfig"
source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
@ -873,12 +780,11 @@ source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
@ -887,15 +793,10 @@ source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"

6
arch/arm/Makefile
View File

@ -51,14 +51,12 @@ machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARMADA_XP) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
@ -80,11 +78,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
libs-y += arch/arm/imx-common/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
endif
endif

10
arch/arm/cpu/arm926ejs/lpc32xx/clk.c
View File

@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void)
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
fout = fref * m_div;
if (val & CLK_HCLK_PLL_FEEDBACK) {
fcco = fout;
fcco = fref * m_div;
fout = fcco;
if (val & CLK_HCLK_PLL_FEEDBACK)
fcco *= p_div;
else
do_div(fout, p_div);
} else
fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;

3
arch/arm/cpu/arm926ejs/lpc32xx/devices.c
View File

@ -44,8 +44,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
writel(DMA_CLK_ENABLE, &clk->dmaclk_ctrl);
writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
}
void lpc32xx_mac_init(void)

34
arch/arm/cpu/arm926ejs/spear/cpu.c
View File

@ -83,3 +83,37 @@ int print_cpuinfo(void)
return 0;
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
if (argc != 2)
goto usage;
if (strncmp(argv[1], "hw", 2) == 0) {
/* 1-bit HW ECC */
printf("Switching to 1-bit HW ECC\n");
fsmc_nand_switch_ecc(1);
} else if (strncmp(argv[1], "bch4", 2) == 0) {
/* 4-bit SW ECC BCH4 */
printf("Switching to 4-bit SW ECC (BCH4)\n");
fsmc_nand_switch_ecc(4);
} else {
goto usage;
}
return 0;
usage:
printf("Usage: nandecc %s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
nandecc, 2, 0, do_switch_ecc,
"switch NAND ECC calculation algorithm",
"hw|bch4 - Switch between NAND hardware 1-bit HW and"
" 4-bit SW BCH\n"
);
#endif

4
arch/arm/cpu/armv7/Makefile
View File

@ -12,7 +12,7 @@ obj-y += cache_v7.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
@ -44,6 +44,7 @@ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
@ -51,5 +52,4 @@ obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_VF610) += vf610/

15
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -13,6 +13,8 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include <config.h>
#include <fsl_wdog.h>
#include "fsl_epu.h"
@ -354,3 +356,16 @@ void smp_kick_all_cpus(void)
asm volatile("sev");
}
#endif
void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
clrbits_be16(&wdog->wcr, WCR_SRS);
while (1) {
/*
* Let the watchdog trigger
*/
}
}

30
arch/arm/cpu/armv7/mx6/Kconfig
View File

@ -35,19 +35,15 @@ choice
config TARGET_ARISTAINETOS
bool "aristainetos"
select CPU_V7
config TARGET_ARISTAINETOS2
bool "aristainetos2"
select CPU_V7
config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
select CPU_V7
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
select CPU_V7
config TARGET_CM_FX6
bool "CM-FX6"
@ -58,77 +54,70 @@ config TARGET_CM_FX6
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
select CPU_V7
config TARGET_GW_VENTANA
bool "gw_ventana"
select CPU_V7
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
select CPU_V7
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
select CPU_V7
select DM
select DM_THERMAL
config TARGET_MX6SABRESD
bool "mx6sabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SLEVK
bool "mx6slevk"
select CPU_V7
select SUPPORT_SPL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select MX6UL
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select MX6UL
select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_NITROGEN6X
bool "nitrogen6x"
select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "platinum-picon"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
select CPU_V7
select SUPPORT_SPL
config TARGET_SECOMX6
@ -136,28 +125,23 @@ config TARGET_SECOMX6
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
select CPU_V7
config TARGET_TITANIUM
bool "titanium"
select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config TARGET_UDOO
bool "udoo"
select CPU_V7
select SUPPORT_SPL
config TARGET_WANDBOARD
bool "wandboard"
select CPU_V7
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
select CPU_V7
endchoice

2
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);

4
arch/arm/cpu/armv7/mx6/ddr.c
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@ -702,8 +702,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
trfc = DIV_ROUND_UP(300000, clkper) - 1;
txs = DIV_ROUND_UP(310000, clkper) - 1;
trfc = DIV_ROUND_UP(260000, clkper) - 1;
txs = DIV_ROUND_UP(270000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;

198
arch/arm/cpu/armv7/mx6/soc.c
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@ -8,9 +8,6 @@
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@ -38,7 +35,7 @@ struct scu_regs {
u32 fpga_rev;
};
#if defined(CONFIG_IMX6_THERMAL)
#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
@ -186,65 +183,6 @@ u32 __weak get_board_rev(void)
}
#endif
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
struct aipstz_regs *aips3;
#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips1->mprot0);
writel(0x77777777, &aips1->mprot1);
writel(0x77777777, &aips2->mprot0);
writel(0x77777777, &aips2->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips1->opacr0);
writel(0x00000000, &aips1->opacr1);
writel(0x00000000, &aips1->opacr2);
writel(0x00000000, &aips1->opacr3);
writel(0x00000000, &aips1->opacr4);
writel(0x00000000, &aips2->opacr0);
writel(0x00000000, &aips2->opacr1);
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
#ifdef CONFIG_MX6SX
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
#endif
}
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
@ -312,20 +250,6 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
return 0;
}
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
writew(enable, &wdog3->wmcr);
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
}
static void set_ahb_rate(u32 val)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -378,22 +302,6 @@ static void set_preclk_from_osc(void)
}
#endif
#define SRC_SCR_WARM_RESET_ENABLE 0
static void init_src(void)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
/*
* force warm reset sources to generate cold reset
* for a more reliable restart
*/
val = readl(&src_regs->scr);
val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
writel(val, &src_regs->scr);
}
int arch_cpu_init(void)
{
init_aips();
@ -440,31 +348,6 @@ int board_postclk_init(void)
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
enum dcache_option option = DCACHE_WRITETHROUGH;
#else
enum dcache_option option = DCACHE_WRITEBACK;
#endif
/* Avoid random hang when download by usb */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
/* Enable caching on OCRAM and ROM */
mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,
option);
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,
option);
}
#endif
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
@ -486,18 +369,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
struct src *psrc = (struct src *)SRC_BASE_ADDR;
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
reg |= 1 << 28;
else
reg &= ~(1 << 28);
writel(reg, &psrc->gpr10);
}
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@ -605,70 +476,3 @@ void imx_setup_hdmi(void)
writel(reg, &mxc_ccm->chsccdr);
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
unsigned int val;
/*
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
* accesses as Cacheable no-allocate.
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
#if defined CONFIG_MX6SL
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
val = readl(&iomux->gpr[11]);
if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
/* L2 cache configured as OCRAM, reset it */
val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
writel(val, &iomux->gpr[11]);
}
#endif
/* Must disable the L2 before changing the latency parameters */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
val = readl(&pl310->pl310_prefetch_ctrl);
/* Turn on the L2 I/D prefetch */
val |= 0x30000000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
* But according to ARM PL310 errata: 752271
* ID: 752271: Double linefill feature can cause data corruption
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
* Workaround: The only workaround to this erratum is to disable the
* double linefill feature. This is the default behavior.
*/
#ifndef CONFIG_MX6Q
val |= 0x40800000;
#endif
writel(val, &pl310->pl310_prefetch_ctrl);
val = readl(&pl310->pl310_power_ctrl);
val |= L2X0_DYNAMIC_CLK_GATING_EN;
val |= L2X0_STNDBY_MODE_EN;
writel(val, &pl310->pl310_power_ctrl);
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */

26
arch/arm/cpu/armv7/mx7/Kconfig Normal file
View File

@ -0,0 +1,26 @@
if ARCH_MX7
config MX7
bool
default y
config MX7D
bool
choice
prompt "MX7 board select"
optional
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
select DM
select DM_THERMAL
endchoice
config SYS_SOC
default "mx7"
source "board/freescale/mx7dsabresd/Kconfig"
endif

8
arch/arm/cpu/armv7/mx7/Makefile Normal file
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@ -0,0 +1,8 @@
#
# (C) Copyright 2015 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
obj-y := soc.o clock.o clock_slice.o

1127
arch/arm/cpu/armv7/mx7/clock.c Normal file
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File diff suppressed because it is too large Load Diff

757
arch/arm/cpu/armv7/mx7/clock_slice.c Normal file
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@ -0,0 +1,757 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* Author:
* Peng Fan <Peng.Fan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
static struct clk_root_map root_array[] = {
{ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
{OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
},
{DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
{ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
},
{NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
},
{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
{DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
{PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
},
{DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
{PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
},
{DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
{DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
},
{USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
},
{PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
},
{PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
},
{EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
},
{LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
},
{MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
},
{MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
},
{SAI1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
},
{SAI2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
},
{SAI3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
},
{SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
},
{ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
},
{ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
},
{ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
},
{ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
},
{ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
},
{EIM_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
},
{NAND_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
},
{QSPI_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
},
{USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
},
{USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
},
{USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
},
{CAN1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
EXT_CLK_1, EXT_CLK_4}
},
{CAN2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
EXT_CLK_1, EXT_CLK_3}
},
{I2C1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
},
{I2C2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
},
{I2C3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
},
{I2C4_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
},
{UART1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
},
{UART2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
},
{UART3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
},
{UART4_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
},
{UART5_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
},
{UART6_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
},
{UART7_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
},
{ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
},
{ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
},
{ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
},
{ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
},
{PWM1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{PWM2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{PWM3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{PWM4_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
},
{SIM1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
},
{SIM2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
},
{GPT1_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
},
{GPT2_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
},
{GPT3_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
},
{GPT4_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
},
{TRACE_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
EXT_CLK_1, EXT_CLK_3}
},
{WDOG_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
},
{CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
},
{WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
},
{IPP_DO_CLKO1, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
},
{IPP_DO_CLKO2, CCM_IP_CHANNEL,
{OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
},
};
/* select which entry of root_array */
static int select(enum clk_root_index clock_id)
{
int i, size;
struct clk_root_map *p = root_array;
size = ARRAY_SIZE(root_array);
for (i = 0; i < size; i++, p++) {
if (clock_id == p->entry)
return i;
}
return -EINVAL;
}
static int src_supported(int entry, enum clk_root_src clock_src)
{
int i, size;
struct clk_root_map *p = &root_array[entry];
if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
size = 2;
else
size = 8;
for (i = 0; i < size; i++) {
if (p->src_mux[i] == clock_src)
return i;
}
return -EINVAL;
}
/* Set src for clock root slice. */
int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
{
int root_entry, src_entry;
u32 reg;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
src_entry = src_supported(root_entry, clock_src);
if (src_entry < 0)
return -EINVAL;
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
reg &= ~CLK_ROOT_MUX_MASK;
reg |= src_entry << CLK_ROOT_MUX_SHIFT;
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
return 0;
}
/* Get src of a clock root slice. */
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
{
u32 val;
int root_entry;
struct clk_root_map *p;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
val &= CLK_ROOT_MUX_MASK;
val >>= CLK_ROOT_MUX_SHIFT;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
*p_clock_src = p->src_mux[val];
return 0;
}
int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
{
int root_entry;
struct clk_root_map *p;
u32 reg;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->type == CCM_CORE_CHANNEL) ||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
(p->type == CCM_DRAM_CHANNEL)) {
if (pre_div != CLK_ROOT_PRE_DIV1) {
printf("Error pre div!\n");
return -EINVAL;
}
}
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
reg &= ~CLK_ROOT_PRE_DIV_MASK;
reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
return 0;
}
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
{
u32 val;
int root_entry;
struct clk_root_map *p;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->type == CCM_CORE_CHANNEL) ||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
(p->type == CCM_DRAM_CHANNEL)) {
*pre_div = 0;
return 0;
}
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
val &= CLK_ROOT_PRE_DIV_MASK;
val >>= CLK_ROOT_PRE_DIV_SHIFT;
*pre_div = val;
return 0;
}
int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
{
u32 reg;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
if (clock_id == DRAM_PHYM_CLK_ROOT) {
if (div != CLK_ROOT_POST_DIV1) {
printf("Error post div!\n");
return -EINVAL;
}
}
/* Only 3 bit post div. */
if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
printf("Error post div!\n");
return -EINVAL;
}
reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
reg &= ~CLK_ROOT_POST_DIV_MASK;
reg |= div << CLK_ROOT_POST_DIV_SHIFT;
__raw_writel(reg, &imx_ccm->root[clock_id].target_root);
return 0;
}
int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
{
u32 val;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
if (clock_id == DRAM_PHYM_CLK_ROOT) {
*div = 0;
return 0;
}
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
if (clock_id == DRAM_CLK_ROOT)
val &= DRAM_CLK_ROOT_POST_DIV_MASK;
else
val &= CLK_ROOT_POST_DIV_MASK;
val >>= CLK_ROOT_POST_DIV_SHIFT;
*div = val;
return 0;
}
int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
int auto_en)
{
u32 val;
int root_entry;
struct clk_root_map *p;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
printf("Auto postdiv not supported.!\n");
return -EINVAL;
}
/*
* Each time only one filed can be changed, no use target_root_set.
*/
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
val &= ~CLK_ROOT_AUTO_DIV_MASK;
val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
if (auto_en)
val |= CLK_ROOT_AUTO_EN;
else
val &= ~CLK_ROOT_AUTO_EN;
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
return 0;
}
int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
int *auto_en)
{
u32 val;
int root_entry;
struct clk_root_map *p;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
/*
* Only bus/ahb channel supports auto div.
* If unsupported, just set auto_en and div with 0.
*/
if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
*auto_en = 0;
*div = 0;
return 0;
}
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
*auto_en = 0;
else
*auto_en = 1;
val &= CLK_ROOT_AUTO_DIV_MASK;
val >>= CLK_ROOT_AUTO_DIV_SHIFT;
*div = val;
return 0;
}
int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
{
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
*val = __raw_readl(&imx_ccm->root[clock_id].target_root);
return 0;
}
int clock_set_target_val(enum clk_root_index clock_id, u32 val)
{
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
return 0;
}
/* Auto_div and auto_en is ignored, they are rarely used. */
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
enum root_post_div post_div, enum clk_root_src clock_src)
{
u32 val;
int root_entry, src_entry;
struct clk_root_map *p;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
root_entry = select(clock_id);
if (root_entry < 0)
return -EINVAL;
p = &root_array[root_entry];
if ((p->type == CCM_CORE_CHANNEL) ||
(p->type == CCM_DRAM_PHYM_CHANNEL) ||
(p->type == CCM_DRAM_CHANNEL)) {
if (pre_div != CLK_ROOT_PRE_DIV1) {
printf("Error pre div!\n");
return -EINVAL;
}
}
/* Only 3 bit post div. */
if (p->type == CCM_DRAM_CHANNEL) {
if (post_div > CLK_ROOT_POST_DIV7) {
printf("Error post div!\n");
return -EINVAL;
}
}
if (p->type == CCM_DRAM_PHYM_CHANNEL) {
if (post_div != CLK_ROOT_POST_DIV1) {
printf("Error post div!\n");
return -EINVAL;
}
}
src_entry = src_supported(root_entry, clock_src);
if (src_entry < 0)
return -EINVAL;
val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
post_div << CLK_ROOT_POST_DIV_SHIFT |
src_entry << CLK_ROOT_MUX_SHIFT;
__raw_writel(val, &imx_ccm->root[clock_id].target_root);
return 0;
}
int clock_root_enabled(enum clk_root_index clock_id)
{
u32 val;
if (clock_id >= CLK_ROOT_MAX)
return -EINVAL;
/*
* No enable bit for DRAM controller and PHY. Just return enabled.
*/
if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
return 1;
val = __raw_readl(&imx_ccm->root[clock_id].target_root);
return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
}
/* CCGR gate operation */
int clock_enable(enum clk_ccgr_index index, bool enable)
{
if (index >= CCGR_MAX)
return -EINVAL;
if (enable)
__raw_writel(CCM_CLK_ON_MSK,
&imx_ccm->ccgr_array[index].ccgr_set);
else
__raw_writel(CCM_CLK_ON_MSK,
&imx_ccm->ccgr_array[index].ccgr_clr);
return 0;
}

267
arch/arm/cpu/armv7/mx7/soc.c Normal file
View File

@ -0,0 +1,267 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 3,
.fuse_word = 3,
};
U_BOOT_DEVICE(imx7_thermal) = {
.name = "imx_thermal",
.platdata = &imx7_thermal_plat,
};
#endif
/*
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
*/
#define OCOTP_TESTER3_SPEED_SHIFT 8
#define OCOTP_TESTER3_SPEED_800MHZ 0
#define OCOTP_TESTER3_SPEED_850MHZ 1
#define OCOTP_TESTER3_SPEED_1GHZ 2
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
uint32_t val;
val = readl(&fuse->tester3);
val >>= OCOTP_TESTER3_SPEED_SHIFT;
val &= 0x3;
switch(val) {
case OCOTP_TESTER3_SPEED_800MHZ:
return 792000000;
case OCOTP_TESTER3_SPEED_850MHZ:
return 852000000;
case OCOTP_TESTER3_SPEED_1GHZ:
return 996000000;
}
return 0;
}
/*
* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
*/
#define OCOTP_TESTER3_TEMP_SHIFT 6
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
uint32_t val;
val = readl(&fuse->tester3);
val >>= OCOTP_TESTER3_TEMP_SHIFT;
val &= 0x3;
if (minc && maxc) {
if (val == TEMP_AUTOMOTIVE) {
*minc = -40;
*maxc = 125;
} else if (val == TEMP_INDUSTRIAL) {
*minc = -40;
*maxc = 105;
} else if (val == TEMP_EXTCOMMERCIAL) {
*minc = -20;
*maxc = 105;
} else {
*minc = 0;
*maxc = 95;
}
}
return val;
}
u32 get_cpu_rev(void)
{
struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
ANATOP_BASE_ADDR;
u32 reg = readl(&ccm_anatop->digprog);
u32 type = (reg >> 16) & 0xff;
reg &= 0xff;
return (type << 12) | reg;
}
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
return get_cpu_rev();
}
#endif
int arch_cpu_init(void)
{
init_aips();
/* Disable PDE bit of WMCR register */
imx_set_wdog_powerdown(false);
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
#endif
return 0;
}
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
serialnr->low = fuse->tester0;
serialnr->high = fuse->tester1;
}
#endif
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[9];
struct fuse_bank9_regs *fuse =
(struct fuse_bank9_regs *)bank->fuse_regs;
if (0 == dev_id) {
u32 value = readl(&fuse->mac_addr1);
mac[0] = (value >> 8);
mac[1] = value;
value = readl(&fuse->mac_addr0);
mac[2] = value >> 24;
mac[3] = value >> 16;
mac[4] = value >> 8;
mac[5] = value;
} else {
u32 value = readl(&fuse->mac_addr2);
mac[0] = value >> 24;
mac[1] = value >> 16;
mac[2] = value >> 8;
mac[3] = value;
value = readl(&fuse->mac_addr1);
mac[4] = value >> 24;
mac[5] = value >> 16;
}
}
#endif
void set_wdog_reset(struct wdog_regs *wdog)
{
u32 reg = readw(&wdog->wcr);
/*
* Output WDOG_B signal to reset external pmic or POR_B decided by
* the board desgin. Without external reset, the peripherals/DDR/
* PMIC are not reset, that may cause system working abnormal.
*/
reg = readw(&wdog->wcr);
reg |= 1 << 3;
/*
* WDZST bit is write-once only bit. Align this bit in kernel,
* otherwise kernel code will have no chance to set this bit.
*/
reg |= 1 << 0;
writew(reg, &wdog->wcr);
}
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
* to SBMR1, which will determine the boot device.
*/
const struct boot_mode soc_boot_modes[] = {
{"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
{"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
{"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
{"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
{"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
{"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
/* 4 bit bus width */
{"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
{"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
{"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
{"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
{"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
{"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
{NULL, 0},
};
enum boot_device get_boot_device(void)
{
struct bootrom_sw_info **p =
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
enum boot_device boot_dev = SD1_BOOT;
u8 boot_type = (*p)->boot_dev_type;
u8 boot_instance = (*p)->boot_dev_instance;
switch (boot_type) {
case BOOT_TYPE_SD:
boot_dev = boot_instance + SD1_BOOT;
break;
case BOOT_TYPE_MMC:
boot_dev = boot_instance + MMC1_BOOT;
break;
case BOOT_TYPE_NAND:
boot_dev = NAND_BOOT;
break;
case BOOT_TYPE_QSPI:
boot_dev = QSPI_BOOT;
break;
case BOOT_TYPE_WEIM:
boot_dev = WEIM_NOR_BOOT;
break;
case BOOT_TYPE_SPINOR:
boot_dev = SPI_NOR_BOOT;
break;
default:
break;
}
return boot_dev;
}
void s_init(void)
{
#if !defined CONFIG_SPL_BUILD
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
#endif
/* clock configuration. */
clock_init();
return;
}

14
arch/arm/cpu/armv7/nonsec_virt.S
View File

@ -53,6 +53,20 @@ _secure_monitor:
bl psci_arch_init
#endif
#ifdef CONFIG_ARM_ERRATA_773022
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 1)
mcr p15, 0, r5, c1, c0, 1
isb
#endif
#ifdef CONFIG_ARM_ERRATA_774769
mrc p15, 0, r5, c1, c0, 1
orr r5, r5, #(1 << 25)
mcr p15, 0, r5, c1, c0, 1
isb
#endif
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits

6
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
/* Disable refreshed before leveling */
clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
EMIF_REG_INITREF_DIS_SHIFT);
clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
EMIF_REG_INITREF_DIS_MASK);
/* Start Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
}
/* Enable refreshes after leveling */
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
debug("HW leveling success\n");
/*

12
arch/arm/cpu/armv7/omap3/Kconfig
View File

@ -12,9 +12,6 @@ config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
select SUPPORT_SPL
config TARGET_OMAP3_SDP3430
bool "TI OMAP3430 SDP"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select SUPPORT_SPL
@ -79,9 +76,6 @@ config TARGET_ECO5PK
bool "ECO5PK"
select SUPPORT_SPL
config TARGET_DIG297
bool "DIG297"
config TARGET_TRICORDER
bool "Tricorder"
select SUPPORT_SPL
@ -96,9 +90,6 @@ config TARGET_OMAP3_LOGIC
select DM_SERIAL
select DM_GPIO
config TARGET_OMAP3_MVBLX
bool "OMAP3 MVBLX"
config TARGET_NOKIA_RX51
bool "Nokia RX51"
@ -131,7 +122,6 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
@ -143,11 +133,9 @@ source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/comelit/dig297/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"

8
arch/arm/cpu/armv7/rmobile/Kconfig
View File

@ -40,6 +40,11 @@ config TARGET_PORTER
select DM
select DM_SERIAL
config TARGET_STOUT
bool "Stout board"
select DM
select DM_SERIAL
endchoice
config SYS_SOC
@ -47,7 +52,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
default n
choice
@ -80,5 +85,6 @@ source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
source "board/renesas/porter/Kconfig"
source "board/renesas/stout/Kconfig"
endif

8
arch/arm/cpu/armv7/sunxi/board.c
View File

@ -21,6 +21,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
@ -152,7 +153,7 @@ u32 spl_boot_device(void)
* binary over USB. If it is found, it determines where SPL was
* read from.
*/
if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return BOOT_DEVICE_BOARD;
/* The BROM will try to boot from mmc0 first, so try that first. */
@ -198,11 +199,6 @@ void board_init_f(ulong dummy)
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
#endif

9
arch/arm/cpu/armv7/u8500/Makefile
View File

@ -1,9 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := timer.o clock.o prcmu.o cpu.o
obj-y += lowlevel.o

74
arch/arm/cpu/armv7/u8500/clock.c
View File

@ -1,74 +0,0 @@
/*
* (C) Copyright 2009 ST-Ericsson
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
struct clkrst {
unsigned int pcken;
unsigned int pckdis;
unsigned int kcken;
unsigned int kckdis;
};
static unsigned int clkrst_base[] = {
U8500_CLKRST1_BASE,
U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE,
0,
U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE,
U8500_CLKRST7_BASE, /* ED only */
};
/* Turn on peripheral clock at PRCC level */
void u8500_clock_enable(int periph, int cluster, int kern)
{
struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
if (kern != -1)
writel(1 << kern, &clkrst->kcken);
if (cluster != -1)
writel(1 << cluster, &clkrst->pcken);
}
void db8500_clocks_init(void)
{
/*
* Enable all clocks. This is u-boot, we can enable it all. There is no
* powersave in u-boot.
*/
u8500_clock_enable(1, 9, -1); /* GPIO0 */
u8500_clock_enable(2, 11, -1);/* GPIO1 */
u8500_clock_enable(3, 8, -1); /* GPIO2 */
u8500_clock_enable(5, 1, -1); /* GPIO3 */
u8500_clock_enable(3, 6, 6); /* UART2 */
u8500_clock_enable(3, 3, 3); /* I2C0 */
u8500_clock_enable(1, 5, 5); /* SDI0 */
u8500_clock_enable(2, 4, 2); /* SDI4 */
u8500_clock_enable(6, 6, -1); /* MTU0 */
u8500_clock_enable(3, 4, 4); /* SDI2 */
/*
* Enabling clocks for all devices which are AMBA devices in the
* kernel. Otherwise they will not get probe()'d because the
* peripheral ID register will not be powered.
*/
/* XXX: some of these differ between ED/V1 */
u8500_clock_enable(1, 1, 1); /* UART1 */
u8500_clock_enable(1, 0, 0); /* UART0 */
u8500_clock_enable(3, 2, 2); /* SSP1 */
u8500_clock_enable(3, 1, 1); /* SSP0 */
u8500_clock_enable(2, 8, -1); /* SPI0 */
u8500_clock_enable(2, 5, 3); /* MSP2 */
}

176
arch/arm/cpu/armv7/u8500/cpu.c
View File

@ -1,176 +0,0 @@
/*
* Copyright (C) 2012 Linaro Limited
* Mathieu Poirier <mathieu.poirier@linaro.org>
*
* Based on original code from Joakim Axelsson at ST-Ericsson
* (C) Copyright 2010 ST-Ericsson
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/prcmu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/hardware.h>
#define CPUID_DB8500V1 0x411fc091
#define CPUID_DB8500V2 0x412fc091
#define ASICID_DB8500V11 0x008500A1
#define CACHE_CONTR_BASE 0xA0412000
/* Cache controller register offsets
* as found in ARM's technical reference manual
*/
#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
static unsigned int read_asicid(void);
static inline unsigned int read_cpuid(void)
{
unsigned int val;
/* Main ID register (MIDR) */
asm("mrc p15, 0, %0, c0, c0, 0"
: "=r" (val)
:
: "cc");
return val;
}
static int cpu_is_u8500v11(void)
{
return read_asicid() == ASICID_DB8500V11;
}
static int cpu_is_u8500v2(void)
{
return read_cpuid() == CPUID_DB8500V2;
}
static unsigned int read_asicid(void)
{
unsigned int *address;
if (cpu_is_u8500v2())
address = (void *) U8500_ASIC_ID_LOC_V2;
else
address = (void *) U8500_ASIC_ID_LOC_ED_V1;
return readl(address);
}
void cpu_cache_initialization(void)
{
unsigned int value;
/* invalidate all cache entries */
writel(0xFFFF, CACHE_INVAL_BY_WAY);
/* ways are set to '0' when they are totally
* cleaned and invalidated
*/
do {
value = readl(CACHE_INVAL_BY_WAY);
} while (value & 0xFF);
/* Invalidate register 9 D and I lockdown */
writel(0xFF, CACHE_LOCKDOWN_BY_D);
writel(0xFF, CACHE_LOCKDOWN_BY_I);
}
#ifdef CONFIG_ARCH_CPU_INIT
/*
* SOC specific cpu init
*/
int arch_cpu_init(void)
{
db8500_prcmu_init();
db8500_clocks_init();
return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */
#ifdef CONFIG_MMC
int u8500_mmc_power_init(void)
{
int ret;
int enable, voltage;
int ab8500_revision;
if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
return 0;
/* Get AB8500 revision */
ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
if (ret < 0)
goto out;
ab8500_revision = ret;
/*
* On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
* card to work. This is done by enabling the regulators in the AB8500
* via PRCMU I2C transactions.
*
* This code is derived from the handling of AB8500_LDO_VAUX3 in
* ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
*
* Turn off and delay is required to have it work across soft reboots.
*/
/* Turn off (read-modify-write) */
ret = ab8500_read(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_REGU_REG);
if (ret < 0)
goto out;
enable = ret;
/* Turn off */
ret = ab8500_write(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_REGU_REG,
enable & ~LDO_VAUX3_ENABLE_MASK);
if (ret < 0)
goto out;
udelay(10 * 1000);
/* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
ret = ab8500_read(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_SEL_REG);
if (ret < 0)
goto out;
voltage = ret;
if (ab8500_revision < 0x20) {
voltage &= ~LDO_VAUX3_SEL_MASK;
voltage |= LDO_VAUX3_SEL_2V9;
} else {
voltage &= ~LDO_VAUX3_V2_SEL_MASK;
voltage |= LDO_VAUX3_V2_SEL_2V91;
}
ret = ab8500_write(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
if (ret < 0)
goto out;
/* Turn on the supply */
enable &= ~LDO_VAUX3_ENABLE_MASK;
enable |= LDO_VAUX3_ENABLE_VAL;
ret = ab8500_write(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
out:
return ret;
}
#endif /* CONFIG_MMC */

21
arch/arm/cpu/armv7/u8500/lowlevel.S
View File

@ -1,21 +0,0 @@
/*
* (C) Copyright 2011 ST-Ericsson
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mov pc, lr
ENDPROC(lowlevel_init)
.align 5
ENTRY(reset_cpu)
ldr r0, =CFG_PRCMU_BASE
ldr r1, =0x1
str r1, [r0, #0x228]
_loop_forever:
b _loop_forever
ENDPROC(reset_cpu)

214
arch/arm/cpu/armv7/u8500/prcmu.c
View File

@ -1,214 +0,0 @@
/*
* Copyright (C) 2009 ST-Ericsson SA
*
* Adapted from the Linux version:
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* NOTE: This currently does not support the I2C workaround access method.
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/prcmu.h>
/* CPU mailbox registers */
#define PRCMU_I2C_WRITE(slave) \
(((slave) << 1) | I2CWRITE | (1 << 6))
#define PRCMU_I2C_READ(slave) \
(((slave) << 1) | I2CREAD | (1 << 6))
#define I2C_MBOX_BIT (1 << 5)
static int prcmu_is_ready(void)
{
int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
if (!ready)
printf("PRCMU firmware not ready\n");
return ready;
}
static int wait_for_i2c_mbx_rdy(void)
{
int timeout = 10000;
if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
printf("prcmu: warning i2c mailbox was not acked\n");
/* clear mailbox 5 ack irq */
writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
}
/* check any already on-going transaction */
while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
timeout--;
if (timeout == 0)
return -1;
return 0;
}
static int wait_for_i2c_req_done(void)
{
int timeout = 10000;
/* Set an interrupt to XP70 */
writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
/* wait for mailbox 5 (i2c) ack */
while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
timeout--;
if (timeout == 0)
return -1;
return 0;
}
/**
* prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
* @reg: - db8500 register bank to be accessed
* @slave: - db8500 register to be accessed
* Returns: ACK_MB5 value containing the status
*/
int prcmu_i2c_read(u8 reg, u16 slave)
{
uint8_t i2c_status;
uint8_t i2c_val;
int ret;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
reg, slave);
ret = wait_for_i2c_mbx_rdy();
if (ret) {
printf("prcmu_i2c_read: mailbox became not ready\n");
return ret;
}
/* prepare the data for mailbox 5 */
writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(0, PRCM_REQ_MB5_I2CVAL);
ret = wait_for_i2c_req_done();
if (ret) {
printf("prcmu_i2c_read: mailbox request timed out\n");
return ret;
}
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
readb(PRCM_ACK_MB5_STATUS));
debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
debug("ack-mb5:slave_add = %x\n",
readb(PRCM_ACK_MB5_SLAVE));
debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
i2c_status = readb(PRCM_ACK_MB5_STATUS);
i2c_val = readb(PRCM_ACK_MB5_VAL);
/* clear mailbox 5 ack irq */
writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
if (i2c_status == I2C_RD_OK)
return i2c_val;
printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
return -1;
}
/**
* prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
* @reg: - db8500 register bank to be accessed
* @slave: - db800 register to be written to
* @reg_data: - the data to write
* Returns: ACK_MB5 value containing the status
*/
int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
{
uint8_t i2c_status;
int ret;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
reg, slave);
ret = wait_for_i2c_mbx_rdy();
if (ret) {
printf("prcmu_i2c_write: mailbox became not ready\n");
return ret;
}
/* prepare the data for mailbox 5 */
writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
ret = wait_for_i2c_req_done();
if (ret) {
printf("prcmu_i2c_write: mailbox request timed out\n");
return ret;
}
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
readb(PRCM_ACK_MB5_STATUS));
debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
debug("ack-mb5:slave_add = %x\n",
readb(PRCM_ACK_MB5_SLAVE));
debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
i2c_status = readb(PRCM_ACK_MB5_STATUS);
debug("\ni2c_status = %x\n", i2c_status);
/* clear mailbox 5 ack irq */
writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
if (i2c_status == I2C_WR_OK)
return 0;
printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
return -1;
}
void u8500_prcmu_enable(u32 *reg)
{
writel(readl(reg) | (1 << 8), reg);
}
void db8500_prcmu_init(void)
{
/* Enable timers */
writel(1 << 17, PRCM_TCR);
u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
/* PER4CLK does not exist */
u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
/* Only exists in ED but is always ok to write to */
u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
/* Clean up the mailbox interrupts after pre-u-boot code. */
writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
}

135
arch/arm/cpu/armv7/u8500/timer.c
View File

@ -1,135 +0,0 @@
/*
* Copyright (C) 2010 Linaro Limited
* John Rigby <john.rigby@linaro.org>
*
* Based on original from Linux kernel source and
* internal ST-Ericsson U-Boot source.
* (C) Copyright 2009 Alessandro Rubini
* (C) Copyright 2010 ST-Ericsson
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The MTU device has some interrupt control registers
* followed by 4 timers.
*/
/* The timers */
struct u8500_mtu_timer {
u32 lr; /* Load value */
u32 cv; /* Current value */
u32 cr; /* Control reg */
u32 bglr; /* ??? */
};
/* The MTU that contains the timers */
struct u8500_mtu {
u32 imsc; /* Interrupt mask set/clear */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt status */
u32 icr; /* Interrupt clear register */
struct u8500_mtu_timer pt[4];
};
/* bits for the control register */
#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
#define MTU_CR_32BITS 0x02
#define MTU_CR_PRESCALE_1 0x00
#define MTU_CR_PRESCALE_16 0x04
#define MTU_CR_PRESCALE_256 0x08
#define MTU_CR_PRESCALE_MASK 0x0c
#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CR_ENA 0x80
/*
* The MTU is clocked at 133 MHz by default. (V1 and later)
*/
#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
#define COUNT_TO_USEC(x) ((x) * 16 / 133)
#define USEC_TO_COUNT(x) ((x) * 133 / 16)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
#define TIMER_LOAD_VAL 0xffffffff
/*
* MTU timer to use (from 0 to 3).
*/
#define MTU_TIMER 2
static struct u8500_mtu_timer *timer_base =
&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(&timer_base->cv))
/* Configure a free-running, auto-wrap counter with /16 prescaler */
int timer_init(void)
{
writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
&timer_base->cr);
return 0;
}
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = TICKS_TO_HZ(READ_TIMER());
if (now >= gd->arch.lastinc) { /* normal (non rollover) */
gd->arch.tbl += (now - gd->arch.lastinc);
} else { /* rollover */
gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
gd->arch.lastinc) + now;
}
gd->arch.lastinc = now;
return gd->arch.tbl;
}
/* Delay x useconds */
void __udelay(ulong usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
ulong now, last = READ_TIMER();
while (tmo > 0) {
now = READ_TIMER();
if (now > last) /* normal (non rollover) */
tmo -= now - last;
else /* rollover */
tmo -= TIMER_LOAD_VAL - last + now;
last = now;
}
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* Emulation of Power architecture long long timebase.
*
* TODO: Support gd->arch.tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* Emulation of Power architecture timebase.
* NB: Low resolution compared to Power tbclk.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

2
arch/arm/cpu/armv8/start.S
View File

@ -54,8 +54,10 @@ reset:
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
#ifdef COUNTER_FREQUENCY
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif
b 0f
2: msr vbar_el2, x0
mov x0, #0x33ff

17
arch/arm/dts/Makefile
View File

@ -39,13 +39,17 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-pro5-4kbox.dtb \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-sld8-ref.dtb
uniphier-ph1-sld8-ref.dtb \
uniphier-proxstream2-gentil.dtb \
uniphier-proxstream2-vodka.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
@ -81,9 +85,11 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet1.dtb \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
@ -91,13 +97,15 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb
sun4i-a10-pcduino.dtb \
sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
sun5i-a13-forfun-q88db.dtb \
sun5i-a13-hsg-h702.dtb \
@ -105,6 +113,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-tzx-q8-713b7.dtb \
sun5i-a13-utoo-p66.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
@ -144,11 +153,13 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \

4
arch/arm/dts/exynos4210-trats.dts
View File

@ -117,4 +117,8 @@
sdhci@12540000 {
status = "disabled";
};
dwmmc@12550000 {
status = "disabled";
};
};

16
arch/arm/dts/ls1021a-twr.dts
View File

@ -17,6 +17,7 @@
enet0_sgmii_phy = &sgmii_phy2;
enet1_sgmii_phy = &sgmii_phy0;
spi0 = &qspi;
spi1 = &dspi1;
};
};
@ -33,6 +34,21 @@
};
};
&dspi1 {
bus-num = <0>;
status = "okay";
dspiflash: at26df081a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
};
&i2c0 {
status = "okay";
};

226
arch/arm/dts/sun4i-a10-inet1.dts Normal file
View File

@ -0,0 +1,226 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun4i-a10.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "iNet-1";
compatible = "inet-tek,inet1", "allwinner,sun4i-a10";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
};
};
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
/* Accelerometer */
bma250@18 {
compatible = "bosch,bma250";
reg = <0x18>;
interrupt-parent = <&pio>;
interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button@200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
button@1000 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <1000000>;
};
button@1200 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <1200000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
cd-inverted;
status = "okay";
};
&ohci0 {
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-int-dll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_usb0_vbus {
status = "okay";
};
&reg_usb1_vbus {
status = "okay";
};
&reg_usb2_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};

219
arch/arm/dts/sun4i-a10-inet9f-rev03.dts Normal file
View File

@ -0,0 +1,219 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun4i-a10.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "iNet-9F Rev 03";
compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci1 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
};
};
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button@200 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <200000>;
};
button@600 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <600000>;
};
button@800 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <800000>;
};
button@1000 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <1000000>;
};
button@1200 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
voltage = <1200000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
cd-inverted;
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-int-dll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_usb0_vbus {
status = "okay";
};
&reg_usb2_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};

209
arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts Normal file
View File

@ -0,0 +1,209 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun4i-a10.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Point of View Protab2-IPS9";
compatible = "pov,protab2-ips9", "allwinner,sun4i-a10";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
};
};
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button@400 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <400000>;
};
button@800 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <800000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
cd-inverted;
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PH4";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
allwinner,pins = "PH5";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-int-dll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_ldo3 {
/*
* We need to always power the camera sensor, otherwhise all access
* to i2c1 is blocked.
*/
regulator-always-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vdd-csi";
};
&reg_usb0_vbus {
status = "okay";
};
&reg_usb1_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

224
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@ -0,0 +1,224 @@
/*
* Copyright 2015 Jelle van der Waa <jelle@vdwaa.nl>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun5i-a10s.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "A10s-Wobo i5";
compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_wobo_i5>;
blue {
label = "a10s-wobo-i5:blue:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_emac_3v3: emac-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&emac_power_pin_wobo>;
regulator-name = "emac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>;
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins_b>;
phy = <&phy1>;
status = "okay";
};
&emac_sram {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
};
};
#include "axp209.dtsi"
&mdio {
phy-supply = <&reg_emac_3v3>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
cd-inverted;
status = "okay";
};
&ohci0 {
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
led_pins_wobo_i5: led_pins@0 {
allwinner,pins = "PB2";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
allwinner,pins = "PB3";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
emac_power_pin_wobo: emac_power_pin@0 {
allwinner,pins = "PA02";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd-int-dll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_ldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&reg_usb1_vbus {
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usb1_vbus_pin_a {
allwinner,pins = "PG12";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

11
arch/arm/dts/sun5i-a10s.dtsi
View File

@ -194,6 +194,17 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_pins_b: emac0@1 {
allwinner,pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
"PD21", "PD22", "PD23", "PD24",
"PD25", "PD26", "PD27";
allwinner,function = "emac";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc1_pins_a: mmc1@0 {
allwinner,pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";

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/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun5i-a13.dtsi"
#include "sun5i-q8-common.dtsi"
/ {
model = "Q8 A13 Tablet";
compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
};
&reg_ldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&usbphy {
usb1_vbus-supply = <&reg_ldo3>;
};

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/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sunxi-q8-common.dtsi"
/ {
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&i2c0 {
axp209: pmic@34 {
reg = <0x34>;
interrupts = <0>;
};
};
&i2c1 {
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
#include "axp209.dtsi"
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
cd-inverted;
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
mmc0_cd_pin_q8: mmc0_cd_pin@0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
allwinner,pins = "PG1";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
};
usb0_id_detect_pin: usb0_id_detect_pin@0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
usb0_vbus_pin_a: usb0_vbus_pin@0 {
allwinner,pins = "PG12";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-int-pll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_usb0_vbus {
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_b>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};

65
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@ -0,0 +1,65 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a23.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A23 Tablet";
compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
};
/*
* FIXME for now we only support host mode and rely on u-boot to have
* turned on Vbus which is controlled by the axp223 pmic on the board.
*
* Once we have axp223 support we should switch to fully supporting otg.
*/
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
status = "okay";
};

65
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@ -0,0 +1,65 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-a33.dtsi"
#include "sun8i-q8-common.dtsi"
/ {
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
/*
* FIXME for now we only support host mode and rely on u-boot to have
* turned on Vbus which is controlled by the axp223 pmic on the board.
*
* Once we have axp223 support we should switch to fully supporting otg.
*/
&usb_otg {
dr_mode = "host";
status = "okay";
};
&usbphy {
status = "okay";
};

84
arch/arm/dts/sun8i-q8-common.dtsi Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sunxi-q8-common.dtsi"
/ {
aliases {
serial0 = &r_uart;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
status = "okay";
};
&pio {
bl_en_pin_q8: bl_en_pin@0 {
allwinner,pins = "PH6";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_q8: mmc0_cd_pin@0 {
allwinner,pins = "PB4";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
};
&r_uart {
pinctrl-names = "default";
pinctrl-0 = <&r_uart_pins_a>;
status = "okay";
};

77
arch/arm/dts/sunxi-q8-common.dtsi Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include "sunxi-common-regulators.dtsi"
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&lradc {
vref-supply = <&reg_vcc3v0>;
status = "okay";
button@200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
button@400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <400000>;
};
};

57
arch/arm/dts/tegra20.dtsi
View File

@ -320,6 +320,63 @@
clocks = <&tegra_car 47>, <&tegra_car 124>;
};
spi@7000d400 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d400 0x200>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC1>;
resets = <&tegra_car 41>;
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d600 0x200>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC2>;
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000d800 0x200>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC3>;
resets = <&tegra_car 46>;
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra20-slink";
reg = <0x7000da00 0x200>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SBC4>;
resets = <&tegra_car 68>;
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
status = "disabled";
};
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;

60
arch/arm/dts/tegra210-p2371-2180.dts Normal file
View File

@ -0,0 +1,60 @@
/dts-v1/;
#include "tegra210.dtsi"
/ {
model = "NVIDIA P2371-2180";
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
chosen {
stdout-path = &uarta;
};
aliases {
i2c0 = "/i2c@0,7000d000";
sdhci0 = "/sdhci@0,700b0600";
sdhci1 = "/sdhci@0,700b0000";
usb0 = "/usb@0,7d000000";
};
memory {
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
sdhci@0,700b0000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
sdhci@0,700b0600 {
status = "okay";
bus-width = <8>;
};
i2c@0,7000d000 {
status = "okay";
clock-frequency = <400000>;
};
usb@0,7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

18
arch/arm/dts/uniphier-ph1-ld4-ref.dts
View File

@ -61,6 +61,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

19
arch/arm/dts/uniphier-ph1-ld6b-ref.dts
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
@ -54,6 +55,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/uniphier-ph1-pro4-ref.dts
View File

@ -68,6 +68,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

64
arch/arm/dts/uniphier-ph1-pro5-4kbox.dts Normal file
View File

@ -0,0 +1,64 @@
/*
* Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-ph1-pro5.dtsi"
/ {
model = "UniPhier PH1-Pro5 4KBOX Board";
compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
chosen {
bootargs = "console=ttyS1,115200";
stdout-path = &serial1;
};
aliases {
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial1 {
status = "okay";
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial1 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/uniphier-ph1-sld8-ref.dts
View File

@ -65,6 +65,20 @@
};
/* for U-boot only */
&serial0 {
u-boot,dm-pre-reloc;
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

38
arch/arm/dts/uniphier-pinctrl.dtsi
View File

@ -3,43 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
* SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {

62
arch/arm/dts/uniphier-proxstream2-gentil.dts Normal file
View File

@ -0,0 +1,62 @@
/*
* Device Tree Source for UniPhier ProXstream2 Gentil Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/ {
model = "UniPhier ProXstream2 Gentil Board";
compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
chosen {
bootargs = "console=ttyS2,115200";
stdout-path = &serial2;
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

62
arch/arm/dts/uniphier-proxstream2-vodka.dts Normal file
View File

@ -0,0 +1,62 @@
/*
* Device Tree Source for UniPhier ProXstream2 Vodka Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "uniphier-proxstream2.dtsi"
/ {
model = "UniPhier ProXstream2 Vodka Board";
compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
chosen {
bootargs = "console=ttyS2,115200";
stdout-path = &serial2;
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
i2c0 = &i2c0;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&serial2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
/* for U-boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

10
arch/arm/imx-common/Makefile
View File

@ -7,7 +7,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
obj-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
@ -18,7 +18,13 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
ifeq ($(SOC),$(filter $(SOC),mx7))
obj-y += cpu.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif

103
arch/arm/imx-common/cache.c Normal file
View File

@ -0,0 +1,103 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/io.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
enum dcache_option option = DCACHE_WRITETHROUGH;
#else
enum dcache_option option = DCACHE_WRITEBACK;
#endif
/* Avoid random hang when download by usb */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
/* Enable caching on OCRAM and ROM */
mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,
option);
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,
option);
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
#ifdef CONFIG_SYS_L2_PL310
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
unsigned int val;
/*
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
* accesses as Cacheable no-allocate.
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
#if defined CONFIG_MX6SL
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
val = readl(&iomux->gpr[11]);
if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
/* L2 cache configured as OCRAM, reset it */
val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
writel(val, &iomux->gpr[11]);
}
#endif
/* Must disable the L2 before changing the latency parameters */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
val = readl(&pl310->pl310_prefetch_ctrl);
/* Turn on the L2 I/D prefetch */
val |= 0x30000000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
* But according to ARM PL310 errata: 752271
* ID: 752271: Double linefill feature can cause data corruption
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
* Workaround: The only workaround to this erratum is to disable the
* double linefill feature. This is the default behavior.
*/
#ifndef CONFIG_MX6Q
val |= 0x40800000;
#endif
writel(val, &pl310->pl310_prefetch_ctrl);
val = readl(&pl310->pl310_power_ctrl);
val |= L2X0_DYNAMIC_CLK_GATING_EN;
val |= L2X0_STNDBY_MODE_EN;
writel(val, &pl310->pl310_power_ctrl);
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2_PL310 */
#endif /* !CONFIG_SYS_L2CACHE_OFF */

35
arch/arm/imx-common/cpu.c
View File

@ -46,13 +46,28 @@ static char *get_reset_cause(void)
case 0x00008:
return "IPP USER";
case 0x00010:
#ifdef CONFIG_MX7
return "WDOG1";
#else
return "WDOG";
#endif
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
case 0x00080:
return "WDOG3";
#ifdef CONFIG_MX7
case 0x00100:
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
#else
case 0x00100:
return "TEMPSENSE";
case 0x10000:
return "WARM BOOT";
#endif
default:
return "unknown reset";
}
@ -122,6 +137,8 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_MX7D:
return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
return "6QP"; /* Quad-Plus version of the mx6 */
case MXC_CPU_MX6DP:
@ -154,14 +171,12 @@ int print_cpuinfo(void)
u32 cpurev;
__maybe_unused u32 max_freq;
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
#endif
cpurev = get_cpu_rev();
#if defined(CONFIG_MX6)
#if defined(CONFIG_IMX_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
printf("CPU: Freescale i.MX%s rev%d.%d",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
@ -181,7 +196,7 @@ int print_cpuinfo(void)
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
#if defined(CONFIG_IMX_THERMAL)
puts("CPU: ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
@ -205,9 +220,9 @@ int print_cpuinfo(void)
if (!ret)
printf(" at %dC\n", cpu_tmp);
else
puts(" - invalid sensor data\n");
debug(" - invalid sensor data\n");
} else {
puts(" - invalid sensor device\n");
debug(" - invalid sensor device\n");
}
#endif
@ -238,6 +253,7 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
#ifndef CONFIG_MX7
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -249,6 +265,7 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
#endif
void arch_preboot_os(void)
{

189
arch/arm/imx-common/ddrmc-vf610.c
View File

@ -12,9 +12,9 @@
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
void ddrmc_setup_iomux(void)
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
static const iomux_v3_cfg_t ddr_pads[] = {
static const iomux_v3_cfg_t default_pads[] = {
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
VF610_PAD_DDR_RESETB,
};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
if ((pads == NULL) || (pads_count == 0)) {
pads = default_pads;
pads_count = ARRAY_SIZE(default_pads);
}
imx_iomux_v3_setup_multiple_pads(pads, pads_count);
}
void ddrmc_phy_init(void)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
static struct ddrmc_phy_setting default_phy_settings[] = {
{ DDRMC_PHY_DQ_TIMING, 0 },
{ DDRMC_PHY_DQ_TIMING, 16 },
{ DDRMC_PHY_DQ_TIMING, 32 },
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
{ DDRMC_PHY_DQS_TIMING, 1 },
{ DDRMC_PHY_DQS_TIMING, 17 },
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
{ DDRMC_PHY_CTRL, 2 },
{ DDRMC_PHY_CTRL, 18 },
{ DDRMC_PHY_CTRL, 34 },
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
{ DDRMC_PHY_MASTER_CTRL, 3 },
{ DDRMC_PHY_MASTER_CTRL, 19 },
{ DDRMC_PHY_MASTER_CTRL, 35 },
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
{ DDRMC_PHY_SLAVE_CTRL, 4 },
{ DDRMC_PHY_SLAVE_CTRL, 20 },
{ DDRMC_PHY_SLAVE_CTRL, 36 },
/* LPDDR2 only parameter */
writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
{ DDRMC_PHY_OFF, 49 },
writel(DDRMC_PHY50_DDR3_MODE |
DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
/* Processor Pad ODT settings */
writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
}
{ DDRMC_PHY_PROC_PAD_ODT, 52 },
static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
if (lvl->wrlvl_reg_en) {
writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
}
if (lvl->rdlvl_reg_en) {
cr102 |= DDRMC_CR102_RDLVL_REG_EN;
cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
}
if (lvl->rdlvl_gt_reg_en) {
cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
}
writel(cr102, &ddrmr->cr[102]);
writel(cr105, &ddrmr->cr[105]);
writel(cr106, &ddrmr->cr[106]);
writel(cr110, &ddrmr->cr[110]);
}
/* end marker */
{ 0, -1 }
};
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
struct ddrmc_lvl_info *lvl,
int col_diff, int row_diff)
struct ddrmc_cr_setting *board_cr_settings,
struct ddrmc_phy_setting *board_phy_settings,
int col_diff, int row_diff)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
struct ddrmc_cr_setting *cr_setting;
struct ddrmc_phy_setting *phy_setting;
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR12_WRLAT(timings->wrlat) |
DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
DDRMC_CR13_TCCD(timings->tccd) |
DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
&ddrmr->cr[13]);
writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
DDRMC_CR14_TWTR(timings->twtr) |
DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
&ddrmr->cr[21]);
writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
writel(DDRMC_CR23_BSTLEN(3) |
writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
writel(DDRMC_CR26_TREF(timings->tref) |
DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR34_CKSRX(timings->cksrx) |
DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(timings->aprebit) |
DDRMC_CR73_COL_DIFF(col_diff) |
DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
DDRMC_CR74_AGE_CNT(timings->age_cnt),
&ddrmr->cr[74]);
writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
DDRMC_CR75_PLEN, &ddrmr->cr[75]);
@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
writel(DDRMC_CR78_Q_FULLNESS(7) |
writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
&ddrmr->cr[87]);
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
if (lvl != NULL)
ddrmc_ctrl_lvl_init(lvl);
/* execute custom CR setting sequence (may be NULL) */
cr_setting = board_cr_settings;
if (cr_setting != NULL)
while (cr_setting->cr_rnum >= 0) {
writel(cr_setting->setting,
&ddrmr->cr[cr_setting->cr_rnum]);
cr_setting++;
}
writel(DDRMC_CR117_AXI0_W_PRI(0) |
DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
writel(DDRMC_CR118_AXI1_W_PRI(1) |
DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
/* perform default PHY settings (may be overriden by custom settings */
phy_setting = default_phy_settings;
while (phy_setting->phy_rnum >= 0) {
writel(phy_setting->setting,
&ddrmr->phy[phy_setting->phy_rnum]);
phy_setting++;
}
writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
writel(DDRMC_CR132_WRLAT_ADJ(5) |
DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
DDRMC_CR139_PHY_WRLV_DLL(3) |
DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) |
DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1) |
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
ddrmc_phy_init();
/* execute custom PHY setting sequence (may be NULL) */
phy_setting = board_phy_settings;
if (phy_setting != NULL)
while (phy_setting->phy_rnum >= 0) {
writel(phy_setting->setting,
&ddrmr->phy[phy_setting->phy_rnum]);
phy_setting++;
}
/* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
while (!(readl(&ddrmr->cr[80]) && 0x100))

118
arch/arm/imx-common/init.c Normal file
View File

@ -0,0 +1,118 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/arch/crm_regs.h>
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2, *aips3;
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips1->mprot0);
writel(0x77777777, &aips1->mprot1);
writel(0x77777777, &aips2->mprot0);
writel(0x77777777, &aips2->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips1->opacr0);
writel(0x00000000, &aips1->opacr1);
writel(0x00000000, &aips1->opacr2);
writel(0x00000000, &aips1->opacr3);
writel(0x00000000, &aips1->opacr4);
writel(0x00000000, &aips2->opacr0);
writel(0x00000000, &aips2->opacr1);
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
}
}
void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
#ifdef CONFIG_MX7D
struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
#endif
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
is_soc_type(MXC_SOC_MX7))
writew(enable, &wdog3->wmcr);
#ifdef CONFIG_MX7D
writew(enable, &wdog4->wmcr);
#endif
}
#define SRC_SCR_WARM_RESET_ENABLE 0
void init_src(void)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
/*
* force warm reset sources to generate cold reset
* for a more reliable restart
*/
val = readl(&src_regs->scr);
val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
writel(val, &src_regs->scr);
}
#ifdef CONFIG_CMD_BMODE
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
struct src *psrc = (struct src *)SRC_BASE_ADDR;
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
reg |= 1 << 28;
else
reg &= ~(1 << 28);
writel(reg, &psrc->gpr10);
}
#endif

6
arch/arm/imx-common/iomux-v3.c
View File

@ -11,10 +11,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
#include <asm/arch/sys_proto.h>
#endif
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/sys_proto.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
@ -53,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
}
#endif
if (mux_ctrl_ofs)
if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)

126
arch/arm/imx-common/syscounter.c Normal file
View File

@ -0,0 +1,126 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* The file use ls102xa/timer.c as a reference.
*/
#include <common.h>
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/syscounter.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* This function is intended for SHORT delays only.
* It will overflow at around 10 seconds @ 400MHz,
* or 20 seconds @ 200MHz.
*/
unsigned long usec2ticks(unsigned long usec)
{
ulong ticks;
if (usec < 1000)
ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
else
ticks = ((usec / 10) * (get_tbclk() / 100000));
return ticks;
}
static inline unsigned long long tick_to_time(unsigned long long tick)
{
unsigned long freq;
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
tick *= CONFIG_SYS_HZ;
do_div(tick, freq);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
unsigned long freq;
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
usec = usec * freq + 999999;
do_div(usec, 1000000);
return usec;
}
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
unsigned long val, freq;
freq = CONFIG_SC_TIMER_CLK;
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
writel(freq, &sctr->cntfid0);
/* Enable system counter */
val = readl(&sctr->cntcr);
val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
writel(val, &sctr->cntcr);
gd->arch.tbl = 0;
gd->arch.tbu = 0;
return 0;
}
unsigned long long get_ticks(void)
{
unsigned long long now;
asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
gd->arch.tbl = (unsigned long)(now & 0xffffffff);
gd->arch.tbu = (unsigned long)(now >> 32);
return now;
}
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
unsigned long freq;
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
return freq;
}

1
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -17,7 +17,6 @@
#include <asm/arch/hardware.h>
#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */

2
arch/arm/include/asm/arch-hi6220/gpio.h
View File

@ -11,8 +11,6 @@
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
0xf7020000 - 0x4000) + (0x1000 * bank))
#define BIT(x) (1 << (x))
#define HI6220_GPIO_PER_BANK 8
#define HI6220_GPIO_DIR 0x400

3
arch/arm/include/asm/arch-hi6220/hi6220.h
View File

@ -13,6 +13,9 @@
#define HI6220_MMC0_BASE 0xF723D000
#define HI6220_MMC1_BASE 0xF723E000
#define HI6220_UART0_BASE 0xF8015000
#define HI6220_UART3_BASE 0xF7113000
#define HI6220_PMUSSI_BASE 0xF8000000
#define HI6220_PERI_BASE 0xF7030000

4
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -21,8 +21,12 @@
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2

3
arch/arm/include/asm/arch-lpc32xx/clk.h
View File

@ -158,9 +158,6 @@ struct clk_pm_regs {
#define CLK_NAND_SLC_SELECT (1 << 2)
#define CLK_NAND_MLC_INT (1 << 5)
/* DMA Clock Control Register bits */
#define DMA_CLK_ENABLE (1 << 0)
/* SSP Clock Control Register bits */
#define CLK_SSP0_ENABLE_CLOCK (1 << 0)

2
arch/arm/include/asm/arch-lpc32xx/emc.h
View File

@ -70,7 +70,7 @@ struct emc_regs {
/* Static Memory Delay Registers */
#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
#define EMC_STAT_WAITOEN(n) ((n) & 0x0F)
#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)

4
arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
View File

@ -12,7 +12,7 @@
/*
* Macro to map the pin for the lpc32xx_gpio driver.
* Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127;
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
@ -26,9 +26,9 @@
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
#define LPC32XX_GPI_P3_GRP 96
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro

4
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -137,8 +137,10 @@
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
@ -219,6 +221,8 @@
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)

348
arch/arm/include/asm/arch-mx7/clock.h Normal file
View File

@ -0,0 +1,348 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* Author:
* Peng Fan <Peng.Fan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CLOCK_H
#define _ASM_ARCH_CLOCK_H
#include <common.h>
#include <asm/arch/crm_regs.h>
#ifdef CONFIG_SYS_MX7_HCLK
#define MXC_HCLK CONFIG_SYS_MX7_HCLK
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_SYS_MX7_CLK32
#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
#else
#define MXC_CLK32 32768
#endif
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
MXC_AXI_CLK,
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_I2C_CLK,
};
/* PLL supported by i.mx7d */
enum pll_clocks {
PLL_CORE, /* Core PLL */
PLL_SYS, /* System PLL*/
PLL_ENET, /* Enet PLL */
PLL_AUDIO, /* Audio PLL */
PLL_VIDEO, /* Video PLL*/
PLL_DDR, /* Dram PLL */
PLL_USB, /* USB PLL, fixed at 480MHZ */
};
/* clk src for clock root gen */
enum clk_root_src {
OSC_24M_CLK,
PLL_ARM_MAIN_800M_CLK,
PLL_SYS_MAIN_480M_CLK,
PLL_SYS_MAIN_240M_CLK,
PLL_SYS_MAIN_120M_CLK,
PLL_SYS_PFD0_392M_CLK,
PLL_SYS_PFD0_196M_CLK,
PLL_SYS_PFD1_332M_CLK,
PLL_SYS_PFD1_166M_CLK,
PLL_SYS_PFD2_270M_CLK,
PLL_SYS_PFD2_135M_CLK,
PLL_SYS_PFD3_CLK,
PLL_SYS_PFD4_CLK,
PLL_SYS_PFD5_CLK,
PLL_SYS_PFD6_CLK,
PLL_SYS_PFD7_CLK,
PLL_ENET_MAIN_500M_CLK,
PLL_ENET_MAIN_250M_CLK,
PLL_ENET_MAIN_125M_CLK,
PLL_ENET_MAIN_100M_CLK,
PLL_ENET_MAIN_50M_CLK,
PLL_ENET_MAIN_40M_CLK,
PLL_ENET_MAIN_25M_CLK,
PLL_DRAM_MAIN_1066M_CLK,
PLL_DRAM_MAIN_533M_CLK,
PLL_AUDIO_MAIN_CLK,
PLL_VIDEO_MAIN_CLK,
PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
EXT_CLK_1,
EXT_CLK_2,
EXT_CLK_3,
EXT_CLK_4,
REF_1M_CLK,
OSC_32K_CLK,
};
/*
* Clock root index
*/
enum clk_root_index {
ARM_A7_CLK_ROOT = 0,
ARM_M4_CLK_ROOT = 1,
ARM_M0_CLK_ROOT = 2,
MAIN_AXI_CLK_ROOT = 16,
DISP_AXI_CLK_ROOT = 17,
ENET_AXI_CLK_ROOT = 18,
NAND_USDHC_BUS_CLK_ROOT = 19,
AHB_CLK_ROOT = 32,
DRAM_PHYM_CLK_ROOT = 48,
DRAM_CLK_ROOT = 49,
DRAM_PHYM_ALT_CLK_ROOT = 64,
DRAM_ALT_CLK_ROOT = 65,
USB_HSIC_CLK_ROOT = 66,
PCIE_CTRL_CLK_ROOT = 67,
PCIE_PHY_CLK_ROOT = 68,
EPDC_PIXEL_CLK_ROOT = 69,
LCDIF_PIXEL_CLK_ROOT = 70,
MIPI_DSI_EXTSER_CLK_ROOT = 71,
MIPI_CSI_WARP_CLK_ROOT = 72,
MIPI_DPHY_REF_CLK_ROOT = 73,
SAI1_CLK_ROOT = 74,
SAI2_CLK_ROOT = 75,
SAI3_CLK_ROOT = 76,
SPDIF_CLK_ROOT = 77,
ENET1_REF_CLK_ROOT = 78,
ENET1_TIME_CLK_ROOT = 79,
ENET2_REF_CLK_ROOT = 80,
ENET2_TIME_CLK_ROOT = 81,
ENET_PHY_REF_CLK_ROOT = 82,
EIM_CLK_ROOT = 83,
NAND_CLK_ROOT = 84,
QSPI_CLK_ROOT = 85,
USDHC1_CLK_ROOT = 86,
USDHC2_CLK_ROOT = 87,
USDHC3_CLK_ROOT = 88,
CAN1_CLK_ROOT = 89,
CAN2_CLK_ROOT = 90,
I2C1_CLK_ROOT = 91,
I2C2_CLK_ROOT = 92,
I2C3_CLK_ROOT = 93,
I2C4_CLK_ROOT = 94,
UART1_CLK_ROOT = 95,
UART2_CLK_ROOT = 96,
UART3_CLK_ROOT = 97,
UART4_CLK_ROOT = 98,
UART5_CLK_ROOT = 99,
UART6_CLK_ROOT = 100,
UART7_CLK_ROOT = 101,
ECSPI1_CLK_ROOT = 102,
ECSPI2_CLK_ROOT = 103,
ECSPI3_CLK_ROOT = 104,
ECSPI4_CLK_ROOT = 105,
PWM1_CLK_ROOT = 106,
PWM2_CLK_ROOT = 107,
PWM3_CLK_ROOT = 108,
PWM4_CLK_ROOT = 109,
FLEXTIMER1_CLK_ROOT = 110,
FLEXTIMER2_CLK_ROOT = 111,
SIM1_CLK_ROOT = 112,
SIM2_CLK_ROOT = 113,
GPT1_CLK_ROOT = 114,
GPT2_CLK_ROOT = 115,
GPT3_CLK_ROOT = 116,
GPT4_CLK_ROOT = 117,
TRACE_CLK_ROOT = 118,
WDOG_CLK_ROOT = 119,
CSI_MCLK_CLK_ROOT = 120,
AUDIO_MCLK_CLK_ROOT = 121,
WRCLK_CLK_ROOT = 122,
IPP_DO_CLKO1 = 123,
IPP_DO_CLKO2 = 124,
CLK_ROOT_MAX,
};
struct clk_root_setting {
enum clk_root_index root;
u32 setting;
};
/*
* CCGR mapping
*/
enum clk_ccgr_index {
CCGR_CPU = 0,
CCGR_M4 = 1,
CCGR_SIM_MAIN = 4,
CCGR_SIM_DISPLAY = 5,
CCGR_SIM_ENET = 6,
CCGR_SIM_M = 7,
CCGR_SIM_S = 8,
CCGR_SIM_WAKEUP = 9,
CCGR_IPMUX1 = 10,
CCGR_IPMUX2 = 11,
CCGR_IPMUX3 = 12,
CCGR_ROM = 16,
CCGR_OCRAM = 17,
CCGR_OCRAM_S = 18,
CCGR_DRAM = 19,
CCGR_RAWNAND = 20,
CCGR_QSPI = 21,
CCGR_WEIM = 22,
CCGR_ADC = 32,
CCGR_ANATOP = 33,
CCGR_SCTR = 34,
CCGR_OCOTP = 35,
CCGR_CAAM = 36,
CCGR_SNVS = 37,
CCGR_RDC = 38,
CCGR_MU = 39,
CCGR_HS = 40,
CCGR_DVFS = 41,
CCGR_QOS = 42,
CCGR_QOS_DISPMIX = 43,
CCGR_QOS_MEGAMIX = 44,
CCGR_CSU = 45,
CCGR_DBGMON = 46,
CCGR_DEBUG = 47,
CCGR_TRACE = 48,
CCGR_SEC_DEBUG = 49,
CCGR_SEMA1 = 64,
CCGR_SEMA2 = 65,
CCGR_PERFMON1 = 68,
CCGR_PERFMON2 = 69,
CCGR_SDMA = 72,
CCGR_CSI = 73,
CCGR_EPDC = 74,
CCGR_LCDIF = 75,
CCGR_PXP = 76,
CCGR_PCIE = 96,
CCGR_MIPI_CSI = 100,
CCGR_MIPI_DSI = 101,
CCGR_MIPI_MEM_PHY = 102,
CCGR_USB_CTRL = 104,
CCGR_USB_HSIC = 105,
CCGR_USB_PHY1 = 106,
CCGR_USB_PHY2 = 107,
CCGR_USDHC1 = 108,
CCGR_USDHC2 = 109,
CCGR_USDHC3 = 110,
CCGR_ENET1 = 112,
CCGR_ENET2 = 113,
CCGR_CAN1 = 116,
CCGR_CAN2 = 117,
CCGR_ECSPI1 = 120,
CCGR_ECSPI2 = 121,
CCGR_ECSPI3 = 122,
CCGR_ECSPI4 = 123,
CCGR_GPT1 = 124,
CCGR_GPT2 = 125,
CCGR_GPT3 = 126,
CCGR_GPT4 = 127,
CCGR_FTM1 = 128,
CCGR_FTM2 = 129,
CCGR_PWM1 = 132,
CCGR_PWM2 = 133,
CCGR_PWM3 = 134,
CCGR_PWM4 = 135,
CCGR_I2C1 = 136,
CCGR_I2C2 = 137,
CCGR_I2C3 = 138,
CCGR_I2C4 = 139,
CCGR_SAI1 = 140,
CCGR_SAI2 = 141,
CCGR_SAI3 = 142,
CCGR_SIM1 = 144,
CCGR_SIM2 = 145,
CCGR_UART1 = 148,
CCGR_UART2 = 149,
CCGR_UART3 = 150,
CCGR_UART4 = 151,
CCGR_UART5 = 152,
CCGR_UART6 = 153,
CCGR_UART7 = 154,
CCGR_WDOG1 = 156,
CCGR_WDOG2 = 157,
CCGR_WDOG3 = 158,
CCGR_WDOG4 = 159,
CCGR_GPIO1 = 160,
CCGR_GPIO2 = 161,
CCGR_GPIO3 = 162,
CCGR_GPIO4 = 163,
CCGR_GPIO5 = 164,
CCGR_GPIO6 = 165,
CCGR_GPIO7 = 166,
CCGR_IOMUX = 168,
CCGR_IOMUX_LPSR = 169,
CCGR_KPP = 170,
CCGR_SKIP,
CCGR_MAX,
};
/* Clock root channel */
enum clk_root_type {
CCM_CORE_CHANNEL,
CCM_BUS_CHANNEL,
CCM_AHB_CHANNEL,
CCM_DRAM_PHYM_CHANNEL,
CCM_DRAM_CHANNEL,
CCM_IP_CHANNEL,
};
#include <asm/arch/clock_slice.h>
/*
* entry: the clock root index
* type: ccm channel
* src_mux: each entry corresponding to the clock src, detailed info in CCM RM
*/
struct clk_root_map {
enum clk_root_index entry;
enum clk_root_type type;
uint8_t src_mux[8];
};
enum enet_freq {
ENET_25MHz,
ENET_50MHz,
ENET_125MHz,
};
u32 get_root_clk(enum clk_root_index clock_id);
u32 mxc_get_clock(enum mxc_clock clk);
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
void clock_init(void);
#ifdef CONFIG_SYS_I2C_MXC
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#endif
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type);
#endif
int set_clk_qspi(void);
int set_clk_nand(void);
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
void enable_usboh3_clk(unsigned char enable);
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable);
#endif
void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
void enable_thermal_clk(void);
#endif

116
arch/arm/include/asm/arch-mx7/clock_slice.h Normal file
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@ -0,0 +1,116 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* Author:
* Peng Fan <Peng.Fan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CLOCK_SLICE_H
#define _ASM_ARCH_CLOCK_SLICE_H
enum root_pre_div {
CLK_ROOT_PRE_DIV1 = 0,
CLK_ROOT_PRE_DIV2,
CLK_ROOT_PRE_DIV3,
CLK_ROOT_PRE_DIV4,
CLK_ROOT_PRE_DIV5,
CLK_ROOT_PRE_DIV6,
CLK_ROOT_PRE_DIV7,
CLK_ROOT_PRE_DIV8,
};
enum root_post_div {
CLK_ROOT_POST_DIV1 = 0,
CLK_ROOT_POST_DIV2,
CLK_ROOT_POST_DIV3,
CLK_ROOT_POST_DIV4,
CLK_ROOT_POST_DIV5,
CLK_ROOT_POST_DIV6,
CLK_ROOT_POST_DIV7,
CLK_ROOT_POST_DIV8,
CLK_ROOT_POST_DIV9,
CLK_ROOT_POST_DIV10,
CLK_ROOT_POST_DIV11,
CLK_ROOT_POST_DIV12,
CLK_ROOT_POST_DIV13,
CLK_ROOT_POST_DIV14,
CLK_ROOT_POST_DIV15,
CLK_ROOT_POST_DIV16,
CLK_ROOT_POST_DIV17,
CLK_ROOT_POST_DIV18,
CLK_ROOT_POST_DIV19,
CLK_ROOT_POST_DIV20,
CLK_ROOT_POST_DIV21,
CLK_ROOT_POST_DIV22,
CLK_ROOT_POST_DIV23,
CLK_ROOT_POST_DIV24,
CLK_ROOT_POST_DIV25,
CLK_ROOT_POST_DIV26,
CLK_ROOT_POST_DIV27,
CLK_ROOT_POST_DIV28,
CLK_ROOT_POST_DIV29,
CLK_ROOT_POST_DIV30,
CLK_ROOT_POST_DIV31,
CLK_ROOT_POST_DIV32,
CLK_ROOT_POST_DIV33,
CLK_ROOT_POST_DIV34,
CLK_ROOT_POST_DIV35,
CLK_ROOT_POST_DIV36,
CLK_ROOT_POST_DIV37,
CLK_ROOT_POST_DIV38,
CLK_ROOT_POST_DIV39,
CLK_ROOT_POST_DIV40,
CLK_ROOT_POST_DIV41,
CLK_ROOT_POST_DIV42,
CLK_ROOT_POST_DIV43,
CLK_ROOT_POST_DIV44,
CLK_ROOT_POST_DIV45,
CLK_ROOT_POST_DIV46,
CLK_ROOT_POST_DIV47,
CLK_ROOT_POST_DIV48,
CLK_ROOT_POST_DIV49,
CLK_ROOT_POST_DIV50,
CLK_ROOT_POST_DIV51,
CLK_ROOT_POST_DIV52,
CLK_ROOT_POST_DIV53,
CLK_ROOT_POST_DIV54,
CLK_ROOT_POST_DIV55,
CLK_ROOT_POST_DIV56,
CLK_ROOT_POST_DIV57,
CLK_ROOT_POST_DIV58,
CLK_ROOT_POST_DIV59,
CLK_ROOT_POST_DIV60,
CLK_ROOT_POST_DIV61,
CLK_ROOT_POST_DIV62,
CLK_ROOT_POST_DIV63,
CLK_ROOT_POST_DIV64,
};
enum root_auto_div {
CLK_ROOT_AUTO_DIV1 = 0,
CLK_ROOT_AUTO_DIV2,
CLK_ROOT_AUTO_DIV4,
CLK_ROOT_AUTO_DIV8,
CLK_ROOT_AUTO_DIV16,
};
int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
int auto_en);
int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
int *auto_en);
int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
int clock_set_target_val(enum clk_root_index clock_id, u32 val);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
enum root_post_div post_div, enum clk_root_src clock_src);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_enable(enum clk_ccgr_index index, bool enable);
#endif

2813
arch/arm/include/asm/arch-mx7/crm_regs.h Normal file
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File diff suppressed because it is too large Load Diff

1307
arch/arm/include/asm/arch-mx7/imx-regs.h Normal file
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File diff suppressed because it is too large Load Diff

9
arch/arm/include/asm/arch-mx7/sys_proto.h Normal file
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@ -0,0 +1,9 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/imx-common/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);

2
arch/arm/include/asm/arch-omap5/cpu.h
View File

@ -56,8 +56,6 @@ struct watchdog {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define BIT(x) (1 << (x))
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555

3
arch/arm/include/asm/arch-rmobile/rcar-base.h
View File

@ -28,6 +28,9 @@
#define SCIF3_BASE 0xE6EA8000
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
#define SCIFA0_BASE 0xE6C40000
#define SCIFA1_BASE 0xE6C50000
#define SCIFA2_BASE 0xE6C60000
/* Module stop status register */
#define MSTPSR0 0xE6150030

1
arch/arm/include/asm/arch-spear/spr_misc.h
View File

@ -253,5 +253,6 @@ struct misc_regs {
#define SOC_SPEAR320 203
extern int get_socrev(void);
int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif

54
arch/arm/include/asm/arch-sunxi/spl.h
View File

@ -1,20 +1,50 @@
/*
* This is a copy of omap3/spl.h:
*
* (C) Copyright 2012
* Texas Instruments, <www.ti.com>
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_NAND 2
#define BOOT_DEVICE_ONE_NAND 3
#define BOOT_DEVICE_MMC2 5 /*emmc*/
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7
#define BOOT_DEVICE_MMC2_2 0xff
#define BOOT0_MAGIC "eGON.BT0"
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
#define SPL_HEADER_VERSION 1
/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */
#define SPL_ADDR 0x0
/* boot head definition from sun4i boot code */
struct boot_file_head {
uint32_t b_instruction; /* one intruction jumping to real code */
uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
uint32_t check_sum; /* generated by PC */
uint32_t length; /* generated by PC */
/*
* We use a simplified header, only filling in what is needed
* by the boot ROM. To be compatible with Allwinner tools we
* would need to implement the proper fields here instead of
* padding.
*
* Actually we want the ability to recognize our "sunxi" variant
* of the SPL. To do so, let's place a special signature into the
* "pub_head_size" field. We can reasonably expect Allwinner's
* boot0 to always have the upper 16 bits of this set to 0 (after
* all the value shouldn't be larger than the limit imposed by
* SRAM size).
* If the signature is present (at 0x14), then we know it's safe
* to use the remaining 8 bytes (at 0x18) for our own purposes.
* (E.g. sunxi-tools "fel" utility can pass information there.)
*/
union {
uint32_t pub_head_size;
uint8_t spl_signature[4];
};
uint32_t fel_script_address;
uint32_t reserved; /* padding, align to 32 bytes */
};
#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
#endif

7
arch/arm/include/asm/arch-tegra/clock.h
View File

@ -44,6 +44,9 @@ enum {
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
/* return the clk_m frequency */
unsigned int clk_m_get_rate(unsigned int parent_rate);
/**
* Start PLL using the provided configuration parameters.
*
@ -338,8 +341,8 @@ void arch_timer_init(void);
void tegra30_set_up_pllp(void);
/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2)
/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3)
struct clk_pll_info {
u32 m_shift:5; /* DIVM_SHIFT */

2
arch/arm/include/asm/arch-tegra/dc.h
View File

@ -364,8 +364,6 @@ struct dc_ctlr {
struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
};
#define BIT(pos) (1U << pos)
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT 5
#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)

9
arch/arm/include/asm/arch-tegra/gpio.h
View File

@ -27,15 +27,6 @@ struct tegra_gpio_config {
u32 init:2;
};
/**
* tegra_spl_gpio_direction_output() - set the output value of a GPIO
*
* This function is only used from SPL on seaboard, which needs to enable a
* GPIO to get the UART running. It could be done in U-Boot rather than SPL,
* but for now, this gets it working
*/
int tegra_spl_gpio_direction_output(int gpio, int value);
/**
* Configure a list of GPIOs
*

1
arch/arm/include/asm/arch-tegra114/clock-tables.h
View File

@ -38,6 +38,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* placeholder */

3
arch/arm/include/asm/arch-tegra114/clock.h
View File

@ -25,4 +25,7 @@
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
#define PLLC_IDDQ (1 << 26)
#endif /* _TEGRA114_CLOCK_H_ */

1
arch/arm/include/asm/arch-tegra124/clock-tables.h
View File

@ -30,6 +30,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */

3
arch/arm/include/asm/arch-tegra124/clock.h
View File

@ -16,6 +16,9 @@
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
#define PLLC_IDDQ (1 << 26)
/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
#define SOR0_CLK_SEL0 (1 << 14)
#define SOR0_CLK_SEL1 (1 << 15)

1
arch/arm/include/asm/arch-tegra20/clock-tables.h
View File

@ -29,6 +29,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,

1
arch/arm/include/asm/arch-tegra210/clock-tables.h
View File

@ -30,6 +30,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */

1
arch/arm/include/asm/arch-tegra30/clock-tables.h
View File

@ -38,6 +38,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */

53
arch/arm/include/asm/arch-u8500/clock.h
View File

@ -1,53 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK
#define __ASM_ARCH_CLOCK
struct prcmu {
unsigned int armclkfix_mgt;
unsigned int armclk_mgt;
unsigned int svammdspclk_mgt;
unsigned int siammdspclk_mgt;
unsigned int reserved;
unsigned int sgaclk_mgt;
unsigned int uartclk_mgt;
unsigned int msp02clk_mgt;
unsigned int i2cclk_mgt;
unsigned int sdmmcclk_mgt;
unsigned int slimclk_mgt;
unsigned int per1clk_mgt;
unsigned int per2clk_mgt;
unsigned int per3clk_mgt;
unsigned int per5clk_mgt;
unsigned int per6clk_mgt;
unsigned int per7clk_mgt;
unsigned int lcdclk_mgt;
unsigned int reserved1;
unsigned int bmlclk_mgt;
unsigned int hsitxclk_mgt;
unsigned int hsirxclk_mgt;
unsigned int hdmiclk_mgt;
unsigned int apeatclk_mgt;
unsigned int apetraceclk_mgt;
unsigned int mcdeclk_mgt;
unsigned int ipi2cclk_mgt;
unsigned int dsialtclk_mgt;
unsigned int spare2clk_mgt;
unsigned int dmaclk_mgt;
unsigned int b2r2clk_mgt;
unsigned int tvclk_mgt;
unsigned int unused[82];
unsigned int tcr;
unsigned int unused1[23];
unsigned int ape_softrst;
};
extern void u8500_clock_enable(int periph, int kern, int cluster);
void db8500_clocks_init(void);
#endif /* __ASM_ARCH_CLOCK */

42
arch/arm/include/asm/arch-u8500/db8500_gpio.h
View File

@ -1,42 +0,0 @@
/*
* Structures and registers for GPIO access in the Nomadik SoC
*
* Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
* The purpose is that GPIO config found in kernel should work by simply
* copy-paste it to U-boot.
*
* Ported to U-boot by:
* Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
* Copyright (C) 2008 STMicroelectronics
* Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
* Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DB8500_GPIO_H__
#define __DB8500_GPIO_H__
/* Alternate functions: function C is set in hw by setting both A and B */
enum db8500_gpio_alt {
DB8500_GPIO_ALT_GPIO = 0,
DB8500_GPIO_ALT_A = 1,
DB8500_GPIO_ALT_B = 2,
DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
};
enum db8500_gpio_pull {
DB8500_GPIO_PULL_NONE,
DB8500_GPIO_PULL_UP,
DB8500_GPIO_PULL_DOWN
};
void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
void db8500_gpio_make_input(unsigned gpio);
int db8500_gpio_get_input(unsigned gpio);
void db8500_gpio_make_output(unsigned gpio, int val);
void db8500_gpio_set_output(unsigned gpio, int val);
#endif /* __DB8500_GPIO_H__ */

170
arch/arm/include/asm/arch-u8500/db8500_pincfg.h
View File

@ -1,170 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
* The purpose is that GPIO config found in kernel should work by simply
* copy-paste it to U-boot. Ported 2010 to U-boot by:
* Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
*
* License terms: GNU General Public License, version 2
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
*
*
* Based on arch/arm/mach-pxa/include/mach/mfp.h:
* Copyright (C) 2007 Marvell International Ltd.
* eric miao <eric.miao@marvell.com>
*/
#ifndef __DB8500_PINCFG_H
#define __DB8500_PINCFG_H
#include "db8500_gpio.h"
/*
* U-boot info:
* SLPM (sleep mode) config will be ignored by U-boot but it is still
* possible to configure it in order to keep cut-n-paste compability
* with Linux kernel config.
*
* pin configurations are represented by 32-bit integers:
*
* bit 0.. 8 - Pin Number (512 Pins Maximum)
* bit 9..10 - Alternate Function Selection
* bit 11..12 - Pull up/down state
* bit 13 - Sleep mode behaviour (not used in U-boot)
* bit 14 - Direction
* bit 15 - Value (if output)
* bit 16..18 - SLPM pull up/down state (not used in U-boot)
* bit 19..20 - SLPM direction (not used in U-boot)
* bit 21..22 - SLPM Value (if output) (not used in U-boot)
*
* to facilitate the definition, the following macros are provided
*
* PIN_CFG_DEFAULT - default config (0):
* pull up/down = disabled
* sleep mode = input/wakeup
* direction = input
* value = low
* SLPM direction = same as normal
* SLPM pull = same as normal
* SLPM value = same as normal
*
* PIN_CFG - default config with alternate function
* PIN_CFG_PULL - default config with alternate function and pull up/down
*/
/* Sleep mode */
enum db8500_gpio_slpm {
DB8500_GPIO_SLPM_INPUT,
DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
DB8500_GPIO_SLPM_NOCHANGE,
DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
};
#define PIN_NUM_MASK 0x1ff
#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
#define PIN_ALT_SHIFT 9
#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
#define PIN_PULL_SHIFT 11
#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
#define PIN_SLPM_SHIFT 13
#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
/* These two replace the above in DB8500v2+ */
#define PIN_SLPM_WAKEUP_ENABLE \
(DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
#define PIN_SLPM_WAKEUP_DISABLE \
(DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
#define PIN_DIR_SHIFT 14
#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
#define PIN_VAL_SHIFT 15
#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
#define PIN_SLPM_PULL_SHIFT 16
#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL(x) \
(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_NONE \
((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_UP \
((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_PULL_DOWN \
((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
#define PIN_SLPM_DIR_SHIFT 19
#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR(x) \
(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
#define PIN_SLPM_VAL_SHIFT 21
#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL(x) \
(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
#define PIN_CFG_DEFAULT (0)
#define PIN_CFG(num, alt) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt))
#define PIN_CFG_INPUT(num, alt, pull) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
#define PIN_CFG_OUTPUT(num, alt, val) \
(PIN_CFG_DEFAULT |\
(PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
#define PIN_CFG_PULL(num, alt, pull) \
((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
(PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
/**
* db8500_gpio_config_pins - configure several pins at once
* @cfgs: array of pin configurations
* @num: number of elments in the array
*
* Configures several GPIO pins.
*/
void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
#endif

231
arch/arm/include/asm/arch-u8500/gpio.h
View File

@ -1,231 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _UX500_GPIO_h
#define _UX500_GPIO_h
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/u8500.h>
#define GPIO_TOTAL_PINS 268
#define GPIO_PINS_PER_BLOCK 32
#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
struct gpio_register {
u32 gpio_dat; /* data register : 0x000 */
u32 gpio_dats; /* data Set register : 0x004 */
u32 gpio_datc; /* data Clear register : 0x008 */
u32 gpio_pdis; /* Pull disable register : 0x00C */
u32 gpio_dir; /* data direction register : 0x010 */
u32 gpio_dirs; /* data dir Set register : 0x014 */
u32 gpio_dirc; /* data dir Clear register : 0x018 */
u32 gpio_slpm; /* Sleep mode register : 0x01C */
u32 gpio_afsa; /* AltFun A Select reg : 0x020 */
u32 gpio_afsb; /* AltFun B Select reg : 0x024 */
u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/
u32 gpio_rimsc; /* rising edge intr set/clear : 0x040 */
u32 gpio_fimsc; /* falling edge intr set/clear register : 0x044 */
u32 gpio_mis; /* masked interrupt status register : 0x048 */
u32 gpio_ic; /* Interrupt Clear register : 0x04C */
u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
u32 gpio_wks; /* Wakeup Status register : 0x058 */
};
/* Error values returned by functions */
enum gpio_error {
GPIO_OK = 0,
GPIO_UNSUPPORTED_HW = -2,
GPIO_UNSUPPORTED_FEATURE = -3,
GPIO_INVALID_PARAMETER = -4,
GPIO_REQUEST_NOT_APPLICABLE = -5,
GPIO_REQUEST_PENDING = -6,
GPIO_NOT_CONFIGURED = -7,
GPIO_INTERNAL_ERROR = -8,
GPIO_INTERNAL_EVENT = 1,
GPIO_REMAINING_EVENT = 2,
GPIO_NO_MORE_PENDING_EVENT = 3,
GPIO_INVALID_CLIENT = -25,
GPIO_INVALID_PIN = -26,
GPIO_PIN_BUSY = -27,
GPIO_PIN_NOT_ALLOCATED = -28,
GPIO_WRONG_CLIENT = -29,
GPIO_UNSUPPORTED_ALTFUNC = -30,
};
/*GPIO DEVICE ID */
enum gpio_device_id {
GPIO_DEVICE_ID_0,
GPIO_DEVICE_ID_1,
GPIO_DEVICE_ID_2,
GPIO_DEVICE_ID_3,
GPIO_DEVICE_ID_INVALID
};
/*
* Alternate Function:
* refered in altfun_table to pointout particular altfun to be enabled
* when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
*/
enum gpio_alt_function {
GPIO_ALT_UART_0_MODEM,
GPIO_ALT_UART_0_NO_MODEM,
GPIO_ALT_UART_1,
GPIO_ALT_UART_2,
GPIO_ALT_I2C_0,
GPIO_ALT_I2C_1,
GPIO_ALT_I2C_2,
GPIO_ALT_I2C_3,
GPIO_ALT_MSP_0,
GPIO_ALT_MSP_1,
GPIO_ALT_MSP_2,
GPIO_ALT_MSP_3,
GPIO_ALT_MSP_4,
GPIO_ALT_MSP_5,
GPIO_ALT_SSP_0,
GPIO_ALT_SSP_1,
GPIO_ALT_MM_CARD0,
GPIO_ALT_SD_CARD0,
GPIO_ALT_DMA_0,
GPIO_ALT_DMA_1,
GPIO_ALT_HSI0,
GPIO_ALT_CCIR656_INPUT,
GPIO_ALT_CCIR656_OUTPUT,
GPIO_ALT_LCD_PANEL,
GPIO_ALT_MDIF,
GPIO_ALT_SDRAM,
GPIO_ALT_HAMAC_AUDIO_DBG,
GPIO_ALT_HAMAC_VIDEO_DBG,
GPIO_ALT_CLOCK_RESET,
GPIO_ALT_TSP,
GPIO_ALT_IRDA,
GPIO_ALT_USB_MINIMUM,
GPIO_ALT_USB_I2C,
GPIO_ALT_OWM,
GPIO_ALT_PWL,
GPIO_ALT_FSMC,
GPIO_ALT_COMP_FLASH,
GPIO_ALT_SRAM_NOR_FLASH,
GPIO_ALT_FSMC_ADDLINE_0_TO_15,
GPIO_ALT_SCROLL_KEY,
GPIO_ALT_MSHC,
GPIO_ALT_HPI,
GPIO_ALT_USB_OTG,
GPIO_ALT_SDIO,
GPIO_ALT_HSMMC,
GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
GPIO_ALT_HSI1,
GPIO_ALT_NOR,
GPIO_ALT_NAND,
GPIO_ALT_KEYPAD,
GPIO_ALT_VPIP,
GPIO_ALT_CAM,
GPIO_ALT_CCP1,
GPIO_ALT_EMMC,
GPIO_ALT_POP_EMMC,
GPIO_ALT_FUNMAX /* Add new alt func before this */
};
/* Defines pin assignment(Software mode or Alternate mode) */
enum gpio_mode {
GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */
GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */
GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */
GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */
};
/* Defines GPIO pin direction */
enum gpio_direction {
GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_DIR_INPUT, /* GPIO set as input */
GPIO_DIR_OUTPUT /* GPIO set as output */
};
/* Interrupt trigger mode */
enum gpio_trig {
GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_TRIG_DISABLE, /* Trigger no IT */
GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */
GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */
GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */
GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */
GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */
};
/* Configuration parameters for one GPIO pin.*/
struct gpio_config {
enum gpio_mode mode;
enum gpio_direction direction;
enum gpio_trig trig;
char *dev_name; /* Who owns the gpio pin */
};
/* GPIO pin data*/
enum gpio_data {
GPIO_DATA_LOW,
GPIO_DATA_HIGH
};
/* GPIO behaviour in sleep mode */
enum gpio_sleep_mode {
GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull
up/down enabled when in sleep
mode. */
GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by
GPIO IP. So mode, direction
and data values for GPIO pin
in sleep mode are determined
by configuration set to GPIO
pin before entering to sleep
mode. */
};
/* GPIO ability to wake the system up from sleep mode.*/
enum gpio_wake {
GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */
GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */
GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */
GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */
GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */
GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */
};
/* Configuration parameters for one GPIO pin in sleep mode.*/
struct gpio_sleep_config {
enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
enum gpio_wake wake; /* GPIO ability to wake up system. */
};
extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
extern int gpio_resetpinconfig(int pin_id, char *dev_name);
extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
extern int gpio_readpin(int pin_id, enum gpio_data *value);
extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
char *dev_name);
extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
char *dev_name);
struct gpio_altfun_data {
u16 altfun;
u16 start;
u16 end;
u16 cont;
u8 type;
};
#endif

94
arch/arm/include/asm/arch-u8500/hardware.h
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@ -1,94 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Peripheral clusters */
#define U8500_PER3_BASE 0x80000000
#define U8500_PER2_BASE 0x80110000
#define U8500_PER1_BASE 0x80120000
#define U8500_PER4_BASE 0x80150000
#define U8500_PER6_BASE 0xa03c0000
#define U8500_PER7_BASE 0xa03d0000
#define U8500_PER5_BASE 0xa03e0000
/* GPIO */
#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
/* Per7 */
#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
/* Per6 */
#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
/* Per5 */
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
/* Per4 */
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
/* Per3 */
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
/* Per2 */
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
/* Per1 */
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
/* Last page of Boot ROM */
#define U8500_BOOTROM_BASE 0x90000000
#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4)
/* AB8500 specifics */
/* address bank */
#define AB8500_REGU_CTRL2 0x0004
#define AB8500_MISC 0x0010
/* registers */
#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
#define AB8500_REV_REG 0x1080
#define AB8500_GPIO_SEL2_REG 0x1001
#define AB8500_GPIO_DIR2_REG 0x1011
#define AB8500_GPIO_DIR4_REG 0x1013
#define AB8500_GPIO_SEL4_REG 0x1003
#define AB8500_GPIO_OUT2_REG 0x1021
#define AB8500_GPIO_OUT4_REG 0x1023
#define LDO_VAUX3_ENABLE_MASK 0x3
#define LDO_VAUX3_ENABLE_VAL 0x1
#define LDO_VAUX3_SEL_MASK 0xf
#define LDO_VAUX3_SEL_2V9 0xd
#define LDO_VAUX3_V2_SEL_MASK 0x7
#define LDO_VAUX3_V2_SEL_2V91 0x7
#endif /* __ASM_ARCH_HARDWARE_H */

64
arch/arm/include/asm/arch-u8500/prcmu.h
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@ -1,64 +0,0 @@
/*
* Copyright (C) 2009 ST-Ericsson SA
*
* Copied from the Linux version:
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_PRCMU_FW_V1_H
#define __MACH_PRCMU_FW_V1_H
#define AP_EXECUTE 2
#define I2CREAD 1
#define I2C_WR_OK 1
#define I2C_RD_OK 2
#define I2CWRITE 0
#define PRCMU_BASE U8500_PRCMU_BASE
#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
#define PRCM_TCR (PRCMU_BASE + 0x1C8)
#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2)
#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3)
/* Mailbox 5 ACKs */
#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1)
#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2)
#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3)
#define LOW_POWER_WAKEUP 1
#define EXE_WAKEUP 0
#define REQ_MB5 5
#define ab8500_read prcmu_i2c_read
#define ab8500_write prcmu_i2c_write
int prcmu_i2c_read(u8 reg, u16 slave);
int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
void u8500_prcmu_enable(u32 *reg);
void db8500_prcmu_init(void);
#endif /* __MACH_PRCMU_FW_V1_H */

12
arch/arm/include/asm/arch-u8500/sys_proto.h
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@ -1,12 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
void gpio_init(void);
int u8500_mmc_power_init(void);
#endif /* _SYS_PROTO_H_ */

31
arch/arm/include/asm/arch-u8500/u8500.h
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@ -1,31 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __U8500_H
#define __U8500_H
/*
* base register values for U8500
*/
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
Management Unit */
#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
/*
* U8500 GPIO register base for 9 banks
*/
#define U8500_GPIO_0_BASE 0x8012E000
#define U8500_GPIO_1_BASE 0x8012E080
#define U8500_GPIO_2_BASE 0x8000E000
#define U8500_GPIO_3_BASE 0x8000E080
#define U8500_GPIO_4_BASE 0x8000E100
#define U8500_GPIO_5_BASE 0x8000E180
#define U8500_GPIO_6_BASE 0x8011E000
#define U8500_GPIO_7_BASE 0x8011E080
#define U8500_GPIO_8_BASE 0xA03FE000
#endif /* __U8500_H */

40
arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
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@ -11,18 +11,6 @@
#ifndef __ASM_ARCH_VF610_DDRMC_H
#define __ASM_ARCH_VF610_DDRMC_H
struct ddrmc_lvl_info {
u16 wrlvl_reg_en;
u16 wrlvl_dl_0;
u16 wrlvl_dl_1;
u16 rdlvl_gt_reg_en;
u16 rdlvl_gt_dl_0;
u16 rdlvl_gt_dl_1;
u16 rdlvl_reg_en;
u16 rdlvl_dl_0;
u16 rdlvl_dl_1;
};
struct ddr3_jedec_timings {
u8 tinit;
u32 trst_pwron;
@ -32,6 +20,7 @@ struct ddr3_jedec_timings {
u8 trc;
u8 trrd;
u8 tccd;
u8 tbst_int_interval;
u8 tfaw;
u8 trp;
u8 twtr;
@ -43,30 +32,51 @@ struct ddr3_jedec_timings {
u8 tckesr;
u8 tcke;
u8 trcd_int;
u8 tras_lockout;
u8 tdal;
u8 bstlen;
u16 tdll;
u8 trp_ab;
u16 tref;
u8 trfc;
u16 tref_int;
u8 tpdex;
u8 txpdll;
u8 txsnr;
u16 txsr;
u8 cksrx;
u8 cksre;
u8 freq_chg_en;
u16 zqcl;
u16 zqinit;
u8 zqcs;
u8 ref_per_zq;
u8 zqcs_rotate;
u8 aprebit;
u8 cmd_age_cnt;
u8 age_cnt;
u8 q_fullness;
u8 odt_rd_mapcs0;
u8 odt_wr_mapcs0;
u8 wlmrd;
u8 wldqsen;
};
void ddrmc_setup_iomux(void);
struct ddrmc_cr_setting {
u32 setting;
int cr_rnum; /* CR register ; -1 for last entry */
};
struct ddrmc_phy_setting {
u32 setting;
int phy_rnum; /* PHY register ; -1 for last entry */
};
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
void ddrmc_phy_init(void);
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
struct ddrmc_lvl_info *lvl,
int col_diff, int row_diff);
struct ddrmc_cr_setting *board_cr_settings,
struct ddrmc_phy_setting *board_phy_settings,
int col_diff, int row_diff);
#endif

6
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@ -148,7 +148,7 @@
#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
#define DDRMC_CR20_AP_EN (1 << 24)
#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
#define DDRMC_CR21_CCMAP_EN 1
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
@ -200,8 +200,8 @@
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)

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