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* Add support for PPChameleon Eval Board

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* Add support for P3G4 board

* Fix problem with MGT5100 FEC driver: add "early" MAC address
  initialization
This commit is contained in:
wdenk
2003-09-02 22:48:03 +00:00
parent 326428cc8b
commit 12f34241cb
31 changed files with 4146 additions and 34 deletions
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19
cpu/mpc5xxx/fec.c
View File

@@ -809,9 +809,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
{
mpc5xxx_fec_priv *fec;
struct eth_device *dev;
char *tmp, *end;
char env_enetaddr[6];
int i;
fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
dev = (struct eth_device *)malloc(sizeof(*dev));
memset(dev, 0, sizeof *dev);
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
@@ -830,6 +834,21 @@ int mpc5xxx_fec_initialize(bd_t * bis)
sprintf(dev->name, "FEC ETHERNET");
eth_register(dev);
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
* the Linux fec driver will try to work with this garbage.
*/
tmp = getenv("ethaddr");
if (tmp) {
for (i=0; i<6; i++) {
env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end+1 : end;
}
mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
}
return 1;
}

10
cpu/ppc4xx/cpu.c
View File

@@ -50,15 +50,15 @@ int checkcpu (void)
{
#if defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_IOP480) || \
defined(CONFIG_440) || \
defined(CONFIG_405EP)
defined(CONFIG_405EP) || \
defined(CONFIG_440) || \
defined(CONFIG_IOP480)
uint pvr = get_pvr();
#endif
#if defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_IOP480) || \
defined(CONFIG_405EP)
defined(CONFIG_405EP) || \
defined(CONFIG_IOP480)
DECLARE_GLOBAL_DATA_PTR;
ulong clock = gd->cpu_clk;

2
cpu/ppc4xx/miiphy.c
View File

@@ -101,6 +101,7 @@ int miiphy_read (unsigned char addr, unsigned char reg,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
sta_reg = sta_reg | (addr << 5); /* Phy address */
out32 (EMAC_STACR, sta_reg);
@@ -156,6 +157,7 @@ int miiphy_write (unsigned char addr, unsigned char reg,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
memcpy (&sta_reg, &value, 2); /* put in data */

3
cpu/ppc4xx/start.S
View File

@@ -702,7 +702,8 @@ _start:
/* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
#endif /* CONFIG_405GP || CONFIG_405CR */
#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
/*----------------------------------------------------------------------- */
/*****************************************************************************/