powerpc: delete Wind River SBC8560/8540 support
The sbc8548/60 (both similar, just variations in UART hardware) support has been removed from the linux kernel as of v3.6-rc1~132 so lets also now remove it from the u-boot tree as well. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
This commit is contained in:
Paul Gortmaker
Tom Rini
parent
953cfd2878
commit
12c79a9578
@ -214,9 +214,7 @@ Siddarth Gore <gores@marvell.com>
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Paul Gortmaker <paul.gortmaker@windriver.com>
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sbc8349 MPC8349
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sbc8540 MPC8540
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sbc8548 MPC8548
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sbc8560 MPC8560
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sbc8641d MPC8641D
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Frank Gottschling <fgottschling@eltec.de>
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@ -1,50 +0,0 @@
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#
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# (C) Copyright 2004-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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# Added support for Wind River SBC8560 board
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_FSL_DDR1) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,57 +0,0 @@
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The port was tested on Wind River System Sbc8560 board
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<www.windriver.com>. U-Boot was installed on the flash memory of the
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CPU card (no the SODIMM).
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NOTE: Please configure uboot compile to the proper PCI frequency and
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setup the appropriate DIP switch settings.
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SBC8560 board:
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Make sure boards switches are set to their appropriate conditions.
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Refer to the Engineering Reference Guide ERG-00300-002. Of particular
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importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
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select the on-board FLASH device (Intel 28F128Jx); 2) The settings
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for the Clock SW9 (33 MHz or 66 MHz).
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Note: SW9 Settings: 66 MHz
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4:1 ratio CCB clocks:SYSCLK
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3:1 ration e500 Core:CCB
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pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
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Note: SW9 Settings: 33 MHz
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8:1 ratio CCB clocks:SYSCLK
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3:1 ration e500 Core:CCB
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pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
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Flashing the FLASH device with the "Wind River ICE":
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1) Properly connect and configure the Wind River ICE to the target
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JTAG port. This includes running the SBC8560 register script. Make
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sure target memory can be read and written.
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2) Build the u-boot image:
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make distclean
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make SBC8560_66_config or SBC8560_33_config
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make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
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Note: reference is made to the ELDK3.0 compiler. Further, it seems
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the ppc_8xx compiler is required for the 85xx (no 85xx
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designated compiler in ELDK3.0)
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3) Convert the uboot (.elf) file to a uboot.bin file (using
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visionClick converter). The bin file should be converted from
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fffc0000 to ffffffff
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4) Setup the Flash Utility (tools menu) for:
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Do a "dc clr" [visionClick] to load the default register settings
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Determine the clock speed of the PCI bus and set SW9 accordingly
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Note: the speed of the PCI bus defaults to the slowest PCI card
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PlayBack the "default" register file for the SBC8560
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Select the uboot.bin file with zero bias
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Select the initialize Target prior to programming
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Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
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Select the erase base address from FFFC0000 to FFFFFFFF
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Select the start address from 0 with size of 4000
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5) Erase and Program
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@ -1,43 +0,0 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 0;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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@ -1,60 +0,0 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(512M) -or- larger
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* c000_0000-cfff_ffff: PCI(256M)
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* d000_0000-dfff_ffff: RapidIO(256M)
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* e000_0000-ffff_ffff: localbus(512M)
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* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
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* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
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* e800_0000-efff_ffff: LBC 128M, nothing here
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* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
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* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
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* f800_0000-fdff_ffff: LBC 64M, nothing here
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* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
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* fd00_0000-fdff_ffff: LBC 16M, nothing here
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* fe00_0000-feff_ffff: LBC 16M, nothing here
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* ff00_0000-ff6f_ffff: LBC 7M, nothing here
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* ff70_0000-ff7f_ffff: CCSRBAR 1M
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* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -1,369 +0,0 @@
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/*
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* (C) Copyright 2003,Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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* Added support for Wind River SBC8560 board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <ioports.h>
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#include <spd_sdram.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
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/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
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/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
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/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
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/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
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/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
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/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
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/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
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/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
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/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
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/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
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/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
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/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
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/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
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/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
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/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
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/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
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/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
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/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
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/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
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/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
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/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
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/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
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/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
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/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
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/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
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/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
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/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
||||
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
|
||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
|
||||
/* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
|
||||
/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
#if defined(CONFIG_PCI)
|
||||
volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
|
||||
|
||||
pci->peer &= 0xfffffffdf; /* disable master abort */
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_phy (void)
|
||||
{
|
||||
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
|
||||
volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
|
||||
#endif
|
||||
/* reset Giga bit Ethernet port if needed here */
|
||||
|
||||
/* reset the CPM FEC port */
|
||||
#if (CONFIG_ETHER_INDEX == 2)
|
||||
bcsr[0] &= ~0x20;
|
||||
udelay(2);
|
||||
bcsr[0] |= 0x20;
|
||||
udelay(1000);
|
||||
#elif (CONFIG_ETHER_INDEX == 3)
|
||||
bcsr[0] &= ~0x10;
|
||||
udelay(2);
|
||||
bcsr[0] |= 0x10;
|
||||
udelay(1000);
|
||||
#endif
|
||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
|
||||
/* reset PHY */
|
||||
miiphy_reset("FCC1", 0x0);
|
||||
|
||||
/* change PHY address to 0x02 */
|
||||
bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
|
||||
|
||||
bb_miiphy_write(NULL, 0x02, MII_BMCR,
|
||||
BMCR_ANENABLE | BMCR_ANRESTART);
|
||||
#endif /* CONFIG_MII */
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
sys_info_t sysinfo;
|
||||
char buf[32];
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
|
||||
#ifdef CONFIG_SBC8560
|
||||
printf ("Board: Wind River SBC8560 Board\n");
|
||||
#else
|
||||
printf ("Board: Wind River SBC8540 Board\n");
|
||||
#endif
|
||||
printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
|
||||
printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
|
||||
printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
|
||||
if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
|
||||
|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
|
||||
printf ("\tLBC: %s MHz\n",
|
||||
strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
|
||||
} else {
|
||||
printf("\tLBC: unknown\n");
|
||||
}
|
||||
printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
|
||||
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_SYS_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
|
||||
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
************************************************************************/
|
||||
phys_size_t fixed_sdram(void)
|
||||
{
|
||||
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc2000000
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
|
||||
|
||||
#if (CONFIG_SYS_SDRAM_SIZE == 512)
|
||||
ddr->cs0_bnds = 0x0000000f;
|
||||
#else
|
||||
ddr->cs0_bnds = 0x00000007;
|
||||
#endif
|
||||
ddr->cs1_bnds = 0x0010001f;
|
||||
ddr->cs2_bnds = 0x00000000;
|
||||
ddr->cs3_bnds = 0x00000000;
|
||||
ddr->cs0_config = 0x80000102;
|
||||
ddr->cs1_config = 0x80000102;
|
||||
ddr->cs2_config = 0x00000000;
|
||||
ddr->cs3_config = 0x00000000;
|
||||
ddr->timing_cfg_1 = 0x37334321;
|
||||
ddr->timing_cfg_2 = 0x00000800;
|
||||
ddr->sdram_cfg = 0x42000000;
|
||||
ddr->sdram_mode = 0x00000022;
|
||||
ddr->sdram_interval = 0x05200100;
|
||||
ddr->err_sbe = 0x00ff0000;
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
ddr->err_disable = 0x0000000D;
|
||||
#endif
|
||||
asm("sync;isync;msync");
|
||||
udelay(500);
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
/* Enable ECC checking */
|
||||
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
|
||||
#else
|
||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
|
||||
#endif
|
||||
asm("sync; isync; msync");
|
||||
udelay(500);
|
||||
#endif
|
||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node;
|
||||
#ifdef CONFIG_PCI
|
||||
const char *path;
|
||||
#endif
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = hose.last_busno - hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -1,65 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB for CCSRBAR (IMMR) */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* TLB for Local Bus stuff, just map the whole 512M */
|
||||
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
|
||||
|
||||
SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
#endif
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 6, BOOKE_PAGESZ_16K, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_256M, 1),
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
@ -682,17 +682,11 @@ suvd3 powerpc mpc83xx km83xx keymile
|
||||
tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1
|
||||
tuxx1 powerpc mpc83xx km83xx keymile
|
||||
kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5
|
||||
sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
|
||||
sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
|
||||
sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
|
||||
sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
|
||||
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
|
||||
sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
|
||||
sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66
|
||||
sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE
|
||||
sbc8560 powerpc mpc85xx sbc8560 - - sbc8560
|
||||
sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560
|
||||
sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560
|
||||
socrates powerpc mpc85xx socrates
|
||||
HWW1U1A powerpc mpc85xx hww1u1a exmeritus
|
||||
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
|
||||
|
||||
@ -1,428 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
|
||||
* Added support for Wind River SBC8540 board
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* sbc8540 board configuration file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Top level Makefile configuration choices
|
||||
*/
|
||||
#ifdef CONFIG_66
|
||||
#define CONFIG_PCI_66
|
||||
#endif
|
||||
|
||||
#define TSEC_DEBUG
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfffc0000
|
||||
|
||||
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
|
||||
#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
|
||||
#define CONFIG_MPC8540 1
|
||||
|
||||
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_PCI /* pci ethernet support */
|
||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Using Localbus SDRAM to emulate flash before we can program the flash,
|
||||
* normally you need a flash-boot image(u-boot.bin), if so undef this.
|
||||
*/
|
||||
#undef CONFIG_RAM_AS_FLASH
|
||||
|
||||
#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
|
||||
#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
|
||||
#else
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
|
||||
#endif
|
||||
|
||||
/* below can be toggled for performance analysis. otherwise use default */
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#undef CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
|
||||
#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
|
||||
defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
|
||||
defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
|
||||
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR1
|
||||
#undef CONFIG_FSL_DDR_INTERACTIVE
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#undef CONFIG_DDR_SPD
|
||||
|
||||
#if defined(CONFIG_MPC85xx_REV1)
|
||||
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
|
||||
#else /* Boot from real Flash */
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
|
||||
#endif
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/* local bus definitions */
|
||||
#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0x00000000
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
|
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
|
||||
#else
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
|
||||
#endif
|
||||
#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
|
||||
|
||||
#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
|
||||
#if 1
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xff000ff7
|
||||
#else
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xff0000f0
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
|
||||
#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
|
||||
#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
#define CONFIG_SYS_LBC_LSRT 0x20000000
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
|
||||
|
||||
/* just hijack the MOT BCSR def for SBC8560 misc devices */
|
||||
#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
|
||||
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#if 0
|
||||
#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
|
||||
#else
|
||||
#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#if 0
|
||||
#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
|
||||
#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
|
||||
#else
|
||||
/* SBC8540 uses internal COMM controller */
|
||||
#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
|
||||
#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
|
||||
#endif
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
|
||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
|
||||
|
||||
# define CONFIG_MPC85xx_TSEC1
|
||||
# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
|
||||
# define CONFIG_MII 1 /* MII PHY management */
|
||||
# define TSEC1_PHY_ADDR 25
|
||||
# define TSEC1_PHYIDX 0
|
||||
/* Options are: TSEC0 */
|
||||
# define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
|
||||
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
|
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2)
|
||||
/*
|
||||
* - Rx-CLK is CLK13
|
||||
* - Tx-CLK is CLK14
|
||||
* - Select bus for bd/buffers
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
|
||||
|
||||
#elif (CONFIG_ETHER_INDEX == 3)
|
||||
/* need more definitions here for FE3 */
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
|
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
|
||||
else iop->pdat &= ~0x00400000
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
|
||||
else iop->pdat &= ~0x00200000
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#if 0
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
|
||||
#endif
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#if 0
|
||||
/* XXX This doesn't work and I don't want to fix it */
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Environment */
|
||||
#if !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
|
||||
/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
|
||||
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
#define CONFIG_CMD_MII
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*Note: change below for your network setting!!! */
|
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
|
||||
# define CONFIG_HAS_ETH1
|
||||
# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
|
||||
# define CONFIG_HAS_ETH2
|
||||
# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
|
||||
#endif
|
||||
|
||||
#define CONFIG_SERVERIP YourServerIP
|
||||
#define CONFIG_IPADDR YourTargetIP
|
||||
#define CONFIG_GATEWAYIP YourGatewayIP
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_HOSTNAME SBC8560
|
||||
#define CONFIG_ROOTPATH "YourRootPath"
|
||||
#define CONFIG_BOOTFILE "YourImageName"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -1,459 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
|
||||
* Added support for Wind River SBC8560 board
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* sbc8560 board configuration file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Top level Makefile configuration choices
|
||||
*/
|
||||
#ifdef CONFIG_66
|
||||
#define CONFIG_PCI_66
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfffc0000
|
||||
|
||||
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
|
||||
#define CONFIG_MPC8560 1
|
||||
|
||||
/* XXX flagging this as something I might want to delete */
|
||||
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_PCI /* pci ethernet support */
|
||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Using Localbus SDRAM to emulate flash before we can program the flash,
|
||||
* normally you need a flash-boot image(u-boot.bin), if so undef this.
|
||||
*/
|
||||
#undef CONFIG_RAM_AS_FLASH
|
||||
|
||||
#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
|
||||
#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
|
||||
#else
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
|
||||
#endif
|
||||
|
||||
/* below can be toggled for performance analysis. otherwise use default */
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#undef CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
|
||||
#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
|
||||
defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
|
||||
defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
|
||||
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR1
|
||||
#undef CONFIG_FSL_DDR_INTERACTIVE
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#undef CONFIG_DDR_SPD
|
||||
|
||||
#if defined(CONFIG_MPC85xx_REV1)
|
||||
#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
|
||||
#else /* Boot from real Flash */
|
||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
|
||||
#endif
|
||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/* local bus definitions */
|
||||
#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
|
||||
#define CONFIG_SYS_OR2_PRELIM 0x00000000
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
|
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
|
||||
#else
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
|
||||
#endif
|
||||
#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
|
||||
|
||||
#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
|
||||
#if 1
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xff000ff7
|
||||
#else
|
||||
#define CONFIG_SYS_OR5_PRELIM 0xff0000f0
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
|
||||
#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
|
||||
#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
#define CONFIG_SYS_LBC_LSRT 0x20000000
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
||||
#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
|
||||
#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
|
||||
|
||||
/* just hijack the MOT BCSR def for SBC8560 misc devices */
|
||||
#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
|
||||
/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
|
||||
#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
|
||||
#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
|
||||
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
|
||||
#ifndef CONFIG_MII
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#endif
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 0x19
|
||||
#define TSEC2_PHY_ADDR 0x1a
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
|
||||
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
|
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
|
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2)
|
||||
/*
|
||||
* - Rx-CLK is CLK13
|
||||
* - Tx-CLK is CLK14
|
||||
* - Select bus for bd/buffers
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
|
||||
|
||||
#elif (CONFIG_ETHER_INDEX == 3)
|
||||
/* need more definitions here for FE3 */
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
|
||||
(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
|
||||
#define MDC_DECLARE MDIO_DECLARE
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
|
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
|
||||
else iop->pdat &= ~0x00400000
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
|
||||
else iop->pdat &= ~0x00200000
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#if 0
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
|
||||
#endif
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#if 0
|
||||
/* XXX This doesn't work and I don't want to fix it */
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Environment */
|
||||
#if !defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
|
||||
/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
#define CONFIG_CMD_MII
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
/* You can compile in a MAC address and your custom net settings by using
|
||||
* the following syntax. Your board should be marked with the assigned
|
||||
* MAC addresses directly on it.
|
||||
*
|
||||
* #define CONFIG_ETHADDR de:ad:be:ef:00:00
|
||||
* #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
|
||||
* #define CONFIG_SERVERIP <server ip>
|
||||
* #define CONFIG_IPADDR <board ip>
|
||||
* #define CONFIG_GATEWAYIP <gateway ip>
|
||||
* #define CONFIG_NETMASK <your netmask>
|
||||
*/
|
||||
|
||||
#define CONFIG_HOSTNAME SBC8560
|
||||
#define CONFIG_ROOTPATH "/home/ppc"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=sbc8560.dtb\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user