usb: r8a66597: Add support for RZ/A series
While the USB HW in the RZ/A is basically the same, there are some differences from the original versions that were in the SH SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
This commit is contained in:
Chris Brandt
Marek Vasut
parent
c0c5f910ad
commit
11f4678962
@ -82,6 +82,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
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}
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} while ((tmp & USBE) != USBE);
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r8a66597_bclr(r8a66597, USBE, SYSCFG0);
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#if !defined(CONFIG_RZA_USB)
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r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
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i = 0;
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@ -94,6 +95,20 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
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return -1;
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}
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} while ((tmp & SCKE) != SCKE);
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#else
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/*
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* RZ/A Only:
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* Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
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* and USB1, so we must always set the USB0 register
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*/
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#if (CONFIG_R8A66597_XTAL == 1)
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setbits(le16, R8A66597_BASE0, XTAL);
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#endif
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mdelay(1);
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setbits(le16, R8A66597_BASE0, UPLLE);
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mdelay(1);
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r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
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#endif /* CONFIG_RZA_USB */
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#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
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return 0;
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@ -101,6 +116,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
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static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
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{
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#if !defined(CONFIG_RZA_USB)
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r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
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udelay(1);
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#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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@ -108,6 +124,15 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
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r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
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r8a66597_bclr(r8a66597, USBE, SYSCFG0);
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#endif
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#else
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r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
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clrbits(le16, R8A66597_BASE0, UPLLE);
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mdelay(1);
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r8a66597_bclr(r8a66597, USBE, SYSCFG0);
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mdelay(1);
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#endif
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}
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static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
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@ -118,7 +143,9 @@ static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
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r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
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r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
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#if !defined(CONFIG_RZA_USB)
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r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
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#endif
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}
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static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
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@ -148,7 +175,9 @@ static int enable_controller(struct r8a66597 *r8a66597)
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if (ret < 0)
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return ret;
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#if !defined(CONFIG_RZA_USB)
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r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG);
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#endif
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r8a66597_bset(r8a66597, USBE, SYSCFG0);
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r8a66597_bset(r8a66597, INTL, SOFCFG);
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@ -266,12 +295,30 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
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unsigned long setup_addr = USBREQ;
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u16 intsts1;
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int timeout = 3000;
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#if defined(CONFIG_RZA_USB)
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u16 dcpctr;
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int timeout2 = 10000;
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#endif
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u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
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r8a66597_write(r8a66597, make_devsel(devsel) |
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(8 << dev->maxpacketsize), DCPMAXP);
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r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
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#if defined(CONFIG_RZA_USB)
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dcpctr = r8a66597_read(r8a66597, DCPCTR);
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if ((dcpctr & PID) == PID_BUF) {
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timeout2 = 10000;
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while (!(dcpctr & BSTS)) {
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dcpctr = r8a66597_read(r8a66597, DCPCTR);
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if (timeout2-- < 0) {
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printf("DCPCTR clear timeout!\n");
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break;
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}
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}
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}
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#endif
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for (i = 0; i < 4; i++) {
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r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);
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setup_addr += 2;
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@ -87,8 +87,10 @@
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#define DEVADD8 0xE0
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#define DEVADD9 0xE2
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#define DEVADDA 0xE4
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#define SUSPMODE0 0x102 /* RZ/A only */
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/* System Configuration Control Register */
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#if !defined(CONFIG_RZA_USB)
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#define XTAL 0xC000 /* b15-14: Crystal selection */
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#define XTAL48 0x8000 /* 48MHz */
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#define XTAL24 0x4000 /* 24MHz */
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@ -98,10 +100,17 @@
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#define SCKE 0x0400 /* b10: USB clock enable */
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#define PCSDIS 0x0200 /* b9: not CS wakeup */
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#define LPSME 0x0100 /* b8: Low power sleep mode */
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#endif
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#define HSE 0x0080 /* b7: Hi-speed enable */
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#define DCFM 0x0040 /* b6: Controller function select */
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#define DRPD 0x0020 /* b5: D+/- pull down control */
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#define DPRPU 0x0010 /* b4: D+ pull up control */
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#if defined(CONFIG_RZA_USB)
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#define XTAL 0x0004 /* b2: Crystal selection */
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#define XTAL12 0x0004 /* 12MHz */
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#define XTAL48 0x0000 /* 48MHz */
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#define UPLLE 0x0002 /* b1: internal PLL control */
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#endif
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#define USBE 0x0001 /* b0: USB module operation enable */
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/* System Configuration Status Register */
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@ -173,10 +182,15 @@
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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#define MBW 0x0800
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#else
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#if !defined(CONFIG_RZA_USB)
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#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
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#else
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#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
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#endif
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#endif
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#define MBW_8 0x0000 /* 8bit */
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#define MBW_16 0x0400 /* 16bit */
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#define MBW_32 0x0800 /* 32bit */
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#define BIGEND 0x0100 /* b8: Big endian mode */
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#define BYTE_LITTLE 0x0000 /* little dendian */
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#define BYTE_BIG 0x0100 /* big endifan */
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@ -379,6 +393,9 @@
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#define USBSPD 0x00C0
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#define RTPORT 0x0001
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/* Suspend Mode Register */
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#define SUSPM 0x4000 /* b14: Suspend */
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#define R8A66597_MAX_NUM_PIPE 10
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#define R8A66597_BUF_BSIZE 8
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#define R8A66597_MAX_DEVICE 10
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@ -419,7 +436,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
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int len)
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{
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int i;
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
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unsigned long fifoaddr = r8a66597->reg + offset;
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unsigned long count;
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unsigned long *p = buf;
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@ -453,7 +470,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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{
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int i;
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unsigned long fifoaddr = r8a66597->reg + offset;
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
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#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
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unsigned long count;
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unsigned char *pb;
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unsigned long *p = buf;
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