Merge git://git.denx.de/u-boot-marvell
This commit is contained in:
Tom Rini committed
commit
1131d4e22c
36 files changed
+379
-60
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@@ -102,6 +102,11 @@ config KIRKWOOD
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bool "Marvell Kirkwood"
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select CPU_ARM926EJS
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config TARGET_DB_88F6820_GP
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bool "Support DB-88F6820-GP"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_DB_MV784MP_GP
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bool "Support db-mv784mp-gp"
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select CPU_V7
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@@ -855,6 +860,7 @@ source "board/BuR/kwb/Kconfig"
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source "board/BuR/tseries/Kconfig"
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source "board/CarMediaLab/flea3/Kconfig"
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source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/db-88f6820-gp/Kconfig"
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source "board/Marvell/db-mv784mp-gp/Kconfig"
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source "board/Marvell/gplugd/Kconfig"
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source "board/altera/socfpga/Kconfig"
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+3
-2
@@ -48,6 +48,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
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machine-$(CONFIG_ARCH_KEYSTONE) += keystone
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# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
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machine-$(CONFIG_KIRKWOOD) += kirkwood
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machine-$(CONFIG_ARMADA_XP) += mvebu
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# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
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machine-$(CONFIG_ARCH_NOMADIK) += nomadik
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# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
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@@ -85,8 +86,8 @@ libs-y += arch/arm/imx-common/
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endif
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endif
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ifneq (,$(filter $(SOC), armada-xp kirkwood))
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libs-y += arch/arm/mvebu-common/
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ifneq (,$(filter $(SOC), kirkwood))
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libs-y += arch/arm/mach-mvebu/
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endif
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# deprecated
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@@ -38,7 +38,6 @@ obj-y += s5p-common/
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endif
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obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
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obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
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obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
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obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
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obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
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@@ -1,9 +0,0 @@
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#
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# Copyright (C) 2014 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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@@ -0,0 +1,24 @@
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#
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# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_KIRKWOOD
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obj-y = dram.o
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obj-y += gpio.o
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obj-y += timer.o
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else
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obj-y = cpu.o
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obj-y += dram.o
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obj-y += gpio.o
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obj-y += mbus.o
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obj-y += timer.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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obj-y += serdes/
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endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored)
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;
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}
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int mvebu_soc_family(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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if (devid == SOC_MV78460_ID)
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return MVEBU_SOC_AXP;
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if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
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devid == SOC_88F6828_ID)
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return MVEBU_SOC_A38X;
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return MVEBU_SOC_UNKNOWN;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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@@ -52,21 +66,46 @@ int print_cpuinfo(void)
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case SOC_MV78460_ID:
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puts("MV78460-");
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break;
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case SOC_88F6810_ID:
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puts("MV88F6810-");
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break;
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case SOC_88F6820_ID:
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puts("MV88F6820-");
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break;
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case SOC_88F6828_ID:
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puts("MV88F6828-");
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break;
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default:
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puts("Unknown-");
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break;
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}
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switch (revid) {
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case 1:
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puts("A0\n");
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break;
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case 2:
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puts("B0\n");
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break;
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default:
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puts("??\n");
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break;
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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switch (revid) {
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case 1:
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puts("A0\n");
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break;
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case 2:
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puts("B0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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switch (revid) {
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case MV_88F68XX_Z1_ID:
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puts("Z1\n");
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break;
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case MV_88F68XX_A0_ID:
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puts("A0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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return 0;
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@@ -145,11 +184,13 @@ int arch_cpu_init(void)
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*/
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mvebu_mbus_probe(NULL, 0);
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/*
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* Now the SDRAM access windows can be reconfigured using
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* the information in the SDRAM scratch pad registers
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*/
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update_sdram_window_sizes();
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/*
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* Now the SDRAM access windows can be reconfigured using
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* the information in the SDRAM scratch pad registers
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*/
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update_sdram_window_sizes();
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}
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/*
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* Finally the mbus windows can be configured with the
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@@ -175,10 +216,22 @@ int arch_misc_init(void)
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#ifdef CONFIG_MVNETA
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int cpu_eth_init(bd_t *bis)
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{
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mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
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mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
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mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
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mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
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u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
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MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
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u8 phy_addr[] = CONFIG_PHY_ADDR;
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int i;
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/*
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* Only Armada XP supports all 4 ethernet interfaces. A38x has
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* slightly different base addresses for its 2-3 interfaces.
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*/
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if (mvebu_soc_family() != MVEBU_SOC_AXP) {
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enet_base[1] = MVEBU_EGIGA2_BASE;
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enet_base[2] = MVEBU_EGIGA3_BASE;
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}
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for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
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mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
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return 0;
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}
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@@ -187,6 +240,9 @@ int cpu_eth_init(bd_t *bis)
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Avoid problem with e.g. neta ethernet driver */
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invalidate_dcache_all();
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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File renamed without changes.
File renamed without changes.
+11
-6
@@ -9,15 +9,17 @@
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/*
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* This file should be included in board config header file.
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*
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* It supports common definitions for Armada XP platforms
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* It supports common definitions for MVEBU platforms
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*/
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#ifndef _ARMADA_XP_CONFIG_H
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#define _ARMADA_XP_CONFIG_H
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#ifndef _MVEBU_CONFIG_H
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#define _MVEBU_CONFIG_H
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#include <asm/arch/soc.h>
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#if defined(CONFIG_ARMADA_XP)
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#define MV88F78X60 /* for the DDR training bin_hdr code */
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#endif
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#define CONFIG_SYS_CACHELINE_SIZE 32
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@@ -33,8 +35,6 @@
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/* Add target to build it automatically upon "make" */
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#ifdef CONFIG_SPL
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#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
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#else
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#define CONFIG_BUILD_TARGET "u-boot.kwb"
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#endif
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/* end of 16M scrubbed by training in bootrom */
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@@ -83,4 +83,9 @@
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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#endif /* _ARMADA_XP_CONFIG_H */
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/* Common SPL configuration */
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#ifndef CONFIG_SPL_LDSCRIPT
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
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#endif
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#endif /* __MVEBU_CONFIG_H */
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@@ -6,8 +6,8 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ARMADA_XP_CPU_H
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#define _ARMADA_XP_CPU_H
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#ifndef _MVEBU_CPU_H
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#define _MVEBU_CPU_H
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#include <asm/system.h>
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@@ -56,6 +56,12 @@ enum cpu_attrib {
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CPU_ATTR_DEV_CS3 = 0x37,
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};
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enum {
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MVEBU_SOC_AXP,
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MVEBU_SOC_A38X,
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MVEBU_SOC_UNKNOWN,
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};
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/*
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* Default Device Address MAP BAR values
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*/
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@@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int mvebu_mbus_probe(struct mbus_win windows[], int count);
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int mvebu_soc_family(void);
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/*
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* Highspeed SERDES PHY config init, ported from bin_hdr
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@@ -120,4 +127,4 @@ int serdes_phy_config(void);
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*/
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int ddr3_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _ARMADA_XP_CPU_H */
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#endif /* _MVEBU_CPU_H */
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@@ -8,10 +8,17 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_ARMADA_XP_H
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#define _ASM_ARCH_ARMADA_XP_H
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#ifndef _MVEBU_SOC_H
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#define _MVEBU_SOC_H
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#define SOC_MV78460_ID 0x7846
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#define SOC_88F6810_ID 0x6810
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#define SOC_88F6820_ID 0x6820
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#define SOC_88F6828_ID 0x6828
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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/* TCLK Core Clock definition */
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#ifndef CONFIG_SYS_TCLK
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@@ -25,6 +32,8 @@
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
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#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
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#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
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#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
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#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
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@@ -46,12 +55,9 @@
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#define SDRAM_MAX_CS 4
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#define SDRAM_ADDR_MASK 0xFF000000
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/* Armada XP GbE controller has 4 ports */
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#define MAX_MVNETA_DEVS 4
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/* Kirkwood CPU memory windows */
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/* MVEBU CPU memory windows */
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#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
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#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
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#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
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#endif /* _ASM_ARCH_ARMADA_XP_H */
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#endif /* _MVEBU_SOC_H */
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File renamed without changes.
@@ -341,9 +341,6 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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w = &mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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#if defined(CONFIG_ARMADA_XP)
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w->mbus_attr |= ATTR_HW_COHERENCY;
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#endif
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w->base = base & DDR_BASE_CS_LOW_MASK;
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w->size = (size | ~DDR_SIZE_MASK) + 1;
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}
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File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
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@@ -0,0 +1,15 @@
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if TARGET_DB_88F6820_GP
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|
||||
config SYS_BOARD
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default "db-88f6820-gp"
|
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|
||||
config SYS_VENDOR
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default "Marvell"
|
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|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "db-88f6820-gp"
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||||
|
||||
endif
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||||
@@ -0,0 +1,7 @@
|
||||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := db-88f6820-gp.o
|
||||
@@ -0,0 +1,16 @@
|
||||
--------
|
||||
WARNING:
|
||||
--------
|
||||
This file should contain the bin_hdr generated by the original Marvell
|
||||
U-Boot implementation. As this is currently not included in this
|
||||
U-Boot version, we have added this placeholder, so that the U-Boot
|
||||
image can be generated without errors.
|
||||
|
||||
If you have a known to be working bin_hdr for your board, then you
|
||||
just need to replace this text file here with the binary header
|
||||
and recompile U-Boot.
|
||||
|
||||
In a few weeks, mainline U-Boot will get support to generate the
|
||||
bin_hdr with the DDR training code itself. By implementing this code
|
||||
as SPL U-Boot. Then this file will not be needed any more and will
|
||||
get removed.
|
||||
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
|
||||
#define ETH_PHY_CTRL_REG 0
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-2014_T3.0"
|
||||
*/
|
||||
#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
|
||||
(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
|
||||
BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
|
||||
BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
|
||||
#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
|
||||
(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
|
||||
BIT(16) | BIT(17) | BIT(18)))
|
||||
|
||||
#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
|
||||
#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
|
||||
#define DB_GP_88F68XX_GPP_POL_LOW 0x0
|
||||
#define DB_GP_88F68XX_GPP_POL_MID 0x0
|
||||
|
||||
/* IO expander on Marvell GP board includes e.g. fan enabling */
|
||||
struct marvell_io_exp {
|
||||
u8 chip;
|
||||
u8 addr;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
static struct marvell_io_exp io_exp[] = {
|
||||
{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
|
||||
{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
|
||||
{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
|
||||
{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
|
||||
{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x11244011, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x22200002, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x30042022, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x55550555, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
/* Init I2C IO expanders */
|
||||
for (i = 0; i < ARRAY_SIZE(io_exp); i++)
|
||||
i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Marvell DB-88F6820-GP\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
#
|
||||
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
|
||||
@@ -7,7 +7,7 @@ config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_SOC
|
||||
default "armada-xp"
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "db-mv784mp-gp"
|
||||
|
||||
@@ -86,7 +86,8 @@ int checkboard(void)
|
||||
/* Configure and enable MV88E1545 PHY */
|
||||
void reset_phy(void)
|
||||
{
|
||||
u16 devadr = CONFIG_PHY_BASE_ADDR;
|
||||
u8 phy_addr[] = CONFIG_PHY_ADDR;
|
||||
u16 devadr = phy_addr[0];
|
||||
char *name = "neta0";
|
||||
u16 reg;
|
||||
|
||||
|
||||
@@ -4,7 +4,7 @@ config SYS_BOARD
|
||||
default "maxbcm"
|
||||
|
||||
config SYS_SOC
|
||||
default "armada-xp"
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "maxbcm"
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
#include <linux/mbus.h>
|
||||
|
||||
#include "../drivers/ddr/mvebu/ddr3_hw_training.h"
|
||||
#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h"
|
||||
#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_DB_88F6820_GP=y
|
||||
@@ -35,7 +35,7 @@
|
||||
|
||||
#define ECC_SUPPORT
|
||||
#define NEW_FABRIC_TWSI_ADDR 0x4E
|
||||
#ifdef DB_784MP_GP
|
||||
#ifdef CONFIG_DB_784MP_GP
|
||||
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
|
||||
#else
|
||||
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_DB_88F6820_GP_H
|
||||
#define _CONFIG_DB_88F6820_GP_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
||||
#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
|
||||
|
||||
#define CONFIG_SYS_L2_PL310
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x04000000
|
||||
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_TFTPPUT
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* SPI NOR flash default params, used by sf commands */
|
||||
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
|
||||
/* Environment in SPI NOR flash */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
||||
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define CONFIG_PHY_ADDR { 1, 0 }
|
||||
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
#endif /* _CONFIG_DB_88F6820_GP_H */
|
||||
@@ -53,7 +53,7 @@
|
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define CONFIG_PHY_BASE_ADDR 0x10
|
||||
#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
|
||||
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
#define CONFIG_RESET_PHY_R
|
||||
@@ -100,7 +100,6 @@
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define CONFIG_PHY_BASE_ADDR 0x0
|
||||
#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
|
||||
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
#define CONFIG_RESET_PHY_R
|
||||
@@ -100,7 +100,6 @@
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
|
||||
@@ -57,6 +57,7 @@
|
||||
115200,230400, 460800, 921600 }
|
||||
/* auto boot */
|
||||
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
|
||||
#define CONFIG_PREBOOT
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
|
||||
Reference in new issue
Block a user