Patch by Yuli Barcohen, 19 Apr 2004:
- Rename DUET_ADS to MPC885ADS - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY - Clean up FADS family port to use the new defines
This commit is contained in:
wdenk
@@ -388,7 +388,7 @@ static void fec_pin_init(int fecidx)
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fecp->fec_mii_speed <<= 1;
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#endif
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#if defined(CONFIG_DUET) && defined(WANT_MII)
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#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
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/* use MDC for MII */
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immr->im_ioport.iop_pdpar |= 0x0080;
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immr->im_ioport.iop_pddir &= ~0x0080;
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@@ -397,7 +397,7 @@ static void fec_pin_init(int fecidx)
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if (fecidx == 0) {
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#if defined(CONFIG_ETHER_ON_FEC1)
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#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
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#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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@@ -489,7 +489,7 @@ static void fec_pin_init(int fecidx)
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#if defined(CONFIG_ETHER_ON_FEC2)
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#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
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#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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@@ -516,7 +516,7 @@ static void fec_pin_init(int fecidx)
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immr->im_cpm.cp_cptr &= ~0x00000028;
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#endif /* CONFIG_RMII */
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#endif /* CONFIG_DUET */
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#endif /* CONFIG_MPC885_FAMILY */
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#endif /* CONFIG_ETHER_ON_FEC2 */
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@@ -533,7 +533,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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if (efis->ether_index == 0) {
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#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
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#if defined(CONFIG_DUET_ADS)
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#if defined(CONFIG_MPC885ADS)
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*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
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#else
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/* configure FADS for fast (FEC) ethernet, half-duplex */
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@@ -553,7 +553,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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*bcsr4 |= BCSR4_FETHRST;
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udelay (10);
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}
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#endif /* CONFIG_DUET_ADS */
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#endif /* CONFIG_MPC885ADS */
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#endif /* CONFIG_FADS */
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}
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@@ -948,7 +948,7 @@ void mii_init (void)
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*/
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fecp->fec_ievent = 0xffc0;
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/* Setup the pin configuration of the FEC(s)
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/* Setup the pin configuration of the FEC(s)
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*/
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fec_pin_init(ether_fcc_info[i].ether_index);
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@@ -90,7 +90,7 @@ unsigned long measure_gclk(void)
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ulong timer2_val;
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ulong msr_val;
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#ifdef CONFIG_MPC866_et_al
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#ifdef CFG_8XX_XIN
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/* dont use OSCM, only use EXTCLK/512 */
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immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
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#else
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@@ -162,7 +162,7 @@ unsigned long measure_gclk(void)
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timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
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immr->im_sit.sit_piscr &= ~PISCR_PTE;
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#if defined(CONFIG_MPC866_et_al)
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#if defined(CFG_8XX_XIN)
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/* not using OSCM, using XIN, so scale appropriately */
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return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
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#else
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@@ -183,22 +183,39 @@ int get_clocks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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#ifndef CONFIG_8xx_GCLK_FREQ
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gd->cpu_clk = measure_gclk();
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#else /* CONFIG_8xx_GCLK_FREQ */
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uint immr = get_immr (0); /* Return full IMMR contents */
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint sccr = immap->im_clkrst.car_sccr;
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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* (For example, the cogent CMA286-60 CPU module has no
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* separate oscillator for PITRTCLK)
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*/
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#if defined(CONFIG_8xx_GCLK_FREQ)
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gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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#elif defined(CONFIG_8xx_OSCLK)
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#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
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uint pll = immap->im_clkrst.car_plprcr;
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uint clk;
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if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
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clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
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(PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
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(1<<PLPRCR_val(S));
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} else {
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clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
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}
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if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
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gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
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} else { /* High frequency division factor is used */
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gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
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}
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#else
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gd->cpu_clk = measure_gclk();
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#endif /* CONFIG_8xx_GCLK_FREQ */
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
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if ((sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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@@ -209,7 +226,7 @@ int get_clocks (void)
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return (0);
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}
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#else /* CONFIG_MPC866_et_al */
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#else /* CONFIG_MPC866_FAMILY */
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static long init_pll_866 (long clk);
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@@ -345,7 +362,7 @@ static long init_pll_866 (long clk)
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return (n);
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}
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#endif /* CONFIG_MPC866_et_al */
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#endif /* CONFIG_MPC866_FAMILY */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
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/*
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