leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mpc83xx: fix pcie configuration space read/write

Browse Source 
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.

Signed-off-by: Leo Liu <liucai.lfn@gmail.com>

fix codingstyle and compiler warning: 'pcie_priv' defined but not used

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Leo Liu 2011-01-19 19:50:47 +08:00 committed by Kim Phillips
parent f69b980d10
commit 10fa8d7c70
2 changed files with 20 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/powerpc/cpu/mpc83xx/pcie.c
View File

@ -48,11 +48,26 @@ static struct {
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
/* private structure for mpc83xx pcie hose */
static struct mpc83xx_pcie_priv {
u8 index;
} pcie_priv[PCIE_MAX_BUSES] = {
{
/* pcie controller 1 */
.index = 0,
},
{
/* pcie controller 2 */
.index = 1,
},
};
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
pex83xx_t *pex = &immr->pciexp[bus];
struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
hose->priv_data = &pcie_priv[bus];
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,

2
include/pci.h
View File

@ -420,6 +420,8 @@ struct pci_controller {
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
void *priv_data;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,