From 10c50b1facbfccbc70099adef629b5a988ec2bb2 Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 15 Dec 2021 11:00:01 +0100
Subject: [PATCH] net: zynq: Add support for PHY configuration in SGMII mode

SGMII configuration depends on proper GT setting that's why when node has
phys property call PSGTR driver to configure it properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/bbc8d7ed9d308199168e4455c7a3e3a5ac0890e7.1639562397.git.michal.simek@xilinx.com
---
 drivers/net/zynq_gem.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 56f668c249..336d569b37 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
+#include <generic-phy.h>
 #include <log.h>
 #include <net.h>
 #include <netdev.h>
@@ -713,6 +714,19 @@ static int zynq_gem_probe(struct udevice *dev)
 	void *bd_space;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	int ret;
+	struct phy phy;
+
+	if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+		ret = generic_phy_get_by_index(dev, 0, &phy);
+		if (!ret) {
+			ret = generic_phy_init(&phy);
+			if (ret)
+				return ret;
+		} else if (ret != -ENOENT) {
+			debug("could not get phy (err %d)\n", ret);
+			return ret;
+		}
+	}
 
 	ret = zynq_gem_reset_init(dev);
 	if (ret)
@@ -769,6 +783,12 @@ static int zynq_gem_probe(struct udevice *dev)
 	if (ret)
 		goto err3;
 
+	if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
+		ret = generic_phy_power_on(&phy);
+		if (ret)
+			return ret;
+	}
+
 	return ret;
 
 err3: