Merge branch 'master' of git://git.denx.de/u-boot-atmel
This commit is contained in:
@@ -66,6 +66,7 @@ config TARGET_STAMP9G20
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config TARGET_AT91SAM9M10G45EK
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bool "Atmel AT91SAM9M10G45-EK board"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_PM9G45
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bool "Ronetix pm9g45 board"
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||||
@@ -74,6 +75,7 @@ config TARGET_PM9G45
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config TARGET_AT91SAM9N12EK
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bool "Atmel AT91SAM9N12-EK board"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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||||
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config TARGET_AT91SAM9RLEK
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bool "Atmel at91sam9rl reference board"
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@@ -82,6 +84,7 @@ config TARGET_AT91SAM9RLEK
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config TARGET_AT91SAM9X5EK
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bool "Atmel AT91SAM9X5-EK board"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_SAMA5D3_XPLAINED
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bool "SAMA5D3 Xplained board"
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@@ -2,6 +2,8 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
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||||
ifneq ($(CONFIG_SPL_BUILD),)
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||||
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
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obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
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obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
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||||
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
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||||
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
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obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
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obj-y += spl.o
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@@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
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void at91_plla_init(u32 pllar)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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int timeout = AT91_PLL_LOCK_TIMEOUT;
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writel(pllar, &pmc->pllar);
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while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
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timeout--;
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if (timeout == 0)
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break;
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}
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while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
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;
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}
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void at91_pllb_init(u32 pllbr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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int timeout = AT91_PLL_LOCK_TIMEOUT;
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writel(pllbr, &pmc->pllbr);
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while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
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timeout--;
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if (timeout == 0)
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break;
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}
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while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
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;
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}
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void at91_mck_init(u32 mckr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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int timeout = AT91_PLL_LOCK_TIMEOUT;
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u32 tmp;
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tmp = readl(&pmc->mckr);
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tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_MASK |
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AT91_PMC_MCKR_CSS_MASK);
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tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_MASK |
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AT91_PMC_MCKR_CSS_MASK);
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tmp &= ~AT91_PMC_MCKR_PRES_MASK;
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tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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||||
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
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||||
timeout--;
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||||
if (timeout == 0)
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||||
break;
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||||
}
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
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tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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||||
;
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||||
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||||
tmp = readl(&pmc->mckr);
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||||
tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
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||||
tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
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||||
writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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||||
;
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||||
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tmp = readl(&pmc->mckr);
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||||
tmp &= ~AT91_PMC_MCKR_CSS_MASK;
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tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
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||||
writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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||||
;
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||||
}
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||||
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||||
void at91_periph_clk_enable(int id)
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||||
@@ -33,22 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
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||||
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#define TIMER_LOAD_VAL 0xfffff
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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||||
do_div(tick, gd->arch.timer_rate_hz);
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||||
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return tick;
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||||
}
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||||
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||||
static inline unsigned long long usec_to_tick(unsigned long long usec)
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||||
{
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||||
usec *= gd->arch.timer_rate_hz;
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do_div(usec, 1000000);
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||||
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||||
return usec;
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}
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/*
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* Use the PITC in full 32 bit incrementing mode
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*/
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@@ -64,53 +48,10 @@ int timer_init(void)
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writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
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gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
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||||
gd->arch.tbu = gd->arch.tbl = 0;
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||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the current 64 bit timer tick count
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||||
*/
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||||
unsigned long long get_ticks(void)
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||||
{
|
||||
at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
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||||
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||||
ulong now = readl(&pit->piir);
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||||
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||||
/* increment tbu if tbl has rolled over */
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||||
if (now < gd->arch.tbl)
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||||
gd->arch.tbu++;
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||||
gd->arch.tbl = now;
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||||
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
|
||||
}
|
||||
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||||
void __udelay(unsigned long usec)
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{
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||||
unsigned long long start;
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ulong tmo;
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start = get_ticks(); /* get current timestamp */
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tmo = usec_to_tick(usec); /* convert usecs to ticks */
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while ((get_ticks() - start) < tmo)
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||||
; /* loop till time has passed */
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||||
}
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||||
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||||
/*
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||||
* get_timer(base) can be used to check for timeouts or
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||||
* to measure elasped time relative to an event:
|
||||
*
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||||
* ulong start_time = get_timer(0) sets start_time to the current
|
||||
* time value.
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||||
* get_timer(start_time) returns the time elapsed since then.
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||||
*
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||||
* The time is used in CONFIG_SYS_HZ units!
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||||
*/
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ulong get_timer(ulong base)
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{
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return tick_to_time(get_ticks()) - base;
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}
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/*
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* Return the number of timer ticks per second.
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||||
*/
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||||
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||||
48
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Normal file
48
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Atmel Corporation
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||||
* Bo Shen <voice.shen@atmel.com>
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||||
*
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||||
* SPDX-License-Identifier: GPL-2.0+
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||||
*/
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
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LENGTH = CONFIG_SPL_MAX_SIZE }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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.text :
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{
|
||||
__start = .;
|
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*(.vectors)
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arch/arm/cpu/arm926ejs/start.o (.text*)
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*(.text*)
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} >.sram
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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__image_copy_end = .;
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||||
|
||||
.end :
|
||||
{
|
||||
*(.__end)
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||||
} >.sram
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||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
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||||
__bss_start = .;
|
||||
*(.bss*)
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||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} >.sdram
|
||||
}
|
||||
@@ -36,22 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define TIMER_LOAD_VAL 0xfffff
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, gd->arch.timer_rate_hz);
|
||||
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long usec_to_tick(unsigned long long usec)
|
||||
{
|
||||
usec *= gd->arch.timer_rate_hz;
|
||||
do_div(usec, 1000000);
|
||||
|
||||
return usec;
|
||||
}
|
||||
|
||||
/*
|
||||
* Use the PITC in full 32 bit incrementing mode
|
||||
*/
|
||||
@@ -67,54 +51,9 @@ int timer_init(void)
|
||||
|
||||
gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
|
||||
|
||||
gd->arch.tbu = 0;
|
||||
gd->arch.tbl = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the current 64 bit timer tick count
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
|
||||
|
||||
ulong now = readl(&pit->piir);
|
||||
|
||||
/* increment tbu if tbl has rolled over */
|
||||
if (now < gd->arch.tbl)
|
||||
gd->arch.tbu++;
|
||||
gd->arch.tbl = now;
|
||||
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long start;
|
||||
ulong tmo;
|
||||
|
||||
start = get_ticks(); /* get current timestamp */
|
||||
tmo = usec_to_tick(usec); /* convert usecs to ticks */
|
||||
while ((get_ticks() - start) < tmo)
|
||||
; /* loop till time has passed */
|
||||
}
|
||||
|
||||
/*
|
||||
* get_timer(base) can be used to check for timeouts or
|
||||
* to measure elasped time relative to an event:
|
||||
*
|
||||
* ulong start_time = get_timer(0) sets start_time to the current
|
||||
* time value.
|
||||
* get_timer(start_time) returns the time elapsed since then.
|
||||
*
|
||||
* The time is used in CONFIG_SYS_HZ units!
|
||||
*/
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return tick_to_time(get_ticks()) - base;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the number of timer ticks per second.
|
||||
*/
|
||||
|
||||
@@ -97,7 +97,8 @@ typedef struct at91_pmc {
|
||||
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
|
||||
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
|
||||
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
|
||||
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
|
||||
#define AT91_PMC_MCKR_PRES_1 0x00000000
|
||||
#define AT91_PMC_MCKR_PRES_2 0x00000010
|
||||
#define AT91_PMC_MCKR_PRES_4 0x00000020
|
||||
@@ -126,7 +127,8 @@ typedef struct at91_pmc {
|
||||
#else
|
||||
#define AT91_PMC_MCKR_MDIV_1 0x00000000
|
||||
#define AT91_PMC_MCKR_MDIV_2 0x00000100
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
|
||||
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
|
||||
#define AT91_PMC_MCKR_MDIV_3 0x00000300
|
||||
#endif
|
||||
#define AT91_PMC_MCKR_MDIV_4 0x00000200
|
||||
|
||||
@@ -133,6 +133,9 @@
|
||||
#define ATMEL_BASE_CS6 0x70000000
|
||||
#define ATMEL_BASE_CS7 0x80000000
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -117,6 +117,9 @@
|
||||
#define ATMEL_BASE_CS6 0x70000000
|
||||
#define ATMEL_BASE_CS7 0x80000000
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -132,6 +132,9 @@
|
||||
#define ATMEL_BASE_CS6 0x70000000
|
||||
#define ATMEL_BASE_CS7 0x80000000
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -136,6 +136,9 @@
|
||||
#define ATMEL_BASE_CS6 0x70000000
|
||||
#define ATMEL_BASE_CS7 0x80000000
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -116,6 +116,9 @@
|
||||
#define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */
|
||||
#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -124,6 +124,16 @@
|
||||
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* External memory
|
||||
*/
|
||||
#define ATMEL_BASE_CS0 0x10000000
|
||||
#define ATMEL_BASE_CS1 0x20000000
|
||||
#define ATMEL_BASE_CS2 0x30000000
|
||||
#define ATMEL_BASE_CS3 0x40000000
|
||||
#define ATMEL_BASE_CS4 0x50000000
|
||||
#define ATMEL_BASE_CS5 0x60000000
|
||||
|
||||
/* 9x5 series chip id definitions */
|
||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||
#define ARCH_ID_VERSION_MASK 0x1f
|
||||
@@ -154,6 +164,9 @@
|
||||
#define ATMEL_CPU_NAME get_cpu_name()
|
||||
#endif
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
|
||||
|
||||
/*
|
||||
* Other misc defines
|
||||
*/
|
||||
|
||||
@@ -189,6 +189,9 @@
|
||||
#define PIO_SCDR_DIV 0x3fff
|
||||
#define CPU_HAS_PCR
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
|
||||
|
||||
/*
|
||||
* PMECC table in ROM
|
||||
*/
|
||||
|
||||
@@ -193,6 +193,9 @@
|
||||
#define cpu_is_sama5d44() (cpu_is_sama5d4() && \
|
||||
(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
|
||||
|
||||
/* Timer */
|
||||
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
|
||||
|
||||
/*
|
||||
* No PMECC Galois table in ROM
|
||||
*/
|
||||
|
||||
@@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
|
||||
|
||||
static int ddr2_decodtype_is_seq(u32 cr)
|
||||
{
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
|
||||
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
|
||||
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
|
||||
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
@@ -29,7 +29,7 @@ u32 spl_boot_device(void)
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
return BOOT_DEVICE_NAND;
|
||||
#elif CONFIG_SYS_USE_SERIALFLASH
|
||||
#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
|
||||
return BOOT_DEVICE_SPI;
|
||||
#endif
|
||||
return BOOT_DEVICE_NONE;
|
||||
|
||||
@@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
void __weak spl_board_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
|
||||
@@ -111,9 +115,14 @@ void spl_board_init(void)
|
||||
timer_init();
|
||||
|
||||
/* enable clocks for all PIOs */
|
||||
#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOAB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOCD);
|
||||
#else
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOA);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOB);
|
||||
at91_periph_clk_enable(ATMEL_ID_PIOC);
|
||||
#endif
|
||||
/* init console */
|
||||
at91_seriald_hw_init();
|
||||
preloader_console_init();
|
||||
|
||||
@@ -70,7 +70,12 @@ __weak void redirect_int_from_saic_to_aic(void)
|
||||
/* This only be used for sama5d4 soc now */
|
||||
}
|
||||
|
||||
/* empty stub to satisfy current lowlevel_init, can be removed any time */
|
||||
void s_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
switch_to_main_crystal_osc();
|
||||
|
||||
@@ -93,4 +98,9 @@ void s_init(void)
|
||||
preloader_console_init();
|
||||
|
||||
mem_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user