ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7
In order to prepare and ease future DT synchronization with kernel DT, migrate all U-boot specific nodes/properties/addons to U-boot DT files. As sdmmc is not yet supported on kernel side, sdmmc nodes are located in eval-u-boot and disco-u-boot DT files. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
parent
fe63d3cfb7
commit
1056303148
@ -1,13 +1,66 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/memory/stm32-sdram.h>
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/{
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clocks {
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u-boot,dm-pre-reloc;
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};
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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mmc0 = &sdmmc1;
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};
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soc {
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u-boot,dm-pre-reloc;
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pin-controller {
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u-boot,dm-pre-reloc;
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};
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fmc: fmc@52004000 {
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compatible = "st,stm32h7-fmc";
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reg = <0x52004000 0x1000>;
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clocks = <&rcc FMC_CK>;
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* firsct bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
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CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
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TWR_1 TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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sdmmc1: sdmmc@52007000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x52007000 0x1000>;
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interrupts = <49>;
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clocks = <&rcc SDMMC1_CK>;
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resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
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st,idma = <1>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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};
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};
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@ -15,21 +68,14 @@
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u-boot,dm-pre-reloc;
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};
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&clk_lse {
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u-boot,dm-pre-reloc;
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};
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&clk_i2s {
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u-boot,dm-pre-reloc;
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};
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&pwrcfg {
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&clk_lse {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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&fmc {
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u-boot,dm-pre-reloc;
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@ -86,3 +132,108 @@
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&gpiok {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
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<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
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<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
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<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
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<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
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<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
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<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
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<STM32H7_PE0_FUNC_FMC_NBL0>,
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<STM32H7_PE1_FUNC_FMC_NBL1>,
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<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
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<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
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<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
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<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
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<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
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<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
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<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
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<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
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<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
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<STM32H7_PF0_FUNC_FMC_A0>,
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<STM32H7_PF1_FUNC_FMC_A1>,
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<STM32H7_PF2_FUNC_FMC_A2>,
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<STM32H7_PF3_FUNC_FMC_A3>,
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<STM32H7_PF4_FUNC_FMC_A4>,
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<STM32H7_PF5_FUNC_FMC_A5>,
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<STM32H7_PF11_FUNC_FMC_SDNRAS>,
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<STM32H7_PF12_FUNC_FMC_A6>,
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<STM32H7_PF13_FUNC_FMC_A7>,
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<STM32H7_PF14_FUNC_FMC_A8>,
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<STM32H7_PF15_FUNC_FMC_A9>,
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<STM32H7_PG0_FUNC_FMC_A10>,
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<STM32H7_PG1_FUNC_FMC_A11>,
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<STM32H7_PG2_FUNC_FMC_A12>,
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<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32H7_PG8_FUNC_FMC_SDCLK>,
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<STM32H7_PG15_FUNC_FMC_SDNCAS>,
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<STM32H7_PH5_FUNC_FMC_SDNWE>,
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<STM32H7_PH6_FUNC_FMC_SDNE1>,
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<STM32H7_PH7_FUNC_FMC_SDCKE1>,
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<STM32H7_PH8_FUNC_FMC_D16>,
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<STM32H7_PH9_FUNC_FMC_D17>,
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<STM32H7_PH10_FUNC_FMC_D18>,
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<STM32H7_PH11_FUNC_FMC_D19>,
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<STM32H7_PH12_FUNC_FMC_D20>,
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<STM32H7_PH13_FUNC_FMC_D21>,
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<STM32H7_PH14_FUNC_FMC_D22>,
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<STM32H7_PH15_FUNC_FMC_D23>,
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<STM32H7_PI0_FUNC_FMC_D24>,
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<STM32H7_PI1_FUNC_FMC_D25>,
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<STM32H7_PI2_FUNC_FMC_D26>,
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<STM32H7_PI3_FUNC_FMC_D27>,
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<STM32H7_PI4_FUNC_FMC_NBL2>,
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<STM32H7_PI5_FUNC_FMC_NBL3>,
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<STM32H7_PI6_FUNC_FMC_D28>,
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<STM32H7_PI7_FUNC_FMC_D29>,
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<STM32H7_PI9_FUNC_FMC_D30>,
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<STM32H7_PI10_FUNC_FMC_D31>;
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slew-rate = <3>;
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};
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};
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pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
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pins {
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pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
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<STM32H7_PB9_FUNC_SDMMC1_CDIR>,
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<STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
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<STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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sdmmc1_pins: sdmmc@0 {
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pins {
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pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
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<STM32H7_PC9_FUNC_SDMMC1_D1>,
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<STM32H7_PC10_FUNC_SDMMC1_D2>,
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<STM32H7_PC11_FUNC_SDMMC1_D3>,
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<STM32H7_PC12_FUNC_SDMMC1_CK>,
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<STM32H7_PD2_FUNC_SDMMC1_CMD>;
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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@ -44,7 +44,7 @@
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/ {
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soc {
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pin-controller {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32h743-pinctrl";
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@ -175,101 +175,6 @@
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bias-disable;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
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<STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
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<STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
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<STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
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<STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
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<STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
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<STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
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<STM32H7_PE0_FUNC_FMC_NBL0>,
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<STM32H7_PE1_FUNC_FMC_NBL1>,
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<STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
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<STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
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<STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
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<STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
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<STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
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<STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
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<STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
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<STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
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<STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
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<STM32H7_PF0_FUNC_FMC_A0>,
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<STM32H7_PF1_FUNC_FMC_A1>,
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<STM32H7_PF2_FUNC_FMC_A2>,
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<STM32H7_PF3_FUNC_FMC_A3>,
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<STM32H7_PF4_FUNC_FMC_A4>,
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<STM32H7_PF5_FUNC_FMC_A5>,
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<STM32H7_PF11_FUNC_FMC_SDNRAS>,
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<STM32H7_PF12_FUNC_FMC_A6>,
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<STM32H7_PF13_FUNC_FMC_A7>,
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<STM32H7_PF14_FUNC_FMC_A8>,
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<STM32H7_PF15_FUNC_FMC_A9>,
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<STM32H7_PG0_FUNC_FMC_A10>,
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<STM32H7_PG1_FUNC_FMC_A11>,
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<STM32H7_PG2_FUNC_FMC_A12>,
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<STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32H7_PG8_FUNC_FMC_SDCLK>,
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<STM32H7_PG15_FUNC_FMC_SDNCAS>,
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<STM32H7_PH5_FUNC_FMC_SDNWE>,
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<STM32H7_PH6_FUNC_FMC_SDNE1>,
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<STM32H7_PH7_FUNC_FMC_SDCKE1>,
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<STM32H7_PH8_FUNC_FMC_D16>,
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<STM32H7_PH9_FUNC_FMC_D17>,
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<STM32H7_PH10_FUNC_FMC_D18>,
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<STM32H7_PH11_FUNC_FMC_D19>,
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<STM32H7_PH12_FUNC_FMC_D20>,
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<STM32H7_PH13_FUNC_FMC_D21>,
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<STM32H7_PH14_FUNC_FMC_D22>,
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<STM32H7_PH15_FUNC_FMC_D23>,
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<STM32H7_PI0_FUNC_FMC_D24>,
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<STM32H7_PI1_FUNC_FMC_D25>,
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<STM32H7_PI2_FUNC_FMC_D26>,
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<STM32H7_PI3_FUNC_FMC_D27>,
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<STM32H7_PI4_FUNC_FMC_NBL2>,
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<STM32H7_PI5_FUNC_FMC_NBL3>,
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<STM32H7_PI6_FUNC_FMC_D28>,
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<STM32H7_PI7_FUNC_FMC_D29>,
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<STM32H7_PI9_FUNC_FMC_D30>,
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<STM32H7_PI10_FUNC_FMC_D31>;
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slew-rate = <3>;
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};
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};
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sdmmc1_pins: sdmmc@0 {
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pins {
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pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
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<STM32H7_PC9_FUNC_SDMMC1_D1>,
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<STM32H7_PC10_FUNC_SDMMC1_D2>,
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<STM32H7_PC11_FUNC_SDMMC1_D3>,
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<STM32H7_PC12_FUNC_SDMMC1_CK>,
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<STM32H7_PD2_FUNC_SDMMC1_CMD>;
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slew-rate = <3>;
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drive-push-pull;
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bias-disable;
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};
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};
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pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
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pins {
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pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
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<STM32H7_PB9_FUNC_SDMMC1_CDIR>,
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<STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
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<STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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};
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};
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};
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@ -104,12 +104,6 @@
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reg = <0x58024800 0x400>;
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};
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fmc: fmc@52004000 {
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compatible = "st,stm32h7-fmc";
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reg = <0x52004000 0x1000>;
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clocks = <&rcc FMC_CK>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -121,18 +115,6 @@
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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sdmmc1: sdmmc@52007000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x52007000 0x1000>;
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interrupts = <49>;
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clocks = <&rcc SDMMC1_CK>;
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resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
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st,idma = <1>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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status = "disabled";
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};
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};
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};
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11
arch/arm/dts/stm32h743i-disco-u-boot.dtsi
Normal file
11
arch/arm/dts/stm32h743i-disco-u-boot.dtsi
Normal file
@ -0,0 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <stm32h7-u-boot.dtsi>
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&sdmmc1 {
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status = "okay";
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pinctrl-0 = <&sdmmc1_pins>;
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pinctrl-names = "default";
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bus-width = <4>;
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cd-gpios = <&gpioi 8 1>;
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};
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@ -43,7 +43,6 @@
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/dts-v1/;
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#include "stm32h743.dtsi"
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#include "stm32h743-pinctrl.dtsi"
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#include <dt-bindings/memory/stm32-sdram.h>
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/ {
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model = "STMicroelectronics STM32H743i-Discovery board";
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@ -60,18 +59,6 @@
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aliases {
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serial0 = &usart2;
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mmc0 = &sdmmc1;
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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};
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};
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@ -81,29 +68,3 @@
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status = "okay";
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};
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&fmc {
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* Memory configuration from sdram datasheet IS42S32800G-6BLI
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* firsct bank is bank@0
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* second bank is bank@1
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*/
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bank1: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
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CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
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TWR_1 TRCD_1>;
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st,sdram-refcount = <1539>;
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};
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};
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&sdmmc1 {
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status = "okay";
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pinctrl-0 = <&sdmmc1_pins>;
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pinctrl-names = "default";
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bus-width = <4>;
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cd-gpios = <&gpioi 8 1>;
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};
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||||
12
arch/arm/dts/stm32h743i-eval-u-boot.dtsi
Normal file
12
arch/arm/dts/stm32h743i-eval-u-boot.dtsi
Normal file
@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
#include <stm32h7-u-boot.dtsi>
|
||||
|
||||
&sdmmc1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdmmc1_pins>,
|
||||
<&pinctrl_sdmmc1_level_shifter>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
st,dirpol;
|
||||
};
|
||||
@ -43,7 +43,6 @@
|
||||
/dts-v1/;
|
||||
#include "stm32h743.dtsi"
|
||||
#include "stm32h743-pinctrl.dtsi"
|
||||
#include <dt-bindings/memory/stm32-sdram.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32H743i-EVAL board";
|
||||
@ -60,17 +59,6 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio9 = &gpioj;
|
||||
gpio10 = &gpiok;
|
||||
};
|
||||
};
|
||||
|
||||
@ -79,31 +67,3 @@
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
pinctrl-0 = <&fmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Memory configuration from sdram datasheet IS42S32800G-6BLI
|
||||
* firsct bank is bank@0
|
||||
* second bank is bank@1
|
||||
*/
|
||||
bank2: bank@1 {
|
||||
st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
|
||||
CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
|
||||
st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
|
||||
TWR_1 TRCD_1>;
|
||||
st,sdram-refcount = <1539>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdmmc1_pins>,
|
||||
<&pinctrl_sdmmc1_level_shifter>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
st,dirpol;
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user