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keystone2: ddr: add DDR3 PHY configs updated for PG 2.0

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Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Hao Zhang
2014-07-09 19:48:41 +03:00
committed by Tom Rini
parent 0b86858956
commit 101eec50f0
4 changed files with 100 additions and 2 deletions
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19
arch/arm/cpu/armv7/keystone/ddr3.c
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@@ -8,6 +8,7 @@
*/
#include <asm/io.h>
#include <common.h>
#include <asm/arch/ddr3.h>
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
@@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
void ddr3_reset_ddrphy(void)
{
u32 tmp;
/* Assert DDR3A PHY reset */
tmp = readl(K2HK_DDR3APLLCTL1);
tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
writel(tmp, K2HK_DDR3APLLCTL1);
/* wait 10us to catch the reset */
udelay(10);
/* Release DDR3A PHY reset */
tmp = readl(K2HK_DDR3APLLCTL1);
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, K2HK_DDR3APLLCTL1);
}

1
arch/arm/include/asm/arch-keystone/ddr3.h
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@@ -49,6 +49,7 @@ struct ddr3_emif_config {
};
void ddr3_init(void);
void ddr3_reset_ddrphy(void);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);

2
arch/arm/include/asm/arch-keystone/hardware.h
View File

@@ -80,6 +80,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000