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CONFIG_SPL_SYS_[DI]CACHE_OFF: add

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While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Trevor Woerner 2019-05-03 09:41:00 -04:00 committed by Tom Rini
parent a0aba8a2eb
commit 1001502545
92 changed files with 206 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arc/Kconfig
View File

@ -114,12 +114,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
menuconfig ARC_DBG
bool "ARC debugging"
default n

4
arch/arc/lib/start.S
View File

@ -16,7 +16,7 @@ ENTRY(_start)
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@ -37,7 +37,7 @@ ENTRY(_start)
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)

14
arch/arm/Kconfig
View File

@ -80,12 +80,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help

12
arch/arm/cpu/arm11/cpu.c
View File

@ -51,7 +51,7 @@ static void cache_flush(void)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@ -95,15 +95,15 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

12
arch/arm/cpu/arm926ejs/cache.c
View File

@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@ -54,7 +54,7 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {}
__weak void invalidate_l2_cache(void) {}
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
@ -80,10 +80,10 @@ void invalidate_icache_all(void) {}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

2
arch/arm/cpu/arm926ejs/cpu.c
View File

@ -44,7 +44,7 @@ int cleanup_before_linux (void)
/* flush I/D-cache */
static void cache_flush (void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));

4
arch/arm/cpu/arm926ejs/start.S
View File

@ -84,7 +84,7 @@ flush_dcache:
/*
* disable MMU and D cache
* enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
* enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@ -95,7 +95,7 @@ flush_dcache:
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0

8
arch/arm/cpu/armv7/cache_v7.c
View File

@ -12,7 +12,7 @@
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
flush_dcache_range(start, stop);
v7_inval_tlb();
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
void arm_init_domains(void)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{

2
arch/arm/cpu/armv7/iproc-common/hwinit-common.c
View File

@ -5,7 +5,7 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/cpu/armv7/kona-common/hwinit-common.c
View File

@ -6,7 +6,7 @@
#include <common.h>
#include <linux/sizes.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

4
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
@ -215,7 +215,7 @@ void enable_caches(void)
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)

4
arch/arm/cpu/armv7/start.S
View File

@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup)
/*
* If I-cache is enabled invalidate it
*/
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache

2
arch/arm/cpu/armv7/vf610/generic.c
View File

@ -360,7 +360,7 @@ int get_clocks(void)
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

8
arch/arm/cpu/armv7m/cache.c
View File

@ -54,7 +54,7 @@ enum cache_action {
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
@ -292,7 +292,7 @@ void invalidate_dcache_all(void)
}
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
@ -349,10 +349,10 @@ int icache_status(void)
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

12
arch/arm/cpu/armv8/cache_v8.c
View File

@ -13,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
@ -657,7 +657,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
__asm_invalidate_tlb_all();
}
#else /* CONFIG_SYS_DCACHE_OFF */
#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@ -694,9 +694,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
{
}
#endif /* CONFIG_SYS_DCACHE_OFF */
#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
@ -720,7 +720,7 @@ void invalidate_icache_all(void)
__asm_invalidate_l3_icache();
}
#else /* CONFIG_SYS_ICACHE_OFF */
#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
@ -739,7 +739,7 @@ void invalidate_icache_all(void)
{
}
#endif /* CONFIG_SYS_ICACHE_OFF */
#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled

4
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -388,7 +388,7 @@ void cpu_name(char *name)
strcpy(name, "unknown");
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@ -611,7 +611,7 @@ void enable_caches(void)
icache_enable();
dcache_enable();
}
#endif /* CONFIG_SYS_DCACHE_OFF */
#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)

2
arch/arm/cpu/armv8/s32v234/cpu.c
View File

@ -16,7 +16,7 @@ u32 cpu_mask(void)
return readl(MC_ME_CS);
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL

6
arch/arm/cpu/pxa/cache.c
View File

@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
{
return invalidate_dcache_range(start, stop);
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@ -43,7 +43,7 @@ void invalidate_dcache_all(void)
void flush_dcache_all(void)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations

4
arch/arm/cpu/pxa/pxa2xx.c
View File

@ -286,10 +286,10 @@ void reset_cpu(ulong ignored)
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

2
arch/arm/include/asm/global_data.h
View File

@ -35,7 +35,7 @@ struct arch_global_data {
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)

6
arch/arm/lib/cache-cp15.c
View File

@ -10,7 +10,7 @@
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit)
}
#endif
#ifdef CONFIG_SYS_ICACHE_OFF
#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
@ -278,7 +278,7 @@ int icache_status(void)
}
#endif
#ifdef CONFIG_SYS_DCACHE_OFF
#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;

2
arch/arm/lib/cache.c
View File

@ -87,7 +87,7 @@ void noncached_init(void)
noncached_end = end;
noncached_next = start;
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}

2
arch/arm/mach-exynos/soc.c
View File

@ -25,7 +25,7 @@ void reset_cpu(ulong addr)
#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-imx/cache.c
View File

@ -37,7 +37,7 @@ static void enable_ca7_smp(void)
}
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

2
arch/arm/mach-imx/imx8/cpu.c
View File

@ -446,7 +446,7 @@ void enable_caches(void)
dcache_enable();
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);

2
arch/arm/mach-imx/mx5/soc.c
View File

@ -62,7 +62,7 @@ u32 __weak get_board_rev(void)
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-keystone/init.c
View File

@ -204,7 +204,7 @@ void reset_cpu(ulong addr)
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif

2
arch/arm/mach-omap2/Makefile
View File

@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
endif
ifeq ($(CONFIG_SYS_DCACHE_OFF),)
ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif

6
arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
View File

@ -16,7 +16,7 @@
.arch_extension sec
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1)
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1)
*/
.section .data
omap_smc_sec_cpu1_args:
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0

4
arch/arm/mach-omap2/sec-common.c
View File

@ -333,7 +333,7 @@ int secure_tee_install(u32 addr)
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@ -356,7 +356,7 @@ int secure_tee_install(u32 addr)
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif

2
arch/arm/mach-rmobile/cpu_info.c
View File

@ -17,7 +17,7 @@ int arch_cpu_init(void)
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();

2
arch/arm/mach-rockchip/rk3036-board.c
View File

@ -48,7 +48,7 @@ int dram_init(void)
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-rockchip/rk3128-board.c
View File

@ -57,7 +57,7 @@ int dram_init_banksize(void)
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-rockchip/rk3188-board.c
View File

@ -75,7 +75,7 @@ err:
#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-rockchip/rk322x-board.c
View File

@ -58,7 +58,7 @@ int dram_init_banksize(void)
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-rockchip/rk3288-board.c
View File

@ -186,7 +186,7 @@ err:
#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-rockchip/rv1108/rv1108.c
View File

@ -6,7 +6,7 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-s5pc1xx/cache.c
View File

@ -9,7 +9,7 @@
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();

4
arch/arm/mach-socfpga/misc.c
View File

@ -48,10 +48,10 @@ int dram_init(void)
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

2
arch/arm/mach-sunxi/board.c
View File

@ -300,7 +300,7 @@ void reset_cpu(ulong addr)
#endif
}
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-tegra/board.c
View File

@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = {
};
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
arch/arm/mach-zynq/cpu.c
View File

@ -83,7 +83,7 @@ void reset_cpu(ulong addr)
;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

14
arch/nds32/Kconfig
View File

@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"

8
arch/nds32/cpu/n1213/start.S
View File

@ -129,7 +129,7 @@ set_ivb:
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
@ -139,7 +139,7 @@ set_ivb:
mtsr $r1, $mr0
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
@ -158,14 +158,14 @@ set_ivb:
#endif
#endif
#if !defined(CONFIG_SYS_ICACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0

6
arch/nds32/lib/cache.c
View File

@ -6,7 +6,7 @@
*/
#include <common.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
}
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
unsigned long end, line_size;
@ -133,7 +133,7 @@ int icache_status(void)
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_wbinval_all(void)
{
unsigned long end, line_size;

14
arch/riscv/Kconfig
View File

@ -25,12 +25,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"

8
arch/riscv/cpu/ax25/cache.c
View File

@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
void icache_enable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@ -43,7 +43,7 @@ void icache_enable(void)
void icache_disable(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
@ -57,7 +57,7 @@ void icache_disable(void)
void dcache_enable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@ -70,7 +70,7 @@ void dcache_enable(void)
void dcache_disable(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"

14
arch/xtensa/Kconfig
View File

@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
source "board/cadence/xtfpga/Kconfig"
endmenu

7
arch/xtensa/cpu/start.S
View File

@ -164,18 +164,19 @@ _start:
* enable data/instruction cache for relocated image.
*/
#if XCHAL_HAVE_SPANNING_WAY && \
!(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
!(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
srli a7, a4, 29
slli a7, a7, 29
addi a7, a7, XCHAL_SPANNING_WAY
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
rdtlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
addi a8, a8, CA_WRITEBACK
wdtlb a8, a7
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
ritlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4

2
board/st/stih410-b2260/board.c
View File

@ -26,7 +26,7 @@ int dram_init_banksize(void)
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */

2
cmd/bdinfo.c
View File

@ -321,7 +321,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
print_eths();
#endif
print_baudrate();
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);

2
common/board_f.c
View File

@ -381,7 +381,7 @@ static int reserve_round_4k(void)
#ifdef CONFIG_ARM
__weak int reserve_mmu(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;

2
common/lcd.c
View File

@ -61,7 +61,7 @@ void lcd_sync(void)
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
int line_length;
if (lcd_flush_dcache)

1
configs/axm_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set

1
configs/bitmain_antminer_s9_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="bitmain"
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL_STACK_R_ADDR=0x200000

2
configs/imx8mq_evk_defconfig
View File

@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8MQ_EVK=y

2
configs/imx8qm_mek_defconfig
View File

@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y

2
configs/imx8qxp_mek_defconfig
View File

@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y

2
configs/smartweb_defconfig
View File

@ -2,6 +2,8 @@ CONFIG_ARM=y
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23000000
CONFIG_TARGET_SMARTWEB=y

1
configs/syzygy_hub_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y

2
configs/taurus_defconfig
View File

@ -2,6 +2,8 @@ CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000

1
configs/topic_miami_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y

1
configs/topic_miamilite_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y

1
configs/topic_miamiplus_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y

1
configs/zynq_cc108_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_cse_nand_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_cse_nor_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_dlc20_rev1_0_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_microzed_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_minized_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_picozed_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_z_turn_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc702_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc706_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc770_xm010_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc770_xm011_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc770_xm011_x16_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc770_xm012_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zc770_xm013_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zed_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zybo_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

1
configs/zynq_zybo_z7_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000

2
drivers/dma/apbh_dma.c
View File

@ -81,7 +81,7 @@ static int mxs_dma_read_semaphore(int channel)
return tmp;
}
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
{
uint32_t addr;

2
drivers/mtd/nand/raw/mxs_nand.c
View File

@ -50,7 +50,7 @@ struct nand_ecclayout fake_ecc_layout;
/*
* Cache management functions
*/
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
uint32_t addr = (uint32_t)info->data_buf;

2
drivers/net/dwc_eth_qos.c
View File

@ -241,7 +241,7 @@ struct eqos_tegra186_regs {
*/
#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
!defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning Cache line size is larger than descriptor size
#endif
#endif

2
drivers/net/rtl8169.c
View File

@ -302,7 +302,7 @@ static unsigned char rxdata[RX_BUF_LEN];
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
!defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning cache-line size is larger than descriptor size
#endif
#endif

3
drivers/net/sh_eth.c
View File

@ -34,7 +34,8 @@
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((u32)addr, \
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))

2
drivers/video/video-uclass.c
View File

@ -149,7 +149,7 @@ void video_sync(struct udevice *vid, bool force)
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct video_priv *priv = dev_get_uclass_priv(vid);
if (priv->flush_dcache) {

2
include/configs/mx7ulp_evk.h
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@ -167,7 +167,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#ifndef CONFIG_SYS_DCACHE_OFF
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define CONFIG_CMD_CACHE
#endif

5
include/configs/smartweb.h
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@ -216,11 +216,6 @@
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10483f0e
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#endif
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO

4
include/configs/taurus.h
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@ -21,10 +21,6 @@
#include <asm/hardware.h>
#include <linux/sizes.h>
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.

5
include/configs/zynq-common.h
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@ -284,11 +284,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#endif
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000