arm: Remove armadillo-800eva board
This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it. Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
d8d5ab40d5
commit
0fb054b3f7
@ -50,9 +50,6 @@ choice
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prompt "Renesas ARM SoCs board select"
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optional
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config TARGET_ARMADILLO_800EVA
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bool "armadillo 800 eva board"
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config TARGET_BLANCHE
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bool "Blanche board"
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select DM
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@ -156,7 +153,6 @@ config QOS_PRI_GFX
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endchoice
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source "board/atmark-techno/armadillo-800eva/Kconfig"
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source "board/renesas/blanche/Kconfig"
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source "board/renesas/gose/Kconfig"
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source "board/renesas/koelsch/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_ARMADILLO_800EVA
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config SYS_BOARD
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default "armadillo-800eva"
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config SYS_VENDOR
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default "atmark-techno"
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config SYS_CONFIG_NAME
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default "armadillo-800eva"
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endif
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@ -1,6 +0,0 @@
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ARMADILLO-800EVA BOARD
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M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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S: Maintained
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F: board/atmark-techno/armadillo-800eva/
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F: include/configs/armadillo-800eva.h
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F: configs/armadillo-800eva_defconfig
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@ -1,5 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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obj-y += armadillo-800eva.o
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@ -1,327 +0,0 @@
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/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/global_data.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#define s_init_wait(cnt) \
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({ \
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volatile u32 i = 0x10000 * cnt; \
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while (i > 0) \
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i--; \
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})
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#define USBCR1 0xE605810A
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void s_init(void)
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{
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struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
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struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
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struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
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struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
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struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
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struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
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/* Watchdog init */
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writew(0xA500, &rwdt0->rwtcsra0);
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writew(0xA500, &rwdt1->rwtcsra0);
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/* CPG */
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writel(0xFF800080, &cpg->rmstpcr4);
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writel(0xFF800080, &cpg->smstpcr4);
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/* USB clock */
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writel(0x00000080, &cpg->usbckcr);
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s_init_wait(1);
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/* USBCR1 */
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writew(0x0710, USBCR1);
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/* FRQCR */
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writel(0x00000000, &cpg->frqcrb);
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writel(0x62030533, &cpg->frqcra);
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writel(0x208A354E, &cpg->frqcrc);
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writel(0x80331050, &cpg->frqcrb);
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s_init_wait(1);
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writel(0x00000000, &cpg->frqcrd);
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s_init_wait(1);
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/* SUBClk */
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writel(0x0000010B, &cpg->subckcr);
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/* PLL */
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writel(0x00004004, &cpg->pllc01cr);
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s_init_wait(1);
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writel(0xa0000000, &cpg->pllc2cr);
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s_init_wait(2);
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/* BSC */
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writel(0x0000001B, &bsc->cmncr);
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writel(0x20000000, &dbsc->dbcmd);
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writel(0x10009C40, &dbsc->dbcmd);
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s_init_wait(1);
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writel(0x00000007, &dbsc->dbkind);
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writel(0x0E030A02, &dbsc->dbconf0);
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writel(0x00000001, &dbsc->dbphytype);
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writel(0x00000000, &dbsc->dbbl);
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writel(0x00000006, &dbsc->dbtr0);
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writel(0x00000005, &dbsc->dbtr1);
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writel(0x00000000, &dbsc->dbtr2);
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writel(0x00000006, &dbsc->dbtr3);
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writel(0x00080006, &dbsc->dbtr4);
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writel(0x00000015, &dbsc->dbtr5);
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writel(0x0000000f, &dbsc->dbtr6);
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writel(0x00000004, &dbsc->dbtr7);
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writel(0x00000018, &dbsc->dbtr8);
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writel(0x00000006, &dbsc->dbtr9);
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writel(0x00000006, &dbsc->dbtr10);
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writel(0x0000000F, &dbsc->dbtr11);
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writel(0x0000000D, &dbsc->dbtr12);
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writel(0x000000A0, &dbsc->dbtr13);
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writel(0x000A0003, &dbsc->dbtr14);
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writel(0x00000003, &dbsc->dbtr15);
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writel(0x40005005, &dbsc->dbtr16);
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writel(0x0C0C0000, &dbsc->dbtr17);
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writel(0x00000200, &dbsc->dbtr18);
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writel(0x00000040, &dbsc->dbtr19);
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writel(0x00000001, &dbsc->dbrnk0);
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writel(0x00000110, &dbsc->dbdficnt);
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writel(0x00000101, &ddrp->funcctrl);
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writel(0x00000001, &ddrp->dllctrl);
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writel(0x00000186, &ddrp->zqcalctrl);
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writel(0xB3440051, &ddrp->zqodtctrl);
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writel(0x94449443, &ddrp->rdctrl);
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writel(0x000000C0, &ddrp->rdtmg);
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writel(0x00000101, &ddrp->fifoinit);
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writel(0x02060506, &ddrp->outctrl);
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writel(0x00004646, &ddrp->dqcalofs1);
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writel(0x00004646, &ddrp->dqcalofs2);
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writel(0x800000aa, &ddrp->dqcalexp);
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writel(0x00000000, &ddrp->dllctrl);
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writel(0x00000000, DDRPNCNT);
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writel(0x0000000C, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00000002, DDRPNCNT);
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writel(0x0000000C, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00000187, &ddrp->zqcalctrl);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00000010, &dbsc->dbdficnt);
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writel(0x02060507, &ddrp->outctrl);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x21009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x00009C40, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x11000044, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x2A000000, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x2B000000, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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writel(0x29000004, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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writel(0x28001520, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x03000200, &dbsc->dbcmd);
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readl(&dbsc->dbwait);
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s_init_wait(1);
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writel(0x000001FF, &dbsc->dbrfcnf0);
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writel(0x00010C30, &dbsc->dbrfcnf1);
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writel(0x00000000, &dbsc->dbrfcnf2);
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writel(0x00000001, &dbsc->dbrfen);
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writel(0x00000001, &dbsc->dbacen);
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/* BSC */
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writel(0x00410400, &bsc->cs0bcr);
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writel(0x00410400, &bsc->cs2bcr);
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writel(0x00410400, &bsc->cs5bbcr);
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writel(0x02CB0400, &bsc->cs6abcr);
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writel(0x00000440, &bsc->cs0wcr);
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writel(0x00000440, &bsc->cs2wcr);
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writel(0x00000240, &bsc->cs5bwcr);
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writel(0x00000240, &bsc->cs6awcr);
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writel(0x00000005, &bsc->rbwtcnt);
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writel(0x00000002, &bsc->cs0wcr2);
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writel(0x00000002, &bsc->cs2wcr2);
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writel(0x00000002, &bsc->cs4wcr2);
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}
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#define GPIO_ICCR (0xE60581A0)
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#define ICCR_15BIT (1 << 15) /* any time 1 */
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#define IIC0_CONTA (1 << 7)
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#define IIC0_CONTB (1 << 6)
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#define IIC1_CONTA (1 << 5)
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#define IIC1_CONTB (1 << 4)
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#define IIC0_PS33E (1 << 1)
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#define IIC1_PS33E (1 << 0)
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#define GPIO_ICCR_DATA \
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(ICCR_15BIT | \
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IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
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IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
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#define MSTPCR1 0xE6150134
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#define TMU0_MSTP125 (1 << 25)
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#define I2C0_MSTP116 (1 << 16)
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#define MSTPCR3 0xE615013C
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#define I2C1_MSTP323 (1 << 23)
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#define GETHER_MSTP309 (1 << 9)
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#define GPIO_SCIFA1_TXD (0xE60520C4)
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#define GPIO_SCIFA1_RXD (0xE60520C3)
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int board_early_init_f(void)
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{
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/* TMU */
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clrbits_le32(MSTPCR1, TMU0_MSTP125);
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/* GETHER */
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clrbits_le32(MSTPCR3, GETHER_MSTP309);
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/* I2C 0/1 */
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clrbits_le32(MSTPCR1, I2C0_MSTP116);
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clrbits_le32(MSTPCR3, I2C1_MSTP323);
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/* SCIFA1 */
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writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
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writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
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/* IICCR */
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writew(GPIO_ICCR_DATA, GPIO_ICCR);
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return 0;
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}
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/* board id for linux */
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gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7740_pinmux_init();
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/* GETHER Enable */
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gpio_request(GPIO_FN_ET_CRS, NULL);
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gpio_request(GPIO_FN_ET_MDC, NULL);
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gpio_request(GPIO_FN_ET_MDIO, NULL);
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gpio_request(GPIO_FN_ET_TX_ER, NULL);
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gpio_request(GPIO_FN_ET_RX_ER, NULL);
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gpio_request(GPIO_FN_ET_ERXD0, NULL);
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gpio_request(GPIO_FN_ET_ERXD1, NULL);
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gpio_request(GPIO_FN_ET_ERXD2, NULL);
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gpio_request(GPIO_FN_ET_ERXD3, NULL);
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gpio_request(GPIO_FN_ET_TX_CLK, NULL);
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gpio_request(GPIO_FN_ET_TX_EN, NULL);
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gpio_request(GPIO_FN_ET_ETXD0, NULL);
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gpio_request(GPIO_FN_ET_ETXD1, NULL);
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gpio_request(GPIO_FN_ET_ETXD2, NULL);
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gpio_request(GPIO_FN_ET_ETXD3, NULL);
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gpio_request(GPIO_FN_ET_PHY_INT, NULL);
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gpio_request(GPIO_FN_ET_COL, NULL);
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gpio_request(GPIO_FN_ET_RX_DV, NULL);
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gpio_request(GPIO_FN_ET_RX_CLK, NULL);
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gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
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gpio_direction_output(GPIO_PORT18, 1);
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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void reset_cpu(void)
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{
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}
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@ -1,54 +0,0 @@
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CONFIG_ARM=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_ARCH_CPU_INIT=y
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# CONFIG_SYS_THUMB_BUILD is not set
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0xE80C0000
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CONFIG_SYS_MALLOC_LEN=0x100000
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CONFIG_SYS_MALLOC_F_LEN=0x400
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board"
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CONFIG_R8A7740=y
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CONFIG_TARGET_ARMADILLO_800EVA=y
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CONFIG_SYS_CLK_FREQ=50000000
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CONFIG_SYS_LOAD_ADDR=0x44000000
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CONFIG_ENV_ADDR=0x40000
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe8083000
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CONFIG_SYS_MONITOR_BASE=0x00000000
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CONFIG_BOOTDELAY=3
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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CONFIG_SYS_CBSIZE=256
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CONFIG_SYS_PBSIZE=256
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_SAVEENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_LOADB is not set
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CONFIG_CMD_SDRAM=y
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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# CONFIG_CMD_SLEEP is not set
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_MMC is not set
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CONFIG_BITBANGMII=y
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CONFIG_BITBANGMII_MULTI=y
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CONFIG_PHY_SMSC=y
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CONFIG_SH_ETHER=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,61 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuation settings for the bonito board
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*/
|
||||
|
||||
#ifndef __ARMADILLO_800EVA_H
|
||||
#define __ARMADILLO_800EVA_H
|
||||
|
||||
#define CONFIG_SH_GPIO_PFC
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_TMU_TIMER
|
||||
#define CONFIG_SYS_TIMER_COUNTS_DOWN
|
||||
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
|
||||
#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4)
|
||||
|
||||
/* STACK */
|
||||
#define STACK_AREA_SIZE 0xC000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
|
||||
/* MEMORY */
|
||||
#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
|
||||
#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define SCIF0_BASE 0xe6c40000
|
||||
#define SCIF1_BASE 0xe6c50000
|
||||
#define SCIF2_BASE 0xe6c60000
|
||||
#define SCIF4_BASE 0xe6c80000
|
||||
#define CONFIG_SCIF_A
|
||||
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
|
||||
|
||||
/* ENV setting */
|
||||
|
||||
/* SH Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x0
|
||||
#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
|
||||
#define CONFIG_SH_ETHER_SH7734_MII (0x01)
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
|
||||
#endif /* __ARMADILLO_800EVA_H */
|
||||
Loading…
Reference in New Issue
Block a user