ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -11,8 +11,6 @@
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#include <linux/sizes.h>
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#include <asm/system.h>
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#include "ssc-regs.h"
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ENTRY(lowlevel_init)
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mov r8, lr @ persevere link reg across call
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@ -88,39 +86,37 @@ ENDPROC(enable_mmu)
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*/
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#define BOOT_RAM_SIZE (SZ_32K)
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#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
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#define BOOT_WAY_BITS (0x00000100) /* way 8 */
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#define BOOT_RAM_WAYS (0x00000100) @ way 8
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#define SSCO_BASE 0x506c0000
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#define SSCOPE 0x244
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#define SSCOQM 0x248
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#define SSCOQAD 0x24c
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#define SSCOQSZ 0x250
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#define SSCOQWN 0x258
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#define SSCOPPQSEF 0x25c
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#define SSCOLPQS 0x260
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ENTRY(setup_init_ram)
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/*
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* Touch to zero for the boot way
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*/
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0:
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/*
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* set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order
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*/
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ldr r0, = 0x00408006 @ touch to zero with address range
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ldr r1, = UNIPHIER_SSCOQM
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str r0, [r1]
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ldr r1, = SSCO_BASE
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/* Touch to zero for the boot way */
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0: ldr r0, = 0x00408006 @ touch to zero with address range
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str r0, [r1, #SSCOQM]
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ldr r0, = BOOT_RAM_BASE
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ldr r1, = UNIPHIER_SSCOQAD
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str r0, [r1]
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str r0, [r1, #SSCOQAD]
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ldr r0, = BOOT_RAM_SIZE
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ldr r1, = UNIPHIER_SSCOQSZ
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str r0, [r1]
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ldr r0, = BOOT_WAY_BITS
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ldr r1, = UNIPHIER_SSCOQWN
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str r0, [r1]
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ldr r1, = UNIPHIER_SSCOPPQSEF
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ldr r0, [r1]
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str r0, [r1, #SSCOQSZ]
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ldr r0, = BOOT_RAM_WAYS
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str r0, [r1, #SSCOQWN]
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ldr r0, [r1, #SSCOPPQSEF]
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cmp r0, #0 @ check if the command is successfully set
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bne 0b @ try again if an error occurs
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ldr r1, = UNIPHIER_SSCOLPQS
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1:
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ldr r0, [r1]
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1: ldr r0, [r1, #SSCOLPQS]
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cmp r0, #0x4
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bne 1b @ wait until the operation is completed
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str r0, [r1] @ clear the complete notification flag
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str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
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mov pc, lr
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ENDPROC(setup_init_ram)
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