ddr: altera: sdram: Clean up set_sdr_addr_rw()
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. Signed-off-by: Marek Vasut <marex@denx.de>
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@ -371,34 +371,24 @@ static void set_sdr_dram_timing(void)
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static void set_sdr_addr_rw(void)
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{
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int rows;
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debug("Configuring DRAMADDRW\n");
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clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
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/*
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* SDRAM Failure When Accessing Non-Existent Memory
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* Update Preloader to artificially increase the number of rows so
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* that the memory thinks it has 4GB of RAM.
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*/
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rows = get_errata_rows();
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clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
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rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
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clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
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/* SDRAM Failure When Accessing Non-Existent Memory
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* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
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* log2(number of chip select bits). Since there's only
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* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
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* which is the same as "chip selects" - 1.
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*/
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clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
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const int rows = get_errata_rows();
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const u32 dram_addrw =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
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(rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
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((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
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debug("Configuring DRAMADDRW\n");
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writel(dram_addrw, &sdr_ctrl->dram_addrw);
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}
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static void set_sdr_static_cfg(void)
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