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armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

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Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Hou Zhiqiang
2016-09-29 12:42:44 +08:00
committed by York Sun
parent adee1d4c9e
commit 0ea3671d35
3 changed files with 21 additions and 0 deletions
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2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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@@ -168,6 +168,8 @@ struct sys_info {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000