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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2018-07-27 13:09:30 -04:00
commit 0e8a8a3110
54 changed files with 334 additions and 182 deletions
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4
Makefile
View File

@ -1111,8 +1111,8 @@ u-boot.sha1: u-boot.bin
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
ifdef CONFIG_TPL
SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
ifneq ($(CONFIG_SPL_PAYLOAD),)
SPL_PAYLOAD := $(CONFIG_SPL_PAYLOAD:"%"=%)
else
SPL_PAYLOAD := u-boot.bin
endif

10
arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
View File

@ -129,6 +129,16 @@ Example:
The "loadables" is not optional. It tells SPL which images to load into memory.
Falcon mode with QSPI boot
--------------------------
To use falcon mode with QSPI boot, SPL needs to be enabled. Similar to SD or
NAND boot, a RAM version full feature U-Boot is needed. Unlike SD or NAND boot,
SPL with QSPI doesn't need to combine SPL image with RAM version image. Two
separated images are used, u-boot-spl.pbl and u-boot.img. The former is SPL
image with RCW and PBI commands to load the SPL payload into On-Chip RAM. The
latter is RAM version U-Boot in FIT format (or legacy format if FIT is not
used).
Other things to consider
-----------------------
Falcon boot skips a lot of initialization in U-Boot. If Linux expects the

54
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -6,8 +6,6 @@
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
#endif
#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(false);
#endif
return 0;
}
#endif
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
}
#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(false);
return 0;
}
#endif
static void erratum_a009929(void)
{
@ -719,9 +668,6 @@ int qspi_ahb_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif

8
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -11,6 +11,7 @@
#include <fsl_csu.h>
#include <asm/arch/fdt.h>
#include <asm/arch/ppa.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
@ -21,6 +22,9 @@ u32 spl_boot_device(void)
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
return BOOT_DEVICE_NAND;
#endif
#ifdef CONFIG_QSPI_BOOT
return BOOT_DEVICE_NOR;
#endif
return 0;
}
@ -52,6 +56,7 @@ void spl_board_init(void)
void board_init_f(ulong dummy)
{
icache_enable();
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f();
@ -101,6 +106,9 @@ void board_init_f(ulong dummy)
gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
qspi_ahb_init();
#endif
}
#ifdef CONFIG_SPL_OS_BOOT

4
arch/arm/dts/fsl-ls1012a-2g5rdb.dts
View File

@ -40,3 +40,7 @@
&duart0 {
status = "okay";
};
&sata {
status = "okay";
};

4
arch/arm/dts/fsl-ls1012a-qds.dtsi
View File

@ -125,3 +125,7 @@
status = "okay";
phy_type = "ulpi";
};
&sata {
status = "okay";
};

4
arch/arm/dts/fsl-ls1012a-rdb.dtsi
View File

@ -34,3 +34,7 @@
&duart0 {
status = "okay";
};
&sata {
status = "okay";
};

8
arch/arm/dts/fsl-ls1012a.dtsi
View File

@ -134,6 +134,14 @@
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
};
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;

35
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@ -85,39 +85,7 @@ struct cpu_type {
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_PHY2_CFG 0x28184d1f
#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
#ifndef __ASSEMBLY__
/* AHCI (sata) register map */
struct ccsr_ahci {
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
u32 pcfg; /* port config */
u32 ppcfg; /* port phy1 config */
u32 pp2c; /* port phy2 config */
u32 pp3c; /* port phy3 config */
u32 pp4c; /* port phy4 config */
u32 pp5c; /* port phy5 config */
u32 axicc; /* AXI cache control */
u32 paxic; /* port AXI config */
u32 axipc; /* AXI PROT control */
u32 ptc; /* port Trans Config */
u32 pts; /* port Trans Status */
u32 plc; /* port link config */
u32 plc1; /* port link config1 */
u32 plc2; /* port link config2 */
u32 pls; /* port link status */
u32 pls1; /* port link status1 */
u32 pcmdc; /* port CMD config */
u32 ppcs; /* port phy control status */
u32 pberr; /* port 0/1 BIST error */
u32 cmds; /* port 0/1 CMD status error */
};
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
int get_core_volt_from_fuse(void);
@ -130,6 +98,9 @@ int board_setup_core_volt(u32 vdd);
void init_pfe_scfg_dcfg_regs(void);
#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
int qspi_ahb_init(void);
#endif
void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635

26
board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg Normal file
View File

@ -0,0 +1,26 @@
#QSPI clk
0957015c 40100000
#Configure Scratch register
09570600 00000000
09570604 10000000
#Disable CCI barrier tranaction
09570178 0000e010
09180000 00000008
#USB PHY frequency sel
09570418 0000009e
0957041c 0000009e
09570420 0000009e
#Serdes SATA
09eb1300 80104e20
09eb08dc 00502880
#PEX gen3 link
09570158 00000300
89400890 01048000
89500890 01048000
89600890 01048000
#Alt base register
09570158 00001000
#flush PBI data
096100c0 000fffff
#Change endianness
09550000 000f400c

7
board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg Normal file
View File

@ -0,0 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
0c150010 0e000000 00000000 00000000
11335559 40005012 40025000 c1000000
00000000 00000000 00000000 00238800
20124000 00003101 00000096 00000001

2
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 NXP Semiconductors
* Copyright 2015 Freescale Semiconductor
* Copyright 2017 NXP
*/
#include <common.h>
#include <malloc.h>

10
common/spl/Kconfig
View File

@ -553,6 +553,16 @@ config SYS_OS_BASE
endif # SPL_OS_BOOT
config SPL_PAYLOAD
string "SPL payload"
default "tpl/u-boot-with-tpl.bin" if TPL
default "u-boot.bin"
help
Payload for SPL boot. For backward compability, default to
u-boot.bin, i.e. RAW image without any header. In case of
TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to
use u-boot.img.
config SPL_PCI_SUPPORT
bool "Support PCI drivers"
help

7
configs/ls1012a2g5rdb_qspi_defconfig
View File

@ -29,11 +29,12 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
@ -44,3 +45,7 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI=y
CONFIG_AHCI=y

1
configs/ls1012afrdm_qspi_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y

8
configs/ls1012aqds_qspi_defconfig
View File

@ -34,11 +34,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
# CONFIG_BLK is not set
CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
@ -56,3 +57,8 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y

8
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View File

@ -31,11 +31,12 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
@ -53,3 +54,8 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y

8
configs/ls1012ardb_qspi_defconfig
View File

@ -30,11 +30,12 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
@ -51,3 +52,8 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y

1
configs/ls1043ardb_sdcard_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

1
configs/ls1046aqds_qspi_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y

8
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
@ -17,6 +21,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y

9
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
@ -17,6 +21,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
@ -37,6 +45,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y

8
configs/ls1046ardb_emmc_defconfig
View File

@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
@ -17,6 +21,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

1
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

1
configs/ls1046ardb_qspi_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

65
configs/ls1046ardb_qspi_spl_defconfig Normal file
View File

@ -0,0 +1,65 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_OS_BASE=0x40980000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_GZIP=y

8
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -1,9 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
@ -16,6 +20,10 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_CMD_GPT=y

8
configs/ls1046ardb_sdcard_defconfig
View File

@ -1,8 +1,12 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
@ -16,6 +20,10 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

1
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/ls1088aqds_qspi_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/ls1088aqds_sdcard_qspi_defconfig
View File

@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/ls1088ardb_qspi_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

1
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y

1
configs/ls1088ardb_sdcard_qspi_defconfig
View File

@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y

3
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
View File

@ -27,6 +27,9 @@ CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y

3
configs/ls2088ardb_qspi_defconfig
View File

@ -31,6 +31,9 @@ CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y

87
drivers/ata/sata_ceva.c
View File

@ -7,8 +7,6 @@
#include <dm.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
/* Vendor Specific Register Offsets */
@ -18,6 +16,7 @@
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
@ -72,45 +71,57 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
struct ceva_sata_priv {
ulong base;
/* flag bit definition */
#define FLAG_COHERENT 1
/* register config value */
#define CEVA_PHY1_CFG 0xa003fffe
#define CEVA_PHY2_CFG 0x28184d1f
#define CEVA_PHY3_CFG 0x0e081509
#define CEVA_TRANS_CFG 0x08000029
#define CEVA_AXICC_CFG 0x3fffffff
/* ecc addr-val pair */
#define ECC_DIS_ADDR_CH2 0x80000000
#define ECC_DIS_VAL_CH2 0x20140520
enum ceva_soc {
CEVA_1V84,
CEVA_LS1012A,
};
static int ceva_init_sata(ulong mmio)
struct ceva_sata_priv {
ulong base;
enum ceva_soc soc;
ulong flag;
};
static int ceva_init_sata(struct ceva_sata_priv *priv)
{
ulong base = priv->base;
ulong tmp;
int i;
/*
* AXI Data bus width to 64
* Set Mem Addr Read, Write ID for data transfers
* Transfer limit to 72 DWord
*/
tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
writel(tmp, mmio + AHCI_VEND_PAXIC);
/* Set AHCI Enable */
tmp = readl(mmio + HOST_CTL);
tmp |= HOST_AHCI_EN;
writel(tmp, mmio + HOST_CTL);
for (i = 0; i < NR_PORTS; i++) {
/* TPSS TPRS scalars, CISE and Port Addr */
tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
writel(tmp, mmio + AHCI_VEND_PCFG);
/* Port Phy Cfg register enables */
switch (priv->soc) {
case CEVA_1V84:
tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
writel(tmp, base + AHCI_VEND_PAXIC);
tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
writel(tmp, base + AHCI_VEND_PCFG);
tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
writel(tmp, mmio + AHCI_VEND_PPCFG);
/* Rx Watermark setting */
writel(tmp, base + AHCI_VEND_PPCFG);
tmp = PTC_RX_WM_VAL | PTC_RSVD;
writel(tmp, mmio + AHCI_VEND_PTC);
writel(tmp, base + AHCI_VEND_PTC);
break;
/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
case CEVA_LS1012A:
writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
if (priv->flag & FLAG_COHERENT)
writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
break;
}
return 0;
}
@ -125,13 +136,14 @@ static int sata_ceva_probe(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
ceva_init_sata(priv->base);
ceva_init_sata(priv);
return ahci_probe_scsi(dev, priv->base);
}
static const struct udevice_id sata_ceva_ids[] = {
{ .compatible = "ceva,ahci-1v84" },
{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ }
};
@ -139,10 +151,15 @@ static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
priv->base = devfdt_get_addr(dev);
if (dev_read_bool(dev, "dma-coherent"))
priv->flag |= FLAG_COHERENT;
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->soc = dev_get_driver_data(dev);
return 0;
}

14
drivers/ddr/fsl/options.c
View File

@ -742,8 +742,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
unsigned int ctrl_num)
{
unsigned int i;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
char buf[HWCONFIG_BUFFER_SIZE];
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
defined(CONFIG_SYS_FSL_DDR4)
@ -757,8 +756,8 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
buf[0] = '\0';
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
@ -1398,15 +1397,14 @@ int fsl_use_spd(void)
int use_spd = 0;
#ifdef CONFIG_DDR_SPD
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
char buf[HWCONFIG_BUFFER_SIZE];
/*
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
buf[0] = '\0';
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {

1
include/configs/B4860QDS.h
View File

@ -17,7 +17,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T102xQDS.h
View File

@ -29,7 +29,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T102xRDB.h
View File

@ -32,7 +32,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T104xRDB.h
View File

@ -21,7 +21,6 @@
#endif
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T208xQDS.h
View File

@ -36,7 +36,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T208xRDB.h
View File

@ -30,7 +30,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T4240QDS.h
View File

@ -21,7 +21,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

1
include/configs/T4240RDB.h
View File

@ -21,7 +21,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000

2
include/configs/ls1043a_common.h
View File

@ -60,7 +60,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x17000
@ -90,7 +89,6 @@
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000

32
include/configs/ls1046a_common.h
View File

@ -16,10 +16,12 @@
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#if defined(CONFIG_SPL_BUILD) && \
(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
#if defined(CONFIG_SPL_BUILD) && \
!defined(CONFIG_SPL_FSL_LS_PPA)
#define SPL_NO_IFC
#endif
@ -58,16 +60,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
#define CONFIG_SPL_STACK 0x10020000
@ -92,10 +84,24 @@
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif
#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1f000
#define CONFIG_SPL_STACK 0x10020000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SYS_MONITOR_LEN 0x100000
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#endif
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT

12
include/configs/ls1046ardb.h
View File

@ -31,17 +31,21 @@
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#endif
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
#define CONFIG_SYS_FSL_PBL_PBI \
board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
#define CONFIG_SYS_UBOOT_BASE 0x40100000
#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
#ifndef SPL_NO_IFC

11
include/configs/ls1088a_common.h
View File

@ -195,17 +195,17 @@ unsigned long long get_qixis_addr(void);
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
"sf read 0x80200000 0xd00000 0x100000;"\
" fsl_mc apply dpl 0x80200000 &&" \
"sf read 0x80001000 0xd00000 0x100000;"\
" fsl_mc lazyapply dpl 0x80001000 &&" \
" sf read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
" fsl_mc apply dpl 0x80200000 &&" \
#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
" fsl_mc lazyapply dpl 0x80001000 &&" \
" mmc read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#else /* NOR BOOT*/
#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
@ -224,7 +224,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000

14
include/configs/ls1088ardb.h
View File

@ -381,8 +381,8 @@
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"env exists mcinitcmd && run mcinitcmd && " \
"mmc read 0x80200000 0x6800 0x800;" \
"fsl_mc apply dpl 0x80200000;" \
"mmc read 0x80001000 0x6800 0x800;" \
"fsl_mc lazyapply dpl 0x80001000;" \
"bootm $load_addr#ls1088ardb\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
@ -402,11 +402,11 @@
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
"sf read 0x80200000 0xd00000 0x100000;" \
"sf read 0x80001000 0xd00000 0x100000;" \
"env exists mcinitcmd && env exists secureboot " \
" && sf read 0x80780000 0x780000 0x100000 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
"&& fsl_mc apply dpl 0x80200000;" \
"&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run qspi_bootcmd;" \
"env exists secureboot && esbc_halt;"
@ -414,11 +414,11 @@
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
"mmc read 0x80200000 0x6800 0x800; " \
"mmc read 0x80001000 0x6800 0x800; " \
"env exists mcinitcmd && env exists secureboot " \
" && mmc read 0x80780000 0x3800 0x10 " \
" && mmc read 0x80780000 0x3C00 0x10 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
"&& fsl_mc apply dpl 0x80200000;" \
"&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#endif

1
include/configs/ls2080a_common.h
View File

@ -206,7 +206,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#ifdef CONFIG_NAND_BOOT

4
include/configs/ls2080ardb.h
View File

@ -281,13 +281,9 @@ unsigned long get_board_sys_clk(void);
/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#endif
#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
#define FSL_QSPI_FLASH_NUM 2
#endif