Adding DIU support for Freescale 5121ADS
Add DIU and cfb console support to FSL 5121ADS board. Use #define CONFIG_VIDEO in config file to enable fb console. Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
Wolfgang Denk
parent
a48ff68d23
commit
0e1bad47cd
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS-y := $(BOARD).o ads5121_diu.o ../freescale/common/fsl_diu_fb.o ../freescale/common/fsl_logo_bmp.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS := $(COBJS-y)
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@ -39,17 +39,35 @@
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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#define MPC5121_IOCTL_PSC6_0 (0x284/4)
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#define MPC5121_IO_DIU_START (0x288/4)
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#define MPC5121_IO_DIU_END (0x2fc/4)
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/* Functional pin muxing */
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#define MPC5121_IO_FUNC1 (0 << 7)
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#define MPC5121_IO_FUNC2 (1 << 7)
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#define MPC5121_IO_FUNC3 (2 << 7)
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#define MPC5121_IO_FUNC4 (3 << 7)
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#define MPC5121_IO_ST (1 << 2)
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#define MPC5121_IO_DS_1 (0)
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#define MPC5121_IO_DS_2 (1)
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#define MPC5121_IO_DS_3 (2)
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#define MPC5121_IO_DS_4 (3)
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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u32 lpcaw;
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u32 lpcaw, tmp32;
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volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
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int i;
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/*
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* Initialize Local Window for the CPLD registers access (CS2 selects
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@ -81,6 +99,16 @@ int board_early_init_f (void)
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im->clk.sccr[0] = SCCR1_CLOCKS_EN;
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im->clk.sccr[1] = SCCR2_CLOCKS_EN;
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/* Configure DIU clock pin */
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tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
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tmp32 &= ~0x1ff;
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tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
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ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
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/* Initialize IO pins (pin mux) for DIU function */
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for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
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ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
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return 0;
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}
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@ -186,6 +214,38 @@ long int fixed_sdram (void)
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return msize;
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}
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int misc_init_r(void)
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{
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u8 tmp_val;
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/* Using this for DIU init before the driver in linux takes over
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* Enable the TFP410 Encoder (I2C address 0x38)
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*/
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i2c_set_bus_num(2);
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tmp_val = 0xBF;
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i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
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tmp_val = 0x10;
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i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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/* Verify if enabled */
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tmp_val = 0;
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i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
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debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
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#ifdef CONFIG_FSL_DIU_FB
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#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
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ads5121_diu_init();
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#endif
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#endif
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return 0;
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}
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int checkboard (void)
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{
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ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
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165
board/ads5121/ads5121_diu.c
Normal file
165
board/ads5121/ads5121_diu.c
Normal file
@ -0,0 +1,165 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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* York Sun <yorksun@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#ifdef CONFIG_FSL_DIU_FB
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#include "../freescale/common/pixis.h"
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#include "../freescale/common/fsl_diu_fb.h"
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#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
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#include <devices.h>
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#include <video_fb.h>
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#endif
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extern unsigned int FSL_Logo_BMP[];
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static int xres, yres;
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile clk512x_t *clk = &immap->clk;
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volatile unsigned int *clkdvdr = &clk->scfr[0];
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unsigned long speed_ccb, temp, pixval;
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speed_ccb = get_bus_freq(0) * 4;
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temp = 1000000000/pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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debug("DIU pixval = %lu\n", pixval);
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/* Modify PXCLK in GUTS CLKDVDR */
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debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
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temp = *clkdvdr & 0xFFFFFF00;
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*clkdvdr = temp | (pixval & 0x1F);
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
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}
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int ads5121_diu_init(void)
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{
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unsigned int pixel_format;
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xres = 1024;
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yres = 768;
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pixel_format = 0x88883316;
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return fsl_diu_init(xres, pixel_format, 0,
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(unsigned char *)FSL_Logo_BMP);
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}
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int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
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int flag, int argc, char *argv[])
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{
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unsigned int addr;
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if (argc < 2) {
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printf("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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if (!strncmp(argv[1], "init", 4)) {
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#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
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fsl_diu_clear_screen();
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drv_video_init();
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#else
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return ads5121_diu_init();
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#endif
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} else {
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addr = simple_strtoul(argv[1], NULL, 16);
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fsl_diu_clear_screen();
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fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
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}
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return 0;
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}
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U_BOOT_CMD(
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diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
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"diufb init | addr - Init or Display BMP file\n",
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"init\n - initialize DIU\n"
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"addr\n - display bmp at address 'addr'\n"
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);
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#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
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/*
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* The Graphic Device
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*/
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GraphicDevice ctfb;
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void *video_hw_init(void)
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{
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GraphicDevice *pGD = (GraphicDevice *) &ctfb;
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struct fb_info *info;
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if (ads5121_diu_init() < 0)
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return;
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/* fill in Graphic device struct */
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sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
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xres, yres, 32, 64, 60);
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pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
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pGD->winSizeX = xres;
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pGD->winSizeY = yres - info->logo_height;
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pGD->plnSizeX = pGD->winSizeX;
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pGD->plnSizeY = pGD->winSizeY;
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pGD->gdfBytesPP = 4;
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pGD->gdfIndex = GDF_32BIT_X888RGB;
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pGD->isaBase = 0;
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pGD->pciBase = 0;
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pGD->memSize = info->screen_size - info->logo_size;
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/* Cursor Start Address */
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pGD->dprBase = 0;
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pGD->vprBase = 0;
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pGD->cprBase = 0;
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return (void *)pGD;
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}
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/**
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* Set the LUT
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*
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* @index: color number
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* @r: red
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* @b: blue
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* @g: green
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*/
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void video_set_lut
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(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
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{
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return;
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}
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#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
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#endif /* CONFIG_FSL_DIU_FB */
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@ -45,14 +45,25 @@
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC512X 1 /* MPC512X family */
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#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
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/* video */
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#undef CONFIG_VIDEO
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#if defined(CONFIG_VIDEO)
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#endif
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/* CONFIG_PCI is defined at config time */
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#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CFG_IMMR 0x80000000
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#define CFG_DIU_ADDR (CFG_IMMR+0x2100)
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#define CFG_MEMTEST_START 0x00200000 /* memtest region */
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#define CFG_MEMTEST_END 0x00400000
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@ -127,28 +138,28 @@
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#define CFG_MICRON_OCD_DEFAULT 0x01010780
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/* DDR Priority Manager Configuration */
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#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
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#define CFG_MDDRCGRP_PM_CFG2 0x00000055
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#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
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#define CFG_MDDRCGRP_LUT0_MU 0x11111117
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#define CFG_MDDRCGRP_LUT0_ML 0x7777777A
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#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
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#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
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#define CFG_MDDRCGRP_LUT2_MU 0x44444444
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#define CFG_MDDRCGRP_PM_CFG1 0x00077777
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#define CFG_MDDRCGRP_PM_CFG2 0x00000000
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#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
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#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC
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#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA
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#define CFG_MDDRCGRP_LUT1_MU 0x66666666
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#define CFG_MDDRCGRP_LUT1_ML 0x55555555
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#define CFG_MDDRCGRP_LUT2_MU 0x44444444
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#define CFG_MDDRCGRP_LUT2_ML 0x44444444
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#define CFG_MDDRCGRP_LUT3_MU 0x55555555
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#define CFG_MDDRCGRP_LUT3_MU 0x55555555
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#define CFG_MDDRCGRP_LUT3_ML 0x55555558
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#define CFG_MDDRCGRP_LUT4_MU 0x11111111
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#define CFG_MDDRCGRP_LUT4_ML 0x1111117C
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#define CFG_MDDRCGRP_LUT0_AU 0x33333377
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#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
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#define CFG_MDDRCGRP_LUT1_AU 0x11111111
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#define CFG_MDDRCGRP_LUT1_AL 0x11111111
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#define CFG_MDDRCGRP_LUT2_AU 0x11111111
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#define CFG_MDDRCGRP_LUT4_MU 0x11111111
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#define CFG_MDDRCGRP_LUT4_ML 0x11111122
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#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa
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#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa
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#define CFG_MDDRCGRP_LUT1_AU 0x66666666
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#define CFG_MDDRCGRP_LUT1_AL 0x66666666
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#define CFG_MDDRCGRP_LUT2_AU 0x11111111
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#define CFG_MDDRCGRP_LUT2_AL 0x11111111
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#define CFG_MDDRCGRP_LUT3_AU 0x11111111
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#define CFG_MDDRCGRP_LUT3_AU 0x11111111
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#define CFG_MDDRCGRP_LUT3_AL 0x11111111
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#define CFG_MDDRCGRP_LUT4_AU 0x11111111
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#define CFG_MDDRCGRP_LUT4_AU 0x11111111
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#define CFG_MDDRCGRP_LUT4_AL 0x11111111
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/*
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@ -189,7 +200,11 @@
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#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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#ifdef CONFIG_FSL_DIU_FB
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#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
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#else
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#define CFG_MALLOC_LEN (512 * 1024)
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#endif
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/*
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* Serial Port
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