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cpu/mpc8xx/interrupts.c
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354
cpu/mpc8xx/interrupts.c
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <mpc8xx.h>
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#include <mpc8xx_irq.h>
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#include <asm/processor.h>
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#include <commproc.h>
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/****************************************************************************/
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unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
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/****************************************************************************/
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/*
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* CPM interrupt vector functions.
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*/
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struct cpm_action {
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interrupt_handler_t *handler;
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void *arg;
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};
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static struct cpm_action cpm_vecs[CPMVEC_NR];
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static void cpm_interrupt_init (void);
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static void cpm_interrupt(int irq, struct pt_regs * regs);
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/****************************************************************************/
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static __inline__ unsigned long get_msr(void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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}
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static __inline__ void set_msr(unsigned long msr)
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{
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asm volatile("mtmsr %0" : : "r" (msr));
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}
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static __inline__ unsigned long get_dec(void)
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{
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unsigned long val;
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asm volatile("mfdec %0" : "=r" (val) :);
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return val;
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}
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static __inline__ void set_dec(unsigned long val)
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{
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asm volatile("mtdec %0" : : "r" (val));
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}
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void enable_interrupts (void)
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{
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set_msr (get_msr() | MSR_EE);
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}
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/* returns flag if MSR_EE was set before */
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int disable_interrupts (void)
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{
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ulong msr = get_msr();
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set_msr (msr & ~MSR_EE);
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return ((msr & MSR_EE) != 0);
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}
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/****************************************************************************/
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int interrupt_init(void)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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decrementer_count = get_tbclk() / CFG_HZ;
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cpm_interrupt_init();
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/* disable all interrupts except for the CPM interrupt */
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immr->im_siu_conf.sc_simask = 1 << (31-CPM_INTERRUPT);
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set_dec (decrementer_count);
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set_msr (get_msr() | MSR_EE);
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return (0);
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}
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/****************************************************************************/
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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int irq;
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ulong simask, newmask;
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ulong vec, v_bit;
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/*
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* read the SIVEC register and shift the bits down
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* to get the irq number
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*/
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vec = immr->im_siu_conf.sc_sivec;
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irq = vec >> 26;
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v_bit = 0x80000000UL >> irq;
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/*
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* Read Interrupt Mask Register and Mask Interrupts
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*/
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simask = immr->im_siu_conf.sc_simask;
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newmask = simask & (~(0xFFFF0000 >> irq));
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immr->im_siu_conf.sc_simask = newmask;
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if (!(irq & 0x1)) { /* External Interrupt ? */
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ulong siel;
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/*
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* Read Interrupt Edge/Level Register
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*/
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siel = immr->im_siu_conf.sc_siel;
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if (siel & v_bit) { /* edge triggered interrupt ? */
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/*
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* Rewrite SIPEND Register to clear interrupt
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*/
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immr->im_siu_conf.sc_sipend = v_bit;
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}
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}
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switch (irq) {
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case CPM_INTERRUPT:
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cpm_interrupt (irq, regs);
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break;
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default:
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printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
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irq, vec);
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/* turn off the bogus interrupt to avoid it from now */
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simask &= ~v_bit;
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break;
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}
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/*
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* Re-Enable old Interrupt Mask
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*/
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immr->im_siu_conf.sc_simask = simask;
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}
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/****************************************************************************/
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/*
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* CPM interrupt handler
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*/
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static void
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cpm_interrupt(int irq, struct pt_regs * regs)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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uint vec;
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/*
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* Get the vector by setting the ACK bit
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* and then reading the register.
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*/
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immr->im_cpic.cpic_civr = 1;
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vec = immr->im_cpic.cpic_civr;
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vec >>= 11;
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if (cpm_vecs[vec].handler != NULL) {
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(*cpm_vecs[vec].handler)(cpm_vecs[vec].arg);
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} else {
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immr->im_cpic.cpic_cimr &= ~(1 << vec);
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printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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immr->im_cpic.cpic_cisr |= (1 << vec);
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}
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/*
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* The CPM can generate the error interrupt when there is a race
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* condition between generating and masking interrupts. All we have
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* to do is ACK it and return. This is a no-op function so we don't
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* need any special tests in the interrupt handler.
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*/
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static void
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cpm_error_interrupt (void *dummy)
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{
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}
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/****************************************************************************/
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/*
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* Install and free a CPM interrupt handler.
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*/
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void
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irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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if (cpm_vecs[vec].handler != NULL) {
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printf ("CPM interrupt 0x%x replacing 0x%x\n",
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(uint)handler, (uint)cpm_vecs[vec].handler);
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}
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cpm_vecs[vec].handler = handler;
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cpm_vecs[vec].arg = arg;
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immr->im_cpic.cpic_cimr |= (1 << vec);
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#if 0
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printf ("Install CPM interrupt for vector %d ==> %p\n", vec, handler);
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#endif
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}
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void
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irq_free_handler(int vec)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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#if 0
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printf ("Free CPM interrupt for vector %d ==> %p\n",
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vec, cpm_vecs[vec].handler);
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#endif
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immr->im_cpic.cpic_cimr &= ~(1 << vec);
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cpm_vecs[vec].handler = NULL;
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cpm_vecs[vec].arg = NULL;
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}
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/****************************************************************************/
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static void
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cpm_interrupt_init (void)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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/*
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* Initialize the CPM interrupt controller.
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*/
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immr->im_cpic.cpic_cicr =
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( CICR_SCD_SCC4 |
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CICR_SCC_SCC3 |
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CICR_SCB_SCC2 |
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CICR_SCA_SCC1 ) | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
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immr->im_cpic.cpic_cimr = 0;
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/*
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* Install the error handler.
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*/
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irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
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immr->im_cpic.cpic_cicr |= CICR_IEN;
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}
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/****************************************************************************/
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volatile ulong timestamp = 0;
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/*
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* timer_interrupt - gets called when the decrementer overflows,
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* with interrupts disabled.
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* Trivial implementation - no need to be really accurate.
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*/
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void timer_interrupt(struct pt_regs *regs)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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#ifdef CONFIG_STATUS_LED
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extern void status_led_tick (ulong);
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#endif
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#if 0
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printf ("*** Timer Interrupt *** ");
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#endif
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/* Reset Timer Expired and Timers Interrupt Status */
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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__asm__("nop");
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immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
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/* Restore Decrementer Count */
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set_dec (decrementer_count);
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timestamp++;
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#ifdef CONFIG_STATUS_LED
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status_led_tick (timestamp);
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#endif /* CONFIG_STATUS_LED */
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#if defined(CONFIG_WATCHDOG) || defined(CFG_CMA_LCD_HEARTBEAT)
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/*
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* The shortest watchdog period of all boards (except LWMON)
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* is approx. 1 sec, thus re-trigger watchdog at least
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* every 500 ms = CFG_HZ / 2
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*/
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#ifndef CONFIG_LWMON
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if ((timestamp % (CFG_HZ / 2)) == 0) {
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#else
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if ((timestamp % (CFG_HZ / 20)) == 0) {
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#endif
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#if defined(CFG_CMA_LCD_HEARTBEAT)
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extern void lcd_heartbeat(void);
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lcd_heartbeat();
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#endif /* CFG_CMA_LCD_HEARTBEAT */
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#if defined(CONFIG_WATCHDOG)
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reset_8xx_watchdog(immr);
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#endif /* CONFIG_WATCHDOG */
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}
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#endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
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}
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/****************************************************************************/
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void reset_timer (void)
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{
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timestamp = 0;
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}
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ulong get_timer (ulong base)
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{
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return (timestamp - base);
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}
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void set_timer (ulong t)
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{
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timestamp = t;
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}
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/****************************************************************************/
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