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x86: acpi: Create a common irqlinks ASL file

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Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2016-05-25 19:19:06 -07:00
parent 6523dbf7cc
commit 0d71511a2a
2 changed files with 35 additions and 21 deletions
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33
arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl → arch/x86/include/asm/acpi/irqlinks.asl
View File

@ -7,26 +7,19 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
Scope (\) /*
{ * Intel chipset PIRQ routing control ASL description
/* Intel Legacy Block */ *
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) * The programming interface is common to most Intel chipsets. But the PRTx
Field(ILBS, AnyAcc, NoLock, Preserve) { * registers may be mapped to different blocks. Some chipsets map them to LPC
Offset (0x8), * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
PRTA, 8, * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
PRTB, 8, * Block (ILB) memory space.
PRTC, 8, *
PRTD, 8, * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
PRTE, 8, * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
PRTF, 8, * defined somewhere else in the platform's ASL files.
PRTG, 8, */
PRTH, 8,
Offset (0x88),
, 3,
UI3E, 1,
UI4E, 1
}
}
Device (LNKA) Device (LNKA)
{ {

23
arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
View File

@ -10,6 +10,27 @@
/* Intel LPC Bus Device - 0:1f.0 */ /* Intel LPC Bus Device - 0:1f.0 */
Scope (\)
{
/* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field(ILBS, AnyAcc, NoLock, Preserve) {
Offset (0x8),
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x88),
, 3,
UI3E, 1,
UI4E, 1
}
}
Device (LPCB) Device (LPCB)
{ {
Name(_ADR, 0x001f0000) Name(_ADR, 0x001f0000)
@ -23,7 +44,7 @@ Device (LPCB)
Offset(0x84) Offset(0x84)
} }
#include "irqlinks.asl" #include <asm/acpi/irqlinks.asl>
/* Firmware Hub */ /* Firmware Hub */
Device (FWH) Device (FWH)