Added 64-bit MMIO accessors for ARMv8
This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
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@ -70,10 +70,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_getq(a) (*(volatile unsigned long long *)(a))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
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extern inline void __raw_writesb(unsigned long addr, const void *data,
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extern inline void __raw_writesb(unsigned long addr, const void *data,
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int bytelen)
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int bytelen)
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@ -123,10 +125,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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#define __raw_writeb(v,a) __arch_putb(v,a)
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#define __raw_writeb(v,a) __arch_putb(v,a)
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#define __raw_writew(v,a) __arch_putw(v,a)
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#define __raw_writew(v,a) __arch_putw(v,a)
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#define __raw_writel(v,a) __arch_putl(v,a)
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#define __raw_writel(v,a) __arch_putl(v,a)
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#define __raw_writeq(v,a) __arch_putq(v,a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readq(a) __arch_getq(a)
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/*
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/*
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* TODO: The kernel offers some more advanced versions of barriers, it might
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* TODO: The kernel offers some more advanced versions of barriers, it might
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@ -139,10 +143,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
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#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
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#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
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#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
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#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
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#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
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#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
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#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
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#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
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/*
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/*
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* The compiler seems to be incapable of optimising constants
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* The compiler seems to be incapable of optimising constants
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@ -168,9 +174,11 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
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#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
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#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
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#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
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#define out_le64(a,v) out_arch(q,le64,a,v)
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#define out_le32(a,v) out_arch(l,le32,a,v)
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#define out_le32(a,v) out_arch(l,le32,a,v)
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#define out_le16(a,v) out_arch(w,le16,a,v)
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#define out_le16(a,v) out_arch(w,le16,a,v)
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#define in_le64(a) in_arch(q,le64,a)
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#define in_le32(a) in_arch(l,le32,a)
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#define in_le32(a) in_arch(l,le32,a)
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#define in_le16(a) in_arch(w,le16,a)
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#define in_le16(a) in_arch(w,le16,a)
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