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armv8: Add workaround for USB erratum A-050106

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USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Ran Wang 2019-11-26 11:40:40 +08:00 committed by Priyanka Jain
parent 055aa33ff9
commit 0cfa00cdb9
3 changed files with 26 additions and 1 deletions
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9
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
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@ -219,6 +219,7 @@ config ARCH_LX2160A
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1 select SYS_FSL_EC1
select SYS_FSL_EC2 select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508 select SYS_FSL_HAS_CCN508
@ -348,6 +349,14 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798" bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A050106
bool "Workaround for USB PHY erratum A050106"
help
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.
config SYS_FSL_ERRATUM_A010315 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315" bool "Workaround for PCIe erratum A010315"

12
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -147,7 +147,7 @@ static void erratum_a008997(void)
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A) defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@ -181,6 +181,15 @@ static void erratum_a009007(void)
} }
#if defined(CONFIG_FSL_LSCH3) #if defined(CONFIG_FSL_LSCH3)
static void erratum_a050106(void)
{
#if defined(CONFIG_ARCH_LX2160A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
#endif
}
/* /*
* This erratum requires setting a value to eddrtqcr1 to * This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance. * optimal the DDR performance.
@ -332,6 +341,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009798(); erratum_a009798();
erratum_a008997(); erratum_a008997();
erratum_a009007(); erratum_a009007();
erratum_a050106();
#ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU /* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions. * to allow only Secure transactions.

6
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -252,8 +252,14 @@
#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
#define USB_PHY_RX_EQ_VAL_1 0x0000 #define USB_PHY_RX_EQ_VAL_1 0x0000
#define USB_PHY_RX_EQ_VAL_2 0x0080 #define USB_PHY_RX_EQ_VAL_2 0x0080
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
#define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_3 0x0380
#define USB_PHY_RX_EQ_VAL_4 0x0b80 #define USB_PHY_RX_EQ_VAL_4 0x0b80
#elif defined(CONFIG_ARCH_LX2160A)
#define USB_PHY_RX_EQ_VAL_3 0x0080
#define USB_PHY_RX_EQ_VAL_4 0x0880
#endif
#define DCSR_USB_IOCR1 0x108004 #define DCSR_USB_IOCR1 0x108004
#define DCSR_USB_PCSTXSWINGFULL 0x71 #define DCSR_USB_PCSTXSWINGFULL 0x71