From 0c85c113c41c1393e10939629aabfb26279c4294 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:28 +0100 Subject: [PATCH 1/7] riscv: clarify error message on undefined exceptions Undefined exceptions are treated as reserved. This is not clearly communicated to the user. Adjust the error message to clarify that a reserved exception has occurred and add additional details. Fixes: e8b522b ("riscv: treat undefined exception codes as reserved") Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/lib/interrupts.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e185933b01..74c1e561c7 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -37,7 +37,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) printf("exception code: %ld , %s , epc %lx , ra %lx\n", code, exception_code[code], epc, regs->ra); } else { - printf("Reserved\n"); + printf("reserved exception code: %ld , epc %lx , ra %lx\n", + code, epc, regs->ra); } hang(); From c9056653ecd6dfedc5e9f00548f9f1c604a3a193 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:29 +0100 Subject: [PATCH 2/7] riscv: move the AX25-specific implementation of flush_dcache_all The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/cache.c | 22 ++++++++++++++++++++++ arch/riscv/lib/cache.c | 10 ++++------ 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae170b8..228fc55f56 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@ #include +void flush_dcache_all(void) +{ + /* + * Andes' AX25 does not have a coherence agent. U-Boot must use data + * cache flush and invalidate functions to keep data in the system + * coherent. + * The implementation of the fence instruction in the AX25 flushes the + * data cache and is used for this purpose. + */ + asm volatile ("fence" ::: "memory"); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..78b19da2c5 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) From f74c416e622cec35be95066fb7fcf4c27ac146e9 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:30 +0100 Subject: [PATCH 3/7] riscv: use invalidate/flush_*cache_range functions in cache.c The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/lib/cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 78b19da2c5..5437a122a1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -40,8 +40,8 @@ void cache_flush(void) void flush_cache(unsigned long addr, unsigned long size) { - invalidate_icache_all(); - flush_dcache_all(); + invalidate_icache_range(addr, addr + size); + flush_dcache_range(addr, addr + size); } __weak void icache_enable(void) From 3c37278ff18577b711b14a1c2fcec37daa959f0a Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:31 +0100 Subject: [PATCH 4/7] riscv: remove RISC-V standalone linker script Standalone applications do not require a separate linker script and can use the default linker script of the compiler instead. Remove the RISC-V standalone linker script. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/config.mk | 1 - examples/standalone/riscv.lds | 40 ----------------------------------- 2 files changed, 41 deletions(-) delete mode 100644 examples/standalone/riscv.lds diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index ff4fe64001..e484a3f0ef 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -24,7 +24,6 @@ EFI_LDS := elf_riscv64_efi.lds endif CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 -LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/riscv.lds PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds deleted file mode 100644 index 9a25861052..0000000000 --- a/examples/standalone/riscv.lds +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -OUTPUT_ARCH(riscv) -ENTRY(_start) -SECTIONS -{ - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .data : { - __global_pointer$ = . + 0x800; - *(.data) - } - - . = ALIGN(4); - - .got : { - __got_start = .; - *(.got) - __got_end = .; - } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - __bss_end = .; - - . = ALIGN(4); - .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } - - _end = .; -} From cbb860f2c89c05c4c1d571f61bb76650db489d7d Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:32 +0100 Subject: [PATCH 5/7] riscv: replace use of callee-saved register in standalone Register x19 (s3) is a callee-saved register. It must not be used to load and jump to exported functions without saving it beforehand. Replace it with t0, a temporary and caller-saved register. Change the code comment to reflect this and fix it to correctly list gp as the register with the pointer to global data. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- examples/standalone/stubs.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index fadde669fa..f37d209da6 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -174,16 +174,16 @@ gd_t *global_data; : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16"); #elif defined(CONFIG_RISCV) /* - * t7 holds the pointer to the global_data. gp is call clobbered. + * gp holds the pointer to the global_data. t0 is call clobbered. */ #define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ -" lw x19, %0(gp)\n" \ -" lw x19, %1(x19)\n" \ -" jr x19\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x19"); +" lw t0, %0(gp)\n" \ +" lw t0, %1(t0)\n" \ +" jr t0\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0"); #elif defined(CONFIG_ARC) /* * r25 holds the pointer to the global_data. r10 is call clobbered. From 7eb792970e3af4aa0c99a972411f239b0fc03a63 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:33 +0100 Subject: [PATCH 6/7] riscv: support standalone applications on RV64I systems Add an implementation of EXPORT_FUNC() for RV64I systems to support them in standalone applications. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- examples/standalone/stubs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index f37d209da6..0827bde35e 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -176,6 +176,16 @@ gd_t *global_data; /* * gp holds the pointer to the global_data. t0 is call clobbered. */ +#ifdef CONFIG_ARCH_RV64I +#define EXPORT_FUNC(f, a, x, ...) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" ld t0, %0(gp)\n" \ +" ld t0, %1(t0)\n" \ +" jr t0\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0"); +#else #define EXPORT_FUNC(f, a, x, ...) \ asm volatile ( \ " .globl " #x "\n" \ @@ -184,6 +194,7 @@ gd_t *global_data; " lw t0, %1(t0)\n" \ " jr t0\n" \ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0"); +#endif #elif defined(CONFIG_ARC) /* * r25 holds the pointer to the global_data. r10 is call clobbered. From 91882c472d8c0aef4db699d3f2de55bf43d4ae4b Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Fri, 4 Jan 2019 01:37:34 +0100 Subject: [PATCH 7/7] riscv: qemu: define standalone load address We need to define the standalone load address to use standalone application on qemu-riscv. Define it and set it equal to CONFIG_SYS_LOAD_ADDR. To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR in arch/riscv/config.mk to a conditional one. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/config.mk | 2 +- include/configs/qemu-riscv.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index e484a3f0ef..84654eb3ed 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,7 +23,7 @@ PLATFORM_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index b29d155d09..2588c5a0b2 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -17,6 +17,8 @@ #define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + /* Environment options */ #define CONFIG_ENV_SIZE SZ_4K