diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 4cf2ba0e3b..b9dda4c7ae 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -120,41 +120,6 @@ int arch_cpu_init_dm(void)
 	return 0;
 }
 
-static int enable_smbus(void)
-{
-	pci_dev_t dev;
-	uint16_t value;
-
-	/* Set the SMBus device statically. */
-	dev = PCI_BDF(0x0, 0x1f, 0x3);
-
-	/* Check to make sure we've got the right device. */
-	value = x86_pci_read_config16(dev, 0x0);
-	if (value != 0x8086) {
-		printf("SMBus controller not found\n");
-		return -ENOSYS;
-	}
-
-	/* Set SMBus I/O base. */
-	x86_pci_write_config32(dev, SMB_BASE,
-			       SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-
-	/* Set SMBus enable. */
-	x86_pci_write_config8(dev, HOSTC, HST_EN);
-
-	/* Set SMBus I/O space enable. */
-	x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
-	/* Disable interrupt generation. */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* Clear any lingering errors, so transactions can run. */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	debug("SMBus controller enabled\n");
-
-	return 0;
-}
-
 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
 #define PCH_XHCI_TEMP_BAR0  0xe8001000
@@ -271,9 +236,11 @@ int print_cpuinfo(void)
 	post_code(POST_EARLY_INIT);
 
 	/* Enable SPD ROMs and DDR-III DRAM */
-	ret = enable_smbus();
+	ret = uclass_first_device(UCLASS_I2C, &dev);
 	if (ret)
 		return ret;
+	if (!dev)
+		return -ENODEV;
 
 	/* Prepare USB controller early in S3 resume */
 	if (boot_mode == PEI_BOOT_RESUME)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 18305a33e5..54f2043172 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -283,6 +283,12 @@
 			intel,sata-port-map = <1>;
 			intel,sata-port0-gen3-tx = <0x00880a7f>;
 		};
+
+		smbus: smbus@1f,3 {
+			compatible = "intel,ich-i2c";
+			reg = <0x0000fb00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+		};
 	};
 
 	tpm {
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 0aee2e52b2..81189f3610 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,5 +1,6 @@
 CONFIG_X86=y
 CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_DM_I2C=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
@@ -20,6 +21,7 @@ CONFIG_CMD_TPM=y
 CONFIG_CMD_TPM_TEST=y
 CONFIG_OF_CONTROL=y
 CONFIG_CPU=y
+CONFIG_SYS_I2C_INTEL=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
index 1082d1a3ed..3d777ff23e 100644
--- a/drivers/i2c/intel_i2c.c
+++ b/drivers/i2c/intel_i2c.c
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <i2c.h>
 #include <asm/io.h>
+#include <asm/arch/pch.h>
 
 int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 {
@@ -27,6 +28,29 @@ int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 
 static int intel_i2c_probe(struct udevice *dev)
 {
+	/*
+	 * So far this is just setup code for ivybridge SMbus. When we have
+	 * a full I2C driver this may need to be moved, generalised or made
+	 * dependant on a particular compatible string.
+	 *
+	 * Set SMBus I/O base
+	 */
+	dm_pci_write_config32(dev, SMB_BASE,
+			      SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+	/* Set SMBus enable. */
+	dm_pci_write_config8(dev, HOSTC, HST_EN);
+
+	/* Set SMBus I/O space enable. */
+	dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+	/* Disable interrupt generation. */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* Clear any lingering errors, so transactions can run. */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+	debug("SMBus controller enabled\n");
+
 	return 0;
 }