From 05c81d98e4f3587180d26068b5925a08f3880dd2 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Mon, 14 Oct 2019 11:43:19 +0000 Subject: [PATCH 01/17] pci: layerscape: Only set EP CFG READY bit In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit of pci controller is set, so that RC can read the config space of EP. While setting the config ready bit, LTSSM_EN bit in same register was also inadvertently getting cleared. This restarts the link training between RC and EP. Update code to just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal Reviewed-by: Hou Zhiqiang Signed-off-by: Priyanka Jain --- drivers/pci/pcie_layerscape.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index db1375a1ce..5ad7c28773 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -406,7 +406,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base) static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) { - ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); + u32 config; + + config = ctrl_readl(pcie, PCIE_PF_CONFIG); + config |= PCIE_CONFIG_READY; + ctrl_writel(pcie, config, PCIE_PF_CONFIG); } static void ls_pcie_setup_ep(struct ls_pcie *pcie) From b50fe3fb7e0e3daf1ad4e1534bd7ba204f5a1699 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Fri, 18 Oct 2019 14:27:53 +1100 Subject: [PATCH 02/17] armv8: dts: ls1088a: add PSCI binding for LS1088A This allows the use of PSCI calls to trusted firmware to initiate reset and poweroff events with CONFIG_PSCI_RESET and CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target board has implemented a custom reset or poweroff procedure in EL3. Signed-off-by: Mathew McBride Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1088a.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4be1ab87d2..abc8b21a11 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -192,4 +192,9 @@ status = "disabled"; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + }; From 28f9393b1aadf61f689e80dadc74b77bf67e7fd6 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Fri, 18 Oct 2019 14:27:54 +1100 Subject: [PATCH 03/17] fsl-layerscape: do not use layerscape EFI reset if PSCI used If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by: Mathew McBride Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8fd6c751c6..1f4c0b29a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1221,7 +1221,7 @@ void __efi_runtime reset_cpu(ulong addr) #endif } -#ifdef CONFIG_EFI_LOADER +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET) void __efi_runtime EFIAPI efi_reset_system( enum efi_reset_type reset_type, From db49c1b2defbcf67ce472787fe5085ac43f19c79 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:52 +0000 Subject: [PATCH 04/17] armv8: fsl-layerscape: guard caam specific defines These macros should only be used when CONFIG_FSL_CAAM is present. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++ arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index d9d125e8ba..9462298fbf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 49e27553b1..23743ae10c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = { SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); From 5047781e993d5a17bc83a01f66937cc7816d3b31 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:53 +0000 Subject: [PATCH 05/17] fsl-layerscape: fix compile error with sec fw disabled If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Signed-off-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..3c06a55cb8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz; #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ From e33938acc93eb961e9ae2be060fb43553128c709 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:54 +0000 Subject: [PATCH 06/17] armv8: ls2088a: add icid setup for platform devices Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 35 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +- board/freescale/ls2080aqds/ls2080aqds.c | 3 ++ board/freescale/ls2080ardb/ls2080ardb.c | 3 ++ 5 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index efecbc07e7..f00ef817b1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,6 +28,7 @@ endif ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +obj-y += icid.o ls2088_ids.o endif ifneq ($(CONFIG_ARCH_LS1043A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c new file mode 100644 index 0000000000..e6403b7952 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 1f1869e8cf..c66fae43bf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif -#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ + defined(CONFIG_ARCH_LS2080A) set_icids(); #endif } diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 91c80353ed..25e80c8ac6 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "../common/qixis.h" @@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index e20267f27c..6a1b8e3f53 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -22,6 +22,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" @@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + return 0; } #endif From ab04dee542f6342d79460c2f6919c49caac89d2a Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:54 +0000 Subject: [PATCH 07/17] fsl-layerscape: add missing SATA3 and SATA4 base addresses LX2160A chips have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Signed-off-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..0e4bf331fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) From 30449aea50ea7ad9ecc416d0b9d3293a6312dbba Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:55 +0000 Subject: [PATCH 08/17] armv8: lx2160a: add icid setup for platform devices Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geanta Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + board/freescale/lx2160a/lx2160a.c | 2 + include/fsl_sec.h | 3 +- 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index f00ef817b1..e398aecd12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -24,6 +24,7 @@ endif ifneq ($(CONFIG_ARCH_LX2160A),) obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o endif ifneq ($(CONFIG_ARCH_LS2080A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c new file mode 100644 index 0000000000..3a0ed1fa55 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c66fae43bf..03a40db186 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ - defined(CONFIG_ARCH_LS2080A) + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0e4bf331fd..d46477d96e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -447,7 +447,9 @@ struct ccsr_gur { u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ u32 misc1_amqr; u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 93bdcc4caa..0b36416ad3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -108,5 +108,7 @@ #define FSL_EDMA_STREAM_ID 70 #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index b509c0312e..eff12747b4 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -27,6 +27,7 @@ #include "../common/qixis.h" #include "../common/vid.h" #include +#include #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" @@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fsl_mc_fixup_iommu_map_entry(blob); fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); return 0; } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index be08a2b88b..c0d2c7e866 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -93,8 +93,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* DECO LIODN Register, MS */ u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[8]; - u8 res4[0x40]; + } decoliodnr[16]; u32 dar; /* DECO Avail Register */ u32 drr; /* DECO Reset Register */ u8 res5[0x4d8]; From b4a59115e2cad84a47352948570c02cce34591b1 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 18 Oct 2019 09:01:56 +0000 Subject: [PATCH 09/17] armv8: ls1028a: add erratum A-050382 workaround Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. The workaround consists in programming the eDMA ICID in the eDMA_AMQR register in DCFG to 40. Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..046dcf539e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 0b36416ad3..94ea99a349 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,7 +105,22 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A-050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 #define FSL_SATA3_STREAM_ID 73 From 065ee175e050873f759d8b190c10f64cde688670 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 22 Oct 2019 01:10:57 +0200 Subject: [PATCH 10/17] armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e67321b4..bbd550b036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) uint rcw_tmp; #endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) #define HWA_CGA_M2_CLK_SEL 0x00380000 #define HWA_CGA_M2_CLK_SHIFT 19 rcw_tmp = in_le32(&gur->rcwsr[5]); @@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) sys_info->freq_cga_m2 = sys_info->freq_systembus; #endif } @@ -176,10 +176,10 @@ int get_clocks(void) #endif #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; #endif -#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) gd->arch.sdhc_clk = sys_info.freq_cga_m2; #endif #else From 762ee522e25e59696698b57519904aaf26d3dc1f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 21 Oct 2019 22:37:45 +0200 Subject: [PATCH 11/17] armv8: fsl-layerscape: introduce fsl_board_late_init() The fsl-layerscape already occupies board_late_init(), therefore it is not possible for a board to have its own board_late_init(). Introduce fsl_board_late_init() which can be implemented in the board specific code. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 03a40db186..f0df88c565 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -829,6 +829,11 @@ int fsl_setenv_mcinitcmd(void) #endif #ifdef CONFIG_BOARD_LATE_INIT +__weak int fsl_board_late_init(void) +{ + return 0; +} + int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST @@ -863,6 +868,6 @@ int board_late_init(void) qspi_ahb_init(); #endif - return 0; + return fsl_board_late_init(); } #endif From 2efb147a0a3388c7e93b87ae86bf457fcff802b0 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 26 Oct 2019 02:39:11 +0200 Subject: [PATCH 12/17] drivers: net: fsl_enetc: set phydev->node The saved ofnode is used by some PHY drivers to access the device tree node of the PHY. Signed-off-by: Michael Walle Reviewed-by: Alex Marginean Reviewed-by: Priyanka Jain --- drivers/net/fsl_enetc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index e7c5062c39..86b80c8941 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -248,6 +248,7 @@ static void enetc_start_phy(struct udevice *dev) supported = GENMASK(6, 0); /* speeds up to 1G & AN */ phy->advertising = phy->supported & supported; + phy->node = phy_node; phy_config(phy); phy_startup(phy); } From 29a6617ada631c1f86512028218491e3c15500cc Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 26 Oct 2019 02:39:12 +0200 Subject: [PATCH 13/17] drivers: net: fsl_enetc: fix RGMII configuration Add the missing RGMII PHY modes in which case the MAC has configure its RGMII settings. The only difference between these modes is the RX and TX delay configuration. A user might choose any RGMII mode in the device tree. Signed-off-by: Michael Walle Reviewed-by: Alex Marginean Reviewed-by: Priyanka Jain --- drivers/net/fsl_enetc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 86b80c8941..0ca7e838a8 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -191,6 +191,9 @@ static void enetc_start_pcs(struct udevice *dev) enetc_init_sgmii(dev); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: enetc_init_rgmii(dev); break; case PHY_INTERFACE_MODE_XGMII: From 812ff53c3e0f100aabb45eaea9b71086d00bed66 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Thu, 31 Oct 2019 05:41:09 +0000 Subject: [PATCH 14/17] fsl-layerscape: fix warning if no hwconfig is defined While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by: Pankaj Bansal Signed-off-by: Priyanka Jain Tested-by: Michael Walle --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 1f4c0b29a3..83a3319321 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -1072,6 +1072,8 @@ static void config_core_prefetch(void) if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; + else + return; prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", &arglen, buf); From 56e6f810b0ac46ddccb6237acb60ab7752a41a99 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Thu, 31 Oct 2019 14:34:40 +0800 Subject: [PATCH 15/17] configs: spi: Add the SPI_FLASH_BAR for ESPI Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry is missed by commit 6d8251783641 ("configs: Don't use SPI_FLASH_BAR as default") Signed-off-by: Xiaowei Bao Signed-off-by: Priyanka Jain --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7be867d5b6..8588866489 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -385,6 +385,7 @@ config CF_SPI config FSL_ESPI bool "Freescale eSPI driver" + imply SPI_FLASH_BAR help Enable the Freescale eSPI driver. This driver can be used to access the SPI interface and SPI NOR flash on platforms embedding From 5536c3c9d0d10c1a4e440e71eac389df3a3dbfa7 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Thu, 7 Nov 2019 16:11:32 +0000 Subject: [PATCH 16/17] freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict with UEFI secure boot. Signed-off-by: Udit Agarwal Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++-- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++-- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- board/freescale/common/Kconfig | 2 +- board/freescale/common/Makefile | 2 +- board/freescale/ls1043ardb/ls1043ardb.c | 2 +- board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +- board/freescale/ls1046aqds/ls1046aqds.c | 2 +- board/freescale/ls1046ardb/ls1046ardb.c | 2 +- configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 +- include/configs/ls1021atwr.h | 4 ++-- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 8 ++++---- include/configs/ls1046a_common.h | 4 ++-- include/configs/ls1088a_common.h | 4 ++-- include/configs/ls1088aqds.h | 6 +++--- include/configs/ls2080aqds.h | 4 ++-- 46 files changed, 57 insertions(+), 57 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 94fa68250d..b9511da3f3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -50,8 +50,8 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 046dcf539e..f1578b10bc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -376,8 +376,8 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of fan speed. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 8eeeef199b..3f6a5f6a42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -34,7 +34,7 @@ u32 spl_boot_device(void) void spl_board_init(void) { -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 8b89c10aba..1b1fd69cb2 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -1,5 +1,5 @@ config CHAIN_OF_TRUST - depends on !FIT_SIGNATURE && SECURE_BOOT + depends on !FIT_SIGNATURE && NXP_ESBC imply CMD_BLOB imply CMD_HASH if ARM select FSL_CAAM diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index a9d61a8bcf..b0e109f0b8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -75,7 +75,7 @@ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o -ifdef CONFIG_SECURE_BOOT +ifdef CONFIG_NXP_ESBC obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index fbd9a2691b..9bc78d6543 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -196,7 +196,7 @@ int board_init(void) init_final_memctl_regs(); #endif -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. * SMMU must be reset in bypass mode. diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index 41412a76b6..ac2f8ee436 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -126,7 +126,7 @@ int checkboard(void) int board_init(void) { -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index b71c1746bb..6a51dcd649 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -407,7 +407,7 @@ int board_init(void) ppa_init(); #endif -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 0a73fe859d..cc6bd883c3 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -69,7 +69,7 @@ int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 3b1568f207..58b5d75e48 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 CONFIG_AHCI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 640a462dfb..7c0a4a7533 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index f011aa02f5..fbdeef325c 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 533e251341..c0f82990c5 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index f3a2a13e0b..a98f02c89c 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 43b3f6d255..8dcd414c15 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 8871c61b87..0770836208 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 8277d6a114..906f0b6e3c 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 3170d81aaf..267fc0dde2 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index c1e88b5465..e3d547cbd7 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 472786ab26..9883d1683d 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 57791a748e..0d9d2dd490 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index c45fc68ac3..65c8435c57 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index bdfa13a0a7..1626004a46 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 5c8257de4e..187d493336 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index e863c97307..f4a95164b1 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 CONFIG_AHCI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 2b4f72f54c..8a7b34b4c2 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index dd784459b3..77d99f52ff 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index fcc3632d9a..37ebaad0b5 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 9423d7db22..fe2a073872 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index bb90ed7549..9c79daff7d 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088AQDS=y CONFIG_SYS_TEXT_BASE=0x20100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 265303c356..df560b0929 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 079ef9d8bc..d243e77626 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y CONFIG_SYS_TEXT_BASE=0x80400000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 45df1347fa..203c7959de 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index c0fde247fc..0ef829bf7e 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080AQDS=y CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=3 CONFIG_AHCI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 5f307f6caf..02173a7c81 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=3 CONFIG_AHCI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index d4b5d87e66..091fe61c6d 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS2080ARDB=y CONFIG_SYS_TEXT_BASE=0x20100000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=3 diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 0f84055993..b0e37bf378 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS2080ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_QSPI_AHB_INIT=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 3d4506bbff..ad5f30a33d 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LX2160AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index ede4e0f75f..ab6dccede9 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LX2160ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_EMC2305=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 31abee81ed..1363d3084d 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -66,13 +66,13 @@ board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg #endif -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC /* * HDR would be appended at end of image and copied to DDR along * with U-Boot image. */ #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 40fcd22582..39f9318007 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -192,7 +192,7 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #include #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 70447a2183..e237012626 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -74,7 +74,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along @@ -85,7 +85,7 @@ #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else #define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #endif /* NAND SPL */ @@ -100,9 +100,9 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_U_BOOT_HDR_SIZE /* diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 59c43f1ae1..cc8f4c0210 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -73,7 +73,7 @@ CONFIG_SPL_BSS_MAX_SIZE) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along @@ -84,7 +84,7 @@ #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else #define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #endif #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 6f04dbaccd..73c56296ff 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -235,7 +235,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along @@ -246,7 +246,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else #define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 85e20617e6..c9c517f93e 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -407,7 +407,7 @@ unsigned long get_board_ddr_clk(void); QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) /* Initial environment variables */ -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -426,7 +426,7 @@ unsigned long get_board_ddr_clk(void); "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ "mcmemsize=0x70000000 \0" -#else /* if !(CONFIG_SECURE_BOOT) */ +#else /* if !(CONFIG_NXP_ESBC) */ #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ @@ -522,7 +522,7 @@ unsigned long get_board_ddr_clk(void); "mcmemsize=0x70000000 \0" #endif #endif /* CONFIG_TFABOOT */ -#endif /* CONFIG_SECURE_BOOT */ +#endif /* CONFIG_NXP_ESBC */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index e2a897557d..08696fa9a3 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -352,7 +352,7 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -442,7 +442,7 @@ unsigned long get_board_ddr_clk(void); "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" #endif /* CONFIG_TFABOOT */ -#endif /* CONFIG_SECURE_BOOT */ +#endif /* CONFIG_NXP_ESBC */ #ifdef CONFIG_TFABOOT #define SD_BOOTCOMMAND \ From bef18454044e62800ece687b8d50ddd853117660 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Thu, 7 Nov 2019 16:11:39 +0000 Subject: [PATCH 17/17] freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid conflicts with UEFI secure boot. Signed-off-by: Udit Agarwal Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 ++-- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/start.S | 10 +++++----- arch/powerpc/cpu/mpc8xxx/law.c | 4 ++-- arch/powerpc/include/asm/fsl_secure_boot.h | 4 ++-- board/freescale/common/p_corenet/tlb.c | 2 +- board/freescale/t104xrdb/tlb.c | 4 ++-- configs/B4860QDS_SECURE_BOOT_defconfig | 2 +- configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 2 +- configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 2 +- configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 2 +- configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 2 +- configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 2 +- configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 2 +- configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 2 +- configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 2 +- configs/C29XPCIE_NOR_SECBOOT_defconfig | 2 +- configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 2 +- configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 2 +- configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 2 +- configs/P2041RDB_SECURE_BOOT_defconfig | 2 +- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/P3041DS_SECURE_BOOT_defconfig | 2 +- configs/P4080DS_SECURE_BOOT_defconfig | 2 +- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/P5020DS_SECURE_BOOT_defconfig | 2 +- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 2 +- configs/P5040DS_SECURE_BOOT_defconfig | 2 +- configs/T1023RDB_SECURE_BOOT_defconfig | 2 +- configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 2 +- configs/T1024QDS_SECURE_BOOT_defconfig | 2 +- configs/T1024RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1040QDS_SECURE_BOOT_defconfig | 2 +- configs/T1040RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 2 +- configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig | 2 +- configs/T1042RDB_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080RDB_SECURE_BOOT_defconfig | 2 +- configs/T4160QDS_SECURE_BOOT_defconfig | 2 +- configs/T4240QDS_SECURE_BOOT_defconfig | 2 +- doc/README.mpc85xx | 8 ++++---- include/configs/P1010RDB.h | 4 ++-- include/configs/T104xRDB.h | 6 +++--- include/configs/corenet_ds.h | 2 +- 56 files changed, 73 insertions(+), 73 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c038a6ddb0..8cc82f80b4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1208,8 +1208,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index cac9280790..c2b2ef2041 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,7 +38,7 @@ #ifdef CONFIG_FSL_CAAM #include #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) #include #include #endif @@ -440,7 +440,7 @@ ulong cpu_init_f(void) #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif -#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_ARCH_MPC8548 @@ -460,7 +460,7 @@ ulong cpu_init_f(void) disable_tlb(14); disable_tlb(15); -#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) @@ -963,7 +963,7 @@ int cpu_init_r(void) fman_enet_init(); #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) if (pamu_init() < 0) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dbc705388c..38e907f5ad 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -33,7 +33,7 @@ #endif #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ - !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define NOR_BOOT #endif @@ -123,7 +123,7 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \ !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later @@ -467,7 +467,7 @@ nexti: mflr r1 /* R1 = our PC */ blt 1b #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ - !defined(CONFIG_SECURE_BOOT) + !defined(CONFIG_NXP_ESBC) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -1065,7 +1065,7 @@ create_init_ram_area: 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC) /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code */ @@ -1080,7 +1080,7 @@ create_init_ram_area: * and for targets with CONFIG_SPL like T1, T2, T4, only for * u-boot-spl i.e. CONFIG_SPL_BUILD */ -#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \ +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE * to L3 Address configured by PBL for ISBC code diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 30f35e25e3..ca9e6aa8eb 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -259,7 +259,7 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \ !defined(CONFIG_E500MC) /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms, * which is not disabled before transferring the control to uboot. @@ -268,7 +268,7 @@ void init_laws(void) disable_law(0); #endif -#if !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_NXP_ESBC) /* * if any non DDR LAWs has been created earlier, remove them before * LAW table is parsed. diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 64c10074a8..035bf12467 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -7,7 +7,7 @@ #define __FSL_SECURE_BOOT_H #include -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #elif defined(CONFIG_TARGET_BSC9132QDS) @@ -74,7 +74,7 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif -#endif /* #ifdef CONFIG_SECURE_BOOT */ +#endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_SPL_BUILD diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 3d9459b133..c0ab1a5fd1 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -43,7 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) -#if !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 6511c04f31..9dcba7933f 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ - !defined(CONFIG_SECURE_BOOT) + !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), -#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) +#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot * the physical address of the SRAM is at 0xbffc0000, diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index 3eb310716c..80735e92b3 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index af1bc88b3a..adcc983c13 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index abc0886de3..5f4c1c2483 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index 81c3b3b73e..cade39d7e2 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index dca12608aa..1ea17b58c3 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 1e5c7627dc..f264ca8f06 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index 1203bdb46d..1ab09ec9c6 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index a0e9cd8d1f..edc640e5ca 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index f086438cd2..8411bddcb9 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index a256315c68..50ba06f6a6 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index 8629f8aa42..f887ec05e7 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index 51b648806d..17fa25f37a 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index b14e7deaf6..99e8b40580 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index b24f704aad..10f17ed6c6 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index 036f8e8a44..96eb27cdb5 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 349fc95ee1..7b58ee80d2 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index 0fa105ce70..37f066a1e9 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index dcc7d11d51..f304be67a9 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index 6ed4467323..4c7f464609 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index 6f43d694ea..aef1f3fb3b 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index 8e76629ad5..844e4a088d 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index cc2a04f710..bcfb589095 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index 78aef8395a..af9bee18cb 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index 91514e1641..cf254d5a10 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig index d83206342e..dc3c69b2de 100644 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index 483e393246..2250e49a25 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index e6b1207d0e..9f4cb9d890 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig index 85f04ac323..ad3bd81d1d 100644 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index 85fa7bdfbf..01131a5c5b 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig index c085e68efb..9a92c0000e 100644 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index 22b4d4ebda..817b6dcd17 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 886aba79df..1deffd8aee 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1023RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index 423d64265c..15c3bf9167 100644 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index 9d6bc98611..c60ab389c1 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index cb751dfc71..a67d50d587 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index 7391eff2a3..e59f8d736e 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040D4RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index 9cd30e5704..e411274a9d 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 5f482c3f60..376d52d2cb 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1040RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index d52521c96c..55541be975 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig index 721641270b..e11757d3f0 100644 --- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0x30001000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index a255e085b9..fc9144a03d 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index dea8479253..12b9e403a5 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 120bfccade..90dd565397 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index fafcdd52cc..81bb197681 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4160QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index 55a7f19dd5..2c6a7ff16f 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -1,6 +1,6 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_SECURE_BOOT=y +CONFIG_NXP_ESBC=y CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y # CONFIG_SYS_MALLOC_F is not set diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 93ed641df3..8464e7f4d8 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -28,11 +28,11 @@ Major Config Switches during various boot Modes NOR boot !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) NOR boot Secure - !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC) RAMBOOT(SD, SPI & NAND boot) defined(CONFIG_SYS_RAMBOOT) RAMBOOT Secure (SD, SPI & NAND) - defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC) NAND SPL BOOT defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) @@ -93,7 +93,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 1) TLB entry to overcome e500 v1/v2 debug restriction Location : Label "_start_e500" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_NXP_ESBC) EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else @@ -104,7 +104,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 2) TLB entry for working in AS1 Location : Label "create_init_ram_area" TLB Entry : 15 -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_NXP_ESBC) EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 1152bca03b..344e19d2c5 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -29,7 +29,7 @@ #endif #ifdef CONFIG_SPIFLASH -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else @@ -50,7 +50,7 @@ #endif #ifdef CONFIG_NAND -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 53ee1484d0..7cc3db943e 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -13,7 +13,7 @@ #ifdef CONFIG_RAMBOOT_PBL -#ifndef CONFIG_SECURE_BOOT +#ifndef CONFIG_NXP_ESBC #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg #else #define CONFIG_SYS_FSL_PBL_PBI \ @@ -32,7 +32,7 @@ #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_NAND -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along @@ -163,7 +163,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_NAND #define CONFIG_BOOTSCRIPT_COPY_RAM #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 60e09c1939..df602f6964 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -12,7 +12,7 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #ifdef CONFIG_NAND