mips: ath79: Fix ar71xx_regs.h indent

The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
2016-05-06 20:10:34 +02:00 · 2016-05-06 20:10:34 +02:00 · 0a6767efab
commit 0a6767efab
parent 0a0a958b68
1 changed files with 969 additions and 934 deletions
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@ -32,19 +32,26 @@
 #define AR71XX_SPI_BASE					0x1f000000
 #define AR71XX_SPI_SIZE					0x01000000

-#define AR71XX_DDR_CTRL_BASE            (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00000000)
 #define AR71XX_DDR_CTRL_SIZE				0x100
-#define AR71XX_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE				0x100
-#define AR71XX_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
 #define AR71XX_USB_CTRL_SIZE				0x100
-#define AR71XX_GPIO_BASE                (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_BASE \
+	(AR71XX_APB_BASE + 0x00040000)
 #define AR71XX_GPIO_SIZE				0x100
-#define AR71XX_PLL_BASE                 (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_BASE \
+	(AR71XX_APB_BASE + 0x00050000)
 #define AR71XX_PLL_SIZE					0x100
-#define AR71XX_RESET_BASE               (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_BASE \
+	(AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE				0x100
-#define AR71XX_MII_BASE                 (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define AR71XX_MII_SIZE					0x100

 #define AR71XX_PCI_MEM_BASE				0x10000000
@ -63,7 +70,8 @@
 	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
 #define AR71XX_PCI_CFG_SIZE				0x100

-#define AR7240_USB_CTRL_BASE            (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x00030000)
 #define AR7240_USB_CTRL_SIZE				0x100
 #define AR7240_OHCI_BASE				0x1b000000
 #define AR7240_OHCI_SIZE				0x1000
@ -73,9 +81,11 @@

 #define AR724X_PCI_CFG_BASE				0x14000000
 #define AR724X_PCI_CFG_SIZE				0x1000
-#define AR724X_PCI_CRP_BASE             (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_BASE \
+	(AR71XX_APB_BASE + 0x000c0000)
 #define AR724X_PCI_CRP_SIZE				0x1000
-#define AR724X_PCI_CTRL_BASE            (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_BASE \
+	(AR71XX_APB_BASE + 0x000f0000)
 #define AR724X_PCI_CTRL_SIZE				0x100

 #define AR724X_EHCI_BASE				0x1b000000
@ -83,47 +93,62 @@

 #define AR913X_EHCI_BASE				0x1b000000
 #define AR913X_EHCI_SIZE				0x1000
-#define AR913X_WMAC_BASE                (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x000C0000)
 #define AR913X_WMAC_SIZE				0x30000

-#define AR933X_UART_BASE                (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_BASE \
+	(AR71XX_APB_BASE + 0x00020000)
 #define AR933X_UART_SIZE				0x14
-#define AR933X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define AR933X_GMAC_SIZE				0x04
-#define AR933X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
 #define AR933X_WMAC_SIZE				0x20000
-#define AR933X_RTC_BASE                 (AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
 #define AR933X_RTC_SIZE					0x1000
 #define AR933X_EHCI_BASE				0x1b000000
 #define AR933X_EHCI_SIZE				0x1000
-#define AR933X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
 #define AR933X_SRIF_SIZE				0x1000

-#define AR934X_GMAC_BASE                (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define AR934X_GMAC_SIZE				0x14
-#define AR934X_WMAC_BASE                (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
 #define AR934X_WMAC_SIZE				0x20000
 #define AR934X_EHCI_BASE				0x1b000000
 #define AR934X_EHCI_SIZE				0x200
 #define AR934X_NFC_BASE					0x1b000200
 #define AR934X_NFC_SIZE					0xb8
-#define AR934X_SRIF_BASE                (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
 #define AR934X_SRIF_SIZE				0x1000

-#define QCA953X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define QCA953X_GMAC_SIZE				0x14
-#define QCA953X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
 #define QCA953X_WMAC_SIZE				0x20000
-#define QCA953X_RTC_BASE                (AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_BASE \
+	(AR71XX_APB_BASE + 0x00107000)
 #define QCA953X_RTC_SIZE				0x1000
 #define QCA953X_EHCI_BASE				0x1b000000
 #define QCA953X_EHCI_SIZE				0x200
-#define QCA953X_SRIF_BASE               (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_BASE \
+	(AR71XX_APB_BASE + 0x00116000)
 #define QCA953X_SRIF_SIZE				0x1000

 #define QCA953X_PCI_CFG_BASE0				0x14000000
-#define QCA953X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
-#define QCA953X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
 #define QCA953X_PCI_MEM_BASE0				0x10000000
 #define QCA953X_PCI_MEM_SIZE				0x02000000

@ -133,16 +158,22 @@
 #define QCA955X_PCI_CFG_BASE0				0x14000000
 #define QCA955X_PCI_CFG_BASE1				0x16000000
 #define QCA955X_PCI_CFG_SIZE				0x1000
-#define QCA955X_PCI_CRP_BASE0           (AR71XX_APB_BASE + 0x000c0000)
-#define QCA955X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_BASE0 \
+	(AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
 #define QCA955X_PCI_CRP_SIZE				0x1000
-#define QCA955X_PCI_CTRL_BASE0          (AR71XX_APB_BASE + 0x000f0000)
-#define QCA955X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_BASE0 \
+	(AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
 #define QCA955X_PCI_CTRL_SIZE				0x100

-#define QCA955X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define QCA955X_GMAC_SIZE				0x40
-#define QCA955X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
 #define QCA955X_WMAC_SIZE				0x20000
 #define QCA955X_EHCI0_BASE				0x1b000000
 #define QCA955X_EHCI1_BASE				0x1b400000
@ -154,17 +185,21 @@
 #define QCA956X_PCI_MEM_SIZE				0x02000000
 #define QCA956X_PCI_CFG_BASE1				0x16000000
 #define QCA956X_PCI_CFG_SIZE				0x1000
-#define QCA956X_PCI_CRP_BASE1           (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_BASE1 \
+	(AR71XX_APB_BASE + 0x00250000)
 #define QCA956X_PCI_CRP_SIZE				0x1000
-#define QCA956X_PCI_CTRL_BASE1          (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_BASE1 \
+	(AR71XX_APB_BASE + 0x00280000)
 #define QCA956X_PCI_CTRL_SIZE				0x100

-#define QCA956X_WMAC_BASE               (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_BASE \
+	(AR71XX_APB_BASE + 0x00100000)
 #define QCA956X_WMAC_SIZE				0x20000
 #define QCA956X_EHCI0_BASE				0x1b000000
 #define QCA956X_EHCI1_BASE				0x1b400000
 #define QCA956X_EHCI_SIZE				0x200
-#define QCA956X_GMAC_BASE               (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_BASE \
+	(AR71XX_APB_BASE + 0x00070000)
 #define QCA956X_GMAC_SIZE				0x64

 /*