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mpc85xx: pcie: Implement workaround for Erratum A007815

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The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers.  This should be done
immediately after resetting the PCI Express controller.

Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Tony O'Brien
2016-12-02 09:22:34 +13:00
committed by York Sun
parent 06ad970b53
commit 09bfd962bd
4 changed files with 19 additions and 1 deletions
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7
drivers/pci/fsl_pci_init.c
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@@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
/* The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers.
*/
clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
#endif
/* Use generic setup_device to initialize standard pci regs,
* but do not allocate any windows since any BAR found (such
* as PCSRBAR) is not in this cpu's memory space.